drm/nouveau/ppwr: enable ppwr on gm107

For some reason, it is now required to wait a 20 µs after the 0x200 reset of
the engine.

Signed-off-by: Martin Peres <martin.peres@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

diff --git a/drivers/gpu/drm/nouveau/core/engine/device/gm100.c b/drivers/gpu/drm/nouveau/core/engine/device/gm100.c
index 136dd9840250001351f42679ce35075fd081417d..9e9f5670faa27419f2aedc38d2ce4fdbd96ba865 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/device/gm100.c
+++ b/drivers/gpu/drm/nouveau/core/engine/device/gm100.c
@@ -75,8 +75,9 @@ gm100_identify(struct nouveau_device *device)
                device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
                device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
                device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
-#if 0
                device->oclass[NVDEV_SUBDEV_PWR    ] =  nv108_pwr_oclass;
+
+#if 0
                device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
 #endif
                device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nvd0_dmaeng_oclass;

diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/base.c b/drivers/gpu/drm/nouveau/core/subdev/pwr/base.c
index 69f1f34f6931d56f53cad1c16faf4d5caef7a935..477c9a214264fd139784bcf52fb2abe474e1f6d0 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/base.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/base.c
@@ -204,6 +204,9 @@ _nouveau_pwr_init(struct nouveau_object *object)
        nv_mask(ppwr, 0x000200, 0x00002000, 0x00000000);
        nv_mask(ppwr, 0x000200, 0x00002000, 0x00002000);
 
+       /* At least one GM107 needs this delay after reset */
+       udelay(20);
+
        /* upload data segment */
        nv_wr32(ppwr, 0x10a1c0, 0x01000000);
        for (i = 0; i < impl->data.size / 4; i++)