drm/fsl-dcu: use bus_flags for pixel clock polarity

The drivers current default configuration drives the pixel data
on rising edge of the pixel clock. However, most display sample
data on rising edge... This leads to color shift artefacts visible
especially at edges.

This patch changes the relevant defines to be useful and actually
set the bits, and changes pixel clock polarity to drive the pixel
data on falling edge by default. The patch also adds an explicit
pixel clock polarity flag to the display introduced with the driver
(NEC WQVGA "nec,nl4827hc19-05b") using the new bus_flags field to
retain the initial behavior.

Signed-off-by: Stefan Agner <stefan@agner.ch>

diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
index 365809edf29a973ae580452eb9e6f406dbd68fca..89c0084c28140091c129a72304ef129186c91a4b 100644 (file)
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
@@ -66,6 +66,7 @@ static void fsl_dcu_drm_crtc_mode_set_nofb(struct drm_crtc *crtc)
 {
        struct drm_device *dev = crtc->dev;
        struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
+       struct drm_connector *con = &fsl_dev->connector.base;
        struct drm_display_mode *mode = &crtc->state->mode;
        unsigned int hbp, hfp, hsw, vbp, vfp, vsw, index, pol = 0;
 
@@ -80,6 +81,10 @@ static void fsl_dcu_drm_crtc_mode_set_nofb(struct drm_crtc *crtc)
        vfp = mode->vsync_start - mode->vdisplay;
        vsw = mode->vsync_end - mode->vsync_start;
 
+       /* INV_PXCK as default (most display sample data on rising edge) */
+       if (!(con->display_info.bus_flags & DRM_BUS_FLAG_PIXDATA_POSEDGE))
+               pol |= DCU_SYN_POL_INV_PXCK;
+
        if (mode->flags & DRM_MODE_FLAG_NHSYNC)
                pol |= DCU_SYN_POL_INV_HS_LOW;
 

diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h
index 5bb7c261fe9594c6d29e53c42ea065344f19eb44..c275f900ff231a564256bc84c2b1252b90dde6f1 100644 (file)
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h
+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h
@@ -47,8 +47,8 @@
 #define DCU_VSYN_PARA_FP(x)            (x)
 
 #define DCU_SYN_POL                    0x0024
-#define DCU_SYN_POL_INV_PXCK_FALL      (0 << 6)
-#define DCU_SYN_POL_NEG_REMAIN         (0 << 5)
+#define DCU_SYN_POL_INV_PXCK           BIT(6)
+#define DCU_SYN_POL_NEG                        BIT(5)
 #define DCU_SYN_POL_INV_VS_LOW         BIT(1)
 #define DCU_SYN_POL_INV_HS_LOW         BIT(0)
 

diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c
index 77ae07f28b7b9dff0cde8113c9b6b35e1f4f8430..b19c88f188b08d6d9b5a80089587d6767b00c96f 100644 (file)
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -1053,7 +1053,8 @@ static const struct panel_desc nec_nl4827hc19_05b = {
                .width = 95,
                .height = 54,
        },
-       .bus_format = MEDIA_BUS_FMT_RGB888_1X24
+       .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
+       .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE,
 };
 
 static const struct display_timing okaya_rs800480t_7x0gp_timing = {