]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
mfd: dbx500-prcmu: Drop DSI pll clock functions
authorLinus Walleij <linus.walleij@linaro.org>
Sat, 28 Dec 2019 22:26:15 +0000 (23:26 +0100)
committerLee Jones <lee.jones@linaro.org>
Fri, 24 Jan 2020 07:33:58 +0000 (07:33 +0000)
The DSI PLLs are handled by the generic clock framework
since ages, this code is completely unused and misleading.
Delete it.

Cc: Stephan Gerhold <stephan@gerhold.net>
Cc: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
drivers/mfd/db8500-prcmu.c
include/linux/mfd/db8500-prcmu.h
include/linux/mfd/dbx500-prcmu.h

index 5f0cfeec8b6a919e6799a9080d79e7d3f4542983..0452b43b04232266f3a5d1e0f09b728ad24e0d94 100644 (file)
@@ -542,72 +542,6 @@ static struct dsiescclk dsiescclk[3] = {
        }
 };
 
-
-/*
-* Used by MCDE to setup all necessary PRCMU registers
-*/
-#define PRCMU_RESET_DSIPLL             0x00004000
-#define PRCMU_UNCLAMP_DSIPLL           0x00400800
-
-#define PRCMU_CLK_PLL_DIV_SHIFT                0
-#define PRCMU_CLK_PLL_SW_SHIFT         5
-#define PRCMU_CLK_38                   (1 << 9)
-#define PRCMU_CLK_38_SRC               (1 << 10)
-#define PRCMU_CLK_38_DIV               (1 << 11)
-
-/* D=101, N=1, R=4, SELDIV2=0 */
-#define PRCMU_PLLDSI_FREQ_SETTING      0x00040165
-
-#define PRCMU_ENABLE_PLLDSI            0x00000001
-#define PRCMU_DISABLE_PLLDSI           0x00000000
-#define PRCMU_RELEASE_RESET_DSS                0x0000400C
-#define PRCMU_DSI_PLLOUT_SEL_SETTING   0x00000202
-/* ESC clk, div0=1, div1=1, div2=3 */
-#define PRCMU_ENABLE_ESCAPE_CLOCK_DIV  0x07030101
-#define PRCMU_DISABLE_ESCAPE_CLOCK_DIV 0x00030101
-#define PRCMU_DSI_RESET_SW             0x00000007
-
-#define PRCMU_PLLDSI_LOCKP_LOCKED      0x3
-
-int db8500_prcmu_enable_dsipll(void)
-{
-       int i;
-
-       /* Clear DSIPLL_RESETN */
-       writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_CLR);
-       /* Unclamp DSIPLL in/out */
-       writel(PRCMU_UNCLAMP_DSIPLL, PRCM_MMIP_LS_CLAMP_CLR);
-
-       /* Set DSI PLL FREQ */
-       writel(PRCMU_PLLDSI_FREQ_SETTING, PRCM_PLLDSI_FREQ);
-       writel(PRCMU_DSI_PLLOUT_SEL_SETTING, PRCM_DSI_PLLOUT_SEL);
-       /* Enable Escape clocks */
-       writel(PRCMU_ENABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV);
-
-       /* Start DSI PLL */
-       writel(PRCMU_ENABLE_PLLDSI, PRCM_PLLDSI_ENABLE);
-       /* Reset DSI PLL */
-       writel(PRCMU_DSI_RESET_SW, PRCM_DSI_SW_RESET);
-       for (i = 0; i < 10; i++) {
-               if ((readl(PRCM_PLLDSI_LOCKP) & PRCMU_PLLDSI_LOCKP_LOCKED)
-                                       == PRCMU_PLLDSI_LOCKP_LOCKED)
-                       break;
-               udelay(100);
-       }
-       /* Set DSIPLL_RESETN */
-       writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_SET);
-       return 0;
-}
-
-int db8500_prcmu_disable_dsipll(void)
-{
-       /* Disable dsi pll */
-       writel(PRCMU_DISABLE_PLLDSI, PRCM_PLLDSI_ENABLE);
-       /* Disable  escapeclock */
-       writel(PRCMU_DISABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV);
-       return 0;
-}
-
 u32 db8500_prcmu_read(unsigned int reg)
 {
        return readl(prcmu_base + reg);
index 7d0c442e0c2514353f953123695702a090191c10..4b63d3ecdcff7de324b183089804bfde2b5f9f90 100644 (file)
@@ -525,8 +525,6 @@ u8 db8500_prcmu_get_power_state_result(void);
 void db8500_prcmu_enable_wakeups(u32 wakeups);
 int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state);
 int db8500_prcmu_request_clock(u8 clock, bool enable);
-int db8500_prcmu_disable_dsipll(void);
-int db8500_prcmu_enable_dsipll(void);
 void db8500_prcmu_config_abb_event_readout(u32 abb_events);
 void db8500_prcmu_get_abb_event_buffer(void __iomem **buf);
 int db8500_prcmu_config_esram0_deep_sleep(u8 state);
@@ -681,16 +679,6 @@ static inline int db8500_prcmu_request_clock(u8 clock, bool enable)
        return 0;
 }
 
-static inline int db8500_prcmu_disable_dsipll(void)
-{
-       return 0;
-}
-
-static inline int db8500_prcmu_enable_dsipll(void)
-{
-       return 0;
-}
-
 static inline int db8500_prcmu_config_esram0_deep_sleep(u8 state)
 {
        return 0;
index 812b6c3c4ef645c6ab2f334d24d1e9d1d1ce04a6..e6ee2ec35de9b4a5cf62fc8524e75a14f06200d5 100644 (file)
@@ -321,16 +321,6 @@ static inline bool prcmu_is_ac_wake_requested(void)
        return db8500_prcmu_is_ac_wake_requested();
 }
 
-static inline int prcmu_disable_dsipll(void)
-{
-       return db8500_prcmu_disable_dsipll();
-}
-
-static inline int prcmu_enable_dsipll(void)
-{
-       return db8500_prcmu_enable_dsipll();
-}
-
 static inline int prcmu_config_esram0_deep_sleep(u8 state)
 {
        return db8500_prcmu_config_esram0_deep_sleep(state);
@@ -506,16 +496,6 @@ static inline bool prcmu_is_ac_wake_requested(void)
        return false;
 }
 
-static inline int prcmu_disable_dsipll(void)
-{
-       return 0;
-}
-
-static inline int prcmu_enable_dsipll(void)
-{
-       return 0;
-}
-
 static inline int prcmu_config_esram0_deep_sleep(u8 state)
 {
        return 0;