clk: tegra: Make sor_safe the parent of dpaux and dpaux1

It turns out that sor_safe, rather than pll_p, is the parent of the
dpaux and dpaux1 clocks.

Acked-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index aab32af77aa22263763278dcfce1a802ea9cc0a4..fe295b4102caa47bb31166fadceade5f91eced61 100644 (file)
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -2466,11 +2466,11 @@ static __init void tegra210_periph_clk_init(void __iomem *clk_base,
                                        1, 2);
        clks[TEGRA210_CLK_XUSB_SS_DIV2] = clk;
 
-       clk = tegra_clk_register_periph_fixed("dpaux", "pll_p", 0, clk_base,
+       clk = tegra_clk_register_periph_fixed("dpaux", "sor_safe", 0, clk_base,
                                              1, 17, 181);
        clks[TEGRA210_CLK_DPAUX] = clk;
 
-       clk = tegra_clk_register_periph_fixed("dpaux1", "pll_p", 0, clk_base,
+       clk = tegra_clk_register_periph_fixed("dpaux1", "sor_safe", 0, clk_base,
                                              1, 17, 207);
        clks[TEGRA210_CLK_DPAUX1] = clk;