BG2CD SoC uses r3p0 Cortex-A9 MPCore single-CPU cluster. Autoselect
pertinent errata, the SCU and the global timer, and allow use of the
local timer on uniprocessor kernels.
PL310 L2 cache controller has revision r3p2; no errata to select.
Signed-off-by: Alexander Monakov <amonakov@ispras.ru>
Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
config MACH_BERLIN_BG2CD
bool "Marvell Armada 1500-mini (BG2CD)"
+ select ARM_ERRATA_754322
+ select ARM_ERRATA_775420
+ select ARM_GLOBAL_TIMER
select CACHE_L2X0
- select HAVE_ARM_TWD if SMP
+ select HAVE_ARM_SCU
+ select HAVE_ARM_TWD
select PINCTRL_BERLIN_BG2CD
config MACH_BERLIN_BG2Q