]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
dt-bindings: ARM: Mediatek: Document bindings for MT8183
authorWeiyi Lu <weiyi.lu@mediatek.com>
Tue, 5 Mar 2019 05:05:41 +0000 (13:05 +0800)
committerStephen Boyd <sboyd@kernel.org>
Thu, 11 Apr 2019 20:15:35 +0000 (13:15 -0700)
This patch adds the binding documentation for apmixedsys, audiosys,
camsys, imgsys, infracfg, mcucfg, mfgcfg, mmsys, topckgen, vdecsys,
vencsys and ipu for Mediatek MT8183.

Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
12 files changed:
Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt
Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys.txt [new file with mode: 0644]
Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt
Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
Documentation/devicetree/bindings/arm/mediatek/mediatek,ipu.txt [new file with mode: 0644]
Documentation/devicetree/bindings/arm/mediatek/mediatek,mcucfg.txt
Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt
Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt
Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt
Documentation/devicetree/bindings/arm/mediatek/mediatek,vencsys.txt

index de4075413d9196a85663f4ab8559ab43a4adee55..9adf28d0141b5aaf1f7204315f210f4e91d6143e 100644 (file)
@@ -14,6 +14,7 @@ Required Properties:
        - "mediatek,mt7629-apmixedsys"
        - "mediatek,mt8135-apmixedsys"
        - "mediatek,mt8173-apmixedsys"
+       - "mediatek,mt8183-apmixedsys", "syscon"
 - #clock-cells: Must be 1
 
 The apmixedsys controller uses the common clk binding from
index d1606b2c3e63b82f613516992340522d30f83632..f3cef1a6d95c7452ba534d6ab4851bbe080ab2e4 100644 (file)
@@ -9,6 +9,7 @@ Required Properties:
        - "mediatek,mt2701-audsys", "syscon"
        - "mediatek,mt7622-audsys", "syscon"
        - "mediatek,mt7623-audsys", "mediatek,mt2701-audsys", "syscon"
+       - "mediatek,mt8183-audiosys", "syscon"
 - #clock-cells: Must be 1
 
 The AUDSYS controller uses the common clk binding from
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys.txt
new file mode 100644 (file)
index 0000000..d8930f6
--- /dev/null
@@ -0,0 +1,22 @@
+MediaTek CAMSYS controller
+============================
+
+The MediaTek camsys controller provides various clocks to the system.
+
+Required Properties:
+
+- compatible: Should be one of:
+       - "mediatek,mt8183-camsys", "syscon"
+- #clock-cells: Must be 1
+
+The camsys controller uses the common clk binding from
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+The available clocks are defined in dt-bindings/clock/mt*-clk.h.
+
+Example:
+
+camsys: camsys@1a000000  {
+       compatible = "mediatek,mt8183-camsys", "syscon";
+       reg = <0 0x1a000000  0 0x1000>;
+       #clock-cells = <1>;
+};
index 3f99672163e37dac2e556d3c9f02534fa0ee01cc..e3bc4a1e7a6e46b419b3aa68e989c3d104813a17 100644 (file)
@@ -11,6 +11,7 @@ Required Properties:
        - "mediatek,mt6797-imgsys", "syscon"
        - "mediatek,mt7623-imgsys", "mediatek,mt2701-imgsys", "syscon"
        - "mediatek,mt8173-imgsys", "syscon"
+       - "mediatek,mt8183-imgsys", "syscon"
 - #clock-cells: Must be 1
 
 The imgsys controller uses the common clk binding from
index 417bd83d13789ff045b2f4951f6b09450b8f3178..0b324d2167249dd8df5866f6d85305bd034e3df9 100644 (file)
@@ -15,6 +15,7 @@ Required Properties:
        - "mediatek,mt7629-infracfg", "syscon"
        - "mediatek,mt8135-infracfg", "syscon"
        - "mediatek,mt8173-infracfg", "syscon"
+       - "mediatek,mt8183-infracfg", "syscon"
 - #clock-cells: Must be 1
 - #reset-cells: Must be 1
 
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ipu.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ipu.txt
new file mode 100644 (file)
index 0000000..aabc8c5
--- /dev/null
@@ -0,0 +1,43 @@
+Mediatek IPU controller
+============================
+
+The Mediatek ipu controller provides various clocks to the system.
+
+Required Properties:
+
+- compatible: Should be one of:
+       - "mediatek,mt8183-ipu_conn", "syscon"
+       - "mediatek,mt8183-ipu_adl", "syscon"
+       - "mediatek,mt8183-ipu_core0", "syscon"
+       - "mediatek,mt8183-ipu_core1", "syscon"
+- #clock-cells: Must be 1
+
+The ipu controller uses the common clk binding from
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+The available clocks are defined in dt-bindings/clock/mt*-clk.h.
+
+Example:
+
+ipu_conn: syscon@19000000 {
+       compatible = "mediatek,mt8183-ipu_conn", "syscon";
+       reg = <0 0x19000000 0 0x1000>;
+       #clock-cells = <1>;
+};
+
+ipu_adl: syscon@19010000 {
+       compatible = "mediatek,mt8183-ipu_adl", "syscon";
+       reg = <0 0x19010000 0 0x1000>;
+       #clock-cells = <1>;
+};
+
+ipu_core0: syscon@19180000 {
+       compatible = "mediatek,mt8183-ipu_core0", "syscon";
+       reg = <0 0x19180000 0 0x1000>;
+       #clock-cells = <1>;
+};
+
+ipu_core1: syscon@19280000 {
+       compatible = "mediatek,mt8183-ipu_core1", "syscon";
+       reg = <0 0x19280000 0 0x1000>;
+       #clock-cells = <1>;
+};
index b8fb03f3613e39123a1b94270850c4b481b7d172..2b882b7ca72ed292cd234bc7a656260f89a72bc1 100644 (file)
@@ -7,6 +7,7 @@ Required Properties:
 
 - compatible: Should be one of:
        - "mediatek,mt2712-mcucfg", "syscon"
+       - "mediatek,mt8183-mcucfg", "syscon"
 - #clock-cells: Must be 1
 
 The mcucfg controller uses the common clk binding from
index 859e67b416d5006ae2851b80352e32493f9c4c7b..72787e7dd2274cd620e4f70bf112d2726a87a75d 100644 (file)
@@ -7,6 +7,7 @@ Required Properties:
 
 - compatible: Should be one of:
        - "mediatek,mt2712-mfgcfg", "syscon"
+       - "mediatek,mt8183-mfgcfg", "syscon"
 - #clock-cells: Must be 1
 
 The mfgcfg controller uses the common clk binding from
index 15d977afad3130e0849e3f9139ded0ccd4ddf9a7..545eab717c967459c25188f61286503be603907e 100644 (file)
@@ -11,6 +11,7 @@ Required Properties:
        - "mediatek,mt6797-mmsys", "syscon"
        - "mediatek,mt7623-mmsys", "mediatek,mt2701-mmsys", "syscon"
        - "mediatek,mt8173-mmsys", "syscon"
+       - "mediatek,mt8183-mmsys", "syscon"
 - #clock-cells: Must be 1
 
 The mmsys controller uses the common clk binding from
index d160c2b4b6fe5cec7156825fefcb86bb9ba6662e..46a1cfeb8b1d1398e9380b10d485acba4c5e49c5 100644 (file)
@@ -14,6 +14,7 @@ Required Properties:
        - "mediatek,mt7629-topckgen"
        - "mediatek,mt8135-topckgen"
        - "mediatek,mt8173-topckgen"
+       - "mediatek,mt8183-topckgen", "syscon"
 - #clock-cells: Must be 1
 
 The topckgen controller uses the common clk binding from
index 3212afc753c8d1f8e03c8d8c999c010bb98d4092..57176bb8dbb508087df62791c4eb3873b65242f2 100644 (file)
@@ -11,6 +11,7 @@ Required Properties:
        - "mediatek,mt6797-vdecsys", "syscon"
        - "mediatek,mt7623-vdecsys", "mediatek,mt2701-vdecsys", "syscon"
        - "mediatek,mt8173-vdecsys", "syscon"
+       - "mediatek,mt8183-vdecsys", "syscon"
 - #clock-cells: Must be 1
 
 The vdecsys controller uses the common clk binding from
index 851545357e94af7f3ec4a96ac882cded0d166d7e..c9faa626908769e54fe68c2f93f0c4ad8ccc5746 100644 (file)
@@ -9,6 +9,7 @@ Required Properties:
        - "mediatek,mt2712-vencsys", "syscon"
        - "mediatek,mt6797-vencsys", "syscon"
        - "mediatek,mt8173-vencsys", "syscon"
+       - "mediatek,mt8183-vencsys", "syscon"
 - #clock-cells: Must be 1
 
 The vencsys controller uses the common clk binding from