drm/i915/tgl: Add the Thunderbolt PLL divider values

The Thunderbolt PLL divider values on TGL differ from the ICL ones,
update the PLL parameter calculation function accordingly.

Bspec: 49204

v2:
- Remove unused refclk config. (José)

Cc: Jose Souza <jose.souza@intel.com>
Cc: Clinton A Taylor <clinton.a.taylor@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Mika Westerberg <mika.westerberg@intel.com>
Tested-by: Mika Westerberg <mika.westerberg@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Jose Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191002204108.32242-1-imre.deak@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index be69a2344294088d6785edd21b519ffe85995a5c..5e9e84c94a15a7df1cb9ca90b8b084a3dc85f483 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -2520,6 +2520,18 @@ static const struct skl_wrpll_params icl_tbt_pll_19_2MHz_values = {
        .pdiv = 0x4 /* 5 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0,
 };
 
+static const struct skl_wrpll_params tgl_tbt_pll_19_2MHz_values = {
+       .dco_integer = 0x54, .dco_fraction = 0x3000,
+       /* the following params are unused */
+       .pdiv = 0, .kdiv = 0, .qdiv_mode = 0, .qdiv_ratio = 0,
+};
+
+static const struct skl_wrpll_params tgl_tbt_pll_24MHz_values = {
+       .dco_integer = 0x43, .dco_fraction = 0x4000,
+       /* the following params are unused */
+       .pdiv = 0, .kdiv = 0, .qdiv_mode = 0, .qdiv_ratio = 0,
+};
+
 static bool icl_calc_dp_combo_pll(struct intel_crtc_state *crtc_state,
                                  struct skl_wrpll_params *pll_params)
 {
@@ -2547,8 +2559,34 @@ static bool icl_calc_tbt_pll(struct intel_crtc_state *crtc_state,
 {
        struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
 
-       *pll_params = dev_priv->cdclk.hw.ref == 24000 ?
-                       icl_tbt_pll_24MHz_values : icl_tbt_pll_19_2MHz_values;
+       if (INTEL_GEN(dev_priv) >= 12) {
+               switch (dev_priv->cdclk.hw.ref) {
+               default:
+                       MISSING_CASE(dev_priv->cdclk.hw.ref);
+                       /* fall-through */
+               case 19200:
+               case 38400:
+                       *pll_params = tgl_tbt_pll_19_2MHz_values;
+                       break;
+               case 24000:
+                       *pll_params = tgl_tbt_pll_24MHz_values;
+                       break;
+               }
+       } else {
+               switch (dev_priv->cdclk.hw.ref) {
+               default:
+                       MISSING_CASE(dev_priv->cdclk.hw.ref);
+                       /* fall-through */
+               case 19200:
+               case 38400:
+                       *pll_params = icl_tbt_pll_19_2MHz_values;
+                       break;
+               case 24000:
+                       *pll_params = icl_tbt_pll_24MHz_values;
+                       break;
+               }
+       }
+
        return true;
 }