]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
cxgb4: collect CIM queue configuration dump
authorRahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Thu, 26 Oct 2017 11:48:34 +0000 (17:18 +0530)
committerDavid S. Miller <davem@davemloft.net>
Fri, 27 Oct 2017 14:48:29 +0000 (23:48 +0900)
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Signed-off-by: Ganesh Goudar <ganeshgr@chelsio.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/chelsio/cxgb4/cudbg_entity.h
drivers/net/ethernet/chelsio/cxgb4/cudbg_if.h
drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c
drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.h
drivers/net/ethernet/chelsio/cxgb4/cxgb4_cudbg.c

index 50540a6379a49a78407a6c6aebdbee513d966a68..ab15c3dfa04e231939a0a3d7fd84559431bbfa0d 100644 (file)
@@ -33,6 +33,15 @@ struct cudbg_mbox_log {
        u32 lo[MBOX_LEN / 8];
 };
 
+struct cudbg_cim_qcfg {
+       u8 chip;
+       u16 base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
+       u16 size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
+       u16 thres[CIM_NUM_IBQ];
+       u32 obq_wr[2 * CIM_NUM_OBQ_T5];
+       u32 stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)];
+};
+
 struct ireg_field {
        u32 ireg_addr;
        u32 ireg_data;
index f65db1b89fdcfe7a03ead0aef2887ed8e15f5dd2..be031aba270693a2febf99377f8bb29bc6b42a08 100644 (file)
@@ -31,6 +31,7 @@ enum cudbg_dbg_entity_type {
        CUDBG_DEV_LOG = 2,
        CUDBG_CIM_LA = 3,
        CUDBG_CIM_MA_LA = 4,
+       CUDBG_CIM_QCFG = 5,
        CUDBG_CIM_IBQ_TP0 = 6,
        CUDBG_CIM_IBQ_TP1 = 7,
        CUDBG_CIM_IBQ_ULP = 8,
index 8b5a12b198448d27b1ea26e6f9a130afa4024ec0..596f2b8e41cfad4e0f38f5f51b2844f24f59d536 100644 (file)
@@ -192,6 +192,45 @@ int cudbg_collect_cim_ma_la(struct cudbg_init *pdbg_init,
        return rc;
 }
 
+int cudbg_collect_cim_qcfg(struct cudbg_init *pdbg_init,
+                          struct cudbg_buffer *dbg_buff,
+                          struct cudbg_error *cudbg_err)
+{
+       struct adapter *padap = pdbg_init->adap;
+       struct cudbg_buffer temp_buff = { 0 };
+       struct cudbg_cim_qcfg *cim_qcfg_data;
+       int rc;
+
+       rc = cudbg_get_buff(dbg_buff, sizeof(struct cudbg_cim_qcfg),
+                           &temp_buff);
+       if (rc)
+               return rc;
+
+       cim_qcfg_data = (struct cudbg_cim_qcfg *)temp_buff.data;
+       cim_qcfg_data->chip = padap->params.chip;
+       rc = t4_cim_read(padap, UP_IBQ_0_RDADDR_A,
+                        ARRAY_SIZE(cim_qcfg_data->stat), cim_qcfg_data->stat);
+       if (rc) {
+               cudbg_err->sys_err = rc;
+               cudbg_put_buff(&temp_buff, dbg_buff);
+               return rc;
+       }
+
+       rc = t4_cim_read(padap, UP_OBQ_0_REALADDR_A,
+                        ARRAY_SIZE(cim_qcfg_data->obq_wr),
+                        cim_qcfg_data->obq_wr);
+       if (rc) {
+               cudbg_err->sys_err = rc;
+               cudbg_put_buff(&temp_buff, dbg_buff);
+               return rc;
+       }
+
+       t4_read_cimq_cfg(padap, cim_qcfg_data->base, cim_qcfg_data->size,
+                        cim_qcfg_data->thres);
+       cudbg_write_and_release_buff(&temp_buff, dbg_buff);
+       return rc;
+}
+
 static int cudbg_read_cim_ibq(struct cudbg_init *pdbg_init,
                              struct cudbg_buffer *dbg_buff,
                              struct cudbg_error *cudbg_err, int qid)
index ad6eff3c33c3e7f734ce50213e5c18765b416c36..f42b7420ff09d9494755c8946ae0b7545dfb3a77 100644 (file)
@@ -30,6 +30,9 @@ int cudbg_collect_cim_la(struct cudbg_init *pdbg_init,
 int cudbg_collect_cim_ma_la(struct cudbg_init *pdbg_init,
                            struct cudbg_buffer *dbg_buff,
                            struct cudbg_error *cudbg_err);
+int cudbg_collect_cim_qcfg(struct cudbg_init *pdbg_init,
+                          struct cudbg_buffer *dbg_buff,
+                          struct cudbg_error *cudbg_err);
 int cudbg_collect_cim_ibq_tp0(struct cudbg_init *pdbg_init,
                              struct cudbg_buffer *dbg_buff,
                              struct cudbg_error *cudbg_err);
index 8bc1b1decf30ef74389f46654a2a7b5cf131ba94..611ece7b7e5ab38189eb774222d66e492145e813 100644 (file)
@@ -31,6 +31,7 @@ static const struct cxgb4_collect_entity cxgb4_collect_hw_dump[] = {
        { CUDBG_REG_DUMP, cudbg_collect_reg_dump },
        { CUDBG_CIM_LA, cudbg_collect_cim_la },
        { CUDBG_CIM_MA_LA, cudbg_collect_cim_ma_la },
+       { CUDBG_CIM_QCFG, cudbg_collect_cim_qcfg },
        { CUDBG_CIM_IBQ_TP0, cudbg_collect_cim_ibq_tp0 },
        { CUDBG_CIM_IBQ_TP1, cudbg_collect_cim_ibq_tp1 },
        { CUDBG_CIM_IBQ_ULP, cudbg_collect_cim_ibq_ulp },
@@ -92,6 +93,9 @@ static u32 cxgb4_get_entity_length(struct adapter *adap, u32 entity)
        case CUDBG_CIM_MA_LA:
                len = 2 * CIM_MALA_SIZE * 5 * sizeof(u32);
                break;
+       case CUDBG_CIM_QCFG:
+               len = sizeof(struct cudbg_cim_qcfg);
+               break;
        case CUDBG_CIM_IBQ_TP0:
        case CUDBG_CIM_IBQ_TP1:
        case CUDBG_CIM_IBQ_ULP: