drm/amd/display: Add GSL source select registers

GSL is a form of locking that can be used to synchronize pipes in a
pipe-split configurations when async flip is used. Add the registers
here.

Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
index 651b8caa4b9f9a9ba19c8a84ea801a3a5d25956a..70fd56fa56c57b048be959d810ee06988431af97 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
@@ -84,7 +84,8 @@
        SRI(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst),\
        SRI(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),\
        SRI(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),\
-       SRI(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst)
+       SRI(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),\
+       SR(GSL_SOURCE_SELECT)
 
 #define TG_COMMON_REG_LIST_DCN1_0(inst) \
        TG_COMMON_REG_LIST_DCN(inst),\
@@ -156,6 +157,7 @@ struct dcn_optc_registers {
        uint32_t OTG_CRC0_WINDOWA_Y_CONTROL;
        uint32_t OTG_CRC0_WINDOWB_X_CONTROL;
        uint32_t OTG_CRC0_WINDOWB_Y_CONTROL;
+       uint32_t GSL_SOURCE_SELECT;
 };
 
 #define TG_COMMON_MASK_SH_LIST_DCN(mask_sh)\
@@ -266,7 +268,10 @@ struct dcn_optc_registers {
        SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_START, mask_sh),\
        SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_END, mask_sh),\
        SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_START, mask_sh),\
-       SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_END, mask_sh)
+       SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_END, mask_sh),\
+       SF(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, mask_sh),\
+       SF(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, mask_sh),\
+       SF(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, mask_sh)
 
 
 #define TG_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\
@@ -413,7 +418,10 @@ struct dcn_optc_registers {
        type OTG_CRC0_WINDOWB_X_START;\
        type OTG_CRC0_WINDOWB_X_END;\
        type OTG_CRC0_WINDOWB_Y_START;\
-       type OTG_CRC0_WINDOWB_Y_END;
+       type OTG_CRC0_WINDOWB_Y_END;\
+       type GSL0_READY_SOURCE_SEL;\
+       type GSL1_READY_SOURCE_SEL;\
+       type GSL2_READY_SOURCE_SEL;
 
 
 #define TG_REG_FIELD_LIST(type) \