]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
drm/amdgpu: remove more of the ring backup code
authorAlex Deucher <alexander.deucher@amd.com>
Wed, 6 Jul 2016 16:40:16 +0000 (12:40 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 7 Jul 2016 19:06:19 +0000 (15:06 -0400)
Not used anymore.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu.h
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
drivers/gpu/drm/amd/amdgpu/cik_sdma.c
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

index ac686e514e01d86bb7153189eada8347409d4f3c..814f12cc7f0801da604d55b60c588e4f4ba731df 100644 (file)
@@ -776,8 +776,6 @@ struct amdgpu_ring {
        struct amdgpu_bo        *ring_obj;
        volatile uint32_t       *ring;
        unsigned                rptr_offs;
-       u64                     next_rptr_gpu_addr;
-       volatile u32            *next_rptr_cpu_addr;
        unsigned                wptr;
        unsigned                wptr_old;
        unsigned                ring_size;
@@ -796,7 +794,6 @@ struct amdgpu_ring {
        u32                     doorbell_index;
        bool                    use_doorbell;
        unsigned                wptr_offs;
-       unsigned                next_rptr_offs;
        unsigned                fence_offs;
        uint64_t                current_ctx;
        enum amdgpu_ring_type   type;
index 71e146180e8ef3bdbeca1d8e227c75bef4e346ec..3b885e3e9b56c006e3881bc966b3f969c8c244cb 100644 (file)
@@ -190,14 +190,6 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
                return r;
        }
 
-       r = amdgpu_wb_get(adev, &ring->next_rptr_offs);
-       if (r) {
-               dev_err(adev->dev, "(%d) ring next_rptr wb alloc failed\n", r);
-               return r;
-       }
-       ring->next_rptr_gpu_addr = adev->wb.gpu_addr + ring->next_rptr_offs * 4;
-       ring->next_rptr_cpu_addr = &adev->wb.wb[ring->next_rptr_offs];
-
        r = amdgpu_wb_get(adev, &ring->cond_exe_offs);
        if (r) {
                dev_err(adev->dev, "(%d) ring cond_exec_polling wb alloc failed\n", r);
@@ -280,7 +272,6 @@ void amdgpu_ring_fini(struct amdgpu_ring *ring)
        amdgpu_wb_free(ring->adev, ring->fence_offs);
        amdgpu_wb_free(ring->adev, ring->rptr_offs);
        amdgpu_wb_free(ring->adev, ring->wptr_offs);
-       amdgpu_wb_free(ring->adev, ring->next_rptr_offs);
 
        if (ring_obj) {
                r = amdgpu_bo_reserve(ring_obj, false);
index 9dc4e24e31e73c2f98ffe845f649f4a914e24290..46aca16a40aaa4d1abe63693da45ef524852541a 100644 (file)
@@ -224,17 +224,6 @@ static void cik_sdma_ring_emit_ib(struct amdgpu_ring *ring,
                                  unsigned vm_id, bool ctx_switch)
 {
        u32 extra_bits = vm_id & 0xf;
-       u32 next_rptr = ring->wptr + 5;
-
-       while ((next_rptr & 7) != 4)
-               next_rptr++;
-
-       next_rptr += 4;
-       amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
-       amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
-       amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
-       amdgpu_ring_write(ring, 1); /* number of DWs to follow */
-       amdgpu_ring_write(ring, next_rptr);
 
        /* IB packet must end on a 8 DW boundary */
        cik_sdma_ring_insert_nop(ring, (12 - (ring->wptr & 7)) % 8);
index 1306a3b741a57d5314d0b459e1c7d9354ff153dd..f6bd9465dbdcdd9eee4062ffae2ead68dc6070bc 100644 (file)
@@ -2056,17 +2056,6 @@ static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
                                      unsigned vm_id, bool ctx_switch)
 {
        u32 header, control = 0;
-       u32 next_rptr = ring->wptr + 5;
-
-       if (ctx_switch)
-               next_rptr += 2;
-
-       next_rptr += 4;
-       amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
-       amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
-       amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
-       amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
-       amdgpu_ring_write(ring, next_rptr);
 
        /* insert SWITCH_BUFFER packet before first IB in the ring frame */
        if (ctx_switch) {
@@ -2095,22 +2084,9 @@ static void gfx_v7_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
                                          struct amdgpu_ib *ib,
                                          unsigned vm_id, bool ctx_switch)
 {
-       u32 header, control = 0;
-       u32 next_rptr = ring->wptr + 5;
-
-       control |= INDIRECT_BUFFER_VALID;
-       next_rptr += 4;
-       amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
-       amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
-       amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
-       amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
-       amdgpu_ring_write(ring, next_rptr);
-
-       header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
+       u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vm_id << 24);
 
-       control |= ib->length_dw | (vm_id << 24);
-
-       amdgpu_ring_write(ring, header);
+       amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
        amdgpu_ring_write(ring,
 #ifdef __BIG_ENDIAN
                                          (2 << 0) |
index 892a41022d8f1c5be302b6192d96a929dbd30c6f..c30b6ac25d8984f13ba70c1f962964a280373fe7 100644 (file)
@@ -5929,17 +5929,6 @@ static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
                                      unsigned vm_id, bool ctx_switch)
 {
        u32 header, control = 0;
-       u32 next_rptr = ring->wptr + 5;
-
-       if (ctx_switch)
-               next_rptr += 2;
-
-       next_rptr += 4;
-       amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
-       amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
-       amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
-       amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
-       amdgpu_ring_write(ring, next_rptr);
 
        /* insert SWITCH_BUFFER packet before first IB in the ring frame */
        if (ctx_switch) {
@@ -5968,23 +5957,9 @@ static void gfx_v8_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
                                          struct amdgpu_ib *ib,
                                          unsigned vm_id, bool ctx_switch)
 {
-       u32 header, control = 0;
-       u32 next_rptr = ring->wptr + 5;
-
-       control |= INDIRECT_BUFFER_VALID;
+       u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vm_id << 24);
 
-       next_rptr += 4;
-       amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
-       amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
-       amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
-       amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
-       amdgpu_ring_write(ring, next_rptr);
-
-       header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
-
-       control |= ib->length_dw | (vm_id << 24);
-
-       amdgpu_ring_write(ring, header);
+       amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
        amdgpu_ring_write(ring,
 #ifdef __BIG_ENDIAN
                                          (2 << 0) |
index b556bd0a8797edce702d3c26ce78ff331ea82945..ac3730a6e49f9cfe62e803b4038d83575535e453 100644 (file)
@@ -255,19 +255,6 @@ static void sdma_v2_4_ring_emit_ib(struct amdgpu_ring *ring,
                                   unsigned vm_id, bool ctx_switch)
 {
        u32 vmid = vm_id & 0xf;
-       u32 next_rptr = ring->wptr + 5;
-
-       while ((next_rptr & 7) != 2)
-               next_rptr++;
-
-       next_rptr += 6;
-
-       amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
-                         SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
-       amdgpu_ring_write(ring, lower_32_bits(ring->next_rptr_gpu_addr) & 0xfffffffc);
-       amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr));
-       amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
-       amdgpu_ring_write(ring, next_rptr);
 
        /* IB packet must end on a 8 DW boundary */
        sdma_v2_4_ring_insert_nop(ring, (10 - (ring->wptr & 7)) % 8);
index 532ea88da66abdff73e21d86debf28867d2d75fb..f00db6f4c04cd6c283f1176364c8a0dcdbba3f74 100644 (file)
@@ -415,18 +415,6 @@ static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring,
                                   unsigned vm_id, bool ctx_switch)
 {
        u32 vmid = vm_id & 0xf;
-       u32 next_rptr = ring->wptr + 5;
-
-       while ((next_rptr & 7) != 2)
-               next_rptr++;
-       next_rptr += 6;
-
-       amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
-                         SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
-       amdgpu_ring_write(ring, lower_32_bits(ring->next_rptr_gpu_addr) & 0xfffffffc);
-       amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr));
-       amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
-       amdgpu_ring_write(ring, next_rptr);
 
        /* IB packet must end on a 8 DW boundary */
        sdma_v3_0_ring_insert_nop(ring, (10 - (ring->wptr & 7)) % 8);