drm/i915: Remove pre-production pooled-EU w/a for Broxton

WaEnablePooledEuFor2x6 only applies to preproduction models, unsupported
since commit 0102ba1fd8af ("drm/i915: Add early BXT sdv to the list of
preproduction machines").

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171114135116.30036-1-chris@chris-wilson.co.uk
Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>

diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index f3e4940fed4993d171b1ef4a7bbb352bf27fe2d5..02f8bf101ccd74617fb6a3ce94355cafedcf1801 100644 (file)
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -235,16 +235,6 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
 #define IS_SS_DISABLED(ss)     (!(sseu->subslice_mask & BIT(ss)))
                info->has_pooled_eu = hweight8(sseu->subslice_mask) == 3;
 
-               /*
-                * There is a HW issue in 2x6 fused down parts that requires
-                * Pooled EU to be enabled as a WA. The pool configuration
-                * changes depending upon which subslice is fused down. This
-                * doesn't affect if the device has all 3 subslices enabled.
-                */
-               /* WaEnablePooledEuFor2x6:bxt */
-               info->has_pooled_eu |= (hweight8(sseu->subslice_mask) == 2 &&
-                                       IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST));
-
                sseu->min_eu_in_pool = 0;
                if (info->has_pooled_eu) {
                        if (IS_SS_DISABLED(2) || IS_SS_DISABLED(0))