ARM: dts: uniphier: add CPU clocks and OPP table for Pro5 SoC

Add a CPU clock to every CPU node and a CPU OPP table to use the
generic cpufreq driver.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>

diff --git a/arch/arm/boot/dts/uniphier-pro5.dtsi b/arch/arm/boot/dts/uniphier-pro5.dtsi
index 5357ea9c14b1ed59944f137b228ba3c4996910c7..5bd6068ac14b7966dcabee14b992aeb744b7d804 100644 (file)
--- a/arch/arm/boot/dts/uniphier-pro5.dtsi
+++ b/arch/arm/boot/dts/uniphier-pro5.dtsi
@@ -56,16 +56,90 @@ cpu@0 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
                        reg = <0>;
+                       clocks = <&sys_clk 32>;
                        enable-method = "psci";
                        next-level-cache = <&l2>;
+                       operating-points-v2 = <&cpu_opp>;
                };
 
                cpu@1 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
                        reg = <1>;
+                       clocks = <&sys_clk 32>;
                        enable-method = "psci";
                        next-level-cache = <&l2>;
+                       operating-points-v2 = <&cpu_opp>;
+               };
+       };
+
+       cpu_opp: opp_table {
+               compatible = "operating-points-v2";
+               opp-shared;
+
+               opp@100000000 {
+                       opp-hz = /bits/ 64 <100000000>;
+                       clock-latency-ns = <300>;
+               };
+               opp@116667000 {
+                       opp-hz = /bits/ 64 <116667000>;
+                       clock-latency-ns = <300>;
+               };
+               opp@150000000 {
+                       opp-hz = /bits/ 64 <150000000>;
+                       clock-latency-ns = <300>;
+               };
+               opp@175000000 {
+                       opp-hz = /bits/ 64 <175000000>;
+                       clock-latency-ns = <300>;
+               };
+               opp@200000000 {
+                       opp-hz = /bits/ 64 <200000000>;
+                       clock-latency-ns = <300>;
+               };
+               opp@233334000 {
+                       opp-hz = /bits/ 64 <233334000>;
+                       clock-latency-ns = <300>;
+               };
+               opp@300000000 {
+                       opp-hz = /bits/ 64 <300000000>;
+                       clock-latency-ns = <300>;
+               };
+               opp@350000000 {
+                       opp-hz = /bits/ 64 <350000000>;
+                       clock-latency-ns = <300>;
+               };
+               opp@400000000 {
+                       opp-hz = /bits/ 64 <400000000>;
+                       clock-latency-ns = <300>;
+               };
+               opp@466667000 {
+                       opp-hz = /bits/ 64 <466667000>;
+                       clock-latency-ns = <300>;
+               };
+               opp@600000000 {
+                       opp-hz = /bits/ 64 <600000000>;
+                       clock-latency-ns = <300>;
+               };
+               opp@700000000 {
+                       opp-hz = /bits/ 64 <700000000>;
+                       clock-latency-ns = <300>;
+               };
+               opp@800000000 {
+                       opp-hz = /bits/ 64 <800000000>;
+                       clock-latency-ns = <300>;
+               };
+               opp@933334000 {
+                       opp-hz = /bits/ 64 <933334000>;
+                       clock-latency-ns = <300>;
+               };
+               opp@1200000000 {
+                       opp-hz = /bits/ 64 <1200000000>;
+                       clock-latency-ns = <300>;
+               };
+               opp@1400000000 {
+                       opp-hz = /bits/ 64 <1400000000>;
+                       clock-latency-ns = <300>;
                };
        };