]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
arm64: tegra: Enable DP support on Jetson Nano
authorThierry Reding <treding@nvidia.com>
Mon, 24 Jun 2019 13:57:07 +0000 (15:57 +0200)
committerThierry Reding <treding@nvidia.com>
Tue, 29 Oct 2019 19:30:07 +0000 (20:30 +0100)
Add the AVDD_IO_EDP_1V05 and enable the SOR and DPAUX hardware blocks
that are used to drive DisplayPort on Jetson Nano.

Signed-off-by: Thierry Reding <treding@nvidia.com>
arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts

index 9d17ec707bcefdf205cf3f4695655d515fa70be1..eab2b12f0676a5374323b54140da7652157cd3da 100644 (file)
@@ -64,6 +64,16 @@ dpaux@54040000 {
                        status = "okay";
                };
 
+               sor@54540000 {
+                       status = "okay";
+
+                       avdd-io-hdmi-dp-supply = <&avdd_io_edp_1v05>;
+                       vdd-hdmi-dp-pll-supply = <&vdd_1v8>;
+
+                       nvidia,xbar-cfg = <2 1 0 3 4>;
+                       nvidia,dpaux = <&dpaux>;
+               };
+
                sor@54580000 {
                        status = "okay";
 
@@ -76,6 +86,10 @@ sor@54580000 {
                                           GPIO_ACTIVE_LOW>;
                        nvidia,xbar-cfg = <0 1 2 3 4>;
                };
+
+               dpaux@545c0000 {
+                       status = "okay";
+               };
        };
 
        gpu@57000000 {
@@ -680,5 +694,19 @@ vdd_gpu: regulator@6 {
                        enable-gpios = <&pmic 6 GPIO_ACTIVE_HIGH>;
                        vin-supply = <&vdd_5v0_sys>;
                };
+
+               avdd_io_edp_1v05: regulator@7 {
+                       compatible = "regulator-fixed";
+                       reg = <7>;
+
+                       regulator-name = "AVDD_IO_EDP_1V05";
+                       regulator-min-microvolt = <1050000>;
+                       regulator-max-microvolt = <1050000>;
+
+                       gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
+                       enable-active-high;
+
+                       vin-supply = <&avdd_1v05_pll>;
+               };
        };
 };