drm/amd/display: Add work-around option to skip DCN20 clock updates

[Why] Auto Overclock Memory fails for some systems that don't support
p-state.

[How] Implement the workaround, and it's corresponding enable flag.

Signed-off-by: Jaehyun Chung <jaehyun.chung@amd.com>
Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
index 24775ab81216b3db529523fb84ab51c47162d596..3e8ac303bd526823c978592f3bcf8838669a3a0b 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
@@ -198,6 +198,9 @@ void dcn2_update_clocks(struct clk_mgr *clk_mgr_base,
        bool force_reset = false;
        int i;
 
+       if (dc->work_arounds.skip_clock_update)
+               return;
+
        if (clk_mgr_base->clks.dispclk_khz == 0 ||
                dc->debug.force_clock_mode & 0x1) {
                //this is from resume or boot up, if forced_clock cfg option used, we bypass program dispclk and DPPCLK, but need set them for S3.

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index e3d7710b5c54e207ce1ba1abb0ce2ed30ca1e18e..1866fa71a764901b3b2210a9f764839537bdd650 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -122,6 +122,7 @@ struct dc_bug_wa {
        bool no_connect_phy_config;
        bool dedcn20_305_wa;
        struct display_mode_lib alternate_dml;
+       bool skip_clock_update;
 };
 #endif