drm/amdgpu: Move IH clientid defs to separate file

This is preparation for sharing client ID definitions
between amdgpu and amdkfd

Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
index b8a7dba6959534628793bbbe0b654f2eb0090180..0e01f115bbe55d74620e1399e8851b5beba24c84 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
@@ -25,51 +25,12 @@
 #define __AMDGPU_IH_H__
 
 #include <linux/chash.h>
+#include "soc15_ih_clientid.h"
 
 struct amdgpu_device;
- /*
-  * vega10+ IH clients
- */
-enum amdgpu_ih_clientid
-{
-    AMDGPU_IH_CLIENTID_IH          = 0x00,
-    AMDGPU_IH_CLIENTID_ACP         = 0x01,
-    AMDGPU_IH_CLIENTID_ATHUB       = 0x02,
-    AMDGPU_IH_CLIENTID_BIF         = 0x03,
-    AMDGPU_IH_CLIENTID_DCE         = 0x04,
-    AMDGPU_IH_CLIENTID_ISP         = 0x05,
-    AMDGPU_IH_CLIENTID_PCIE0       = 0x06,
-    AMDGPU_IH_CLIENTID_RLC         = 0x07,
-    AMDGPU_IH_CLIENTID_SDMA0       = 0x08,
-    AMDGPU_IH_CLIENTID_SDMA1       = 0x09,
-    AMDGPU_IH_CLIENTID_SE0SH       = 0x0a,
-    AMDGPU_IH_CLIENTID_SE1SH       = 0x0b,
-    AMDGPU_IH_CLIENTID_SE2SH       = 0x0c,
-    AMDGPU_IH_CLIENTID_SE3SH       = 0x0d,
-    AMDGPU_IH_CLIENTID_SYSHUB      = 0x0e,
-    AMDGPU_IH_CLIENTID_THM         = 0x0f,
-    AMDGPU_IH_CLIENTID_UVD         = 0x10,
-    AMDGPU_IH_CLIENTID_VCE0        = 0x11,
-    AMDGPU_IH_CLIENTID_VMC         = 0x12,
-    AMDGPU_IH_CLIENTID_XDMA        = 0x13,
-    AMDGPU_IH_CLIENTID_GRBM_CP     = 0x14,
-    AMDGPU_IH_CLIENTID_ATS         = 0x15,
-    AMDGPU_IH_CLIENTID_ROM_SMUIO    = 0x16,
-    AMDGPU_IH_CLIENTID_DF          = 0x17,
-    AMDGPU_IH_CLIENTID_VCE1        = 0x18,
-    AMDGPU_IH_CLIENTID_PWR         = 0x19,
-    AMDGPU_IH_CLIENTID_UTCL2       = 0x1b,
-    AMDGPU_IH_CLIENTID_EA          = 0x1c,
-    AMDGPU_IH_CLIENTID_UTCL2LOG            = 0x1d,
-    AMDGPU_IH_CLIENTID_MP0         = 0x1e,
-    AMDGPU_IH_CLIENTID_MP1         = 0x1f,
-
-    AMDGPU_IH_CLIENTID_MAX,
-
-    AMDGPU_IH_CLIENTID_VCN         = AMDGPU_IH_CLIENTID_UVD
-};
 
 #define AMDGPU_IH_CLIENTID_LEGACY 0
+#define AMDGPU_IH_CLIENTID_MAX SOC15_IH_CLIENTID_MAX
 
 #define AMDGPU_PAGEFAULT_HASH_BITS 8
 struct amdgpu_retryfault_hashtable {

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index d73bbb092202c67666eb4f9130ae09d4db9f7deb..d1d2c27156b2051390d1f545b050aef49ef6a735 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1261,23 +1261,23 @@ static int gfx_v9_0_sw_init(void *handle)
        adev->gfx.mec.num_queue_per_pipe = 8;
 
        /* KIQ event */
-       r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 178, &adev->gfx.kiq.irq);
+       r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 178, &adev->gfx.kiq.irq);
        if (r)
                return r;
 
        /* EOP Event */
-       r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 181, &adev->gfx.eop_irq);
+       r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 181, &adev->gfx.eop_irq);
        if (r)
                return r;
 
        /* Privileged reg */
-       r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 184,
+       r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 184,
                              &adev->gfx.priv_reg_irq);
        if (r)
                return r;
 
        /* Privileged inst */
-       r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 185,
+       r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 185,
                              &adev->gfx.priv_inst_irq);
        if (r)
                return r;

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index ceab14f16795f43db6f08a1aa6790aef9ce8df9c..a70cbc45c4c1c47faf89c70858f5d5d38aa6a797 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -861,9 +861,9 @@ static int gmc_v9_0_sw_init(void *handle)
        }
 
        /* This interrupt is VMC page fault.*/
-       r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_VMC, 0,
+       r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, 0,
                                &adev->gmc.vm_fault);
-       r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_UTCL2, 0,
+       r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, 0,
                                &adev->gmc.vm_fault);
 
        if (r)

diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
index 8b47484e169ad1509eaaaa675b0ecc84eb642c8e..8fb933c62cf5e1c8818a84633697fa2d1844b544 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
+++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
@@ -329,11 +329,11 @@ int xgpu_ai_mailbox_add_irq_id(struct amdgpu_device *adev)
 {
        int r;
 
-       r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_BIF, 135, &adev->virt.rcv_irq);
+       r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 135, &adev->virt.rcv_irq);
        if (r)
                return r;
 
-       r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_BIF, 138, &adev->virt.ack_irq);
+       r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 138, &adev->virt.ack_irq);
        if (r) {
                amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0);
                return r;

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 215743df09578c53eb250d3ba1386122c1a3d14a..939f92b295a2481dd203b5466df1d5cecb8e7fdd 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -1172,13 +1172,13 @@ static int sdma_v4_0_sw_init(void *handle)
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
        /* SDMA trap event */
-       r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_SDMA0, 224,
+       r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0, 224,
                              &adev->sdma.trap_irq);
        if (r)
                return r;
 
        /* SDMA trap event */
-       r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_SDMA1, 224,
+       r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1, 224,
                              &adev->sdma.trap_irq);
        if (r)
                return r;
@@ -1333,7 +1333,7 @@ static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev,
 {
        DRM_DEBUG("IH: SDMA trap\n");
        switch (entry->client_id) {
-       case AMDGPU_IH_CLIENTID_SDMA0:
+       case SOC15_IH_CLIENTID_SDMA0:
                switch (entry->ring_id) {
                case 0:
                        amdgpu_fence_process(&adev->sdma.instance[0].ring);
@@ -1349,7 +1349,7 @@ static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev,
                        break;
                }
                break;
-       case AMDGPU_IH_CLIENTID_SDMA1:
+       case SOC15_IH_CLIENTID_SDMA1:
                switch (entry->ring_id) {
                case 0:
                        amdgpu_fence_process(&adev->sdma.instance[1].ring);

diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
index e54cc3ca23034826a76d8d85ac672e24ddc32437..eddc57f3b72a442f541b7592b5297780acaf861f 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
@@ -390,13 +390,13 @@ static int uvd_v7_0_sw_init(void *handle)
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
        /* UVD TRAP */
-       r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_UVD, 124, &adev->uvd.irq);
+       r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UVD, 124, &adev->uvd.irq);
        if (r)
                return r;
 
        /* UVD ENC TRAP */
        for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
-               r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_UVD, i + 119, &adev->uvd.irq);
+               r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UVD, i + 119, &adev->uvd.irq);
                if (r)
                        return r;
        }

diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
index 2329b310ccf2259f3c831f18b18e726fd6b64ddc..73fd48d6c756636e19f9dd70bedf2efa3614ebd3 100755 (executable)
--- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
@@ -420,7 +420,7 @@ static int vce_v4_0_sw_init(void *handle)
        unsigned size;
        int r, i;
 
-       r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_VCE0, 167, &adev->vce.irq);
+       r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCE0, 167, &adev->vce.irq);
        if (r)
                return r;
 

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index fdf4ac9313cf314ad84f673fa9bd42be47debf57..8c132673bc794bfdb77981fe2189293ddbb3e649 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -75,13 +75,13 @@ static int vcn_v1_0_sw_init(void *handle)
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
        /* VCN DEC TRAP */
-       r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_VCN, 124, &adev->vcn.irq);
+       r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 124, &adev->vcn.irq);
        if (r)
                return r;
 
        /* VCN ENC TRAP */
        for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
-               r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_VCN, i + 119,
+               r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, i + 119,
                                        &adev->vcn.irq);
                if (r)
                        return r;

diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
index cc8ce7e352a8b5f4f111642a5e1dfeb9f9883ecd..5ae5ed2e62d63ba6c667f9ca232501908896b9c5 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
@@ -245,8 +245,8 @@ static bool vega10_ih_prescreen_iv(struct amdgpu_device *adev)
         * some faults get cleared.
         */
        switch (dw0 & 0xff) {
-       case AMDGPU_IH_CLIENTID_VMC:
-       case AMDGPU_IH_CLIENTID_UTCL2:
+       case SOC15_IH_CLIENTID_VMC:
+       case SOC15_IH_CLIENTID_UTCL2:
                break;
        default:
                /* Not a VM fault */

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index f523b2476c1e4564a858c1e84c5f03099d45d552..9e2f673cb6e14cb3945cd602136e827952254509 100644 (file)
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1131,7 +1131,7 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev)
 
        if (adev->asic_type == CHIP_VEGA10 ||
            adev->asic_type == CHIP_RAVEN)
-               client_id = AMDGPU_IH_CLIENTID_DCE;
+               client_id = SOC15_IH_CLIENTID_DCE;
 
        int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
        int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
@@ -1231,7 +1231,7 @@ static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
        for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
                        i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
                        i++) {
-               r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_DCE, i, &adev->crtc_irq);
+               r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
 
                if (r) {
                        DRM_ERROR("Failed to add crtc irq id!\n");
@@ -1255,7 +1255,7 @@ static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
        for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
                        i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1;
                        i++) {
-               r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
+               r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
                if (r) {
                        DRM_ERROR("Failed to add page flip irq id!\n");
                        return r;
@@ -1276,7 +1276,7 @@ static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
        }
 
        /* HPD */
-       r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
+       r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
                        &adev->hpd_irq);
        if (r) {
                DRM_ERROR("Failed to add hpd irq id!\n");

diff --git a/drivers/gpu/drm/amd/include/soc15_ih_clientid.h b/drivers/gpu/drm/amd/include/soc15_ih_clientid.h
new file mode 100644 (file)
index 0000000..a12d4f2
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/soc15_ih_clientid.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __SOC15_IH_CLIENTID_H__
+#define __SOC15_IH_CLIENTID_H__
+
+ /*
+  * vega10+ IH clients
+ */
+enum soc15_ih_clientid {
+       SOC15_IH_CLIENTID_IH            = 0x00,
+       SOC15_IH_CLIENTID_ACP           = 0x01,
+       SOC15_IH_CLIENTID_ATHUB         = 0x02,
+       SOC15_IH_CLIENTID_BIF           = 0x03,
+       SOC15_IH_CLIENTID_DCE           = 0x04,
+       SOC15_IH_CLIENTID_ISP           = 0x05,
+       SOC15_IH_CLIENTID_PCIE0         = 0x06,
+       SOC15_IH_CLIENTID_RLC           = 0x07,
+       SOC15_IH_CLIENTID_SDMA0         = 0x08,
+       SOC15_IH_CLIENTID_SDMA1         = 0x09,
+       SOC15_IH_CLIENTID_SE0SH         = 0x0a,
+       SOC15_IH_CLIENTID_SE1SH         = 0x0b,
+       SOC15_IH_CLIENTID_SE2SH         = 0x0c,
+       SOC15_IH_CLIENTID_SE3SH         = 0x0d,
+       SOC15_IH_CLIENTID_SYSHUB        = 0x0e,
+       SOC15_IH_CLIENTID_THM           = 0x0f,
+       SOC15_IH_CLIENTID_UVD           = 0x10,
+       SOC15_IH_CLIENTID_VCE0          = 0x11,
+       SOC15_IH_CLIENTID_VMC           = 0x12,
+       SOC15_IH_CLIENTID_XDMA          = 0x13,
+       SOC15_IH_CLIENTID_GRBM_CP       = 0x14,
+       SOC15_IH_CLIENTID_ATS           = 0x15,
+       SOC15_IH_CLIENTID_ROM_SMUIO     = 0x16,
+       SOC15_IH_CLIENTID_DF            = 0x17,
+       SOC15_IH_CLIENTID_VCE1          = 0x18,
+       SOC15_IH_CLIENTID_PWR           = 0x19,
+       SOC15_IH_CLIENTID_UTCL2         = 0x1b,
+       SOC15_IH_CLIENTID_EA            = 0x1c,
+       SOC15_IH_CLIENTID_UTCL2LOG      = 0x1d,
+       SOC15_IH_CLIENTID_MP0           = 0x1e,
+       SOC15_IH_CLIENTID_MP1           = 0x1f,
+
+       SOC15_IH_CLIENTID_MAX,
+
+       SOC15_IH_CLIENTID_VCN           = SOC15_IH_CLIENTID_UVD
+};
+
+#endif
+
+

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index f23861f2c6855b67117e710585e639193bc532a7..2fcbb17b794dd5bad8f058423efa9c27d8fbeea7 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -4874,12 +4874,12 @@ static int vega10_register_thermal_interrupt(struct pp_hwmgr *hwmgr,
                hwmgr->thermal_controller.ucType ==
                        ATOM_VEGA10_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL) {
                PP_ASSERT_WITH_CODE(!cgs_add_irq_source(hwmgr->device,
-                               0xf, /* AMDGPU_IH_CLIENTID_THM */
+                               SOC15_IH_CLIENTID_THM,
                                0, 0, irq_src[0].set, irq_src[0].handler, hwmgr),
                                "Failed to register high thermal interrupt!",
                                return -EINVAL);
                PP_ASSERT_WITH_CODE(!cgs_add_irq_source(hwmgr->device,
-                               0xf, /* AMDGPU_IH_CLIENTID_THM */
+                               SOC15_IH_CLIENTID_THM,
                                1, 0, irq_src[1].set, irq_src[1].handler, hwmgr),
                                "Failed to register low thermal interrupt!",
                                return -EINVAL);
@@ -4887,7 +4887,7 @@ static int vega10_register_thermal_interrupt(struct pp_hwmgr *hwmgr,
 
        /* Register CTF(GPIO_19) interrupt */
        PP_ASSERT_WITH_CODE(!cgs_add_irq_source(hwmgr->device,
-                       0x16, /* AMDGPU_IH_CLIENTID_ROM_SMUIO, */
+                       SOC15_IH_CLIENTID_ROM_SMUIO,
                        83, 0, irq_src[2].set, irq_src[2].handler, hwmgr),
                        "Failed to register CTF thermal interrupt!",
                        return -EINVAL);