drm/amd/powerplay: move set_clockgating_by_smu to pp func table

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
index f79f9ea58b172073bec20086560aec8cfbec57e9..7279fb5c3abc4472a08d4495aaba105abeba40ed 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
@@ -356,6 +356,10 @@ enum amdgpu_pcie_gen {
                ((adev)->powerplay.pp_funcs->switch_power_profile(\
                        (adev)->powerplay.pp_handle, type))
 
+#define amdgpu_dpm_set_clockgating_by_smu(adev, msg_id) \
+               ((adev)->powerplay.pp_funcs->set_clockgating_by_smu(\
+                       (adev)->powerplay.pp_handle, msg_id))
+
 struct amdgpu_dpm {
        struct amdgpu_ps        *ps;
        /* number of valid power states */

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 1640dd796618d3ab02655456532e13280482c5d3..147e92b3a9596de92d4d6ea5809847fe39a62154 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -5984,7 +5984,6 @@ static int gfx_v8_0_tonga_update_gfx_clock_gating(struct amdgpu_device *adev,
 {
        uint32_t msg_id, pp_state = 0;
        uint32_t pp_support_state = 0;
-       void *pp_handle = adev->powerplay.pp_handle;
 
        if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)) {
                if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {
@@ -6002,7 +6001,8 @@ static int gfx_v8_0_tonga_update_gfx_clock_gating(struct amdgpu_device *adev,
                                PP_BLOCK_GFX_CG,
                                pp_support_state,
                                pp_state);
-               amd_set_clockgating_by_smu(pp_handle, msg_id);
+               if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
+                       amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
        }
 
        if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)) {
@@ -6023,7 +6023,8 @@ static int gfx_v8_0_tonga_update_gfx_clock_gating(struct amdgpu_device *adev,
                                PP_BLOCK_GFX_MG,
                                pp_support_state,
                                pp_state);
-               amd_set_clockgating_by_smu(pp_handle, msg_id);
+               if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
+                       amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
        }
 
        return 0;
@@ -6035,7 +6036,6 @@ static int gfx_v8_0_polaris_update_gfx_clock_gating(struct amdgpu_device *adev,
 
        uint32_t msg_id, pp_state = 0;
        uint32_t pp_support_state = 0;
-       void *pp_handle = adev->powerplay.pp_handle;
 
        if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)) {
                if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {
@@ -6053,7 +6053,8 @@ static int gfx_v8_0_polaris_update_gfx_clock_gating(struct amdgpu_device *adev,
                                PP_BLOCK_GFX_CG,
                                pp_support_state,
                                pp_state);
-               amd_set_clockgating_by_smu(pp_handle, msg_id);
+               if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
+                       amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
        }
 
        if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS)) {
@@ -6072,7 +6073,8 @@ static int gfx_v8_0_polaris_update_gfx_clock_gating(struct amdgpu_device *adev,
                                PP_BLOCK_GFX_3D,
                                pp_support_state,
                                pp_state);
-               amd_set_clockgating_by_smu(pp_handle, msg_id);
+               if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
+                       amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
        }
 
        if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)) {
@@ -6093,7 +6095,8 @@ static int gfx_v8_0_polaris_update_gfx_clock_gating(struct amdgpu_device *adev,
                                PP_BLOCK_GFX_MG,
                                pp_support_state,
                                pp_state);
-               amd_set_clockgating_by_smu(pp_handle, msg_id);
+               if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
+                       amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
        }
 
        if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
@@ -6108,7 +6111,8 @@ static int gfx_v8_0_polaris_update_gfx_clock_gating(struct amdgpu_device *adev,
                                PP_BLOCK_GFX_RLC,
                                pp_support_state,
                                pp_state);
-               amd_set_clockgating_by_smu(pp_handle, msg_id);
+               if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
+                       amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
        }
 
        if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
@@ -6122,7 +6126,8 @@ static int gfx_v8_0_polaris_update_gfx_clock_gating(struct amdgpu_device *adev,
                        PP_BLOCK_GFX_CP,
                        pp_support_state,
                        pp_state);
-               amd_set_clockgating_by_smu(pp_handle, msg_id);
+               if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
+                       amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
        }
 
        return 0;

diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 9ff69b90df363c4ee95472e2133f4f6d2059996e..f3cfef48aa996aab7760a39a8327d503951b1c5b 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -1254,7 +1254,6 @@ static int vi_common_set_clockgating_state_by_smu(void *handle,
        uint32_t msg_id, pp_state = 0;
        uint32_t pp_support_state = 0;
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-       void *pp_handle = adev->powerplay.pp_handle;
 
        if (adev->cg_flags & (AMD_CG_SUPPORT_MC_LS | AMD_CG_SUPPORT_MC_MGCG)) {
                if (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) {
@@ -1271,7 +1270,8 @@ static int vi_common_set_clockgating_state_by_smu(void *handle,
                               PP_BLOCK_SYS_MC,
                               pp_support_state,
                               pp_state);
-               amd_set_clockgating_by_smu(pp_handle, msg_id);
+               if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
+                       amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
        }
 
        if (adev->cg_flags & (AMD_CG_SUPPORT_SDMA_LS | AMD_CG_SUPPORT_SDMA_MGCG)) {
@@ -1289,7 +1289,8 @@ static int vi_common_set_clockgating_state_by_smu(void *handle,
                               PP_BLOCK_SYS_SDMA,
                               pp_support_state,
                               pp_state);
-               amd_set_clockgating_by_smu(pp_handle, msg_id);
+               if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
+                       amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
        }
 
        if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_MGCG)) {
@@ -1307,7 +1308,8 @@ static int vi_common_set_clockgating_state_by_smu(void *handle,
                               PP_BLOCK_SYS_HDP,
                               pp_support_state,
                               pp_state);
-               amd_set_clockgating_by_smu(pp_handle, msg_id);
+               if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
+                       amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
        }
 
 
@@ -1321,7 +1323,8 @@ static int vi_common_set_clockgating_state_by_smu(void *handle,
                               PP_BLOCK_SYS_BIF,
                               PP_STATE_SUPPORT_LS,
                                pp_state);
-               amd_set_clockgating_by_smu(pp_handle, msg_id);
+               if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
+                       amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
        }
        if (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG) {
                if (state == AMD_CG_STATE_UNGATE)
@@ -1333,7 +1336,8 @@ static int vi_common_set_clockgating_state_by_smu(void *handle,
                               PP_BLOCK_SYS_BIF,
                               PP_STATE_SUPPORT_CG,
                               pp_state);
-               amd_set_clockgating_by_smu(pp_handle, msg_id);
+               if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
+                       amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
        }
 
        if (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS) {
@@ -1347,7 +1351,8 @@ static int vi_common_set_clockgating_state_by_smu(void *handle,
                               PP_BLOCK_SYS_DRM,
                               PP_STATE_SUPPORT_LS,
                               pp_state);
-               amd_set_clockgating_by_smu(pp_handle, msg_id);
+               if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
+                       amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
        }
 
        if (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG) {
@@ -1361,7 +1366,8 @@ static int vi_common_set_clockgating_state_by_smu(void *handle,
                               PP_BLOCK_SYS_ROM,
                               PP_STATE_SUPPORT_CG,
                               pp_state);
-               amd_set_clockgating_by_smu(pp_handle, msg_id);
+               if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
+                       amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
        }
        return 0;
 }

diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index 6e0b35245555e92c0bd7c61380bdfbc60b8d99f3..71bb7d932c86bb57aa547549b5e588e9452086da 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -222,28 +222,6 @@ static int pp_sw_reset(void *handle)
        return 0;
 }
 
-
-int amd_set_clockgating_by_smu(void *handle, uint32_t msg_id)
-{
-       struct pp_hwmgr  *hwmgr;
-       struct pp_instance *pp_handle = (struct pp_instance *)handle;
-       int ret = 0;
-
-       ret = pp_check(pp_handle);
-
-       if (!ret)
-               return ret;
-
-       hwmgr = pp_handle->hwmgr;
-
-       if (hwmgr->hwmgr_func->update_clock_gatings == NULL) {
-               pr_info("%s was not implemented.\n", __func__);
-               return 0;
-       }
-
-       return hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
-}
-
 static int pp_set_powergating_state(void *handle,
                                    enum amd_powergating_state state)
 {
@@ -335,6 +313,27 @@ static int pp_dpm_fw_loading_complete(void *handle)
        return 0;
 }
 
+static int pp_set_clockgating_by_smu(void *handle, uint32_t msg_id)
+{
+       struct pp_hwmgr  *hwmgr;
+       struct pp_instance *pp_handle = (struct pp_instance *)handle;
+       int ret = 0;
+
+       ret = pp_check(pp_handle);
+
+       if (ret)
+               return ret;
+
+       hwmgr = pp_handle->hwmgr;
+
+       if (hwmgr->hwmgr_func->update_clock_gatings == NULL) {
+               pr_info("%s was not implemented.\n", __func__);
+               return 0;
+       }
+
+       return hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
+}
+
 static void pp_dpm_en_umd_pstate(struct pp_hwmgr  *hwmgr,
                                                enum amd_dpm_forced_level *level)
 {
@@ -1177,6 +1176,7 @@ const struct amd_pm_funcs pp_dpm_funcs = {
        .get_power_profile_state = pp_dpm_get_power_profile_state,
        .set_power_profile_state = pp_dpm_set_power_profile_state,
        .switch_power_profile = pp_dpm_switch_power_profile,
+       .set_clockgating_by_smu = pp_set_clockgating_by_smu,
 };
 
 int amd_powerplay_reset(void *handle)

diff --git a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
index e52adc873413c984c6aa72ebce90f891b33c29cb..95932cc884604b95bb706d228b502508c2194756 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
@@ -304,6 +304,5 @@ int amd_powerplay_display_clock_voltage_request(void *handle,
 int amd_powerplay_get_display_mode_validation_clocks(void *handle,
                struct amd_pp_simple_clock_info *output);
 
-int amd_set_clockgating_by_smu(void *handle, uint32_t msg_id);
 
 #endif /* _AMD_POWERPLAY_H_ */