drm/amdgpu/psp: Update waiting in psp mode1 reset.

No point in use mdelay unless running from interrupt context (which we are not)
This is busy wait which will block the CPU for the entirety of the wait time.
Also, reduce wait time to 500ms as it is done in refernce code because
1s might cause PSP FW TO issues during XGMI hive reset.

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index e5dd052d9e06a5af4ea8d76b99944f42617b3f63..2b19616cb4021ead10f34715f952845f94906fae 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
@@ -547,7 +547,7 @@ static int psp_v11_0_mode1_reset(struct psp_context *psp)
        /*send the mode 1 reset command*/
        WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST);
 
-       mdelay(1000);
+       msleep(500);
 
        offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
 

diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
index 7efb823dd3b113c621b16fe79b934a055e00a75c..7357fd56e61445f18bd16b7a2553e9eaf4d1d960 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
@@ -592,7 +592,7 @@ static int psp_v3_1_mode1_reset(struct psp_context *psp)
        /*send the mode 1 reset command*/
        WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST);
 
-       mdelay(1000);
+       msleep(500);
 
        offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);