drm/amd/display: reset drr programming on pipe reset

[why]
drr is still enabled after driver is unloaded causing black screen

[how]
disable drr during pipe reset.

Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index e720be6be36914b2f5b223533d42739d92141616..04399c541c28679397a1505adf446725bceffb4b 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -823,6 +823,9 @@ static void dcn10_reset_back_end_for_pipe(
                pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);
 
                pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);
+               if (pipe_ctx->stream_res.tg->funcs->set_drr)
+                       pipe_ctx->stream_res.tg->funcs->set_drr(
+                                       pipe_ctx->stream_res.tg, NULL);
        }
 
        for (i = 0; i < dc->res_pool->pipe_count; i++)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 38b3c89b2a599de55fbe260ecb5e832ce72f5d38..27d143418cc720254ac8af9aa2bac93fb9c92cb7 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1834,6 +1834,10 @@ static void dcn20_reset_back_end_for_pipe(
                if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass)
                        pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
                                        pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
+
+               if (pipe_ctx->stream_res.tg->funcs->set_drr)
+                       pipe_ctx->stream_res.tg->funcs->set_drr(
+                                       pipe_ctx->stream_res.tg, NULL);
        }
 
        for (i = 0; i < dc->res_pool->pipe_count; i++)