[ARM] Kirkwood: restrict the scope of the PCIe reset workaround

Commit 21f0ba90a447 "orion/kirkwood: reset PCIe unit on boot" made the
reset of the PCIe unit unconditional.  While this may fix problems on some
targets, this also causes problems on other targets.

Saeed Bishara <saeed@marvell.com> said about the original problem: "We
couln't pinpoint the root cause of this issue, actually we failed to
reproduce that issue."

So let's restrict the reset of the PCIe unit only to the target where
the original problem was observed.

Signed-off-by: Nicolas Pitre <nico@fluxnic.net>

diff --git a/arch/arm/mach-kirkwood/ts41x-setup.c b/arch/arm/mach-kirkwood/ts41x-setup.c
index 2e14afef07a2ace0708e144b98bf4ef1f2a446b1..6995199a91279c1323551d88d4f66d916aadab67 100644 (file)
--- a/arch/arm/mach-kirkwood/ts41x-setup.c
+++ b/arch/arm/mach-kirkwood/ts41x-setup.c
@@ -27,6 +27,10 @@
 #include "mpp.h"
 #include "tsx1x-common.h"
 
+/* for the PCIe reset workaround */
+#include <plat/pcie.h>
+
+
 #define QNAP_TS41X_JUMPER_JP1  45
 
 static struct i2c_board_info __initdata qnap_ts41x_i2c_rtc = {
@@ -140,8 +144,16 @@ static void __init qnap_ts41x_init(void)
 
 static int __init ts41x_pci_init(void)
 {
-       if (machine_is_ts41x())
+       if (machine_is_ts41x()) {
+               /*
+                * Without this explicit reset, the PCIe SATA controller
+                * (Marvell 88sx7042/sata_mv) is known to stop working
+                * after a few minutes.
+                */
+               orion_pcie_reset((void __iomem *)PCIE_VIRT_BASE);
+
                kirkwood_pcie_init(KW_PCIE0);
+       }
 
    return 0;
 }

diff --git a/arch/arm/plat-orion/include/plat/pcie.h b/arch/arm/plat-orion/include/plat/pcie.h
index 3ebfef72b4e700406f43131349eda135747a3304..cc99163e73fdbde0f4945a93c35cdd5830c25ac5 100644 (file)
--- a/arch/arm/plat-orion/include/plat/pcie.h
+++ b/arch/arm/plat-orion/include/plat/pcie.h
@@ -11,12 +11,15 @@
 #ifndef __PLAT_PCIE_H
 #define __PLAT_PCIE_H
 
+struct pci_bus;
+
 u32 orion_pcie_dev_id(void __iomem *base);
 u32 orion_pcie_rev(void __iomem *base);
 int orion_pcie_link_up(void __iomem *base);
 int orion_pcie_x4_mode(void __iomem *base);
 int orion_pcie_get_local_bus_nr(void __iomem *base);
 void orion_pcie_set_local_bus_nr(void __iomem *base, int nr);
+void orion_pcie_reset(void __iomem *base);
 void orion_pcie_setup(void __iomem *base,
                      struct mbus_dram_target_info *dram);
 int orion_pcie_rd_conf(void __iomem *base, struct pci_bus *bus,

diff --git a/arch/arm/plat-orion/pcie.c b/arch/arm/plat-orion/pcie.c
index 779553a1595e938ead6a4764e84ee8d87087acb9..af2d733c50b5cf9a32ec07932a1b64131d95ca46 100644 (file)
--- a/arch/arm/plat-orion/pcie.c
+++ b/arch/arm/plat-orion/pcie.c
@@ -181,11 +181,6 @@ void __init orion_pcie_setup(void __iomem *base,
        u16 cmd;
        u32 mask;
 
-       /*
-        * soft reset PCIe unit
-        */
-       orion_pcie_reset(base);
-
        /*
         * Point PCIe unit MBUS decode windows to DRAM space.
         */