drm: meson: crtc: use proper macros instead of magic constants

This patch add new macros which describe couple bits field of the
following registers:
- VD1_BLEND_SRC_CTRL
- VPP_SC_MISC

Signed-off-by: Julien Masson <jmasson@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://patchwork.freedesktop.org/patch/msgid/86wohb82fa.fsf@baylibre.com

diff --git a/drivers/gpu/drm/meson/meson_crtc.c b/drivers/gpu/drm/meson/meson_crtc.c
index 3320a74e67fa437497d2e6fa7bc010ae3b99e421..bba25325aa9c253850e6576a387264da2335a57e 100644 (file)
--- a/drivers/gpu/drm/meson/meson_crtc.c
+++ b/drivers/gpu/drm/meson/meson_crtc.c
@@ -265,11 +265,11 @@ static void meson_crtc_enable_vd1(struct meson_drm *priv)
 
 static void meson_g12a_crtc_enable_vd1(struct meson_drm *priv)
 {
-       writel_relaxed(((1 << 16) | /* post bld premult*/
-                       (1 << 8) | /* post src */
-                       (1 << 4) | /* pre bld premult*/
-                       (1 << 0)),
-                       priv->io_base + _REG(VD1_BLEND_SRC_CTRL));
+       writel_relaxed(VD_BLEND_PREBLD_SRC_VD1 |
+                      VD_BLEND_PREBLD_PREMULT_EN |
+                      VD_BLEND_POSTBLD_SRC_VD1 |
+                      VD_BLEND_POSTBLD_PREMULT_EN,
+                      priv->io_base + _REG(VD1_BLEND_SRC_CTRL));
 }
 
 void meson_crtc_irq(struct meson_drm *priv)
@@ -487,7 +487,12 @@ void meson_crtc_irq(struct meson_drm *priv)
                writel_relaxed(priv->viu.vd1_range_map_cr,
                                priv->io_base + meson_crtc->viu_offset +
                                _REG(VD1_IF0_RANGE_MAP_CR));
-               writel_relaxed(0x78404,
+               writel_relaxed(VPP_VSC_BANK_LENGTH(4) |
+                              VPP_HSC_BANK_LENGTH(4) |
+                              VPP_SC_VD_EN_ENABLE |
+                              VPP_SC_TOP_EN_ENABLE |
+                              VPP_SC_HSC_EN_ENABLE |
+                              VPP_SC_VSC_EN_ENABLE,
                                priv->io_base + _REG(VPP_SC_MISC));
                writel_relaxed(priv->viu.vpp_pic_in_height,
                                priv->io_base + _REG(VPP_PIC_IN_HEIGHT));

diff --git a/drivers/gpu/drm/meson/meson_registers.h b/drivers/gpu/drm/meson/meson_registers.h
index f8dd1be0131e2d676958cb458c17e2fa32dc4396..e5e87c2303b7ccd6402444b0fa3bb1c5673f5bd6 100644 (file)
--- a/drivers/gpu/drm/meson/meson_registers.h
+++ b/drivers/gpu/drm/meson/meson_registers.h
@@ -362,6 +362,12 @@
 #define VPP_HSC_REGION4_PHASE_SLOPE 0x1d17
 #define VPP_HSC_PHASE_CTRL 0x1d18
 #define VPP_SC_MISC 0x1d19
+#define                VPP_SC_VD_EN_ENABLE             BIT(15)
+#define                VPP_SC_TOP_EN_ENABLE            BIT(16)
+#define                VPP_SC_HSC_EN_ENABLE            BIT(17)
+#define                VPP_SC_VSC_EN_ENABLE            BIT(18)
+#define                VPP_VSC_BANK_LENGTH(length)     (length & 0x7)
+#define                VPP_HSC_BANK_LENGTH(length)     ((length & 0x7) << 8)
 #define VPP_PREBLEND_VD1_H_START_END 0x1d1a
 #define VPP_PREBLEND_VD1_V_START_END 0x1d1b
 #define VPP_POSTBLEND_VD1_H_START_END 0x1d1c
@@ -1630,6 +1636,16 @@
 #define VPP_SLEEP_CTRL 0x1dfa
 #define VD1_BLEND_SRC_CTRL 0x1dfb
 #define VD2_BLEND_SRC_CTRL 0x1dfc
+#define                VD_BLEND_PREBLD_SRC_VD1         (1 << 0)
+#define                VD_BLEND_PREBLD_SRC_VD2         (2 << 0)
+#define                VD_BLEND_PREBLD_SRC_OSD1        (3 << 0)
+#define                VD_BLEND_PREBLD_SRC_OSD2        (4 << 0)
+#define                VD_BLEND_PREBLD_PREMULT_EN      BIT(4)
+#define                VD_BLEND_POSTBLD_SRC_VD1        (1 << 8)
+#define                VD_BLEND_POSTBLD_SRC_VD2        (2 << 8)
+#define                VD_BLEND_POSTBLD_SRC_OSD1       (3 << 8)
+#define                VD_BLEND_POSTBLD_SRC_OSD2       (4 << 8)
+#define                VD_BLEND_POSTBLD_PREMULT_EN     BIT(16)
 #define OSD1_BLEND_SRC_CTRL 0x1dfd
 #define OSD2_BLEND_SRC_CTRL 0x1dfe