arm64: dts: allwinner: a64: Add L2 cache nodes

Current kernels complain when booting on an A64 Soc:
....
[    1.904297] cacheinfo: Unable to detect cache hierarchy for CPU 0
....
Not a real biggie on this flat topology, but also easy enough to fix.

Add the L2 cache node and let each CPU point to it.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 925bf38fb5366cf32cdc1fc3067fcebf9ad76e77..b73f9287c3f050dc6d1cd27b35a1f696f2fdf3db 100644 (file)
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -88,6 +88,7 @@ cpu0: cpu@0 {
                        device_type = "cpu";
                        reg = <0>;
                        enable-method = "psci";
+                       next-level-cache = <&L2>;
                };
 
                cpu1: cpu@1 {
@@ -95,6 +96,7 @@ cpu1: cpu@1 {
                        device_type = "cpu";
                        reg = <1>;
                        enable-method = "psci";
+                       next-level-cache = <&L2>;
                };
 
                cpu2: cpu@2 {
@@ -102,6 +104,7 @@ cpu2: cpu@2 {
                        device_type = "cpu";
                        reg = <2>;
                        enable-method = "psci";
+                       next-level-cache = <&L2>;
                };
 
                cpu3: cpu@3 {
@@ -109,6 +112,12 @@ cpu3: cpu@3 {
                        device_type = "cpu";
                        reg = <3>;
                        enable-method = "psci";
+                       next-level-cache = <&L2>;
+               };
+
+               L2: l2-cache {
+                       compatible = "cache";
+                       cache-level = <2>;
                };
        };