]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
e1000e: Initial Support for CannonLake
authorSasha Neftin <sasha.neftin@intel.com>
Thu, 6 Apr 2017 07:26:32 +0000 (10:26 +0300)
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>
Sun, 30 Apr 2017 12:15:08 +0000 (05:15 -0700)
i219 (6) and i219 (7) are the next LOM generations that will be
available on the nextIntel Client platform (CannonLake)
This patch provides the initial support for these devices

Signed-off-by: Sasha Neftin <sasha.neftin@intel.com>
Reviewed-by: Raanan Avargil <raanan.avargil@intel.com>
Reviewed-by: Dima Ruinskiy <dima.ruinskiy@intel.com>
Tested-by: Aaron Brown <aaron.f.brown@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
drivers/net/ethernet/intel/e1000e/e1000.h
drivers/net/ethernet/intel/e1000e/hw.h
drivers/net/ethernet/intel/e1000e/ich8lan.c
drivers/net/ethernet/intel/e1000e/netdev.c

index a29b12e80855b1f13b7f6c86af460dc2e661c5e6..f16d9826c66da9a6d8c3a35311b341a177a09686 100644 (file)
@@ -135,7 +135,8 @@ enum e1000_boards {
        board_pchlan,
        board_pch2lan,
        board_pch_lpt,
-       board_pch_spt
+       board_pch_spt,
+       board_pch_cnp
 };
 
 struct e1000_ps_page {
@@ -515,6 +516,7 @@ extern const struct e1000_info e1000_pch_info;
 extern const struct e1000_info e1000_pch2_info;
 extern const struct e1000_info e1000_pch_lpt_info;
 extern const struct e1000_info e1000_pch_spt_info;
+extern const struct e1000_info e1000_pch_cnp_info;
 extern const struct e1000_info e1000_es2_info;
 
 void e1000e_ptp_init(struct e1000_adapter *adapter);
index 4e733bf1a38e3d24953ed430946129546e3785ff..66bd5060a65b2bd9c6453583a0db67efcb6080f1 100644 (file)
@@ -96,6 +96,10 @@ struct e1000_hw;
 #define E1000_DEV_ID_PCH_SPT_I219_V4           0x15D8
 #define E1000_DEV_ID_PCH_SPT_I219_LM5          0x15E3
 #define E1000_DEV_ID_PCH_SPT_I219_V5           0x15D6
+#define E1000_DEV_ID_PCH_CNP_I219_LM6          0x15BD
+#define E1000_DEV_ID_PCH_CNP_I219_V6           0x15BE
+#define E1000_DEV_ID_PCH_CNP_I219_LM7          0x15BB
+#define E1000_DEV_ID_PCH_CNP_I219_V7           0x15BC
 
 #define E1000_REVISION_4       4
 
@@ -118,6 +122,7 @@ enum e1000_mac_type {
        e1000_pch2lan,
        e1000_pch_lpt,
        e1000_pch_spt,
+       e1000_pch_cnp,
 };
 
 enum e1000_media_type {
index 72add037f07e99f8be56e1310d57ef47de27546d..c0cd2874cba618dab52d2f93f35657cbc24878ef 100644 (file)
@@ -5915,3 +5915,23 @@ const struct e1000_info e1000_pch_spt_info = {
        .phy_ops                = &ich8_phy_ops,
        .nvm_ops                = &spt_nvm_ops,
 };
+
+const struct e1000_info e1000_pch_cnp_info = {
+       .mac                    = e1000_pch_cnp,
+       .flags                  = FLAG_IS_ICH
+                                 | FLAG_HAS_WOL
+                                 | FLAG_HAS_HW_TIMESTAMP
+                                 | FLAG_HAS_CTRLEXT_ON_LOAD
+                                 | FLAG_HAS_AMT
+                                 | FLAG_HAS_FLASH
+                                 | FLAG_HAS_JUMBO_FRAMES
+                                 | FLAG_APME_IN_WUC,
+       .flags2                 = FLAG2_HAS_PHY_STATS
+                                 | FLAG2_HAS_EEE,
+       .pba                    = 26,
+       .max_hw_frame_size      = 9022,
+       .get_variants           = e1000_get_variants_ich8lan,
+       .mac_ops                = &ich8_mac_ops,
+       .phy_ops                = &ich8_phy_ops,
+       .nvm_ops                = &spt_nvm_ops,
+};
index 667fc45ce906bb54b574e026d9cd3e7dc6345b2a..974fda2dd663db02197aea079b02716fb10b8cc3 100644 (file)
@@ -71,6 +71,7 @@ static const struct e1000_info *e1000_info_tbl[] = {
        [board_pch2lan]         = &e1000_pch2_info,
        [board_pch_lpt]         = &e1000_pch_lpt_info,
        [board_pch_spt]         = &e1000_pch_spt_info,
+       [board_pch_cnp]         = &e1000_pch_cnp_info,
 };
 
 struct e1000_reg_info {
@@ -7514,6 +7515,10 @@ static const struct pci_device_id e1000_pci_tbl[] = {
        { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V4), board_pch_spt },
        { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM5), board_pch_spt },
        { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V5), board_pch_spt },
+       { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_LM6), board_pch_cnp },
+       { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_V6), board_pch_cnp },
+       { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_LM7), board_pch_cnp },
+       { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_V7), board_pch_cnp },
 
        { 0, 0, 0, 0, 0, 0, 0 } /* terminate list */
 };