drm/amd/display: Optimize clocks on clock change

[WHY]
Presently, there is no way for clocks to be lowered, only raised.

[HOW]
Compare clock status against previous known clock status, and optimize
if different.
This requires re-ordering the layout of the dc_clocks structure, as the
current ordering allows identical clock states to appear different.

Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index cbc4501d1c4a0817a4dc4aab0c8bbfb4c62ff777..a31c514235295fa96bcf9f26c7fbf19efe675a8a 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1646,6 +1646,9 @@ enum surface_update_type dc_check_update_surfaces_for_stream(
                        updates[i].surface->update_flags.raw = 0xFFFFFFFF;
        }
 
+       if (type == UPDATE_TYPE_FAST && memcmp(&dc->current_state->bw_ctx.bw.dcn.clk, &dc->clk_mgr->clks, offsetof(struct dc_clocks, prev_p_state_change_support)) != 0)
+               dc->optimized_required = true;
+
        return type;
 }
 

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 30ef31a788f823ecd8a167eae9cd52903b0c9140..c65f34aa2523e93b9d287fb041475a1055de9032 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -252,11 +252,7 @@ enum wm_report_mode {
  */
 struct dc_clocks {
        int dispclk_khz;
-       int max_supported_dppclk_khz;
-       int max_supported_dispclk_khz;
        int dppclk_khz;
-       int bw_dppclk_khz; /*a copy of dppclk_khz*/
-       int bw_dispclk_khz;
        int dcfclk_khz;
        int socclk_khz;
        int dcfclk_deep_sleep_khz;
@@ -270,6 +266,10 @@ struct dc_clocks {
         * optimization required
         */
        bool prev_p_state_change_support;
+       int max_supported_dppclk_khz;
+       int max_supported_dispclk_khz;
+       int bw_dppclk_khz; /*a copy of dppclk_khz*/
+       int bw_dispclk_khz;
 };
 
 struct dc_bw_validation_profile {