clk: qcom: Add freq tables for a few rcgs

Add frequency tables for a few RCG clocks in msm8996

Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c
index fe03e6fbc7df590d9d354891a5aa05d686d59fd7..e22bbc27c9078acc0c3dd9fb20ca0472aac1c568 100644 (file)
--- a/drivers/clk/qcom/gcc-msm8996.c
+++ b/drivers/clk/qcom/gcc-msm8996.c
@@ -464,10 +464,18 @@ static struct clk_rcg2 sdcc1_apps_clk_src = {
        },
 };
 
+static struct freq_tbl ftbl_sdcc1_ice_core_clk_src[] = {
+       F(19200000, P_XO, 1, 0, 0),
+       F(150000000, P_GPLL0, 4, 0, 0),
+       F(300000000, P_GPLL0, 2, 0, 0),
+       { }
+};
+
 static struct clk_rcg2 sdcc1_ice_core_clk_src = {
        .cmd_rcgr = 0x13024,
        .hid_width = 5,
        .parent_map = gcc_xo_gpll0_gpll4_gpll0_early_div_map,
+       .freq_tbl = ftbl_sdcc1_ice_core_clk_src,
        .clkr.hw.init = &(struct clk_init_data){
                .name = "sdcc1_ice_core_clk_src",
                .parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div,
@@ -1230,10 +1238,18 @@ static struct clk_rcg2 ufs_axi_clk_src = {
        },
 };
 
+static const struct freq_tbl ftbl_ufs_ice_core_clk_src[] = {
+       F(19200000, P_XO, 1, 0, 0),
+       F(150000000, P_GPLL0, 4, 0, 0),
+       F(300000000, P_GPLL0, 2, 0, 0),
+       { }
+};
+
 static struct clk_rcg2 ufs_ice_core_clk_src = {
        .cmd_rcgr = 0x76014,
        .hid_width = 5,
        .parent_map = gcc_xo_gpll0_map,
+       .freq_tbl = ftbl_ufs_ice_core_clk_src,
        .clkr.hw.init = &(struct clk_init_data){
                .name = "ufs_ice_core_clk_src",
                .parent_names = gcc_xo_gpll0,
@@ -1242,10 +1258,19 @@ static struct clk_rcg2 ufs_ice_core_clk_src = {
        },
 };
 
+static const struct freq_tbl ftbl_qspi_ser_clk_src[] = {
+       F(75000000, P_GPLL0, 8, 0, 0),
+       F(150000000, P_GPLL0, 4, 0, 0),
+       F(256000000, P_GPLL4, 1.5, 0, 0),
+       F(300000000, P_GPLL0, 2, 0, 0),
+       { }
+};
+
 static struct clk_rcg2 qspi_ser_clk_src = {
        .cmd_rcgr = 0x8b00c,
        .hid_width = 5,
        .parent_map = gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div_map,
+       .freq_tbl = ftbl_qspi_ser_clk_src,
        .clkr.hw.init = &(struct clk_init_data){
                .name = "qspi_ser_clk_src",
                .parent_names = gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div,