]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
clk: renesas: rcar-gen3: Correct parent clock of SYS-DMAC
authorTakeshi Kihara <takeshi.kihara.df@renesas.com>
Fri, 28 Sep 2018 07:18:00 +0000 (16:18 +0900)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Tue, 2 Apr 2019 08:08:29 +0000 (10:08 +0200)
The clock sources of the AXI BUS clock (266.66 MHz) used for SYS-DMAC
DMA transfers are:

    Channel      R-Car H3    R-Car M3-W    R-Car M3-N
    -------------------------------------------------
    SYS-DMAC0    S0D3        S0D3          S0D3
    SYS-DMAC1    S3D1        S3D1          S3D1
    SYS-DMAC2    S3D1        S3D1          S3D1

As a result, change the parent clocks of the SYS-DMAC{1,2} module clocks
on R-Car H3, R-Car M3-W, and R-Car M3-N to S3D1.

NOTE: This information will be reflected in a future revision of the
      R-Car Gen3 Hardware Manual.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[geert: Update RZ/G2M]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
drivers/clk/renesas/r8a774a1-cpg-mssr.c
drivers/clk/renesas/r8a7795-cpg-mssr.c
drivers/clk/renesas/r8a7796-cpg-mssr.c
drivers/clk/renesas/r8a77965-cpg-mssr.c

index 676e6a1120900b17a1153c96dd7c8accb25a6734..13bf7260204f507806a4d14661b525a72ceea43d 100644 (file)
@@ -123,8 +123,8 @@ static const struct mssr_mod_clk r8a774a1_mod_clks[] __initconst = {
        DEF_MOD("msiof2",                209,   R8A774A1_CLK_MSO),
        DEF_MOD("msiof1",                210,   R8A774A1_CLK_MSO),
        DEF_MOD("msiof0",                211,   R8A774A1_CLK_MSO),
-       DEF_MOD("sys-dmac2",             217,   R8A774A1_CLK_S0D3),
-       DEF_MOD("sys-dmac1",             218,   R8A774A1_CLK_S0D3),
+       DEF_MOD("sys-dmac2",             217,   R8A774A1_CLK_S3D1),
+       DEF_MOD("sys-dmac1",             218,   R8A774A1_CLK_S3D1),
        DEF_MOD("sys-dmac0",             219,   R8A774A1_CLK_S0D3),
        DEF_MOD("cmt3",                  300,   R8A774A1_CLK_R),
        DEF_MOD("cmt2",                  301,   R8A774A1_CLK_R),
index 5b658b0861180268297cfd9449161efab47c1006..a576a42f104442ffd120c0bc23a75e0d294753da 100644 (file)
@@ -130,8 +130,8 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = {
        DEF_MOD("msiof2",                209,   R8A7795_CLK_MSO),
        DEF_MOD("msiof1",                210,   R8A7795_CLK_MSO),
        DEF_MOD("msiof0",                211,   R8A7795_CLK_MSO),
-       DEF_MOD("sys-dmac2",             217,   R8A7795_CLK_S0D3),
-       DEF_MOD("sys-dmac1",             218,   R8A7795_CLK_S0D3),
+       DEF_MOD("sys-dmac2",             217,   R8A7795_CLK_S3D1),
+       DEF_MOD("sys-dmac1",             218,   R8A7795_CLK_S3D1),
        DEF_MOD("sys-dmac0",             219,   R8A7795_CLK_S0D3),
        DEF_MOD("sceg-pub",              229,   R8A7795_CLK_CR),
        DEF_MOD("cmt3",                  300,   R8A7795_CLK_R),
index fa1c1ac14d5caa1cc1a1c13e160c862d76dc6243..369092e8d893255f6850bc1f6f06433cecaa5c5a 100644 (file)
@@ -127,8 +127,8 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {
        DEF_MOD("msiof2",                209,   R8A7796_CLK_MSO),
        DEF_MOD("msiof1",                210,   R8A7796_CLK_MSO),
        DEF_MOD("msiof0",                211,   R8A7796_CLK_MSO),
-       DEF_MOD("sys-dmac2",             217,   R8A7796_CLK_S0D3),
-       DEF_MOD("sys-dmac1",             218,   R8A7796_CLK_S0D3),
+       DEF_MOD("sys-dmac2",             217,   R8A7796_CLK_S3D1),
+       DEF_MOD("sys-dmac1",             218,   R8A7796_CLK_S3D1),
        DEF_MOD("sys-dmac0",             219,   R8A7796_CLK_S0D3),
        DEF_MOD("cmt3",                  300,   R8A7796_CLK_R),
        DEF_MOD("cmt2",                  301,   R8A7796_CLK_R),
index 48a9add7d4db8975b17466a6ca2502a37c4bf157..623bbda2d24ec112ae2ec450af63e2bae28954eb 100644 (file)
@@ -123,8 +123,8 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = {
        DEF_MOD("msiof2",               209,    R8A77965_CLK_MSO),
        DEF_MOD("msiof1",               210,    R8A77965_CLK_MSO),
        DEF_MOD("msiof0",               211,    R8A77965_CLK_MSO),
-       DEF_MOD("sys-dmac2",            217,    R8A77965_CLK_S0D3),
-       DEF_MOD("sys-dmac1",            218,    R8A77965_CLK_S0D3),
+       DEF_MOD("sys-dmac2",            217,    R8A77965_CLK_S3D1),
+       DEF_MOD("sys-dmac1",            218,    R8A77965_CLK_S3D1),
        DEF_MOD("sys-dmac0",            219,    R8A77965_CLK_S0D3),
 
        DEF_MOD("cmt3",                 300,    R8A77965_CLK_R),