]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
arm: dts: rockchip: add reset node for the exist saradc SoCs
authorCaesar Wang <wxt@rock-chips.com>
Wed, 27 Jul 2016 14:24:07 +0000 (22:24 +0800)
committerJonathan Cameron <jic23@kernel.org>
Tue, 23 Aug 2016 18:08:29 +0000 (19:08 +0100)
SARADC controller needs to be reset before programming it, otherwise
it will not function properly.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Cc: <Stable@vger.kernel.org>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
arch/arm/boot/dts/rk3066a.dtsi
arch/arm/boot/dts/rk3288.dtsi
arch/arm/boot/dts/rk3xxx.dtsi

index c0ba86c3a2abf1f1463d6644d12f28cb6870d7cb..0d0dae3a16949f58c3a62c2826365118a1691cee 100644 (file)
@@ -197,6 +197,8 @@ tsadc: tsadc@20060000 {
                clock-names = "saradc", "apb_pclk";
                interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
                #io-channel-cells = <1>;
+               resets = <&cru SRST_SARADC>;
+               reset-names = "saradc-apb";
                status = "disabled";
        };
 
index cd33f017089001469df88ff6077253cb477afdb7..91c4b3c7a8d51def2cd4ef18b3e1a5ec7628fb9f 100644 (file)
@@ -279,6 +279,8 @@ saradc: saradc@ff100000 {
                #io-channel-cells = <1>;
                clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
                clock-names = "saradc", "apb_pclk";
+               resets = <&cru SRST_SARADC>;
+               reset-names = "saradc-apb";
                status = "disabled";
        };
 
index 99bbcc2c9b8978b28be5a253f6be236a8896a315..e2cd683b4e4b3d19825adf4f28da4b356179e43d 100644 (file)
@@ -399,6 +399,8 @@ saradc: saradc@2006c000 {
                #io-channel-cells = <1>;
                clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
                clock-names = "saradc", "apb_pclk";
+               resets = <&cru SRST_SARADC>;
+               reset-names = "saradc-apb";
                status = "disabled";
        };