arm64: dts: meson-sm1-sei610: enable DVFS

This enables DVFS for the Amlogic SM1 based SEI610 board by:
- Adding the SM1 SoC OPPs taken from the vendor tree
- Selecting the SM1 Clock controller instead of the G12A one
- Adding the CPU rail regulator, PWM and OPPs for each CPU nodes.

Each power supply can achieve 0.69V to 1.05V using a single PWM
output clocked at 666KHz with an inverse duty-cycle.

DVFS has been tested by running the arm64 cpuburn at [1] and cycling
between all the possible cpufreq translations of the cpu cluster and
checking the final frequency using the clock-measurer, script at [2].

[1] https://github.com/ssvb/cpuburn-arm/blob/master/cpuburn-a53.S
[2] https://gist.github.com/superna9999/d4de964dbc0f84b7d527e1df2ddea25f

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>

diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts
index 26469160103607904634b418680bd64b1425d0be..3435aaa4e8db50c7f28c0b08f2b802faf8e6f20f 100644 (file)
--- a/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts
@@ -136,6 +136,25 @@ vddao_3v3_t: regulator-vddao_3v3_t {
                regulator-always-on;
        };
 
+       vddcpu: regulator-vddcpu {
+               /*
+                * SY8120B1ABC DC/DC Regulator.
+                */
+               compatible = "pwm-regulator";
+
+               regulator-name = "VDDCPU";
+               regulator-min-microvolt = <690000>;
+               regulator-max-microvolt = <1050000>;
+
+               vin-supply = <&dc_in>;
+
+               pwms = <&pwm_AO_cd 1 1500 0>;
+               pwm-dutycycle-range = <100 0>;
+
+               regulator-boot-on;
+               regulator-always-on;
+       };
+
        vddio_ao1v8: regulator-vddio_ao1v8 {
                compatible = "regulator-fixed";
                regulator-name = "VDDIO_AO1V8";
@@ -182,6 +201,34 @@ &cecb_AO {
        hdmi-phandle = <&hdmi_tx>;
 };
 
+&cpu0 {
+       cpu-supply = <&vddcpu>;
+       operating-points-v2 = <&cpu_opp_table>;
+       clocks = <&clkc CLKID_CPU_CLK>;
+       clock-latency = <50000>;
+};
+
+&cpu1 {
+       cpu-supply = <&vddcpu>;
+       operating-points-v2 = <&cpu_opp_table>;
+       clocks = <&clkc CLKID_CPU1_CLK>;
+       clock-latency = <50000>;
+};
+
+&cpu2 {
+       cpu-supply = <&vddcpu>;
+       operating-points-v2 = <&cpu_opp_table>;
+       clocks = <&clkc CLKID_CPU2_CLK>;
+       clock-latency = <50000>;
+};
+
+&cpu3 {
+       cpu-supply = <&vddcpu>;
+       operating-points-v2 = <&cpu_opp_table>;
+       clocks = <&clkc CLKID_CPU3_CLK>;
+       clock-latency = <50000>;
+};
+
 &ethmac {
        status = "okay";
        phy-handle = <&internal_ephy>;
@@ -220,6 +267,14 @@ &pwm_AO_ab {
        clock-names = "clkin0";
 };
 
+&pwm_AO_cd {
+       pinctrl-0 = <&pwm_ao_d_e_pins>;
+       pinctrl-names = "default";
+       clocks = <&xtal>;
+       clock-names = "clkin1";
+       status = "okay";
+};
+
 &pwm_ef {
        status = "okay";
        pinctrl-0 = <&pwm_e_pins>;

diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
index 2322836aba65409b20af6bba71f4296a515a1df2..521573f3a5babef270b05b6080c846ef1def4431 100644 (file)
--- a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
@@ -50,6 +50,71 @@ l2: l2-cache0 {
                        compatible = "cache";
                };
        };
+
+       cpu_opp_table: opp-table {
+               compatible = "operating-points-v2";
+               opp-shared;
+
+               opp-100000000 {
+                       opp-hz = /bits/ 64 <100000000>;
+                       opp-microvolt = <730000>;
+               };
+
+               opp-250000000 {
+                       opp-hz = /bits/ 64 <250000000>;
+                       opp-microvolt = <730000>;
+               };
+
+               opp-500000000 {
+                       opp-hz = /bits/ 64 <500000000>;
+                       opp-microvolt = <730000>;
+               };
+
+               opp-667000000 {
+                       opp-hz = /bits/ 64 <666666666>;
+                       opp-microvolt = <750000>;
+               };
+
+               opp-1000000000 {
+                       opp-hz = /bits/ 64 <1000000000>;
+                       opp-microvolt = <770000>;
+               };
+
+               opp-1200000000 {
+                       opp-hz = /bits/ 64 <1200000000>;
+                       opp-microvolt = <780000>;
+               };
+
+               opp-1404000000 {
+                       opp-hz = /bits/ 64 <1404000000>;
+                       opp-microvolt = <790000>;
+               };
+
+               opp-1512000000 {
+                       opp-hz = /bits/ 64 <1500000000>;
+                       opp-microvolt = <800000>;
+               };
+
+               opp-1608000000 {
+                       opp-hz = /bits/ 64 <1608000000>;
+                       opp-microvolt = <810000>;
+               };
+
+               opp-1704000000 {
+                       opp-hz = /bits/ 64 <1704000000>;
+                       opp-microvolt = <850000>;
+               };
+
+               opp-1800000000 {
+                       opp-hz = /bits/ 64 <1800000000>;
+                       opp-microvolt = <900000>;
+               };
+
+               opp-1908000000 {
+                       opp-hz = /bits/ 64 <1908000000>;
+                       opp-microvolt = <950000>;
+               };
+       };
 };
 
 &cecb_AO {
@@ -61,6 +126,10 @@ &clk_msr {
 };
 
 
+&clkc {
+       compatible = "amlogic,sm1-clkc";
+};
+
 &ethmac {
        power-domains = <&pwrc PWRC_SM1_ETH_ID>;
 };