]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
clk: hi6220: add acpu clock
authorZhangfei Gao <zhangfei.gao@linaro.org>
Wed, 31 May 2017 01:45:38 +0000 (09:45 +0800)
committerStephen Boyd <sboyd@codeaurora.org>
Tue, 20 Jun 2017 02:02:42 +0000 (19:02 -0700)
Add acpu clock, including sft clock controlling hi6220 coresight module

Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: Li Pengcheng <lipengcheng8@huawei.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Documentation/devicetree/bindings/clock/hi6220-clock.txt
drivers/clk/hisilicon/clk-hi6220.c
include/dt-bindings/clock/hi6220-clock.h

index e4d5feaebc292c7944f32fe5484c2839444f7658..ef3deb7b86eaf18468a2b779c9b7786c92d158d0 100644 (file)
@@ -11,6 +11,7 @@ Required Properties:
 - compatible: the compatible should be one of the following strings to
        indicate the clock controller functionality.
 
+       - "hisilicon,hi6220-acpu-sctrl"
        - "hisilicon,hi6220-aoctrl"
        - "hisilicon,hi6220-sysctrl"
        - "hisilicon,hi6220-mediactrl"
index 2ae151ce623a9602f389c09a6817eb5698c3a32e..4181b68085456d9cc8f9f0ff0b8bbca5eb3fa7f5 100644 (file)
@@ -285,3 +285,25 @@ static void __init hi6220_clk_power_init(struct device_node *np)
                                ARRAY_SIZE(hi6220_div_clks_power), clk_data);
 }
 CLK_OF_DECLARE(hi6220_clk_power, "hisilicon,hi6220-pmctrl", hi6220_clk_power_init);
+
+/* clocks in acpu */
+static const struct hisi_gate_clock hi6220_acpu_sc_gate_sep_clks[] = {
+       { HI6220_ACPU_SFT_AT_S, "sft_at_s", "cs_atb",
+         CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0xc, 11, 0, },
+};
+
+static void __init hi6220_clk_acpu_init(struct device_node *np)
+{
+       struct hisi_clock_data *clk_data;
+       int nr = ARRAY_SIZE(hi6220_acpu_sc_gate_sep_clks);
+
+       clk_data = hisi_clk_init(np, nr);
+       if (!clk_data)
+               return;
+
+       hisi_clk_register_gate_sep(hi6220_acpu_sc_gate_sep_clks,
+                                  ARRAY_SIZE(hi6220_acpu_sc_gate_sep_clks),
+                                  clk_data);
+}
+
+CLK_OF_DECLARE(hi6220_clk_acpu, "hisilicon,hi6220-acpu-sctrl", hi6220_clk_acpu_init);
index b8ba665aab7b3486ad39777acda4a4aa0a249a5d..409cc02cd844c5f4760164795671ba61e6ef5e13 100644 (file)
 #define HI6220_DDRC_AXI1       7
 
 #define HI6220_POWER_NR_CLKS   8
+
+/* clk in Hi6220 acpu sctrl */
+#define HI6220_ACPU_SFT_AT_S           0
+
 #endif