arm64: dts: qcom: qcs404: Add HFPLL node

The high frequency pll functionality is required to enable CPU
frequency scaling operation.

Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20191125142511.681149-3-niklas.cassel@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
index c9e8e629045bcba7f6b1ef8799a1f243cfebe791..b5dff2aa1ab4d10f1b827c12afeb16e8481a52b9 100644 (file)
--- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
@@ -904,6 +904,15 @@ apcs_glb: mailbox@b011000 {
                        #mbox-cells = <1>;
                };
 
+               apcs_hfpll: clock-controller@b016000 {
+                       compatible = "qcom,hfpll";
+                       reg = <0x0b016000 0x30>;
+                       #clock-cells = <0>;
+                       clock-output-names = "apcs_hfpll";
+                       clocks = <&xo_board>;
+                       clock-names = "xo";
+               };
+
                watchdog@b017000 {
                        compatible = "qcom,apss-wdt-qcs404", "qcom,kpss-wdt";
                        reg = <0x0b017000 0x1000>;