PCI: dwc: Rename variable name from data to d on dw_pci_bottom_mask/unmask()

Rename variable from data to d to maintain consistency between driver
functions, such as dw_msi_mask_irq() and dw_msi_unmask_irq().

No functional change is intended.

Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Joao Pinto <jpinto@synopsys.com>
Cc: Jingoo Han <jingoohan1@gmail.com>

diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index 721d60a5d9e461ac0fd14ca6766266651fd4255f..36e284c75934bf322274781c0439f401731ca560 100644 (file)
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -149,20 +149,20 @@ static int dw_pci_msi_set_affinity(struct irq_data *irq_data,
        return -EINVAL;
 }
 
-static void dw_pci_bottom_mask(struct irq_data *data)
+static void dw_pci_bottom_mask(struct irq_data *d)
 {
-       struct pcie_port *pp = irq_data_get_irq_chip_data(data);
+       struct pcie_port *pp = irq_data_get_irq_chip_data(d);
        unsigned int res, bit, ctrl;
        unsigned long flags;
 
        raw_spin_lock_irqsave(&pp->lock, flags);
 
        if (pp->ops->msi_clear_irq) {
-               pp->ops->msi_clear_irq(pp, data->hwirq);
+               pp->ops->msi_clear_irq(pp, d->hwirq);
        } else {
-               ctrl = data->hwirq / MAX_MSI_IRQS_PER_CTRL;
+               ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;
                res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
-               bit = data->hwirq % MAX_MSI_IRQS_PER_CTRL;
+               bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
 
                pp->irq_status[ctrl] &= ~(1 << bit);
                dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + res, 4,
@@ -172,20 +172,20 @@ static void dw_pci_bottom_mask(struct irq_data *data)
        raw_spin_unlock_irqrestore(&pp->lock, flags);
 }
 
-static void dw_pci_bottom_unmask(struct irq_data *data)
+static void dw_pci_bottom_unmask(struct irq_data *d)
 {
-       struct pcie_port *pp = irq_data_get_irq_chip_data(data);
+       struct pcie_port *pp = irq_data_get_irq_chip_data(d);
        unsigned int res, bit, ctrl;
        unsigned long flags;
 
        raw_spin_lock_irqsave(&pp->lock, flags);
 
        if (pp->ops->msi_set_irq) {
-               pp->ops->msi_set_irq(pp, data->hwirq);
+               pp->ops->msi_set_irq(pp, d->hwirq);
        } else {
-               ctrl = data->hwirq / MAX_MSI_IRQS_PER_CTRL;
+               ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;
                res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
-               bit = data->hwirq % MAX_MSI_IRQS_PER_CTRL;
+               bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
 
                pp->irq_status[ctrl] |= 1 << bit;
                dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + res, 4,