]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
drm/amdgpu: Refine function name
authorRex Zhu <Rex.Zhu@amd.com>
Tue, 28 Aug 2018 10:20:19 +0000 (18:20 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 27 Sep 2018 02:09:18 +0000 (21:09 -0500)
change function name gfx_v6/7/8/9_0_gpu_init to
gfx_v6/7/8/9_0_constants_init.
this function is just for init gfx constants such
as max pipes, render backends...

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

index de184a8860573ef0413661ddb8b4d199b31513de..95d916ff099e31538673e84aadc6554011b22492 100644 (file)
@@ -1552,7 +1552,7 @@ static void gfx_v6_0_config_init(struct amdgpu_device *adev)
        adev->gfx.config.double_offchip_lds_buf = 0;
 }
 
-static void gfx_v6_0_gpu_init(struct amdgpu_device *adev)
+static void gfx_v6_0_constants_init(struct amdgpu_device *adev)
 {
        u32 gb_addr_config = 0;
        u32 mc_shared_chmap, mc_arb_ramcfg;
@@ -3175,7 +3175,7 @@ static int gfx_v6_0_hw_init(void *handle)
        int r;
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
-       gfx_v6_0_gpu_init(adev);
+       gfx_v6_0_constants_init(adev);
 
        r = gfx_v6_0_rlc_resume(adev);
        if (r)
index fc39ebbc9d9fd6dfc4ccfdd6d140ac046667d8a9..1c9ede0ba77ff45816e53bfe9e3a1da2ddbb1730 100644 (file)
@@ -1886,14 +1886,14 @@ static void gfx_v7_0_config_init(struct amdgpu_device *adev)
 }
 
 /**
- * gfx_v7_0_gpu_init - setup the 3D engine
+ * gfx_v7_0_constants_init - setup the 3D engine
  *
  * @adev: amdgpu_device pointer
  *
- * Configures the 3D engine and tiling configuration
- * registers so that the 3D engine is usable.
+ * init the gfx constants such as the 3D engine, tiling configuration
+ * registers, maximum number of quad pipes, render backends...
  */
-static void gfx_v7_0_gpu_init(struct amdgpu_device *adev)
+static void gfx_v7_0_constants_init(struct amdgpu_device *adev)
 {
        u32 sh_mem_cfg, sh_static_mem_cfg, sh_mem_base;
        u32 tmp;
@@ -4624,7 +4624,7 @@ static int gfx_v7_0_hw_init(void *handle)
        int r;
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
-       gfx_v7_0_gpu_init(adev);
+       gfx_v7_0_constants_init(adev);
 
        /* init rlc */
        r = gfx_v7_0_rlc_resume(adev);
index 470dc80f4fe72a520e58e55e3b84d0cc36bc2dbe..05b5bba7a5831e2fd4d3bc532a8f9ad3abce7d01 100644 (file)
@@ -3835,7 +3835,7 @@ static void gfx_v8_0_config_init(struct amdgpu_device *adev)
        }
 }
 
-static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
+static void gfx_v8_0_constants_init(struct amdgpu_device *adev)
 {
        u32 tmp, sh_static_mem_cfg;
        int i;
@@ -5039,7 +5039,7 @@ static int gfx_v8_0_hw_init(void *handle)
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
        gfx_v8_0_init_golden_registers(adev);
-       gfx_v8_0_gpu_init(adev);
+       gfx_v8_0_constants_init(adev);
 
        r = gfx_v8_0_rlc_resume(adev);
        if (r)
index f369d960343573aec5ea3c20f75bb54e177dcfb5..261bb051b14df176bdb9fa8bed70662a3ef08082 100644 (file)
@@ -1847,7 +1847,7 @@ static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev)
        mutex_unlock(&adev->srbm_mutex);
 }
 
-static void gfx_v9_0_gpu_init(struct amdgpu_device *adev)
+static void gfx_v9_0_constants_init(struct amdgpu_device *adev)
 {
        u32 tmp;
        int i;
@@ -3235,7 +3235,7 @@ static int gfx_v9_0_hw_init(void *handle)
 
        gfx_v9_0_init_golden_registers(adev);
 
-       gfx_v9_0_gpu_init(adev);
+       gfx_v9_0_constants_init(adev);
 
        r = gfx_v9_0_csb_vram_pin(adev);
        if (r)