usb/uhci: Add support for Aspeed BMC SoCs

The Aspeed 2400/2500 families have a variant of UHCI which requires
some quirks to the driver to work:

 - The register offsets are different. We add a remapping helper.

 - All accesses have to be done via 32-bit loads and stores. We
   force all accessors to use readl/writel. This is of no consequence
   for reads as we never read "in the middle" of a register. For writes
   it also works fine as the registers only actually implement the bits
   we try to write (16-bit for the registers accessed with writew and
   8-bit for the register accessed with writeb), so always using a
   32-bit write will have no negative effect. We never do partial writes.

 - The resume detect interrupt is broken

 - The number of ports is (optionally) provided via the device-tree

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Acked-by: Alan Stern <stern@rowland.harvard.edu>
--

v2. Remove the bulk of the #ifdef's

 drivers/usb/host/Kconfig         |  6 ++++-
 drivers/usb/host/uhci-hcd.c      | 17 +++++++++++---
 drivers/usb/host/uhci-hcd.h      | 51 ++++++++++++++++++++++++++++++++++++++++
 drivers/usb/host/uhci-platform.c | 22 ++++++++++++++++-
 4 files changed, 91 insertions(+), 5 deletions(-)
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index ababb91d654ab2a7ee3885da9c35ae8465290013..70d32a0cacab836ef352a18034749d5a5c71e163 100644 (file)
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -627,7 +627,11 @@ config USB_UHCI_SUPPORT_NON_PCI_HC
 
 config USB_UHCI_PLATFORM
        bool
-       default y if ARCH_VT8500
+       default y if (ARCH_VT8500 || ARCH_ASPEED)
+
+config USB_UHCI_ASPEED
+       bool
+       default y if ARCH_ASPEED
 
 config USB_UHCI_BIG_ENDIAN_MMIO
        bool

diff --git a/drivers/usb/host/uhci-hcd.c b/drivers/usb/host/uhci-hcd.c
index 94b150196d4f5d575ba5775aae1a29f112df0f55..c3267a78c94ea5852d67a720c7e74176ac24e34d 100644 (file)
--- a/drivers/usb/host/uhci-hcd.c
+++ b/drivers/usb/host/uhci-hcd.c
@@ -265,9 +265,13 @@ static void configure_hc(struct uhci_hcd *uhci)
 
 static int resume_detect_interrupts_are_broken(struct uhci_hcd *uhci)
 {
-       /* If we have to ignore overcurrent events then almost by definition
-        * we can't depend on resume-detect interrupts. */
-       if (ignore_oc)
+       /*
+        * If we have to ignore overcurrent events then almost by definition
+        * we can't depend on resume-detect interrupts.
+        *
+        * Those interrupts also don't seem to work on ASpeed SoCs.
+        */
+       if (ignore_oc || uhci_is_aspeed(uhci))
                return 1;
 
        return uhci->resume_detect_interrupts_are_broken ?
@@ -384,6 +388,13 @@ static void start_rh(struct uhci_hcd *uhci)
 {
        uhci->is_stopped = 0;
 
+       /*
+        * Clear stale status bits on Aspeed as we get a stale HCH
+        * which causes problems later on
+        */
+       if (uhci_is_aspeed(uhci))
+               uhci_writew(uhci, uhci_readw(uhci, USBSTS), USBSTS);
+
        /* Mark it configured and running with a 64-byte max packet.
         * All interrupts are enabled, even though RESUME won't do anything.
         */

diff --git a/drivers/usb/host/uhci-hcd.h b/drivers/usb/host/uhci-hcd.h
index 7fa318a3091d6556a1e9bb46fa3eda0f4ba39625..91b22b2ea3aa7d4cf11c46ffb3b679c8a9c9942f 100644 (file)
--- a/drivers/usb/host/uhci-hcd.h
+++ b/drivers/usb/host/uhci-hcd.h
@@ -48,6 +48,8 @@
 /* USB port status and control registers */
 #define USBPORTSC1     16
 #define USBPORTSC2     18
+#define USBPORTSC3     20
+#define USBPORTSC4     22
 #define   USBPORTSC_CCS                0x0001  /* Current Connect Status
                                         * ("device present") */
 #define   USBPORTSC_CSC                0x0002  /* Connect Status Change */
@@ -427,6 +429,7 @@ struct uhci_hcd {
        unsigned int wait_for_hp:1;             /* Wait for HP port reset */
        unsigned int big_endian_mmio:1;         /* Big endian registers */
        unsigned int big_endian_desc:1;         /* Big endian descriptors */
+       unsigned int is_aspeed:1;               /* Aspeed impl. workarounds */
 
        /* Support for port suspend/resume/reset */
        unsigned long port_c_suspend;           /* Bit-arrays of ports */
@@ -490,6 +493,12 @@ struct urb_priv {
 #define PCI_VENDOR_ID_GENESYS          0x17a0
 #define PCI_DEVICE_ID_GL880S_UHCI      0x8083
 
+/* Aspeed SoC needs some quirks */
+static inline bool uhci_is_aspeed(const struct uhci_hcd *uhci)
+{
+       return IS_ENABLED(CONFIG_USB_UHCI_ASPEED) && uhci->is_aspeed;
+}
+
 /*
  * Functions used to access controller registers. The UCHI spec says that host
  * controller I/O registers are mapped into PCI I/O space. For non-PCI hosts
@@ -545,10 +554,42 @@ static inline void uhci_writeb(const struct uhci_hcd *uhci, u8 val, int reg)
 #define uhci_big_endian_mmio(u)                0
 #endif
 
+static inline int uhci_aspeed_reg(unsigned int reg)
+{
+       switch (reg) {
+       case USBCMD:
+               return 00;
+       case USBSTS:
+               return 0x04;
+       case USBINTR:
+               return 0x08;
+       case USBFRNUM:
+               return 0x80;
+       case USBFLBASEADD:
+               return 0x0c;
+       case USBSOF:
+               return 0x84;
+       case USBPORTSC1:
+               return 0x88;
+       case USBPORTSC2:
+               return 0x8c;
+       case USBPORTSC3:
+               return 0x90;
+       case USBPORTSC4:
+               return 0x94;
+       default:
+               pr_warn("UHCI: Unsupported register 0x%02x on Aspeed\n", reg);
+               /* Return an unimplemented register */
+               return 0x10;
+       }
+}
+
 static inline u32 uhci_readl(const struct uhci_hcd *uhci, int reg)
 {
        if (uhci_has_pci_registers(uhci))
                return inl(uhci->io_addr + reg);
+       else if (uhci_is_aspeed(uhci))
+               return readl(uhci->regs + uhci_aspeed_reg(reg));
 #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO
        else if (uhci_big_endian_mmio(uhci))
                return readl_be(uhci->regs + reg);
@@ -561,6 +602,8 @@ static inline void uhci_writel(const struct uhci_hcd *uhci, u32 val, int reg)
 {
        if (uhci_has_pci_registers(uhci))
                outl(val, uhci->io_addr + reg);
+       else if (uhci_is_aspeed(uhci))
+               writel(val, uhci->regs + uhci_aspeed_reg(reg));
 #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO
        else if (uhci_big_endian_mmio(uhci))
                writel_be(val, uhci->regs + reg);
@@ -573,6 +616,8 @@ static inline u16 uhci_readw(const struct uhci_hcd *uhci, int reg)
 {
        if (uhci_has_pci_registers(uhci))
                return inw(uhci->io_addr + reg);
+       else if (uhci_is_aspeed(uhci))
+               return readl(uhci->regs + uhci_aspeed_reg(reg));
 #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO
        else if (uhci_big_endian_mmio(uhci))
                return readw_be(uhci->regs + reg);
@@ -585,6 +630,8 @@ static inline void uhci_writew(const struct uhci_hcd *uhci, u16 val, int reg)
 {
        if (uhci_has_pci_registers(uhci))
                outw(val, uhci->io_addr + reg);
+       else if (uhci_is_aspeed(uhci))
+               writel(val, uhci->regs + uhci_aspeed_reg(reg));
 #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO
        else if (uhci_big_endian_mmio(uhci))
                writew_be(val, uhci->regs + reg);
@@ -597,6 +644,8 @@ static inline u8 uhci_readb(const struct uhci_hcd *uhci, int reg)
 {
        if (uhci_has_pci_registers(uhci))
                return inb(uhci->io_addr + reg);
+       else if (uhci_is_aspeed(uhci))
+               return readl(uhci->regs + uhci_aspeed_reg(reg));
 #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO
        else if (uhci_big_endian_mmio(uhci))
                return readb_be(uhci->regs + reg);
@@ -609,6 +658,8 @@ static inline void uhci_writeb(const struct uhci_hcd *uhci, u8 val, int reg)
 {
        if (uhci_has_pci_registers(uhci))
                outb(val, uhci->io_addr + reg);
+       else if (uhci_is_aspeed(uhci))
+               writel(val, uhci->regs + uhci_aspeed_reg(reg));
 #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO
        else if (uhci_big_endian_mmio(uhci))
                writeb_be(val, uhci->regs + reg);

diff --git a/drivers/usb/host/uhci-platform.c b/drivers/usb/host/uhci-platform.c
index 32a6f3d8deecf54abd4deaaa330bcd44f752cc11..1b4e086c33a0d5400442198bac244579c85033c5 100644 (file)
--- a/drivers/usb/host/uhci-platform.c
+++ b/drivers/usb/host/uhci-platform.c
@@ -15,7 +15,9 @@ static int uhci_platform_init(struct usb_hcd *hcd)
 {
        struct uhci_hcd *uhci = hcd_to_uhci(hcd);
 
-       uhci->rh_numports = uhci_count_ports(hcd);
+       /* Probe number of ports if not already provided by DT */
+       if (!uhci->rh_numports)
+               uhci->rh_numports = uhci_count_ports(hcd);
 
        /* Set up pointers to to generic functions */
        uhci->reset_hc = uhci_generic_reset_hc;
@@ -63,6 +65,7 @@ static const struct hc_driver uhci_platform_hc_driver = {
 
 static int uhci_hcd_platform_probe(struct platform_device *pdev)
 {
+       struct device_node *np = pdev->dev.of_node;
        struct usb_hcd *hcd;
        struct uhci_hcd *uhci;
        struct resource *res;
@@ -98,6 +101,23 @@ static int uhci_hcd_platform_probe(struct platform_device *pdev)
 
        uhci->regs = hcd->regs;
 
+       /* Grab some things from the device-tree */
+       if (np) {
+               u32 num_ports;
+
+               if (of_property_read_u32(np, "#ports", &num_ports) == 0) {
+                       uhci->rh_numports = num_ports;
+                       dev_info(&pdev->dev,
+                               "Detected %d ports from device-tree\n",
+                               num_ports);
+               }
+               if (of_device_is_compatible(np, "aspeed,ast2400-uhci") ||
+                   of_device_is_compatible(np, "aspeed,ast2500-uhci")) {
+                       uhci->is_aspeed = 1;
+                       dev_info(&pdev->dev,
+                                "Enabled Aspeed implementation workarounds\n");
+               }
+       }
        ret = usb_add_hcd(hcd, pdev->resource[1].start, IRQF_SHARED);
        if (ret)
                goto err_rmr;