pinctrl: sunxi: refactor irq related register function to have desc

As the new H6 SoC has holes in the IRQ registers, refactor the IRQ
related register function for getting the full pinctrl desc structure.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
index bc3d59f2173f2ad78faa28904e81a91c041d9a94..020d6d84639ca002e20f843c7d0e33ba80031e02 100644 (file)
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -835,7 +835,7 @@ static void sunxi_pinctrl_irq_release_resources(struct irq_data *d)
 static int sunxi_pinctrl_irq_set_type(struct irq_data *d, unsigned int type)
 {
        struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
-       u32 reg = sunxi_irq_cfg_reg(d->hwirq, pctl->desc->irq_bank_base);
+       u32 reg = sunxi_irq_cfg_reg(pctl->desc, d->hwirq);
        u8 index = sunxi_irq_cfg_offset(d->hwirq);
        unsigned long flags;
        u32 regval;
@@ -882,8 +882,7 @@ static int sunxi_pinctrl_irq_set_type(struct irq_data *d, unsigned int type)
 static void sunxi_pinctrl_irq_ack(struct irq_data *d)
 {
        struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
-       u32 status_reg = sunxi_irq_status_reg(d->hwirq,
-                                             pctl->desc->irq_bank_base);
+       u32 status_reg = sunxi_irq_status_reg(pctl->desc, d->hwirq);
        u8 status_idx = sunxi_irq_status_offset(d->hwirq);
 
        /* Clear the IRQ */
@@ -893,7 +892,7 @@ static void sunxi_pinctrl_irq_ack(struct irq_data *d)
 static void sunxi_pinctrl_irq_mask(struct irq_data *d)
 {
        struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
-       u32 reg = sunxi_irq_ctrl_reg(d->hwirq, pctl->desc->irq_bank_base);
+       u32 reg = sunxi_irq_ctrl_reg(pctl->desc, d->hwirq);
        u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
        unsigned long flags;
        u32 val;
@@ -910,7 +909,7 @@ static void sunxi_pinctrl_irq_mask(struct irq_data *d)
 static void sunxi_pinctrl_irq_unmask(struct irq_data *d)
 {
        struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
-       u32 reg = sunxi_irq_ctrl_reg(d->hwirq, pctl->desc->irq_bank_base);
+       u32 reg = sunxi_irq_ctrl_reg(pctl->desc, d->hwirq);
        u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
        unsigned long flags;
        u32 val;
@@ -1002,7 +1001,7 @@ static void sunxi_pinctrl_irq_handler(struct irq_desc *desc)
        if (bank == pctl->desc->irq_banks)
                return;
 
-       reg = sunxi_irq_status_reg_from_bank(bank, pctl->desc->irq_bank_base);
+       reg = sunxi_irq_status_reg_from_bank(pctl->desc, bank);
        val = readl(pctl->membase + reg);
 
        if (val) {
@@ -1234,8 +1233,7 @@ static int sunxi_pinctrl_setup_debounce(struct sunxi_pinctrl *pctl,
 
                writel(src | div << 4,
                       pctl->membase +
-                      sunxi_irq_debounce_reg_from_bank(i,
-                                                       pctl->desc->irq_bank_base));
+                      sunxi_irq_debounce_reg_from_bank(pctl->desc, i));
        }
 
        return 0;
@@ -1411,11 +1409,11 @@ int sunxi_pinctrl_init_with_variant(struct platform_device *pdev,
 
        for (i = 0; i < pctl->desc->irq_banks; i++) {
                /* Mask and clear all IRQs before registering a handler */
-               writel(0, pctl->membase + sunxi_irq_ctrl_reg_from_bank(i,
-                                               pctl->desc->irq_bank_base));
+               writel(0, pctl->membase +
+                         sunxi_irq_ctrl_reg_from_bank(pctl->desc, i));
                writel(0xffffffff,
-                      pctl->membase + sunxi_irq_status_reg_from_bank(i,
-                                               pctl->desc->irq_bank_base));
+                      pctl->membase +
+                      sunxi_irq_status_reg_from_bank(pctl->desc, i));
 
                irq_set_chained_handler_and_data(pctl->irq[i],
                                                 sunxi_pinctrl_irq_handler,

diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
index 11b128f54ed2def6e8efb7044497a1d3e24a85be..a13bd57d880da3b3da5bc0a6888e04c02fadd630 100644 (file)
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
@@ -263,8 +263,10 @@ static inline u32 sunxi_pull_offset(u16 pin)
        return pin_num * PULL_PINS_BITS;
 }
 
-static inline u32 sunxi_irq_cfg_reg(u16 irq, unsigned bank_base)
+static inline u32 sunxi_irq_cfg_reg(const struct sunxi_pinctrl_desc *desc,
+                                   u16 irq)
 {
+       unsigned bank_base = desc->irq_bank_base;
        u8 bank = irq / IRQ_PER_BANK;
        u8 reg = (irq % IRQ_PER_BANK) / IRQ_CFG_IRQ_PER_REG * 0x04;
 
@@ -277,16 +279,19 @@ static inline u32 sunxi_irq_cfg_offset(u16 irq)
        return irq_num * IRQ_CFG_IRQ_BITS;
 }
 
-static inline u32 sunxi_irq_ctrl_reg_from_bank(u8 bank, unsigned bank_base)
+static inline u32 sunxi_irq_ctrl_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank)
 {
+       unsigned bank_base = desc->irq_bank_base;
+
        return IRQ_CTRL_REG + (bank_base + bank) * IRQ_MEM_SIZE;
 }
 
-static inline u32 sunxi_irq_ctrl_reg(u16 irq, unsigned bank_base)
+static inline u32 sunxi_irq_ctrl_reg(const struct sunxi_pinctrl_desc *desc,
+                                    u16 irq)
 {
        u8 bank = irq / IRQ_PER_BANK;
 
-       return sunxi_irq_ctrl_reg_from_bank(bank, bank_base);
+       return sunxi_irq_ctrl_reg_from_bank(desc, bank);
 }
 
 static inline u32 sunxi_irq_ctrl_offset(u16 irq)
@@ -295,21 +300,26 @@ static inline u32 sunxi_irq_ctrl_offset(u16 irq)
        return irq_num * IRQ_CTRL_IRQ_BITS;
 }
 
-static inline u32 sunxi_irq_debounce_reg_from_bank(u8 bank, unsigned bank_base)
+static inline u32 sunxi_irq_debounce_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank)
 {
+       unsigned bank_base = desc->irq_bank_base;
+
        return IRQ_DEBOUNCE_REG + (bank_base + bank) * IRQ_MEM_SIZE;
 }
 
-static inline u32 sunxi_irq_status_reg_from_bank(u8 bank, unsigned bank_base)
+static inline u32 sunxi_irq_status_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank)
 {
+       unsigned bank_base = desc->irq_bank_base;
+
        return IRQ_STATUS_REG + (bank_base + bank) * IRQ_MEM_SIZE;
 }
 
-static inline u32 sunxi_irq_status_reg(u16 irq, unsigned bank_base)
+static inline u32 sunxi_irq_status_reg(const struct sunxi_pinctrl_desc *desc,
+                                      u16 irq)
 {
        u8 bank = irq / IRQ_PER_BANK;
 
-       return sunxi_irq_status_reg_from_bank(bank, bank_base);
+       return sunxi_irq_status_reg_from_bank(desc, bank);
 }
 
 static inline u32 sunxi_irq_status_offset(u16 irq)