]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
ARM: dts: rockchip: move rk3288 edp phy under the GRF
authorHeiko Stuebner <heiko@sntech.de>
Fri, 15 Apr 2016 21:28:57 +0000 (23:28 +0200)
committerHeiko Stuebner <heiko@sntech.de>
Fri, 15 Apr 2016 21:28:57 +0000 (23:28 +0200)
The edp-phy control is a part of the General Register Files and
with a recent patch in 4.6 the phy driver can now also handle this
correctly, so move the dts node under the GRF as well.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
arch/arm/boot/dts/rk3288.dtsi

index 180eb975ead51afdeb34dd5e34be617333a52cec..9068189552150115ec7a0660c701da6b5649cbe0 100644 (file)
@@ -201,15 +201,6 @@ xin24m: oscillator {
                #clock-cells = <0>;
        };
 
-       edp_phy: edp-phy {
-               compatible = "rockchip,rk3288-dp-phy";
-               clocks = <&cru SCLK_EDP_24M>;
-               clock-names = "24m";
-               rockchip,grf = <&grf>;
-               #phy-cells = <0>;
-               status = "disabled";
-       };
-
        timer {
                compatible = "arm,armv7-timer";
                arm,cpu-registers-not-fw-configured;
@@ -756,6 +747,14 @@ cru: clock-controller@ff760000 {
        grf: syscon@ff770000 {
                compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
                reg = <0xff770000 0x1000>;
+
+               edp_phy: edp-phy {
+                       compatible = "rockchip,rk3288-dp-phy";
+                       clocks = <&cru SCLK_EDP_24M>;
+                       clock-names = "24m";
+                       #phy-cells = <0>;
+                       status = "disabled";
+               };
        };
 
        wdt: watchdog@ff800000 {