mtd: spi-nor: intel-spi: add support for Intel Cannon Lake SPI flash

Now that SPI flash controllers without a software sequencer are
supported, it's trivial to add support for CNL and its PCI ID.

Values from https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/300-series-chipset-pch-datasheet-vol-2.pdf

Signed-off-by: Jethro Beekman <jethro@fortanix.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>

diff --git a/drivers/mtd/spi-nor/intel-spi-pci.c b/drivers/mtd/spi-nor/intel-spi-pci.c
index 3cda8e7a68f8167437cc7397f68a6743836ee8b1..581d154796c1e5ced02c0b573831051575492d86 100644 (file)
--- a/drivers/mtd/spi-nor/intel-spi-pci.c
+++ b/drivers/mtd/spi-nor/intel-spi-pci.c
@@ -20,6 +20,10 @@ static const struct intel_spi_boardinfo bxt_info = {
        .type = INTEL_SPI_BXT,
 };
 
+static const struct intel_spi_boardinfo cnl_info = {
+       .type = INTEL_SPI_CNL,
+};
+
 static int intel_spi_pci_probe(struct pci_dev *pdev,
                               const struct pci_device_id *id)
 {
@@ -68,6 +72,7 @@ static const struct pci_device_id intel_spi_pci_ids[] = {
        { PCI_VDEVICE(INTEL, 0xa0a4), (unsigned long)&bxt_info },
        { PCI_VDEVICE(INTEL, 0xa1a4), (unsigned long)&bxt_info },
        { PCI_VDEVICE(INTEL, 0xa224), (unsigned long)&bxt_info },
+       { PCI_VDEVICE(INTEL, 0xa324), (unsigned long)&cnl_info },
        { },
 };
 MODULE_DEVICE_TABLE(pci, intel_spi_pci_ids);

diff --git a/drivers/mtd/spi-nor/intel-spi.c b/drivers/mtd/spi-nor/intel-spi.c
index a85af3b65f2f5e18bb6c100c027c613866612c0b..8420528dbaa873c0ea25ffb125e214735ab21d16 100644 (file)
--- a/drivers/mtd/spi-nor/intel-spi.c
+++ b/drivers/mtd/spi-nor/intel-spi.c
@@ -108,6 +108,10 @@
 #define BXT_FREG_NUM                   12
 #define BXT_PR_NUM                     6
 
+#define CNL_PR                         0x84
+#define CNL_FREG_NUM                   6
+#define CNL_PR_NUM                     5
+
 #define LVSCC                          0xc4
 #define UVSCC                          0xc8
 #define ERASE_OPCODE_SHIFT             8
@@ -344,6 +348,13 @@ static int intel_spi_init(struct intel_spi *ispi)
                ispi->erase_64k = true;
                break;
 
+       case INTEL_SPI_CNL:
+               ispi->sregs = NULL;
+               ispi->pregs = ispi->base + CNL_PR;
+               ispi->nregions = CNL_FREG_NUM;
+               ispi->pr_num = CNL_PR_NUM;
+               break;
+
        default:
                return -EINVAL;
        }

diff --git a/include/linux/platform_data/intel-spi.h b/include/linux/platform_data/intel-spi.h
index ebb4f332588b270d6975a30e82fca7b669957afe..7f53a5c6f35e88a704116a0b30577e8633c194b6 100644 (file)
--- a/include/linux/platform_data/intel-spi.h
+++ b/include/linux/platform_data/intel-spi.h
@@ -13,6 +13,7 @@ enum intel_spi_type {
        INTEL_SPI_BYT = 1,
        INTEL_SPI_LPT,
        INTEL_SPI_BXT,
+       INTEL_SPI_CNL,
 };
 
 /**