- directory with info on controlling backlights in flat panel displays
bcache.txt
- Block-layer cache on fast SSDs to improve slow (raid) I/O performance.
-blackfin/
- - directory with documentation for the Blackfin arch.
block/
- info on the Block I/O (BIO) layer.
blockdev/
APM Advanced Power Management support is enabled.
ARM ARM architecture is enabled.
AX25 Appropriate AX.25 support is enabled.
- BLACKFIN Blackfin architecture is enabled.
CLK Common clock infrastructure is enabled.
CMA Contiguous Memory Area support is enabled.
DRM Direct Rendering Management support is enabled.
address. The serial port must already be setup
and configured. Options are not yet supported.
- earlyprintk= [X86,SH,BLACKFIN,ARM,M68k,S390]
+ earlyprintk= [X86,SH,ARM,M68k,S390]
earlyprintk=vga
earlyprintk=efi
earlyprintk=sclp
+++ /dev/null
-00-INDEX
- - This file
-bfin-gpio-notes.txt
- - Notes in developing/using bfin-gpio driver.
-bfin-spi-notes.txt
- - Notes for using bfin spi bus driver.
+++ /dev/null
-/*
- * File: Documentation/blackfin/bfin-gpio-notes.txt
- * Based on:
- * Author:
- *
- * Created: $Id: bfin-gpio-note.txt 2008-11-24 16:42 grafyang $
- * Description: This file contains the notes in developing/using bfin-gpio.
- *
- *
- * Rev:
- *
- * Modified:
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Bugs: Enter bugs at http://blackfin.uclinux.org/
- *
- */
-
-
-1. Blackfin GPIO introduction
-
- There are many GPIO pins on Blackfin. Most of these pins are muxed to
- multi-functions. They can be configured as peripheral, or just as GPIO,
- configured to input with interrupt enabled, or output.
-
- For detailed information, please see "arch/blackfin/kernel/bfin_gpio.c",
- or the relevant HRM.
-
-
-2. Avoiding resource conflict
-
- Followed function groups are used to avoiding resource conflict,
- - Use the pin as peripheral,
- int peripheral_request(unsigned short per, const char *label);
- int peripheral_request_list(const unsigned short per[], const char *label);
- void peripheral_free(unsigned short per);
- void peripheral_free_list(const unsigned short per[]);
- - Use the pin as GPIO,
- int bfin_gpio_request(unsigned gpio, const char *label);
- void bfin_gpio_free(unsigned gpio);
- - Use the pin as GPIO interrupt,
- int bfin_gpio_irq_request(unsigned gpio, const char *label);
- void bfin_gpio_irq_free(unsigned gpio);
-
- The request functions will record the function state for a certain pin,
- the free functions will clear its function state.
- Once a pin is requested, it can't be requested again before it is freed by
- previous caller, otherwise kernel will dump stacks, and the request
- function fail.
- These functions are wrapped by other functions, most of the users need not
- care.
-
-
-3. But there are some exceptions
- - Kernel permit the identical GPIO be requested both as GPIO and GPIO
- interrupt.
- Some drivers, like gpio-keys, need this behavior. Kernel only print out
- warning messages like,
- bfin-gpio: GPIO 24 is already reserved by gpio-keys: BTN0, and you are
-configuring it as IRQ!
-
- Note: Consider the case that, if there are two drivers need the
- identical GPIO, one of them use it as GPIO, the other use it as
- GPIO interrupt. This will really cause resource conflict. So if
- there is any abnormal driver behavior, please check the bfin-gpio
- warning messages.
-
- - Kernel permit the identical GPIO be requested from the same driver twice.
-
-
-
+++ /dev/null
-SPI Chip Select behavior:
-
-With the Blackfin on-chip SPI peripheral, there is some logic tied to the CPHA
-bit whether the Slave Select Line is controlled by hardware (CPHA=0) or
-controlled by software (CPHA=1). However, the Linux SPI bus driver assumes that
-the Slave Select is always under software control and being asserted during
-the entire SPI transfer. - And not just bits_per_word duration.
-
-In most cases you can utilize SPI MODE_3 instead of MODE_0 to work-around this
-behavior. If your SPI slave device in question requires SPI MODE_0 or MODE_2
-timing, you can utilize the GPIO controlled SPI Slave Select option instead.
-In this case, you should use GPIO based CS for all of your slaves and not just
-the ones using mode 0 or 2 in order to guarantee correct CS toggling behavior.
-
-You can even use the same pin whose peripheral role is a SSEL,
-but use it as a GPIO instead.
F: fs/bfs/
F: include/uapi/linux/bfs_fs.h
-BLACKFIN ARCHITECTURE
-L: adi-buildroot-devel@lists.sourceforge.net (moderated for non-subscribers)
-T: git git://git.code.sf.net/p/adi-linux/code
-W: http://blackfin.uclinux.org
-S: Orphan
-F: arch/blackfin/
-
-BLACKFIN EMAC DRIVER
-L: adi-buildroot-devel@lists.sourceforge.net (moderated for non-subscribers)
-W: http://blackfin.uclinux.org
-S: Orphan
-F: drivers/net/ethernet/adi/
-
-BLACKFIN MEDIA DRIVER
-L: adi-buildroot-devel@lists.sourceforge.net (moderated for non-subscribers)
-W: http://blackfin.uclinux.org/
-S: Orphan
-F: drivers/media/platform/blackfin/
-F: drivers/media/i2c/adv7183*
-F: drivers/media/i2c/vs6624*
-
-BLACKFIN RTC DRIVER
-L: adi-buildroot-devel@lists.sourceforge.net (moderated for non-subscribers)
-W: http://blackfin.uclinux.org
-S: Orphan
-F: drivers/rtc/rtc-bfin.c
-
-BLACKFIN SDH DRIVER
-L: adi-buildroot-devel@lists.sourceforge.net (moderated for non-subscribers)
-W: http://blackfin.uclinux.org
-S: Orphan
-F: drivers/mmc/host/bfin_sdh.c
-
-BLACKFIN SERIAL DRIVER
-L: adi-buildroot-devel@lists.sourceforge.net (moderated for non-subscribers)
-W: http://blackfin.uclinux.org
-S: Orphan
-F: drivers/tty/serial/bfin_uart.c
-
-BLACKFIN WATCHDOG DRIVER
-L: adi-buildroot-devel@lists.sourceforge.net (moderated for non-subscribers)
-W: http://blackfin.uclinux.org
-S: Orphan
-F: drivers/watchdog/bfin_wdt.c
-
BLINKM RGB LED DRIVER
M: Jan-Simon Moeller <jansimon.moeller@gmx.de>
S: Maintained
+++ /dev/null
-The Clear BSD license:
-
-Copyright (c) 2012, Analog Devices, Inc. All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted (subject to the limitations in the
-disclaimer below) provided that the following conditions are met:
-
-* Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
-
-* Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the
- distribution.
-
-* Neither the name of Analog Devices, Inc. nor the names of its
- contributors may be used to endorse or promote products derived
- from this software without specific prior written permission.
-
-NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
-GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
-HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
-WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
-OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
-IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0
-config MMU
- def_bool n
-
-config FPU
- def_bool n
-
-config RWSEM_GENERIC_SPINLOCK
- def_bool y
-
-config RWSEM_XCHGADD_ALGORITHM
- def_bool n
-
-config BLACKFIN
- def_bool y
- select HAVE_ARCH_KGDB
- select HAVE_ARCH_TRACEHOOK
- select HAVE_DYNAMIC_FTRACE
- select HAVE_FTRACE_MCOUNT_RECORD
- select HAVE_FUNCTION_GRAPH_TRACER
- select HAVE_FUNCTION_TRACER
- select HAVE_IDE
- select HAVE_KERNEL_GZIP if RAMKERNEL
- select HAVE_KERNEL_BZIP2 if RAMKERNEL
- select HAVE_KERNEL_LZMA if RAMKERNEL
- select HAVE_KERNEL_LZO if RAMKERNEL
- select HAVE_OPROFILE
- select HAVE_PERF_EVENTS
- select ARCH_HAVE_CUSTOM_GPIO_H
- select GPIOLIB
- select HAVE_UID16
- select HAVE_UNDERSCORE_SYMBOL_PREFIX
- select VIRT_TO_BUS
- select ARCH_WANT_IPC_PARSE_VERSION
- select GENERIC_ATOMIC64
- select GENERIC_IRQ_PROBE
- select GENERIC_IRQ_SHOW
- select HAVE_NMI_WATCHDOG if NMI_WATCHDOG
- select GENERIC_SMP_IDLE_THREAD
- select ARCH_USES_GETTIMEOFFSET if !GENERIC_CLOCKEVENTS
- select HAVE_MOD_ARCH_SPECIFIC
- select MODULES_USE_ELF_RELA
- select HAVE_DEBUG_STACKOVERFLOW
- select HAVE_NMI
- select ARCH_NO_COHERENT_DMA_MMAP
-
-config GENERIC_CSUM
- def_bool y
-
-config GENERIC_BUG
- def_bool y
- depends on BUG
-
-config ZONE_DMA
- def_bool y
-
-config FORCE_MAX_ZONEORDER
- int
- default "14"
-
-config GENERIC_CALIBRATE_DELAY
- def_bool y
-
-config LOCKDEP_SUPPORT
- def_bool y
-
-config STACKTRACE_SUPPORT
- def_bool y
-
-config TRACE_IRQFLAGS_SUPPORT
- def_bool y
-
-source "init/Kconfig"
-
-source "kernel/Kconfig.preempt"
-
-source "kernel/Kconfig.freezer"
-
-menu "Blackfin Processor Options"
-
-comment "Processor and Board Settings"
-
-choice
- prompt "CPU"
- default BF533
-
-config BF512
- bool "BF512"
- help
- BF512 Processor Support.
-
-config BF514
- bool "BF514"
- help
- BF514 Processor Support.
-
-config BF516
- bool "BF516"
- help
- BF516 Processor Support.
-
-config BF518
- bool "BF518"
- help
- BF518 Processor Support.
-
-config BF522
- bool "BF522"
- help
- BF522 Processor Support.
-
-config BF523
- bool "BF523"
- help
- BF523 Processor Support.
-
-config BF524
- bool "BF524"
- help
- BF524 Processor Support.
-
-config BF525
- bool "BF525"
- help
- BF525 Processor Support.
-
-config BF526
- bool "BF526"
- help
- BF526 Processor Support.
-
-config BF527
- bool "BF527"
- help
- BF527 Processor Support.
-
-config BF531
- bool "BF531"
- help
- BF531 Processor Support.
-
-config BF532
- bool "BF532"
- help
- BF532 Processor Support.
-
-config BF533
- bool "BF533"
- help
- BF533 Processor Support.
-
-config BF534
- bool "BF534"
- help
- BF534 Processor Support.
-
-config BF536
- bool "BF536"
- help
- BF536 Processor Support.
-
-config BF537
- bool "BF537"
- help
- BF537 Processor Support.
-
-config BF538
- bool "BF538"
- help
- BF538 Processor Support.
-
-config BF539
- bool "BF539"
- help
- BF539 Processor Support.
-
-config BF542_std
- bool "BF542"
- help
- BF542 Processor Support.
-
-config BF542M
- bool "BF542m"
- help
- BF542 Processor Support.
-
-config BF544_std
- bool "BF544"
- help
- BF544 Processor Support.
-
-config BF544M
- bool "BF544m"
- help
- BF544 Processor Support.
-
-config BF547_std
- bool "BF547"
- help
- BF547 Processor Support.
-
-config BF547M
- bool "BF547m"
- help
- BF547 Processor Support.
-
-config BF548_std
- bool "BF548"
- help
- BF548 Processor Support.
-
-config BF548M
- bool "BF548m"
- help
- BF548 Processor Support.
-
-config BF549_std
- bool "BF549"
- help
- BF549 Processor Support.
-
-config BF549M
- bool "BF549m"
- help
- BF549 Processor Support.
-
-config BF561
- bool "BF561"
- help
- BF561 Processor Support.
-
-config BF609
- bool "BF609"
- select CLKDEV_LOOKUP
- help
- BF609 Processor Support.
-
-endchoice
-
-config SMP
- depends on BF561
- select TICKSOURCE_CORETMR
- bool "Symmetric multi-processing support"
- ---help---
- This enables support for systems with more than one CPU,
- like the dual core BF561. If you have a system with only one
- CPU, say N. If you have a system with more than one CPU, say Y.
-
- If you don't know what to do here, say N.
-
-config NR_CPUS
- int
- depends on SMP
- default 2 if BF561
-
-config HOTPLUG_CPU
- bool "Support for hot-pluggable CPUs"
- depends on SMP
- default y
-
-config BF_REV_MIN
- int
- default 0 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x
- default 2 if (BF537 || BF536 || BF534)
- default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
- default 4 if (BF538 || BF539)
-
-config BF_REV_MAX
- int
- default 2 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x
- default 3 if (BF537 || BF536 || BF534 || BF54xM)
- default 5 if (BF561 || BF538 || BF539)
- default 6 if (BF533 || BF532 || BF531)
-
-choice
- prompt "Silicon Rev"
- default BF_REV_0_0 if (BF51x || BF52x || BF60x)
- default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
- default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
-
-config BF_REV_0_0
- bool "0.0"
- depends on (BF51x || BF52x || (BF54x && !BF54xM) || BF60x)
-
-config BF_REV_0_1
- bool "0.1"
- depends on (BF51x || BF52x || (BF54x && !BF54xM) || BF60x)
-
-config BF_REV_0_2
- bool "0.2"
- depends on (BF51x || BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
-
-config BF_REV_0_3
- bool "0.3"
- depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
-
-config BF_REV_0_4
- bool "0.4"
- depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539 || BF54x)
-
-config BF_REV_0_5
- bool "0.5"
- depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
-
-config BF_REV_0_6
- bool "0.6"
- depends on (BF533 || BF532 || BF531)
-
-config BF_REV_ANY
- bool "any"
-
-config BF_REV_NONE
- bool "none"
-
-endchoice
-
-config BF53x
- bool
- depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
- default y
-
-config GPIO_ADI
- def_bool y
- depends on !PINCTRL
- depends on (BF51x || BF52x || BF53x || BF538 || BF539 || BF561)
-
-config PINCTRL_BLACKFIN_ADI2
- def_bool y
- depends on (BF54x || BF60x)
- select PINCTRL
- select PINCTRL_ADI2
-
-config MEM_MT48LC64M4A2FB_7E
- bool
- depends on (BFIN533_STAMP)
- default y
-
-config MEM_MT48LC16M16A2TG_75
- bool
- depends on (BFIN533_EZKIT || BFIN561_EZKIT \
- || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \
- || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \
- || BFIN527_BLUETECHNIX_CM)
- default y
-
-config MEM_MT48LC32M8A2_75
- bool
- depends on (BFIN518F_EZBRD || BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
- default y
-
-config MEM_MT48LC8M32B2B5_7
- bool
- depends on (BFIN561_BLUETECHNIX_CM)
- default y
-
-config MEM_MT48LC32M16A2TG_75
- bool
- depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP || BFIN527_AD7160EVAL)
- default y
-
-config MEM_MT48H32M16LFCJ_75
- bool
- depends on (BFIN526_EZBRD)
- default y
-
-config MEM_MT47H64M16
- bool
- depends on (BFIN609_EZKIT)
- default y
-
-source "arch/blackfin/mach-bf518/Kconfig"
-source "arch/blackfin/mach-bf527/Kconfig"
-source "arch/blackfin/mach-bf533/Kconfig"
-source "arch/blackfin/mach-bf561/Kconfig"
-source "arch/blackfin/mach-bf537/Kconfig"
-source "arch/blackfin/mach-bf538/Kconfig"
-source "arch/blackfin/mach-bf548/Kconfig"
-source "arch/blackfin/mach-bf609/Kconfig"
-
-menu "Board customizations"
-
-config CMDLINE_BOOL
- bool "Default bootloader kernel arguments"
-
-config CMDLINE
- string "Initial kernel command string"
- depends on CMDLINE_BOOL
- default "console=ttyBF0,57600"
- help
- If you don't have a boot loader capable of passing a command line string
- to the kernel, you may specify one here. As a minimum, you should specify
- the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
-
-config BOOT_LOAD
- hex "Kernel load address for booting"
- default "0x1000"
- range 0x1000 0x20000000
- help
- This option allows you to set the load address of the kernel.
- This can be useful if you are on a board which has a small amount
- of memory or you wish to reserve some memory at the beginning of
- the address space.
-
- Note that you need to keep this value above 4k (0x1000) as this
- memory region is used to capture NULL pointer references as well
- as some core kernel functions.
-
-config PHY_RAM_BASE_ADDRESS
- hex "Physical RAM Base"
- default 0x0
- help
- set BF609 FPGA physical SRAM base address
-
-config ROM_BASE
- hex "Kernel ROM Base"
- depends on ROMKERNEL
- default "0x20040040"
- range 0x20000000 0x20400000 if !(BF54x || BF561 || BF60x)
- range 0x20000000 0x30000000 if (BF54x || BF561)
- range 0xB0000000 0xC0000000 if (BF60x)
- help
- Make sure your ROM base does not include any file-header
- information that is prepended to the kernel.
-
- For example, the bootable U-Boot format (created with
- mkimage) has a 64 byte header (0x40). So while the image
- you write to flash might start at say 0x20080000, you have
- to add 0x40 to get the kernel's ROM base as it will come
- after the header.
-
-comment "Clock/PLL Setup"
-
-config CLKIN_HZ
- int "Frequency of the crystal on the board in Hz"
- default "10000000" if BFIN532_IP0X
- default "11059200" if BFIN533_STAMP
- default "24576000" if PNAV10
- default "25000000" # most people use this
- default "27000000" if BFIN533_EZKIT
- default "30000000" if BFIN561_EZKIT
- default "24000000" if BFIN527_AD7160EVAL
- help
- The frequency of CLKIN crystal oscillator on the board in Hz.
- Warning: This value should match the crystal on the board. Otherwise,
- peripherals won't work properly.
-
-config BFIN_KERNEL_CLOCK
- bool "Re-program Clocks while Kernel boots?"
- default n
- help
- This option decides if kernel clocks are re-programed from the
- bootloader settings. If the clocks are not set, the SDRAM settings
- are also not changed, and the Bootloader does 100% of the hardware
- configuration.
-
-config PLL_BYPASS
- bool "Bypass PLL"
- depends on BFIN_KERNEL_CLOCK && (!BF60x)
- default n
-
-config CLKIN_HALF
- bool "Half Clock In"
- depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
- default n
- help
- If this is set the clock will be divided by 2, before it goes to the PLL.
-
-config VCO_MULT
- int "VCO Multiplier"
- depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
- range 1 64
- default "22" if BFIN533_EZKIT
- default "45" if BFIN533_STAMP
- default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
- default "22" if BFIN533_BLUETECHNIX_CM
- default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
- default "20" if (BFIN561_EZKIT || BF609)
- default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
- default "25" if BFIN527_AD7160EVAL
- help
- This controls the frequency of the on-chip PLL. This can be between 1 and 64.
- PLL Frequency = (Crystal Frequency) * (this setting)
-
-choice
- prompt "Core Clock Divider"
- depends on BFIN_KERNEL_CLOCK
- default CCLK_DIV_1
- help
- This sets the frequency of the core. It can be 1, 2, 4 or 8
- Core Frequency = (PLL frequency) / (this setting)
-
-config CCLK_DIV_1
- bool "1"
-
-config CCLK_DIV_2
- bool "2"
-
-config CCLK_DIV_4
- bool "4"
-
-config CCLK_DIV_8
- bool "8"
-endchoice
-
-config SCLK_DIV
- int "System Clock Divider"
- depends on BFIN_KERNEL_CLOCK
- range 1 15
- default 4
- help
- This sets the frequency of the system clock (including SDRAM or DDR) on
- !BF60x else it set the clock for system buses and provides the
- source from which SCLK0 and SCLK1 are derived.
- This can be between 1 and 15
- System Clock = (PLL frequency) / (this setting)
-
-config SCLK0_DIV
- int "System Clock0 Divider"
- depends on BFIN_KERNEL_CLOCK && BF60x
- range 1 15
- default 1
- help
- This sets the frequency of the system clock0 for PVP and all other
- peripherals not clocked by SCLK1.
- This can be between 1 and 15
- System Clock0 = (System Clock) / (this setting)
-
-config SCLK1_DIV
- int "System Clock1 Divider"
- depends on BFIN_KERNEL_CLOCK && BF60x
- range 1 15
- default 1
- help
- This sets the frequency of the system clock1 (including SPORT, SPI and ACM).
- This can be between 1 and 15
- System Clock1 = (System Clock) / (this setting)
-
-config DCLK_DIV
- int "DDR Clock Divider"
- depends on BFIN_KERNEL_CLOCK && BF60x
- range 1 15
- default 2
- help
- This sets the frequency of the DDR memory.
- This can be between 1 and 15
- DDR Clock = (PLL frequency) / (this setting)
-
-choice
- prompt "DDR SDRAM Chip Type"
- depends on BFIN_KERNEL_CLOCK
- depends on BF54x
- default MEM_MT46V32M16_5B
-
-config MEM_MT46V32M16_6T
- bool "MT46V32M16_6T"
-
-config MEM_MT46V32M16_5B
- bool "MT46V32M16_5B"
-endchoice
-
-choice
- prompt "DDR/SDRAM Timing"
- depends on BFIN_KERNEL_CLOCK && !BF60x
- default BFIN_KERNEL_CLOCK_MEMINIT_CALC
- help
- This option allows you to specify Blackfin SDRAM/DDR Timing parameters
- The calculated SDRAM timing parameters may not be 100%
- accurate - This option is therefore marked experimental.
-
-config BFIN_KERNEL_CLOCK_MEMINIT_CALC
- bool "Calculate Timings"
-
-config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
- bool "Provide accurate Timings based on target SCLK"
- help
- Please consult the Blackfin Hardware Reference Manuals as well
- as the memory device datasheet.
- http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
-endchoice
-
-menu "Memory Init Control"
- depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
-
-config MEM_DDRCTL0
- depends on BF54x
- hex "DDRCTL0"
- default 0x0
-
-config MEM_DDRCTL1
- depends on BF54x
- hex "DDRCTL1"
- default 0x0
-
-config MEM_DDRCTL2
- depends on BF54x
- hex "DDRCTL2"
- default 0x0
-
-config MEM_EBIU_DDRQUE
- depends on BF54x
- hex "DDRQUE"
- default 0x0
-
-config MEM_SDRRC
- depends on !BF54x
- hex "SDRRC"
- default 0x0
-
-config MEM_SDGCTL
- depends on !BF54x
- hex "SDGCTL"
- default 0x0
-endmenu
-
-#
-# Max & Min Speeds for various Chips
-#
-config MAX_VCO_HZ
- int
- default 400000000 if BF512
- default 400000000 if BF514
- default 400000000 if BF516
- default 400000000 if BF518
- default 400000000 if BF522
- default 600000000 if BF523
- default 400000000 if BF524
- default 600000000 if BF525
- default 400000000 if BF526
- default 600000000 if BF527
- default 400000000 if BF531
- default 400000000 if BF532
- default 750000000 if BF533
- default 500000000 if BF534
- default 400000000 if BF536
- default 600000000 if BF537
- default 533333333 if BF538
- default 533333333 if BF539
- default 600000000 if BF542
- default 533333333 if BF544
- default 600000000 if BF547
- default 600000000 if BF548
- default 533333333 if BF549
- default 600000000 if BF561
- default 800000000 if BF609
-
-config MIN_VCO_HZ
- int
- default 50000000
-
-config MAX_SCLK_HZ
- int
- default 200000000 if BF609
- default 133333333
-
-config MIN_SCLK_HZ
- int
- default 27000000
-
-comment "Kernel Timer/Scheduler"
-
-source kernel/Kconfig.hz
-
-config SET_GENERIC_CLOCKEVENTS
- bool "Generic clock events"
- default y
- select GENERIC_CLOCKEVENTS
-
-menu "Clock event device"
- depends on GENERIC_CLOCKEVENTS
-config TICKSOURCE_GPTMR0
- bool "GPTimer0"
- depends on !SMP
- select BFIN_GPTIMERS
-
-config TICKSOURCE_CORETMR
- bool "Core timer"
- default y
-endmenu
-
-menu "Clock source"
- depends on GENERIC_CLOCKEVENTS
-config CYCLES_CLOCKSOURCE
- bool "CYCLES"
- default y
- depends on !BFIN_SCRATCH_REG_CYCLES
- depends on !SMP
- help
- If you say Y here, you will enable support for using the 'cycles'
- registers as a clock source. Doing so means you will be unable to
- safely write to the 'cycles' register during runtime. You will
- still be able to read it (such as for performance monitoring), but
- writing the registers will most likely crash the kernel.
-
-config GPTMR0_CLOCKSOURCE
- bool "GPTimer0"
- select BFIN_GPTIMERS
- depends on !TICKSOURCE_GPTMR0
-endmenu
-
-comment "Misc"
-
-choice
- prompt "Blackfin Exception Scratch Register"
- default BFIN_SCRATCH_REG_RETN
- help
- Select the resource to reserve for the Exception handler:
- - RETN: Non-Maskable Interrupt (NMI)
- - RETE: Exception Return (JTAG/ICE)
- - CYCLES: Performance counter
-
- If you are unsure, please select "RETN".
-
-config BFIN_SCRATCH_REG_RETN
- bool "RETN"
- help
- Use the RETN register in the Blackfin exception handler
- as a stack scratch register. This means you cannot
- safely use NMI on the Blackfin while running Linux, but
- you can debug the system with a JTAG ICE and use the
- CYCLES performance registers.
-
- If you are unsure, please select "RETN".
-
-config BFIN_SCRATCH_REG_RETE
- bool "RETE"
- help
- Use the RETE register in the Blackfin exception handler
- as a stack scratch register. This means you cannot
- safely use a JTAG ICE while debugging a Blackfin board,
- but you can safely use the CYCLES performance registers
- and the NMI.
-
- If you are unsure, please select "RETN".
-
-config BFIN_SCRATCH_REG_CYCLES
- bool "CYCLES"
- help
- Use the CYCLES register in the Blackfin exception handler
- as a stack scratch register. This means you cannot
- safely use the CYCLES performance registers on a Blackfin
- board at anytime, but you can debug the system with a JTAG
- ICE and use the NMI.
-
- If you are unsure, please select "RETN".
-
-endchoice
-
-endmenu
-
-
-menu "Blackfin Kernel Optimizations"
-
-comment "Memory Optimizations"
-
-config I_ENTRY_L1
- bool "Locate interrupt entry code in L1 Memory"
- default y
- depends on !SMP
- help
- If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
- into L1 instruction memory. (less latency)
-
-config EXCPT_IRQ_SYSC_L1
- bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
- default y
- depends on !SMP
- help
- If enabled, the entire ASM lowlevel exception and interrupt entry code
- (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
- (less latency)
-
-config DO_IRQ_L1
- bool "Locate frequently called do_irq dispatcher function in L1 Memory"
- default y
- depends on !SMP
- help
- If enabled, the frequently called do_irq dispatcher function is linked
- into L1 instruction memory. (less latency)
-
-config CORE_TIMER_IRQ_L1
- bool "Locate frequently called timer_interrupt() function in L1 Memory"
- default y
- depends on !SMP
- help
- If enabled, the frequently called timer_interrupt() function is linked
- into L1 instruction memory. (less latency)
-
-config IDLE_L1
- bool "Locate frequently idle function in L1 Memory"
- default y
- depends on !SMP
- help
- If enabled, the frequently called idle function is linked
- into L1 instruction memory. (less latency)
-
-config SCHEDULE_L1
- bool "Locate kernel schedule function in L1 Memory"
- default y
- depends on !SMP
- help
- If enabled, the frequently called kernel schedule is linked
- into L1 instruction memory. (less latency)
-
-config ARITHMETIC_OPS_L1
- bool "Locate kernel owned arithmetic functions in L1 Memory"
- default y
- depends on !SMP
- help
- If enabled, arithmetic functions are linked
- into L1 instruction memory. (less latency)
-
-config ACCESS_OK_L1
- bool "Locate access_ok function in L1 Memory"
- default y
- depends on !SMP
- help
- If enabled, the access_ok function is linked
- into L1 instruction memory. (less latency)
-
-config MEMSET_L1
- bool "Locate memset function in L1 Memory"
- default y
- depends on !SMP
- help
- If enabled, the memset function is linked
- into L1 instruction memory. (less latency)
-
-config MEMCPY_L1
- bool "Locate memcpy function in L1 Memory"
- default y
- depends on !SMP
- help
- If enabled, the memcpy function is linked
- into L1 instruction memory. (less latency)
-
-config STRCMP_L1
- bool "locate strcmp function in L1 Memory"
- default y
- depends on !SMP
- help
- If enabled, the strcmp function is linked
- into L1 instruction memory (less latency).
-
-config STRNCMP_L1
- bool "locate strncmp function in L1 Memory"
- default y
- depends on !SMP
- help
- If enabled, the strncmp function is linked
- into L1 instruction memory (less latency).
-
-config STRCPY_L1
- bool "locate strcpy function in L1 Memory"
- default y
- depends on !SMP
- help
- If enabled, the strcpy function is linked
- into L1 instruction memory (less latency).
-
-config STRNCPY_L1
- bool "locate strncpy function in L1 Memory"
- default y
- depends on !SMP
- help
- If enabled, the strncpy function is linked
- into L1 instruction memory (less latency).
-
-config SYS_BFIN_SPINLOCK_L1
- bool "Locate sys_bfin_spinlock function in L1 Memory"
- default y
- depends on !SMP
- help
- If enabled, sys_bfin_spinlock function is linked
- into L1 instruction memory. (less latency)
-
-config CACHELINE_ALIGNED_L1
- bool "Locate cacheline_aligned data to L1 Data Memory"
- default y if !BF54x
- default n if BF54x
- depends on !SMP && !BF531 && !CRC32
- help
- If enabled, cacheline_aligned data is linked
- into L1 data memory. (less latency)
-
-config SYSCALL_TAB_L1
- bool "Locate Syscall Table L1 Data Memory"
- default n
- depends on !SMP && !BF531
- help
- If enabled, the Syscall LUT is linked
- into L1 data memory. (less latency)
-
-config CPLB_SWITCH_TAB_L1
- bool "Locate CPLB Switch Tables L1 Data Memory"
- default n
- depends on !SMP && !BF531
- help
- If enabled, the CPLB Switch Tables are linked
- into L1 data memory. (less latency)
-
-config ICACHE_FLUSH_L1
- bool "Locate icache flush funcs in L1 Inst Memory"
- default y
- help
- If enabled, the Blackfin icache flushing functions are linked
- into L1 instruction memory.
-
- Note that this might be required to address anomalies, but
- these functions are pretty small, so it shouldn't be too bad.
- If you are using a processor affected by an anomaly, the build
- system will double check for you and prevent it.
-
-config DCACHE_FLUSH_L1
- bool "Locate dcache flush funcs in L1 Inst Memory"
- default y
- depends on !SMP
- help
- If enabled, the Blackfin dcache flushing functions are linked
- into L1 instruction memory.
-
-config APP_STACK_L1
- bool "Support locating application stack in L1 Scratch Memory"
- default y
- depends on !SMP
- help
- If enabled the application stack can be located in L1
- scratch memory (less latency).
-
- Currently only works with FLAT binaries.
-
-config EXCEPTION_L1_SCRATCH
- bool "Locate exception stack in L1 Scratch Memory"
- default n
- depends on !SMP && !APP_STACK_L1
- help
- Whenever an exception occurs, use the L1 Scratch memory for
- stack storage. You cannot place the stacks of FLAT binaries
- in L1 when using this option.
-
- If you don't use L1 Scratch, then you should say Y here.
-
-comment "Speed Optimizations"
-config BFIN_INS_LOWOVERHEAD
- bool "ins[bwl] low overhead, higher interrupt latency"
- default y
- depends on !SMP
- help
- Reads on the Blackfin are speculative. In Blackfin terms, this means
- they can be interrupted at any time (even after they have been issued
- on to the external bus), and re-issued after the interrupt occurs.
- For memory - this is not a big deal, since memory does not change if
- it sees a read.
-
- If a FIFO is sitting on the end of the read, it will see two reads,
- when the core only sees one since the FIFO receives both the read
- which is cancelled (and not delivered to the core) and the one which
- is re-issued (which is delivered to the core).
-
- To solve this, interrupts are turned off before reads occur to
- I/O space. This option controls which the overhead/latency of
- controlling interrupts during this time
- "n" turns interrupts off every read
- (higher overhead, but lower interrupt latency)
- "y" turns interrupts off every loop
- (low overhead, but longer interrupt latency)
-
- default behavior is to leave this set to on (type "Y"). If you are experiencing
- interrupt latency issues, it is safe and OK to turn this off.
-
-endmenu
-
-choice
- prompt "Kernel executes from"
- help
- Choose the memory type that the kernel will be running in.
-
-config RAMKERNEL
- bool "RAM"
- help
- The kernel will be resident in RAM when running.
-
-config ROMKERNEL
- bool "ROM"
- help
- The kernel will be resident in FLASH/ROM when running.
-
-endchoice
-
-# Common code uses "ROMKERNEL" or "XIP_KERNEL", so define both
-config XIP_KERNEL
- bool
- default y
- depends on ROMKERNEL
-
-source "mm/Kconfig"
-
-config BFIN_GPTIMERS
- tristate "Enable Blackfin General Purpose Timers API"
- default n
- help
- Enable support for the General Purpose Timers API. If you
- are unsure, say N.
-
- To compile this driver as a module, choose M here: the module
- will be called gptimers.
-
-choice
- prompt "Uncached DMA region"
- default DMA_UNCACHED_1M
-config DMA_UNCACHED_32M
- bool "Enable 32M DMA region"
-config DMA_UNCACHED_16M
- bool "Enable 16M DMA region"
-config DMA_UNCACHED_8M
- bool "Enable 8M DMA region"
-config DMA_UNCACHED_4M
- bool "Enable 4M DMA region"
-config DMA_UNCACHED_2M
- bool "Enable 2M DMA region"
-config DMA_UNCACHED_1M
- bool "Enable 1M DMA region"
-config DMA_UNCACHED_512K
- bool "Enable 512K DMA region"
-config DMA_UNCACHED_256K
- bool "Enable 256K DMA region"
-config DMA_UNCACHED_128K
- bool "Enable 128K DMA region"
-config DMA_UNCACHED_NONE
- bool "Disable DMA region"
-endchoice
-
-
-comment "Cache Support"
-
-config BFIN_ICACHE
- bool "Enable ICACHE"
- default y
-config BFIN_EXTMEM_ICACHEABLE
- bool "Enable ICACHE for external memory"
- depends on BFIN_ICACHE
- default y
-config BFIN_L2_ICACHEABLE
- bool "Enable ICACHE for L2 SRAM"
- depends on BFIN_ICACHE
- depends on (BF54x || BF561 || BF60x) && !SMP
- default n
-
-config BFIN_DCACHE
- bool "Enable DCACHE"
- default y
-config BFIN_DCACHE_BANKA
- bool "Enable only 16k BankA DCACHE - BankB is SRAM"
- depends on BFIN_DCACHE && !BF531
- default n
-config BFIN_EXTMEM_DCACHEABLE
- bool "Enable DCACHE for external memory"
- depends on BFIN_DCACHE
- default y
-choice
- prompt "External memory DCACHE policy"
- depends on BFIN_EXTMEM_DCACHEABLE
- default BFIN_EXTMEM_WRITEBACK if !SMP
- default BFIN_EXTMEM_WRITETHROUGH if SMP
-config BFIN_EXTMEM_WRITEBACK
- bool "Write back"
- depends on !SMP
- help
- Write Back Policy:
- Cached data will be written back to SDRAM only when needed.
- This can give a nice increase in performance, but beware of
- broken drivers that do not properly invalidate/flush their
- cache.
-
- Write Through Policy:
- Cached data will always be written back to SDRAM when the
- cache is updated. This is a completely safe setting, but
- performance is worse than Write Back.
-
- If you are unsure of the options and you want to be safe,
- then go with Write Through.
-
-config BFIN_EXTMEM_WRITETHROUGH
- bool "Write through"
- help
- Write Back Policy:
- Cached data will be written back to SDRAM only when needed.
- This can give a nice increase in performance, but beware of
- broken drivers that do not properly invalidate/flush their
- cache.
-
- Write Through Policy:
- Cached data will always be written back to SDRAM when the
- cache is updated. This is a completely safe setting, but
- performance is worse than Write Back.
-
- If you are unsure of the options and you want to be safe,
- then go with Write Through.
-
-endchoice
-
-config BFIN_L2_DCACHEABLE
- bool "Enable DCACHE for L2 SRAM"
- depends on BFIN_DCACHE
- depends on (BF54x || BF561 || BF60x) && !SMP
- default n
-choice
- prompt "L2 SRAM DCACHE policy"
- depends on BFIN_L2_DCACHEABLE
- default BFIN_L2_WRITEBACK
-config BFIN_L2_WRITEBACK
- bool "Write back"
-
-config BFIN_L2_WRITETHROUGH
- bool "Write through"
-endchoice
-
-
-comment "Memory Protection Unit"
-config MPU
- bool "Enable the memory protection unit"
- default n
- help
- Use the processor's MPU to protect applications from accessing
- memory they do not own. This comes at a performance penalty
- and is recommended only for debugging.
-
-comment "Asynchronous Memory Configuration"
-
-menu "EBIU_AMGCTL Global Control"
- depends on !BF60x
-config C_AMCKEN
- bool "Enable CLKOUT"
- default y
-
-config C_CDPRIO
- bool "DMA has priority over core for ext. accesses"
- default n
-
-config C_B0PEN
- depends on BF561
- bool "Bank 0 16 bit packing enable"
- default y
-
-config C_B1PEN
- depends on BF561
- bool "Bank 1 16 bit packing enable"
- default y
-
-config C_B2PEN
- depends on BF561
- bool "Bank 2 16 bit packing enable"
- default y
-
-config C_B3PEN
- depends on BF561
- bool "Bank 3 16 bit packing enable"
- default n
-
-choice
- prompt "Enable Asynchronous Memory Banks"
- default C_AMBEN_ALL
-
-config C_AMBEN
- bool "Disable All Banks"
-
-config C_AMBEN_B0
- bool "Enable Bank 0"
-
-config C_AMBEN_B0_B1
- bool "Enable Bank 0 & 1"
-
-config C_AMBEN_B0_B1_B2
- bool "Enable Bank 0 & 1 & 2"
-
-config C_AMBEN_ALL
- bool "Enable All Banks"
-endchoice
-endmenu
-
-menu "EBIU_AMBCTL Control"
- depends on !BF60x
-config BANK_0
- hex "Bank 0 (AMBCTL0.L)"
- default 0x7BB0
- help
- These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
- used to control the Asynchronous Memory Bank 0 settings.
-
-config BANK_1
- hex "Bank 1 (AMBCTL0.H)"
- default 0x7BB0
- default 0x5558 if BF54x
- help
- These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
- used to control the Asynchronous Memory Bank 1 settings.
-
-config BANK_2
- hex "Bank 2 (AMBCTL1.L)"
- default 0x7BB0
- help
- These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
- used to control the Asynchronous Memory Bank 2 settings.
-
-config BANK_3
- hex "Bank 3 (AMBCTL1.H)"
- default 0x99B3
- help
- These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
- used to control the Asynchronous Memory Bank 3 settings.
-
-endmenu
-
-config EBIU_MBSCTLVAL
- hex "EBIU Bank Select Control Register"
- depends on BF54x
- default 0
-
-config EBIU_MODEVAL
- hex "Flash Memory Mode Control Register"
- depends on BF54x
- default 1
-
-config EBIU_FCTLVAL
- hex "Flash Memory Bank Control Register"
- depends on BF54x
- default 6
-endmenu
-
-#############################################################################
-menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
-
-config PCI
- bool "PCI support"
- depends on BROKEN
- help
- Support for PCI bus.
-
-source "drivers/pci/Kconfig"
-
-source "drivers/pcmcia/Kconfig"
-
-endmenu
-
-menu "Executable file formats"
-
-source "fs/Kconfig.binfmt"
-
-endmenu
-
-menu "Power management options"
-
-source "kernel/power/Kconfig"
-
-config ARCH_SUSPEND_POSSIBLE
- def_bool y
-
-choice
- prompt "Standby Power Saving Mode"
- depends on PM && !BF60x
- default PM_BFIN_SLEEP_DEEPER
-config PM_BFIN_SLEEP_DEEPER
- bool "Sleep Deeper"
- help
- Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
- power dissipation by disabling the clock to the processor core (CCLK).
- Furthermore, Standby sets the internal power supply voltage (VDDINT)
- to 0.85 V to provide the greatest power savings, while preserving the
- processor state.
- The PLL and system clock (SCLK) continue to operate at a very low
- frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
- the SDRAM is put into Self Refresh Mode. Typically an external event
- such as GPIO interrupt or RTC activity wakes up the processor.
- Various Peripherals such as UART, SPORT, PPI may not function as
- normal during Sleep Deeper, due to the reduced SCLK frequency.
- When in the sleep mode, system DMA access to L1 memory is not supported.
-
- If unsure, select "Sleep Deeper".
-
-config PM_BFIN_SLEEP
- bool "Sleep"
- help
- Sleep Mode (High Power Savings) - The sleep mode reduces power
- dissipation by disabling the clock to the processor core (CCLK).
- The PLL and system clock (SCLK), however, continue to operate in
- this mode. Typically an external event or RTC activity will wake
- up the processor. When in the sleep mode, system DMA access to L1
- memory is not supported.
-
- If unsure, select "Sleep Deeper".
-endchoice
-
-comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
- depends on PM
-
-config PM_BFIN_WAKE_PH6
- bool "Allow Wake-Up from on-chip PHY or PH6 GP"
- depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
- default n
- help
- Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
-
-config PM_BFIN_WAKE_GP
- bool "Allow Wake-Up from GPIOs"
- depends on PM && BF54x
- default n
- help
- Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
- (all processors, except ADSP-BF549). This option sets
- the general-purpose wake-up enable (GPWE) control bit to enable
- wake-up upon detection of an active low signal on the /GPW (PH7) pin.
- On ADSP-BF549 this option enables the same functionality on the
- /MRXON pin also PH7.
-
-config PM_BFIN_WAKE_PA15
- bool "Allow Wake-Up from PA15"
- depends on PM && BF60x
- default n
- help
- Enable PA15 Wake-Up
-
-config PM_BFIN_WAKE_PA15_POL
- int "Wake-up priority"
- depends on PM_BFIN_WAKE_PA15
- default 0
- help
- Wake-Up priority 0(low) 1(high)
-
-config PM_BFIN_WAKE_PB15
- bool "Allow Wake-Up from PB15"
- depends on PM && BF60x
- default n
- help
- Enable PB15 Wake-Up
-
-config PM_BFIN_WAKE_PB15_POL
- int "Wake-up priority"
- depends on PM_BFIN_WAKE_PB15
- default 0
- help
- Wake-Up priority 0(low) 1(high)
-
-config PM_BFIN_WAKE_PC15
- bool "Allow Wake-Up from PC15"
- depends on PM && BF60x
- default n
- help
- Enable PC15 Wake-Up
-
-config PM_BFIN_WAKE_PC15_POL
- int "Wake-up priority"
- depends on PM_BFIN_WAKE_PC15
- default 0
- help
- Wake-Up priority 0(low) 1(high)
-
-config PM_BFIN_WAKE_PD06
- bool "Allow Wake-Up from PD06(ETH0_PHYINT)"
- depends on PM && BF60x
- default n
- help
- Enable PD06(ETH0_PHYINT) Wake-up
-
-config PM_BFIN_WAKE_PD06_POL
- int "Wake-up priority"
- depends on PM_BFIN_WAKE_PD06
- default 0
- help
- Wake-Up priority 0(low) 1(high)
-
-config PM_BFIN_WAKE_PE12
- bool "Allow Wake-Up from PE12(ETH1_PHYINT, PUSH BUTTON)"
- depends on PM && BF60x
- default n
- help
- Enable PE12(ETH1_PHYINT, PUSH BUTTON) Wake-up
-
-config PM_BFIN_WAKE_PE12_POL
- int "Wake-up priority"
- depends on PM_BFIN_WAKE_PE12
- default 0
- help
- Wake-Up priority 0(low) 1(high)
-
-config PM_BFIN_WAKE_PG04
- bool "Allow Wake-Up from PG04(CAN0_RX)"
- depends on PM && BF60x
- default n
- help
- Enable PG04(CAN0_RX) Wake-up
-
-config PM_BFIN_WAKE_PG04_POL
- int "Wake-up priority"
- depends on PM_BFIN_WAKE_PG04
- default 0
- help
- Wake-Up priority 0(low) 1(high)
-
-config PM_BFIN_WAKE_PG13
- bool "Allow Wake-Up from PG13"
- depends on PM && BF60x
- default n
- help
- Enable PG13 Wake-Up
-
-config PM_BFIN_WAKE_PG13_POL
- int "Wake-up priority"
- depends on PM_BFIN_WAKE_PG13
- default 0
- help
- Wake-Up priority 0(low) 1(high)
-
-config PM_BFIN_WAKE_USB
- bool "Allow Wake-Up from (USB)"
- depends on PM && BF60x
- default n
- help
- Enable (USB) Wake-up
-
-config PM_BFIN_WAKE_USB_POL
- int "Wake-up priority"
- depends on PM_BFIN_WAKE_USB
- default 0
- help
- Wake-Up priority 0(low) 1(high)
-
-endmenu
-
-menu "CPU Frequency scaling"
-
-source "drivers/cpufreq/Kconfig"
-
-config BFIN_CPU_FREQ
- bool
- depends on CPU_FREQ
- default y
-
-config CPU_VOLTAGE
- bool "CPU Voltage scaling"
- depends on CPU_FREQ
- default n
- help
- Say Y here if you want CPU voltage scaling according to the CPU frequency.
- This option violates the PLL BYPASS recommendation in the Blackfin Processor
- manuals. There is a theoretical risk that during VDDINT transitions
- the PLL may unlock.
-
-endmenu
-
-source "net/Kconfig"
-
-source "drivers/Kconfig"
-
-source "drivers/firmware/Kconfig"
-
-source "fs/Kconfig"
-
-source "arch/blackfin/Kconfig.debug"
-
-source "security/Kconfig"
-
-source "crypto/Kconfig"
-
-source "lib/Kconfig"
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0
-menu "Kernel hacking"
-
-source "lib/Kconfig.debug"
-
-config DEBUG_VERBOSE
- bool "Verbose fault messages"
- default y
- select PRINTK
- help
- When a program crashes due to an exception, or the kernel detects
- an internal error, the kernel can print a not so brief message
- explaining what the problem was. This debugging information is
- useful to developers and kernel hackers when tracking down problems,
- but mostly meaningless to other people. This is always helpful for
- debugging but serves no purpose on a production system.
- Most people should say N here.
-
-config DEBUG_MMRS
- tristate "Generate Blackfin MMR tree"
- depends on !PINCTRL
- select DEBUG_FS
- help
- Create a tree of Blackfin MMRs via the debugfs tree. If
- you enable this, you will find all MMRs laid out in the
- /sys/kernel/debug/blackfin/ directory where you can read/write
- MMRs directly from userspace. This is obviously just a debug
- feature.
-
-config DEBUG_HWERR
- bool "Hardware error interrupt debugging"
- depends on DEBUG_KERNEL
- help
- When enabled, the hardware error interrupt is never disabled, and
- will happen immediately when an error condition occurs. This comes
- at a slight cost in code size, but is necessary if you are getting
- hardware error interrupts and need to know where they are coming
- from.
-
-config EXACT_HWERR
- bool "Try to make Hardware errors exact"
- depends on DEBUG_HWERR
- help
- By default, the Blackfin hardware errors are not exact - the error
- be reported multiple cycles after the error happens. This delay
- can cause the wrong application, or even the kernel to receive a
- signal to be killed. If you are getting HW errors in your system,
- try turning this on to ensure they are at least coming from the
- proper thread.
-
- On production systems, it is safe (and a small optimization) to say N.
-
-config DEBUG_DOUBLEFAULT
- bool "Debug Double Faults"
- default n
- help
- If an exception is caused while executing code within the exception
- handler, the NMI handler, the reset vector, or in emulator mode,
- a double fault occurs. On the Blackfin, this is a unrecoverable
- event. You have two options:
- - RESET exactly when double fault occurs. The excepting
- instruction address is stored in RETX, where the next kernel
- boot will print it out.
- - Print debug message. This is much more error prone, although
- easier to handle. It is error prone since:
- - The excepting instruction is not committed.
- - All writebacks from the instruction are prevented.
- - The generated exception is not taken.
- - The EXCAUSE field is updated with an unrecoverable event
- The only way to check this is to see if EXCAUSE contains the
- unrecoverable event value at every exception return. By selecting
- this option, you are skipping over the faulting instruction, and
- hoping things stay together enough to print out a debug message.
-
- This does add a little kernel code, but is the only method to debug
- double faults - if unsure say "Y"
-
-choice
- prompt "Double Fault Failure Method"
- default DEBUG_DOUBLEFAULT_PRINT
- depends on DEBUG_DOUBLEFAULT
-
-config DEBUG_DOUBLEFAULT_PRINT
- bool "Print"
-
-config DEBUG_DOUBLEFAULT_RESET
- bool "Reset"
-
-endchoice
-
-config DEBUG_HUNT_FOR_ZERO
- bool "Catch NULL pointer reads/writes"
- default y
- help
- Say Y here to catch reads/writes to anywhere in the memory range
- from 0x0000 - 0x0FFF (the first 4k) of memory. This is useful in
- catching common programming errors such as NULL pointer dereferences.
-
- Misbehaving applications will be killed (generate a SEGV) while the
- kernel will trigger a panic.
-
- Enabling this option will take up an extra entry in CPLB table.
- Otherwise, there is no extra overhead.
-
-config DEBUG_BFIN_HWTRACE_ON
- bool "Turn on Blackfin's Hardware Trace"
- default y
- help
- All Blackfins include a Trace Unit which stores a history of the last
- 16 changes in program flow taken by the program sequencer. The history
- allows the user to recreate the program sequencer’s recent path. This
- can be handy when an application dies - we print out the execution
- path of how it got to the offending instruction.
-
- By turning this off, you may save a tiny amount of power.
-
-choice
- prompt "Omit loop Tracing"
- default DEBUG_BFIN_HWTRACE_COMPRESSION_OFF
- depends on DEBUG_BFIN_HWTRACE_ON
- help
- The trace buffer can be configured to omit recording of changes in
- program flow that match either the last entry or one of the last
- two entries. Omitting one of these entries from the record prevents
- the trace buffer from overflowing because of any sort of loop (for, do
- while, etc) in the program.
-
- Because zero-overhead Hardware loops are not recorded in the trace buffer,
- this feature can be used to prevent trace overflow from loops that
- are nested four deep.
-
-config DEBUG_BFIN_HWTRACE_COMPRESSION_OFF
- bool "Trace all Loops"
- help
- The trace buffer records all changes of flow
-
-config DEBUG_BFIN_HWTRACE_COMPRESSION_ONE
- bool "Compress single-level loops"
- help
- The trace buffer does not record single loops - helpful if trace
- is spinning on a while or do loop.
-
-config DEBUG_BFIN_HWTRACE_COMPRESSION_TWO
- bool "Compress two-level loops"
- help
- The trace buffer does not record loops two levels deep. Helpful if
- the trace is spinning in a nested loop
-
-endchoice
-
-config DEBUG_BFIN_HWTRACE_COMPRESSION
- int
- depends on DEBUG_BFIN_HWTRACE_ON
- default 0 if DEBUG_BFIN_HWTRACE_COMPRESSION_OFF
- default 1 if DEBUG_BFIN_HWTRACE_COMPRESSION_ONE
- default 2 if DEBUG_BFIN_HWTRACE_COMPRESSION_TWO
-
-
-config DEBUG_BFIN_HWTRACE_EXPAND
- bool "Expand Trace Buffer greater than 16 entries"
- depends on DEBUG_BFIN_HWTRACE_ON
- default n
- help
- By selecting this option, every time the 16 hardware entries in
- the Blackfin's HW Trace buffer are full, the kernel will move them
- into a software buffer, for dumping when there is an issue. This
- has a great impact on performance, (an interrupt every 16 change of
- flows) and should normally be turned off, except in those nasty
- debugging sessions
-
-config DEBUG_BFIN_HWTRACE_EXPAND_LEN
- int "Size of Trace buffer (in power of 2k)"
- range 0 4
- depends on DEBUG_BFIN_HWTRACE_EXPAND
- default 1
- help
- This sets the size of the software buffer that the trace information
- is kept in.
- 0 for (2^0) 1k, or 256 entries,
- 1 for (2^1) 2k, or 512 entries,
- 2 for (2^2) 4k, or 1024 entries,
- 3 for (2^3) 8k, or 2048 entries,
- 4 for (2^4) 16k, or 4096 entries
-
-config DEBUG_BFIN_NO_KERN_HWTRACE
- bool "Turn off hwtrace in CPLB handlers"
- depends on DEBUG_BFIN_HWTRACE_ON
- default y
- help
- The CPLB error handler contains a lot of flow changes which can
- quickly fill up the hardware trace buffer. When debugging crashes,
- the hardware trace may indicate that the problem lies in kernel
- space when in reality an application is buggy.
-
- Say Y here to disable hardware tracing in some known "jumpy" pieces
- of code so that the trace buffer will extend further back.
-
-config EARLY_PRINTK
- bool "Early printk"
- default n
- select SERIAL_CORE_CONSOLE
- help
- This option enables special console drivers which allow the kernel
- to print messages very early in the bootup process.
-
- This is useful for kernel debugging when your machine crashes very
- early before the console code is initialized. After enabling this
- feature, you must add "earlyprintk=serial,uart0,57600" to the
- command line (bootargs). It is safe to say Y here in all cases, as
- all of this lives in the init section and is thrown away after the
- kernel boots completely.
-
-config NMI_WATCHDOG
- bool "Enable NMI watchdog to help debugging lockup on SMP"
- default n
- depends on SMP
- help
- If any CPU in the system does not execute the period local timer
- interrupt for more than 5 seconds, then the NMI handler dumps debug
- information. This information can be used to debug the lockup.
-
-config CPLB_INFO
- bool "Display the CPLB information"
- help
- Display the CPLB information via /proc/cplbinfo.
-
-config ACCESS_CHECK
- bool "Check the user pointer address"
- default y
- help
- Usually the pointer transfer from user space is checked to see if its
- address is in the kernel space.
-
- Say N here to disable that check to improve the performance.
-
-config BFIN_ISRAM_SELF_TEST
- bool "isram boot self tests"
- default n
- help
- Run some self tests of the isram driver code at boot.
-
-config BFIN_PSEUDODBG_INSNS
- bool "Support pseudo debug instructions"
- default n
- help
- This option allows the kernel to emulate some pseudo instructions which
- allow simulator test cases to be run under Linux with no changes.
-
- Most people should say N here.
-
-config BFIN_PM_WAKEUP_TIME_BENCH
- bool "Display the total time for kernel to resume from power saving mode"
- default n
- help
- Display the total time when kernel resumes normal from standby or
- suspend to mem mode.
-
-endmenu
+++ /dev/null
-#
-# arch/blackfin/Makefile
-#
-# This file is subject to the terms and conditions of the GNU General Public
-# License. See the file "COPYING" in the main directory of this archive
-# for more details.
-#
-
-ifeq ($(CROSS_COMPILE),)
-CROSS_COMPILE := bfin-uclinux-
-endif
-LDFLAGS_vmlinux := -X
-OBJCOPYFLAGS := -O binary -R .note -R .comment -S
-GZFLAGS := -9
-
-KBUILD_CFLAGS += $(call cc-option,-mno-fdpic)
-ifeq ($(CONFIG_ROMKERNEL),y)
-KBUILD_CFLAGS += -mlong-calls
-endif
-KBUILD_AFLAGS += $(call cc-option,-mno-fdpic)
-KBUILD_CFLAGS_MODULE += -mlong-calls
-LDFLAGS += -m elf32bfin
-
-KBUILD_DEFCONFIG := BF537-STAMP_defconfig
-
-# setup the machine name and the machine dependent settings
-machine-$(CONFIG_BF512) := bf518
-machine-$(CONFIG_BF514) := bf518
-machine-$(CONFIG_BF516) := bf518
-machine-$(CONFIG_BF518) := bf518
-machine-$(CONFIG_BF522) := bf527
-machine-$(CONFIG_BF523) := bf527
-machine-$(CONFIG_BF524) := bf527
-machine-$(CONFIG_BF525) := bf527
-machine-$(CONFIG_BF526) := bf527
-machine-$(CONFIG_BF527) := bf527
-machine-$(CONFIG_BF531) := bf533
-machine-$(CONFIG_BF532) := bf533
-machine-$(CONFIG_BF533) := bf533
-machine-$(CONFIG_BF534) := bf537
-machine-$(CONFIG_BF536) := bf537
-machine-$(CONFIG_BF537) := bf537
-machine-$(CONFIG_BF538) := bf538
-machine-$(CONFIG_BF539) := bf538
-machine-$(CONFIG_BF542) := bf548
-machine-$(CONFIG_BF542M) := bf548
-machine-$(CONFIG_BF544) := bf548
-machine-$(CONFIG_BF544M) := bf548
-machine-$(CONFIG_BF547) := bf548
-machine-$(CONFIG_BF547M) := bf548
-machine-$(CONFIG_BF548) := bf548
-machine-$(CONFIG_BF548M) := bf548
-machine-$(CONFIG_BF549) := bf548
-machine-$(CONFIG_BF549M) := bf548
-machine-$(CONFIG_BF561) := bf561
-machine-$(CONFIG_BF609) := bf609
-MACHINE := $(machine-y)
-export MACHINE
-
-cpu-$(CONFIG_BF512) := bf512
-cpu-$(CONFIG_BF514) := bf514
-cpu-$(CONFIG_BF516) := bf516
-cpu-$(CONFIG_BF518) := bf518
-cpu-$(CONFIG_BF522) := bf522
-cpu-$(CONFIG_BF523) := bf523
-cpu-$(CONFIG_BF524) := bf524
-cpu-$(CONFIG_BF525) := bf525
-cpu-$(CONFIG_BF526) := bf526
-cpu-$(CONFIG_BF527) := bf527
-cpu-$(CONFIG_BF531) := bf531
-cpu-$(CONFIG_BF532) := bf532
-cpu-$(CONFIG_BF533) := bf533
-cpu-$(CONFIG_BF534) := bf534
-cpu-$(CONFIG_BF536) := bf536
-cpu-$(CONFIG_BF537) := bf537
-cpu-$(CONFIG_BF538) := bf538
-cpu-$(CONFIG_BF539) := bf539
-cpu-$(CONFIG_BF542) := bf542
-cpu-$(CONFIG_BF542M) := bf542m
-cpu-$(CONFIG_BF544) := bf544
-cpu-$(CONFIG_BF544M) := bf544m
-cpu-$(CONFIG_BF547) := bf547
-cpu-$(CONFIG_BF547M) := bf547m
-cpu-$(CONFIG_BF548) := bf548
-cpu-$(CONFIG_BF548M) := bf548m
-cpu-$(CONFIG_BF549) := bf549
-cpu-$(CONFIG_BF549M) := bf549m
-cpu-$(CONFIG_BF561) := bf561
-cpu-$(CONFIG_BF609) := bf609
-
-rev-$(CONFIG_BF_REV_0_0) := 0.0
-rev-$(CONFIG_BF_REV_0_1) := 0.1
-rev-$(CONFIG_BF_REV_0_2) := 0.2
-rev-$(CONFIG_BF_REV_0_3) := 0.3
-rev-$(CONFIG_BF_REV_0_4) := 0.4
-rev-$(CONFIG_BF_REV_0_5) := 0.5
-rev-$(CONFIG_BF_REV_0_6) := 0.6
-rev-$(CONFIG_BF_REV_NONE) := none
-rev-$(CONFIG_BF_REV_ANY) := any
-
-CPU_REV := $(cpu-y)-$(rev-y)
-export CPU_REV
-
-KBUILD_CFLAGS += -mcpu=$(CPU_REV)
-KBUILD_AFLAGS += -mcpu=$(CPU_REV)
-
-# - we utilize the silicon rev from the toolchain, so move it over to the checkflags
-CHECKFLAGS_SILICON = $(shell echo "" | $(CPP) $(KBUILD_CFLAGS) -dD - 2>/dev/null | awk '$$2 == "__SILICON_REVISION__" { print $$3 }')
-CHECKFLAGS += -D__SILICON_REVISION__=$(CHECKFLAGS_SILICON) -D__bfin__
-
-core-y += arch/$(ARCH)/kernel/ arch/$(ARCH)/mm/ arch/$(ARCH)/mach-common/
-
-# If we have a machine-specific directory, then include it in the build.
-ifneq ($(machine-y),)
-core-y += arch/$(ARCH)/mach-$(MACHINE)/
-core-y += arch/$(ARCH)/mach-$(MACHINE)/boards/
-endif
-
-ifeq ($(CONFIG_MPU),y)
-core-y += arch/$(ARCH)/kernel/cplb-mpu/
-else
-core-y += arch/$(ARCH)/kernel/cplb-nompu/
-endif
-
-drivers-$(CONFIG_OPROFILE) += arch/$(ARCH)/oprofile/
-
-libs-y += arch/$(ARCH)/lib/
-
-machdirs := $(patsubst %,arch/blackfin/mach-%/, $(machine-y))
-
-KBUILD_CFLAGS += -Iarch/$(ARCH)/include/
-KBUILD_CFLAGS += -Iarch/$(ARCH)/mach-$(MACHINE)/include
-
-KBUILD_CPPFLAGS += $(patsubst %,-I$(srctree)/%include,$(machdirs))
-
-CLEAN_FILES += \
- arch/$(ARCH)/kernel/asm-offsets.s \
-
-archclean:
- $(Q)$(MAKE) $(clean)=$(boot)
-
-INSTALL_PATH ?= /tftpboot
-boot := arch/$(ARCH)/boot
-BOOT_TARGETS = uImage uImage.bin uImage.bz2 uImage.gz uImage.lzma uImage.lzo uImage.xip
-PHONY += $(BOOT_TARGETS) install
-KBUILD_IMAGE := $(boot)/uImage
-
-all: uImage
-
-$(BOOT_TARGETS): vmlinux
- $(Q)$(MAKE) $(build)=$(boot) $(boot)/$@
-
-install:
- $(Q)$(MAKE) $(build)=$(boot) BOOTIMAGE=$(KBUILD_IMAGE) install
-
-define archhelp
- echo '* vmImage - Alias to selected kernel format (vmImage.gz by default)'
- echo ' vmImage.bin - Uncompressed Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.bin)'
- echo ' vmImage.bz2 - Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.bz2)'
- echo '* vmImage.gz - Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.gz)'
- echo ' vmImage.lzma - Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.lzma)'
- echo ' vmImage.lzo - Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.lzo)'
- echo ' vmImage.xip - XIP Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.xip)'
- echo ' install - Install kernel using'
- echo ' (your) ~/bin/$(INSTALLKERNEL) or'
- echo ' (distribution) PATH: $(INSTALLKERNEL) or'
- echo ' install to $$(INSTALL_PATH)'
-endef
+++ /dev/null
-vmImage*
-vmlinux*
-uImage*
+++ /dev/null
-#
-# arch/blackfin/boot/Makefile
-#
-# This file is subject to the terms and conditions of the GNU General Public
-# License. See the file "COPYING" in the main directory of this archive
-# for more details.
-#
-
-targets := uImage uImage.bin uImage.bz2 uImage.gz uImage.lzma uImage.lzo uImage.xip
-extra-y += vmlinux.bin vmlinux.bin.gz vmlinux.bin.bz2 vmlinux.bin.lzma vmlinux.bin.lzo vmlinux.bin.xip
-
-ifeq ($(CONFIG_RAMKERNEL),y)
-UIMAGE_LOADADDR = $(CONFIG_BOOT_LOAD)
-else # CONFIG_ROMKERNEL must be set
-UIMAGE_LOADADDR = $(CONFIG_ROM_BASE)
-endif
-UIMAGE_ENTRYADDR = $(shell $(NM) vmlinux | awk '$$NF == "__start" {print $$1}')
-UIMAGE_NAME = '$(CPU_REV)-$(KERNELRELEASE)'
-UIMAGE_OPTS-$(CONFIG_ROMKERNEL) += -x
-
-$(obj)/vmlinux.bin: vmlinux FORCE
- $(call if_changed,objcopy)
-
-$(obj)/vmlinux.bin.gz: $(obj)/vmlinux.bin FORCE
- $(call if_changed,gzip)
-
-$(obj)/vmlinux.bin.bz2: $(obj)/vmlinux.bin FORCE
- $(call if_changed,bzip2)
-
-$(obj)/vmlinux.bin.lzma: $(obj)/vmlinux.bin FORCE
- $(call if_changed,lzma)
-
-$(obj)/vmlinux.bin.lzo: $(obj)/vmlinux.bin FORCE
- $(call if_changed,lzo)
-
-# The mkimage tool wants 64bytes prepended to the image
-quiet_cmd_mk_bin_xip = BIN $@
- cmd_mk_bin_xip = ( printf '%64s' | tr ' ' '\377' ; cat $< ) > $@
-$(obj)/vmlinux.bin.xip: $(obj)/vmlinux.bin FORCE
- $(call if_changed,mk_bin_xip)
-
-$(obj)/uImage.bin: $(obj)/vmlinux.bin
- $(call if_changed,uimage,none)
-
-$(obj)/uImage.bz2: $(obj)/vmlinux.bin.bz2
- $(call if_changed,uimage,bzip2)
-
-$(obj)/uImage.gz: $(obj)/vmlinux.bin.gz
- $(call if_changed,uimage,gzip)
-
-$(obj)/uImage.lzma: $(obj)/vmlinux.bin.lzma
- $(call if_changed,uimage,lzma)
-
-$(obj)/uImage.lzo: $(obj)/vmlinux.bin.lzo
- $(call if_changed,uimage,lzo)
-
-$(obj)/uImage.xip: $(obj)/vmlinux.bin.xip
- $(call if_changed,uimage,none)
-
-suffix-y := bin
-suffix-$(CONFIG_KERNEL_GZIP) := gz
-suffix-$(CONFIG_KERNEL_BZIP2) := bz2
-suffix-$(CONFIG_KERNEL_LZMA) := lzma
-suffix-$(CONFIG_KERNEL_LZO) := lzo
-suffix-$(CONFIG_ROMKERNEL) := xip
-
-$(obj)/uImage: $(obj)/uImage.$(suffix-y)
- @ln -sf $(notdir $<) $@
-
-install:
- sh $(srctree)/$(src)/install.sh $(KERNELRELEASE) $(BOOTIMAGE) System.map "$(INSTALL_PATH)"
+++ /dev/null
-#!/bin/sh
-#
-# arch/blackfin/boot/install.sh
-#
-# This file is subject to the terms and conditions of the GNU General Public
-# License. See the file "COPYING" in the main directory of this archive
-# for more details.
-#
-# Copyright (C) 1995 by Linus Torvalds
-#
-# Adapted from code in arch/i386/boot/Makefile by H. Peter Anvin
-# Adapted from code in arch/i386/boot/install.sh by Mike Frysinger
-#
-# "make install" script for Blackfin architecture
-#
-# Arguments:
-# $1 - kernel version
-# $2 - kernel image file
-# $3 - kernel map file
-# $4 - default install path (blank if root directory)
-#
-
-verify () {
- if [ ! -f "$1" ]; then
- echo "" 1>&2
- echo " *** Missing file: $1" 1>&2
- echo ' *** You need to run "make" before "make install".' 1>&2
- echo "" 1>&2
- exit 1
- fi
-}
-
-# Make sure the files actually exist
-verify "$2"
-verify "$3"
-
-# User may have a custom install script
-
-if [ -x ~/bin/${INSTALLKERNEL} ]; then exec ~/bin/${INSTALLKERNEL} "$@"; fi
-if which ${INSTALLKERNEL} >/dev/null 2>&1; then
- exec ${INSTALLKERNEL} "$@"
-fi
-
-# Default install - same as make zlilo
-
-back_it_up() {
- local file=$1
- [ -f ${file} ] || return 0
- local stamp=$(stat -c %Y ${file} 2>/dev/null)
- mv ${file} ${file}.${stamp:-old}
-}
-
-back_it_up $4/uImage
-back_it_up $4/System.map
-
-cat $2 > $4/uImage
-cp $3 $4/System.map
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BF518=y
-CONFIG_IRQ_TIMER0=12
-# CONFIG_CYCLES_CLOCKSOURCE is not set
-# CONFIG_SCHEDULE_L1 is not set
-# CONFIG_MEMSET_L1 is not set
-# CONFIG_MEMCPY_L1 is not set
-# CONFIG_SYS_BFIN_SPINLOCK_L1 is not set
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BFIN_GPTIMERS=m
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_3=0x99B2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_JEDECPROBE=m
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=m
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_BFIN=y
-CONFIG_BFIN_MAC=y
-# CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CHELSIO is not set
-# CONFIG_NET_VENDOR_INTEL is not set
-# CONFIG_NET_VENDOR_MARVELL is not set
-# CONFIG_NET_VENDOR_MICREL is not set
-# CONFIG_NET_VENDOR_MICROCHIP is not set
-# CONFIG_NET_VENDOR_NATSEMI is not set
-# CONFIG_NET_VENDOR_SEEQ is not set
-# CONFIG_NET_VENDOR_SMSC is not set
-# CONFIG_NET_VENDOR_STMICRO is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_BFIN_JTAG_COMM=m
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART0=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_BLACKFIN_TWI=y
-CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-# CONFIG_USB_SUPPORT is not set
-CONFIG_MMC=y
-CONFIG_SDH_BFIN=y
-CONFIG_SDH_BFIN_MISSING_CMD_PULLUP_WORKAROUND=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_BFIN=y
-CONFIG_EXT2_FS=m
-# CONFIG_DNOTIFY is not set
-CONFIG_VFAT_FS=m
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_NLS_CODEPAGE_437=m
-CONFIG_NLS_CODEPAGE_936=m
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_UTF8=m
-CONFIG_DEBUG_SHIRQ=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_MMRS=y
-CONFIG_DEBUG_HWERR=y
-CONFIG_EXACT_HWERR=y
-CONFIG_DEBUG_DOUBLEFAULT=y
-CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_BFIN_PSEUDODBG_INSNS=y
-CONFIG_CRYPTO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRC_CCITT=m
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BF526=y
-CONFIG_IRQ_TIMER0=12
-CONFIG_BFIN526_EZBRD=y
-CONFIG_IRQ_USB_INT0=11
-CONFIG_IRQ_USB_INT1=11
-CONFIG_IRQ_USB_INT2=11
-CONFIG_IRQ_USB_DMA=11
-# CONFIG_CYCLES_CLOCKSOURCE is not set
-# CONFIG_SCHEDULE_L1 is not set
-# CONFIG_MEMSET_L1 is not set
-# CONFIG_MEMCPY_L1 is not set
-# CONFIG_SYS_BFIN_SPINLOCK_L1 is not set
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BFIN_GPTIMERS=m
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_3=0x99B2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=m
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_NAND=m
-CONFIG_MTD_SPI_NOR=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_SCSI=y
-# CONFIG_SCSI_PROC_FS is not set
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_DEV_SR=m
-# CONFIG_SCSI_LOWLEVEL is not set
-CONFIG_NETDEVICES=y
-CONFIG_NET_BFIN=y
-CONFIG_BFIN_MAC=y
-# CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CHELSIO is not set
-# CONFIG_NET_VENDOR_INTEL is not set
-# CONFIG_NET_VENDOR_MARVELL is not set
-# CONFIG_NET_VENDOR_MICREL is not set
-# CONFIG_NET_VENDOR_MICROCHIP is not set
-# CONFIG_NET_VENDOR_NATSEMI is not set
-# CONFIG_NET_VENDOR_SEEQ is not set
-# CONFIG_NET_VENDOR_SMSC is not set
-# CONFIG_NET_VENDOR_STMICRO is not set
-# CONFIG_WLAN is not set
-CONFIG_INPUT_FF_MEMLESS=m
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_MISC=y
-# CONFIG_SERIO is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_BFIN_JTAG_COMM=m
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART1=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=m
-CONFIG_I2C_BLACKFIN_TWI=y
-CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_LOGITECH=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_USB=y
-# CONFIG_USB_DEVICE_CLASS is not set
-CONFIG_USB_OTG_BLACKLIST_HUB=y
-CONFIG_USB_MON=y
-CONFIG_USB_STORAGE=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_BFIN=y
-CONFIG_EXT2_FS=m
-# CONFIG_DNOTIFY is not set
-CONFIG_ISO9660_FS=m
-CONFIG_JOLIET=y
-CONFIG_VFAT_FS=m
-CONFIG_JFFS2_FS=m
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_NLS_CODEPAGE_437=m
-CONFIG_NLS_CODEPAGE_936=m
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_UTF8=m
-CONFIG_DEBUG_SHIRQ=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_MMRS=y
-CONFIG_DEBUG_HWERR=y
-CONFIG_EXACT_HWERR=y
-CONFIG_DEBUG_DOUBLEFAULT=y
-CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_BFIN_PSEUDODBG_INSNS=y
-CONFIG_CRYPTO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRC_CCITT=m
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_ELF_CORE is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_PREEMPT=y
-CONFIG_BF527=y
-CONFIG_BF_REV_0_2=y
-CONFIG_IRQ_TWI=7
-CONFIG_IRQ_PORTH_INTA=7
-CONFIG_IRQ_PORTH_INTB=7
-CONFIG_BFIN527_AD7160EVAL=y
-CONFIG_BF527_SPORT0_PORTF=y
-CONFIG_BF527_UART1_PORTG=y
-CONFIG_IRQ_USB_INT0=11
-CONFIG_IRQ_USB_INT1=11
-CONFIG_IRQ_USB_INT2=11
-CONFIG_IRQ_USB_DMA=11
-CONFIG_CMDLINE_BOOL=y
-CONFIG_CMDLINE="bootargs=root=/dev/mtdblock0 rw clkin_hz=24000000 earlyprintk=serial,uart0,57600 console=tty0 console=ttyBF0,57600"
-CONFIG_CLKIN_HZ=24000000
-CONFIG_HZ_300=y
-# CONFIG_CYCLES_CLOCKSOURCE is not set
-CONFIG_IP_CHECKSUM_L1=y
-CONFIG_SYSCALL_TAB_L1=y
-CONFIG_CPLB_SWITCH_TAB_L1=y
-CONFIG_BFIN_GPTIMERS=y
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_1=0x5554
-CONFIG_BANK_3=0xFFC0
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_NET=y
-CONFIG_UNIX=y
-# CONFIG_WIRELESS is not set
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_AD7160=y
-CONFIG_TOUCHSCREEN_AD7160_FW=y
-# CONFIG_SERIO is not set
-# CONFIG_BFIN_DMA_INTERFACE is not set
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART0=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_BFIN_OTP is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-# CONFIG_I2C_HELPER_AUTO is not set
-CONFIG_I2C_ALGOBIT=y
-CONFIG_I2C_BLACKFIN_TWI=y
-CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=400
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HWMON is not set
-CONFIG_FB=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-# CONFIG_LOGO_LINUX_CLUT224 is not set
-# CONFIG_LOGO_BLACKFIN_VGA16 is not set
-# CONFIG_HID_SUPPORT is not set
-CONFIG_USB_MUSB_HDRC=y
-CONFIG_USB_GADGET_MUSB_HDRC=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_VBUS_DRAW=500
-CONFIG_USB_G_SERIAL=y
-CONFIG_MMC=y
-CONFIG_MMC_SPI=y
-CONFIG_EXT2_FS=y
-# CONFIG_DNOTIFY is not set
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DETECT_HUNG_TASK=y
-# CONFIG_SCHED_DEBUG is not set
-# CONFIG_DEBUG_BUGVERBOSE is not set
-# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_CRC_CCITT=m
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BF527=y
-CONFIG_BF_REV_0_2=y
-CONFIG_BFIN527_EZKIT_V2=y
-CONFIG_IRQ_USB_INT0=11
-CONFIG_IRQ_USB_INT1=11
-CONFIG_IRQ_USB_INT2=11
-CONFIG_IRQ_USB_DMA=11
-# CONFIG_CYCLES_CLOCKSOURCE is not set
-# CONFIG_SCHEDULE_L1 is not set
-# CONFIG_MEMSET_L1 is not set
-# CONFIG_MEMCPY_L1 is not set
-# CONFIG_SYS_BFIN_SPINLOCK_L1 is not set
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_3=0x99B2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_IRDA=m
-CONFIG_IRLAN=m
-CONFIG_IRCOMM=m
-CONFIG_IRTTY_SIR=m
-CONFIG_BFIN_SIR=m
-CONFIG_BFIN_SIR0=y
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_JEDECPROBE=m
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=m
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_NAND=m
-CONFIG_MTD_SPI_NOR=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_SCSI=y
-# CONFIG_SCSI_PROC_FS is not set
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_DEV_SR=m
-# CONFIG_SCSI_LOWLEVEL is not set
-CONFIG_NETDEVICES=y
-CONFIG_NET_BFIN=y
-CONFIG_BFIN_MAC=y
-# CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CHELSIO is not set
-# CONFIG_NET_VENDOR_INTEL is not set
-# CONFIG_NET_VENDOR_MARVELL is not set
-# CONFIG_NET_VENDOR_MICREL is not set
-# CONFIG_NET_VENDOR_MICROCHIP is not set
-# CONFIG_NET_VENDOR_NATSEMI is not set
-# CONFIG_NET_VENDOR_SEEQ is not set
-# CONFIG_NET_VENDOR_SMSC is not set
-# CONFIG_NET_VENDOR_STMICRO is not set
-# CONFIG_WLAN is not set
-CONFIG_INPUT_FF_MEMLESS=m
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_KEYBOARD_ADP5520=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_AD7879=y
-CONFIG_TOUCHSCREEN_AD7879_I2C=y
-CONFIG_INPUT_MISC=y
-# CONFIG_SERIO is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_BFIN_JTAG_COMM=m
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART1=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=m
-CONFIG_I2C_BLACKFIN_TWI=y
-CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-CONFIG_PMIC_ADP5520=y
-CONFIG_FB=y
-CONFIG_FB_BFIN_LQ035Q1=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-# CONFIG_LOGO_LINUX_CLUT224 is not set
-# CONFIG_LOGO_BLACKFIN_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-CONFIG_SND_SOC=y
-CONFIG_SND_BF5XX_I2S=y
-CONFIG_SND_BF5XX_SOC_SSM2602=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_LOGITECH=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_USB=y
-# CONFIG_USB_DEVICE_CLASS is not set
-CONFIG_USB_OTG_BLACKLIST_HUB=y
-CONFIG_USB_MON=y
-CONFIG_USB_MUSB_HDRC=y
-CONFIG_USB_MUSB_BLACKFIN=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_ADP5520=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_BFIN=y
-CONFIG_EXT2_FS=m
-# CONFIG_DNOTIFY is not set
-CONFIG_ISO9660_FS=m
-CONFIG_JOLIET=y
-CONFIG_UDF_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_JFFS2_FS=m
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_NLS_CODEPAGE_437=m
-CONFIG_NLS_CODEPAGE_936=m
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_UTF8=m
-CONFIG_DEBUG_SHIRQ=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_MMRS=y
-CONFIG_DEBUG_HWERR=y
-CONFIG_EXACT_HWERR=y
-CONFIG_DEBUG_DOUBLEFAULT=y
-CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_BFIN_PSEUDODBG_INSNS=y
-CONFIG_CRYPTO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BF527=y
-CONFIG_BF_REV_0_1=y
-CONFIG_IRQ_USB_INT0=11
-CONFIG_IRQ_USB_INT1=11
-CONFIG_IRQ_USB_INT2=11
-CONFIG_IRQ_USB_DMA=11
-# CONFIG_CYCLES_CLOCKSOURCE is not set
-# CONFIG_SCHEDULE_L1 is not set
-# CONFIG_MEMSET_L1 is not set
-# CONFIG_MEMCPY_L1 is not set
-# CONFIG_SYS_BFIN_SPINLOCK_L1 is not set
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_3=0x99B2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_IRDA=m
-CONFIG_IRLAN=m
-CONFIG_IRCOMM=m
-CONFIG_IRTTY_SIR=m
-CONFIG_BFIN_SIR=m
-CONFIG_BFIN_SIR0=y
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_JEDECPROBE=m
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=m
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_NAND=m
-CONFIG_MTD_SPI_NOR=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_SCSI=y
-# CONFIG_SCSI_PROC_FS is not set
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_DEV_SR=m
-# CONFIG_SCSI_LOWLEVEL is not set
-CONFIG_NETDEVICES=y
-CONFIG_NET_BFIN=y
-CONFIG_BFIN_MAC=y
-# CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CHELSIO is not set
-# CONFIG_NET_VENDOR_INTEL is not set
-# CONFIG_NET_VENDOR_MARVELL is not set
-# CONFIG_NET_VENDOR_MICREL is not set
-# CONFIG_NET_VENDOR_MICROCHIP is not set
-# CONFIG_NET_VENDOR_NATSEMI is not set
-# CONFIG_NET_VENDOR_SEEQ is not set
-# CONFIG_NET_VENDOR_SMSC is not set
-# CONFIG_NET_VENDOR_STMICRO is not set
-# CONFIG_WLAN is not set
-CONFIG_INPUT_FF_MEMLESS=m
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_MISC=y
-# CONFIG_SERIO is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_BFIN_JTAG_COMM=m
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART1=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=m
-CONFIG_I2C_BLACKFIN_TWI=y
-CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-CONFIG_FB=y
-CONFIG_FB_BFIN_T350MCQB=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-CONFIG_LCD_LTV350QV=m
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-# CONFIG_LOGO_LINUX_CLUT224 is not set
-# CONFIG_LOGO_BLACKFIN_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-CONFIG_SND_SOC=y
-CONFIG_SND_BF5XX_I2S=y
-CONFIG_SND_BF5XX_SOC_SSM2602=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_LOGITECH=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_USB=y
-# CONFIG_USB_DEVICE_CLASS is not set
-CONFIG_USB_OTG_BLACKLIST_HUB=y
-CONFIG_USB_MON=y
-CONFIG_USB_MUSB_HDRC=y
-CONFIG_MUSB_PIO_ONLY=y
-CONFIG_USB_MUSB_BLACKFIN=y
-CONFIG_MUSB_PIO_ONLY=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_BFIN=y
-CONFIG_EXT2_FS=m
-# CONFIG_DNOTIFY is not set
-CONFIG_ISO9660_FS=m
-CONFIG_JOLIET=y
-CONFIG_UDF_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_JFFS2_FS=m
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_NLS_CODEPAGE_437=m
-CONFIG_NLS_CODEPAGE_936=m
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_UTF8=m
-CONFIG_DEBUG_SHIRQ=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_MMRS=y
-CONFIG_DEBUG_HWERR=y
-CONFIG_EXACT_HWERR=y
-CONFIG_DEBUG_DOUBLEFAULT=y
-CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_BFIN_PSEUDODBG_INSNS=y
-CONFIG_CRYPTO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-CONFIG_LOCALVERSION="DEV_0-1_pre2010"
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BF527=y
-CONFIG_BF_REV_0_2=y
-CONFIG_BFIN527_TLL6527M=y
-CONFIG_BF527_UART1_PORTG=y
-CONFIG_IRQ_USB_INT0=11
-CONFIG_IRQ_USB_INT1=11
-CONFIG_IRQ_USB_INT2=11
-CONFIG_IRQ_USB_DMA=11
-CONFIG_BOOT_LOAD=0x400000
-# CONFIG_CYCLES_CLOCKSOURCE is not set
-# CONFIG_SCHEDULE_L1 is not set
-# CONFIG_MEMSET_L1 is not set
-# CONFIG_MEMCPY_L1 is not set
-# CONFIG_SYS_BFIN_SPINLOCK_L1 is not set
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BFIN_GPTIMERS=y
-CONFIG_DMA_UNCACHED_2M=y
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_0=0xFFC2
-CONFIG_BANK_1=0xFFC2
-CONFIG_BANK_2=0xFFC2
-CONFIG_BANK_3=0xFFC2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_IRDA=m
-CONFIG_IRLAN=m
-CONFIG_IRCOMM=m
-CONFIG_IRTTY_SIR=m
-CONFIG_BFIN_SIR=m
-CONFIG_BFIN_SIR0=y
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=y
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_GPIO_ADDR=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_SCSI=y
-# CONFIG_SCSI_PROC_FS is not set
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_DEV_SR=m
-# CONFIG_SCSI_LOWLEVEL is not set
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_BFIN_MAC=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_AD7879=m
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_AD714X=y
-CONFIG_INPUT_ADXL34X=y
-# CONFIG_SERIO is not set
-CONFIG_BFIN_PPI=m
-CONFIG_BFIN_SIMPLE_TIMER=m
-CONFIG_BFIN_SPORT=m
-# CONFIG_CONSOLE_TRANSLATIONS is not set
-# CONFIG_DEVKMEM is not set
-CONFIG_BFIN_JTAG_COMM=m
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART1=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C_CHARDEV=y
-# CONFIG_I2C_HELPER_AUTO is not set
-CONFIG_I2C_SMBUS=y
-CONFIG_I2C_BLACKFIN_TWI=y
-CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
-CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
-CONFIG_VIDEO_BLACKFIN_CAM=m
-CONFIG_OV9655=y
-CONFIG_FB=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FONTS=y
-CONFIG_FONT_6x11=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-# CONFIG_LOGO_LINUX_CLUT224 is not set
-# CONFIG_LOGO_BLACKFIN_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-CONFIG_SND_MIXER_OSS=y
-CONFIG_SND_PCM_OSS=y
-CONFIG_SND_SOC=y
-CONFIG_SND_BF5XX_I2S=y
-CONFIG_SND_BF5XX_SOC_SSM2602=y
-# CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
-CONFIG_MMC=m
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_BFIN=y
-CONFIG_EXT2_FS=y
-# CONFIG_DNOTIFY is not set
-CONFIG_ISO9660_FS=m
-CONFIG_JOLIET=y
-CONFIG_UDF_FS=m
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_JFFS2_FS=y
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-# CONFIG_RPCSEC_GSS_KRB5 is not set
-CONFIG_NLS_CODEPAGE_437=m
-CONFIG_NLS_CODEPAGE_936=m
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_UTF8=m
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_SHIRQ=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_MMRS=y
-CONFIG_DEBUG_HWERR=y
-CONFIG_EXACT_HWERR=y
-CONFIG_DEBUG_DOUBLEFAULT=y
-CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_CRYPTO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRC7=m
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BFIN533_EZKIT=y
-CONFIG_TIMER0=11
-CONFIG_CLKIN_HZ=27000000
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BFIN_GPTIMERS=m
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_3=0xAAC2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_IRDA=m
-CONFIG_IRLAN=m
-CONFIG_IRCOMM=m
-CONFIG_IRDA_CACHE_LAST_LSAP=y
-CONFIG_IRTTY_SIR=m
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_JEDECPROBE=y
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=y
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_PLATRAM=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-# CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CHELSIO is not set
-# CONFIG_NET_VENDOR_INTEL is not set
-# CONFIG_NET_VENDOR_MARVELL is not set
-# CONFIG_NET_VENDOR_MICREL is not set
-# CONFIG_NET_VENDOR_MICROCHIP is not set
-# CONFIG_NET_VENDOR_NATSEMI is not set
-# CONFIG_NET_VENDOR_SEEQ is not set
-CONFIG_SMC91X=y
-# CONFIG_NET_VENDOR_STMICRO is not set
-# CONFIG_WLAN is not set
-CONFIG_INPUT=m
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=m
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_BFIN_JTAG_COMM=m
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-# CONFIG_USB_SUPPORT is not set
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_BFIN=y
-# CONFIG_DNOTIFY is not set
-CONFIG_JFFS2_FS=m
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_DEBUG_SHIRQ=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_MMRS=y
-CONFIG_DEBUG_HWERR=y
-CONFIG_EXACT_HWERR=y
-CONFIG_DEBUG_DOUBLEFAULT=y
-CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_BFIN_PSEUDODBG_INSNS=y
-CONFIG_CRYPTO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_TIMER0=11
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BFIN_GPTIMERS=m
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_3=0xAAC2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_IRDA=m
-CONFIG_IRLAN=m
-CONFIG_IRCOMM=m
-CONFIG_IRDA_CACHE_LAST_LSAP=y
-CONFIG_IRTTY_SIR=m
-CONFIG_BFIN_SIR=m
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=m
-CONFIG_MTD_CFI_AMDSTD=m
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=m
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-# CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CHELSIO is not set
-# CONFIG_NET_VENDOR_INTEL is not set
-# CONFIG_NET_VENDOR_MARVELL is not set
-# CONFIG_NET_VENDOR_MICREL is not set
-# CONFIG_NET_VENDOR_MICROCHIP is not set
-# CONFIG_NET_VENDOR_NATSEMI is not set
-# CONFIG_NET_VENDOR_SEEQ is not set
-CONFIG_SMC91X=y
-# CONFIG_NET_VENDOR_STMICRO is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=m
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_MISC=y
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_BFIN_JTAG_COMM=m
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=m
-CONFIG_I2C_CHARDEV=m
-CONFIG_I2C_GPIO=m
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-CONFIG_FB=m
-CONFIG_FIRMWARE_EDID=y
-CONFIG_SOUND=m
-CONFIG_SND=m
-CONFIG_SND_MIXER_OSS=m
-CONFIG_SND_PCM_OSS=m
-CONFIG_SND_SOC=m
-CONFIG_SND_BF5XX_I2S=m
-CONFIG_SND_BF5XX_SOC_AD73311=m
-# CONFIG_USB_SUPPORT is not set
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_BFIN=y
-# CONFIG_DNOTIFY is not set
-CONFIG_JFFS2_FS=m
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_DEBUG_SHIRQ=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_MMRS=y
-CONFIG_DEBUG_HWERR=y
-CONFIG_EXACT_HWERR=y
-CONFIG_DEBUG_DOUBLEFAULT=y
-CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_BFIN_PSEUDODBG_INSNS=y
-CONFIG_CRYPTO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BF537=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BFIN_GPTIMERS=m
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_3=0x99B2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_CAN=m
-CONFIG_CAN_RAW=m
-CONFIG_CAN_BCM=m
-CONFIG_CAN_BFIN=m
-CONFIG_IRDA=m
-CONFIG_IRLAN=m
-CONFIG_IRCOMM=m
-CONFIG_IRDA_CACHE_LAST_LSAP=y
-CONFIG_IRTTY_SIR=m
-CONFIG_BFIN_SIR=m
-CONFIG_BFIN_SIR1=y
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=m
-CONFIG_MTD_CFI_AMDSTD=m
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=m
-CONFIG_MTD_PHYSMAP=m
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_BFIN=y
-CONFIG_BFIN_MAC=y
-# CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CHELSIO is not set
-# CONFIG_NET_VENDOR_INTEL is not set
-# CONFIG_NET_VENDOR_MARVELL is not set
-# CONFIG_NET_VENDOR_MICREL is not set
-# CONFIG_NET_VENDOR_MICROCHIP is not set
-# CONFIG_NET_VENDOR_NATSEMI is not set
-# CONFIG_NET_VENDOR_SEEQ is not set
-# CONFIG_NET_VENDOR_SMSC is not set
-# CONFIG_NET_VENDOR_STMICRO is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=m
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_MISC=y
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_BFIN_JTAG_COMM=m
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART0=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=m
-CONFIG_I2C_CHARDEV=m
-CONFIG_I2C_BLACKFIN_TWI=m
-CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-CONFIG_FB=m
-CONFIG_FIRMWARE_EDID=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-CONFIG_SOUND=m
-CONFIG_SND=m
-CONFIG_SND_MIXER_OSS=m
-CONFIG_SND_PCM_OSS=m
-CONFIG_SND_SOC=m
-CONFIG_SND_BF5XX_I2S=m
-CONFIG_SND_BF5XX_SOC_AD73311=m
-# CONFIG_USB_SUPPORT is not set
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_BFIN=y
-# CONFIG_DNOTIFY is not set
-CONFIG_JFFS2_FS=m
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_DEBUG_SHIRQ=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_MMRS=y
-CONFIG_DEBUG_HWERR=y
-CONFIG_EXACT_HWERR=y
-CONFIG_DEBUG_DOUBLEFAULT=y
-CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_BFIN_PSEUDODBG_INSNS=y
-CONFIG_CRYPTO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BF538=y
-CONFIG_IRQ_TIMER0=12
-CONFIG_IRQ_TIMER1=12
-CONFIG_IRQ_TIMER2=12
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_3=0x99B2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_PM=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_CAN=m
-CONFIG_CAN_RAW=m
-CONFIG_CAN_BCM=m
-CONFIG_CAN_DEV=m
-CONFIG_CAN_BFIN=m
-CONFIG_IRDA=m
-CONFIG_IRLAN=m
-CONFIG_IRCOMM=m
-CONFIG_IRDA_CACHE_LAST_LSAP=y
-CONFIG_IRTTY_SIR=m
-CONFIG_BFIN_SIR=m
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=m
-CONFIG_MTD_CFI_AMDSTD=m
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=m
-CONFIG_MTD_PHYSMAP=m
-CONFIG_MTD_NAND=m
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-CONFIG_SMSC_PHY=y
-CONFIG_NET_ETHERNET=y
-CONFIG_SMC91X=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=m
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_AD7879=y
-CONFIG_TOUCHSCREEN_AD7879_SPI=y
-CONFIG_INPUT_MISC=y
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_DEVKMEM is not set
-CONFIG_BFIN_JTAG_COMM=m
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART0=y
-CONFIG_SERIAL_BFIN_UART1=y
-CONFIG_SERIAL_BFIN_UART2=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=m
-CONFIG_I2C_BLACKFIN_TWI=m
-CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-CONFIG_FB=m
-CONFIG_FB_BFIN_LQ035Q1=m
-# CONFIG_USB_SUPPORT is not set
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_BFIN=y
-# CONFIG_DNOTIFY is not set
-CONFIG_JFFS2_FS=m
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_SMB_FS=m
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_SHIRQ=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_MMRS=y
-CONFIG_DEBUG_HWERR=y
-CONFIG_EXACT_HWERR=y
-CONFIG_DEBUG_DOUBLEFAULT=y
-CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_BFIN_PSEUDODBG_INSNS=y
-CONFIG_CRYPTO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BF548_std=y
-CONFIG_IRQ_TIMER0=11
-# CONFIG_CYCLES_CLOCKSOURCE is not set
-# CONFIG_SCHEDULE_L1 is not set
-# CONFIG_MEMSET_L1 is not set
-# CONFIG_MEMCPY_L1 is not set
-# CONFIG_SYS_BFIN_SPINLOCK_L1 is not set
-CONFIG_CACHELINE_ALIGNED_L1=y
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BFIN_GPTIMERS=m
-CONFIG_DMA_UNCACHED_2M=y
-CONFIG_BFIN_EXTMEM_WRITETHROUGH=y
-CONFIG_BANK_3=0x99B2
-CONFIG_EBIU_MBSCTLVAL=0x0
-CONFIG_EBIU_MODEVAL=0x1
-CONFIG_EBIU_FCTLVAL=0x6
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_CAN=m
-CONFIG_CAN_RAW=m
-CONFIG_CAN_BCM=m
-CONFIG_CAN_BFIN=m
-CONFIG_IRDA=m
-CONFIG_IRLAN=m
-CONFIG_IRCOMM=m
-CONFIG_IRTTY_SIR=m
-CONFIG_BFIN_SIR=m
-CONFIG_BFIN_SIR3=y
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_FW_LOADER=m
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_BF5XX=y
-# CONFIG_MTD_NAND_BF5XX_HWECC is not set
-CONFIG_MTD_SPI_NOR=y
-CONFIG_BLK_DEV_RAM=y
-# CONFIG_SCSI_PROC_FS is not set
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_DEV_SR=m
-# CONFIG_SCSI_LOWLEVEL is not set
-CONFIG_ATA=y
-# CONFIG_SATA_PMP is not set
-CONFIG_PATA_BF54X=y
-CONFIG_NETDEVICES=y
-# CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CHELSIO is not set
-# CONFIG_NET_VENDOR_INTEL is not set
-# CONFIG_NET_VENDOR_MARVELL is not set
-# CONFIG_NET_VENDOR_MICREL is not set
-# CONFIG_NET_VENDOR_MICROCHIP is not set
-# CONFIG_NET_VENDOR_NATSEMI is not set
-# CONFIG_NET_VENDOR_SEEQ is not set
-CONFIG_SMSC911X=y
-# CONFIG_NET_VENDOR_STMICRO is not set
-# CONFIG_WLAN is not set
-CONFIG_INPUT_FF_MEMLESS=m
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=m
-CONFIG_INPUT_EVBUG=m
-# CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_KEYBOARD_BFIN=y
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_AD7877=m
-CONFIG_INPUT_MISC=y
-# CONFIG_SERIO is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_BFIN_JTAG_COMM=m
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART1=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_BLACKFIN_TWI=y
-CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-CONFIG_FB=y
-CONFIG_FIRMWARE_EDID=y
-CONFIG_FB_BF54X_LQ043=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FONTS=y
-CONFIG_FONT_6x11=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-# CONFIG_LOGO_LINUX_CLUT224 is not set
-# CONFIG_LOGO_BLACKFIN_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-CONFIG_SND_MIXER_OSS=y
-CONFIG_SND_PCM_OSS=y
-CONFIG_SND_SOC=y
-CONFIG_SND_BF5XX_AC97=y
-CONFIG_SND_BF5XX_SOC_AD1980=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_LOGITECH=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_USB=y
-# CONFIG_USB_DEVICE_CLASS is not set
-CONFIG_USB_OTG_BLACKLIST_HUB=y
-CONFIG_USB_MON=y
-CONFIG_USB_MUSB_HDRC=y
-CONFIG_USB_MUSB_BLACKFIN=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=m
-CONFIG_SDH_BFIN=y
-CONFIG_SDH_BFIN_MISSING_CMD_PULLUP_WORKAROUND=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_BFIN=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-# CONFIG_DNOTIFY is not set
-CONFIG_ISO9660_FS=m
-CONFIG_JOLIET=y
-CONFIG_ZISOFS=y
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_NTFS_FS=m
-CONFIG_NTFS_RW=y
-CONFIG_JFFS2_FS=m
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_NFSD=m
-CONFIG_NFSD_V3=y
-CONFIG_CIFS=y
-CONFIG_NLS_CODEPAGE_437=m
-CONFIG_NLS_CODEPAGE_936=m
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_UTF8=m
-CONFIG_DEBUG_SHIRQ=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_MMRS=y
-CONFIG_DEBUG_HWERR=y
-CONFIG_EXACT_HWERR=y
-CONFIG_DEBUG_DOUBLEFAULT=y
-CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_BFIN_PSEUDODBG_INSNS=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SYSFS_DEPRECATED_V2=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BF561=y
-CONFIG_BF_REV_0_5=y
-CONFIG_IRQ_TIMER0=10
-CONFIG_BFIN561_ACVILON=y
-# CONFIG_BF561_COREB is not set
-CONFIG_CLKIN_HZ=12000000
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BFIN_GPTIMERS=y
-CONFIG_DMA_UNCACHED_4M=y
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_0=0x99b2
-CONFIG_BANK_1=0x3350
-CONFIG_BANK_3=0xAAC2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_SYN_COOKIES=y
-# CONFIG_INET_LRO is not set
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_PLATRAM=y
-CONFIG_MTD_PHRAM=y
-CONFIG_MTD_BLOCK2MTD=y
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_PLATFORM=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=2
-CONFIG_BLK_DEV_RAM_SIZE=16384
-CONFIG_SCSI=y
-# CONFIG_SCSI_PROC_FS is not set
-CONFIG_BLK_DEV_SD=y
-# CONFIG_SCSI_LOWLEVEL is not set
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_SMSC911X=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_PIO=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_PCA_PLATFORM=y
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_SPI_SPIDEV=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_PCF857X=y
-CONFIG_SENSORS_LM75=y
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-CONFIG_SOUND=y
-CONFIG_SND=y
-CONFIG_SND_MIXER_OSS=y
-CONFIG_SND_PCM_OSS=y
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_USB is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_BF5XX_I2S=y
-CONFIG_SND_BF5XX_SPORT_NUM=1
-CONFIG_USB=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-# CONFIG_USB_DEVICE_CLASS is not set
-CONFIG_USB_MON=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_FTDI_SIO=y
-CONFIG_USB_SERIAL_PL2303=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_DS1307=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_EXT2_FS_POSIX_ACL=y
-CONFIG_EXT2_FS_SECURITY=y
-# CONFIG_DNOTIFY is not set
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_FAT_DEFAULT_CODEPAGE=866
-CONFIG_FAT_DEFAULT_IOCHARSET="cp1251"
-CONFIG_NTFS_FS=y
-CONFIG_CONFIGFS_FS=y
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_COMPRESSION_OPTIONS=y
-# CONFIG_JFFS2_ZLIB is not set
-CONFIG_JFFS2_LZO=y
-# CONFIG_JFFS2_RTIME is not set
-CONFIG_JFFS2_CMODE_FAVOURLZO=y
-CONFIG_CRAMFS=y
-CONFIG_MINIX_FS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS_DEFAULT="cp1251"
-CONFIG_NLS_CODEPAGE_866=y
-CONFIG_NLS_CODEPAGE_1251=y
-CONFIG_NLS_KOI8_R=y
-CONFIG_NLS_UTF8=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_SHIRQ=y
-CONFIG_DETECT_HUNG_TASK=y
-# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_MMRS=y
-# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
-CONFIG_CPLB_INFO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BF561=y
-CONFIG_SMP=y
-CONFIG_IRQ_TIMER0=10
-CONFIG_CLKIN_HZ=30000000
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BFIN_GPTIMERS=m
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_3=0xAAC2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_IRDA=m
-CONFIG_IRLAN=m
-CONFIG_IRCOMM=m
-CONFIG_IRDA_CACHE_LAST_LSAP=y
-CONFIG_IRTTY_SIR=m
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=m
-CONFIG_MTD_PHYSMAP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-# CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CHELSIO is not set
-# CONFIG_NET_VENDOR_INTEL is not set
-# CONFIG_NET_VENDOR_MARVELL is not set
-# CONFIG_NET_VENDOR_MICREL is not set
-# CONFIG_NET_VENDOR_MICROCHIP is not set
-# CONFIG_NET_VENDOR_NATSEMI is not set
-# CONFIG_NET_VENDOR_SEEQ is not set
-CONFIG_SMC91X=y
-# CONFIG_NET_VENDOR_STMICRO is not set
-# CONFIG_WLAN is not set
-CONFIG_INPUT=m
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=m
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_BFIN_JTAG_COMM=m
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-# CONFIG_USB_SUPPORT is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_JFFS2_FS=m
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_DEBUG_SHIRQ=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_MMRS=y
-CONFIG_DEBUG_HWERR=y
-CONFIG_EXACT_HWERR=y
-CONFIG_DEBUG_DOUBLEFAULT=y
-CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_BFIN_PSEUDODBG_INSNS=y
-CONFIG_CRYPTO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BF561=y
-CONFIG_IRQ_TIMER0=10
-CONFIG_CLKIN_HZ=30000000
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BFIN_GPTIMERS=m
-CONFIG_BFIN_EXTMEM_WRITETHROUGH=y
-CONFIG_BFIN_L2_DCACHEABLE=y
-CONFIG_BFIN_L2_WRITETHROUGH=y
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_3=0xAAC2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_IRDA=m
-CONFIG_IRLAN=m
-CONFIG_IRCOMM=m
-CONFIG_IRDA_CACHE_LAST_LSAP=y
-CONFIG_IRTTY_SIR=m
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=m
-CONFIG_MTD_PHYSMAP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-# CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CHELSIO is not set
-# CONFIG_NET_VENDOR_INTEL is not set
-# CONFIG_NET_VENDOR_MARVELL is not set
-# CONFIG_NET_VENDOR_MICREL is not set
-# CONFIG_NET_VENDOR_MICROCHIP is not set
-# CONFIG_NET_VENDOR_NATSEMI is not set
-# CONFIG_NET_VENDOR_SEEQ is not set
-CONFIG_SMC91X=y
-# CONFIG_NET_VENDOR_STMICRO is not set
-# CONFIG_WLAN is not set
-CONFIG_INPUT=m
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=m
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_BFIN_JTAG_COMM=m
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-# CONFIG_USB_SUPPORT is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_JFFS2_FS=m
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_DEBUG_SHIRQ=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_MMRS=y
-CONFIG_DEBUG_HWERR=y
-CONFIG_EXACT_HWERR=y
-CONFIG_DEBUG_DOUBLEFAULT=y
-CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_BFIN_PSEUDODBG_INSNS=y
-CONFIG_CRYPTO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BF609=y
-CONFIG_PINT1_ASSIGN=0x01010000
-CONFIG_PINT2_ASSIGN=0x07000101
-CONFIG_PINT3_ASSIGN=0x02020303
-CONFIG_IP_CHECKSUM_L1=y
-CONFIG_SYSCALL_TAB_L1=y
-CONFIG_CPLB_SWITCH_TAB_L1=y
-# CONFIG_APP_STACK_L1 is not set
-# CONFIG_BFIN_INS_LOWOVERHEAD is not set
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_PM_BFIN_WAKE_PE12=y
-CONFIG_PM_BFIN_WAKE_PE12_POL=1
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_RARP=y
-# CONFIG_IPV6 is not set
-CONFIG_NETFILTER=y
-CONFIG_CAN=y
-CONFIG_CAN_BFIN=y
-CONFIG_IRDA=y
-CONFIG_IRTTY_SIR=y
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_FW_LOADER=m
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_CFI_STAA=y
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_UBI=m
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_NETDEVICES=y
-# CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CHELSIO is not set
-# CONFIG_NET_VENDOR_INTEL is not set
-# CONFIG_NET_VENDOR_MARVELL is not set
-# CONFIG_NET_VENDOR_MICREL is not set
-# CONFIG_NET_VENDOR_MICROCHIP is not set
-# CONFIG_NET_VENDOR_NATSEMI is not set
-# CONFIG_NET_VENDOR_SEEQ is not set
-# CONFIG_NET_VENDOR_SMSC is not set
-CONFIG_STMMAC_ETH=y
-CONFIG_STMMAC_IEEE1588=y
-# CONFIG_WLAN is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_BFIN_ROTARY=y
-# CONFIG_SERIO is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_BFIN_SIMPLE_TIMER=m
-# CONFIG_BFIN_CRC is not set
-CONFIG_BFIN_LINKPORT=y
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART0=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_BLACKFIN_TWI=y
-CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
-CONFIG_SPI=y
-CONFIG_SPI_ADI_V3=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_PINCTRL_MCP23S08=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-CONFIG_SOUND=m
-CONFIG_SND=m
-CONFIG_SND_MIXER_OSS=m
-CONFIG_SND_PCM_OSS=m
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_SPI is not set
-# CONFIG_SND_USB is not set
-CONFIG_SND_SOC=m
-CONFIG_USB=y
-CONFIG_USB_MUSB_HDRC=y
-CONFIG_USB_MUSB_BLACKFIN=m
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MUSB_HDRC=y
-CONFIG_USB_ZERO=y
-CONFIG_MMC=y
-CONFIG_SDH_BFIN=y
-# CONFIG_IOMMU_SUPPORT is not set
-CONFIG_EXT2_FS=y
-# CONFIG_DNOTIFY is not set
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_JFFS2_FS=m
-CONFIG_UBIFS_FS=m
-CONFIG_NFS_FS=m
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_SHIRQ=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEBUG_INFO=y
-CONFIG_FRAME_POINTER=y
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_BFIN_PSEUDODBG_INSNS=y
-CONFIG_CRYPTO_HMAC=m
-CONFIG_CRYPTO_MD4=m
-CONFIG_CRYPTO_MD5=m
-CONFIG_CRYPTO_ARC4=m
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRYPTO_DEV_BFIN_CRC=m
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SYSFS_DEPRECATED_V2=y
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BF532=y
-CONFIG_BF_REV_0_5=y
-CONFIG_BLACKSTAMP=y
-CONFIG_TIMER0=11
-# CONFIG_CYCLES_CLOCKSOURCE is not set
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_ROMKERNEL=y
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BFIN_GPTIMERS=y
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_3=0xAAC2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_BINFMT_SHARED_FLAT=y
-CONFIG_PM=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_LRO is not set
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=m
-CONFIG_MTD_CFI_AMDSTD=m
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=m
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_NBD=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_MISC_DEVICES=y
-CONFIG_EEPROM_AT25=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_SMC91X=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=m
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_HW_RANDOM=y
-CONFIG_I2C=m
-CONFIG_I2C_CHARDEV=m
-CONFIG_I2C_GPIO=m
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_SPI_SPIDEV=m
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-# CONFIG_USB_SUPPORT is not set
-CONFIG_MMC=y
-CONFIG_MMC_SPI=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_BFIN=y
-# CONFIG_DNOTIFY is not set
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_JFFS2_FS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_NFS_V4=y
-CONFIG_SMB_FS=y
-CONFIG_CIFS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_UTF8=y
-CONFIG_SYSCTL_SYSCALL_CHECK=y
-CONFIG_DEBUG_MMRS=y
-# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_CRC_CCITT=m
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-CONFIG_KERNEL_LZMA=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_RD_GZIP is not set
-CONFIG_RD_LZMA=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BF527=y
-CONFIG_BF_REV_0_1=y
-CONFIG_IRQ_TIMER0=12
-CONFIG_BFIN527_BLUETECHNIX_CM=y
-CONFIG_IRQ_USB_INT0=11
-CONFIG_IRQ_USB_INT1=11
-CONFIG_IRQ_USB_INT2=11
-CONFIG_IRQ_USB_DMA=11
-# CONFIG_CYCLES_CLOCKSOURCE is not set
-# CONFIG_SCHEDULE_L1 is not set
-# CONFIG_MEMSET_L1 is not set
-# CONFIG_MEMCPY_L1 is not set
-# CONFIG_SYS_BFIN_SPINLOCK_L1 is not set
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BFIN_GPTIMERS=y
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_3=0xFFC0
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=m
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_GPIO_ADDR=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-# CONFIG_SCSI_LOWLEVEL is not set
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_BFIN_MAC=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART0=y
-CONFIG_SERIAL_BFIN_UART1=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=m
-CONFIG_I2C_BLACKFIN_TWI=m
-CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-CONFIG_USB=m
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-# CONFIG_USB_DEVICE_CLASS is not set
-CONFIG_USB_OTG_BLACKLIST_HUB=y
-CONFIG_USB_MON=m
-CONFIG_USB_MUSB_HDRC=m
-CONFIG_USB_MUSB_PERIPHERAL=y
-CONFIG_USB_GADGET_MUSB_HDRC=y
-CONFIG_MUSB_PIO_ONLY=y
-CONFIG_USB_STORAGE=m
-CONFIG_USB_GADGET=m
-CONFIG_USB_ETH=m
-CONFIG_USB_MASS_STORAGE=m
-CONFIG_USB_G_SERIAL=m
-CONFIG_USB_G_PRINTER=m
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_BFIN=y
-# CONFIG_DNOTIFY is not set
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_JFFS2_FS=y
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_SMB_FS=m
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_DEBUG_FS=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
-CONFIG_EARLY_PRINTK=y
-CONFIG_CRYPTO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRC_CCITT=m
-CONFIG_CRC_ITU_T=y
-CONFIG_CRC7=y
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-CONFIG_KERNEL_LZMA=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_RD_GZIP is not set
-CONFIG_RD_LZMA=y
-CONFIG_EXPERT=y
-# CONFIG_UID16 is not set
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_BFIN533_BLUETECHNIX_CM=y
-CONFIG_TIMER0=11
-# CONFIG_CYCLES_CLOCKSOURCE is not set
-CONFIG_IP_CHECKSUM_L1=y
-CONFIG_SYSCALL_TAB_L1=y
-CONFIG_CPLB_SWITCH_TAB_L1=y
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_3=0xFFC2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_BINFMT_SHARED_FLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_NETDEVICES=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-# CONFIG_HWMON is not set
-# CONFIG_USB_SUPPORT is not set
-CONFIG_MMC=y
-# CONFIG_MMC_BLOCK_BOUNCE is not set
-CONFIG_MMC_SPI=m
-# CONFIG_DNOTIFY is not set
-CONFIG_VFAT_FS=y
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_DEBUG_MMRS=y
-# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_CRC_CCITT=y
-CONFIG_CRC_ITU_T=y
-CONFIG_CRC7=y
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-CONFIG_KERNEL_LZMA=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_RD_GZIP is not set
-CONFIG_RD_LZMA=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_UID16 is not set
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_DEFAULT_NOOP=y
-CONFIG_BF537=y
-CONFIG_IRQ_TIMER0=12
-CONFIG_BFIN537_BLUETECHNIX_CM_E=y
-# CONFIG_CYCLES_CLOCKSOURCE is not set
-CONFIG_IP_CHECKSUM_L1=y
-CONFIG_SYSCALL_TAB_L1=y
-CONFIG_CPLB_SWITCH_TAB_L1=y
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_3=0xFFC2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_BINFMT_SHARED_FLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=m
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_GPIO_ADDR=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_BFIN_MAC=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART0=y
-CONFIG_SERIAL_BFIN_UART1=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_USB_GADGET=m
-CONFIG_USB_ETH=m
-CONFIG_MMC=y
-# CONFIG_MMC_BLOCK_BOUNCE is not set
-CONFIG_MMC_SPI=m
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-# CONFIG_DNOTIFY is not set
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_JFFS2_FS=y
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_DEBUG_MMRS=y
-# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_CRYPTO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRC_CCITT=m
-CONFIG_CRC_ITU_T=y
-CONFIG_CRC7=y
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-CONFIG_KERNEL_LZMA=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_RD_GZIP is not set
-CONFIG_RD_LZMA=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_UID16 is not set
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_DEFAULT_NOOP=y
-CONFIG_BF537=y
-CONFIG_IRQ_TIMER0=12
-CONFIG_BFIN537_BLUETECHNIX_CM_U=y
-CONFIG_CLKIN_HZ=30000000
-# CONFIG_CYCLES_CLOCKSOURCE is not set
-CONFIG_IP_CHECKSUM_L1=y
-CONFIG_SYSCALL_TAB_L1=y
-CONFIG_CPLB_SWITCH_TAB_L1=y
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_2=0xFFC2
-CONFIG_BANK_3=0xFFC2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_BINFMT_SHARED_FLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=m
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_GPIO_ADDR=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART0=y
-CONFIG_SERIAL_BFIN_UART1=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_ETH=y
-CONFIG_MMC=y
-CONFIG_MMC_SPI=m
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-# CONFIG_DNOTIFY is not set
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_JFFS2_FS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_DEBUG_MMRS=y
-# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_CRC_CCITT=m
-CONFIG_CRC_ITU_T=y
-CONFIG_CRC7=y
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-CONFIG_KERNEL_LZMA=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_RD_GZIP is not set
-CONFIG_RD_LZMA=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_UID16 is not set
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_DEFAULT_NOOP=y
-CONFIG_BF548_std=y
-CONFIG_BF_REV_ANY=y
-CONFIG_IRQ_TIMER0=11
-CONFIG_BFIN548_BLUETECHNIX_CM=y
-# CONFIG_DEB_DMA_URGENT is not set
-# CONFIG_SCHEDULE_L1 is not set
-# CONFIG_MEMSET_L1 is not set
-# CONFIG_MEMCPY_L1 is not set
-# CONFIG_SYS_BFIN_SPINLOCK_L1 is not set
-CONFIG_CACHELINE_ALIGNED_L1=y
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BFIN_EXTMEM_WRITETHROUGH=y
-CONFIG_BANK_1=0x5554
-CONFIG_EBIU_MBSCTLVAL=0x0
-CONFIG_EBIU_MODEVAL=0x1
-CONFIG_EBIU_FCTLVAL=0x6
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_INET_XFRM_MODE_TRANSPORT=m
-CONFIG_INET_XFRM_MODE_TUNNEL=m
-CONFIG_INET_XFRM_MODE_BEET=m
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_SCSI=m
-CONFIG_BLK_DEV_SD=m
-# CONFIG_SCSI_LOWLEVEL is not set
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_SMSC911X=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=m
-CONFIG_INPUT_EVBUG=m
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_PIO=y
-CONFIG_SERIAL_BFIN_UART1=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_BLACKFIN_TWI=y
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-# CONFIG_HID_SUPPORT is not set
-CONFIG_USB=m
-# CONFIG_USB_DEVICE_CLASS is not set
-CONFIG_USB_MON=m
-CONFIG_USB_MUSB_HDRC=m
-CONFIG_USB_MUSB_PERIPHERAL=y
-CONFIG_USB_GADGET_MUSB_HDRC=y
-CONFIG_USB_STORAGE=m
-CONFIG_USB_GADGET=m
-CONFIG_USB_ZERO=m
-CONFIG_USB_ETH=m
-# CONFIG_USB_ETH_RNDIS is not set
-CONFIG_USB_GADGETFS=m
-CONFIG_USB_MASS_STORAGE=m
-CONFIG_USB_G_SERIAL=m
-CONFIG_USB_G_PRINTER=m
-CONFIG_MMC=m
-CONFIG_SDH_BFIN=m
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_BFIN=m
-CONFIG_EXT2_FS=m
-# CONFIG_DNOTIFY is not set
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_NTFS_FS=m
-CONFIG_NTFS_RW=y
-CONFIG_JFFS2_FS=y
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_CIFS=m
-CONFIG_NLS=y
-CONFIG_NLS_CODEPAGE_437=m
-CONFIG_NLS_CODEPAGE_737=m
-CONFIG_NLS_CODEPAGE_775=m
-CONFIG_NLS_CODEPAGE_850=m
-CONFIG_NLS_CODEPAGE_852=m
-CONFIG_NLS_CODEPAGE_855=m
-CONFIG_NLS_CODEPAGE_857=m
-CONFIG_NLS_CODEPAGE_860=m
-CONFIG_NLS_CODEPAGE_861=m
-CONFIG_NLS_CODEPAGE_862=m
-CONFIG_NLS_CODEPAGE_863=m
-CONFIG_NLS_CODEPAGE_864=m
-CONFIG_NLS_CODEPAGE_865=m
-CONFIG_NLS_CODEPAGE_866=m
-CONFIG_NLS_CODEPAGE_869=m
-CONFIG_NLS_CODEPAGE_936=m
-CONFIG_NLS_CODEPAGE_950=m
-CONFIG_NLS_CODEPAGE_932=m
-CONFIG_NLS_CODEPAGE_949=m
-CONFIG_NLS_CODEPAGE_874=m
-CONFIG_NLS_ISO8859_8=m
-CONFIG_NLS_CODEPAGE_1250=m
-CONFIG_NLS_CODEPAGE_1251=m
-CONFIG_NLS_ASCII=m
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_ISO8859_2=m
-CONFIG_NLS_ISO8859_3=m
-CONFIG_NLS_ISO8859_4=m
-CONFIG_NLS_ISO8859_5=m
-CONFIG_NLS_ISO8859_6=m
-CONFIG_NLS_ISO8859_7=m
-CONFIG_NLS_ISO8859_9=m
-CONFIG_NLS_ISO8859_13=m
-CONFIG_NLS_ISO8859_14=m
-CONFIG_NLS_ISO8859_15=m
-CONFIG_NLS_KOI8_R=m
-CONFIG_NLS_KOI8_U=m
-CONFIG_NLS_UTF8=m
-CONFIG_DEBUG_FS=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-# CONFIG_CRYPTO_HW is not set
-CONFIG_CRC_CCITT=m
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-CONFIG_KERNEL_LZMA=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_RD_GZIP is not set
-CONFIG_RD_LZMA=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_UID16 is not set
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_DEFAULT_NOOP=y
-CONFIG_BF561=y
-CONFIG_IRQ_TIMER0=10
-CONFIG_BFIN561_BLUETECHNIX_CM=y
-# CONFIG_CYCLES_CLOCKSOURCE is not set
-CONFIG_IP_CHECKSUM_L1=y
-CONFIG_SYSCALL_TAB_L1=y
-CONFIG_CPLB_SWITCH_TAB_L1=y
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BFIN_EXTMEM_WRITETHROUGH=y
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_3=0xFFC2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_BINFMT_SHARED_FLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=m
-CONFIG_MTD_PHYSMAP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=y
-CONFIG_SMSC911X=m
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_USB_GADGET=m
-CONFIG_USB_ETH=m
-CONFIG_USB_MASS_STORAGE=m
-CONFIG_USB_G_SERIAL=m
-CONFIG_USB_G_PRINTER=m
-CONFIG_MMC=y
-CONFIG_MMC_SPI=m
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-# CONFIG_DNOTIFY is not set
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_JFFS2_FS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_DEBUG_MMRS=y
-# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_CRC_CCITT=m
-CONFIG_CRC_ITU_T=y
-CONFIG_CRC7=y
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-CONFIG_LOCALVERSION="DNP5370"
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-CONFIG_SLOB=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_BF537=y
-CONFIG_BF_REV_0_3=y
-CONFIG_DNP5370=y
-CONFIG_IRQ_ERROR=7
-# CONFIG_CYCLES_CLOCKSOURCE is not set
-CONFIG_C_CDPRIO=y
-CONFIG_C_AMBEN_B0_B1_B2=y
-CONFIG_PM=y
-# CONFIG_SUSPEND is not set
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_RARP=y
-CONFIG_SYN_COOKIES=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_LLC2=y
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_MTD=y
-CONFIG_MTD_DEBUG=y
-CONFIG_MTD_DEBUG_VERBOSE=1
-CONFIG_MTD_BLOCK=y
-CONFIG_NFTL=y
-CONFIG_NFTL_RW=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_ROM=y
-CONFIG_MTD_ABSENT=y
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_UCLINUX=y
-CONFIG_MTD_PLATRAM=y
-CONFIG_MTD_DATAFLASH=y
-CONFIG_MTD_BLOCK2MTD=y
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_PLATFORM=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-CONFIG_DAVICOM_PHY=y
-CONFIG_NET_ETHERNET=y
-CONFIG_BFIN_MAC=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT is not set
-# CONFIG_SERIO is not set
-# CONFIG_BFIN_DMA_INTERFACE is not set
-# CONFIG_VT is not set
-# CONFIG_DEVKMEM is not set
-CONFIG_BFIN_JTAG_COMM=y
-CONFIG_BFIN_JTAG_COMM_CONSOLE=y
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART0=y
-CONFIG_LEGACY_PTY_COUNT=64
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_BLACKFIN_TWI=y
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_SPI_SPIDEV=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_SENSORS_LM75=y
-# CONFIG_USB_SUPPORT is not set
-CONFIG_MMC=y
-CONFIG_MMC_SPI=y
-CONFIG_DMADEVICES=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-# CONFIG_DNOTIFY is not set
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_FAT_DEFAULT_CODEPAGE=850
-CONFIG_JFFS2_FS=y
-CONFIG_CRAMFS=y
-CONFIG_ROMFS_FS=y
-CONFIG_ROMFS_BACKED_BY_BOTH=y
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_850=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_SHIRQ=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEBUG_OBJECTS=y
-CONFIG_DEBUG_LOCK_ALLOC=y
-CONFIG_DEBUG_KOBJECT=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_VM=y
-CONFIG_DEBUG_MEMORY_INIT=y
-CONFIG_DEBUG_LIST=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_SYSCTL_SYSCALL_CHECK=y
-CONFIG_PAGE_POISONING=y
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_DOUBLEFAULT=y
-CONFIG_CPLB_INFO=y
-CONFIG_CRC_CCITT=y
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_BF532=y
-CONFIG_BF_REV_0_5=y
-CONFIG_H8606_HVSISTEMAS=y
-CONFIG_TIMER0=11
-# CONFIG_CACHELINE_ALIGNED_L1 is not set
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BFIN_GPTIMERS=y
-CONFIG_C_CDPRIO=y
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_PM=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_IPV6 is not set
-CONFIG_IRDA=m
-CONFIG_IRLAN=m
-CONFIG_IRCOMM=m
-CONFIG_IRDA_CACHE_LAST_LSAP=y
-CONFIG_IRTTY_SIR=m
-# CONFIG_WIRELESS is not set
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=y
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_MISC_DEVICES=y
-CONFIG_EEPROM_AT25=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_DM9000=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_KEYBOARD_GPIO=y
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_SPI_SPIDEV=y
-CONFIG_WATCHDOG=y
-CONFIG_SOUND=m
-CONFIG_SND=m
-CONFIG_SND_MIXER_OSS=m
-CONFIG_SND_PCM_OSS=m
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_INTF_DEV_UIE_EMUL=y
-CONFIG_RTC_DRV_BFIN=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-# CONFIG_DNOTIFY is not set
-CONFIG_JFFS2_FS=y
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_NLS=m
-# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
-CONFIG_CPLB_INFO=y
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_HOTPLUG is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_BF532=y
-CONFIG_BF_REV_0_5=y
-CONFIG_BFIN532_IP0X=y
-CONFIG_TIMER0=11
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-# CONFIG_BFIN_ICACHE is not set
-# CONFIG_BFIN_DCACHE is not set
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_0=0xffc2
-CONFIG_BANK_1=0xffc2
-CONFIG_BANK_2=0xffc2
-CONFIG_BANK_3=0xffc2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_PM=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_IPV6 is not set
-CONFIG_NETFILTER=y
-CONFIG_NETFILTER_XT_MATCH_MAC=y
-CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
-CONFIG_IP_NF_IPTABLES=y
-CONFIG_IP_NF_FILTER=y
-CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_MANGLE=y
-# CONFIG_WIRELESS is not set
-CONFIG_MTD=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_UCLINUX=y
-CONFIG_MTD_PLATRAM=y
-CONFIG_MTD_NAND=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_SCSI=y
-# CONFIG_SCSI_PROC_FS is not set
-CONFIG_BLK_DEV_SD=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_DM9000=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_HW_RANDOM=y
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_USB=y
-CONFIG_USB_OTG_WHITELIST=y
-CONFIG_USB_MON=y
-CONFIG_USB_ISP1362_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_MMC=m
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_BFIN=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-# CONFIG_DNOTIFY is not set
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
-CONFIG_CPLB_INFO=y
-CONFIG_CRC_CCITT=y
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BF537=y
-CONFIG_IRQ_TIMER0=12
-CONFIG_PNAV10=y
-# CONFIG_CYCLES_CLOCKSOURCE is not set
-CONFIG_IP_CHECKSUM_L1=y
-CONFIG_SYSCALL_TAB_L1=y
-CONFIG_CPLB_SWITCH_TAB_L1=y
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BFIN_GPTIMERS=y
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_1=0x33B0
-CONFIG_BANK_2=0x33B0
-CONFIG_BANK_3=0x99B2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_UCLINUX=y
-CONFIG_MTD_NAND=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_BFIN_MAC=y
-# CONFIG_BFIN_MAC_USE_L1 is not set
-CONFIG_BFIN_TX_DESC_NUM=100
-CONFIG_BFIN_RX_DESC_NUM=100
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_AD7877=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_UINPUT=y
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART0=y
-CONFIG_SERIAL_BFIN_UART1=y
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_HW_RANDOM=y
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_BLACKFIN_TWI=y
-CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_FB=y
-CONFIG_FIRMWARE_EDID=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-CONFIG_LCD_CLASS_DEVICE=y
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_SOUND=y
-CONFIG_SND=m
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-CONFIG_SOUND_PRIME=y
-# CONFIG_HID is not set
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_BFIN=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-# CONFIG_DNOTIFY is not set
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_SMB_FS=m
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_DEBUG_HUNT_FOR_ZERO is not set
-# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
-# CONFIG_ACCESS_CHECK is not set
-CONFIG_CRYPTO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRC_CCITT=m
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_SYSCTL_SYSCALL is not set
-CONFIG_KALLSYMS_ALL=y
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BF537=y
-CONFIG_IRQ_TIMER0=12
-CONFIG_BOOT_LOAD=0x400000
-CONFIG_CLKIN_HZ=22118400
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_DMA_UNCACHED_2M=y
-CONFIG_C_CDPRIO=y
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_PM=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_IPV6 is not set
-CONFIG_IRDA=m
-CONFIG_IRLAN=m
-CONFIG_IRCOMM=m
-CONFIG_IRDA_CACHE_LAST_LSAP=y
-CONFIG_IRTTY_SIR=m
-# CONFIG_WIRELESS is not set
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_JEDECPROBE=m
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=m
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_UCLINUX=y
-CONFIG_MTD_NAND=m
-CONFIG_BLK_DEV_RAM=y
-CONFIG_MISC_DEVICES=y
-CONFIG_EEPROM_AT25=m
-CONFIG_NETDEVICES=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=m
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_UINPUT=y
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART0=y
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_BLACKFIN_TWI=y
-CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_HWMON=m
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-# CONFIG_HID is not set
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-# CONFIG_DNOTIFY is not set
-CONFIG_JFFS2_FS=m
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_SMB_FS=m
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_DEBUG_INFO=y
-# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
-CONFIG_CPLB_INFO=y
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-CONFIG_KERNEL_LZMA=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_RD_GZIP is not set
-CONFIG_RD_LZMA=y
-CONFIG_EXPERT=y
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BF518=y
-CONFIG_BF_REV_0_1=y
-CONFIG_BFIN518F_TCM=y
-CONFIG_IRQ_TIMER0=12
-# CONFIG_CYCLES_CLOCKSOURCE is not set
-# CONFIG_SCHEDULE_L1 is not set
-# CONFIG_MEMSET_L1 is not set
-# CONFIG_MEMCPY_L1 is not set
-# CONFIG_SYS_BFIN_SPINLOCK_L1 is not set
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BFIN_GPTIMERS=m
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_3=0x99B2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_GEOMETRY=y
-# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
-# CONFIG_MTD_CFI_I2 is not set
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=m
-CONFIG_MTD_PHYSMAP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_BFIN_MAC=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_MISC=y
-# CONFIG_SERIO is not set
-# CONFIG_DEVKMEM is not set
-CONFIG_BFIN_JTAG_COMM=m
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART0=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_BLACKFIN_TWI=y
-CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-# CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
-CONFIG_MMC=y
-CONFIG_MMC_DEBUG=y
-CONFIG_MMC_SPI=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_BFIN=y
-CONFIG_EXT2_FS=y
-# CONFIG_DNOTIFY is not set
-CONFIG_VFAT_FS=m
-# CONFIG_MISC_FILESYSTEMS is not set
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS_CODEPAGE_437=m
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_UTF8=m
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_SHIRQ=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_MMRS=y
-CONFIG_DEBUG_HWERR=y
-CONFIG_EXACT_HWERR=y
-CONFIG_DEBUG_DOUBLEFAULT=y
-CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_CRYPTO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRC_CCITT=m
+++ /dev/null
-CONFIG_EXPERIMENTAL=y
-CONFIG_KERNEL_LZMA=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_RD_GZIP is not set
-CONFIG_RD_LZMA=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_UID16 is not set
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_DEFAULT_NOOP=y
-CONFIG_BF537=y
-CONFIG_IRQ_TIMER0=12
-CONFIG_BFIN537_BLUETECHNIX_TCM=y
-# CONFIG_CYCLES_CLOCKSOURCE is not set
-CONFIG_IP_CHECKSUM_L1=y
-CONFIG_SYSCALL_TAB_L1=y
-CONFIG_CPLB_SWITCH_TAB_L1=y
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_3=0xFFC2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_BINFMT_SHARED_FLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=m
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_GPIO_ADDR=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_BFIN_MAC=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART0=y
-CONFIG_SERIAL_BFIN_UART1=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_ETH=y
-CONFIG_MMC=y
-CONFIG_MMC_SPI=m
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-# CONFIG_DNOTIFY is not set
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_JFFS2_FS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_DEBUG_MMRS=y
-# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRC_ITU_T=y
-CONFIG_CRC7=y
+++ /dev/null
-generic-y += bugs.h
-generic-y += current.h
-generic-y += device.h
-generic-y += div64.h
-generic-y += emergency-restart.h
-generic-y += extable.h
-generic-y += fb.h
-generic-y += futex.h
-generic-y += hw_irq.h
-generic-y += irq_regs.h
-generic-y += irq_work.h
-generic-y += kdebug.h
-generic-y += kmap_types.h
-generic-y += kprobes.h
-generic-y += local.h
-generic-y += local64.h
-generic-y += mcs_spinlock.h
-generic-y += mm-arch-hooks.h
-generic-y += percpu.h
-generic-y += pgalloc.h
-generic-y += preempt.h
-generic-y += serial.h
-generic-y += topology.h
-generic-y += trace_clock.h
-generic-y += unaligned.h
-generic-y += user.h
-generic-y += word-at-a-time.h
-generic-y += xor.h
+++ /dev/null
-#include <generated/asm-offsets.h>
+++ /dev/null
-/*
- * Copyright 2004-2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ARCH_BLACKFIN_ATOMIC__
-#define __ARCH_BLACKFIN_ATOMIC__
-
-#include <asm/cmpxchg.h>
-
-#ifdef CONFIG_SMP
-
-#include <asm/barrier.h>
-#include <linux/linkage.h>
-#include <linux/types.h>
-
-asmlinkage int __raw_uncached_fetch_asm(const volatile int *ptr);
-asmlinkage int __raw_atomic_add_asm(volatile int *ptr, int value);
-asmlinkage int __raw_atomic_xadd_asm(volatile int *ptr, int value);
-
-asmlinkage int __raw_atomic_and_asm(volatile int *ptr, int value);
-asmlinkage int __raw_atomic_or_asm(volatile int *ptr, int value);
-asmlinkage int __raw_atomic_xor_asm(volatile int *ptr, int value);
-asmlinkage int __raw_atomic_test_asm(const volatile int *ptr, int value);
-
-#define atomic_read(v) __raw_uncached_fetch_asm(&(v)->counter)
-
-#define atomic_add_return(i, v) __raw_atomic_add_asm(&(v)->counter, i)
-#define atomic_sub_return(i, v) __raw_atomic_add_asm(&(v)->counter, -(i))
-
-#define atomic_fetch_add(i, v) __raw_atomic_xadd_asm(&(v)->counter, i)
-#define atomic_fetch_sub(i, v) __raw_atomic_xadd_asm(&(v)->counter, -(i))
-
-#define atomic_or(i, v) (void)__raw_atomic_or_asm(&(v)->counter, i)
-#define atomic_and(i, v) (void)__raw_atomic_and_asm(&(v)->counter, i)
-#define atomic_xor(i, v) (void)__raw_atomic_xor_asm(&(v)->counter, i)
-
-#define atomic_fetch_or(i, v) __raw_atomic_or_asm(&(v)->counter, i)
-#define atomic_fetch_and(i, v) __raw_atomic_and_asm(&(v)->counter, i)
-#define atomic_fetch_xor(i, v) __raw_atomic_xor_asm(&(v)->counter, i)
-
-#endif
-
-#include <asm-generic/atomic.h>
-
-#endif
+++ /dev/null
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * Tony Kou (tonyko@lineo.ca)
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _BLACKFIN_BARRIER_H
-#define _BLACKFIN_BARRIER_H
-
-#include <asm/cache.h>
-
-#define nop() __asm__ __volatile__ ("nop;\n\t" : : )
-
-/*
- * Force strict CPU ordering.
- */
-#ifdef CONFIG_SMP
-
-#ifdef __ARCH_SYNC_CORE_DCACHE
-/* Force Core data cache coherence */
-# define mb() do { barrier(); smp_check_barrier(); smp_mark_barrier(); } while (0)
-# define rmb() do { barrier(); smp_check_barrier(); } while (0)
-# define wmb() do { barrier(); smp_mark_barrier(); } while (0)
-/*
- * read_barrier_depends - Flush all pending reads that subsequents reads
- * depend on.
- *
- * No data-dependent reads from memory-like regions are ever reordered
- * over this barrier. All reads preceding this primitive are guaranteed
- * to access memory (but not necessarily other CPUs' caches) before any
- * reads following this primitive that depend on the data return by
- * any of the preceding reads. This primitive is much lighter weight than
- * rmb() on most CPUs, and is never heavier weight than is
- * rmb().
- *
- * These ordering constraints are respected by both the local CPU
- * and the compiler.
- *
- * Ordering is not guaranteed by anything other than these primitives,
- * not even by data dependencies. See the documentation for
- * memory_barrier() for examples and URLs to more information.
- *
- * For example, the following code would force ordering (the initial
- * value of "a" is zero, "b" is one, and "p" is "&a"):
- *
- * <programlisting>
- * CPU 0 CPU 1
- *
- * b = 2;
- * memory_barrier();
- * p = &b; q = p;
- * read_barrier_depends();
- * d = *q;
- * </programlisting>
- *
- * because the read of "*q" depends on the read of "p" and these
- * two reads are separated by a read_barrier_depends(). However,
- * the following code, with the same initial values for "a" and "b":
- *
- * <programlisting>
- * CPU 0 CPU 1
- *
- * a = 2;
- * memory_barrier();
- * b = 3; y = b;
- * read_barrier_depends();
- * x = a;
- * </programlisting>
- *
- * does not enforce ordering, since there is no data dependency between
- * the read of "a" and the read of "b". Therefore, on some CPUs, such
- * as Alpha, "y" could be set to 3 and "x" to 0. Use rmb()
- * in cases like this where there are no data dependencies.
- */
-# define read_barrier_depends() do { barrier(); smp_check_barrier(); } while (0)
-#endif
-
-#endif /* !CONFIG_SMP */
-
-#define __smp_mb__before_atomic() barrier()
-#define __smp_mb__after_atomic() barrier()
-
-#include <asm-generic/barrier.h>
-
-#endif /* _BLACKFIN_BARRIER_H */
+++ /dev/null
-/*
- * Global extern defines for blackfin
- *
- * Copyright 2006-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BFIN_GLOBAL_H_
-#define _BFIN_GLOBAL_H_
-
-#ifndef __ASSEMBLY__
-
-#include <linux/linkage.h>
-#include <linux/types.h>
-
-#if defined(CONFIG_DMA_UNCACHED_32M)
-# define DMA_UNCACHED_REGION (32 * 1024 * 1024)
-#elif defined(CONFIG_DMA_UNCACHED_16M)
-# define DMA_UNCACHED_REGION (16 * 1024 * 1024)
-#elif defined(CONFIG_DMA_UNCACHED_8M)
-# define DMA_UNCACHED_REGION (8 * 1024 * 1024)
-#elif defined(CONFIG_DMA_UNCACHED_4M)
-# define DMA_UNCACHED_REGION (4 * 1024 * 1024)
-#elif defined(CONFIG_DMA_UNCACHED_2M)
-# define DMA_UNCACHED_REGION (2 * 1024 * 1024)
-#elif defined(CONFIG_DMA_UNCACHED_1M)
-# define DMA_UNCACHED_REGION (1024 * 1024)
-#elif defined(CONFIG_DMA_UNCACHED_512K)
-# define DMA_UNCACHED_REGION (512 * 1024)
-#elif defined(CONFIG_DMA_UNCACHED_256K)
-# define DMA_UNCACHED_REGION (256 * 1024)
-#elif defined(CONFIG_DMA_UNCACHED_128K)
-# define DMA_UNCACHED_REGION (128 * 1024)
-#else
-# define DMA_UNCACHED_REGION (0)
-#endif
-
-extern void bfin_setup_caches(unsigned int cpu);
-extern void bfin_setup_cpudata(unsigned int cpu);
-
-extern unsigned long get_cclk(void);
-extern unsigned long get_sclk(void);
-#ifdef CONFIG_BF60x
-extern unsigned long get_sclk0(void);
-extern unsigned long get_sclk1(void);
-extern unsigned long get_dclk(void);
-#endif
-extern unsigned long sclk_to_usecs(unsigned long sclk);
-extern unsigned long usecs_to_sclk(unsigned long usecs);
-
-struct pt_regs;
-#if defined(CONFIG_DEBUG_VERBOSE)
-extern void dump_bfin_process(struct pt_regs *regs);
-extern void dump_bfin_mem(struct pt_regs *regs);
-extern void dump_bfin_trace_buffer(void);
-#else
-#define dump_bfin_process(regs)
-#define dump_bfin_mem(regs)
-#define dump_bfin_trace_buffer()
-#endif
-
-extern void *l1_data_A_sram_alloc(size_t);
-extern void *l1_data_B_sram_alloc(size_t);
-extern void *l1_inst_sram_alloc(size_t);
-extern void *l1_data_sram_alloc(size_t);
-extern void *l1_data_sram_zalloc(size_t);
-extern void *l2_sram_alloc(size_t);
-extern void *l2_sram_zalloc(size_t);
-extern int l1_data_A_sram_free(const void*);
-extern int l1_data_B_sram_free(const void*);
-extern int l1_inst_sram_free(const void*);
-extern int l1_data_sram_free(const void*);
-extern int l2_sram_free(const void *);
-extern int sram_free(const void*);
-
-#define L1_INST_SRAM 0x00000001
-#define L1_DATA_A_SRAM 0x00000002
-#define L1_DATA_B_SRAM 0x00000004
-#define L1_DATA_SRAM 0x00000006
-#define L2_SRAM 0x00000008
-extern void *sram_alloc_with_lsl(size_t, unsigned long);
-extern int sram_free_with_lsl(const void*);
-
-extern void *isram_memcpy(void *dest, const void *src, size_t n);
-
-extern const char bfin_board_name[];
-
-extern unsigned long bfin_sic_iwr[];
-extern unsigned vr_wakeup;
-extern u16 _bfin_swrst; /* shadow for Software Reset Register (SWRST) */
-
-#endif
-
-#endif /* _BLACKFIN_H_ */
+++ /dev/null
-/*
- * Blackfin LCD Framebuffer driver SHARP LQ035Q1DH02
- *
- * Copyright 2008-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef BFIN_LQ035Q1_H
-#define BFIN_LQ035Q1_H
-
-/*
- * LCD Modes
- */
-#define LQ035_RL (0 << 8) /* Right -> Left Scan */
-#define LQ035_LR (1 << 8) /* Left -> Right Scan */
-#define LQ035_TB (1 << 9) /* Top -> Botton Scan */
-#define LQ035_BT (0 << 9) /* Botton -> Top Scan */
-#define LQ035_BGR (1 << 11) /* Use BGR format */
-#define LQ035_RGB (0 << 11) /* Use RGB format */
-#define LQ035_NORM (1 << 13) /* Reversal */
-#define LQ035_REV (0 << 13) /* Reversal */
-
-/*
- * PPI Modes
- */
-
-#define USE_RGB565_16_BIT_PPI 1
-#define USE_RGB565_8_BIT_PPI 2
-#define USE_RGB888_8_BIT_PPI 3
-
-struct bfin_lq035q1fb_disp_info {
-
- unsigned mode;
- unsigned ppi_mode;
- /* GPIOs */
- int use_bl;
- unsigned gpio_bl;
-};
-
-#endif /* BFIN_LQ035Q1_H */
+++ /dev/null
-/*
- * Blackfin On-Chip SPI Driver
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _SPI_CHANNEL_H_
-#define _SPI_CHANNEL_H_
-
-#define MIN_SPI_BAUD_VAL 2
-
-#define BIT_CTL_ENABLE 0x4000
-#define BIT_CTL_OPENDRAIN 0x2000
-#define BIT_CTL_MASTER 0x1000
-#define BIT_CTL_CPOL 0x0800
-#define BIT_CTL_CPHA 0x0400
-#define BIT_CTL_LSBF 0x0200
-#define BIT_CTL_WORDSIZE 0x0100
-#define BIT_CTL_EMISO 0x0020
-#define BIT_CTL_PSSE 0x0010
-#define BIT_CTL_GM 0x0008
-#define BIT_CTL_SZ 0x0004
-#define BIT_CTL_RXMOD 0x0000
-#define BIT_CTL_TXMOD 0x0001
-#define BIT_CTL_TIMOD_DMA_TX 0x0003
-#define BIT_CTL_TIMOD_DMA_RX 0x0002
-#define BIT_CTL_SENDOPT 0x0004
-#define BIT_CTL_TIMOD 0x0003
-
-#define BIT_STAT_SPIF 0x0001
-#define BIT_STAT_MODF 0x0002
-#define BIT_STAT_TXE 0x0004
-#define BIT_STAT_TXS 0x0008
-#define BIT_STAT_RBSY 0x0010
-#define BIT_STAT_RXS 0x0020
-#define BIT_STAT_TXCOL 0x0040
-#define BIT_STAT_CLR 0xFFFF
-
-#define BIT_STU_SENDOVER 0x0001
-#define BIT_STU_RECVFULL 0x0020
-
-/*
- * All Blackfin system MMRs are padded to 32bits even if the register
- * itself is only 16bits. So use a helper macro to streamline this.
- */
-#define __BFP(m) u16 m; u16 __pad_##m
-
-/*
- * bfin spi registers layout
- */
-struct bfin_spi_regs {
- __BFP(ctl);
- __BFP(flg);
- __BFP(stat);
- __BFP(tdbr);
- __BFP(rdbr);
- __BFP(baud);
- __BFP(shadow);
-};
-
-#undef __BFP
-
-#define MAX_CTRL_CS 8 /* cs in spi controller */
-
-/* device.platform_data for SSP controller devices */
-struct bfin5xx_spi_master {
- u16 num_chipselect;
- u8 enable_dma;
- u16 pin_req[7];
-};
-
-/* spi_board_info.controller_data for SPI slave devices,
- * copied to spi_device.platform_data ... mostly for dma tuning
- */
-struct bfin5xx_spi_chip {
- u16 ctl_reg;
- u8 enable_dma;
- u16 cs_chg_udelay; /* Some devices require 16-bit delays */
- /* Value to send if no TX value is supplied, usually 0x0 or 0xFFFF */
- u16 idle_tx_val;
- u8 pio_interrupt; /* Enable spi data irq */
-};
-
-#endif /* _SPI_CHANNEL_H_ */
+++ /dev/null
-/*
- * bfin_can.h - interface to Blackfin CANs
- *
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_BFIN_CAN_H__
-#define __ASM_BFIN_CAN_H__
-
-/*
- * transmit and receive channels
- */
-#define TRANSMIT_CHL 24
-#define RECEIVE_STD_CHL 0
-#define RECEIVE_EXT_CHL 4
-#define RECEIVE_RTR_CHL 8
-#define RECEIVE_EXT_RTR_CHL 12
-#define MAX_CHL_NUMBER 32
-
-/*
- * All Blackfin system MMRs are padded to 32bits even if the register
- * itself is only 16bits. So use a helper macro to streamline this.
- */
-#define __BFP(m) u16 m; u16 __pad_##m
-
-/*
- * bfin can registers layout
- */
-struct bfin_can_mask_regs {
- __BFP(aml);
- __BFP(amh);
-};
-
-struct bfin_can_channel_regs {
- /* data[0,2,4,6] -> data{0,1,2,3} while data[1,3,5,7] is padding */
- u16 data[8];
- __BFP(dlc);
- __BFP(tsv);
- __BFP(id0);
- __BFP(id1);
-};
-
-struct bfin_can_regs {
- /*
- * global control and status registers
- */
- __BFP(mc1); /* offset 0x00 */
- __BFP(md1); /* offset 0x04 */
- __BFP(trs1); /* offset 0x08 */
- __BFP(trr1); /* offset 0x0c */
- __BFP(ta1); /* offset 0x10 */
- __BFP(aa1); /* offset 0x14 */
- __BFP(rmp1); /* offset 0x18 */
- __BFP(rml1); /* offset 0x1c */
- __BFP(mbtif1); /* offset 0x20 */
- __BFP(mbrif1); /* offset 0x24 */
- __BFP(mbim1); /* offset 0x28 */
- __BFP(rfh1); /* offset 0x2c */
- __BFP(opss1); /* offset 0x30 */
- u32 __pad1[3];
- __BFP(mc2); /* offset 0x40 */
- __BFP(md2); /* offset 0x44 */
- __BFP(trs2); /* offset 0x48 */
- __BFP(trr2); /* offset 0x4c */
- __BFP(ta2); /* offset 0x50 */
- __BFP(aa2); /* offset 0x54 */
- __BFP(rmp2); /* offset 0x58 */
- __BFP(rml2); /* offset 0x5c */
- __BFP(mbtif2); /* offset 0x60 */
- __BFP(mbrif2); /* offset 0x64 */
- __BFP(mbim2); /* offset 0x68 */
- __BFP(rfh2); /* offset 0x6c */
- __BFP(opss2); /* offset 0x70 */
- u32 __pad2[3];
- __BFP(clock); /* offset 0x80 */
- __BFP(timing); /* offset 0x84 */
- __BFP(debug); /* offset 0x88 */
- __BFP(status); /* offset 0x8c */
- __BFP(cec); /* offset 0x90 */
- __BFP(gis); /* offset 0x94 */
- __BFP(gim); /* offset 0x98 */
- __BFP(gif); /* offset 0x9c */
- __BFP(control); /* offset 0xa0 */
- __BFP(intr); /* offset 0xa4 */
- __BFP(version); /* offset 0xa8 */
- __BFP(mbtd); /* offset 0xac */
- __BFP(ewr); /* offset 0xb0 */
- __BFP(esr); /* offset 0xb4 */
- u32 __pad3[2];
- __BFP(ucreg); /* offset 0xc0 */
- __BFP(uccnt); /* offset 0xc4 */
- __BFP(ucrc); /* offset 0xc8 */
- __BFP(uccnf); /* offset 0xcc */
- u32 __pad4[1];
- __BFP(version2); /* offset 0xd4 */
- u32 __pad5[10];
-
- /*
- * channel(mailbox) mask and message registers
- */
- struct bfin_can_mask_regs msk[MAX_CHL_NUMBER]; /* offset 0x100 */
- struct bfin_can_channel_regs chl[MAX_CHL_NUMBER]; /* offset 0x200 */
-};
-
-#undef __BFP
-
-/* CAN_CONTROL Masks */
-#define SRS 0x0001 /* Software Reset */
-#define DNM 0x0002 /* Device Net Mode */
-#define ABO 0x0004 /* Auto-Bus On Enable */
-#define TXPRIO 0x0008 /* TX Priority (Priority/Mailbox*) */
-#define WBA 0x0010 /* Wake-Up On CAN Bus Activity Enable */
-#define SMR 0x0020 /* Sleep Mode Request */
-#define CSR 0x0040 /* CAN Suspend Mode Request */
-#define CCR 0x0080 /* CAN Configuration Mode Request */
-
-/* CAN_STATUS Masks */
-#define WT 0x0001 /* TX Warning Flag */
-#define WR 0x0002 /* RX Warning Flag */
-#define EP 0x0004 /* Error Passive Mode */
-#define EBO 0x0008 /* Error Bus Off Mode */
-#define SMA 0x0020 /* Sleep Mode Acknowledge */
-#define CSA 0x0040 /* Suspend Mode Acknowledge */
-#define CCA 0x0080 /* Configuration Mode Acknowledge */
-#define MBPTR 0x1F00 /* Mailbox Pointer */
-#define TRM 0x4000 /* Transmit Mode */
-#define REC 0x8000 /* Receive Mode */
-
-/* CAN_CLOCK Masks */
-#define BRP 0x03FF /* Bit-Rate Pre-Scaler */
-
-/* CAN_TIMING Masks */
-#define TSEG1 0x000F /* Time Segment 1 */
-#define TSEG2 0x0070 /* Time Segment 2 */
-#define SAM 0x0080 /* Sampling */
-#define SJW 0x0300 /* Synchronization Jump Width */
-
-/* CAN_DEBUG Masks */
-#define DEC 0x0001 /* Disable CAN Error Counters */
-#define DRI 0x0002 /* Disable CAN RX Input */
-#define DTO 0x0004 /* Disable CAN TX Output */
-#define DIL 0x0008 /* Disable CAN Internal Loop */
-#define MAA 0x0010 /* Mode Auto-Acknowledge Enable */
-#define MRB 0x0020 /* Mode Read Back Enable */
-#define CDE 0x8000 /* CAN Debug Enable */
-
-/* CAN_CEC Masks */
-#define RXECNT 0x00FF /* Receive Error Counter */
-#define TXECNT 0xFF00 /* Transmit Error Counter */
-
-/* CAN_INTR Masks */
-#define MBRIRQ 0x0001 /* Mailbox Receive Interrupt */
-#define MBTIRQ 0x0002 /* Mailbox Transmit Interrupt */
-#define GIRQ 0x0004 /* Global Interrupt */
-#define SMACK 0x0008 /* Sleep Mode Acknowledge */
-#define CANTX 0x0040 /* CAN TX Bus Value */
-#define CANRX 0x0080 /* CAN RX Bus Value */
-
-/* CAN_MBxx_ID1 and CAN_MBxx_ID0 Masks */
-#define DFC 0xFFFF /* Data Filtering Code (If Enabled) (ID0) */
-#define EXTID_LO 0xFFFF /* Lower 16 Bits of Extended Identifier (ID0) */
-#define EXTID_HI 0x0003 /* Upper 2 Bits of Extended Identifier (ID1) */
-#define BASEID 0x1FFC /* Base Identifier */
-#define IDE 0x2000 /* Identifier Extension */
-#define RTR 0x4000 /* Remote Frame Transmission Request */
-#define AME 0x8000 /* Acceptance Mask Enable */
-
-/* CAN_MBxx_TIMESTAMP Masks */
-#define TSV 0xFFFF /* Timestamp */
-
-/* CAN_MBxx_LENGTH Masks */
-#define DLC 0x000F /* Data Length Code */
-
-/* CAN_AMxxH and CAN_AMxxL Masks */
-#define DFM 0xFFFF /* Data Field Mask (If Enabled) (CAN_AMxxL) */
-#define EXTID_LO 0xFFFF /* Lower 16 Bits of Extended Identifier (CAN_AMxxL) */
-#define EXTID_HI 0x0003 /* Upper 2 Bits of Extended Identifier (CAN_AMxxH) */
-#define BASEID 0x1FFC /* Base Identifier */
-#define AMIDE 0x2000 /* Acceptance Mask ID Extension Enable */
-#define FMD 0x4000 /* Full Mask Data Field Enable */
-#define FDF 0x8000 /* Filter On Data Field Enable */
-
-/* CAN_MC1 Masks */
-#define MC0 0x0001 /* Enable Mailbox 0 */
-#define MC1 0x0002 /* Enable Mailbox 1 */
-#define MC2 0x0004 /* Enable Mailbox 2 */
-#define MC3 0x0008 /* Enable Mailbox 3 */
-#define MC4 0x0010 /* Enable Mailbox 4 */
-#define MC5 0x0020 /* Enable Mailbox 5 */
-#define MC6 0x0040 /* Enable Mailbox 6 */
-#define MC7 0x0080 /* Enable Mailbox 7 */
-#define MC8 0x0100 /* Enable Mailbox 8 */
-#define MC9 0x0200 /* Enable Mailbox 9 */
-#define MC10 0x0400 /* Enable Mailbox 10 */
-#define MC11 0x0800 /* Enable Mailbox 11 */
-#define MC12 0x1000 /* Enable Mailbox 12 */
-#define MC13 0x2000 /* Enable Mailbox 13 */
-#define MC14 0x4000 /* Enable Mailbox 14 */
-#define MC15 0x8000 /* Enable Mailbox 15 */
-
-/* CAN_MC2 Masks */
-#define MC16 0x0001 /* Enable Mailbox 16 */
-#define MC17 0x0002 /* Enable Mailbox 17 */
-#define MC18 0x0004 /* Enable Mailbox 18 */
-#define MC19 0x0008 /* Enable Mailbox 19 */
-#define MC20 0x0010 /* Enable Mailbox 20 */
-#define MC21 0x0020 /* Enable Mailbox 21 */
-#define MC22 0x0040 /* Enable Mailbox 22 */
-#define MC23 0x0080 /* Enable Mailbox 23 */
-#define MC24 0x0100 /* Enable Mailbox 24 */
-#define MC25 0x0200 /* Enable Mailbox 25 */
-#define MC26 0x0400 /* Enable Mailbox 26 */
-#define MC27 0x0800 /* Enable Mailbox 27 */
-#define MC28 0x1000 /* Enable Mailbox 28 */
-#define MC29 0x2000 /* Enable Mailbox 29 */
-#define MC30 0x4000 /* Enable Mailbox 30 */
-#define MC31 0x8000 /* Enable Mailbox 31 */
-
-/* CAN_MD1 Masks */
-#define MD0 0x0001 /* Enable Mailbox 0 For Receive */
-#define MD1 0x0002 /* Enable Mailbox 1 For Receive */
-#define MD2 0x0004 /* Enable Mailbox 2 For Receive */
-#define MD3 0x0008 /* Enable Mailbox 3 For Receive */
-#define MD4 0x0010 /* Enable Mailbox 4 For Receive */
-#define MD5 0x0020 /* Enable Mailbox 5 For Receive */
-#define MD6 0x0040 /* Enable Mailbox 6 For Receive */
-#define MD7 0x0080 /* Enable Mailbox 7 For Receive */
-#define MD8 0x0100 /* Enable Mailbox 8 For Receive */
-#define MD9 0x0200 /* Enable Mailbox 9 For Receive */
-#define MD10 0x0400 /* Enable Mailbox 10 For Receive */
-#define MD11 0x0800 /* Enable Mailbox 11 For Receive */
-#define MD12 0x1000 /* Enable Mailbox 12 For Receive */
-#define MD13 0x2000 /* Enable Mailbox 13 For Receive */
-#define MD14 0x4000 /* Enable Mailbox 14 For Receive */
-#define MD15 0x8000 /* Enable Mailbox 15 For Receive */
-
-/* CAN_MD2 Masks */
-#define MD16 0x0001 /* Enable Mailbox 16 For Receive */
-#define MD17 0x0002 /* Enable Mailbox 17 For Receive */
-#define MD18 0x0004 /* Enable Mailbox 18 For Receive */
-#define MD19 0x0008 /* Enable Mailbox 19 For Receive */
-#define MD20 0x0010 /* Enable Mailbox 20 For Receive */
-#define MD21 0x0020 /* Enable Mailbox 21 For Receive */
-#define MD22 0x0040 /* Enable Mailbox 22 For Receive */
-#define MD23 0x0080 /* Enable Mailbox 23 For Receive */
-#define MD24 0x0100 /* Enable Mailbox 24 For Receive */
-#define MD25 0x0200 /* Enable Mailbox 25 For Receive */
-#define MD26 0x0400 /* Enable Mailbox 26 For Receive */
-#define MD27 0x0800 /* Enable Mailbox 27 For Receive */
-#define MD28 0x1000 /* Enable Mailbox 28 For Receive */
-#define MD29 0x2000 /* Enable Mailbox 29 For Receive */
-#define MD30 0x4000 /* Enable Mailbox 30 For Receive */
-#define MD31 0x8000 /* Enable Mailbox 31 For Receive */
-
-/* CAN_RMP1 Masks */
-#define RMP0 0x0001 /* RX Message Pending In Mailbox 0 */
-#define RMP1 0x0002 /* RX Message Pending In Mailbox 1 */
-#define RMP2 0x0004 /* RX Message Pending In Mailbox 2 */
-#define RMP3 0x0008 /* RX Message Pending In Mailbox 3 */
-#define RMP4 0x0010 /* RX Message Pending In Mailbox 4 */
-#define RMP5 0x0020 /* RX Message Pending In Mailbox 5 */
-#define RMP6 0x0040 /* RX Message Pending In Mailbox 6 */
-#define RMP7 0x0080 /* RX Message Pending In Mailbox 7 */
-#define RMP8 0x0100 /* RX Message Pending In Mailbox 8 */
-#define RMP9 0x0200 /* RX Message Pending In Mailbox 9 */
-#define RMP10 0x0400 /* RX Message Pending In Mailbox 10 */
-#define RMP11 0x0800 /* RX Message Pending In Mailbox 11 */
-#define RMP12 0x1000 /* RX Message Pending In Mailbox 12 */
-#define RMP13 0x2000 /* RX Message Pending In Mailbox 13 */
-#define RMP14 0x4000 /* RX Message Pending In Mailbox 14 */
-#define RMP15 0x8000 /* RX Message Pending In Mailbox 15 */
-
-/* CAN_RMP2 Masks */
-#define RMP16 0x0001 /* RX Message Pending In Mailbox 16 */
-#define RMP17 0x0002 /* RX Message Pending In Mailbox 17 */
-#define RMP18 0x0004 /* RX Message Pending In Mailbox 18 */
-#define RMP19 0x0008 /* RX Message Pending In Mailbox 19 */
-#define RMP20 0x0010 /* RX Message Pending In Mailbox 20 */
-#define RMP21 0x0020 /* RX Message Pending In Mailbox 21 */
-#define RMP22 0x0040 /* RX Message Pending In Mailbox 22 */
-#define RMP23 0x0080 /* RX Message Pending In Mailbox 23 */
-#define RMP24 0x0100 /* RX Message Pending In Mailbox 24 */
-#define RMP25 0x0200 /* RX Message Pending In Mailbox 25 */
-#define RMP26 0x0400 /* RX Message Pending In Mailbox 26 */
-#define RMP27 0x0800 /* RX Message Pending In Mailbox 27 */
-#define RMP28 0x1000 /* RX Message Pending In Mailbox 28 */
-#define RMP29 0x2000 /* RX Message Pending In Mailbox 29 */
-#define RMP30 0x4000 /* RX Message Pending In Mailbox 30 */
-#define RMP31 0x8000 /* RX Message Pending In Mailbox 31 */
-
-/* CAN_RML1 Masks */
-#define RML0 0x0001 /* RX Message Lost In Mailbox 0 */
-#define RML1 0x0002 /* RX Message Lost In Mailbox 1 */
-#define RML2 0x0004 /* RX Message Lost In Mailbox 2 */
-#define RML3 0x0008 /* RX Message Lost In Mailbox 3 */
-#define RML4 0x0010 /* RX Message Lost In Mailbox 4 */
-#define RML5 0x0020 /* RX Message Lost In Mailbox 5 */
-#define RML6 0x0040 /* RX Message Lost In Mailbox 6 */
-#define RML7 0x0080 /* RX Message Lost In Mailbox 7 */
-#define RML8 0x0100 /* RX Message Lost In Mailbox 8 */
-#define RML9 0x0200 /* RX Message Lost In Mailbox 9 */
-#define RML10 0x0400 /* RX Message Lost In Mailbox 10 */
-#define RML11 0x0800 /* RX Message Lost In Mailbox 11 */
-#define RML12 0x1000 /* RX Message Lost In Mailbox 12 */
-#define RML13 0x2000 /* RX Message Lost In Mailbox 13 */
-#define RML14 0x4000 /* RX Message Lost In Mailbox 14 */
-#define RML15 0x8000 /* RX Message Lost In Mailbox 15 */
-
-/* CAN_RML2 Masks */
-#define RML16 0x0001 /* RX Message Lost In Mailbox 16 */
-#define RML17 0x0002 /* RX Message Lost In Mailbox 17 */
-#define RML18 0x0004 /* RX Message Lost In Mailbox 18 */
-#define RML19 0x0008 /* RX Message Lost In Mailbox 19 */
-#define RML20 0x0010 /* RX Message Lost In Mailbox 20 */
-#define RML21 0x0020 /* RX Message Lost In Mailbox 21 */
-#define RML22 0x0040 /* RX Message Lost In Mailbox 22 */
-#define RML23 0x0080 /* RX Message Lost In Mailbox 23 */
-#define RML24 0x0100 /* RX Message Lost In Mailbox 24 */
-#define RML25 0x0200 /* RX Message Lost In Mailbox 25 */
-#define RML26 0x0400 /* RX Message Lost In Mailbox 26 */
-#define RML27 0x0800 /* RX Message Lost In Mailbox 27 */
-#define RML28 0x1000 /* RX Message Lost In Mailbox 28 */
-#define RML29 0x2000 /* RX Message Lost In Mailbox 29 */
-#define RML30 0x4000 /* RX Message Lost In Mailbox 30 */
-#define RML31 0x8000 /* RX Message Lost In Mailbox 31 */
-
-/* CAN_OPSS1 Masks */
-#define OPSS0 0x0001 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 0 */
-#define OPSS1 0x0002 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 1 */
-#define OPSS2 0x0004 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 2 */
-#define OPSS3 0x0008 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 3 */
-#define OPSS4 0x0010 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 4 */
-#define OPSS5 0x0020 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 5 */
-#define OPSS6 0x0040 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 6 */
-#define OPSS7 0x0080 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 7 */
-#define OPSS8 0x0100 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 8 */
-#define OPSS9 0x0200 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 9 */
-#define OPSS10 0x0400 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 10 */
-#define OPSS11 0x0800 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 11 */
-#define OPSS12 0x1000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 12 */
-#define OPSS13 0x2000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 13 */
-#define OPSS14 0x4000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 14 */
-#define OPSS15 0x8000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 15 */
-
-/* CAN_OPSS2 Masks */
-#define OPSS16 0x0001 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 16 */
-#define OPSS17 0x0002 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 17 */
-#define OPSS18 0x0004 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 18 */
-#define OPSS19 0x0008 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 19 */
-#define OPSS20 0x0010 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 20 */
-#define OPSS21 0x0020 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 21 */
-#define OPSS22 0x0040 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 22 */
-#define OPSS23 0x0080 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 23 */
-#define OPSS24 0x0100 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 24 */
-#define OPSS25 0x0200 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 25 */
-#define OPSS26 0x0400 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 26 */
-#define OPSS27 0x0800 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 27 */
-#define OPSS28 0x1000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 28 */
-#define OPSS29 0x2000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 29 */
-#define OPSS30 0x4000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 30 */
-#define OPSS31 0x8000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 31 */
-
-/* CAN_TRR1 Masks */
-#define TRR0 0x0001 /* Deny But Don't Lock Access To Mailbox 0 */
-#define TRR1 0x0002 /* Deny But Don't Lock Access To Mailbox 1 */
-#define TRR2 0x0004 /* Deny But Don't Lock Access To Mailbox 2 */
-#define TRR3 0x0008 /* Deny But Don't Lock Access To Mailbox 3 */
-#define TRR4 0x0010 /* Deny But Don't Lock Access To Mailbox 4 */
-#define TRR5 0x0020 /* Deny But Don't Lock Access To Mailbox 5 */
-#define TRR6 0x0040 /* Deny But Don't Lock Access To Mailbox 6 */
-#define TRR7 0x0080 /* Deny But Don't Lock Access To Mailbox 7 */
-#define TRR8 0x0100 /* Deny But Don't Lock Access To Mailbox 8 */
-#define TRR9 0x0200 /* Deny But Don't Lock Access To Mailbox 9 */
-#define TRR10 0x0400 /* Deny But Don't Lock Access To Mailbox 10 */
-#define TRR11 0x0800 /* Deny But Don't Lock Access To Mailbox 11 */
-#define TRR12 0x1000 /* Deny But Don't Lock Access To Mailbox 12 */
-#define TRR13 0x2000 /* Deny But Don't Lock Access To Mailbox 13 */
-#define TRR14 0x4000 /* Deny But Don't Lock Access To Mailbox 14 */
-#define TRR15 0x8000 /* Deny But Don't Lock Access To Mailbox 15 */
-
-/* CAN_TRR2 Masks */
-#define TRR16 0x0001 /* Deny But Don't Lock Access To Mailbox 16 */
-#define TRR17 0x0002 /* Deny But Don't Lock Access To Mailbox 17 */
-#define TRR18 0x0004 /* Deny But Don't Lock Access To Mailbox 18 */
-#define TRR19 0x0008 /* Deny But Don't Lock Access To Mailbox 19 */
-#define TRR20 0x0010 /* Deny But Don't Lock Access To Mailbox 20 */
-#define TRR21 0x0020 /* Deny But Don't Lock Access To Mailbox 21 */
-#define TRR22 0x0040 /* Deny But Don't Lock Access To Mailbox 22 */
-#define TRR23 0x0080 /* Deny But Don't Lock Access To Mailbox 23 */
-#define TRR24 0x0100 /* Deny But Don't Lock Access To Mailbox 24 */
-#define TRR25 0x0200 /* Deny But Don't Lock Access To Mailbox 25 */
-#define TRR26 0x0400 /* Deny But Don't Lock Access To Mailbox 26 */
-#define TRR27 0x0800 /* Deny But Don't Lock Access To Mailbox 27 */
-#define TRR28 0x1000 /* Deny But Don't Lock Access To Mailbox 28 */
-#define TRR29 0x2000 /* Deny But Don't Lock Access To Mailbox 29 */
-#define TRR30 0x4000 /* Deny But Don't Lock Access To Mailbox 30 */
-#define TRR31 0x8000 /* Deny But Don't Lock Access To Mailbox 31 */
-
-/* CAN_TRS1 Masks */
-#define TRS0 0x0001 /* Remote Frame Request For Mailbox 0 */
-#define TRS1 0x0002 /* Remote Frame Request For Mailbox 1 */
-#define TRS2 0x0004 /* Remote Frame Request For Mailbox 2 */
-#define TRS3 0x0008 /* Remote Frame Request For Mailbox 3 */
-#define TRS4 0x0010 /* Remote Frame Request For Mailbox 4 */
-#define TRS5 0x0020 /* Remote Frame Request For Mailbox 5 */
-#define TRS6 0x0040 /* Remote Frame Request For Mailbox 6 */
-#define TRS7 0x0080 /* Remote Frame Request For Mailbox 7 */
-#define TRS8 0x0100 /* Remote Frame Request For Mailbox 8 */
-#define TRS9 0x0200 /* Remote Frame Request For Mailbox 9 */
-#define TRS10 0x0400 /* Remote Frame Request For Mailbox 10 */
-#define TRS11 0x0800 /* Remote Frame Request For Mailbox 11 */
-#define TRS12 0x1000 /* Remote Frame Request For Mailbox 12 */
-#define TRS13 0x2000 /* Remote Frame Request For Mailbox 13 */
-#define TRS14 0x4000 /* Remote Frame Request For Mailbox 14 */
-#define TRS15 0x8000 /* Remote Frame Request For Mailbox 15 */
-
-/* CAN_TRS2 Masks */
-#define TRS16 0x0001 /* Remote Frame Request For Mailbox 16 */
-#define TRS17 0x0002 /* Remote Frame Request For Mailbox 17 */
-#define TRS18 0x0004 /* Remote Frame Request For Mailbox 18 */
-#define TRS19 0x0008 /* Remote Frame Request For Mailbox 19 */
-#define TRS20 0x0010 /* Remote Frame Request For Mailbox 20 */
-#define TRS21 0x0020 /* Remote Frame Request For Mailbox 21 */
-#define TRS22 0x0040 /* Remote Frame Request For Mailbox 22 */
-#define TRS23 0x0080 /* Remote Frame Request For Mailbox 23 */
-#define TRS24 0x0100 /* Remote Frame Request For Mailbox 24 */
-#define TRS25 0x0200 /* Remote Frame Request For Mailbox 25 */
-#define TRS26 0x0400 /* Remote Frame Request For Mailbox 26 */
-#define TRS27 0x0800 /* Remote Frame Request For Mailbox 27 */
-#define TRS28 0x1000 /* Remote Frame Request For Mailbox 28 */
-#define TRS29 0x2000 /* Remote Frame Request For Mailbox 29 */
-#define TRS30 0x4000 /* Remote Frame Request For Mailbox 30 */
-#define TRS31 0x8000 /* Remote Frame Request For Mailbox 31 */
-
-/* CAN_AA1 Masks */
-#define AA0 0x0001 /* Aborted Message In Mailbox 0 */
-#define AA1 0x0002 /* Aborted Message In Mailbox 1 */
-#define AA2 0x0004 /* Aborted Message In Mailbox 2 */
-#define AA3 0x0008 /* Aborted Message In Mailbox 3 */
-#define AA4 0x0010 /* Aborted Message In Mailbox 4 */
-#define AA5 0x0020 /* Aborted Message In Mailbox 5 */
-#define AA6 0x0040 /* Aborted Message In Mailbox 6 */
-#define AA7 0x0080 /* Aborted Message In Mailbox 7 */
-#define AA8 0x0100 /* Aborted Message In Mailbox 8 */
-#define AA9 0x0200 /* Aborted Message In Mailbox 9 */
-#define AA10 0x0400 /* Aborted Message In Mailbox 10 */
-#define AA11 0x0800 /* Aborted Message In Mailbox 11 */
-#define AA12 0x1000 /* Aborted Message In Mailbox 12 */
-#define AA13 0x2000 /* Aborted Message In Mailbox 13 */
-#define AA14 0x4000 /* Aborted Message In Mailbox 14 */
-#define AA15 0x8000 /* Aborted Message In Mailbox 15 */
-
-/* CAN_AA2 Masks */
-#define AA16 0x0001 /* Aborted Message In Mailbox 16 */
-#define AA17 0x0002 /* Aborted Message In Mailbox 17 */
-#define AA18 0x0004 /* Aborted Message In Mailbox 18 */
-#define AA19 0x0008 /* Aborted Message In Mailbox 19 */
-#define AA20 0x0010 /* Aborted Message In Mailbox 20 */
-#define AA21 0x0020 /* Aborted Message In Mailbox 21 */
-#define AA22 0x0040 /* Aborted Message In Mailbox 22 */
-#define AA23 0x0080 /* Aborted Message In Mailbox 23 */
-#define AA24 0x0100 /* Aborted Message In Mailbox 24 */
-#define AA25 0x0200 /* Aborted Message In Mailbox 25 */
-#define AA26 0x0400 /* Aborted Message In Mailbox 26 */
-#define AA27 0x0800 /* Aborted Message In Mailbox 27 */
-#define AA28 0x1000 /* Aborted Message In Mailbox 28 */
-#define AA29 0x2000 /* Aborted Message In Mailbox 29 */
-#define AA30 0x4000 /* Aborted Message In Mailbox 30 */
-#define AA31 0x8000 /* Aborted Message In Mailbox 31 */
-
-/* CAN_TA1 Masks */
-#define TA0 0x0001 /* Transmit Successful From Mailbox 0 */
-#define TA1 0x0002 /* Transmit Successful From Mailbox 1 */
-#define TA2 0x0004 /* Transmit Successful From Mailbox 2 */
-#define TA3 0x0008 /* Transmit Successful From Mailbox 3 */
-#define TA4 0x0010 /* Transmit Successful From Mailbox 4 */
-#define TA5 0x0020 /* Transmit Successful From Mailbox 5 */
-#define TA6 0x0040 /* Transmit Successful From Mailbox 6 */
-#define TA7 0x0080 /* Transmit Successful From Mailbox 7 */
-#define TA8 0x0100 /* Transmit Successful From Mailbox 8 */
-#define TA9 0x0200 /* Transmit Successful From Mailbox 9 */
-#define TA10 0x0400 /* Transmit Successful From Mailbox 10 */
-#define TA11 0x0800 /* Transmit Successful From Mailbox 11 */
-#define TA12 0x1000 /* Transmit Successful From Mailbox 12 */
-#define TA13 0x2000 /* Transmit Successful From Mailbox 13 */
-#define TA14 0x4000 /* Transmit Successful From Mailbox 14 */
-#define TA15 0x8000 /* Transmit Successful From Mailbox 15 */
-
-/* CAN_TA2 Masks */
-#define TA16 0x0001 /* Transmit Successful From Mailbox 16 */
-#define TA17 0x0002 /* Transmit Successful From Mailbox 17 */
-#define TA18 0x0004 /* Transmit Successful From Mailbox 18 */
-#define TA19 0x0008 /* Transmit Successful From Mailbox 19 */
-#define TA20 0x0010 /* Transmit Successful From Mailbox 20 */
-#define TA21 0x0020 /* Transmit Successful From Mailbox 21 */
-#define TA22 0x0040 /* Transmit Successful From Mailbox 22 */
-#define TA23 0x0080 /* Transmit Successful From Mailbox 23 */
-#define TA24 0x0100 /* Transmit Successful From Mailbox 24 */
-#define TA25 0x0200 /* Transmit Successful From Mailbox 25 */
-#define TA26 0x0400 /* Transmit Successful From Mailbox 26 */
-#define TA27 0x0800 /* Transmit Successful From Mailbox 27 */
-#define TA28 0x1000 /* Transmit Successful From Mailbox 28 */
-#define TA29 0x2000 /* Transmit Successful From Mailbox 29 */
-#define TA30 0x4000 /* Transmit Successful From Mailbox 30 */
-#define TA31 0x8000 /* Transmit Successful From Mailbox 31 */
-
-/* CAN_MBTD Masks */
-#define TDPTR 0x001F /* Mailbox To Temporarily Disable */
-#define TDA 0x0040 /* Temporary Disable Acknowledge */
-#define TDR 0x0080 /* Temporary Disable Request */
-
-/* CAN_RFH1 Masks */
-#define RFH0 0x0001 /* Enable Automatic Remote Frame Handling For Mailbox 0 */
-#define RFH1 0x0002 /* Enable Automatic Remote Frame Handling For Mailbox 1 */
-#define RFH2 0x0004 /* Enable Automatic Remote Frame Handling For Mailbox 2 */
-#define RFH3 0x0008 /* Enable Automatic Remote Frame Handling For Mailbox 3 */
-#define RFH4 0x0010 /* Enable Automatic Remote Frame Handling For Mailbox 4 */
-#define RFH5 0x0020 /* Enable Automatic Remote Frame Handling For Mailbox 5 */
-#define RFH6 0x0040 /* Enable Automatic Remote Frame Handling For Mailbox 6 */
-#define RFH7 0x0080 /* Enable Automatic Remote Frame Handling For Mailbox 7 */
-#define RFH8 0x0100 /* Enable Automatic Remote Frame Handling For Mailbox 8 */
-#define RFH9 0x0200 /* Enable Automatic Remote Frame Handling For Mailbox 9 */
-#define RFH10 0x0400 /* Enable Automatic Remote Frame Handling For Mailbox 10 */
-#define RFH11 0x0800 /* Enable Automatic Remote Frame Handling For Mailbox 11 */
-#define RFH12 0x1000 /* Enable Automatic Remote Frame Handling For Mailbox 12 */
-#define RFH13 0x2000 /* Enable Automatic Remote Frame Handling For Mailbox 13 */
-#define RFH14 0x4000 /* Enable Automatic Remote Frame Handling For Mailbox 14 */
-#define RFH15 0x8000 /* Enable Automatic Remote Frame Handling For Mailbox 15 */
-
-/* CAN_RFH2 Masks */
-#define RFH16 0x0001 /* Enable Automatic Remote Frame Handling For Mailbox 16 */
-#define RFH17 0x0002 /* Enable Automatic Remote Frame Handling For Mailbox 17 */
-#define RFH18 0x0004 /* Enable Automatic Remote Frame Handling For Mailbox 18 */
-#define RFH19 0x0008 /* Enable Automatic Remote Frame Handling For Mailbox 19 */
-#define RFH20 0x0010 /* Enable Automatic Remote Frame Handling For Mailbox 20 */
-#define RFH21 0x0020 /* Enable Automatic Remote Frame Handling For Mailbox 21 */
-#define RFH22 0x0040 /* Enable Automatic Remote Frame Handling For Mailbox 22 */
-#define RFH23 0x0080 /* Enable Automatic Remote Frame Handling For Mailbox 23 */
-#define RFH24 0x0100 /* Enable Automatic Remote Frame Handling For Mailbox 24 */
-#define RFH25 0x0200 /* Enable Automatic Remote Frame Handling For Mailbox 25 */
-#define RFH26 0x0400 /* Enable Automatic Remote Frame Handling For Mailbox 26 */
-#define RFH27 0x0800 /* Enable Automatic Remote Frame Handling For Mailbox 27 */
-#define RFH28 0x1000 /* Enable Automatic Remote Frame Handling For Mailbox 28 */
-#define RFH29 0x2000 /* Enable Automatic Remote Frame Handling For Mailbox 29 */
-#define RFH30 0x4000 /* Enable Automatic Remote Frame Handling For Mailbox 30 */
-#define RFH31 0x8000 /* Enable Automatic Remote Frame Handling For Mailbox 31 */
-
-/* CAN_MBTIF1 Masks */
-#define MBTIF0 0x0001 /* TX Interrupt Active In Mailbox 0 */
-#define MBTIF1 0x0002 /* TX Interrupt Active In Mailbox 1 */
-#define MBTIF2 0x0004 /* TX Interrupt Active In Mailbox 2 */
-#define MBTIF3 0x0008 /* TX Interrupt Active In Mailbox 3 */
-#define MBTIF4 0x0010 /* TX Interrupt Active In Mailbox 4 */
-#define MBTIF5 0x0020 /* TX Interrupt Active In Mailbox 5 */
-#define MBTIF6 0x0040 /* TX Interrupt Active In Mailbox 6 */
-#define MBTIF7 0x0080 /* TX Interrupt Active In Mailbox 7 */
-#define MBTIF8 0x0100 /* TX Interrupt Active In Mailbox 8 */
-#define MBTIF9 0x0200 /* TX Interrupt Active In Mailbox 9 */
-#define MBTIF10 0x0400 /* TX Interrupt Active In Mailbox 10 */
-#define MBTIF11 0x0800 /* TX Interrupt Active In Mailbox 11 */
-#define MBTIF12 0x1000 /* TX Interrupt Active In Mailbox 12 */
-#define MBTIF13 0x2000 /* TX Interrupt Active In Mailbox 13 */
-#define MBTIF14 0x4000 /* TX Interrupt Active In Mailbox 14 */
-#define MBTIF15 0x8000 /* TX Interrupt Active In Mailbox 15 */
-
-/* CAN_MBTIF2 Masks */
-#define MBTIF16 0x0001 /* TX Interrupt Active In Mailbox 16 */
-#define MBTIF17 0x0002 /* TX Interrupt Active In Mailbox 17 */
-#define MBTIF18 0x0004 /* TX Interrupt Active In Mailbox 18 */
-#define MBTIF19 0x0008 /* TX Interrupt Active In Mailbox 19 */
-#define MBTIF20 0x0010 /* TX Interrupt Active In Mailbox 20 */
-#define MBTIF21 0x0020 /* TX Interrupt Active In Mailbox 21 */
-#define MBTIF22 0x0040 /* TX Interrupt Active In Mailbox 22 */
-#define MBTIF23 0x0080 /* TX Interrupt Active In Mailbox 23 */
-#define MBTIF24 0x0100 /* TX Interrupt Active In Mailbox 24 */
-#define MBTIF25 0x0200 /* TX Interrupt Active In Mailbox 25 */
-#define MBTIF26 0x0400 /* TX Interrupt Active In Mailbox 26 */
-#define MBTIF27 0x0800 /* TX Interrupt Active In Mailbox 27 */
-#define MBTIF28 0x1000 /* TX Interrupt Active In Mailbox 28 */
-#define MBTIF29 0x2000 /* TX Interrupt Active In Mailbox 29 */
-#define MBTIF30 0x4000 /* TX Interrupt Active In Mailbox 30 */
-#define MBTIF31 0x8000 /* TX Interrupt Active In Mailbox 31 */
-
-/* CAN_MBRIF1 Masks */
-#define MBRIF0 0x0001 /* RX Interrupt Active In Mailbox 0 */
-#define MBRIF1 0x0002 /* RX Interrupt Active In Mailbox 1 */
-#define MBRIF2 0x0004 /* RX Interrupt Active In Mailbox 2 */
-#define MBRIF3 0x0008 /* RX Interrupt Active In Mailbox 3 */
-#define MBRIF4 0x0010 /* RX Interrupt Active In Mailbox 4 */
-#define MBRIF5 0x0020 /* RX Interrupt Active In Mailbox 5 */
-#define MBRIF6 0x0040 /* RX Interrupt Active In Mailbox 6 */
-#define MBRIF7 0x0080 /* RX Interrupt Active In Mailbox 7 */
-#define MBRIF8 0x0100 /* RX Interrupt Active In Mailbox 8 */
-#define MBRIF9 0x0200 /* RX Interrupt Active In Mailbox 9 */
-#define MBRIF10 0x0400 /* RX Interrupt Active In Mailbox 10 */
-#define MBRIF11 0x0800 /* RX Interrupt Active In Mailbox 11 */
-#define MBRIF12 0x1000 /* RX Interrupt Active In Mailbox 12 */
-#define MBRIF13 0x2000 /* RX Interrupt Active In Mailbox 13 */
-#define MBRIF14 0x4000 /* RX Interrupt Active In Mailbox 14 */
-#define MBRIF15 0x8000 /* RX Interrupt Active In Mailbox 15 */
-
-/* CAN_MBRIF2 Masks */
-#define MBRIF16 0x0001 /* RX Interrupt Active In Mailbox 16 */
-#define MBRIF17 0x0002 /* RX Interrupt Active In Mailbox 17 */
-#define MBRIF18 0x0004 /* RX Interrupt Active In Mailbox 18 */
-#define MBRIF19 0x0008 /* RX Interrupt Active In Mailbox 19 */
-#define MBRIF20 0x0010 /* RX Interrupt Active In Mailbox 20 */
-#define MBRIF21 0x0020 /* RX Interrupt Active In Mailbox 21 */
-#define MBRIF22 0x0040 /* RX Interrupt Active In Mailbox 22 */
-#define MBRIF23 0x0080 /* RX Interrupt Active In Mailbox 23 */
-#define MBRIF24 0x0100 /* RX Interrupt Active In Mailbox 24 */
-#define MBRIF25 0x0200 /* RX Interrupt Active In Mailbox 25 */
-#define MBRIF26 0x0400 /* RX Interrupt Active In Mailbox 26 */
-#define MBRIF27 0x0800 /* RX Interrupt Active In Mailbox 27 */
-#define MBRIF28 0x1000 /* RX Interrupt Active In Mailbox 28 */
-#define MBRIF29 0x2000 /* RX Interrupt Active In Mailbox 29 */
-#define MBRIF30 0x4000 /* RX Interrupt Active In Mailbox 30 */
-#define MBRIF31 0x8000 /* RX Interrupt Active In Mailbox 31 */
-
-/* CAN_MBIM1 Masks */
-#define MBIM0 0x0001 /* Enable Interrupt For Mailbox 0 */
-#define MBIM1 0x0002 /* Enable Interrupt For Mailbox 1 */
-#define MBIM2 0x0004 /* Enable Interrupt For Mailbox 2 */
-#define MBIM3 0x0008 /* Enable Interrupt For Mailbox 3 */
-#define MBIM4 0x0010 /* Enable Interrupt For Mailbox 4 */
-#define MBIM5 0x0020 /* Enable Interrupt For Mailbox 5 */
-#define MBIM6 0x0040 /* Enable Interrupt For Mailbox 6 */
-#define MBIM7 0x0080 /* Enable Interrupt For Mailbox 7 */
-#define MBIM8 0x0100 /* Enable Interrupt For Mailbox 8 */
-#define MBIM9 0x0200 /* Enable Interrupt For Mailbox 9 */
-#define MBIM10 0x0400 /* Enable Interrupt For Mailbox 10 */
-#define MBIM11 0x0800 /* Enable Interrupt For Mailbox 11 */
-#define MBIM12 0x1000 /* Enable Interrupt For Mailbox 12 */
-#define MBIM13 0x2000 /* Enable Interrupt For Mailbox 13 */
-#define MBIM14 0x4000 /* Enable Interrupt For Mailbox 14 */
-#define MBIM15 0x8000 /* Enable Interrupt For Mailbox 15 */
-
-/* CAN_MBIM2 Masks */
-#define MBIM16 0x0001 /* Enable Interrupt For Mailbox 16 */
-#define MBIM17 0x0002 /* Enable Interrupt For Mailbox 17 */
-#define MBIM18 0x0004 /* Enable Interrupt For Mailbox 18 */
-#define MBIM19 0x0008 /* Enable Interrupt For Mailbox 19 */
-#define MBIM20 0x0010 /* Enable Interrupt For Mailbox 20 */
-#define MBIM21 0x0020 /* Enable Interrupt For Mailbox 21 */
-#define MBIM22 0x0040 /* Enable Interrupt For Mailbox 22 */
-#define MBIM23 0x0080 /* Enable Interrupt For Mailbox 23 */
-#define MBIM24 0x0100 /* Enable Interrupt For Mailbox 24 */
-#define MBIM25 0x0200 /* Enable Interrupt For Mailbox 25 */
-#define MBIM26 0x0400 /* Enable Interrupt For Mailbox 26 */
-#define MBIM27 0x0800 /* Enable Interrupt For Mailbox 27 */
-#define MBIM28 0x1000 /* Enable Interrupt For Mailbox 28 */
-#define MBIM29 0x2000 /* Enable Interrupt For Mailbox 29 */
-#define MBIM30 0x4000 /* Enable Interrupt For Mailbox 30 */
-#define MBIM31 0x8000 /* Enable Interrupt For Mailbox 31 */
-
-/* CAN_GIM Masks */
-#define EWTIM 0x0001 /* Enable TX Error Count Interrupt */
-#define EWRIM 0x0002 /* Enable RX Error Count Interrupt */
-#define EPIM 0x0004 /* Enable Error-Passive Mode Interrupt */
-#define BOIM 0x0008 /* Enable Bus Off Interrupt */
-#define WUIM 0x0010 /* Enable Wake-Up Interrupt */
-#define UIAIM 0x0020 /* Enable Access To Unimplemented Address Interrupt */
-#define AAIM 0x0040 /* Enable Abort Acknowledge Interrupt */
-#define RMLIM 0x0080 /* Enable RX Message Lost Interrupt */
-#define UCEIM 0x0100 /* Enable Universal Counter Overflow Interrupt */
-#define EXTIM 0x0200 /* Enable External Trigger Output Interrupt */
-#define ADIM 0x0400 /* Enable Access Denied Interrupt */
-
-/* CAN_GIS Masks */
-#define EWTIS 0x0001 /* TX Error Count IRQ Status */
-#define EWRIS 0x0002 /* RX Error Count IRQ Status */
-#define EPIS 0x0004 /* Error-Passive Mode IRQ Status */
-#define BOIS 0x0008 /* Bus Off IRQ Status */
-#define WUIS 0x0010 /* Wake-Up IRQ Status */
-#define UIAIS 0x0020 /* Access To Unimplemented Address IRQ Status */
-#define AAIS 0x0040 /* Abort Acknowledge IRQ Status */
-#define RMLIS 0x0080 /* RX Message Lost IRQ Status */
-#define UCEIS 0x0100 /* Universal Counter Overflow IRQ Status */
-#define EXTIS 0x0200 /* External Trigger Output IRQ Status */
-#define ADIS 0x0400 /* Access Denied IRQ Status */
-
-/* CAN_GIF Masks */
-#define EWTIF 0x0001 /* TX Error Count IRQ Flag */
-#define EWRIF 0x0002 /* RX Error Count IRQ Flag */
-#define EPIF 0x0004 /* Error-Passive Mode IRQ Flag */
-#define BOIF 0x0008 /* Bus Off IRQ Flag */
-#define WUIF 0x0010 /* Wake-Up IRQ Flag */
-#define UIAIF 0x0020 /* Access To Unimplemented Address IRQ Flag */
-#define AAIF 0x0040 /* Abort Acknowledge IRQ Flag */
-#define RMLIF 0x0080 /* RX Message Lost IRQ Flag */
-#define UCEIF 0x0100 /* Universal Counter Overflow IRQ Flag */
-#define EXTIF 0x0200 /* External Trigger Output IRQ Flag */
-#define ADIF 0x0400 /* Access Denied IRQ Flag */
-
-/* CAN_UCCNF Masks */
-#define UCCNF 0x000F /* Universal Counter Mode */
-#define UC_STAMP 0x0001 /* Timestamp Mode */
-#define UC_WDOG 0x0002 /* Watchdog Mode */
-#define UC_AUTOTX 0x0003 /* Auto-Transmit Mode */
-#define UC_ERROR 0x0006 /* CAN Error Frame Count */
-#define UC_OVER 0x0007 /* CAN Overload Frame Count */
-#define UC_LOST 0x0008 /* Arbitration Lost During TX Count */
-#define UC_AA 0x0009 /* TX Abort Count */
-#define UC_TA 0x000A /* TX Successful Count */
-#define UC_REJECT 0x000B /* RX Message Rejected Count */
-#define UC_RML 0x000C /* RX Message Lost Count */
-#define UC_RX 0x000D /* Total Successful RX Messages Count */
-#define UC_RMP 0x000E /* Successful RX W/Matching ID Count */
-#define UC_ALL 0x000F /* Correct Message On CAN Bus Line Count */
-#define UCRC 0x0020 /* Universal Counter Reload/Clear */
-#define UCCT 0x0040 /* Universal Counter CAN Trigger */
-#define UCE 0x0080 /* Universal Counter Enable */
-
-/* CAN_ESR Masks */
-#define ACKE 0x0004 /* Acknowledge Error */
-#define SER 0x0008 /* Stuff Error */
-#define CRCE 0x0010 /* CRC Error */
-#define SA0 0x0020 /* Stuck At Dominant Error */
-#define BEF 0x0040 /* Bit Error Flag */
-#define FER 0x0080 /* Form Error Flag */
-
-/* CAN_EWR Masks */
-#define EWLREC 0x00FF /* RX Error Count Limit (For EWRIS) */
-#define EWLTEC 0xFF00 /* TX Error Count Limit (For EWTIS) */
-
-#endif
+++ /dev/null
-/*
- * bfin_dma.h - Blackfin DMA defines/structures/etc...
- *
- * Copyright 2004-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_BFIN_DMA_H__
-#define __ASM_BFIN_DMA_H__
-
-#include <linux/types.h>
-
-/* DMA_CONFIG Masks */
-#define DMAEN 0x0001 /* DMA Channel Enable */
-#define WNR 0x0002 /* Channel Direction (W/R*) */
-#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */
-#define PSIZE_8 0x00000000 /* Transfer Word Size = 16 */
-
-#ifdef CONFIG_BF60x
-
-#define PSIZE_16 0x00000010 /* Transfer Word Size = 16 */
-#define PSIZE_32 0x00000020 /* Transfer Word Size = 32 */
-#define PSIZE_64 0x00000030 /* Transfer Word Size = 32 */
-#define WDSIZE_16 0x00000100 /* Transfer Word Size = 16 */
-#define WDSIZE_32 0x00000200 /* Transfer Word Size = 32 */
-#define WDSIZE_64 0x00000300 /* Transfer Word Size = 32 */
-#define WDSIZE_128 0x00000400 /* Transfer Word Size = 32 */
-#define WDSIZE_256 0x00000500 /* Transfer Word Size = 32 */
-#define DMA2D 0x04000000 /* DMA Mode (2D/1D*) */
-#define RESTART 0x00000004 /* DMA Buffer Clear SYNC */
-#define DI_EN_X 0x00100000 /* Data Interrupt Enable in X count */
-#define DI_EN_Y 0x00200000 /* Data Interrupt Enable in Y count */
-#define DI_EN_P 0x00300000 /* Data Interrupt Enable in Peripheral */
-#define DI_EN DI_EN_X /* Data Interrupt Enable */
-#define NDSIZE_0 0x00000000 /* Next Descriptor Size = 1 */
-#define NDSIZE_1 0x00010000 /* Next Descriptor Size = 2 */
-#define NDSIZE_2 0x00020000 /* Next Descriptor Size = 3 */
-#define NDSIZE_3 0x00030000 /* Next Descriptor Size = 4 */
-#define NDSIZE_4 0x00040000 /* Next Descriptor Size = 5 */
-#define NDSIZE_5 0x00050000 /* Next Descriptor Size = 6 */
-#define NDSIZE_6 0x00060000 /* Next Descriptor Size = 7 */
-#define NDSIZE 0x00070000 /* Next Descriptor Size */
-#define NDSIZE_OFFSET 16 /* Next Descriptor Size Offset */
-#define DMAFLOW_LIST 0x00004000 /* Descriptor List Mode */
-#define DMAFLOW_LARGE DMAFLOW_LIST
-#define DMAFLOW_ARRAY 0x00005000 /* Descriptor Array Mode */
-#define DMAFLOW_LIST_DEMAND 0x00006000 /* Descriptor Demand List Mode */
-#define DMAFLOW_ARRAY_DEMAND 0x00007000 /* Descriptor Demand Array Mode */
-#define DMA_RUN_DFETCH 0x00000100 /* DMA Channel Running Indicator (DFETCH) */
-#define DMA_RUN 0x00000200 /* DMA Channel Running Indicator */
-#define DMA_RUN_WAIT_TRIG 0x00000300 /* DMA Channel Running Indicator (WAIT TRIG) */
-#define DMA_RUN_WAIT_ACK 0x00000400 /* DMA Channel Running Indicator (WAIT ACK) */
-
-#else
-
-#define PSIZE_16 0x0000 /* Transfer Word Size = 16 */
-#define PSIZE_32 0x0000 /* Transfer Word Size = 32 */
-#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */
-#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */
-#define DMA2D 0x0010 /* DMA Mode (2D/1D*) */
-#define RESTART 0x0020 /* DMA Buffer Clear */
-#define DI_SEL 0x0040 /* Data Interrupt Timing Select */
-#define DI_EN 0x0080 /* Data Interrupt Enable */
-#define DI_EN_X 0x00C0 /* Data Interrupt Enable in X count*/
-#define DI_EN_Y 0x0080 /* Data Interrupt Enable in Y count*/
-#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
-#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
-#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
-#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
-#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
-#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
-#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
-#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
-#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
-#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
-#define NDSIZE 0x0f00 /* Next Descriptor Size */
-#define NDSIZE_OFFSET 8 /* Next Descriptor Size Offset */
-#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */
-#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
-#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
-#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */
-#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */
-
-#endif
-#define DMAFLOW 0x7000 /* Flow Control */
-#define DMAFLOW_STOP 0x0000 /* Stop Mode */
-#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
-
-/* DMA_IRQ_STATUS Masks */
-#define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */
-#define DMA_ERR 0x0002 /* DMA Error Interrupt Status */
-#ifdef CONFIG_BF60x
-#define DMA_PIRQ 0x0004 /* DMA Peripheral Error Interrupt Status */
-#else
-#define DMA_PIRQ 0
-#endif
-
-/*
- * All Blackfin system MMRs are padded to 32bits even if the register
- * itself is only 16bits. So use a helper macro to streamline this.
- */
-#define __BFP(m) u16 m; u16 __pad_##m
-
-/*
- * bfin dma registers layout
- */
-struct bfin_dma_regs {
- u32 next_desc_ptr;
- u32 start_addr;
-#ifdef CONFIG_BF60x
- u32 cfg;
- u32 x_count;
- u32 x_modify;
- u32 y_count;
- u32 y_modify;
- u32 pad1;
- u32 pad2;
- u32 curr_desc_ptr;
- u32 prev_desc_ptr;
- u32 curr_addr;
- u32 irq_status;
- u32 curr_x_count;
- u32 curr_y_count;
- u32 pad3;
- u32 bw_limit_count;
- u32 curr_bw_limit_count;
- u32 bw_monitor_count;
- u32 curr_bw_monitor_count;
-#else
- __BFP(config);
- u32 __pad0;
- __BFP(x_count);
- __BFP(x_modify);
- __BFP(y_count);
- __BFP(y_modify);
- u32 curr_desc_ptr;
- u32 curr_addr;
- __BFP(irq_status);
- __BFP(peripheral_map);
- __BFP(curr_x_count);
- u32 __pad1;
- __BFP(curr_y_count);
- u32 __pad2;
-#endif
-};
-
-#ifndef CONFIG_BF60x
-/*
- * bfin handshake mdma registers layout
- */
-struct bfin_hmdma_regs {
- __BFP(control);
- __BFP(ecinit);
- __BFP(bcinit);
- __BFP(ecurgent);
- __BFP(ecoverflow);
- __BFP(ecount);
- __BFP(bcount);
-};
-#endif
-
-#undef __BFP
-
-#endif
+++ /dev/null
-/*
- * Blackfin Performance Monitor definitions
- *
- * Copyright 2005-2011 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or GPL-2 (or later).
- */
-
-#ifndef __ASM_BFIN_PFMON_H__
-#define __ASM_BFIN_PFMON_H__
-
-/* PFCTL Masks */
-#define PFMON_MASK 0xff
-#define PFCEN_MASK 0x3
-#define PFCEN_DISABLE 0x0
-#define PFCEN_ENABLE_USER 0x1
-#define PFCEN_ENABLE_SUPV 0x2
-#define PFCEN_ENABLE_ALL (PFCEN_ENABLE_USER | PFCEN_ENABLE_SUPV)
-
-#define PFPWR_P 0
-#define PEMUSW0_P 2
-#define PFCEN0_P 3
-#define PFMON0_P 5
-#define PEMUSW1_P 13
-#define PFCEN1_P 14
-#define PFMON1_P 16
-#define PFCNT0_P 24
-#define PFCNT1_P 25
-
-#define PFPWR (1 << PFPWR_P)
-#define PEMUSW(n, x) ((x) << ((n) ? PEMUSW1_P : PEMUSW0_P))
-#define PEMUSW0 PEMUSW(0, 1)
-#define PEMUSW1 PEMUSW(1, 1)
-#define PFCEN(n, x) ((x) << ((n) ? PFCEN1_P : PFCEN0_P))
-#define PFCEN0 PFCEN(0, PFCEN_MASK)
-#define PFCEN1 PFCEN(1, PFCEN_MASK)
-#define PFCNT(n, x) ((x) << ((n) ? PFCNT1_P : PFCNT0_P))
-#define PFCNT0 PFCNT(0, 1)
-#define PFCNT1 PFCNT(1, 1)
-#define PFMON(n, x) ((x) << ((n) ? PFMON1_P : PFMON0_P))
-#define PFMON0 PFMON(0, PFMON_MASK)
-#define PFMON1 PFMON(1, PFMON_MASK)
-
-#endif
+++ /dev/null
-/*
- * bfin_ppi.h - interface to Blackfin PPIs
- *
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_BFIN_PPI_H__
-#define __ASM_BFIN_PPI_H__
-
-#include <linux/types.h>
-#include <asm/blackfin.h>
-
-/*
- * All Blackfin system MMRs are padded to 32bits even if the register
- * itself is only 16bits. So use a helper macro to streamline this.
- */
-#define __BFP(m) u16 m; u16 __pad_##m
-
-/*
- * bfin ppi registers layout
- */
-struct bfin_ppi_regs {
- __BFP(control);
- __BFP(status);
- __BFP(count);
- __BFP(delay);
- __BFP(frame);
-};
-
-/*
- * bfin eppi registers layout
- */
-struct bfin_eppi_regs {
- __BFP(status);
- __BFP(hcount);
- __BFP(hdelay);
- __BFP(vcount);
- __BFP(vdelay);
- __BFP(frame);
- __BFP(line);
- __BFP(clkdiv);
- u32 control;
- u32 fs1w_hbl;
- u32 fs1p_avpl;
- u32 fs2w_lvb;
- u32 fs2p_lavf;
- u32 clip;
-};
-
-/*
- * bfin eppi3 registers layout
- */
-struct bfin_eppi3_regs {
- u32 stat;
- u32 hcnt;
- u32 hdly;
- u32 vcnt;
- u32 vdly;
- u32 frame;
- u32 line;
- u32 clkdiv;
- u32 ctl;
- u32 fs1_wlhb;
- u32 fs1_paspl;
- u32 fs2_wlvb;
- u32 fs2_palpf;
- u32 imsk;
- u32 oddclip;
- u32 evenclip;
- u32 fs1_dly;
- u32 fs2_dly;
- u32 ctl2;
-};
-
-#undef __BFP
-
-#ifdef EPPI0_CTL2
-#define EPPI_STAT_CFIFOERR 0x00000001 /* Chroma FIFO Error */
-#define EPPI_STAT_YFIFOERR 0x00000002 /* Luma FIFO Error */
-#define EPPI_STAT_LTERROVR 0x00000004 /* Line Track Overflow */
-#define EPPI_STAT_LTERRUNDR 0x00000008 /* Line Track Underflow */
-#define EPPI_STAT_FTERROVR 0x00000010 /* Frame Track Overflow */
-#define EPPI_STAT_FTERRUNDR 0x00000020 /* Frame Track Underflow */
-#define EPPI_STAT_ERRNCOR 0x00000040 /* Preamble Error Not Corrected */
-#define EPPI_STAT_PXPERR 0x00000080 /* PxP Ready Error */
-#define EPPI_STAT_ERRDET 0x00004000 /* Preamble Error Detected */
-#define EPPI_STAT_FLD 0x00008000 /* Current Field Received by EPPI */
-
-#define EPPI_HCNT_VALUE 0x0000FFFF /* Holds the number of samples to read in or write out per line, after PPIx_HDLY number of cycles have expired since the last assertion of PPIx_FS1 */
-
-#define EPPI_HDLY_VALUE 0x0000FFFF /* Number of PPIx_CLK cycles to delay after assertion of PPIx_FS1 before starting to read or write data */
-
-#define EPPI_VCNT_VALUE 0x0000FFFF /* Holds the number of lines to read in or write out, after PPIx_VDLY number of lines from the start of frame */
-
-#define EPPI_VDLY_VALUE 0x0000FFFF /* Number of lines to wait after the start of a new frame before starting to read/transmit data */
-
-#define EPPI_FRAME_VALUE 0x0000FFFF /* Holds the number of lines expected per frame of data */
-
-#define EPPI_LINE_VALUE 0x0000FFFF /* Holds the number of samples expected per line */
-
-#define EPPI_CLKDIV_VALUE 0x0000FFFF /* Internal clock divider */
-
-#define EPPI_CTL_EN 0x00000001 /* PPI Enable */
-#define EPPI_CTL_DIR 0x00000002 /* PPI Direction */
-#define EPPI_CTL_XFRTYPE 0x0000000C /* PPI Operating Mode */
-#define EPPI_CTL_ACTIVE656 0x00000000 /* XFRTYPE: ITU656 Active Video Only Mode */
-#define EPPI_CTL_ENTIRE656 0x00000004 /* XFRTYPE: ITU656 Entire Field Mode */
-#define EPPI_CTL_VERT656 0x00000008 /* XFRTYPE: ITU656 Vertical Blanking Only Mode */
-#define EPPI_CTL_NON656 0x0000000C /* XFRTYPE: Non-ITU656 Mode (GP Mode) */
-#define EPPI_CTL_FSCFG 0x00000030 /* Frame Sync Configuration */
-#define EPPI_CTL_SYNC0 0x00000000 /* FSCFG: Sync Mode 0 */
-#define EPPI_CTL_SYNC1 0x00000010 /* FSCFG: Sync Mode 1 */
-#define EPPI_CTL_SYNC2 0x00000020 /* FSCFG: Sync Mode 2 */
-#define EPPI_CTL_SYNC3 0x00000030 /* FSCFG: Sync Mode 3 */
-#define EPPI_CTL_FLDSEL 0x00000040 /* Field Select/Trigger */
-#define EPPI_CTL_ITUTYPE 0x00000080 /* ITU Interlace or Progressive */
-#define EPPI_CTL_BLANKGEN 0x00000100 /* ITU Output Mode with Internal Blanking Generation */
-#define EPPI_CTL_ICLKGEN 0x00000200 /* Internal Clock Generation */
-#define EPPI_CTL_IFSGEN 0x00000400 /* Internal Frame Sync Generation */
-#define EPPI_CTL_SIGNEXT 0x00000800 /* Sign Extension */
-#define EPPI_CTL_POLC 0x00003000 /* Frame Sync and Data Driving and Sampling Edges */
-#define EPPI_CTL_POLC0 0x00000000 /* POLC: Clock/Sync polarity mode 0 */
-#define EPPI_CTL_POLC1 0x00001000 /* POLC: Clock/Sync polarity mode 1 */
-#define EPPI_CTL_POLC2 0x00002000 /* POLC: Clock/Sync polarity mode 2 */
-#define EPPI_CTL_POLC3 0x00003000 /* POLC: Clock/Sync polarity mode 3 */
-#define EPPI_CTL_POLS 0x0000C000 /* Frame Sync Polarity */
-#define EPPI_CTL_FS1HI_FS2HI 0x00000000 /* POLS: FS1 and FS2 are active high */
-#define EPPI_CTL_FS1LO_FS2HI 0x00004000 /* POLS: FS1 is active low. FS2 is active high */
-#define EPPI_CTL_FS1HI_FS2LO 0x00008000 /* POLS: FS1 is active high. FS2 is active low */
-#define EPPI_CTL_FS1LO_FS2LO 0x0000C000 /* POLS: FS1 and FS2 are active low */
-#define EPPI_CTL_DLEN 0x00070000 /* Data Length */
-#define EPPI_CTL_DLEN08 0x00000000 /* DLEN: 8 bits */
-#define EPPI_CTL_DLEN10 0x00010000 /* DLEN: 10 bits */
-#define EPPI_CTL_DLEN12 0x00020000 /* DLEN: 12 bits */
-#define EPPI_CTL_DLEN14 0x00030000 /* DLEN: 14 bits */
-#define EPPI_CTL_DLEN16 0x00040000 /* DLEN: 16 bits */
-#define EPPI_CTL_DLEN18 0x00050000 /* DLEN: 18 bits */
-#define EPPI_CTL_DLEN20 0x00060000 /* DLEN: 20 bits */
-#define EPPI_CTL_DLEN24 0x00070000 /* DLEN: 24 bits */
-#define EPPI_CTL_DMIRR 0x00080000 /* Data Mirroring */
-#define EPPI_CTL_SKIPEN 0x00100000 /* Skip Enable */
-#define EPPI_CTL_SKIPEO 0x00200000 /* Skip Even or Odd */
-#define EPPI_CTL_PACKEN 0x00400000 /* Pack/Unpack Enable */
-#define EPPI_CTL_SWAPEN 0x00800000 /* Swap Enable */
-#define EPPI_CTL_SPLTEO 0x01000000 /* Split Even and Odd Data Samples */
-#define EPPI_CTL_SUBSPLTODD 0x02000000 /* Sub-Split Odd Samples */
-#define EPPI_CTL_SPLTWRD 0x04000000 /* Split Word */
-#define EPPI_CTL_RGBFMTEN 0x08000000 /* RGB Formatting Enable */
-#define EPPI_CTL_DMACFG 0x10000000 /* One or Two DMA Channels Mode */
-#define EPPI_CTL_DMAFINEN 0x20000000 /* DMA Finish Enable */
-#define EPPI_CTL_MUXSEL 0x40000000 /* MUX Select */
-#define EPPI_CTL_CLKGATEN 0x80000000 /* Clock Gating Enable */
-
-#define EPPI_FS2_WLVB_F2VBAD 0xFF000000 /* In GP transmit mode with BLANKGEN = 1, contains number of lines of vertical blanking after field 2 */
-#define EPPI_FS2_WLVB_F2VBBD 0x00FF0000 /* In GP transmit mode with BLANKGEN = 1, contains number of lines of vertical blanking before field 2 */
-#define EPPI_FS2_WLVB_F1VBAD 0x0000FF00 /* In GP transmit mode with, BLANKGEN = 1, contains number of lines of vertical blanking after field 1 */
-#define EPPI_FS2_WLVB_F1VBBD 0x000000FF /* In GP 2, or 3 FS modes used to generate PPIx_FS2 width (32-bit). In GP Transmit mode, with BLANKGEN=1, contains the number of lines of Vertical blanking before field 1. */
-
-#define EPPI_FS2_PALPF_F2ACT 0xFFFF0000 /* Number of lines of Active Data in Field 2 */
-#define EPPI_FS2_PALPF_F1ACT 0x0000FFFF /* Number of lines of Active Data in Field 1 */
-
-#define EPPI_IMSK_CFIFOERR 0x00000001 /* Mask CFIFO Underflow or Overflow Error Interrupt */
-#define EPPI_IMSK_YFIFOERR 0x00000002 /* Mask YFIFO Underflow or Overflow Error Interrupt */
-#define EPPI_IMSK_LTERROVR 0x00000004 /* Mask Line Track Overflow Error Interrupt */
-#define EPPI_IMSK_LTERRUNDR 0x00000008 /* Mask Line Track Underflow Error Interrupt */
-#define EPPI_IMSK_FTERROVR 0x00000010 /* Mask Frame Track Overflow Error Interrupt */
-#define EPPI_IMSK_FTERRUNDR 0x00000020 /* Mask Frame Track Underflow Error Interrupt */
-#define EPPI_IMSK_ERRNCOR 0x00000040 /* Mask ITU Preamble Error Not Corrected Interrupt */
-#define EPPI_IMSK_PXPERR 0x00000080 /* Mask PxP Ready Error Interrupt */
-
-#define EPPI_ODDCLIP_HIGHODD 0xFFFF0000
-#define EPPI_ODDCLIP_LOWODD 0x0000FFFF
-
-#define EPPI_EVENCLIP_HIGHEVEN 0xFFFF0000
-#define EPPI_EVENCLIP_LOWEVEN 0x0000FFFF
-
-#define EPPI_CTL2_FS1FINEN 0x00000002 /* HSYNC Finish Enable */
-#endif
-#endif
+++ /dev/null
-/*
- * Blackfin Secure Digital Host (SDH) definitions
- *
- * Copyright 2008-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_SDH_H__
-#define __BFIN_SDH_H__
-
-/* Platform resources */
-struct bfin_sd_host {
- int dma_chan;
- int irq_int0;
- int irq_int1;
- u16 pin_req[7];
-};
-
-/* SDH_COMMAND bitmasks */
-#define CMD_IDX 0x3f /* Command Index */
-#define CMD_RSP (1 << 6) /* Response */
-#define CMD_L_RSP (1 << 7) /* Long Response */
-#define CMD_INT_E (1 << 8) /* Command Interrupt */
-#define CMD_PEND_E (1 << 9) /* Command Pending */
-#define CMD_E (1 << 10) /* Command Enable */
-#ifdef RSI_BLKSZ
-#define CMD_CRC_CHECK_D (1 << 11) /* CRC Check is disabled */
-#define CMD_DATA0_BUSY (1 << 12) /* Check for Busy State on the DATA0 pin */
-#endif
-
-/* SDH_PWR_CTL bitmasks */
-#ifndef RSI_BLKSZ
-#define PWR_ON 0x3 /* Power On */
-#define SD_CMD_OD (1 << 6) /* Open Drain Output */
-#define ROD_CTL (1 << 7) /* Rod Control */
-#endif
-
-/* SDH_CLK_CTL bitmasks */
-#define CLKDIV 0xff /* MC_CLK Divisor */
-#define CLK_E (1 << 8) /* MC_CLK Bus Clock Enable */
-#define PWR_SV_E (1 << 9) /* Power Save Enable */
-#define CLKDIV_BYPASS (1 << 10) /* Bypass Divisor */
-#define BUS_MODE_MASK 0x1800 /* Bus Mode Mask */
-#define STD_BUS_1 0x000 /* Standard Bus 1 bit mode */
-#define WIDE_BUS_4 0x800 /* Wide Bus 4 bit mode */
-#define BYTE_BUS_8 0x1000 /* Byte Bus 8 bit mode */
-
-/* SDH_RESP_CMD bitmasks */
-#define RESP_CMD 0x3f /* Response Command */
-
-/* SDH_DATA_CTL bitmasks */
-#define DTX_E (1 << 0) /* Data Transfer Enable */
-#define DTX_DIR (1 << 1) /* Data Transfer Direction */
-#define DTX_MODE (1 << 2) /* Data Transfer Mode */
-#define DTX_DMA_E (1 << 3) /* Data Transfer DMA Enable */
-#ifndef RSI_BLKSZ
-#define DTX_BLK_LGTH (0xf << 4) /* Data Transfer Block Length */
-#else
-
-/* Bit masks for SDH_BLK_SIZE */
-#define DTX_BLK_LGTH 0x1fff /* Data Transfer Block Length */
-#endif
-
-/* SDH_STATUS bitmasks */
-#define CMD_CRC_FAIL (1 << 0) /* CMD CRC Fail */
-#define DAT_CRC_FAIL (1 << 1) /* Data CRC Fail */
-#define CMD_TIME_OUT (1 << 2) /* CMD Time Out */
-#define DAT_TIME_OUT (1 << 3) /* Data Time Out */
-#define TX_UNDERRUN (1 << 4) /* Transmit Underrun */
-#define RX_OVERRUN (1 << 5) /* Receive Overrun */
-#define CMD_RESP_END (1 << 6) /* CMD Response End */
-#define CMD_SENT (1 << 7) /* CMD Sent */
-#define DAT_END (1 << 8) /* Data End */
-#define START_BIT_ERR (1 << 9) /* Start Bit Error */
-#define DAT_BLK_END (1 << 10) /* Data Block End */
-#define CMD_ACT (1 << 11) /* CMD Active */
-#define TX_ACT (1 << 12) /* Transmit Active */
-#define RX_ACT (1 << 13) /* Receive Active */
-#define TX_FIFO_STAT (1 << 14) /* Transmit FIFO Status */
-#define RX_FIFO_STAT (1 << 15) /* Receive FIFO Status */
-#define TX_FIFO_FULL (1 << 16) /* Transmit FIFO Full */
-#define RX_FIFO_FULL (1 << 17) /* Receive FIFO Full */
-#define TX_FIFO_ZERO (1 << 18) /* Transmit FIFO Empty */
-#define RX_DAT_ZERO (1 << 19) /* Receive FIFO Empty */
-#define TX_DAT_RDY (1 << 20) /* Transmit Data Available */
-#define RX_FIFO_RDY (1 << 21) /* Receive Data Available */
-
-/* SDH_STATUS_CLR bitmasks */
-#define CMD_CRC_FAIL_STAT (1 << 0) /* CMD CRC Fail Status */
-#define DAT_CRC_FAIL_STAT (1 << 1) /* Data CRC Fail Status */
-#define CMD_TIMEOUT_STAT (1 << 2) /* CMD Time Out Status */
-#define DAT_TIMEOUT_STAT (1 << 3) /* Data Time Out status */
-#define TX_UNDERRUN_STAT (1 << 4) /* Transmit Underrun Status */
-#define RX_OVERRUN_STAT (1 << 5) /* Receive Overrun Status */
-#define CMD_RESP_END_STAT (1 << 6) /* CMD Response End Status */
-#define CMD_SENT_STAT (1 << 7) /* CMD Sent Status */
-#define DAT_END_STAT (1 << 8) /* Data End Status */
-#define START_BIT_ERR_STAT (1 << 9) /* Start Bit Error Status */
-#define DAT_BLK_END_STAT (1 << 10) /* Data Block End Status */
-
-/* SDH_MASK0 bitmasks */
-#define CMD_CRC_FAIL_MASK (1 << 0) /* CMD CRC Fail Mask */
-#define DAT_CRC_FAIL_MASK (1 << 1) /* Data CRC Fail Mask */
-#define CMD_TIMEOUT_MASK (1 << 2) /* CMD Time Out Mask */
-#define DAT_TIMEOUT_MASK (1 << 3) /* Data Time Out Mask */
-#define TX_UNDERRUN_MASK (1 << 4) /* Transmit Underrun Mask */
-#define RX_OVERRUN_MASK (1 << 5) /* Receive Overrun Mask */
-#define CMD_RESP_END_MASK (1 << 6) /* CMD Response End Mask */
-#define CMD_SENT_MASK (1 << 7) /* CMD Sent Mask */
-#define DAT_END_MASK (1 << 8) /* Data End Mask */
-#define START_BIT_ERR_MASK (1 << 9) /* Start Bit Error Mask */
-#define DAT_BLK_END_MASK (1 << 10) /* Data Block End Mask */
-#define CMD_ACT_MASK (1 << 11) /* CMD Active Mask */
-#define TX_ACT_MASK (1 << 12) /* Transmit Active Mask */
-#define RX_ACT_MASK (1 << 13) /* Receive Active Mask */
-#define TX_FIFO_STAT_MASK (1 << 14) /* Transmit FIFO Status Mask */
-#define RX_FIFO_STAT_MASK (1 << 15) /* Receive FIFO Status Mask */
-#define TX_FIFO_FULL_MASK (1 << 16) /* Transmit FIFO Full Mask */
-#define RX_FIFO_FULL_MASK (1 << 17) /* Receive FIFO Full Mask */
-#define TX_FIFO_ZERO_MASK (1 << 18) /* Transmit FIFO Empty Mask */
-#define RX_DAT_ZERO_MASK (1 << 19) /* Receive FIFO Empty Mask */
-#define TX_DAT_RDY_MASK (1 << 20) /* Transmit Data Available Mask */
-#define RX_FIFO_RDY_MASK (1 << 21) /* Receive Data Available Mask */
-
-/* SDH_FIFO_CNT bitmasks */
-#define FIFO_COUNT 0x7fff /* FIFO Count */
-
-/* SDH_E_STATUS bitmasks */
-#define SDIO_INT_DET (1 << 1) /* SDIO Int Detected */
-#define SD_CARD_DET (1 << 4) /* SD Card Detect */
-#define SD_CARD_BUSYMODE (1 << 31) /* Card is in Busy mode */
-#define SD_CARD_SLPMODE (1 << 30) /* Card in Sleep Mode */
-#define SD_CARD_READY (1 << 17) /* Card Ready */
-
-/* SDH_E_MASK bitmasks */
-#define SDIO_MSK (1 << 1) /* Mask SDIO Int Detected */
-#define SCD_MSK (1 << 4) /* Mask Card Detect */
-#define CARD_READY_MSK (1 << 16) /* Mask Card Ready */
-
-/* SDH_CFG bitmasks */
-#define CLKS_EN (1 << 0) /* Clocks Enable */
-#define SD4E (1 << 2) /* SDIO 4-Bit Enable */
-#define MWE (1 << 3) /* Moving Window Enable */
-#define SD_RST (1 << 4) /* SDMMC Reset */
-#define PUP_SDDAT (1 << 5) /* Pull-up SD_DAT */
-#define PUP_SDDAT3 (1 << 6) /* Pull-up SD_DAT3 */
-#ifndef RSI_BLKSZ
-#define PD_SDDAT3 (1 << 7) /* Pull-down SD_DAT3 */
-#else
-#define PWR_ON 0x600 /* Power On */
-#define SD_CMD_OD (1 << 11) /* Open Drain Output */
-#define BOOT_EN (1 << 12) /* Boot Enable */
-#define BOOT_MODE (1 << 13) /* Alternate Boot Mode */
-#define BOOT_ACK_EN (1 << 14) /* Boot ACK is expected */
-#endif
-
-/* SDH_RD_WAIT_EN bitmasks */
-#define RWR (1 << 0) /* Read Wait Request */
-
-#endif
+++ /dev/null
-/*
- * bfin_serial.h - Blackfin UART/Serial definitions
- *
- * Copyright 2006-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_ASM_SERIAL_H__
-#define __BFIN_ASM_SERIAL_H__
-
-#include <linux/circ_buf.h>
-#include <linux/serial_core.h>
-#include <linux/spinlock.h>
-#include <linux/timer.h>
-#include <linux/workqueue.h>
-#include <mach/anomaly.h>
-#include <mach/bfin_serial.h>
-
-#if defined(CONFIG_BFIN_UART0_CTSRTS) || \
- defined(CONFIG_BFIN_UART1_CTSRTS) || \
- defined(CONFIG_BFIN_UART2_CTSRTS) || \
- defined(CONFIG_BFIN_UART3_CTSRTS)
-# if defined(BFIN_UART_BF54X_STYLE) || defined(BFIN_UART_BF60X_STYLE)
-# define SERIAL_BFIN_HARD_CTSRTS
-# else
-# define SERIAL_BFIN_CTSRTS
-# endif
-#endif
-
-struct bfin_serial_port {
- struct uart_port port;
- unsigned int old_status;
- int tx_irq;
- int rx_irq;
- int status_irq;
-#ifndef BFIN_UART_BF54X_STYLE
- unsigned int lsr;
-#endif
-#ifdef CONFIG_SERIAL_BFIN_DMA
- int tx_done;
- int tx_count;
- struct circ_buf rx_dma_buf;
- struct timer_list rx_dma_timer;
- int rx_dma_nrows;
- spinlock_t rx_lock;
- unsigned int tx_dma_channel;
- unsigned int rx_dma_channel;
- struct work_struct tx_dma_workqueue;
-#elif ANOMALY_05000363
- unsigned int anomaly_threshold;
-#endif
-#if defined(SERIAL_BFIN_CTSRTS) || \
- defined(SERIAL_BFIN_HARD_CTSRTS)
- int cts_pin;
- int rts_pin;
-#endif
-};
-
-#ifdef BFIN_UART_BF60X_STYLE
-
-/* UART_CTL Masks */
-#define UCEN 0x1 /* Enable UARTx Clocks */
-#define LOOP_ENA 0x2 /* Loopback Mode Enable */
-#define UMOD_MDB 0x10 /* Enable MDB Mode */
-#define UMOD_IRDA 0x20 /* Enable IrDA Mode */
-#define UMOD_MASK 0x30 /* Uart Mode Mask */
-#define WLS(x) (((x-5) & 0x03) << 8) /* Word Length Select */
-#define WLS_MASK 0x300 /* Word length Select Mask */
-#define WLS_OFFSET 8 /* Word length Select Offset */
-#define STB 0x1000 /* Stop Bits */
-#define STBH 0x2000 /* Half Stop Bits */
-#define PEN 0x4000 /* Parity Enable */
-#define EPS 0x8000 /* Even Parity Select */
-#define STP 0x10000 /* Stick Parity */
-#define FPE 0x20000 /* Force Parity Error On Transmit */
-#define FFE 0x40000 /* Force Framing Error On Transmit */
-#define SB 0x80000 /* Set Break */
-#define LCR_MASK (SB | STP | EPS | PEN | STB | WLS_MASK)
-#define FCPOL 0x400000 /* Flow Control Pin Polarity */
-#define RPOLC 0x800000 /* IrDA RX Polarity Change */
-#define TPOLC 0x1000000 /* IrDA TX Polarity Change */
-#define MRTS 0x2000000 /* Manual Request To Send */
-#define XOFF 0x4000000 /* Transmitter Off */
-#define ARTS 0x8000000 /* Automatic Request To Send */
-#define ACTS 0x10000000 /* Automatic Clear To Send */
-#define RFIT 0x20000000 /* Receive FIFO IRQ Threshold */
-#define RFRT 0x40000000 /* Receive FIFO RTS Threshold */
-
-/* UART_STAT Masks */
-#define DR 0x01 /* Data Ready */
-#define OE 0x02 /* Overrun Error */
-#define PE 0x04 /* Parity Error */
-#define FE 0x08 /* Framing Error */
-#define BI 0x10 /* Break Interrupt */
-#define THRE 0x20 /* THR Empty */
-#define TEMT 0x80 /* TSR and UART_THR Empty */
-#define TFI 0x100 /* Transmission Finished Indicator */
-
-#define ASTKY 0x200 /* Address Sticky */
-#define ADDR 0x400 /* Address bit status */
-#define RO 0x800 /* Reception Ongoing */
-#define SCTS 0x1000 /* Sticky CTS */
-#define CTS 0x10000 /* Clear To Send */
-#define RFCS 0x20000 /* Receive FIFO Count Status */
-
-/* UART_CLOCK Masks */
-#define EDBO 0x80000000 /* Enable Devide by One */
-
-#else /* BFIN_UART_BF60X_STYLE */
-
-/* UART_LCR Masks */
-#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
-#define WLS_MASK 0x03 /* Word length Select Mask */
-#define WLS_OFFSET 0 /* Word length Select Offset */
-#define STB 0x04 /* Stop Bits */
-#define PEN 0x08 /* Parity Enable */
-#define EPS 0x10 /* Even Parity Select */
-#define STP 0x20 /* Stick Parity */
-#define SB 0x40 /* Set Break */
-#define DLAB 0x80 /* Divisor Latch Access */
-#define LCR_MASK (SB | STP | EPS | PEN | STB | WLS_MASK)
-
-/* UART_LSR Masks */
-#define DR 0x01 /* Data Ready */
-#define OE 0x02 /* Overrun Error */
-#define PE 0x04 /* Parity Error */
-#define FE 0x08 /* Framing Error */
-#define BI 0x10 /* Break Interrupt */
-#define THRE 0x20 /* THR Empty */
-#define TEMT 0x40 /* TSR and UART_THR Empty */
-#define TFI 0x80 /* Transmission Finished Indicator */
-
-/* UART_MCR Masks */
-#define XOFF 0x01 /* Transmitter Off */
-#define MRTS 0x02 /* Manual Request To Send */
-#define RFIT 0x04 /* Receive FIFO IRQ Threshold */
-#define RFRT 0x08 /* Receive FIFO RTS Threshold */
-#define LOOP_ENA 0x10 /* Loopback Mode Enable */
-#define FCPOL 0x20 /* Flow Control Pin Polarity */
-#define ARTS 0x40 /* Automatic Request To Send */
-#define ACTS 0x80 /* Automatic Clear To Send */
-
-/* UART_MSR Masks */
-#define SCTS 0x01 /* Sticky CTS */
-#define CTS 0x10 /* Clear To Send */
-#define RFCS 0x20 /* Receive FIFO Count Status */
-
-/* UART_GCTL Masks */
-#define UCEN 0x01 /* Enable UARTx Clocks */
-#define UMOD_IRDA 0x02 /* Enable IrDA Mode */
-#define UMOD_MASK 0x02 /* Uart Mode Mask */
-#define TPOLC 0x04 /* IrDA TX Polarity Change */
-#define RPOLC 0x08 /* IrDA RX Polarity Change */
-#define FPE 0x10 /* Force Parity Error On Transmit */
-#define FFE 0x20 /* Force Framing Error On Transmit */
-
-#endif /* BFIN_UART_BF60X_STYLE */
-
-/* UART_IER Masks */
-#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */
-#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */
-#define ELSI 0x04 /* Enable RX Status Interrupt */
-#define EDSSI 0x08 /* Enable Modem Status Interrupt */
-#define EDTPTI 0x10 /* Enable DMA Transmit PIRQ Interrupt */
-#define ETFI 0x20 /* Enable Transmission Finished Interrupt */
-#define ERFCI 0x40 /* Enable Receive FIFO Count Interrupt */
-
-#if defined(BFIN_UART_BF60X_STYLE)
-# define OFFSET_REDIV 0x00 /* Version ID Register */
-# define OFFSET_CTL 0x04 /* Control Register */
-# define OFFSET_STAT 0x08 /* Status Register */
-# define OFFSET_SCR 0x0C /* SCR Scratch Register */
-# define OFFSET_CLK 0x10 /* Clock Rate Register */
-# define OFFSET_IER 0x14 /* Interrupt Enable Register */
-# define OFFSET_IER_SET 0x18 /* Set Interrupt Enable Register */
-# define OFFSET_IER_CLEAR 0x1C /* Clear Interrupt Enable Register */
-# define OFFSET_RBR 0x20 /* Receive Buffer register */
-# define OFFSET_THR 0x24 /* Transmit Holding register */
-#elif defined(BFIN_UART_BF54X_STYLE)
-# define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
-# define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
-# define OFFSET_GCTL 0x08 /* Global Control Register */
-# define OFFSET_LCR 0x0C /* Line Control Register */
-# define OFFSET_MCR 0x10 /* Modem Control Register */
-# define OFFSET_LSR 0x14 /* Line Status Register */
-# define OFFSET_MSR 0x18 /* Modem Status Register */
-# define OFFSET_SCR 0x1C /* SCR Scratch Register */
-# define OFFSET_IER_SET 0x20 /* Set Interrupt Enable Register */
-# define OFFSET_IER_CLEAR 0x24 /* Clear Interrupt Enable Register */
-# define OFFSET_THR 0x28 /* Transmit Holding register */
-# define OFFSET_RBR 0x2C /* Receive Buffer register */
-#else /* BF533 style */
-# define OFFSET_THR 0x00 /* Transmit Holding register */
-# define OFFSET_RBR 0x00 /* Receive Buffer register */
-# define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
-# define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
-# define OFFSET_IER 0x04 /* Interrupt Enable Register */
-# define OFFSET_IIR 0x08 /* Interrupt Identification Register */
-# define OFFSET_LCR 0x0C /* Line Control Register */
-# define OFFSET_MCR 0x10 /* Modem Control Register */
-# define OFFSET_LSR 0x14 /* Line Status Register */
-# define OFFSET_MSR 0x18 /* Modem Status Register */
-# define OFFSET_SCR 0x1C /* SCR Scratch Register */
-# define OFFSET_GCTL 0x24 /* Global Control Register */
-/* code should not need IIR, so force build error if they use it */
-# undef OFFSET_IIR
-#endif
-
-/*
- * All Blackfin system MMRs are padded to 32bits even if the register
- * itself is only 16bits. So use a helper macro to streamline this.
- */
-#define __BFP(m) u16 m; u16 __pad_##m
-struct bfin_uart_regs {
-#if defined(BFIN_UART_BF60X_STYLE)
- u32 revid;
- u32 ctl;
- u32 stat;
- u32 scr;
- u32 clk;
- u32 ier;
- u32 ier_set;
- u32 ier_clear;
- u32 rbr;
- u32 thr;
- u32 taip;
- u32 tsr;
- u32 rsr;
- u32 txdiv;
- u32 rxdiv;
-#elif defined(BFIN_UART_BF54X_STYLE)
- __BFP(dll);
- __BFP(dlh);
- __BFP(gctl);
- __BFP(lcr);
- __BFP(mcr);
- __BFP(lsr);
- __BFP(msr);
- __BFP(scr);
- __BFP(ier_set);
- __BFP(ier_clear);
- __BFP(thr);
- __BFP(rbr);
-#else
- union {
- u16 dll;
- u16 thr;
- const u16 rbr;
- };
- const u16 __pad0;
- union {
- u16 dlh;
- u16 ier;
- };
- const u16 __pad1;
- const __BFP(iir);
- __BFP(lcr);
- __BFP(mcr);
- __BFP(lsr);
- __BFP(msr);
- __BFP(scr);
- const u32 __pad2;
- __BFP(gctl);
-#endif
-};
-#undef __BFP
-
-#define port_membase(uart) (((struct bfin_serial_port *)(uart))->port.membase)
-
-/*
-#ifndef port_membase
-# define port_membase(p) 0
-#endif
-*/
-#ifdef BFIN_UART_BF60X_STYLE
-
-#define UART_GET_CHAR(p) bfin_read32(port_membase(p) + OFFSET_RBR)
-#define UART_GET_CLK(p) bfin_read32(port_membase(p) + OFFSET_CLK)
-#define UART_GET_CTL(p) bfin_read32(port_membase(p) + OFFSET_CTL)
-#define UART_GET_GCTL(p) UART_GET_CTL(p)
-#define UART_GET_LCR(p) UART_GET_CTL(p)
-#define UART_GET_MCR(p) UART_GET_CTL(p)
-#if ANOMALY_16000030
-#define UART_GET_STAT(p) \
-({ \
- u32 __ret; \
- unsigned long flags; \
- flags = hard_local_irq_save(); \
- __ret = bfin_read32(port_membase(p) + OFFSET_STAT); \
- hard_local_irq_restore(flags); \
- __ret; \
-})
-#else
-#define UART_GET_STAT(p) bfin_read32(port_membase(p) + OFFSET_STAT)
-#endif
-#define UART_GET_MSR(p) UART_GET_STAT(p)
-
-#define UART_PUT_CHAR(p, v) bfin_write32(port_membase(p) + OFFSET_THR, v)
-#define UART_PUT_CLK(p, v) bfin_write32(port_membase(p) + OFFSET_CLK, v)
-#define UART_PUT_CTL(p, v) bfin_write32(port_membase(p) + OFFSET_CTL, v)
-#define UART_PUT_GCTL(p, v) UART_PUT_CTL(p, v)
-#define UART_PUT_LCR(p, v) UART_PUT_CTL(p, v)
-#define UART_PUT_MCR(p, v) UART_PUT_CTL(p, v)
-#define UART_PUT_STAT(p, v) bfin_write32(port_membase(p) + OFFSET_STAT, v)
-
-#define UART_CLEAR_IER(p, v) bfin_write32(port_membase(p) + OFFSET_IER_CLEAR, v)
-#define UART_GET_IER(p) bfin_read32(port_membase(p) + OFFSET_IER)
-#define UART_SET_IER(p, v) bfin_write32(port_membase(p) + OFFSET_IER_SET, v)
-
-#define UART_CLEAR_DLAB(p) /* MMRs not muxed on BF60x */
-#define UART_SET_DLAB(p) /* MMRs not muxed on BF60x */
-
-#define UART_CLEAR_LSR(p) UART_PUT_STAT(p, -1)
-#define UART_GET_LSR(p) UART_GET_STAT(p)
-#define UART_PUT_LSR(p, v) UART_PUT_STAT(p, v)
-
-/* This handles hard CTS/RTS */
-#define BFIN_UART_CTSRTS_HARD
-#define UART_CLEAR_SCTS(p) UART_PUT_STAT(p, SCTS)
-#define UART_GET_CTS(x) (UART_GET_MSR(x) & CTS)
-#define UART_DISABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) & ~(ARTS | MRTS))
-#define UART_ENABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) | MRTS | ARTS)
-#define UART_ENABLE_INTS(x, v) UART_SET_IER(x, v)
-#define UART_DISABLE_INTS(x) UART_CLEAR_IER(x, 0xF)
-
-#else /* BFIN_UART_BF60X_STYLE */
-
-#define UART_GET_CHAR(p) bfin_read16(port_membase(p) + OFFSET_RBR)
-#define UART_GET_DLL(p) bfin_read16(port_membase(p) + OFFSET_DLL)
-#define UART_GET_DLH(p) bfin_read16(port_membase(p) + OFFSET_DLH)
-#define UART_GET_CLK(p) ((UART_GET_DLH(p) << 8) | UART_GET_DLL(p))
-#define UART_GET_GCTL(p) bfin_read16(port_membase(p) + OFFSET_GCTL)
-#define UART_GET_LCR(p) bfin_read16(port_membase(p) + OFFSET_LCR)
-#define UART_GET_MCR(p) bfin_read16(port_membase(p) + OFFSET_MCR)
-#define UART_GET_MSR(p) bfin_read16(port_membase(p) + OFFSET_MSR)
-
-#define UART_PUT_CHAR(p, v) bfin_write16(port_membase(p) + OFFSET_THR, v)
-#define UART_PUT_DLL(p, v) bfin_write16(port_membase(p) + OFFSET_DLL, v)
-#define UART_PUT_DLH(p, v) bfin_write16(port_membase(p) + OFFSET_DLH, v)
-#define UART_PUT_CLK(p, v) do \
-{\
-UART_PUT_DLL(p, v & 0xFF); \
-UART_PUT_DLH(p, (v >> 8) & 0xFF); } while (0);
-
-#define UART_PUT_GCTL(p, v) bfin_write16(port_membase(p) + OFFSET_GCTL, v)
-#define UART_PUT_LCR(p, v) bfin_write16(port_membase(p) + OFFSET_LCR, v)
-#define UART_PUT_MCR(p, v) bfin_write16(port_membase(p) + OFFSET_MCR, v)
-
-#ifdef BFIN_UART_BF54X_STYLE
-
-#define UART_CLEAR_IER(p, v) bfin_write16(port_membase(p) + OFFSET_IER_CLEAR, v)
-#define UART_GET_IER(p) bfin_read16(port_membase(p) + OFFSET_IER_SET)
-#define UART_SET_IER(p, v) bfin_write16(port_membase(p) + OFFSET_IER_SET, v)
-
-#define UART_CLEAR_DLAB(p) /* MMRs not muxed on BF54x */
-#define UART_SET_DLAB(p) /* MMRs not muxed on BF54x */
-
-#define UART_CLEAR_LSR(p) bfin_write16(port_membase(p) + OFFSET_LSR, -1)
-#define UART_GET_LSR(p) bfin_read16(port_membase(p) + OFFSET_LSR)
-#define UART_PUT_LSR(p, v) bfin_write16(port_membase(p) + OFFSET_LSR, v)
-
-/* This handles hard CTS/RTS */
-#define BFIN_UART_CTSRTS_HARD
-#define UART_CLEAR_SCTS(p) bfin_write16((port_membase(p) + OFFSET_MSR), SCTS)
-#define UART_GET_CTS(x) (UART_GET_MSR(x) & CTS)
-#define UART_DISABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) & ~(ARTS | MRTS))
-#define UART_ENABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) | MRTS | ARTS)
-#define UART_ENABLE_INTS(x, v) UART_SET_IER(x, v)
-#define UART_DISABLE_INTS(x) UART_CLEAR_IER(x, 0xF)
-
-#else /* BF533 style */
-
-#define UART_CLEAR_IER(p, v) UART_PUT_IER(p, UART_GET_IER(p) & ~(v))
-#define UART_GET_IER(p) bfin_read16(port_membase(p) + OFFSET_IER)
-#define UART_PUT_IER(p, v) bfin_write16(port_membase(p) + OFFSET_IER, v)
-#define UART_SET_IER(p, v) UART_PUT_IER(p, UART_GET_IER(p) | (v))
-
-#define UART_CLEAR_DLAB(p) do { UART_PUT_LCR(p, UART_GET_LCR(p) & ~DLAB); SSYNC(); } while (0)
-#define UART_SET_DLAB(p) do { UART_PUT_LCR(p, UART_GET_LCR(p) | DLAB); SSYNC(); } while (0)
-
-#define get_lsr_cache(uart) (((struct bfin_serial_port *)(uart))->lsr)
-#define put_lsr_cache(uart, v) (((struct bfin_serial_port *)(uart))->lsr = (v))
-
-/*
-#ifndef put_lsr_cache
-# define put_lsr_cache(p, v)
-#endif
-#ifndef get_lsr_cache
-# define get_lsr_cache(p) 0
-#endif
-*/
-
-/* The hardware clears the LSR bits upon read, so we need to cache
- * some of the more fun bits in software so they don't get lost
- * when checking the LSR in other code paths (TX).
- */
-static inline void UART_CLEAR_LSR(void *p)
-{
- put_lsr_cache(p, 0);
- bfin_write16(port_membase(p) + OFFSET_LSR, -1);
-}
-static inline unsigned int UART_GET_LSR(void *p)
-{
- unsigned int lsr = bfin_read16(port_membase(p) + OFFSET_LSR);
- put_lsr_cache(p, get_lsr_cache(p) | (lsr & (BI|FE|PE|OE)));
- return lsr | get_lsr_cache(p);
-}
-static inline void UART_PUT_LSR(void *p, uint16_t val)
-{
- put_lsr_cache(p, get_lsr_cache(p) & ~val);
-}
-
-/* This handles soft CTS/RTS */
-#define UART_GET_CTS(x) gpio_get_value((x)->cts_pin)
-#define UART_DISABLE_RTS(x) gpio_set_value((x)->rts_pin, 1)
-#define UART_ENABLE_RTS(x) gpio_set_value((x)->rts_pin, 0)
-#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
-#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
-
-#endif /* BFIN_UART_BF54X_STYLE */
-
-#endif /* BFIN_UART_BF60X_STYLE */
-
-#ifndef BFIN_UART_TX_FIFO_SIZE
-# define BFIN_UART_TX_FIFO_SIZE 2
-#endif
-
-#endif /* __BFIN_ASM_SERIAL_H__ */
+++ /dev/null
-/*
- * Copyright 2006-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _bfin_simple_timer_h_
-#define _bfin_simple_timer_h_
-
-#include <linux/ioctl.h>
-
-#define BFIN_SIMPLE_TIMER_IOCTL_MAGIC 't'
-
-#define BFIN_SIMPLE_TIMER_SET_PERIOD _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 2)
-#define BFIN_SIMPLE_TIMER_SET_WIDTH _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 3)
-#define BFIN_SIMPLE_TIMER_SET_MODE _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 4)
-#define BFIN_SIMPLE_TIMER_START _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 6)
-#define BFIN_SIMPLE_TIMER_STOP _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 8)
-#define BFIN_SIMPLE_TIMER_READ _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 10)
-#define BFIN_SIMPLE_TIMER_READ_COUNTER _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 11)
-
-#define BFIN_SIMPLE_TIMER_MODE_PWM_ONESHOT 0
-#define BFIN_SIMPLE_TIMER_MODE_PWMOUT_CONT 1
-#define BFIN_SIMPLE_TIMER_MODE_WDTH_CAP 2
-#define BFIN_SIMPLE_TIMER_MODE_PWMOUT_CONT_NOIRQ 3
-
-#endif
+++ /dev/null
-/*
- * bfin_sport.h - interface to Blackfin SPORTs
- *
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-#ifndef __BFIN_SPORT_H__
-#define __BFIN_SPORT_H__
-
-
-#include <linux/types.h>
-#include <uapi/asm/bfin_sport.h>
-
-/*
- * All Blackfin system MMRs are padded to 32bits even if the register
- * itself is only 16bits. So use a helper macro to streamline this.
- */
-#define __BFP(m) u16 m; u16 __pad_##m
-struct sport_register {
- __BFP(tcr1);
- __BFP(tcr2);
- __BFP(tclkdiv);
- __BFP(tfsdiv);
- union {
- u32 tx32;
- u16 tx16;
- };
- u32 __pad_tx;
- union {
- u32 rx32; /* use the anomaly wrapper below */
- u16 rx16;
- };
- u32 __pad_rx;
- __BFP(rcr1);
- __BFP(rcr2);
- __BFP(rclkdiv);
- __BFP(rfsdiv);
- __BFP(stat);
- __BFP(chnl);
- __BFP(mcmc1);
- __BFP(mcmc2);
- u32 mtcs0;
- u32 mtcs1;
- u32 mtcs2;
- u32 mtcs3;
- u32 mrcs0;
- u32 mrcs1;
- u32 mrcs2;
- u32 mrcs3;
-};
-#undef __BFP
-
-struct bfin_snd_platform_data {
- const unsigned short *pin_req;
-};
-
-#define bfin_read_sport_rx32(base) \
-({ \
- struct sport_register *__mmrs = (void *)base; \
- u32 __ret; \
- unsigned long flags; \
- if (ANOMALY_05000473) \
- local_irq_save(flags); \
- __ret = __mmrs->rx32; \
- if (ANOMALY_05000473) \
- local_irq_restore(flags); \
- __ret; \
-})
-
-#endif
+++ /dev/null
-/*
- * bfin_sport - Analog Devices BF6XX SPORT registers
- *
- * Copyright (c) 2012 Analog Devices Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef _BFIN_SPORT3_H_
-#define _BFIN_SPORT3_H_
-
-#include <linux/types.h>
-
-#define SPORT_CTL_SPENPRI 0x00000001 /* Enable Primary Channel */
-#define SPORT_CTL_DTYPE 0x00000006 /* Data type select */
-#define SPORT_CTL_RJUSTIFY_ZFILL 0x00000000 /* DTYPE: MCM mode: Right-justify, zero-fill unused MSBs */
-#define SPORT_CTL_RJUSTIFY_SFILL 0x00000002 /* DTYPE: MCM mode: Right-justify, sign-extend unused MSBs */
-#define SPORT_CTL_USE_U_LAW 0x00000004 /* DTYPE: MCM mode: Compand using u-law */
-#define SPORT_CTL_USE_A_LAW 0x00000006 /* DTYPE: MCM mode: Compand using A-law */
-#define SPORT_CTL_LSBF 0x00000008 /* Serial bit endian select */
-#define SPORT_CTL_SLEN 0x000001F0 /* Serial Word length select */
-#define SPORT_CTL_PACK 0x00000200 /* 16-bit to 32-bit packing enable */
-#define SPORT_CTL_ICLK 0x00000400 /* Internal Clock Select */
-#define SPORT_CTL_OPMODE 0x00000800 /* Operation mode */
-#define SPORT_CTL_CKRE 0x00001000 /* Clock rising edge select */
-#define SPORT_CTL_FSR 0x00002000 /* Frame Sync required */
-#define SPORT_CTL_IFS 0x00004000 /* Internal Frame Sync select */
-#define SPORT_CTL_DIFS 0x00008000 /* Data-independent frame sync select */
-#define SPORT_CTL_LFS 0x00010000 /* Active low frame sync select */
-#define SPORT_CTL_LAFS 0x00020000 /* Late Transmit frame select */
-#define SPORT_CTL_RJUST 0x00040000 /* Right Justified mode select */
-#define SPORT_CTL_FSED 0x00080000 /* External frame sync edge select */
-#define SPORT_CTL_TFIEN 0x00100000 /* Transmit finish interrupt enable select */
-#define SPORT_CTL_GCLKEN 0x00200000 /* Gated clock mode select */
-#define SPORT_CTL_SPENSEC 0x01000000 /* Enable secondary channel */
-#define SPORT_CTL_SPTRAN 0x02000000 /* Data direction control */
-#define SPORT_CTL_DERRSEC 0x04000000 /* Secondary channel error status */
-#define SPORT_CTL_DXSSEC 0x18000000 /* Secondary channel data buffer status */
-#define SPORT_CTL_SEC_EMPTY 0x00000000 /* DXSSEC: Empty */
-#define SPORT_CTL_SEC_PART_FULL 0x10000000 /* DXSSEC: Partially full */
-#define SPORT_CTL_SEC_FULL 0x18000000 /* DXSSEC: Full */
-#define SPORT_CTL_DERRPRI 0x20000000 /* Primary channel error status */
-#define SPORT_CTL_DXSPRI 0xC0000000 /* Primary channel data buffer status */
-#define SPORT_CTL_PRM_EMPTY 0x00000000 /* DXSPRI: Empty */
-#define SPORT_CTL_PRM_PART_FULL 0x80000000 /* DXSPRI: Partially full */
-#define SPORT_CTL_PRM_FULL 0xC0000000 /* DXSPRI: Full */
-
-#define SPORT_DIV_CLKDIV 0x0000FFFF /* Clock divisor */
-#define SPORT_DIV_FSDIV 0xFFFF0000 /* Frame sync divisor */
-
-#define SPORT_MCTL_MCE 0x00000001 /* Multichannel enable */
-#define SPORT_MCTL_MCPDE 0x00000004 /* Multichannel data packing select */
-#define SPORT_MCTL_MFD 0x000000F0 /* Multichannel frame delay */
-#define SPORT_MCTL_WSIZE 0x00007F00 /* Number of multichannel slots */
-#define SPORT_MCTL_WOFFSET 0x03FF0000 /* Window offset size */
-
-#define SPORT_CNT_CLKCNT 0x0000FFFF /* Current state of clk div counter */
-#define SPORT_CNT_FSDIVCNT 0xFFFF0000 /* Current state of frame div counter */
-
-#define SPORT_ERR_DERRPMSK 0x00000001 /* Primary channel data error interrupt enable */
-#define SPORT_ERR_DERRSMSK 0x00000002 /* Secondary channel data error interrupt enable */
-#define SPORT_ERR_FSERRMSK 0x00000004 /* Frame sync error interrupt enable */
-#define SPORT_ERR_DERRPSTAT 0x00000010 /* Primary channel data error status */
-#define SPORT_ERR_DERRSSTAT 0x00000020 /* Secondary channel data error status */
-#define SPORT_ERR_FSERRSTAT 0x00000040 /* Frame sync error status */
-
-#define SPORT_MSTAT_CURCHAN 0x000003FF /* Channel which is being serviced in the multichannel operation */
-
-#define SPORT_CTL2_FSMUXSEL 0x00000001 /* Frame Sync MUX Select */
-#define SPORT_CTL2_CKMUXSEL 0x00000002 /* Clock MUX Select */
-#define SPORT_CTL2_LBSEL 0x00000004 /* Loopback Select */
-
-struct sport_register {
- u32 spctl;
- u32 div;
- u32 spmctl;
- u32 spcs0;
- u32 spcs1;
- u32 spcs2;
- u32 spcs3;
- u32 spcnt;
- u32 sperrctl;
- u32 spmstat;
- u32 spctl2;
- u32 txa;
- u32 rxa;
- u32 txb;
- u32 rxb;
- u32 revid;
-};
-
-struct bfin_snd_platform_data {
- const unsigned short *pin_req;
-};
-
-#endif
+++ /dev/null
-/*
- * bfin_twi.h - interface to Blackfin TWIs
- *
- * Copyright 2005-2014 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_BFIN_TWI_H__
-#define __ASM_BFIN_TWI_H__
-
-#include <asm/blackfin.h>
-#include <linux/types.h>
-#include <linux/i2c.h>
-
-/*
- * ADI twi registers layout
- */
-struct bfin_twi_regs {
- u16 clkdiv;
- u16 dummy1;
- u16 control;
- u16 dummy2;
- u16 slave_ctl;
- u16 dummy3;
- u16 slave_stat;
- u16 dummy4;
- u16 slave_addr;
- u16 dummy5;
- u16 master_ctl;
- u16 dummy6;
- u16 master_stat;
- u16 dummy7;
- u16 master_addr;
- u16 dummy8;
- u16 int_stat;
- u16 dummy9;
- u16 int_mask;
- u16 dummy10;
- u16 fifo_ctl;
- u16 dummy11;
- u16 fifo_stat;
- u16 dummy12;
- u32 __pad[20];
- u16 xmt_data8;
- u16 dummy13;
- u16 xmt_data16;
- u16 dummy14;
- u16 rcv_data8;
- u16 dummy15;
- u16 rcv_data16;
- u16 dummy16;
-};
-
-struct bfin_twi_iface {
- int irq;
- spinlock_t lock;
- char read_write;
- u8 command;
- u8 *transPtr;
- int readNum;
- int writeNum;
- int cur_mode;
- int manual_stop;
- int result;
- struct i2c_adapter adap;
- struct completion complete;
- struct i2c_msg *pmsg;
- int msg_num;
- int cur_msg;
- u16 saved_clkdiv;
- u16 saved_control;
- struct bfin_twi_regs __iomem *regs_base;
-};
-
-/* ******************** TWO-WIRE INTERFACE (TWI) MASKS ********************/
-/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */
-#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */
-#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */
-
-/* TWI_PRESCALE Masks */
-#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */
-#define TWI_ENA 0x0080 /* TWI Enable */
-#define SCCB 0x0200 /* SCCB Compatibility Enable */
-
-/* TWI_SLAVE_CTL Masks */
-#define SEN 0x0001 /* Slave Enable */
-#define SADD_LEN 0x0002 /* Slave Address Length */
-#define STDVAL 0x0004 /* Slave Transmit Data Valid */
-#define NAK 0x0008 /* NAK Generated At Conclusion Of Transfer */
-#define GEN 0x0010 /* General Call Address Matching Enabled */
-
-/* TWI_SLAVE_STAT Masks */
-#define SDIR 0x0001 /* Slave Transfer Direction (RX/TX*) */
-#define GCALL 0x0002 /* General Call Indicator */
-
-/* TWI_MASTER_CTL Masks */
-#define MEN 0x0001 /* Master Mode Enable */
-#define MADD_LEN 0x0002 /* Master Address Length */
-#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */
-#define FAST 0x0008 /* Use Fast Mode Timing Specs */
-#define STOP 0x0010 /* Issue Stop Condition */
-#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */
-#define DCNT 0x3FC0 /* Data Bytes To Transfer */
-#define SDAOVR 0x4000 /* Serial Data Override */
-#define SCLOVR 0x8000 /* Serial Clock Override */
-
-/* TWI_MASTER_STAT Masks */
-#define MPROG 0x0001 /* Master Transfer In Progress */
-#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */
-#define ANAK 0x0004 /* Address Not Acknowledged */
-#define DNAK 0x0008 /* Data Not Acknowledged */
-#define BUFRDERR 0x0010 /* Buffer Read Error */
-#define BUFWRERR 0x0020 /* Buffer Write Error */
-#define SDASEN 0x0040 /* Serial Data Sense */
-#define SCLSEN 0x0080 /* Serial Clock Sense */
-#define BUSBUSY 0x0100 /* Bus Busy Indicator */
-
-/* TWI_INT_SRC and TWI_INT_ENABLE Masks */
-#define SINIT 0x0001 /* Slave Transfer Initiated */
-#define SCOMP 0x0002 /* Slave Transfer Complete */
-#define SERR 0x0004 /* Slave Transfer Error */
-#define SOVF 0x0008 /* Slave Overflow */
-#define MCOMP 0x0010 /* Master Transfer Complete */
-#define MERR 0x0020 /* Master Transfer Error */
-#define XMTSERV 0x0040 /* Transmit FIFO Service */
-#define RCVSERV 0x0080 /* Receive FIFO Service */
-
-/* TWI_FIFO_CTRL Masks */
-#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */
-#define RCVFLUSH 0x0002 /* Receive Buffer Flush */
-#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */
-#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */
-
-/* TWI_FIFO_STAT Masks */
-#define XMTSTAT 0x0003 /* Transmit FIFO Status */
-#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */
-#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */
-#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */
-
-#define RCVSTAT 0x000C /* Receive FIFO Status */
-#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */
-#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */
-#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */
-
-#define DEFINE_TWI_REG(reg_name, reg) \
-static inline u16 read_##reg_name(struct bfin_twi_iface *iface) \
- { return bfin_read16(&iface->regs_base->reg); } \
-static inline void write_##reg_name(struct bfin_twi_iface *iface, u16 v) \
- { bfin_write16(&iface->regs_base->reg, v); }
-
-DEFINE_TWI_REG(CLKDIV, clkdiv)
-DEFINE_TWI_REG(SLAVE_CTL, slave_ctl)
-DEFINE_TWI_REG(SLAVE_STAT, slave_stat)
-DEFINE_TWI_REG(SLAVE_ADDR, slave_addr)
-DEFINE_TWI_REG(MASTER_CTL, master_ctl)
-DEFINE_TWI_REG(MASTER_STAT, master_stat)
-DEFINE_TWI_REG(MASTER_ADDR, master_addr)
-DEFINE_TWI_REG(INT_STAT, int_stat)
-DEFINE_TWI_REG(INT_MASK, int_mask)
-DEFINE_TWI_REG(FIFO_STAT, fifo_stat)
-DEFINE_TWI_REG(XMT_DATA8, xmt_data8)
-DEFINE_TWI_REG(XMT_DATA16, xmt_data16)
-#if !ANOMALY_16000030
-DEFINE_TWI_REG(RCV_DATA8, rcv_data8)
-DEFINE_TWI_REG(RCV_DATA16, rcv_data16)
-#else
-static inline u16 read_RCV_DATA8(struct bfin_twi_iface *iface)
-{
- u16 ret;
- unsigned long flags;
-
- flags = hard_local_irq_save();
- ret = bfin_read16(&iface->regs_base->rcv_data8);
- hard_local_irq_restore(flags);
-
- return ret;
-}
-
-static inline u16 read_RCV_DATA16(struct bfin_twi_iface *iface)
-{
- u16 ret;
- unsigned long flags;
-
- flags = hard_local_irq_save();
- ret = bfin_read16(&iface->regs_base->rcv_data16);
- hard_local_irq_restore(flags);
-
- return ret;
-}
-#endif
-
-static inline u16 read_FIFO_CTL(struct bfin_twi_iface *iface)
-{
- return bfin_read16(&iface->regs_base->fifo_ctl);
-}
-
-static inline void write_FIFO_CTL(struct bfin_twi_iface *iface, u16 v)
-{
- bfin_write16(&iface->regs_base->fifo_ctl, v);
- SSYNC();
-}
-
-static inline u16 read_CONTROL(struct bfin_twi_iface *iface)
-{
- return bfin_read16(&iface->regs_base->control);
-}
-
-static inline void write_CONTROL(struct bfin_twi_iface *iface, u16 v)
-{
- SSYNC();
- bfin_write16(&iface->regs_base->control, v);
-}
-#endif
+++ /dev/null
-/*
- * bfin_watchdog.h - Blackfin watchdog definitions
- *
- * Copyright 2006-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BFIN_WATCHDOG_H
-#define _BFIN_WATCHDOG_H
-
-/* Bit in SWRST that indicates boot caused by watchdog */
-#define SWRST_RESET_WDOG 0x4000
-
-/* Bit in WDOG_CTL that indicates watchdog has expired (WDR0) */
-#define WDOG_EXPIRED 0x8000
-
-/* Masks for WDEV field in WDOG_CTL register */
-#define ICTL_RESET 0x0
-#define ICTL_NMI 0x2
-#define ICTL_GPI 0x4
-#define ICTL_NONE 0x6
-#define ICTL_MASK 0x6
-
-/* Masks for WDEN field in WDOG_CTL register */
-#define WDEN_MASK 0x0FF0
-#define WDEN_ENABLE 0x0000
-#define WDEN_DISABLE 0x0AD0
-
-#endif
+++ /dev/null
-/* Blackfin on-chip ROM API
- *
- * Copyright 2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFROM_H__
-#define __BFROM_H__
-
-#include <linux/types.h>
-
-/* Possible syscontrol action flags */
-#define SYSCTRL_READ 0x00000000 /* read registers */
-#define SYSCTRL_WRITE 0x00000001 /* write registers */
-#define SYSCTRL_SYSRESET 0x00000002 /* perform system reset */
-#define SYSCTRL_CORERESET 0x00000004 /* perform core reset */
-#define SYSCTRL_SOFTRESET 0x00000006 /* perform core and system reset */
-#define SYSCTRL_VRCTL 0x00000010 /* read/write VR_CTL register */
-#define SYSCTRL_EXTVOLTAGE 0x00000020 /* VDDINT supplied externally */
-#define SYSCTRL_INTVOLTAGE 0x00000000 /* VDDINT generated by on-chip regulator */
-#define SYSCTRL_OTPVOLTAGE 0x00000040 /* For Factory Purposes Only */
-#define SYSCTRL_PLLCTL 0x00000100 /* read/write PLL_CTL register */
-#define SYSCTRL_PLLDIV 0x00000200 /* read/write PLL_DIV register */
-#define SYSCTRL_LOCKCNT 0x00000400 /* read/write PLL_LOCKCNT register */
-#define SYSCTRL_PLLSTAT 0x00000800 /* read/write PLL_STAT register */
-
-typedef struct ADI_SYSCTRL_VALUES {
- uint16_t uwVrCtl;
- uint16_t uwPllCtl;
- uint16_t uwPllDiv;
- uint16_t uwPllLockCnt;
- uint16_t uwPllStat;
-} ADI_SYSCTRL_VALUES;
-
-static uint32_t (* const bfrom_SysControl)(uint32_t action_flags, ADI_SYSCTRL_VALUES *power_settings, void *reserved) = (void *)0xEF000038;
-
-/* We need a dedicated function since we need to screw with the stack pointer
- * when resetting. The on-chip ROM will save/restore registers on the stack
- * when doing a system reset, so the stack cannot be outside of the chip.
- */
-__attribute__((__noreturn__))
-static inline void bfrom_SoftReset(void *new_stack)
-{
- while (1)
- /*
- * We don't declare the SP as clobbered on purpose, since
- * it confuses the heck out of the compiler, and this function
- * never returns
- */
- __asm__ __volatile__(
- "sp = %[stack];"
- "jump (%[bfrom_syscontrol]);"
- : : [bfrom_syscontrol] "p"(bfrom_SysControl),
- "q0"(SYSCTRL_SOFTRESET),
- "q1"(0),
- "q2"(NULL),
- [stack] "p"(new_stack)
- );
-}
-
-/* OTP Functions */
-static uint32_t (* const bfrom_OtpCommand)(uint32_t command, uint32_t value) = (void *)0xEF000018;
-static uint32_t (* const bfrom_OtpRead)(uint32_t page, uint32_t flags, uint64_t *page_content) = (void *)0xEF00001A;
-static uint32_t (* const bfrom_OtpWrite)(uint32_t page, uint32_t flags, uint64_t *page_content) = (void *)0xEF00001C;
-
-/* otp command: defines for "command" */
-#define OTP_INIT 0x00000001
-#define OTP_CLOSE 0x00000002
-
-/* otp read/write: defines for "flags" */
-#define OTP_LOWER_HALF 0x00000000 /* select upper/lower 64-bit half (bit 0) */
-#define OTP_UPPER_HALF 0x00000001
-#define OTP_NO_ECC 0x00000010 /* do not use ECC */
-#define OTP_LOCK 0x00000020 /* sets page protection bit for page */
-#define OTP_CHECK_FOR_PREV_WRITE 0x00000080
-
-/* Return values for all functions */
-#define OTP_SUCCESS 0x00000000
-#define OTP_MASTER_ERROR 0x001
-#define OTP_WRITE_ERROR 0x003
-#define OTP_READ_ERROR 0x005
-#define OTP_ACC_VIO_ERROR 0x009
-#define OTP_DATA_MULT_ERROR 0x011
-#define OTP_ECC_MULT_ERROR 0x021
-#define OTP_PREV_WR_ERROR 0x041
-#define OTP_DATA_SB_WARN 0x100
-#define OTP_ECC_SB_WARN 0x200
-
-#endif
+++ /dev/null
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BLACKFIN_BITOPS_H
-#define _BLACKFIN_BITOPS_H
-
-#include <linux/compiler.h>
-
-#include <asm-generic/bitops/__ffs.h>
-#include <asm-generic/bitops/ffz.h>
-#include <asm-generic/bitops/fls.h>
-#include <asm-generic/bitops/__fls.h>
-#include <asm-generic/bitops/fls64.h>
-#include <asm-generic/bitops/find.h>
-
-#ifndef _LINUX_BITOPS_H
-#error only <linux/bitops.h> can be included directly
-#endif
-
-#include <asm-generic/bitops/sched.h>
-#include <asm-generic/bitops/ffs.h>
-#include <asm-generic/bitops/const_hweight.h>
-#include <asm-generic/bitops/lock.h>
-
-#include <asm-generic/bitops/ext2-atomic.h>
-
-#include <asm/barrier.h>
-
-#ifndef CONFIG_SMP
-#include <linux/irqflags.h>
-/*
- * clear_bit may not imply a memory barrier
- */
-#include <asm-generic/bitops/atomic.h>
-#include <asm-generic/bitops/non-atomic.h>
-#else
-
-#include <asm/byteorder.h> /* swab32 */
-#include <linux/linkage.h>
-
-asmlinkage int __raw_bit_set_asm(volatile unsigned long *addr, int nr);
-
-asmlinkage int __raw_bit_clear_asm(volatile unsigned long *addr, int nr);
-
-asmlinkage int __raw_bit_toggle_asm(volatile unsigned long *addr, int nr);
-
-asmlinkage int __raw_bit_test_set_asm(volatile unsigned long *addr, int nr);
-
-asmlinkage int __raw_bit_test_clear_asm(volatile unsigned long *addr, int nr);
-
-asmlinkage int __raw_bit_test_toggle_asm(volatile unsigned long *addr, int nr);
-
-asmlinkage int __raw_bit_test_asm(const volatile unsigned long *addr, int nr);
-
-static inline void set_bit(int nr, volatile unsigned long *addr)
-{
- volatile unsigned long *a = addr + (nr >> 5);
- __raw_bit_set_asm(a, nr & 0x1f);
-}
-
-static inline void clear_bit(int nr, volatile unsigned long *addr)
-{
- volatile unsigned long *a = addr + (nr >> 5);
- __raw_bit_clear_asm(a, nr & 0x1f);
-}
-
-static inline void change_bit(int nr, volatile unsigned long *addr)
-{
- volatile unsigned long *a = addr + (nr >> 5);
- __raw_bit_toggle_asm(a, nr & 0x1f);
-}
-
-static inline int test_bit(int nr, const volatile unsigned long *addr)
-{
- volatile const unsigned long *a = addr + (nr >> 5);
- return __raw_bit_test_asm(a, nr & 0x1f) != 0;
-}
-
-static inline int test_and_set_bit(int nr, volatile unsigned long *addr)
-{
- volatile unsigned long *a = addr + (nr >> 5);
- return __raw_bit_test_set_asm(a, nr & 0x1f);
-}
-
-static inline int test_and_clear_bit(int nr, volatile unsigned long *addr)
-{
- volatile unsigned long *a = addr + (nr >> 5);
- return __raw_bit_test_clear_asm(a, nr & 0x1f);
-}
-
-static inline int test_and_change_bit(int nr, volatile unsigned long *addr)
-{
- volatile unsigned long *a = addr + (nr >> 5);
- return __raw_bit_test_toggle_asm(a, nr & 0x1f);
-}
-
-#define test_bit __skip_test_bit
-#include <asm-generic/bitops/non-atomic.h>
-#undef test_bit
-
-#endif /* CONFIG_SMP */
-
-/* Needs to be after test_bit and friends */
-#include <asm-generic/bitops/le.h>
-
-/*
- * hweightN: returns the hamming weight (i.e. the number
- * of bits set) of a N-bit word
- */
-
-static inline unsigned int __arch_hweight32(unsigned int w)
-{
- unsigned int res;
-
- __asm__ ("%0.l = ONES %1;"
- "%0 = %0.l (Z);"
- : "=d" (res) : "d" (w));
- return res;
-}
-
-static inline unsigned int __arch_hweight64(__u64 w)
-{
- return __arch_hweight32((unsigned int)(w >> 32)) +
- __arch_hweight32((unsigned int)w);
-}
-
-static inline unsigned int __arch_hweight16(unsigned int w)
-{
- return __arch_hweight32(w & 0xffff);
-}
-
-static inline unsigned int __arch_hweight8(unsigned int w)
-{
- return __arch_hweight32(w & 0xff);
-}
-
-#endif /* _BLACKFIN_BITOPS_H */
+++ /dev/null
-/*
- * Common header file for Blackfin family of processors.
- *
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BLACKFIN_H_
-#define _BLACKFIN_H_
-
-#include <mach/anomaly.h>
-
-#ifndef __ASSEMBLY__
-
-/* SSYNC implementation for C file */
-static inline void SSYNC(void)
-{
- int _tmp;
- if (ANOMALY_05000312 || ANOMALY_05000244)
- __asm__ __volatile__(
- "cli %0;"
- "nop;"
- "nop;"
- "nop;"
- "ssync;"
- "sti %0;"
- : "=d" (_tmp)
- );
- else
- __asm__ __volatile__("ssync;");
-}
-
-/* CSYNC implementation for C file */
-static inline void CSYNC(void)
-{
- int _tmp;
- if (ANOMALY_05000312 || ANOMALY_05000244)
- __asm__ __volatile__(
- "cli %0;"
- "nop;"
- "nop;"
- "nop;"
- "csync;"
- "sti %0;"
- : "=d" (_tmp)
- );
- else
- __asm__ __volatile__("csync;");
-}
-
-#else /* __ASSEMBLY__ */
-
-#define LO(con32) ((con32) & 0xFFFF)
-#define lo(con32) ((con32) & 0xFFFF)
-#define HI(con32) (((con32) >> 16) & 0xFFFF)
-#define hi(con32) (((con32) >> 16) & 0xFFFF)
-
-/* SSYNC & CSYNC implementations for assembly files */
-
-#define ssync(x) SSYNC(x)
-#define csync(x) CSYNC(x)
-
-#if ANOMALY_05000312 || ANOMALY_05000244
-#define SSYNC(scratch) \
- cli scratch; \
- nop; nop; nop; \
- SSYNC; \
- sti scratch;
-
-#define CSYNC(scratch) \
- cli scratch; \
- nop; nop; nop; \
- CSYNC; \
- sti scratch;
-
-#else
-#define SSYNC(scratch) SSYNC;
-#define CSYNC(scratch) CSYNC;
-#endif /* ANOMALY_05000312 & ANOMALY_05000244 handling */
-
-#endif /* __ASSEMBLY__ */
-
-#include <asm/mem_map.h>
-#include <mach/blackfin.h>
-#include <asm/bfin-global.h>
-
-#endif /* _BLACKFIN_H_ */
+++ /dev/null
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BLACKFIN_BUG_H
-#define _BLACKFIN_BUG_H
-
-#ifdef CONFIG_BUG
-
-/*
- * This can be any undefined 16-bit opcode, meaning
- * ((opcode & 0xc000) != 0xc000)
- * Anything from 0x0001 to 0x000A (inclusive) will work
- */
-#define BFIN_BUG_OPCODE 0x0001
-
-#ifdef CONFIG_DEBUG_BUGVERBOSE
-
-#define _BUG_OR_WARN(flags) \
- asm volatile( \
- "1: .hword %0\n" \
- " .section __bug_table,\"aw\",@progbits\n" \
- "2: .long 1b\n" \
- " .long %1\n" \
- " .short %2\n" \
- " .short %3\n" \
- " .org 2b + %4\n" \
- " .previous" \
- : \
- : "i"(BFIN_BUG_OPCODE), "i"(__FILE__), \
- "i"(__LINE__), "i"(flags), \
- "i"(sizeof(struct bug_entry)))
-
-#else
-
-#define _BUG_OR_WARN(flags) \
- asm volatile( \
- "1: .hword %0\n" \
- " .section __bug_table,\"aw\",@progbits\n" \
- "2: .long 1b\n" \
- " .short %1\n" \
- " .org 2b + %2\n" \
- " .previous" \
- : \
- : "i"(BFIN_BUG_OPCODE), "i"(flags), \
- "i"(sizeof(struct bug_entry)))
-
-#endif /* CONFIG_DEBUG_BUGVERBOSE */
-
-#define BUG() \
- do { \
- _BUG_OR_WARN(0); \
- unreachable(); \
- } while (0)
-
-#define WARN_ON(condition) \
- ({ \
- int __ret_warn_on = !!(condition); \
- if (unlikely(__ret_warn_on)) \
- _BUG_OR_WARN(BUGFLAG_WARNING); \
- unlikely(__ret_warn_on); \
- })
-
-#define HAVE_ARCH_BUG
-#define HAVE_ARCH_WARN_ON
-
-#endif
-
-#include <asm-generic/bug.h>
-
-#endif
+++ /dev/null
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ARCH_BLACKFIN_CACHE_H
-#define __ARCH_BLACKFIN_CACHE_H
-
-#include <linux/linkage.h> /* for asmlinkage */
-
-/*
- * Bytes per L1 cache line
- * Blackfin loads 32 bytes for cache
- */
-#define L1_CACHE_SHIFT 5
-#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
-#define SMP_CACHE_BYTES L1_CACHE_BYTES
-
-#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
-
-#ifdef CONFIG_SMP
-#define __cacheline_aligned
-#else
-#define ____cacheline_aligned
-
-/*
- * Put cacheline_aliged data to L1 data memory
- */
-#ifdef CONFIG_CACHELINE_ALIGNED_L1
-#define __cacheline_aligned \
- __attribute__((__aligned__(L1_CACHE_BYTES), \
- __section__(".data_l1.cacheline_aligned")))
-#endif
-
-#endif
-
-/*
- * largest L1 which this arch supports
- */
-#define L1_CACHE_SHIFT_MAX 5
-
-#if defined(CONFIG_SMP) && \
- !defined(CONFIG_BFIN_CACHE_COHERENT)
-# if defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) || defined(CONFIG_BFIN_L2_ICACHEABLE)
-# define __ARCH_SYNC_CORE_ICACHE
-# endif
-# if defined(CONFIG_BFIN_EXTMEM_DCACHEABLE) || defined(CONFIG_BFIN_L2_DCACHEABLE)
-# define __ARCH_SYNC_CORE_DCACHE
-# endif
-#ifndef __ASSEMBLY__
-asmlinkage void __raw_smp_mark_barrier_asm(void);
-asmlinkage void __raw_smp_check_barrier_asm(void);
-
-static inline void smp_mark_barrier(void)
-{
- __raw_smp_mark_barrier_asm();
-}
-static inline void smp_check_barrier(void)
-{
- __raw_smp_check_barrier_asm();
-}
-
-void resync_core_dcache(void);
-void resync_core_icache(void);
-#endif
-#endif
-
-
-#endif
+++ /dev/null
-/*
- * Blackfin low-level cache routines
- *
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BLACKFIN_CACHEFLUSH_H
-#define _BLACKFIN_CACHEFLUSH_H
-
-#include <asm/blackfin.h> /* for SSYNC() */
-#include <asm/sections.h> /* for _ramend */
-#ifdef CONFIG_SMP
-#include <asm/smp.h>
-#endif
-
-extern void blackfin_icache_flush_range(unsigned long start_address, unsigned long end_address);
-extern void blackfin_dcache_flush_range(unsigned long start_address, unsigned long end_address);
-extern void blackfin_dcache_invalidate_range(unsigned long start_address, unsigned long end_address);
-extern void blackfin_dflush_page(void *page);
-extern void blackfin_invalidate_entire_dcache(void);
-extern void blackfin_invalidate_entire_icache(void);
-
-#define flush_dcache_mmap_lock(mapping) do { } while (0)
-#define flush_dcache_mmap_unlock(mapping) do { } while (0)
-#define flush_cache_mm(mm) do { } while (0)
-#define flush_cache_range(vma, start, end) do { } while (0)
-#define flush_cache_page(vma, vmaddr) do { } while (0)
-#define flush_cache_vmap(start, end) do { } while (0)
-#define flush_cache_vunmap(start, end) do { } while (0)
-
-#ifdef CONFIG_SMP
-#define flush_icache_range_others(start, end) \
- smp_icache_flush_range_others((start), (end))
-#else
-#define flush_icache_range_others(start, end) do { } while (0)
-#endif
-
-static inline void flush_icache_range(unsigned start, unsigned end)
-{
-#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK)
- if (end <= physical_mem_end)
- blackfin_dcache_flush_range(start, end);
-#endif
-#if defined(CONFIG_BFIN_L2_WRITEBACK)
- if (start >= L2_START && end <= L2_START + L2_LENGTH)
- blackfin_dcache_flush_range(start, end);
-#endif
-
- /* Make sure all write buffers in the data side of the core
- * are flushed before trying to invalidate the icache. This
- * needs to be after the data flush and before the icache
- * flush so that the SSYNC does the right thing in preventing
- * the instruction prefetcher from hitting things in cached
- * memory at the wrong time -- it runs much further ahead than
- * the pipeline.
- */
- SSYNC();
-#if defined(CONFIG_BFIN_EXTMEM_ICACHEABLE)
- if (end <= physical_mem_end) {
- blackfin_icache_flush_range(start, end);
- flush_icache_range_others(start, end);
- }
-#endif
-#if defined(CONFIG_BFIN_L2_ICACHEABLE)
- if (start >= L2_START && end <= L2_START + L2_LENGTH) {
- blackfin_icache_flush_range(start, end);
- flush_icache_range_others(start, end);
- }
-#endif
-}
-
-#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
-do { memcpy(dst, src, len); \
- flush_icache_range((unsigned) (dst), (unsigned) (dst) + (len)); \
-} while (0)
-
-#define copy_from_user_page(vma, page, vaddr, dst, src, len) memcpy(dst, src, len)
-
-#if defined(CONFIG_BFIN_DCACHE)
-# define invalidate_dcache_range(start,end) blackfin_dcache_invalidate_range((start), (end))
-#else
-# define invalidate_dcache_range(start,end) do { } while (0)
-#endif
-#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
-# define flush_dcache_range(start,end) blackfin_dcache_flush_range((start), (end))
-#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
-# define flush_dcache_page(page) blackfin_dflush_page(page_address(page))
-#else
-# define flush_dcache_range(start,end) do { } while (0)
-#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
-# define flush_dcache_page(page) do { } while (0)
-#endif
-
-extern unsigned long reserved_mem_dcache_on;
-extern unsigned long reserved_mem_icache_on;
-
-static inline int bfin_addr_dcacheable(unsigned long addr)
-{
-#ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE
- if (addr < (_ramend - DMA_UNCACHED_REGION))
- return 1;
-#endif
-
- if (reserved_mem_dcache_on &&
- addr >= _ramend && addr < physical_mem_end)
- return 1;
-
-#ifdef CONFIG_BFIN_L2_DCACHEABLE
- if (addr >= L2_START && addr < L2_START + L2_LENGTH)
- return 1;
-#endif
-
- return 0;
-}
-
-#endif /* _BLACKFIN_ICACHEFLUSH_H */
+++ /dev/null
-/*
- * Copyright 2005-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CDEF_LPBLACKFIN_H
-#define _CDEF_LPBLACKFIN_H
-
-/*#if !defined(__ADSPLPBLACKFIN__)
-#warning cdef_LPBlackfin.h should only be included for 532 compatible chips.
-#endif
-*/
-#include <asm/def_LPBlackfin.h>
-
-/*Cache & SRAM Memory*/
-#define bfin_read_SRAM_BASE_ADDRESS() bfin_read32(SRAM_BASE_ADDRESS)
-#define bfin_write_SRAM_BASE_ADDRESS(val) bfin_write32(SRAM_BASE_ADDRESS,val)
-#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL)
-#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL,val)
-#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS)
-#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS,val)
-#define bfin_read_DCPLB_FAULT_ADDR() bfin_read32(DCPLB_FAULT_ADDR)
-#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_write32(DCPLB_FAULT_ADDR,val)
-/*
-#define MMR_TIMEOUT 0xFFE00010
-*/
-#define bfin_read_DCPLB_ADDR0() bfin_read32(DCPLB_ADDR0)
-#define bfin_write_DCPLB_ADDR0(val) bfin_write32(DCPLB_ADDR0,val)
-#define bfin_read_DCPLB_ADDR1() bfin_read32(DCPLB_ADDR1)
-#define bfin_write_DCPLB_ADDR1(val) bfin_write32(DCPLB_ADDR1,val)
-#define bfin_read_DCPLB_ADDR2() bfin_read32(DCPLB_ADDR2)
-#define bfin_write_DCPLB_ADDR2(val) bfin_write32(DCPLB_ADDR2,val)
-#define bfin_read_DCPLB_ADDR3() bfin_read32(DCPLB_ADDR3)
-#define bfin_write_DCPLB_ADDR3(val) bfin_write32(DCPLB_ADDR3,val)
-#define bfin_read_DCPLB_ADDR4() bfin_read32(DCPLB_ADDR4)
-#define bfin_write_DCPLB_ADDR4(val) bfin_write32(DCPLB_ADDR4,val)
-#define bfin_read_DCPLB_ADDR5() bfin_read32(DCPLB_ADDR5)
-#define bfin_write_DCPLB_ADDR5(val) bfin_write32(DCPLB_ADDR5,val)
-#define bfin_read_DCPLB_ADDR6() bfin_read32(DCPLB_ADDR6)
-#define bfin_write_DCPLB_ADDR6(val) bfin_write32(DCPLB_ADDR6,val)
-#define bfin_read_DCPLB_ADDR7() bfin_read32(DCPLB_ADDR7)
-#define bfin_write_DCPLB_ADDR7(val) bfin_write32(DCPLB_ADDR7,val)
-#define bfin_read_DCPLB_ADDR8() bfin_read32(DCPLB_ADDR8)
-#define bfin_write_DCPLB_ADDR8(val) bfin_write32(DCPLB_ADDR8,val)
-#define bfin_read_DCPLB_ADDR9() bfin_read32(DCPLB_ADDR9)
-#define bfin_write_DCPLB_ADDR9(val) bfin_write32(DCPLB_ADDR9,val)
-#define bfin_read_DCPLB_ADDR10() bfin_read32(DCPLB_ADDR10)
-#define bfin_write_DCPLB_ADDR10(val) bfin_write32(DCPLB_ADDR10,val)
-#define bfin_read_DCPLB_ADDR11() bfin_read32(DCPLB_ADDR11)
-#define bfin_write_DCPLB_ADDR11(val) bfin_write32(DCPLB_ADDR11,val)
-#define bfin_read_DCPLB_ADDR12() bfin_read32(DCPLB_ADDR12)
-#define bfin_write_DCPLB_ADDR12(val) bfin_write32(DCPLB_ADDR12,val)
-#define bfin_read_DCPLB_ADDR13() bfin_read32(DCPLB_ADDR13)
-#define bfin_write_DCPLB_ADDR13(val) bfin_write32(DCPLB_ADDR13,val)
-#define bfin_read_DCPLB_ADDR14() bfin_read32(DCPLB_ADDR14)
-#define bfin_write_DCPLB_ADDR14(val) bfin_write32(DCPLB_ADDR14,val)
-#define bfin_read_DCPLB_ADDR15() bfin_read32(DCPLB_ADDR15)
-#define bfin_write_DCPLB_ADDR15(val) bfin_write32(DCPLB_ADDR15,val)
-#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0)
-#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0,val)
-#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1)
-#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1,val)
-#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2)
-#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2,val)
-#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3)
-#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3,val)
-#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4)
-#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4,val)
-#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5)
-#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5,val)
-#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6)
-#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6,val)
-#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7)
-#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7,val)
-#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8)
-#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8,val)
-#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9)
-#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9,val)
-#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10)
-#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10,val)
-#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11)
-#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11,val)
-#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12)
-#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12,val)
-#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13)
-#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13,val)
-#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14)
-#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14,val)
-#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15)
-#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15,val)
-#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND)
-#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND,val)
-/*
-#define DTEST_INDEX 0xFFE00304
-*/
-#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0)
-#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0,val)
-#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1)
-#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1,val)
-/*
-#define DTEST_DATA2 0xFFE00408
-#define DTEST_DATA3 0xFFE0040C
-*/
-#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL)
-#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL,val)
-#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS)
-#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS,val)
-#define bfin_read_ICPLB_FAULT_ADDR() bfin_read32(ICPLB_FAULT_ADDR)
-#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_write32(ICPLB_FAULT_ADDR,val)
-#define bfin_read_ICPLB_ADDR0() bfin_read32(ICPLB_ADDR0)
-#define bfin_write_ICPLB_ADDR0(val) bfin_write32(ICPLB_ADDR0,val)
-#define bfin_read_ICPLB_ADDR1() bfin_read32(ICPLB_ADDR1)
-#define bfin_write_ICPLB_ADDR1(val) bfin_write32(ICPLB_ADDR1,val)
-#define bfin_read_ICPLB_ADDR2() bfin_read32(ICPLB_ADDR2)
-#define bfin_write_ICPLB_ADDR2(val) bfin_write32(ICPLB_ADDR2,val)
-#define bfin_read_ICPLB_ADDR3() bfin_read32(ICPLB_ADDR3)
-#define bfin_write_ICPLB_ADDR3(val) bfin_write32(ICPLB_ADDR3,val)
-#define bfin_read_ICPLB_ADDR4() bfin_read32(ICPLB_ADDR4)
-#define bfin_write_ICPLB_ADDR4(val) bfin_write32(ICPLB_ADDR4,val)
-#define bfin_read_ICPLB_ADDR5() bfin_read32(ICPLB_ADDR5)
-#define bfin_write_ICPLB_ADDR5(val) bfin_write32(ICPLB_ADDR5,val)
-#define bfin_read_ICPLB_ADDR6() bfin_read32(ICPLB_ADDR6)
-#define bfin_write_ICPLB_ADDR6(val) bfin_write32(ICPLB_ADDR6,val)
-#define bfin_read_ICPLB_ADDR7() bfin_read32(ICPLB_ADDR7)
-#define bfin_write_ICPLB_ADDR7(val) bfin_write32(ICPLB_ADDR7,val)
-#define bfin_read_ICPLB_ADDR8() bfin_read32(ICPLB_ADDR8)
-#define bfin_write_ICPLB_ADDR8(val) bfin_write32(ICPLB_ADDR8,val)
-#define bfin_read_ICPLB_ADDR9() bfin_read32(ICPLB_ADDR9)
-#define bfin_write_ICPLB_ADDR9(val) bfin_write32(ICPLB_ADDR9,val)
-#define bfin_read_ICPLB_ADDR10() bfin_read32(ICPLB_ADDR10)
-#define bfin_write_ICPLB_ADDR10(val) bfin_write32(ICPLB_ADDR10,val)
-#define bfin_read_ICPLB_ADDR11() bfin_read32(ICPLB_ADDR11)
-#define bfin_write_ICPLB_ADDR11(val) bfin_write32(ICPLB_ADDR11,val)
-#define bfin_read_ICPLB_ADDR12() bfin_read32(ICPLB_ADDR12)
-#define bfin_write_ICPLB_ADDR12(val) bfin_write32(ICPLB_ADDR12,val)
-#define bfin_read_ICPLB_ADDR13() bfin_read32(ICPLB_ADDR13)
-#define bfin_write_ICPLB_ADDR13(val) bfin_write32(ICPLB_ADDR13,val)
-#define bfin_read_ICPLB_ADDR14() bfin_read32(ICPLB_ADDR14)
-#define bfin_write_ICPLB_ADDR14(val) bfin_write32(ICPLB_ADDR14,val)
-#define bfin_read_ICPLB_ADDR15() bfin_read32(ICPLB_ADDR15)
-#define bfin_write_ICPLB_ADDR15(val) bfin_write32(ICPLB_ADDR15,val)
-#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0)
-#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0,val)
-#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1)
-#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1,val)
-#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2)
-#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2,val)
-#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3)
-#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3,val)
-#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4)
-#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4,val)
-#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5)
-#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5,val)
-#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6)
-#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6,val)
-#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7)
-#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7,val)
-#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8)
-#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8,val)
-#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9)
-#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9,val)
-#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10)
-#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10,val)
-#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11)
-#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11,val)
-#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12)
-#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12,val)
-#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13)
-#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13,val)
-#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14)
-#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14,val)
-#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15)
-#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15,val)
-#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND,val)
-#if 0
-#define ITEST_INDEX 0xFFE01304 /* Instruction Test Index Register */
-#endif
-#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0,val)
-#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1,val)
-
-#if !ANOMALY_05000481
-#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND)
-#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0)
-#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1)
-#endif
-
-/* Event/Interrupt Registers*/
-
-#define bfin_read_EVT0() bfin_read32(EVT0)
-#define bfin_write_EVT0(val) bfin_write32(EVT0,val)
-#define bfin_read_EVT1() bfin_read32(EVT1)
-#define bfin_write_EVT1(val) bfin_write32(EVT1,val)
-#define bfin_read_EVT2() bfin_read32(EVT2)
-#define bfin_write_EVT2(val) bfin_write32(EVT2,val)
-#define bfin_read_EVT3() bfin_read32(EVT3)
-#define bfin_write_EVT3(val) bfin_write32(EVT3,val)
-#define bfin_read_EVT4() bfin_read32(EVT4)
-#define bfin_write_EVT4(val) bfin_write32(EVT4,val)
-#define bfin_read_EVT5() bfin_read32(EVT5)
-#define bfin_write_EVT5(val) bfin_write32(EVT5,val)
-#define bfin_read_EVT6() bfin_read32(EVT6)
-#define bfin_write_EVT6(val) bfin_write32(EVT6,val)
-#define bfin_read_EVT7() bfin_read32(EVT7)
-#define bfin_write_EVT7(val) bfin_write32(EVT7,val)
-#define bfin_read_EVT8() bfin_read32(EVT8)
-#define bfin_write_EVT8(val) bfin_write32(EVT8,val)
-#define bfin_read_EVT9() bfin_read32(EVT9)
-#define bfin_write_EVT9(val) bfin_write32(EVT9,val)
-#define bfin_read_EVT10() bfin_read32(EVT10)
-#define bfin_write_EVT10(val) bfin_write32(EVT10,val)
-#define bfin_read_EVT11() bfin_read32(EVT11)
-#define bfin_write_EVT11(val) bfin_write32(EVT11,val)
-#define bfin_read_EVT12() bfin_read32(EVT12)
-#define bfin_write_EVT12(val) bfin_write32(EVT12,val)
-#define bfin_read_EVT13() bfin_read32(EVT13)
-#define bfin_write_EVT13(val) bfin_write32(EVT13,val)
-#define bfin_read_EVT14() bfin_read32(EVT14)
-#define bfin_write_EVT14(val) bfin_write32(EVT14,val)
-#define bfin_read_EVT15() bfin_read32(EVT15)
-#define bfin_write_EVT15(val) bfin_write32(EVT15,val)
-#define bfin_read_EVT_OVERRIDE() bfin_read32(EVT_OVERRIDE)
-#define bfin_write_EVT_OVERRIDE(val) bfin_write32(EVT_OVERRIDE,val)
-#define bfin_read_IMASK() bfin_read32(IMASK)
-#define bfin_write_IMASK(val) bfin_write32(IMASK,val)
-#define bfin_read_IPEND() bfin_read32(IPEND)
-#define bfin_write_IPEND(val) bfin_write32(IPEND,val)
-#define bfin_read_ILAT() bfin_read32(ILAT)
-#define bfin_write_ILAT(val) bfin_write32(ILAT,val)
-#define bfin_read_IPRIO() bfin_read32(IPRIO)
-#define bfin_write_IPRIO(val) bfin_write32(IPRIO,val)
-
-/*Core Timer Registers*/
-#define bfin_read_TCNTL() bfin_read32(TCNTL)
-#define bfin_write_TCNTL(val) bfin_write32(TCNTL,val)
-#define bfin_read_TPERIOD() bfin_read32(TPERIOD)
-#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD,val)
-#define bfin_read_TSCALE() bfin_read32(TSCALE)
-#define bfin_write_TSCALE(val) bfin_write32(TSCALE,val)
-#define bfin_read_TCOUNT() bfin_read32(TCOUNT)
-#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT,val)
-
-/*Debug/MP/Emulation Registers*/
-#define bfin_read_DSPID() bfin_read32(DSPID)
-#define bfin_write_DSPID(val) bfin_write32(DSPID,val)
-#define bfin_read_DBGCTL() bfin_read32(DBGCTL)
-#define bfin_write_DBGCTL(val) bfin_write32(DBGCTL,val)
-#define bfin_read_DBGSTAT() bfin_read32(DBGSTAT)
-#define bfin_write_DBGSTAT(val) bfin_write32(DBGSTAT,val)
-#define bfin_read_EMUDAT() bfin_read32(EMUDAT)
-#define bfin_write_EMUDAT(val) bfin_write32(EMUDAT,val)
-
-/*Trace Buffer Registers*/
-#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL)
-#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL,val)
-#define bfin_read_TBUFSTAT() bfin_read32(TBUFSTAT)
-#define bfin_write_TBUFSTAT(val) bfin_write32(TBUFSTAT,val)
-#define bfin_read_TBUF() bfin_read32(TBUF)
-#define bfin_write_TBUF(val) bfin_write32(TBUF,val)
-
-/*Watch Point Control Registers*/
-#define bfin_read_WPIACTL() bfin_read32(WPIACTL)
-#define bfin_write_WPIACTL(val) bfin_write32(WPIACTL,val)
-#define bfin_read_WPIA0() bfin_read32(WPIA0)
-#define bfin_write_WPIA0(val) bfin_write32(WPIA0,val)
-#define bfin_read_WPIA1() bfin_read32(WPIA1)
-#define bfin_write_WPIA1(val) bfin_write32(WPIA1,val)
-#define bfin_read_WPIA2() bfin_read32(WPIA2)
-#define bfin_write_WPIA2(val) bfin_write32(WPIA2,val)
-#define bfin_read_WPIA3() bfin_read32(WPIA3)
-#define bfin_write_WPIA3(val) bfin_write32(WPIA3,val)
-#define bfin_read_WPIA4() bfin_read32(WPIA4)
-#define bfin_write_WPIA4(val) bfin_write32(WPIA4,val)
-#define bfin_read_WPIA5() bfin_read32(WPIA5)
-#define bfin_write_WPIA5(val) bfin_write32(WPIA5,val)
-#define bfin_read_WPIACNT0() bfin_read32(WPIACNT0)
-#define bfin_write_WPIACNT0(val) bfin_write32(WPIACNT0,val)
-#define bfin_read_WPIACNT1() bfin_read32(WPIACNT1)
-#define bfin_write_WPIACNT1(val) bfin_write32(WPIACNT1,val)
-#define bfin_read_WPIACNT2() bfin_read32(WPIACNT2)
-#define bfin_write_WPIACNT2(val) bfin_write32(WPIACNT2,val)
-#define bfin_read_WPIACNT3() bfin_read32(WPIACNT3)
-#define bfin_write_WPIACNT3(val) bfin_write32(WPIACNT3,val)
-#define bfin_read_WPIACNT4() bfin_read32(WPIACNT4)
-#define bfin_write_WPIACNT4(val) bfin_write32(WPIACNT4,val)
-#define bfin_read_WPIACNT5() bfin_read32(WPIACNT5)
-#define bfin_write_WPIACNT5(val) bfin_write32(WPIACNT5,val)
-#define bfin_read_WPDACTL() bfin_read32(WPDACTL)
-#define bfin_write_WPDACTL(val) bfin_write32(WPDACTL,val)
-#define bfin_read_WPDA0() bfin_read32(WPDA0)
-#define bfin_write_WPDA0(val) bfin_write32(WPDA0,val)
-#define bfin_read_WPDA1() bfin_read32(WPDA1)
-#define bfin_write_WPDA1(val) bfin_write32(WPDA1,val)
-#define bfin_read_WPDACNT0() bfin_read32(WPDACNT0)
-#define bfin_write_WPDACNT0(val) bfin_write32(WPDACNT0,val)
-#define bfin_read_WPDACNT1() bfin_read32(WPDACNT1)
-#define bfin_write_WPDACNT1(val) bfin_write32(WPDACNT1,val)
-#define bfin_read_WPSTAT() bfin_read32(WPSTAT)
-#define bfin_write_WPSTAT(val) bfin_write32(WPSTAT,val)
-
-/*Performance Monitor Registers*/
-#define bfin_read_PFCTL() bfin_read32(PFCTL)
-#define bfin_write_PFCTL(val) bfin_write32(PFCTL,val)
-#define bfin_read_PFCNTR0() bfin_read32(PFCNTR0)
-#define bfin_write_PFCNTR0(val) bfin_write32(PFCNTR0,val)
-#define bfin_read_PFCNTR1() bfin_read32(PFCNTR1)
-#define bfin_write_PFCNTR1(val) bfin_write32(PFCNTR1,val)
-
-#endif /* _CDEF_LPBLACKFIN_H */
+++ /dev/null
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * akbar.hussain@lineo.com
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BFIN_CHECKSUM_H
-#define _BFIN_CHECKSUM_H
-
-/*
- * computes the checksum of the TCP/UDP pseudo-header
- * returns a 16-bit checksum, already complemented
- */
-
-static inline __wsum
-__csum_tcpudp_nofold(__be32 saddr, __be32 daddr, __u32 len,
- __u8 proto, __wsum sum)
-{
- unsigned int carry;
-
- __asm__ ("%0 = %0 + %2;\n\t"
- "CC = AC0;\n\t"
- "%1 = CC;\n\t"
- "%0 = %0 + %1;\n\t"
- "%0 = %0 + %3;\n\t"
- "CC = AC0;\n\t"
- "%1 = CC;\n\t"
- "%0 = %0 + %1;\n\t"
- "%0 = %0 + %4;\n\t"
- "CC = AC0;\n\t"
- "%1 = CC;\n\t"
- "%0 = %0 + %1;\n\t"
- : "=d" (sum), "=&d" (carry)
- : "d" (daddr), "d" (saddr), "d" ((len + proto) << 8), "0"(sum)
- : "CC");
-
- return (sum);
-}
-#define csum_tcpudp_nofold __csum_tcpudp_nofold
-
-#include <asm-generic/checksum.h>
-
-#endif
+++ /dev/null
-/*
- * Common Clock definitions for various kernel files
- *
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BFIN_CLOCKS_H
-#define _BFIN_CLOCKS_H
-
-#include <asm/dpmc.h>
-
-#ifdef CONFIG_CCLK_DIV_1
-# define CONFIG_CCLK_ACT_DIV CCLK_DIV1
-# define CONFIG_CCLK_DIV 1
-#endif
-
-#ifdef CONFIG_CCLK_DIV_2
-# define CONFIG_CCLK_ACT_DIV CCLK_DIV2
-# define CONFIG_CCLK_DIV 2
-#endif
-
-#ifdef CONFIG_CCLK_DIV_4
-# define CONFIG_CCLK_ACT_DIV CCLK_DIV4
-# define CONFIG_CCLK_DIV 4
-#endif
-
-#ifdef CONFIG_CCLK_DIV_8
-# define CONFIG_CCLK_ACT_DIV CCLK_DIV8
-# define CONFIG_CCLK_DIV 8
-#endif
-
-#ifndef CONFIG_PLL_BYPASS
-# ifndef CONFIG_CLKIN_HALF
-# define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)
-# else
-# define CONFIG_VCO_HZ ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)/2)
-# endif
-
-# define CONFIG_CCLK_HZ (CONFIG_VCO_HZ/CONFIG_CCLK_DIV)
-# define CONFIG_SCLK_HZ (CONFIG_VCO_HZ/CONFIG_SCLK_DIV)
-
-#else
-# define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ)
-# define CONFIG_CCLK_HZ (CONFIG_CLKIN_HZ)
-# define CONFIG_SCLK_HZ (CONFIG_CLKIN_HZ)
-# define CONFIG_VCO_MULT 0
-#endif
-
-#include <linux/clk.h>
-
-struct clk_ops {
- unsigned long (*get_rate)(struct clk *clk);
- unsigned long (*round_rate)(struct clk *clk, unsigned long rate);
- int (*set_rate)(struct clk *clk, unsigned long rate);
- int (*enable)(struct clk *clk);
- int (*disable)(struct clk *clk);
-};
-
-struct clk {
- struct clk *parent;
- const char *name;
- unsigned long rate;
- spinlock_t lock;
- u32 flags;
- const struct clk_ops *ops;
- void __iomem *reg;
- u32 mask;
- u32 shift;
-};
-
-int clk_init(void);
-#endif
+++ /dev/null
-/*
- * Copyright 2004-2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ARCH_BLACKFIN_CMPXCHG__
-#define __ARCH_BLACKFIN_CMPXCHG__
-
-#ifdef CONFIG_SMP
-
-#include <linux/linkage.h>
-
-asmlinkage unsigned long __raw_xchg_1_asm(volatile void *ptr, unsigned long value);
-asmlinkage unsigned long __raw_xchg_2_asm(volatile void *ptr, unsigned long value);
-asmlinkage unsigned long __raw_xchg_4_asm(volatile void *ptr, unsigned long value);
-asmlinkage unsigned long __raw_cmpxchg_1_asm(volatile void *ptr,
- unsigned long new, unsigned long old);
-asmlinkage unsigned long __raw_cmpxchg_2_asm(volatile void *ptr,
- unsigned long new, unsigned long old);
-asmlinkage unsigned long __raw_cmpxchg_4_asm(volatile void *ptr,
- unsigned long new, unsigned long old);
-
-static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
- int size)
-{
- unsigned long tmp;
-
- switch (size) {
- case 1:
- tmp = __raw_xchg_1_asm(ptr, x);
- break;
- case 2:
- tmp = __raw_xchg_2_asm(ptr, x);
- break;
- case 4:
- tmp = __raw_xchg_4_asm(ptr, x);
- break;
- }
-
- return tmp;
-}
-
-/*
- * Atomic compare and exchange. Compare OLD with MEM, if identical,
- * store NEW in MEM. Return the initial value in MEM. Success is
- * indicated by comparing RETURN with OLD.
- */
-static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
- unsigned long new, int size)
-{
- unsigned long tmp;
-
- switch (size) {
- case 1:
- tmp = __raw_cmpxchg_1_asm(ptr, new, old);
- break;
- case 2:
- tmp = __raw_cmpxchg_2_asm(ptr, new, old);
- break;
- case 4:
- tmp = __raw_cmpxchg_4_asm(ptr, new, old);
- break;
- }
-
- return tmp;
-}
-#define cmpxchg(ptr, o, n) \
- ((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(o), \
- (unsigned long)(n), sizeof(*(ptr))))
-
-#else /* !CONFIG_SMP */
-
-#include <mach/blackfin.h>
-#include <asm/irqflags.h>
-
-struct __xchg_dummy {
- unsigned long a[100];
-};
-#define __xg(x) ((volatile struct __xchg_dummy *)(x))
-
-static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
- int size)
-{
- unsigned long tmp = 0;
- unsigned long flags;
-
- flags = hard_local_irq_save();
-
- switch (size) {
- case 1:
- __asm__ __volatile__
- ("%0 = b%2 (z);\n\t"
- "b%2 = %1;\n\t"
- : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
- break;
- case 2:
- __asm__ __volatile__
- ("%0 = w%2 (z);\n\t"
- "w%2 = %1;\n\t"
- : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
- break;
- case 4:
- __asm__ __volatile__
- ("%0 = %2;\n\t"
- "%2 = %1;\n\t"
- : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
- break;
- }
- hard_local_irq_restore(flags);
- return tmp;
-}
-
-#include <asm-generic/cmpxchg-local.h>
-
-/*
- * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
- * them available.
- */
-#define cmpxchg_local(ptr, o, n) \
- ((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\
- (unsigned long)(n), sizeof(*(ptr))))
-#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
-
-#define cmpxchg(ptr, o, n) cmpxchg_local((ptr), (o), (n))
-#define cmpxchg64(ptr, o, n) cmpxchg64_local((ptr), (o), (n))
-
-#endif /* !CONFIG_SMP */
-
-#define xchg(ptr, x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x), (ptr), sizeof(*(ptr))))
-
-#endif /* __ARCH_BLACKFIN_CMPXCHG__ */
+++ /dev/null
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-/*
- * NOTE! The single-stepping code assumes that all interrupt handlers
- * start by saving SYSCFG on the stack with their first instruction.
- */
-
-/*
- * Code to save processor context.
- * We even save the register which are preserved by a function call
- * - r4, r5, r6, r7, p3, p4, p5
- */
-.macro save_context_with_interrupts
- [--sp] = SYSCFG;
-
- [--sp] = P0; /*orig_p0*/
- [--sp] = R0; /*orig_r0*/
-
- [--sp] = ( R7:0, P5:0 );
- [--sp] = fp;
- [--sp] = usp;
-
- [--sp] = i0;
- [--sp] = i1;
- [--sp] = i2;
- [--sp] = i3;
-
- [--sp] = m0;
- [--sp] = m1;
- [--sp] = m2;
- [--sp] = m3;
-
- [--sp] = l0;
- [--sp] = l1;
- [--sp] = l2;
- [--sp] = l3;
-
- [--sp] = b0;
- [--sp] = b1;
- [--sp] = b2;
- [--sp] = b3;
- [--sp] = a0.x;
- [--sp] = a0.w;
- [--sp] = a1.x;
- [--sp] = a1.w;
-
- [--sp] = LC0;
- [--sp] = LC1;
- [--sp] = LT0;
- [--sp] = LT1;
- [--sp] = LB0;
- [--sp] = LB1;
-
- [--sp] = ASTAT;
-
- [--sp] = r0; /* Skip reserved */
- [--sp] = RETS;
- r0 = RETI;
- [--sp] = r0;
- [--sp] = RETX;
- [--sp] = RETN;
- [--sp] = RETE;
- [--sp] = SEQSTAT;
- [--sp] = r0; /* Skip IPEND as well. */
- /* Switch to other method of keeping interrupts disabled. */
-#ifdef CONFIG_DEBUG_HWERR
- r0 = 0x3f;
- sti r0;
-#else
- cli r0;
-#endif
-#ifdef CONFIG_TRACE_IRQFLAGS
- sp += -12;
- call _trace_hardirqs_off;
- sp += 12;
-#endif
- [--sp] = RETI; /*orig_pc*/
- /* Clear all L registers. */
- r0 = 0 (x);
- l0 = r0;
- l1 = r0;
- l2 = r0;
- l3 = r0;
-.endm
-
-.macro save_context_syscall
- [--sp] = SYSCFG;
-
- [--sp] = P0; /*orig_p0*/
- [--sp] = R0; /*orig_r0*/
- [--sp] = ( R7:0, P5:0 );
- [--sp] = fp;
- [--sp] = usp;
-
- [--sp] = i0;
- [--sp] = i1;
- [--sp] = i2;
- [--sp] = i3;
-
- [--sp] = m0;
- [--sp] = m1;
- [--sp] = m2;
- [--sp] = m3;
-
- [--sp] = l0;
- [--sp] = l1;
- [--sp] = l2;
- [--sp] = l3;
-
- [--sp] = b0;
- [--sp] = b1;
- [--sp] = b2;
- [--sp] = b3;
- [--sp] = a0.x;
- [--sp] = a0.w;
- [--sp] = a1.x;
- [--sp] = a1.w;
-
- [--sp] = LC0;
- [--sp] = LC1;
- [--sp] = LT0;
- [--sp] = LT1;
- [--sp] = LB0;
- [--sp] = LB1;
-
- [--sp] = ASTAT;
-
- [--sp] = r0; /* Skip reserved */
- [--sp] = RETS;
- r0 = RETI;
- [--sp] = r0;
- [--sp] = RETX;
- [--sp] = RETN;
- [--sp] = RETE;
- [--sp] = SEQSTAT;
- [--sp] = r0; /* Skip IPEND as well. */
- [--sp] = RETI; /*orig_pc*/
- /* Clear all L registers. */
- r0 = 0 (x);
- l0 = r0;
- l1 = r0;
- l2 = r0;
- l3 = r0;
-.endm
-
-.macro save_context_no_interrupts
- [--sp] = SYSCFG;
- [--sp] = P0; /* orig_p0 */
- [--sp] = R0; /* orig_r0 */
- [--sp] = ( R7:0, P5:0 );
- [--sp] = fp;
- [--sp] = usp;
-
- [--sp] = i0;
- [--sp] = i1;
- [--sp] = i2;
- [--sp] = i3;
-
- [--sp] = m0;
- [--sp] = m1;
- [--sp] = m2;
- [--sp] = m3;
-
- [--sp] = l0;
- [--sp] = l1;
- [--sp] = l2;
- [--sp] = l3;
-
- [--sp] = b0;
- [--sp] = b1;
- [--sp] = b2;
- [--sp] = b3;
- [--sp] = a0.x;
- [--sp] = a0.w;
- [--sp] = a1.x;
- [--sp] = a1.w;
-
- [--sp] = LC0;
- [--sp] = LC1;
- [--sp] = LT0;
- [--sp] = LT1;
- [--sp] = LB0;
- [--sp] = LB1;
-
- [--sp] = ASTAT;
-
-#ifdef CONFIG_KGDB
- fp = 0(Z);
- r1 = sp;
- r1 += 60;
- r1 += 60;
- r1 += 60;
- [--sp] = r1;
-#else
- [--sp] = r0; /* Skip reserved */
-#endif
- [--sp] = RETS;
- r0 = RETI;
- [--sp] = r0;
- [--sp] = RETX;
- [--sp] = RETN;
- [--sp] = RETE;
- [--sp] = SEQSTAT;
-#ifdef CONFIG_DEBUG_KERNEL
- p1.l = lo(IPEND);
- p1.h = hi(IPEND);
- r1 = [p1];
- [--sp] = r1;
-#else
- [--sp] = r0; /* Skip IPEND as well. */
-#endif
- [--sp] = r0; /*orig_pc*/
- /* Clear all L registers. */
- r0 = 0 (x);
- l0 = r0;
- l1 = r0;
- l2 = r0;
- l3 = r0;
-.endm
-
-.macro restore_context_no_interrupts
- sp += 4; /* Skip orig_pc */
- sp += 4; /* Skip IPEND */
- SEQSTAT = [sp++];
- RETE = [sp++];
- RETN = [sp++];
- RETX = [sp++];
- r0 = [sp++];
- RETI = r0; /* Restore RETI indirectly when in exception */
- RETS = [sp++];
-
- sp += 4; /* Skip Reserved */
-
- ASTAT = [sp++];
-
- LB1 = [sp++];
- LB0 = [sp++];
- LT1 = [sp++];
- LT0 = [sp++];
- LC1 = [sp++];
- LC0 = [sp++];
-
- a1.w = [sp++];
- a1.x = [sp++];
- a0.w = [sp++];
- a0.x = [sp++];
- b3 = [sp++];
- b2 = [sp++];
- b1 = [sp++];
- b0 = [sp++];
-
- l3 = [sp++];
- l2 = [sp++];
- l1 = [sp++];
- l0 = [sp++];
-
- m3 = [sp++];
- m2 = [sp++];
- m1 = [sp++];
- m0 = [sp++];
-
- i3 = [sp++];
- i2 = [sp++];
- i1 = [sp++];
- i0 = [sp++];
-
- sp += 4;
- fp = [sp++];
-
- ( R7 : 0, P5 : 0) = [ SP ++ ];
- sp += 8; /* Skip orig_r0/orig_p0 */
- SYSCFG = [sp++];
-.endm
-
-.macro restore_context_with_interrupts
- sp += 4; /* Skip orig_pc */
- sp += 4; /* Skip IPEND */
- SEQSTAT = [sp++];
- RETE = [sp++];
- RETN = [sp++];
- RETX = [sp++];
- RETI = [sp++];
-
-#ifdef CONFIG_TRACE_IRQFLAGS
- sp += -12;
- call _trace_hardirqs_on;
- sp += 12;
-#endif
-
- RETS = [sp++];
-
-#ifdef CONFIG_SMP
- GET_PDA(p0, r0);
- r0 = [p0 + PDA_IRQFLAGS];
-#else
- p0.h = _bfin_irq_flags;
- p0.l = _bfin_irq_flags;
- r0 = [p0];
-#endif
- sti r0;
-
- sp += 4; /* Skip Reserved */
-
- ASTAT = [sp++];
-
- LB1 = [sp++];
- LB0 = [sp++];
- LT1 = [sp++];
- LT0 = [sp++];
- LC1 = [sp++];
- LC0 = [sp++];
-
- a1.w = [sp++];
- a1.x = [sp++];
- a0.w = [sp++];
- a0.x = [sp++];
- b3 = [sp++];
- b2 = [sp++];
- b1 = [sp++];
- b0 = [sp++];
-
- l3 = [sp++];
- l2 = [sp++];
- l1 = [sp++];
- l0 = [sp++];
-
- m3 = [sp++];
- m2 = [sp++];
- m1 = [sp++];
- m0 = [sp++];
-
- i3 = [sp++];
- i2 = [sp++];
- i1 = [sp++];
- i0 = [sp++];
-
- sp += 4;
- fp = [sp++];
-
- ( R7 : 0, P5 : 0) = [ SP ++ ];
- sp += 8; /* Skip orig_r0/orig_p0 */
- csync;
- SYSCFG = [sp++];
- csync;
-.endm
-
-.macro save_context_cplb
- [--sp] = (R7:0, P5:0);
- [--sp] = fp;
-
- [--sp] = a0.x;
- [--sp] = a0.w;
- [--sp] = a1.x;
- [--sp] = a1.w;
-
- [--sp] = LC0;
- [--sp] = LC1;
- [--sp] = LT0;
- [--sp] = LT1;
- [--sp] = LB0;
- [--sp] = LB1;
-
- [--sp] = RETS;
-.endm
-
-.macro restore_context_cplb
- RETS = [sp++];
-
- LB1 = [sp++];
- LB0 = [sp++];
- LT1 = [sp++];
- LT0 = [sp++];
- LC1 = [sp++];
- LC0 = [sp++];
-
- a1.w = [sp++];
- a1.x = [sp++];
- a0.w = [sp++];
- a0.x = [sp++];
-
- fp = [sp++];
-
- (R7:0, P5:0) = [SP++];
-.endm
-
-.macro pseudo_long_call func:req, scratch:req
-#ifdef CONFIG_ROMKERNEL
- \scratch\().l = \func;
- \scratch\().h = \func;
- call (\scratch);
-#else
- call \func;
-#endif
-.endm
-
-#if defined(CONFIG_BFIN_SCRATCH_REG_RETN)
-# define EX_SCRATCH_REG RETN
-#elif defined(CONFIG_BFIN_SCRATCH_REG_RETE)
-# define EX_SCRATCH_REG RETE
-#else
-# define EX_SCRATCH_REG CYCLES
-#endif
-
+++ /dev/null
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CPLB_H
-#define _CPLB_H
-
-#include <mach/anomaly.h>
-
-#define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)
-#define SDRAM_IKERNEL (SDRAM_IGENERIC | CPLB_LOCK)
-#define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
-#define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID)
-
-#if ANOMALY_05000158
-#define ANOMALY_05000158_WORKAROUND 0x200
-#else
-#define ANOMALY_05000158_WORKAROUND 0x0
-#endif
-
-#define CPLB_COMMON (CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
-
-#ifdef CONFIG_BFIN_EXTMEM_WRITEBACK
-#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_COMMON)
-#elif defined(CONFIG_BFIN_EXTMEM_WRITETHROUGH)
-#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON)
-#else
-#define SDRAM_DGENERIC (CPLB_COMMON)
-#endif
-
-#define SDRAM_DNON_CHBL (CPLB_COMMON)
-#define SDRAM_EBIU (CPLB_COMMON)
-#define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY)
-
-#define L1_DMEMORY (CPLB_LOCK | CPLB_COMMON)
-
-#ifdef CONFIG_SMP
-#define L2_ATTR (INITIAL_T | I_CPLB | D_CPLB)
-#define L2_IMEMORY (CPLB_COMMON | PAGE_SIZE_1MB)
-#define L2_DMEMORY (CPLB_LOCK | CPLB_COMMON | PAGE_SIZE_1MB)
-
-#else
-#define L2_ATTR (INITIAL_T | SWITCH_T | I_CPLB | D_CPLB)
-# if defined(CONFIG_BFIN_L2_ICACHEABLE)
-# define L2_IMEMORY (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | PAGE_SIZE_1MB)
-# else
-# define L2_IMEMORY ( CPLB_USER_RD | CPLB_VALID | PAGE_SIZE_1MB)
-# endif
-
-# if defined(CONFIG_BFIN_L2_WRITEBACK)
-# define L2_DMEMORY (CPLB_L1_CHBL | CPLB_COMMON | PAGE_SIZE_1MB)
-# elif defined(CONFIG_BFIN_L2_WRITETHROUGH)
-# define L2_DMEMORY (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON | PAGE_SIZE_1MB)
-# else
-# define L2_DMEMORY (CPLB_COMMON | PAGE_SIZE_1MB)
-# endif
-#endif /* CONFIG_SMP */
-
-#define SIZE_1K 0x00000400 /* 1K */
-#define SIZE_4K 0x00001000 /* 4K */
-#define SIZE_1M 0x00100000 /* 1M */
-#define SIZE_4M 0x00400000 /* 4M */
-#define SIZE_16K 0x00004000 /* 16K */
-#define SIZE_64K 0x00010000 /* 64K */
-#define SIZE_16M 0x01000000 /* 16M */
-#define SIZE_64M 0x04000000 /* 64M */
-
-#define MAX_CPLBS 16
-
-#define CPLB_ENABLE_ICACHE_P 0
-#define CPLB_ENABLE_DCACHE_P 1
-#define CPLB_ENABLE_DCACHE2_P 2
-#define CPLB_ENABLE_CPLBS_P 3 /* Deprecated! */
-#define CPLB_ENABLE_ICPLBS_P 4
-#define CPLB_ENABLE_DCPLBS_P 5
-
-#define CPLB_ENABLE_ICACHE (1<<CPLB_ENABLE_ICACHE_P)
-#define CPLB_ENABLE_DCACHE (1<<CPLB_ENABLE_DCACHE_P)
-#define CPLB_ENABLE_DCACHE2 (1<<CPLB_ENABLE_DCACHE2_P)
-#define CPLB_ENABLE_CPLBS (1<<CPLB_ENABLE_CPLBS_P)
-#define CPLB_ENABLE_ICPLBS (1<<CPLB_ENABLE_ICPLBS_P)
-#define CPLB_ENABLE_DCPLBS (1<<CPLB_ENABLE_DCPLBS_P)
-#define CPLB_ENABLE_ANY_CPLBS CPLB_ENABLE_CPLBS | \
- CPLB_ENABLE_ICPLBS | \
- CPLB_ENABLE_DCPLBS
-
-#define CPLB_RELOADED 0x0000
-#define CPLB_NO_UNLOCKED 0x0001
-#define CPLB_NO_ADDR_MATCH 0x0002
-#define CPLB_PROT_VIOL 0x0003
-#define CPLB_UNKNOWN_ERR 0x0004
-
-#define CPLB_DEF_CACHE CPLB_L1_CHBL | CPLB_WT
-#define CPLB_CACHE_ENABLED CPLB_L1_CHBL | CPLB_DIRTY
-
-#define CPLB_I_PAGE_MGMT CPLB_LOCK | CPLB_VALID
-#define CPLB_D_PAGE_MGMT CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID
-#define CPLB_DNOCACHE CPLB_ALL_ACCESS | CPLB_VALID
-#define CPLB_DDOCACHE CPLB_DNOCACHE | CPLB_DEF_CACHE
-#define CPLB_INOCACHE CPLB_USER_RD | CPLB_VALID
-#define CPLB_IDOCACHE CPLB_INOCACHE | CPLB_L1_CHBL
-
-#define FAULT_RW (1 << 16)
-#define FAULT_USERSUPV (1 << 17)
-#define FAULT_CPLBBITS 0x0000ffff
-
-#ifndef __ASSEMBLY__
-
-static inline void _disable_cplb(u32 mmr, u32 mask)
-{
- u32 ctrl = bfin_read32(mmr) & ~mask;
- /* CSYNC to ensure load store ordering */
- __builtin_bfin_csync();
- bfin_write32(mmr, ctrl);
- __builtin_bfin_ssync();
-}
-static inline void disable_cplb(u32 mmr, u32 mask)
-{
- u32 ctrl = bfin_read32(mmr) & ~mask;
- CSYNC();
- bfin_write32(mmr, ctrl);
- SSYNC();
-}
-#define _disable_dcplb() _disable_cplb(DMEM_CONTROL, ENDCPLB)
-#define disable_dcplb() disable_cplb(DMEM_CONTROL, ENDCPLB)
-#define _disable_icplb() _disable_cplb(IMEM_CONTROL, ENICPLB)
-#define disable_icplb() disable_cplb(IMEM_CONTROL, ENICPLB)
-
-static inline void _enable_cplb(u32 mmr, u32 mask)
-{
- u32 ctrl = bfin_read32(mmr) | mask;
- /* CSYNC to ensure load store ordering */
- __builtin_bfin_csync();
- bfin_write32(mmr, ctrl);
- __builtin_bfin_ssync();
-}
-static inline void enable_cplb(u32 mmr, u32 mask)
-{
- u32 ctrl = bfin_read32(mmr) | mask;
- CSYNC();
- bfin_write32(mmr, ctrl);
- SSYNC();
-}
-#define _enable_dcplb() _enable_cplb(DMEM_CONTROL, ENDCPLB)
-#define enable_dcplb() enable_cplb(DMEM_CONTROL, ENDCPLB)
-#define _enable_icplb() _enable_cplb(IMEM_CONTROL, ENICPLB)
-#define enable_icplb() enable_cplb(IMEM_CONTROL, ENICPLB)
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* _CPLB_H */
+++ /dev/null
-/*
- * Common CPLB definitions for CPLB init
- *
- * Copyright 2006-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_CPLBINIT_H__
-#define __ASM_CPLBINIT_H__
-
-#include <asm/blackfin.h>
-#include <asm/cplb.h>
-#include <linux/threads.h>
-
-#ifdef CONFIG_CPLB_SWITCH_TAB_L1
-# define PDT_ATTR __attribute__((l1_data))
-#else
-# define PDT_ATTR
-#endif
-
-struct cplb_entry {
- unsigned long data, addr;
-};
-
-struct cplb_boundary {
- unsigned long eaddr; /* End of this region. */
- unsigned long data; /* CPLB data value. */
-};
-
-extern struct cplb_boundary dcplb_bounds[];
-extern struct cplb_boundary icplb_bounds[];
-extern int dcplb_nr_bounds, icplb_nr_bounds;
-
-extern struct cplb_entry dcplb_tbl[NR_CPUS][MAX_CPLBS];
-extern struct cplb_entry icplb_tbl[NR_CPUS][MAX_CPLBS];
-extern int first_switched_icplb;
-extern int first_switched_dcplb;
-
-extern int nr_dcplb_miss[], nr_icplb_miss[], nr_icplb_supv_miss[];
-extern int nr_dcplb_prot[], nr_cplb_flush[];
-
-#ifdef CONFIG_MPU
-
-extern int first_mask_dcplb;
-
-extern int page_mask_order;
-extern int page_mask_nelts;
-
-extern unsigned long *current_rwx_mask[NR_CPUS];
-
-extern void flush_switched_cplbs(unsigned int);
-extern void set_mask_dcplbs(unsigned long *, unsigned int);
-
-extern void __noreturn panic_cplb_error(int seqstat, struct pt_regs *);
-
-#endif /* CONFIG_MPU */
-
-extern void bfin_icache_init(struct cplb_entry *icplb_tbl);
-extern void bfin_dcache_init(struct cplb_entry *icplb_tbl);
-
-#if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE)
-extern void generate_cplb_tables_all(void);
-extern void generate_cplb_tables_cpu(unsigned int cpu);
-#endif
-#endif
+++ /dev/null
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- * Philippe Gerum <rpm@xenomai.org>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_BLACKFIN_CPU_H
-#define __ASM_BLACKFIN_CPU_H
-
-#include <linux/percpu.h>
-
-struct blackfin_cpudata {
- struct cpu cpu;
- unsigned int imemctl;
- unsigned int dmemctl;
-#ifdef CONFIG_SMP
- struct task_struct *idle;
-#endif
-};
-
-DECLARE_PER_CPU(struct blackfin_cpudata, cpu_data);
-
-#endif
+++ /dev/null
-/*
- * Blackfin core register bit & address definitions
- *
- * Copyright 2005-2008 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or GPL-2 (or later).
- */
-
-#ifndef _DEF_LPBLACKFIN_H
-#define _DEF_LPBLACKFIN_H
-
-#include <mach/anomaly.h>
-
-#define MK_BMSK_(x) (1<<x)
-#define BFIN_DEPOSIT(mask, x) (((x) << __ffs(mask)) & (mask))
-#define BFIN_EXTRACT(mask, x) (((x) & (mask)) >> __ffs(mask))
-
-#ifndef __ASSEMBLY__
-
-#include <linux/types.h>
-
-#if ANOMALY_05000198
-# define NOP_PAD_ANOMALY_05000198 "nop;"
-#else
-# define NOP_PAD_ANOMALY_05000198
-#endif
-
-#define _bfin_readX(addr, size, asm_size, asm_ext) ({ \
- u32 __v; \
- __asm__ __volatile__( \
- NOP_PAD_ANOMALY_05000198 \
- "%0 = " #asm_size "[%1]" #asm_ext ";" \
- : "=d" (__v) \
- : "a" (addr) \
- ); \
- __v; })
-#define _bfin_writeX(addr, val, size, asm_size) \
- __asm__ __volatile__( \
- NOP_PAD_ANOMALY_05000198 \
- #asm_size "[%0] = %1;" \
- : \
- : "a" (addr), "d" ((u##size)(val)) \
- : "memory" \
- )
-
-#define bfin_read8(addr) _bfin_readX(addr, 8, b, (z))
-#define bfin_read16(addr) _bfin_readX(addr, 16, w, (z))
-#define bfin_read32(addr) _bfin_readX(addr, 32, , )
-#define bfin_write8(addr, val) _bfin_writeX(addr, val, 8, b)
-#define bfin_write16(addr, val) _bfin_writeX(addr, val, 16, w)
-#define bfin_write32(addr, val) _bfin_writeX(addr, val, 32, )
-
-#define bfin_read(addr) \
-({ \
- sizeof(*(addr)) == 1 ? bfin_read8(addr) : \
- sizeof(*(addr)) == 2 ? bfin_read16(addr) : \
- sizeof(*(addr)) == 4 ? bfin_read32(addr) : \
- ({ BUG(); 0; }); \
-})
-#define bfin_write(addr, val) \
-do { \
- switch (sizeof(*(addr))) { \
- case 1: bfin_write8(addr, val); break; \
- case 2: bfin_write16(addr, val); break; \
- case 4: bfin_write32(addr, val); break; \
- default: BUG(); \
- } \
-} while (0)
-
-#define bfin_write_or(addr, bits) \
-do { \
- typeof(addr) __addr = (addr); \
- bfin_write(__addr, bfin_read(__addr) | (bits)); \
-} while (0)
-
-#define bfin_write_and(addr, bits) \
-do { \
- typeof(addr) __addr = (addr); \
- bfin_write(__addr, bfin_read(__addr) & (bits)); \
-} while (0)
-
-#endif /* __ASSEMBLY__ */
-
-/**************************************************
- * System Register Bits
- **************************************************/
-
-/**************************************************
- * ASTAT register
- **************************************************/
-
-/* definitions of ASTAT bit positions*/
-
-/*Result of last ALU0 or shifter operation is zero*/
-#define ASTAT_AZ_P 0x00000000
-/*Result of last ALU0 or shifter operation is negative*/
-#define ASTAT_AN_P 0x00000001
-/*Condition Code, used for holding comparison results*/
-#define ASTAT_CC_P 0x00000005
-/*Quotient Bit*/
-#define ASTAT_AQ_P 0x00000006
-/*Rounding mode, set for biased, clear for unbiased*/
-#define ASTAT_RND_MOD_P 0x00000008
-/*Result of last ALU0 operation generated a carry*/
-#define ASTAT_AC0_P 0x0000000C
-/*Result of last ALU0 operation generated a carry*/
-#define ASTAT_AC0_COPY_P 0x00000002
-/*Result of last ALU1 operation generated a carry*/
-#define ASTAT_AC1_P 0x0000000D
-/*Result of last ALU0 or MAC0 operation overflowed, sticky for MAC*/
-#define ASTAT_AV0_P 0x00000010
-/*Sticky version of ASTAT_AV0 */
-#define ASTAT_AV0S_P 0x00000011
-/*Result of last MAC1 operation overflowed, sticky for MAC*/
-#define ASTAT_AV1_P 0x00000012
-/*Sticky version of ASTAT_AV1 */
-#define ASTAT_AV1S_P 0x00000013
-/*Result of last ALU0 or MAC0 operation overflowed*/
-#define ASTAT_V_P 0x00000018
-/*Result of last ALU0 or MAC0 operation overflowed*/
-#define ASTAT_V_COPY_P 0x00000003
-/*Sticky version of ASTAT_V*/
-#define ASTAT_VS_P 0x00000019
-
-/* Masks */
-
-/*Result of last ALU0 or shifter operation is zero*/
-#define ASTAT_AZ MK_BMSK_(ASTAT_AZ_P)
-/*Result of last ALU0 or shifter operation is negative*/
-#define ASTAT_AN MK_BMSK_(ASTAT_AN_P)
-/*Result of last ALU0 operation generated a carry*/
-#define ASTAT_AC0 MK_BMSK_(ASTAT_AC0_P)
-/*Result of last ALU0 operation generated a carry*/
-#define ASTAT_AC0_COPY MK_BMSK_(ASTAT_AC0_COPY_P)
-/*Result of last ALU0 operation generated a carry*/
-#define ASTAT_AC1 MK_BMSK_(ASTAT_AC1_P)
-/*Result of last ALU0 or MAC0 operation overflowed, sticky for MAC*/
-#define ASTAT_AV0 MK_BMSK_(ASTAT_AV0_P)
-/*Result of last MAC1 operation overflowed, sticky for MAC*/
-#define ASTAT_AV1 MK_BMSK_(ASTAT_AV1_P)
-/*Condition Code, used for holding comparison results*/
-#define ASTAT_CC MK_BMSK_(ASTAT_CC_P)
-/*Quotient Bit*/
-#define ASTAT_AQ MK_BMSK_(ASTAT_AQ_P)
-/*Rounding mode, set for biased, clear for unbiased*/
-#define ASTAT_RND_MOD MK_BMSK_(ASTAT_RND_MOD_P)
-/*Overflow Bit*/
-#define ASTAT_V MK_BMSK_(ASTAT_V_P)
-/*Overflow Bit*/
-#define ASTAT_V_COPY MK_BMSK_(ASTAT_V_COPY_P)
-
-/**************************************************
- * SEQSTAT register
- **************************************************/
-
-/* Bit Positions */
-#define SEQSTAT_EXCAUSE0_P 0x00000000 /* Last exception cause bit 0 */
-#define SEQSTAT_EXCAUSE1_P 0x00000001 /* Last exception cause bit 1 */
-#define SEQSTAT_EXCAUSE2_P 0x00000002 /* Last exception cause bit 2 */
-#define SEQSTAT_EXCAUSE3_P 0x00000003 /* Last exception cause bit 3 */
-#define SEQSTAT_EXCAUSE4_P 0x00000004 /* Last exception cause bit 4 */
-#define SEQSTAT_EXCAUSE5_P 0x00000005 /* Last exception cause bit 5 */
-#define SEQSTAT_IDLE_REQ_P 0x0000000C /* Pending idle mode request,
- * set by IDLE instruction.
- */
-#define SEQSTAT_SFTRESET_P 0x0000000D /* Indicates whether the last
- * reset was a software reset
- * (=1)
- */
-#define SEQSTAT_HWERRCAUSE0_P 0x0000000E /* Last hw error cause bit 0 */
-#define SEQSTAT_HWERRCAUSE1_P 0x0000000F /* Last hw error cause bit 1 */
-#define SEQSTAT_HWERRCAUSE2_P 0x00000010 /* Last hw error cause bit 2 */
-#define SEQSTAT_HWERRCAUSE3_P 0x00000011 /* Last hw error cause bit 3 */
-#define SEQSTAT_HWERRCAUSE4_P 0x00000012 /* Last hw error cause bit 4 */
-/* Masks */
-/* Exception cause */
-#define SEQSTAT_EXCAUSE (MK_BMSK_(SEQSTAT_EXCAUSE0_P) | \
- MK_BMSK_(SEQSTAT_EXCAUSE1_P) | \
- MK_BMSK_(SEQSTAT_EXCAUSE2_P) | \
- MK_BMSK_(SEQSTAT_EXCAUSE3_P) | \
- MK_BMSK_(SEQSTAT_EXCAUSE4_P) | \
- MK_BMSK_(SEQSTAT_EXCAUSE5_P) | \
- 0)
-
-/* Indicates whether the last reset was a software reset (=1) */
-#define SEQSTAT_SFTRESET (MK_BMSK_(SEQSTAT_SFTRESET_P))
-
-/* Last hw error cause */
-#define SEQSTAT_HWERRCAUSE (MK_BMSK_(SEQSTAT_HWERRCAUSE0_P) | \
- MK_BMSK_(SEQSTAT_HWERRCAUSE1_P) | \
- MK_BMSK_(SEQSTAT_HWERRCAUSE2_P) | \
- MK_BMSK_(SEQSTAT_HWERRCAUSE3_P) | \
- MK_BMSK_(SEQSTAT_HWERRCAUSE4_P) | \
- 0)
-
-/* Translate bits to something useful */
-
-/* Last hw error cause */
-#define SEQSTAT_HWERRCAUSE_SHIFT (14)
-#define SEQSTAT_HWERRCAUSE_SYSTEM_MMR (0x02 << SEQSTAT_HWERRCAUSE_SHIFT)
-#define SEQSTAT_HWERRCAUSE_EXTERN_ADDR (0x03 << SEQSTAT_HWERRCAUSE_SHIFT)
-#define SEQSTAT_HWERRCAUSE_PERF_FLOW (0x12 << SEQSTAT_HWERRCAUSE_SHIFT)
-#define SEQSTAT_HWERRCAUSE_RAISE_5 (0x18 << SEQSTAT_HWERRCAUSE_SHIFT)
-
-/**************************************************
- * SYSCFG register
- **************************************************/
-
-/* Bit Positions */
-#define SYSCFG_SSSTEP_P 0x00000000 /* Supervisor single step, when
- * set it forces an exception
- * for each instruction executed
- */
-#define SYSCFG_CCEN_P 0x00000001 /* Enable cycle counter (=1) */
-#define SYSCFG_SNEN_P 0x00000002 /* Self nesting Interrupt Enable */
-
-/* Masks */
-
-/* Supervisor single step, when set it forces an exception for each
- *instruction executed
- */
-#define SYSCFG_SSSTEP MK_BMSK_(SYSCFG_SSSTEP_P )
-/* Enable cycle counter (=1) */
-#define SYSCFG_CCEN MK_BMSK_(SYSCFG_CCEN_P )
-/* Self Nesting Interrupt Enable */
-#define SYSCFG_SNEN MK_BMSK_(SYSCFG_SNEN_P)
-/* Backward-compatibility for typos in prior releases */
-#define SYSCFG_SSSSTEP SYSCFG_SSSTEP
-#define SYSCFG_CCCEN SYSCFG_CCEN
-
-/****************************************************
- * Core MMR Register Map
- ****************************************************/
-
-/* Data Cache & SRAM Memory (0xFFE00000 - 0xFFE00404) */
-
-#define SRAM_BASE_ADDRESS 0xFFE00000 /* SRAM Base Address Register */
-#define DMEM_CONTROL 0xFFE00004 /* Data memory control */
-#define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside
- * Buffer Status
- */
-#define DCPLB_FAULT_STATUS 0xFFE00008 /* "" (older define) */
-#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside
- * Buffer Fault Address
- */
-#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside
- * Buffer 0
- */
-#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside
- * Buffer 1
- */
-#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside
- * Buffer 2
- */
-#define DCPLB_ADDR3 0xFFE0010C /* Data Cacheability Protection
- * Lookaside Buffer 3
- */
-#define DCPLB_ADDR4 0xFFE00110 /* Data Cacheability Protection
- * Lookaside Buffer 4
- */
-#define DCPLB_ADDR5 0xFFE00114 /* Data Cacheability Protection
- * Lookaside Buffer 5
- */
-#define DCPLB_ADDR6 0xFFE00118 /* Data Cacheability Protection
- * Lookaside Buffer 6
- */
-#define DCPLB_ADDR7 0xFFE0011C /* Data Cacheability Protection
- * Lookaside Buffer 7
- */
-#define DCPLB_ADDR8 0xFFE00120 /* Data Cacheability Protection
- * Lookaside Buffer 8
- */
-#define DCPLB_ADDR9 0xFFE00124 /* Data Cacheability Protection
- * Lookaside Buffer 9
- */
-#define DCPLB_ADDR10 0xFFE00128 /* Data Cacheability Protection
- * Lookaside Buffer 10
- */
-#define DCPLB_ADDR11 0xFFE0012C /* Data Cacheability Protection
- * Lookaside Buffer 11
- */
-#define DCPLB_ADDR12 0xFFE00130 /* Data Cacheability Protection
- * Lookaside Buffer 12
- */
-#define DCPLB_ADDR13 0xFFE00134 /* Data Cacheability Protection
- * Lookaside Buffer 13
- */
-#define DCPLB_ADDR14 0xFFE00138 /* Data Cacheability Protection
- * Lookaside Buffer 14
- */
-#define DCPLB_ADDR15 0xFFE0013C /* Data Cacheability Protection
- * Lookaside Buffer 15
- */
-#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */
-#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */
-#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */
-#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */
-#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */
-#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */
-#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */
-#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */
-#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */
-#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */
-#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */
-#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */
-#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */
-#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */
-#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */
-#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */
-#define DCPLB_DATA16 0xFFE00240 /* Extra Dummy entry */
-
-#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */
-#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */
-#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */
-
-/* Instruction Cache & SRAM Memory (0xFFE01004 - 0xFFE01404) */
-
-#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */
-#define ICPLB_STATUS 0xFFE01008 /* Instruction Cache miss status */
-#define CODE_FAULT_STATUS 0xFFE01008 /* "" (older define) */
-#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache miss address */
-#define CODE_FAULT_ADDR 0xFFE0100C /* "" (older define) */
-#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability
- * Protection Lookaside Buffer 0
- */
-#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability
- * Protection Lookaside Buffer 1
- */
-#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability
- * Protection Lookaside Buffer 2
- */
-#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability
- * Protection Lookaside Buffer 3
- */
-#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability
- * Protection Lookaside Buffer 4
- */
-#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability
- * Protection Lookaside Buffer 5
- */
-#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability
- * Protection Lookaside Buffer 6
- */
-#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability
- * Protection Lookaside Buffer 7
- */
-#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability
- * Protection Lookaside Buffer 8
- */
-#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability
- * Protection Lookaside Buffer 9
- */
-#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability
- * Protection Lookaside Buffer 10
- */
-#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability
- * Protection Lookaside Buffer 11
- */
-#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability
- * Protection Lookaside Buffer 12
- */
-#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability
- * Protection Lookaside Buffer 13
- */
-#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability
- * Protection Lookaside Buffer 14
- */
-#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability
- * Protection Lookaside Buffer 15
- */
-#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */
-#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */
-#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */
-#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */
-#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */
-#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */
-#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */
-#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */
-#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */
-#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */
-#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */
-#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */
-#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */
-#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */
-#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */
-#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */
-#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */
-#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */
-#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */
-
-/* Event/Interrupt Controller Registers (0xFFE02000 - 0xFFE02110) */
-
-#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */
-#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */
-#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */
-#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */
-#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */
-#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */
-#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */
-#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */
-#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */
-#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */
-#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */
-#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */
-#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */
-#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */
-#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */
-#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */
-#define EVT_OVERRIDE 0xFFE02100 /* Event Vector Override Register */
-#define IMASK 0xFFE02104 /* Interrupt Mask Register */
-#define IPEND 0xFFE02108 /* Interrupt Pending Register */
-#define ILAT 0xFFE0210C /* Interrupt Latch Register */
-#define IPRIO 0xFFE02110 /* Core Interrupt Priority Register */
-
-/* Core Timer Registers (0xFFE03000 - 0xFFE0300C) */
-
-#define TCNTL 0xFFE03000 /* Core Timer Control Register */
-#define TPERIOD 0xFFE03004 /* Core Timer Period Register */
-#define TSCALE 0xFFE03008 /* Core Timer Scale Register */
-#define TCOUNT 0xFFE0300C /* Core Timer Count Register */
-
-/* Debug/MP/Emulation Registers (0xFFE05000 - 0xFFE05008) */
-#define DSPID 0xFFE05000 /* DSP Processor ID Register for
- * MP implementations
- */
-
-#define DBGSTAT 0xFFE05008 /* Debug Status Register */
-
-/* Trace Buffer Registers (0xFFE06000 - 0xFFE06100) */
-
-#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */
-#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */
-#define TBUF 0xFFE06100 /* Trace Buffer */
-
-/* Watchpoint Control Registers (0xFFE07000 - 0xFFE07200) */
-
-/* Watchpoint Instruction Address Control Register */
-#define WPIACTL 0xFFE07000
-/* Watchpoint Instruction Address Register 0 */
-#define WPIA0 0xFFE07040
-/* Watchpoint Instruction Address Register 1 */
-#define WPIA1 0xFFE07044
-/* Watchpoint Instruction Address Register 2 */
-#define WPIA2 0xFFE07048
-/* Watchpoint Instruction Address Register 3 */
-#define WPIA3 0xFFE0704C
-/* Watchpoint Instruction Address Register 4 */
-#define WPIA4 0xFFE07050
-/* Watchpoint Instruction Address Register 5 */
-#define WPIA5 0xFFE07054
-/* Watchpoint Instruction Address Count Register 0 */
-#define WPIACNT0 0xFFE07080
-/* Watchpoint Instruction Address Count Register 1 */
-#define WPIACNT1 0xFFE07084
-/* Watchpoint Instruction Address Count Register 2 */
-#define WPIACNT2 0xFFE07088
-/* Watchpoint Instruction Address Count Register 3 */
-#define WPIACNT3 0xFFE0708C
-/* Watchpoint Instruction Address Count Register 4 */
-#define WPIACNT4 0xFFE07090
-/* Watchpoint Instruction Address Count Register 5 */
-#define WPIACNT5 0xFFE07094
-/* Watchpoint Data Address Control Register */
-#define WPDACTL 0xFFE07100
-/* Watchpoint Data Address Register 0 */
-#define WPDA0 0xFFE07140
-/* Watchpoint Data Address Register 1 */
-#define WPDA1 0xFFE07144
-/* Watchpoint Data Address Count Value Register 0 */
-#define WPDACNT0 0xFFE07180
-/* Watchpoint Data Address Count Value Register 1 */
-#define WPDACNT1 0xFFE07184
-/* Watchpoint Status Register */
-#define WPSTAT 0xFFE07200
-
-/* Performance Monitor Registers (0xFFE08000 - 0xFFE08104) */
-
-/* Performance Monitor Control Register */
-#define PFCTL 0xFFE08000
-/* Performance Monitor Counter Register 0 */
-#define PFCNTR0 0xFFE08100
-/* Performance Monitor Counter Register 1 */
-#define PFCNTR1 0xFFE08104
-
-/****************************************************
- * Core MMR Register Bits
- ****************************************************/
-
-/**************************************************
- * EVT registers (ILAT, IMASK, and IPEND).
- **************************************************/
-
-/* Bit Positions */
-#define EVT_EMU_P 0x00000000 /* Emulator interrupt bit position */
-#define EVT_RST_P 0x00000001 /* Reset interrupt bit position */
-#define EVT_NMI_P 0x00000002 /* Non Maskable interrupt bit position */
-#define EVT_EVX_P 0x00000003 /* Exception bit position */
-#define EVT_IRPTEN_P 0x00000004 /* Global interrupt enable bit position */
-#define EVT_IVHW_P 0x00000005 /* Hardware Error interrupt bit position */
-#define EVT_IVTMR_P 0x00000006 /* Timer interrupt bit position */
-#define EVT_IVG7_P 0x00000007 /* IVG7 interrupt bit position */
-#define EVT_IVG8_P 0x00000008 /* IVG8 interrupt bit position */
-#define EVT_IVG9_P 0x00000009 /* IVG9 interrupt bit position */
-#define EVT_IVG10_P 0x0000000a /* IVG10 interrupt bit position */
-#define EVT_IVG11_P 0x0000000b /* IVG11 interrupt bit position */
-#define EVT_IVG12_P 0x0000000c /* IVG12 interrupt bit position */
-#define EVT_IVG13_P 0x0000000d /* IVG13 interrupt bit position */
-#define EVT_IVG14_P 0x0000000e /* IVG14 interrupt bit position */
-#define EVT_IVG15_P 0x0000000f /* IVG15 interrupt bit position */
-
-/* Masks */
-#define EVT_EMU MK_BMSK_(EVT_EMU_P ) /* Emulator interrupt mask */
-#define EVT_RST MK_BMSK_(EVT_RST_P ) /* Reset interrupt mask */
-#define EVT_NMI MK_BMSK_(EVT_NMI_P ) /* Non Maskable interrupt mask */
-#define EVT_EVX MK_BMSK_(EVT_EVX_P ) /* Exception mask */
-#define EVT_IRPTEN MK_BMSK_(EVT_IRPTEN_P) /* Global interrupt enable mask */
-#define EVT_IVHW MK_BMSK_(EVT_IVHW_P ) /* Hardware Error interrupt mask */
-#define EVT_IVTMR MK_BMSK_(EVT_IVTMR_P ) /* Timer interrupt mask */
-#define EVT_IVG7 MK_BMSK_(EVT_IVG7_P ) /* IVG7 interrupt mask */
-#define EVT_IVG8 MK_BMSK_(EVT_IVG8_P ) /* IVG8 interrupt mask */
-#define EVT_IVG9 MK_BMSK_(EVT_IVG9_P ) /* IVG9 interrupt mask */
-#define EVT_IVG10 MK_BMSK_(EVT_IVG10_P ) /* IVG10 interrupt mask */
-#define EVT_IVG11 MK_BMSK_(EVT_IVG11_P ) /* IVG11 interrupt mask */
-#define EVT_IVG12 MK_BMSK_(EVT_IVG12_P ) /* IVG12 interrupt mask */
-#define EVT_IVG13 MK_BMSK_(EVT_IVG13_P ) /* IVG13 interrupt mask */
-#define EVT_IVG14 MK_BMSK_(EVT_IVG14_P ) /* IVG14 interrupt mask */
-#define EVT_IVG15 MK_BMSK_(EVT_IVG15_P ) /* IVG15 interrupt mask */
-
-/**************************************************
- * DMEM_CONTROL Register
- **************************************************/
-/* Bit Positions */
-#define ENDM_P 0x00 /* (doesn't really exist) Enable
- *Data Memory L1
- */
-#define DMCTL_ENDM_P ENDM_P /* "" (older define) */
-
-#define ENDCPLB_P 0x01 /* Enable DCPLBS */
-#define DMCTL_ENDCPLB_P ENDCPLB_P /* "" (older define) */
-#define DMC0_P 0x02 /* L1 Data Memory Configure bit 0 */
-#define DMCTL_DMC0_P DMC0_P /* "" (older define) */
-#define DMC1_P 0x03 /* L1 Data Memory Configure bit 1 */
-#define DMCTL_DMC1_P DMC1_P /* "" (older define) */
-#define DCBS_P 0x04 /* L1 Data Cache Bank Select */
-#define PORT_PREF0_P 0x12 /* DAG0 Port Preference */
-#define PORT_PREF1_P 0x13 /* DAG1 Port Preference */
-#define RDCHK 0x9 /* Enable L1 Parity Check */
-
-/* Masks */
-#define ENDM 0x00000001 /* (doesn't really exist) Enable
- * Data Memory L1
- */
-#define ENDCPLB 0x00000002 /* Enable DCPLB */
-#define ASRAM_BSRAM 0x00000000
-#define ACACHE_BSRAM 0x00000008
-#define ACACHE_BCACHE 0x0000000C
-#define DCBS 0x00000010 /* L1 Data Cache Bank Select */
-#define PORT_PREF0 0x00001000 /* DAG0 Port Preference */
-#define PORT_PREF1 0x00002000 /* DAG1 Port Preference */
-
-/* IMEM_CONTROL Register */
-/* Bit Positions */
-#define ENIM_P 0x00 /* Enable L1 Code Memory */
-#define IMCTL_ENIM_P 0x00 /* "" (older define) */
-#define ENICPLB_P 0x01 /* Enable ICPLB */
-#define IMCTL_ENICPLB_P 0x01 /* "" (older define) */
-#define IMC_P 0x02 /* Enable */
-#define IMCTL_IMC_P 0x02 /* Configure L1 code memory as
- * cache (0=SRAM)
- */
-#define ILOC0_P 0x03 /* Lock Way 0 */
-#define ILOC1_P 0x04 /* Lock Way 1 */
-#define ILOC2_P 0x05 /* Lock Way 2 */
-#define ILOC3_P 0x06 /* Lock Way 3 */
-#define LRUPRIORST_P 0x0D /* Least Recently Used Replacement
- * Priority
- */
-/* Masks */
-#define ENIM 0x00000001 /* Enable L1 Code Memory */
-#define ENICPLB 0x00000002 /* Enable ICPLB */
-#define IMC 0x00000004 /* Configure L1 code memory as
- * cache (0=SRAM)
- */
-#define ILOC0 0x00000008 /* Lock Way 0 */
-#define ILOC1 0x00000010 /* Lock Way 1 */
-#define ILOC2 0x00000020 /* Lock Way 2 */
-#define ILOC3 0x00000040 /* Lock Way 3 */
-#define LRUPRIORST 0x00002000 /* Least Recently Used Replacement
- * Priority
- */
-
-/* TCNTL Masks */
-#define TMPWR 0x00000001 /* Timer Low Power Control,
- * 0=low power mode, 1=active state
- */
-#define TMREN 0x00000002 /* Timer enable, 0=disable, 1=enable */
-#define TAUTORLD 0x00000004 /* Timer auto reload */
-#define TINT 0x00000008 /* Timer generated interrupt 0=no
- * interrupt has been generated,
- * 1=interrupt has been generated
- * (sticky)
- */
-
-/* DCPLB_DATA and ICPLB_DATA Registers */
-/* Bit Positions */
-#define CPLB_VALID_P 0x00000000 /* 0=invalid entry, 1=valid entry */
-#define CPLB_LOCK_P 0x00000001 /* 0=entry may be replaced, 1=entry
- * locked
- */
-#define CPLB_USER_RD_P 0x00000002 /* 0=no read access, 1=read access
- * allowed (user mode)
- */
-/* Masks */
-#define CPLB_VALID 0x00000001 /* 0=invalid entry, 1=valid entry */
-#define CPLB_LOCK 0x00000002 /* 0=entry may be replaced, 1=entry
- * locked
- */
-#define CPLB_USER_RD 0x00000004 /* 0=no read access, 1=read access
- * allowed (user mode)
- */
-
-#define PAGE_SIZE_1KB 0x00000000 /* 1 KB page size */
-#define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */
-#define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */
-#define PAGE_SIZE_4MB 0x00030000 /* 4 MB page size */
-#ifdef CONFIG_BF60x
-#define PAGE_SIZE_16KB 0x00040000 /* 16 KB page size */
-#define PAGE_SIZE_64KB 0x00050000 /* 64 KB page size */
-#define PAGE_SIZE_16MB 0x00060000 /* 16 MB page size */
-#define PAGE_SIZE_64MB 0x00070000 /* 64 MB page size */
-#endif
-#define CPLB_L1SRAM 0x00000020 /* 0=SRAM mapped in L1, 0=SRAM not
- * mapped to L1
- */
-#define CPLB_PORTPRIO 0x00000200 /* 0=low priority port, 1= high
- * priority port
- */
-#define CPLB_L1_CHBL 0x00001000 /* 0=non-cacheable in L1, 1=cacheable
- * in L1
- */
-/* ICPLB_DATA only */
-#define CPLB_LRUPRIO 0x00000100 /* 0=can be replaced by any line,
- * 1=priority for non-replacement
- */
-/* DCPLB_DATA only */
-#define CPLB_USER_WR 0x00000008 /* 0=no write access, 0=write
- * access allowed (user mode)
- */
-#define CPLB_SUPV_WR 0x00000010 /* 0=no write access, 0=write
- * access allowed (supervisor mode)
- */
-#define CPLB_DIRTY 0x00000080 /* 1=dirty, 0=clean */
-#define CPLB_L1_AOW 0x00008000 /* 0=do not allocate cache lines on
- * write-through writes,
- * 1= allocate cache lines on
- * write-through writes.
- */
-#define CPLB_WT 0x00004000 /* 0=write-back, 1=write-through */
-
-#define CPLB_ALL_ACCESS CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR
-
-/* TBUFCTL Masks */
-#define TBUFPWR 0x0001
-#define TBUFEN 0x0002
-#define TBUFOVF 0x0004
-#define TBUFCMPLP_SINGLE 0x0008
-#define TBUFCMPLP_DOUBLE 0x0010
-#define TBUFCMPLP (TBUFCMPLP_SINGLE | TBUFCMPLP_DOUBLE)
-
-/* TBUFSTAT Masks */
-#define TBUFCNT 0x001F
-
-/* ITEST_COMMAND and DTEST_COMMAND Registers */
-/* Masks */
-#define TEST_READ 0x00000000 /* Read Access */
-#define TEST_WRITE 0x00000002 /* Write Access */
-#define TEST_TAG 0x00000000 /* Access TAG */
-#define TEST_DATA 0x00000004 /* Access DATA */
-#define TEST_DW0 0x00000000 /* Select Double Word 0 */
-#define TEST_DW1 0x00000008 /* Select Double Word 1 */
-#define TEST_DW2 0x00000010 /* Select Double Word 2 */
-#define TEST_DW3 0x00000018 /* Select Double Word 3 */
-#define TEST_MB0 0x00000000 /* Select Mini-Bank 0 */
-#define TEST_MB1 0x00010000 /* Select Mini-Bank 1 */
-#define TEST_MB2 0x00020000 /* Select Mini-Bank 2 */
-#define TEST_MB3 0x00030000 /* Select Mini-Bank 3 */
-#define TEST_SET(x) ((x << 5) & 0x03E0) /* Set Index 0->31 */
-#define TEST_WAY0 0x00000000 /* Access Way0 */
-#define TEST_WAY1 0x04000000 /* Access Way1 */
-/* ITEST_COMMAND only */
-#define TEST_WAY2 0x08000000 /* Access Way2 */
-#define TEST_WAY3 0x0C000000 /* Access Way3 */
-/* DTEST_COMMAND only */
-#define TEST_BNKSELA 0x00000000 /* Access SuperBank A */
-#define TEST_BNKSELB 0x00800000 /* Access SuperBank B */
-
-#endif /* _DEF_LPBLACKFIN_H */
+++ /dev/null
-/*
- * delay.h - delay functions
- *
- * Copyright (c) 2004-2007 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_DELAY_H__
-#define __ASM_DELAY_H__
-
-#include <mach/anomaly.h>
-
-static inline void __delay(unsigned long loops)
-{
-__asm__ __volatile__ (
- "LSETUP(1f, 1f) LC0 = %0;"
- "1: NOP;"
- :
- : "a" (loops)
- : "LT0", "LB0", "LC0"
- );
-}
-
-#include <linux/param.h> /* needed for HZ */
-
-/*
- * close approximation borrowed from m68knommu to avoid 64-bit math
- */
-
-#define HZSCALE (268435456 / (1000000/HZ))
-
-static inline unsigned long __to_delay(unsigned long scale)
-{
- extern unsigned long loops_per_jiffy;
- return (((scale * HZSCALE) >> 11) * (loops_per_jiffy >> 11)) >> 6;
-}
-
-static inline void udelay(unsigned long usecs)
-{
- __delay(__to_delay(usecs));
-}
-
-static inline void ndelay(unsigned long nsecs)
-{
- __delay(__to_delay(1) * nsecs / 1000);
-}
-
-#define ndelay ndelay
-
-#endif
+++ /dev/null
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BLACKFIN_DMA_MAPPING_H
-#define _BLACKFIN_DMA_MAPPING_H
-
-#include <asm/cacheflush.h>
-
-extern void
-__dma_sync(dma_addr_t addr, size_t size, enum dma_data_direction dir);
-static inline void
-__dma_sync_inline(dma_addr_t addr, size_t size, enum dma_data_direction dir)
-{
- switch (dir) {
- case DMA_NONE:
- BUG();
- case DMA_TO_DEVICE: /* writeback only */
- flush_dcache_range(addr, addr + size);
- break;
- case DMA_FROM_DEVICE: /* invalidate only */
- case DMA_BIDIRECTIONAL: /* flush and invalidate */
- /* Blackfin has no dedicated invalidate (it includes a flush) */
- invalidate_dcache_range(addr, addr + size);
- break;
- }
-}
-static inline void
-_dma_sync(dma_addr_t addr, size_t size, enum dma_data_direction dir)
-{
- if (__builtin_constant_p(dir))
- __dma_sync_inline(addr, size, dir);
- else
- __dma_sync(addr, size, dir);
-}
-
-extern const struct dma_map_ops bfin_dma_ops;
-
-static inline const struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus)
-{
- return &bfin_dma_ops;
-}
-
-#endif /* _BLACKFIN_DMA_MAPPING_H */
+++ /dev/null
-/*
- * dma.h - Blackfin DMA defines/structures/etc...
- *
- * Copyright 2004-2008 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BLACKFIN_DMA_H_
-#define _BLACKFIN_DMA_H_
-
-#include <linux/interrupt.h>
-#include <mach/dma.h>
-#include <linux/atomic.h>
-#include <asm/blackfin.h>
-#include <asm/page.h>
-#include <asm-generic/dma.h>
-#include <asm/bfin_dma.h>
-
-/*-------------------------
- * config reg bits value
- *-------------------------*/
-#define DATA_SIZE_8 0
-#define DATA_SIZE_16 1
-#define DATA_SIZE_32 2
-#ifdef CONFIG_BF60x
-#define DATA_SIZE_64 3
-#endif
-
-#define DMA_FLOW_STOP 0
-#define DMA_FLOW_AUTO 1
-#ifdef CONFIG_BF60x
-#define DMA_FLOW_LIST 4
-#define DMA_FLOW_ARRAY 5
-#define DMA_FLOW_LIST_DEMAND 6
-#define DMA_FLOW_ARRAY_DEMAND 7
-#else
-#define DMA_FLOW_ARRAY 4
-#define DMA_FLOW_SMALL 6
-#define DMA_FLOW_LARGE 7
-#endif
-
-#define DIMENSION_LINEAR 0
-#define DIMENSION_2D 1
-
-#define DIR_READ 0
-#define DIR_WRITE 1
-
-#define INTR_DISABLE 0
-#ifdef CONFIG_BF60x
-#define INTR_ON_PERI 1
-#endif
-#define INTR_ON_BUF 2
-#define INTR_ON_ROW 3
-
-#define DMA_NOSYNC_KEEP_DMA_BUF 0
-#define DMA_SYNC_RESTART 1
-
-#ifdef DMA_MMR_SIZE_32
-#define DMA_MMR_SIZE_TYPE long
-#define DMA_MMR_READ bfin_read32
-#define DMA_MMR_WRITE bfin_write32
-#else
-#define DMA_MMR_SIZE_TYPE short
-#define DMA_MMR_READ bfin_read16
-#define DMA_MMR_WRITE bfin_write16
-#endif
-
-struct dma_desc_array {
- unsigned long start_addr;
- unsigned DMA_MMR_SIZE_TYPE cfg;
- unsigned DMA_MMR_SIZE_TYPE x_count;
- DMA_MMR_SIZE_TYPE x_modify;
-} __attribute__((packed));
-
-struct dmasg {
- void *next_desc_addr;
- unsigned long start_addr;
- unsigned DMA_MMR_SIZE_TYPE cfg;
- unsigned DMA_MMR_SIZE_TYPE x_count;
- DMA_MMR_SIZE_TYPE x_modify;
- unsigned DMA_MMR_SIZE_TYPE y_count;
- DMA_MMR_SIZE_TYPE y_modify;
-} __attribute__((packed));
-
-struct dma_register {
- void *next_desc_ptr; /* DMA Next Descriptor Pointer register */
- unsigned long start_addr; /* DMA Start address register */
-#ifdef CONFIG_BF60x
- unsigned long cfg; /* DMA Configuration register */
-
- unsigned long x_count; /* DMA x_count register */
-
- long x_modify; /* DMA x_modify register */
-
- unsigned long y_count; /* DMA y_count register */
-
- long y_modify; /* DMA y_modify register */
-
- unsigned long reserved;
- unsigned long reserved2;
-
- void *curr_desc_ptr; /* DMA Current Descriptor Pointer
- register */
- void *prev_desc_ptr; /* DMA previous initial Descriptor Pointer
- register */
- unsigned long curr_addr_ptr; /* DMA Current Address Pointer
- register */
- unsigned long irq_status; /* DMA irq status register */
-
- unsigned long curr_x_count; /* DMA Current x-count register */
-
- unsigned long curr_y_count; /* DMA Current y-count register */
-
- unsigned long reserved3;
-
- unsigned long bw_limit_count; /* DMA band width limit count register */
- unsigned long curr_bw_limit_count; /* DMA Current band width limit
- count register */
- unsigned long bw_monitor_count; /* DMA band width limit count register */
- unsigned long curr_bw_monitor_count; /* DMA Current band width limit
- count register */
-#else
- unsigned short cfg; /* DMA Configuration register */
- unsigned short dummy1; /* DMA Configuration register */
-
- unsigned long reserved;
-
- unsigned short x_count; /* DMA x_count register */
- unsigned short dummy2;
-
- short x_modify; /* DMA x_modify register */
- unsigned short dummy3;
-
- unsigned short y_count; /* DMA y_count register */
- unsigned short dummy4;
-
- short y_modify; /* DMA y_modify register */
- unsigned short dummy5;
-
- void *curr_desc_ptr; /* DMA Current Descriptor Pointer
- register */
- unsigned long curr_addr_ptr; /* DMA Current Address Pointer
- register */
- unsigned short irq_status; /* DMA irq status register */
- unsigned short dummy6;
-
- unsigned short peripheral_map; /* DMA peripheral map register */
- unsigned short dummy7;
-
- unsigned short curr_x_count; /* DMA Current x-count register */
- unsigned short dummy8;
-
- unsigned long reserved2;
-
- unsigned short curr_y_count; /* DMA Current y-count register */
- unsigned short dummy9;
-
- unsigned long reserved3;
-#endif
-
-};
-
-struct dma_channel {
- const char *device_id;
- atomic_t chan_status;
- volatile struct dma_register *regs;
- struct dmasg *sg; /* large mode descriptor */
- unsigned int irq;
- void *data;
-#ifdef CONFIG_PM
- unsigned short saved_peripheral_map;
-#endif
-};
-
-#ifdef CONFIG_PM
-int blackfin_dma_suspend(void);
-void blackfin_dma_resume(void);
-#endif
-
-/*******************************************************************************
-* DMA API's
-*******************************************************************************/
-extern struct dma_channel dma_ch[MAX_DMA_CHANNELS];
-extern struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS];
-extern int channel2irq(unsigned int channel);
-
-static inline void set_dma_start_addr(unsigned int channel, unsigned long addr)
-{
- dma_ch[channel].regs->start_addr = addr;
-}
-static inline void set_dma_next_desc_addr(unsigned int channel, void *addr)
-{
- dma_ch[channel].regs->next_desc_ptr = addr;
-}
-static inline void set_dma_curr_desc_addr(unsigned int channel, void *addr)
-{
- dma_ch[channel].regs->curr_desc_ptr = addr;
-}
-static inline void set_dma_x_count(unsigned int channel, unsigned DMA_MMR_SIZE_TYPE x_count)
-{
- dma_ch[channel].regs->x_count = x_count;
-}
-static inline void set_dma_y_count(unsigned int channel, unsigned DMA_MMR_SIZE_TYPE y_count)
-{
- dma_ch[channel].regs->y_count = y_count;
-}
-static inline void set_dma_x_modify(unsigned int channel, DMA_MMR_SIZE_TYPE x_modify)
-{
- dma_ch[channel].regs->x_modify = x_modify;
-}
-static inline void set_dma_y_modify(unsigned int channel, DMA_MMR_SIZE_TYPE y_modify)
-{
- dma_ch[channel].regs->y_modify = y_modify;
-}
-static inline void set_dma_config(unsigned int channel, unsigned DMA_MMR_SIZE_TYPE config)
-{
- dma_ch[channel].regs->cfg = config;
-}
-static inline void set_dma_curr_addr(unsigned int channel, unsigned long addr)
-{
- dma_ch[channel].regs->curr_addr_ptr = addr;
-}
-
-#ifdef CONFIG_BF60x
-static inline unsigned long
-set_bfin_dma_config2(char direction, char flow_mode, char intr_mode,
- char dma_mode, char mem_width, char syncmode, char peri_width)
-{
- unsigned long config = 0;
-
- switch (intr_mode) {
- case INTR_ON_BUF:
- if (dma_mode == DIMENSION_2D)
- config = DI_EN_Y;
- else
- config = DI_EN_X;
- break;
- case INTR_ON_ROW:
- config = DI_EN_X;
- break;
- case INTR_ON_PERI:
- config = DI_EN_P;
- break;
- };
-
- return config | (direction << 1) | (mem_width << 8) | (dma_mode << 26) |
- (flow_mode << 12) | (syncmode << 2) | (peri_width << 4);
-}
-#endif
-
-static inline unsigned DMA_MMR_SIZE_TYPE
-set_bfin_dma_config(char direction, char flow_mode,
- char intr_mode, char dma_mode, char mem_width, char syncmode)
-{
-#ifdef CONFIG_BF60x
- return set_bfin_dma_config2(direction, flow_mode, intr_mode, dma_mode,
- mem_width, syncmode, mem_width);
-#else
- return (direction << 1) | (mem_width << 2) | (dma_mode << 4) |
- (intr_mode << 6) | (flow_mode << 12) | (syncmode << 5);
-#endif
-}
-
-static inline unsigned DMA_MMR_SIZE_TYPE get_dma_curr_irqstat(unsigned int channel)
-{
- return dma_ch[channel].regs->irq_status;
-}
-static inline unsigned DMA_MMR_SIZE_TYPE get_dma_curr_xcount(unsigned int channel)
-{
- return dma_ch[channel].regs->curr_x_count;
-}
-static inline unsigned DMA_MMR_SIZE_TYPE get_dma_curr_ycount(unsigned int channel)
-{
- return dma_ch[channel].regs->curr_y_count;
-}
-static inline void *get_dma_next_desc_ptr(unsigned int channel)
-{
- return dma_ch[channel].regs->next_desc_ptr;
-}
-static inline void *get_dma_curr_desc_ptr(unsigned int channel)
-{
- return dma_ch[channel].regs->curr_desc_ptr;
-}
-static inline unsigned DMA_MMR_SIZE_TYPE get_dma_config(unsigned int channel)
-{
- return dma_ch[channel].regs->cfg;
-}
-static inline unsigned long get_dma_curr_addr(unsigned int channel)
-{
- return dma_ch[channel].regs->curr_addr_ptr;
-}
-
-static inline void set_dma_sg(unsigned int channel, struct dmasg *sg, int ndsize)
-{
- /* Make sure the internal data buffers in the core are drained
- * so that the DMA descriptors are completely written when the
- * DMA engine goes to fetch them below.
- */
- SSYNC();
-
- dma_ch[channel].regs->next_desc_ptr = sg;
- dma_ch[channel].regs->cfg =
- (dma_ch[channel].regs->cfg & ~NDSIZE) |
- ((ndsize << NDSIZE_OFFSET) & NDSIZE);
-}
-
-static inline int dma_channel_active(unsigned int channel)
-{
- return atomic_read(&dma_ch[channel].chan_status);
-}
-
-static inline void disable_dma(unsigned int channel)
-{
- dma_ch[channel].regs->cfg &= ~DMAEN;
- SSYNC();
-}
-static inline void enable_dma(unsigned int channel)
-{
- dma_ch[channel].regs->curr_x_count = 0;
- dma_ch[channel].regs->curr_y_count = 0;
- dma_ch[channel].regs->cfg |= DMAEN;
-}
-int set_dma_callback(unsigned int channel, irq_handler_t callback, void *data);
-
-static inline void dma_disable_irq(unsigned int channel)
-{
- disable_irq(dma_ch[channel].irq);
-}
-static inline void dma_disable_irq_nosync(unsigned int channel)
-{
- disable_irq_nosync(dma_ch[channel].irq);
-}
-static inline void dma_enable_irq(unsigned int channel)
-{
- enable_irq(dma_ch[channel].irq);
-}
-static inline void clear_dma_irqstat(unsigned int channel)
-{
- dma_ch[channel].regs->irq_status = DMA_DONE | DMA_ERR | DMA_PIRQ;
-}
-
-void *dma_memcpy(void *dest, const void *src, size_t count);
-void *dma_memcpy_nocache(void *dest, const void *src, size_t count);
-void *safe_dma_memcpy(void *dest, const void *src, size_t count);
-void blackfin_dma_early_init(void);
-void early_dma_memcpy(void *dest, const void *src, size_t count);
-void early_dma_memcpy_done(void);
-
-#endif
+++ /dev/null
-/*
- * Miscellaneous IOCTL commands for Dynamic Power Management Controller Driver
- *
- * Copyright (C) 2004-2009 Analog Device Inc.
- *
- * Licensed under the GPL-2
- */
-
-#ifndef _BLACKFIN_DPMC_H_
-#define _BLACKFIN_DPMC_H_
-
-#ifdef __ASSEMBLY__
-#define PM_REG0 R7
-#define PM_REG1 R6
-#define PM_REG2 R5
-#define PM_REG3 R4
-#define PM_REG4 R3
-#define PM_REG5 R2
-#define PM_REG6 R1
-#define PM_REG7 R0
-#define PM_REG8 P5
-#define PM_REG9 P4
-#define PM_REG10 P3
-#define PM_REG11 P2
-#define PM_REG12 P1
-#define PM_REG13 P0
-
-#define PM_REGSET0 R7:7
-#define PM_REGSET1 R7:6
-#define PM_REGSET2 R7:5
-#define PM_REGSET3 R7:4
-#define PM_REGSET4 R7:3
-#define PM_REGSET5 R7:2
-#define PM_REGSET6 R7:1
-#define PM_REGSET7 R7:0
-#define PM_REGSET8 R7:0, P5:5
-#define PM_REGSET9 R7:0, P5:4
-#define PM_REGSET10 R7:0, P5:3
-#define PM_REGSET11 R7:0, P5:2
-#define PM_REGSET12 R7:0, P5:1
-#define PM_REGSET13 R7:0, P5:0
-
-#define _PM_PUSH(n, x, w, base) PM_REG##n = w[FP + ((x) - (base))];
-#define _PM_POP(n, x, w, base) w[FP + ((x) - (base))] = PM_REG##n;
-#define PM_PUSH_SYNC(n) [--sp] = (PM_REGSET##n);
-#define PM_POP_SYNC(n) (PM_REGSET##n) = [sp++];
-#define PM_PUSH(n, x) PM_REG##n = [FP++];
-#define PM_POP(n, x) [FP--] = PM_REG##n;
-#define PM_CORE_PUSH(n, x) _PM_PUSH(n, x, , COREMMR_BASE)
-#define PM_CORE_POP(n, x) _PM_POP(n, x, , COREMMR_BASE)
-#define PM_SYS_PUSH(n, x) _PM_PUSH(n, x, , SYSMMR_BASE)
-#define PM_SYS_POP(n, x) _PM_POP(n, x, , SYSMMR_BASE)
-#define PM_SYS_PUSH16(n, x) _PM_PUSH(n, x, w, SYSMMR_BASE)
-#define PM_SYS_POP16(n, x) _PM_POP(n, x, w, SYSMMR_BASE)
-
- .macro bfin_init_pm_bench_cycles
-#ifdef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH
- R4 = 0;
- CYCLES = R4;
- CYCLES2 = R4;
- R4 = SYSCFG;
- BITSET(R4, 1);
- SYSCFG = R4;
-#endif
- .endm
-
- .macro bfin_cpu_reg_save
- /*
- * Save the core regs early so we can blow them away when
- * saving/restoring MMR states
- */
- [--sp] = (R7:0, P5:0);
- [--sp] = fp;
- [--sp] = usp;
-
- [--sp] = i0;
- [--sp] = i1;
- [--sp] = i2;
- [--sp] = i3;
-
- [--sp] = m0;
- [--sp] = m1;
- [--sp] = m2;
- [--sp] = m3;
-
- [--sp] = l0;
- [--sp] = l1;
- [--sp] = l2;
- [--sp] = l3;
-
- [--sp] = b0;
- [--sp] = b1;
- [--sp] = b2;
- [--sp] = b3;
- [--sp] = a0.x;
- [--sp] = a0.w;
- [--sp] = a1.x;
- [--sp] = a1.w;
-
- [--sp] = LC0;
- [--sp] = LC1;
- [--sp] = LT0;
- [--sp] = LT1;
- [--sp] = LB0;
- [--sp] = LB1;
-
- /* We can't push RETI directly as that'll change IPEND[4] */
- r7 = RETI;
- [--sp] = RETS;
- [--sp] = ASTAT;
-#ifndef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH
- [--sp] = CYCLES;
- [--sp] = CYCLES2;
-#endif
- [--sp] = SYSCFG;
- [--sp] = RETX;
- [--sp] = SEQSTAT;
- [--sp] = r7;
-
- /* Save first func arg in M3 */
- M3 = R0;
- .endm
-
- .macro bfin_cpu_reg_restore
- /* Restore Core Registers */
- RETI = [sp++];
- SEQSTAT = [sp++];
- RETX = [sp++];
- SYSCFG = [sp++];
-#ifndef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH
- CYCLES2 = [sp++];
- CYCLES = [sp++];
-#endif
- ASTAT = [sp++];
- RETS = [sp++];
-
- LB1 = [sp++];
- LB0 = [sp++];
- LT1 = [sp++];
- LT0 = [sp++];
- LC1 = [sp++];
- LC0 = [sp++];
-
- a1.w = [sp++];
- a1.x = [sp++];
- a0.w = [sp++];
- a0.x = [sp++];
- b3 = [sp++];
- b2 = [sp++];
- b1 = [sp++];
- b0 = [sp++];
-
- l3 = [sp++];
- l2 = [sp++];
- l1 = [sp++];
- l0 = [sp++];
-
- m3 = [sp++];
- m2 = [sp++];
- m1 = [sp++];
- m0 = [sp++];
-
- i3 = [sp++];
- i2 = [sp++];
- i1 = [sp++];
- i0 = [sp++];
-
- usp = [sp++];
- fp = [sp++];
- (R7:0, P5:0) = [sp++];
-
- .endm
-
- .macro bfin_sys_mmr_save
- /* Save system MMRs */
- FP.H = hi(SYSMMR_BASE);
- FP.L = lo(SYSMMR_BASE);
-#ifdef SIC_IMASK0
- PM_SYS_PUSH(0, SIC_IMASK0)
- PM_SYS_PUSH(1, SIC_IMASK1)
-# ifdef SIC_IMASK2
- PM_SYS_PUSH(2, SIC_IMASK2)
-# endif
-#else
-# ifdef SIC_IMASK
- PM_SYS_PUSH(0, SIC_IMASK)
-# endif
-#endif
-
-#ifdef SIC_IAR0
- PM_SYS_PUSH(3, SIC_IAR0)
- PM_SYS_PUSH(4, SIC_IAR1)
- PM_SYS_PUSH(5, SIC_IAR2)
-#endif
-#ifdef SIC_IAR3
- PM_SYS_PUSH(6, SIC_IAR3)
-#endif
-#ifdef SIC_IAR4
- PM_SYS_PUSH(7, SIC_IAR4)
- PM_SYS_PUSH(8, SIC_IAR5)
- PM_SYS_PUSH(9, SIC_IAR6)
-#endif
-#ifdef SIC_IAR7
- PM_SYS_PUSH(10, SIC_IAR7)
-#endif
-#ifdef SIC_IAR8
- PM_SYS_PUSH(11, SIC_IAR8)
- PM_SYS_PUSH(12, SIC_IAR9)
- PM_SYS_PUSH(13, SIC_IAR10)
-#endif
- PM_PUSH_SYNC(13)
-#ifdef SIC_IAR11
- PM_SYS_PUSH(0, SIC_IAR11)
-#endif
-
-#ifdef SIC_IWR
- PM_SYS_PUSH(1, SIC_IWR)
-#endif
-#ifdef SIC_IWR0
- PM_SYS_PUSH(1, SIC_IWR0)
-#endif
-#ifdef SIC_IWR1
- PM_SYS_PUSH(2, SIC_IWR1)
-#endif
-#ifdef SIC_IWR2
- PM_SYS_PUSH(3, SIC_IWR2)
-#endif
-
-#ifdef PINT0_ASSIGN
- PM_SYS_PUSH(4, PINT0_MASK_SET)
- PM_SYS_PUSH(5, PINT1_MASK_SET)
- PM_SYS_PUSH(6, PINT2_MASK_SET)
- PM_SYS_PUSH(7, PINT3_MASK_SET)
- PM_SYS_PUSH(8, PINT0_ASSIGN)
- PM_SYS_PUSH(9, PINT1_ASSIGN)
- PM_SYS_PUSH(10, PINT2_ASSIGN)
- PM_SYS_PUSH(11, PINT3_ASSIGN)
- PM_SYS_PUSH(12, PINT0_INVERT_SET)
- PM_SYS_PUSH(13, PINT1_INVERT_SET)
- PM_PUSH_SYNC(13)
- PM_SYS_PUSH(0, PINT2_INVERT_SET)
- PM_SYS_PUSH(1, PINT3_INVERT_SET)
- PM_SYS_PUSH(2, PINT0_EDGE_SET)
- PM_SYS_PUSH(3, PINT1_EDGE_SET)
- PM_SYS_PUSH(4, PINT2_EDGE_SET)
- PM_SYS_PUSH(5, PINT3_EDGE_SET)
-#endif
-
-#ifdef SYSCR
- PM_SYS_PUSH16(6, SYSCR)
-#endif
-
-#ifdef EBIU_AMGCTL
- PM_SYS_PUSH16(7, EBIU_AMGCTL)
- PM_SYS_PUSH(8, EBIU_AMBCTL0)
- PM_SYS_PUSH(9, EBIU_AMBCTL1)
-#endif
-#ifdef EBIU_FCTL
- PM_SYS_PUSH(10, EBIU_MBSCTL)
- PM_SYS_PUSH(11, EBIU_MODE)
- PM_SYS_PUSH(12, EBIU_FCTL)
- PM_PUSH_SYNC(12)
-#else
- PM_PUSH_SYNC(9)
-#endif
- .endm
-
-
- .macro bfin_sys_mmr_restore
-/* Restore System MMRs */
- FP.H = hi(SYSMMR_BASE);
- FP.L = lo(SYSMMR_BASE);
-
-#ifdef EBIU_FCTL
- PM_POP_SYNC(12)
- PM_SYS_POP(12, EBIU_FCTL)
- PM_SYS_POP(11, EBIU_MODE)
- PM_SYS_POP(10, EBIU_MBSCTL)
-#else
- PM_POP_SYNC(9)
-#endif
-
-#ifdef EBIU_AMGCTL
- PM_SYS_POP(9, EBIU_AMBCTL1)
- PM_SYS_POP(8, EBIU_AMBCTL0)
- PM_SYS_POP16(7, EBIU_AMGCTL)
-#endif
-
-#ifdef SYSCR
- PM_SYS_POP16(6, SYSCR)
-#endif
-
-#ifdef PINT0_ASSIGN
- PM_SYS_POP(5, PINT3_EDGE_SET)
- PM_SYS_POP(4, PINT2_EDGE_SET)
- PM_SYS_POP(3, PINT1_EDGE_SET)
- PM_SYS_POP(2, PINT0_EDGE_SET)
- PM_SYS_POP(1, PINT3_INVERT_SET)
- PM_SYS_POP(0, PINT2_INVERT_SET)
- PM_POP_SYNC(13)
- PM_SYS_POP(13, PINT1_INVERT_SET)
- PM_SYS_POP(12, PINT0_INVERT_SET)
- PM_SYS_POP(11, PINT3_ASSIGN)
- PM_SYS_POP(10, PINT2_ASSIGN)
- PM_SYS_POP(9, PINT1_ASSIGN)
- PM_SYS_POP(8, PINT0_ASSIGN)
- PM_SYS_POP(7, PINT3_MASK_SET)
- PM_SYS_POP(6, PINT2_MASK_SET)
- PM_SYS_POP(5, PINT1_MASK_SET)
- PM_SYS_POP(4, PINT0_MASK_SET)
-#endif
-
-#ifdef SIC_IWR2
- PM_SYS_POP(3, SIC_IWR2)
-#endif
-#ifdef SIC_IWR1
- PM_SYS_POP(2, SIC_IWR1)
-#endif
-#ifdef SIC_IWR0
- PM_SYS_POP(1, SIC_IWR0)
-#endif
-#ifdef SIC_IWR
- PM_SYS_POP(1, SIC_IWR)
-#endif
-
-#ifdef SIC_IAR11
- PM_SYS_POP(0, SIC_IAR11)
-#endif
- PM_POP_SYNC(13)
-#ifdef SIC_IAR8
- PM_SYS_POP(13, SIC_IAR10)
- PM_SYS_POP(12, SIC_IAR9)
- PM_SYS_POP(11, SIC_IAR8)
-#endif
-#ifdef SIC_IAR7
- PM_SYS_POP(10, SIC_IAR7)
-#endif
-#ifdef SIC_IAR6
- PM_SYS_POP(9, SIC_IAR6)
- PM_SYS_POP(8, SIC_IAR5)
- PM_SYS_POP(7, SIC_IAR4)
-#endif
-#ifdef SIC_IAR3
- PM_SYS_POP(6, SIC_IAR3)
-#endif
-#ifdef SIC_IAR0
- PM_SYS_POP(5, SIC_IAR2)
- PM_SYS_POP(4, SIC_IAR1)
- PM_SYS_POP(3, SIC_IAR0)
-#endif
-#ifdef SIC_IMASK0
-# ifdef SIC_IMASK2
- PM_SYS_POP(2, SIC_IMASK2)
-# endif
- PM_SYS_POP(1, SIC_IMASK1)
- PM_SYS_POP(0, SIC_IMASK0)
-#else
-# ifdef SIC_IMASK
- PM_SYS_POP(0, SIC_IMASK)
-# endif
-#endif
- .endm
-
- .macro bfin_core_mmr_save
- /* Save Core MMRs */
- I0.H = hi(COREMMR_BASE);
- I0.L = lo(COREMMR_BASE);
- I1 = I0;
- I2 = I0;
- I3 = I0;
- B0 = I0;
- B1 = I0;
- B2 = I0;
- B3 = I0;
- I1.L = lo(DCPLB_ADDR0);
- I2.L = lo(DCPLB_DATA0);
- I3.L = lo(ICPLB_ADDR0);
- B0.L = lo(ICPLB_DATA0);
- B1.L = lo(EVT2);
- B2.L = lo(IMASK);
- B3.L = lo(TCNTL);
-
- /* Event Vectors */
- FP = B1;
- PM_PUSH(0, EVT2)
- PM_PUSH(1, EVT3)
- FP += 4; /* EVT4 */
- PM_PUSH(2, EVT5)
- PM_PUSH(3, EVT6)
- PM_PUSH(4, EVT7)
- PM_PUSH(5, EVT8)
- PM_PUSH_SYNC(5)
-
- PM_PUSH(0, EVT9)
- PM_PUSH(1, EVT10)
- PM_PUSH(2, EVT11)
- PM_PUSH(3, EVT12)
- PM_PUSH(4, EVT13)
- PM_PUSH(5, EVT14)
- PM_PUSH(6, EVT15)
-
- /* CEC */
- FP = B2;
- PM_PUSH(7, IMASK)
- FP += 4; /* IPEND */
- PM_PUSH(8, ILAT)
- PM_PUSH(9, IPRIO)
-
- /* Core Timer */
- FP = B3;
- PM_PUSH(10, TCNTL)
- PM_PUSH(11, TPERIOD)
- PM_PUSH(12, TSCALE)
- PM_PUSH(13, TCOUNT)
- PM_PUSH_SYNC(13)
-
- /* Misc non-contiguous registers */
- FP = I0;
- PM_CORE_PUSH(0, DMEM_CONTROL);
- PM_CORE_PUSH(1, IMEM_CONTROL);
- PM_CORE_PUSH(2, TBUFCTL);
- PM_PUSH_SYNC(2)
-
- /* DCPLB Addr */
- FP = I1;
- PM_PUSH(0, DCPLB_ADDR0)
- PM_PUSH(1, DCPLB_ADDR1)
- PM_PUSH(2, DCPLB_ADDR2)
- PM_PUSH(3, DCPLB_ADDR3)
- PM_PUSH(4, DCPLB_ADDR4)
- PM_PUSH(5, DCPLB_ADDR5)
- PM_PUSH(6, DCPLB_ADDR6)
- PM_PUSH(7, DCPLB_ADDR7)
- PM_PUSH(8, DCPLB_ADDR8)
- PM_PUSH(9, DCPLB_ADDR9)
- PM_PUSH(10, DCPLB_ADDR10)
- PM_PUSH(11, DCPLB_ADDR11)
- PM_PUSH(12, DCPLB_ADDR12)
- PM_PUSH(13, DCPLB_ADDR13)
- PM_PUSH_SYNC(13)
- PM_PUSH(0, DCPLB_ADDR14)
- PM_PUSH(1, DCPLB_ADDR15)
-
- /* DCPLB Data */
- FP = I2;
- PM_PUSH(2, DCPLB_DATA0)
- PM_PUSH(3, DCPLB_DATA1)
- PM_PUSH(4, DCPLB_DATA2)
- PM_PUSH(5, DCPLB_DATA3)
- PM_PUSH(6, DCPLB_DATA4)
- PM_PUSH(7, DCPLB_DATA5)
- PM_PUSH(8, DCPLB_DATA6)
- PM_PUSH(9, DCPLB_DATA7)
- PM_PUSH(10, DCPLB_DATA8)
- PM_PUSH(11, DCPLB_DATA9)
- PM_PUSH(12, DCPLB_DATA10)
- PM_PUSH(13, DCPLB_DATA11)
- PM_PUSH_SYNC(13)
- PM_PUSH(0, DCPLB_DATA12)
- PM_PUSH(1, DCPLB_DATA13)
- PM_PUSH(2, DCPLB_DATA14)
- PM_PUSH(3, DCPLB_DATA15)
-
- /* ICPLB Addr */
- FP = I3;
- PM_PUSH(4, ICPLB_ADDR0)
- PM_PUSH(5, ICPLB_ADDR1)
- PM_PUSH(6, ICPLB_ADDR2)
- PM_PUSH(7, ICPLB_ADDR3)
- PM_PUSH(8, ICPLB_ADDR4)
- PM_PUSH(9, ICPLB_ADDR5)
- PM_PUSH(10, ICPLB_ADDR6)
- PM_PUSH(11, ICPLB_ADDR7)
- PM_PUSH(12, ICPLB_ADDR8)
- PM_PUSH(13, ICPLB_ADDR9)
- PM_PUSH_SYNC(13)
- PM_PUSH(0, ICPLB_ADDR10)
- PM_PUSH(1, ICPLB_ADDR11)
- PM_PUSH(2, ICPLB_ADDR12)
- PM_PUSH(3, ICPLB_ADDR13)
- PM_PUSH(4, ICPLB_ADDR14)
- PM_PUSH(5, ICPLB_ADDR15)
-
- /* ICPLB Data */
- FP = B0;
- PM_PUSH(6, ICPLB_DATA0)
- PM_PUSH(7, ICPLB_DATA1)
- PM_PUSH(8, ICPLB_DATA2)
- PM_PUSH(9, ICPLB_DATA3)
- PM_PUSH(10, ICPLB_DATA4)
- PM_PUSH(11, ICPLB_DATA5)
- PM_PUSH(12, ICPLB_DATA6)
- PM_PUSH(13, ICPLB_DATA7)
- PM_PUSH_SYNC(13)
- PM_PUSH(0, ICPLB_DATA8)
- PM_PUSH(1, ICPLB_DATA9)
- PM_PUSH(2, ICPLB_DATA10)
- PM_PUSH(3, ICPLB_DATA11)
- PM_PUSH(4, ICPLB_DATA12)
- PM_PUSH(5, ICPLB_DATA13)
- PM_PUSH(6, ICPLB_DATA14)
- PM_PUSH(7, ICPLB_DATA15)
- PM_PUSH_SYNC(7)
- .endm
-
- .macro bfin_core_mmr_restore
- /* Restore Core MMRs */
- I0.H = hi(COREMMR_BASE);
- I0.L = lo(COREMMR_BASE);
- I1 = I0;
- I2 = I0;
- I3 = I0;
- B0 = I0;
- B1 = I0;
- B2 = I0;
- B3 = I0;
- I1.L = lo(DCPLB_ADDR15);
- I2.L = lo(DCPLB_DATA15);
- I3.L = lo(ICPLB_ADDR15);
- B0.L = lo(ICPLB_DATA15);
- B1.L = lo(EVT15);
- B2.L = lo(IPRIO);
- B3.L = lo(TCOUNT);
-
- /* ICPLB Data */
- FP = B0;
- PM_POP_SYNC(7)
- PM_POP(7, ICPLB_DATA15)
- PM_POP(6, ICPLB_DATA14)
- PM_POP(5, ICPLB_DATA13)
- PM_POP(4, ICPLB_DATA12)
- PM_POP(3, ICPLB_DATA11)
- PM_POP(2, ICPLB_DATA10)
- PM_POP(1, ICPLB_DATA9)
- PM_POP(0, ICPLB_DATA8)
- PM_POP_SYNC(13)
- PM_POP(13, ICPLB_DATA7)
- PM_POP(12, ICPLB_DATA6)
- PM_POP(11, ICPLB_DATA5)
- PM_POP(10, ICPLB_DATA4)
- PM_POP(9, ICPLB_DATA3)
- PM_POP(8, ICPLB_DATA2)
- PM_POP(7, ICPLB_DATA1)
- PM_POP(6, ICPLB_DATA0)
-
- /* ICPLB Addr */
- FP = I3;
- PM_POP(5, ICPLB_ADDR15)
- PM_POP(4, ICPLB_ADDR14)
- PM_POP(3, ICPLB_ADDR13)
- PM_POP(2, ICPLB_ADDR12)
- PM_POP(1, ICPLB_ADDR11)
- PM_POP(0, ICPLB_ADDR10)
- PM_POP_SYNC(13)
- PM_POP(13, ICPLB_ADDR9)
- PM_POP(12, ICPLB_ADDR8)
- PM_POP(11, ICPLB_ADDR7)
- PM_POP(10, ICPLB_ADDR6)
- PM_POP(9, ICPLB_ADDR5)
- PM_POP(8, ICPLB_ADDR4)
- PM_POP(7, ICPLB_ADDR3)
- PM_POP(6, ICPLB_ADDR2)
- PM_POP(5, ICPLB_ADDR1)
- PM_POP(4, ICPLB_ADDR0)
-
- /* DCPLB Data */
- FP = I2;
- PM_POP(3, DCPLB_DATA15)
- PM_POP(2, DCPLB_DATA14)
- PM_POP(1, DCPLB_DATA13)
- PM_POP(0, DCPLB_DATA12)
- PM_POP_SYNC(13)
- PM_POP(13, DCPLB_DATA11)
- PM_POP(12, DCPLB_DATA10)
- PM_POP(11, DCPLB_DATA9)
- PM_POP(10, DCPLB_DATA8)
- PM_POP(9, DCPLB_DATA7)
- PM_POP(8, DCPLB_DATA6)
- PM_POP(7, DCPLB_DATA5)
- PM_POP(6, DCPLB_DATA4)
- PM_POP(5, DCPLB_DATA3)
- PM_POP(4, DCPLB_DATA2)
- PM_POP(3, DCPLB_DATA1)
- PM_POP(2, DCPLB_DATA0)
-
- /* DCPLB Addr */
- FP = I1;
- PM_POP(1, DCPLB_ADDR15)
- PM_POP(0, DCPLB_ADDR14)
- PM_POP_SYNC(13)
- PM_POP(13, DCPLB_ADDR13)
- PM_POP(12, DCPLB_ADDR12)
- PM_POP(11, DCPLB_ADDR11)
- PM_POP(10, DCPLB_ADDR10)
- PM_POP(9, DCPLB_ADDR9)
- PM_POP(8, DCPLB_ADDR8)
- PM_POP(7, DCPLB_ADDR7)
- PM_POP(6, DCPLB_ADDR6)
- PM_POP(5, DCPLB_ADDR5)
- PM_POP(4, DCPLB_ADDR4)
- PM_POP(3, DCPLB_ADDR3)
- PM_POP(2, DCPLB_ADDR2)
- PM_POP(1, DCPLB_ADDR1)
- PM_POP(0, DCPLB_ADDR0)
-
-
- /* Misc non-contiguous registers */
-
- /* icache & dcache will enable later
- drop IMEM_CONTROL, DMEM_CONTROL pop
- */
- FP = I0;
- PM_POP_SYNC(2)
- PM_CORE_POP(2, TBUFCTL)
- PM_CORE_POP(1, IMEM_CONTROL)
- PM_CORE_POP(0, DMEM_CONTROL)
-
- /* Core Timer */
- FP = B3;
- R0 = 0x1;
- [FP - 0xC] = R0;
-
- PM_POP_SYNC(13)
- FP = B3;
- PM_POP(13, TCOUNT)
- PM_POP(12, TSCALE)
- PM_POP(11, TPERIOD)
- PM_POP(10, TCNTL)
-
- /* CEC */
- FP = B2;
- PM_POP(9, IPRIO)
- PM_POP(8, ILAT)
- FP += -4; /* IPEND */
- PM_POP(7, IMASK)
-
- /* Event Vectors */
- FP = B1;
- PM_POP(6, EVT15)
- PM_POP(5, EVT14)
- PM_POP(4, EVT13)
- PM_POP(3, EVT12)
- PM_POP(2, EVT11)
- PM_POP(1, EVT10)
- PM_POP(0, EVT9)
- PM_POP_SYNC(5)
- PM_POP(5, EVT8)
- PM_POP(4, EVT7)
- PM_POP(3, EVT6)
- PM_POP(2, EVT5)
- FP += -4; /* EVT4 */
- PM_POP(1, EVT3)
- PM_POP(0, EVT2)
- .endm
-#endif
-
-#include <mach/pll.h>
-
-/* PLL_CTL Masks */
-#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
-#define PLL_OFF 0x0002 /* PLL Not Powered */
-#define STOPCK 0x0008 /* Core Clock Off */
-#define PDWN 0x0020 /* Enter Deep Sleep Mode */
-#ifdef __ADSPBF539__
-# define IN_DELAY 0x0014 /* Add 200ps Delay To EBIU Input Latches */
-# define OUT_DELAY 0x00C0 /* Add 200ps Delay To EBIU Output Signals */
-#else
-# define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */
-# define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */
-#endif
-#define BYPASS 0x0100 /* Bypass the PLL */
-#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */
-#define SPORT_HYST 0x8000 /* Enable Additional Hysteresis on SPORT Input Pins */
-#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
-
-/* PLL_DIV Masks */
-#define SSEL 0x000F /* System Select */
-#define CSEL 0x0030 /* Core Select */
-#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */
-#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */
-#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */
-#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */
-
-#define CCLK_DIV1 CSEL_DIV1
-#define CCLK_DIV2 CSEL_DIV2
-#define CCLK_DIV4 CSEL_DIV4
-#define CCLK_DIV8 CSEL_DIV8
-
-#define SET_SSEL(x) ((x) & 0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
-#define SCLK_DIV(x) (x) /* SCLK = VCO / x */
-
-/* PLL_STAT Masks */
-#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
-#define FULL_ON 0x0002 /* Processor In Full On Mode */
-#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
-#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
-
-#define RTCWS 0x0400 /* RTC/Reset Wake-Up Status */
-#define CANWS 0x0800 /* CAN Wake-Up Status */
-#define USBWS 0x2000 /* USB Wake-Up Status */
-#define KPADWS 0x4000 /* Keypad Wake-Up Status */
-#define ROTWS 0x8000 /* Rotary Wake-Up Status */
-#define GPWS 0x1000 /* General-Purpose Wake-Up Status */
-
-/* VR_CTL Masks */
-#if defined(__ADSPBF52x__) || defined(__ADSPBF51x__)
-#define FREQ 0x3000 /* Switching Oscillator Frequency For Regulator */
-#define FREQ_1000 0x3000 /* Switching Frequency Is 1 MHz */
-#else
-#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */
-#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */
-#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */
-#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */
-#endif
-#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
-
-#define GAIN 0x000C /* Voltage Level Gain */
-#define GAIN_5 0x0000 /* GAIN = 5 */
-#define GAIN_10 0x0004 /* GAIN = 1 */
-#define GAIN_20 0x0008 /* GAIN = 2 */
-#define GAIN_50 0x000C /* GAIN = 5 */
-
-#define VLEV 0x00F0 /* Internal Voltage Level */
-#ifdef __ADSPBF52x__
-#define VLEV_085 0x0040 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
-#define VLEV_090 0x0050 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
-#define VLEV_095 0x0060 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
-#define VLEV_100 0x0070 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
-#define VLEV_105 0x0080 /* VLEV = 1.05 V (-5% - +10% Accuracy) */
-#define VLEV_110 0x0090 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
-#define VLEV_115 0x00A0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
-#define VLEV_120 0x00B0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
-#else
-#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
-#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
-#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
-#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
-#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */
-#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
-#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
-#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
-#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */
-#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */
-#endif
-
-#ifdef CONFIG_BF60x
-#define PA15WE 0x00000001 /* Allow Wake-Up from PA15 */
-#define PB15WE 0x00000002 /* Allow Wake-Up from PB15 */
-#define PC15WE 0x00000004 /* Allow Wake-Up from PC15 */
-#define PD06WE 0x00000008 /* Allow Wake-Up from PD06(ETH0_PHYINT) */
-#define PE12WE 0x00000010 /* Allow Wake-Up from PE12(ETH1_PHYINT, PUSH BUTTON) */
-#define PG04WE 0x00000020 /* Allow Wake-Up from PG04(CAN0_RX) */
-#define PG13WE 0x00000040 /* Allow Wake-Up from PG13 */
-#define USBWE 0x00000080 /* Allow Wake-Up from (USB) */
-#else
-#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
-#define CANWE 0x0200 /* Enable CAN Wakeup From Hibernate */
-#define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */
-#define GPWE 0x0400 /* General-Purpose Wake-Up Enable */
-#define MXVRWE 0x0400 /* Enable MXVR Wakeup From Hibernate */
-#define KPADWE 0x1000 /* Keypad Wake-Up Enable */
-#define ROTWE 0x2000 /* Rotary Wake-Up Enable */
-#define CLKBUFOE 0x4000 /* CLKIN Buffer Output Enable */
-#define SCKELOW 0x8000 /* Do Not Drive SCKE High During Reset After Hibernate */
-
-#if defined(__ADSPBF52x__) || defined(__ADSPBF51x__)
-#define USBWE 0x0200 /* Enable USB Wakeup From Hibernate */
-#else
-#define USBWE 0x0800 /* Enable USB Wakeup From Hibernate */
-#endif
-#endif
-
-#ifndef __ASSEMBLY__
-
-void sleep_mode(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
-void sleep_deeper(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
-void do_hibernate(int wakeup);
-void set_dram_srfs(void);
-void unset_dram_srfs(void);
-
-#define VRPAIR(vlev, freq) (((vlev) << 16) | ((freq) >> 16))
-
-#ifdef CONFIG_CPU_FREQ
-#define CPUFREQ_CPU 0
-#endif
-struct bfin_dpmc_platform_data {
- const unsigned int *tuple_tab;
- unsigned short tabsize;
- unsigned short vr_settling_time; /* in us */
-};
-
-#endif
-
-#endif /*_BLACKFIN_DPMC_H_*/
+++ /dev/null
-/*
- * function prototpyes for early printk
- *
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_EARLY_PRINTK_H__
-#define __ASM_EARLY_PRINTK_H__
-
-#ifdef CONFIG_EARLY_PRINTK
-/* For those that don't include it already */
-#include <linux/console.h>
-
-extern int setup_early_printk(char *);
-extern void enable_shadow_console(void);
-extern int shadow_console_enabled(void);
-extern void mark_shadow_error(void);
-extern void early_shadow_reg(unsigned long reg, unsigned int n);
-extern void early_shadow_write(struct console *con, const char *s,
- unsigned int n) __attribute__((nonnull(2)));
-#define early_shadow_puts(str) early_shadow_write(NULL, str, strlen(str))
-#define early_shadow_stamp() \
- do { \
- early_shadow_puts(__FILE__ " : " __stringify(__LINE__) " ["); \
- early_shadow_puts(__func__); \
- early_shadow_puts("]\n"); \
- } while (0)
-#else
-#define setup_early_printk(fmt) do { } while (0)
-#define enable_shadow_console(fmt) do { } while (0)
-#define early_shadow_stamp() do { } while (0)
-#endif /* CONFIG_EARLY_PRINTK */
-
-#endif /* __ASM_EARLY_PRINTK_H__ */
+++ /dev/null
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASMBFIN_ELF_H
-#define __ASMBFIN_ELF_H
-
-/*
- * ELF register definitions..
- */
-
-#include <asm/ptrace.h>
-#include <asm/user.h>
-
-/* Processor specific flags for the ELF header e_flags field. */
-#define EF_BFIN_PIC 0x00000001 /* -fpic */
-#define EF_BFIN_FDPIC 0x00000002 /* -mfdpic */
-#define EF_BFIN_CODE_IN_L1 0x00000010 /* --code-in-l1 */
-#define EF_BFIN_DATA_IN_L1 0x00000020 /* --data-in-l1 */
-#define EF_BFIN_CODE_IN_L2 0x00000040 /* --code-in-l2 */
-#define EF_BFIN_DATA_IN_L2 0x00000080 /* --data-in-l2 */
-
-#if 1 /* core dumps not supported, but linux/elfcore.h needs these */
-typedef unsigned long elf_greg_t;
-
-#define ELF_NGREG (sizeof(struct pt_regs) / sizeof(elf_greg_t))
-typedef elf_greg_t elf_gregset_t[ELF_NGREG];
-
-typedef struct { } elf_fpregset_t;
-#endif
-
-/*
- * This is used to ensure we don't load something for the wrong architecture.
- */
-#define elf_check_arch(x) ((x)->e_machine == EM_BLACKFIN)
-
-#define elf_check_fdpic(x) ((x)->e_flags & EF_BFIN_FDPIC /* && !((x)->e_flags & EF_FRV_NON_PIC_RELOCS) */)
-#define elf_check_const_displacement(x) ((x)->e_flags & EF_BFIN_PIC)
-
-/* EM_BLACKFIN defined in linux/elf.h */
-
-/*
- * These are used to set parameters in the core dumps.
- */
-#define ELF_CLASS ELFCLASS32
-#define ELF_DATA ELFDATA2LSB
-#define ELF_ARCH EM_BLACKFIN
-
-#define ELF_PLAT_INIT(_r) _r->p1 = 0
-
-#define ELF_FDPIC_PLAT_INIT(_regs, _exec_map_addr, _interp_map_addr, _dynamic_addr) \
-do { \
- _regs->r7 = 0; \
- _regs->p0 = _exec_map_addr; \
- _regs->p1 = _interp_map_addr; \
- _regs->p2 = _dynamic_addr; \
-} while(0)
-
-#if 0
-#define CORE_DUMP_USE_REGSET
-#endif
-#define ELF_FDPIC_CORE_EFLAGS EF_BFIN_FDPIC
-#define ELF_EXEC_PAGESIZE 4096
-
-#define R_BFIN_UNUSED0 0 /* relocation type 0 is not defined */
-#define R_BFIN_PCREL5M2 1 /* LSETUP part a */
-#define R_BFIN_UNUSED1 2 /* relocation type 2 is not defined */
-#define R_BFIN_PCREL10 3 /* type 3, if cc jump <target> */
-#define R_BFIN_PCREL12_JUMP 4 /* type 4, jump <target> */
-#define R_BFIN_RIMM16 5 /* type 0x5, rN = <target> */
-#define R_BFIN_LUIMM16 6 /* # 0x6, preg.l=<target> Load imm 16 to lower half */
-#define R_BFIN_HUIMM16 7 /* # 0x7, preg.h=<target> Load imm 16 to upper half */
-#define R_BFIN_PCREL12_JUMP_S 8 /* # 0x8 jump.s <target> */
-#define R_BFIN_PCREL24_JUMP_X 9 /* # 0x9 jump.x <target> */
-#define R_BFIN_PCREL24 10 /* # 0xa call <target> , not expandable */
-#define R_BFIN_UNUSEDB 11 /* # 0xb not generated */
-#define R_BFIN_UNUSEDC 12 /* # 0xc not used */
-#define R_BFIN_PCREL24_JUMP_L 13 /* 0xd jump.l <target> */
-#define R_BFIN_PCREL24_CALL_X 14 /* 0xE, call.x <target> if <target> is above 24 bit limit call through P1 */
-#define R_BFIN_VAR_EQ_SYMB 15 /* 0xf, linker should treat it same as 0x12 */
-#define R_BFIN_BYTE_DATA 16 /* 0x10, .byte var = symbol */
-#define R_BFIN_BYTE2_DATA 17 /* 0x11, .byte2 var = symbol */
-#define R_BFIN_BYTE4_DATA 18 /* 0x12, .byte4 var = symbol and .var var=symbol */
-#define R_BFIN_PCREL11 19 /* 0x13, lsetup part b */
-#define R_BFIN_UNUSED14 20 /* 0x14, undefined */
-#define R_BFIN_UNUSED15 21 /* not generated by VDSP 3.5 */
-
-/* arithmetic relocations */
-#define R_BFIN_PUSH 0xE0
-#define R_BFIN_CONST 0xE1
-#define R_BFIN_ADD 0xE2
-#define R_BFIN_SUB 0xE3
-#define R_BFIN_MULT 0xE4
-#define R_BFIN_DIV 0xE5
-#define R_BFIN_MOD 0xE6
-#define R_BFIN_LSHIFT 0xE7
-#define R_BFIN_RSHIFT 0xE8
-#define R_BFIN_AND 0xE9
-#define R_BFIN_OR 0xEA
-#define R_BFIN_XOR 0xEB
-#define R_BFIN_LAND 0xEC
-#define R_BFIN_LOR 0xED
-#define R_BFIN_LEN 0xEE
-#define R_BFIN_NEG 0xEF
-#define R_BFIN_COMP 0xF0
-#define R_BFIN_PAGE 0xF1
-#define R_BFIN_HWPAGE 0xF2
-#define R_BFIN_ADDR 0xF3
-
-/* This is the location that an ET_DYN program is loaded if exec'ed. Typical
- use of this is to invoke "./ld.so someprog" to test out a new version of
- the loader. We need to make sure that it is out of the way of the program
- that it will "exec", and that there is sufficient room for the brk. */
-
-#define ELF_ET_DYN_BASE 0xD0000000UL
-
-#define ELF_CORE_COPY_REGS(pr_reg, regs) \
- memcpy((char *) &pr_reg, (char *)regs, \
- sizeof(struct pt_regs));
-#define ELF_CORE_COPY_FPREGS(...) 0 /* Blackfin has no FPU */
-
-/* This yields a mask that user programs can use to figure out what
- instruction set this cpu supports. */
-
-#define ELF_HWCAP (0)
-
-/* This yields a string that ld.so will use to load implementation
- specific libraries for optimization. This is more specific in
- intent than poking at uname or /proc/cpuinfo. */
-
-#define ELF_PLATFORM (NULL)
-
-#endif
+++ /dev/null
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_ENTRY_H
-#define __BFIN_ENTRY_H
-
-#include <asm/setup.h>
-#include <asm/page.h>
-
-#ifdef __ASSEMBLY__
-
-#define LFLUSH_I_AND_D 0x00000808
-#define LSIGTRAP 5
-
-/*
- * NOTE! The single-stepping code assumes that all interrupt handlers
- * start by saving SYSCFG on the stack with their first instruction.
- */
-
-/* This one is used for exceptions, emulation, and NMI. It doesn't push
- RETI and doesn't do cli. */
-#define SAVE_ALL_SYS save_context_no_interrupts
-/* This is used for all normal interrupts. It saves a minimum of registers
- to the stack, loads the IRQ number, and jumps to common code. */
-#ifdef CONFIG_IPIPE
-# define LOAD_IPIPE_IPEND \
- P0.l = lo(IPEND); \
- P0.h = hi(IPEND); \
- R1 = [P0];
-#else
-# define LOAD_IPIPE_IPEND
-#endif
-
-/*
- * Workaround for anomalies 05000283 and 05000315
- */
-#if ANOMALY_05000283 || ANOMALY_05000315
-# define ANOMALY_283_315_WORKAROUND(preg, dreg) \
- cc = dreg == dreg; \
- preg.h = HI(CHIPID); \
- preg.l = LO(CHIPID); \
- if cc jump 1f; \
- dreg.l = W[preg]; \
-1:
-#else
-# define ANOMALY_283_315_WORKAROUND(preg, dreg)
-#endif /* ANOMALY_05000283 || ANOMALY_05000315 */
-
-#ifndef CONFIG_EXACT_HWERR
-/* As a debugging aid - we save IPEND when DEBUG_KERNEL is on,
- * otherwise it is a waste of cycles.
- */
-# ifndef CONFIG_DEBUG_KERNEL
-#define INTERRUPT_ENTRY(N) \
- [--sp] = SYSCFG; \
- [--sp] = P0; /*orig_p0*/ \
- [--sp] = R0; /*orig_r0*/ \
- [--sp] = (R7:0,P5:0); \
- R0 = (N); \
- LOAD_IPIPE_IPEND \
- jump __common_int_entry;
-# else /* CONFIG_DEBUG_KERNEL */
-#define INTERRUPT_ENTRY(N) \
- [--sp] = SYSCFG; \
- [--sp] = P0; /*orig_p0*/ \
- [--sp] = R0; /*orig_r0*/ \
- [--sp] = (R7:0,P5:0); \
- p0.l = lo(IPEND); \
- p0.h = hi(IPEND); \
- r1 = [p0]; \
- R0 = (N); \
- LOAD_IPIPE_IPEND \
- jump __common_int_entry;
-# endif /* CONFIG_DEBUG_KERNEL */
-
-/* For timer interrupts, we need to save IPEND, since the user_mode
- *macro accesses it to determine where to account time.
- */
-#define TIMER_INTERRUPT_ENTRY(N) \
- [--sp] = SYSCFG; \
- [--sp] = P0; /*orig_p0*/ \
- [--sp] = R0; /*orig_r0*/ \
- [--sp] = (R7:0,P5:0); \
- p0.l = lo(IPEND); \
- p0.h = hi(IPEND); \
- r1 = [p0]; \
- R0 = (N); \
- jump __common_int_entry;
-#else /* CONFIG_EXACT_HWERR is defined */
-
-/* if we want hardware error to be exact, we need to do a SSYNC (which forces
- * read/writes to complete to the memory controllers), and check to see that
- * caused a pending HW error condition. If so, we assume it was caused by user
- * space, by setting the same interrupt that we are in (so it goes off again)
- * and context restore, and a RTI (without servicing anything). This should
- * cause the pending HWERR to fire, and when that is done, this interrupt will
- * be re-serviced properly.
- * As you can see by the code - we actually need to do two SSYNCS - one to
- * make sure the read/writes complete, and another to make sure the hardware
- * error is recognized by the core.
- *
- * The extra nop before the SSYNC is to make sure we work around 05000244,
- * since the 283/315 workaround includes a branch to the end
- */
-#define INTERRUPT_ENTRY(N) \
- [--sp] = SYSCFG; \
- [--sp] = P0; /*orig_p0*/ \
- [--sp] = R0; /*orig_r0*/ \
- [--sp] = (R7:0,P5:0); \
- R1 = ASTAT; \
- ANOMALY_283_315_WORKAROUND(p0, r0) \
- P0.L = LO(ILAT); \
- P0.H = HI(ILAT); \
- NOP; \
- SSYNC; \
- SSYNC; \
- R0 = [P0]; \
- CC = BITTST(R0, EVT_IVHW_P); \
- IF CC JUMP 1f; \
- ASTAT = R1; \
- p0.l = lo(IPEND); \
- p0.h = hi(IPEND); \
- r1 = [p0]; \
- R0 = (N); \
- LOAD_IPIPE_IPEND \
- jump __common_int_entry; \
-1: ASTAT = R1; \
- RAISE N; \
- (R7:0, P5:0) = [SP++]; \
- SP += 0x8; \
- SYSCFG = [SP++]; \
- CSYNC; \
- RTI;
-
-#define TIMER_INTERRUPT_ENTRY(N) \
- [--sp] = SYSCFG; \
- [--sp] = P0; /*orig_p0*/ \
- [--sp] = R0; /*orig_r0*/ \
- [--sp] = (R7:0,P5:0); \
- R1 = ASTAT; \
- ANOMALY_283_315_WORKAROUND(p0, r0) \
- P0.L = LO(ILAT); \
- P0.H = HI(ILAT); \
- NOP; \
- SSYNC; \
- SSYNC; \
- R0 = [P0]; \
- CC = BITTST(R0, EVT_IVHW_P); \
- IF CC JUMP 1f; \
- ASTAT = R1; \
- p0.l = lo(IPEND); \
- p0.h = hi(IPEND); \
- r1 = [p0]; \
- R0 = (N); \
- jump __common_int_entry; \
-1: ASTAT = R1; \
- RAISE N; \
- (R7:0, P5:0) = [SP++]; \
- SP += 0x8; \
- SYSCFG = [SP++]; \
- CSYNC; \
- RTI;
-#endif /* CONFIG_EXACT_HWERR */
-
-/* This one pushes RETI without using CLI. Interrupts are enabled. */
-#define SAVE_CONTEXT_SYSCALL save_context_syscall
-#define SAVE_CONTEXT save_context_with_interrupts
-#define SAVE_CONTEXT_CPLB save_context_cplb
-
-#define RESTORE_ALL_SYS restore_context_no_interrupts
-#define RESTORE_CONTEXT restore_context_with_interrupts
-#define RESTORE_CONTEXT_CPLB restore_context_cplb
-
-#endif /* __ASSEMBLY__ */
-#endif /* __BFIN_ENTRY_H */
+++ /dev/null
-/* define arch_align_stack() here */
+++ /dev/null
-/*
- * This file defines the fixed addresses where userspace programs
- * can find atomic code sequences.
- *
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-#ifndef __BFIN_ASM_FIXED_CODE_H__
-#define __BFIN_ASM_FIXED_CODE_H__
-
-#include <uapi/asm/fixed_code.h>
-
-#ifndef __ASSEMBLY__
-#include <linux/linkage.h>
-#include <linux/ptrace.h>
-extern asmlinkage void finish_atomic_sections(struct pt_regs *regs);
-extern char fixed_code_start;
-extern char fixed_code_end;
-extern int atomic_xchg32(void);
-extern int atomic_cas32(void);
-extern int atomic_add32(void);
-extern int atomic_sub32(void);
-extern int atomic_ior32(void);
-extern int atomic_and32(void);
-extern int atomic_xor32(void);
-extern void safe_user_instruction(void);
-extern void sigreturn_stub(void);
-#endif
-#endif
+++ /dev/null
-/*
- * uClinux flat-format executables
- *
- * Copyright 2003-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2
- */
-
-#ifndef __BLACKFIN_FLAT_H__
-#define __BLACKFIN_FLAT_H__
-
-#include <asm/unaligned.h>
-
-#define flat_argvp_envp_on_stack() 0
-#define flat_old_ram_flag(flags) (flags)
-
-extern unsigned long bfin_get_addr_from_rp (u32 *ptr, u32 relval,
- u32 flags, u32 *persistent);
-
-extern void bfin_put_addr_at_rp(u32 *ptr, u32 addr, u32 relval);
-
-/* The amount by which a relocation can exceed the program image limits
- without being regarded as an error. */
-
-#define flat_reloc_valid(reloc, size) ((reloc) <= (size))
-
-static inline int flat_get_addr_from_rp(u32 __user *rp, u32 relval, u32 flags,
- u32 *addr, u32 *persistent)
-{
- *addr = bfin_get_addr_from_rp(rp, relval, flags, persistent);
- return 0;
-}
-
-static inline int flat_put_addr_at_rp(u32 __user *rp, u32 val, u32 relval)
-{
- bfin_put_addr_at_rp(rp, val, relval);
- return 0;
-}
-
-/* Convert a relocation entry into an address. */
-static inline unsigned long
-flat_get_relocate_addr (unsigned long relval)
-{
- return relval & 0x03ffffff; /* Mask out top 6 bits */
-}
-
-static inline int flat_set_persistent(u32 relval, u32 *persistent)
-{
- int type = (relval >> 26) & 7;
- if (type == 3) {
- *persistent = relval << 16;
- return 1;
- }
- return 0;
-}
-
-static inline int flat_addr_absolute(unsigned long relval)
-{
- return (relval & (1 << 29)) != 0;
-}
-
-#endif /* __BLACKFIN_FLAT_H__ */
+++ /dev/null
-/*
- * Blackfin ftrace code
- *
- * Copyright 2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_BFIN_FTRACE_H__
-#define __ASM_BFIN_FTRACE_H__
-
-#define MCOUNT_INSN_SIZE 6 /* sizeof "[++sp] = rets; call __mcount;" */
-
-#ifndef __ASSEMBLY__
-
-#ifdef CONFIG_DYNAMIC_FTRACE
-
-extern void _mcount(void);
-#define MCOUNT_ADDR ((unsigned long)_mcount)
-
-static inline unsigned long ftrace_call_adjust(unsigned long addr)
-{
- return addr;
-}
-
-struct dyn_arch_ftrace {
- /* No extra data needed for Blackfin */
-};
-
-#endif
-
-#ifdef CONFIG_FRAME_POINTER
-#include <linux/mm.h>
-
-extern inline void *return_address(unsigned int level)
-{
- unsigned long *endstack, *fp, *ret_addr;
- unsigned int current_level = 0;
-
- if (level == 0)
- return __builtin_return_address(0);
-
- fp = (unsigned long *)__builtin_frame_address(0);
- endstack = (unsigned long *)PAGE_ALIGN((unsigned long)&level);
-
- while (((unsigned long)fp & 0x3) == 0 && fp &&
- (fp + 1) < endstack && current_level < level) {
- fp = (unsigned long *)*fp;
- current_level++;
- }
-
- if (((unsigned long)fp & 0x3) == 0 && fp &&
- (fp + 1) < endstack)
- ret_addr = (unsigned long *)*(fp + 1);
- else
- ret_addr = NULL;
-
- return ret_addr;
-}
-
-#else
-
-extern inline void *return_address(unsigned int level)
-{
- return NULL;
-}
-
-#endif /* CONFIG_FRAME_POINTER */
-
-#define ftrace_return_address(n) return_address(n)
-
-#endif /* __ASSEMBLY__ */
-
-#endif
+++ /dev/null
-/*
- * Copyright 2006-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ARCH_BLACKFIN_GPIO_H__
-#define __ARCH_BLACKFIN_GPIO_H__
-
-#define gpio_bank(x) ((x) >> 4)
-#define gpio_bit(x) (1<<((x) & 0xF))
-#define gpio_sub_n(x) ((x) & 0xF)
-
-#define GPIO_BANKSIZE 16
-#define GPIO_BANK_NUM DIV_ROUND_UP(MAX_BLACKFIN_GPIOS, GPIO_BANKSIZE)
-
-#include <mach/gpio.h>
-
-#define PERIPHERAL_USAGE 1
-#define GPIO_USAGE 0
-
-#ifndef BFIN_GPIO_PINT
-# define BFIN_GPIO_PINT 0
-#endif
-
-#ifndef __ASSEMBLY__
-
-#ifndef CONFIG_PINCTRL
-
-#include <linux/compiler.h>
-#include <asm/blackfin.h>
-#include <asm/portmux.h>
-#include <asm/irq_handler.h>
-
-/***********************************************************
-*
-* FUNCTIONS: Blackfin General Purpose Ports Access Functions
-*
-* INPUTS/OUTPUTS:
-* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS
-*
-*
-* DESCRIPTION: These functions abstract direct register access
-* to Blackfin processor General Purpose
-* Ports Regsiters
-*
-* CAUTION: These functions do not belong to the GPIO Driver API
-*************************************************************
-* MODIFICATION HISTORY :
-**************************************************************/
-
-void set_gpio_dir(unsigned, unsigned short);
-void set_gpio_inen(unsigned, unsigned short);
-void set_gpio_polar(unsigned, unsigned short);
-void set_gpio_edge(unsigned, unsigned short);
-void set_gpio_both(unsigned, unsigned short);
-void set_gpio_data(unsigned, unsigned short);
-void set_gpio_maska(unsigned, unsigned short);
-void set_gpio_maskb(unsigned, unsigned short);
-void set_gpio_toggle(unsigned);
-void set_gpiop_dir(unsigned, unsigned short);
-void set_gpiop_inen(unsigned, unsigned short);
-void set_gpiop_polar(unsigned, unsigned short);
-void set_gpiop_edge(unsigned, unsigned short);
-void set_gpiop_both(unsigned, unsigned short);
-void set_gpiop_data(unsigned, unsigned short);
-void set_gpiop_maska(unsigned, unsigned short);
-void set_gpiop_maskb(unsigned, unsigned short);
-unsigned short get_gpio_dir(unsigned);
-unsigned short get_gpio_inen(unsigned);
-unsigned short get_gpio_polar(unsigned);
-unsigned short get_gpio_edge(unsigned);
-unsigned short get_gpio_both(unsigned);
-unsigned short get_gpio_maska(unsigned);
-unsigned short get_gpio_maskb(unsigned);
-unsigned short get_gpio_data(unsigned);
-unsigned short get_gpiop_dir(unsigned);
-unsigned short get_gpiop_inen(unsigned);
-unsigned short get_gpiop_polar(unsigned);
-unsigned short get_gpiop_edge(unsigned);
-unsigned short get_gpiop_both(unsigned);
-unsigned short get_gpiop_maska(unsigned);
-unsigned short get_gpiop_maskb(unsigned);
-unsigned short get_gpiop_data(unsigned);
-
-struct gpio_port_t {
- unsigned short data;
- unsigned short dummy1;
- unsigned short data_clear;
- unsigned short dummy2;
- unsigned short data_set;
- unsigned short dummy3;
- unsigned short toggle;
- unsigned short dummy4;
- unsigned short maska;
- unsigned short dummy5;
- unsigned short maska_clear;
- unsigned short dummy6;
- unsigned short maska_set;
- unsigned short dummy7;
- unsigned short maska_toggle;
- unsigned short dummy8;
- unsigned short maskb;
- unsigned short dummy9;
- unsigned short maskb_clear;
- unsigned short dummy10;
- unsigned short maskb_set;
- unsigned short dummy11;
- unsigned short maskb_toggle;
- unsigned short dummy12;
- unsigned short dir;
- unsigned short dummy13;
- unsigned short polar;
- unsigned short dummy14;
- unsigned short edge;
- unsigned short dummy15;
- unsigned short both;
- unsigned short dummy16;
- unsigned short inen;
-};
-
-#ifdef BFIN_SPECIAL_GPIO_BANKS
-void bfin_special_gpio_free(unsigned gpio);
-int bfin_special_gpio_request(unsigned gpio, const char *label);
-# ifdef CONFIG_PM
-void bfin_special_gpio_pm_hibernate_restore(void);
-void bfin_special_gpio_pm_hibernate_suspend(void);
-# endif
-#endif
-
-#ifdef CONFIG_PM
-void bfin_gpio_pm_hibernate_restore(void);
-void bfin_gpio_pm_hibernate_suspend(void);
-int bfin_gpio_pm_wakeup_ctrl(unsigned gpio, unsigned ctrl);
-int bfin_gpio_pm_standby_ctrl(unsigned ctrl);
-
-static inline int bfin_pm_standby_setup(void)
-{
- return bfin_gpio_pm_standby_ctrl(1);
-}
-
-static inline void bfin_pm_standby_restore(void)
-{
- bfin_gpio_pm_standby_ctrl(0);
-}
-
-
-struct gpio_port_s {
- unsigned short data;
- unsigned short maska;
- unsigned short maskb;
- unsigned short dir;
- unsigned short polar;
- unsigned short edge;
- unsigned short both;
- unsigned short inen;
-
- unsigned short fer;
- unsigned short reserved;
- unsigned short mux;
-};
-#endif /*CONFIG_PM*/
-
-/***********************************************************
-*
-* FUNCTIONS: Blackfin GPIO Driver
-*
-* INPUTS/OUTPUTS:
-* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS
-*
-*
-* DESCRIPTION: Blackfin GPIO Driver API
-*
-* CAUTION:
-*************************************************************
-* MODIFICATION HISTORY :
-**************************************************************/
-int bfin_gpio_irq_request(unsigned gpio, const char *label);
-void bfin_gpio_irq_free(unsigned gpio);
-void bfin_gpio_irq_prepare(unsigned gpio);
-
-static inline int irq_to_gpio(unsigned irq)
-{
- return irq - GPIO_IRQ_BASE;
-}
-
-#else /* CONFIG_PINCTRL */
-
-/*
- * CONFIG_PM is not working with pin control and should probably
- * avoid being selected when pin control is active, but so far,
- * these stubs are here to make allyesconfig and allmodconfig
- * compile properly. These functions are normally backed by the
- * CONFIG_ADI_GPIO custom GPIO implementation.
- */
-
-static inline int bfin_pm_standby_setup(void)
-{
- return 0;
-}
-
-static inline void bfin_pm_standby_restore(void)
-{
-}
-
-#endif /* CONFIG_PINCTRL */
-
-#include <asm/irq.h>
-#include <asm/errno.h>
-
-#include <asm-generic/gpio.h> /* cansleep wrappers */
-
-static inline int gpio_get_value(unsigned int gpio)
-{
- return __gpio_get_value(gpio);
-}
-
-static inline void gpio_set_value(unsigned int gpio, int value)
-{
- __gpio_set_value(gpio, value);
-}
-
-static inline int gpio_cansleep(unsigned int gpio)
-{
- return __gpio_cansleep(gpio);
-}
-
-static inline int gpio_to_irq(unsigned gpio)
-{
- return __gpio_to_irq(gpio);
-}
-#endif /* __ASSEMBLY__ */
-
-#endif /* __ARCH_BLACKFIN_GPIO_H__ */
+++ /dev/null
-/*
- * gptimers.h - Blackfin General Purpose Timer structs/defines/prototypes
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- * Copyright (C) 2005 John DeHority
- * Copyright (C) 2006 Hella Aglaia GmbH (awe@aglaia-gmbh.de)
- *
- * Licensed under the GPL-2.
- */
-
-#ifndef _BLACKFIN_TIMERS_H_
-#define _BLACKFIN_TIMERS_H_
-
-#include <linux/types.h>
-#include <asm/blackfin.h>
-
-/*
- * BF51x/BF52x/BF537: 8 timers:
- */
-#if defined(CONFIG_BF51x) || defined(CONFIG_BF52x) || defined(BF537_FAMILY)
-# define MAX_BLACKFIN_GPTIMERS 8
-# define TIMER0_GROUP_REG TIMER_ENABLE
-#endif
-/*
- * BF54x: 11 timers (BF542: 8 timers):
- */
-#if defined(CONFIG_BF54x)
-# ifdef CONFIG_BF542
-# define MAX_BLACKFIN_GPTIMERS 8
-# else
-# define MAX_BLACKFIN_GPTIMERS 11
-# define TIMER8_GROUP_REG TIMER_ENABLE1
-# define TIMER_GROUP2 1
-# endif
-# define TIMER0_GROUP_REG TIMER_ENABLE0
-#endif
-/*
- * BF561: 12 timers:
- */
-#if defined(CONFIG_BF561)
-# define MAX_BLACKFIN_GPTIMERS 12
-# define TIMER0_GROUP_REG TMRS8_ENABLE
-# define TIMER8_GROUP_REG TMRS4_ENABLE
-# define TIMER_GROUP2 1
-#endif
-/*
- * BF609: 8 timers:
- */
-#if defined(CONFIG_BF60x)
-# define MAX_BLACKFIN_GPTIMERS 8
-# define TIMER0_GROUP_REG TIMER_RUN
-#endif
-/*
- * All others: 3 timers:
- */
-#define TIMER_GROUP1 0
-#if !defined(MAX_BLACKFIN_GPTIMERS)
-# define MAX_BLACKFIN_GPTIMERS 3
-# define TIMER0_GROUP_REG TIMER_ENABLE
-#endif
-
-#define BLACKFIN_GPTIMER_IDMASK ((1UL << MAX_BLACKFIN_GPTIMERS) - 1)
-#define BFIN_TIMER_OCTET(x) ((x) >> 3)
-
-/* used in masks for timer_enable() and timer_disable() */
-#define TIMER0bit 0x0001 /* 0001b */
-#define TIMER1bit 0x0002 /* 0010b */
-#define TIMER2bit 0x0004 /* 0100b */
-#define TIMER3bit 0x0008
-#define TIMER4bit 0x0010
-#define TIMER5bit 0x0020
-#define TIMER6bit 0x0040
-#define TIMER7bit 0x0080
-#define TIMER8bit 0x0100
-#define TIMER9bit 0x0200
-#define TIMER10bit 0x0400
-#define TIMER11bit 0x0800
-
-#define TIMER0_id 0
-#define TIMER1_id 1
-#define TIMER2_id 2
-#define TIMER3_id 3
-#define TIMER4_id 4
-#define TIMER5_id 5
-#define TIMER6_id 6
-#define TIMER7_id 7
-#define TIMER8_id 8
-#define TIMER9_id 9
-#define TIMER10_id 10
-#define TIMER11_id 11
-
-/* associated timers for ppi framesync: */
-
-#if defined(CONFIG_BF561)
-# define FS0_1_TIMER_ID TIMER8_id
-# define FS0_2_TIMER_ID TIMER9_id
-# define FS1_1_TIMER_ID TIMER10_id
-# define FS1_2_TIMER_ID TIMER11_id
-# define FS0_1_TIMER_BIT TIMER8bit
-# define FS0_2_TIMER_BIT TIMER9bit
-# define FS1_1_TIMER_BIT TIMER10bit
-# define FS1_2_TIMER_BIT TIMER11bit
-# undef FS1_TIMER_ID
-# undef FS2_TIMER_ID
-# undef FS1_TIMER_BIT
-# undef FS2_TIMER_BIT
-#else
-# define FS1_TIMER_ID TIMER0_id
-# define FS2_TIMER_ID TIMER1_id
-# define FS1_TIMER_BIT TIMER0bit
-# define FS2_TIMER_BIT TIMER1bit
-#endif
-
-#ifdef CONFIG_BF60x
-/*
- * Timer Configuration Register Bits
- */
-#define TIMER_EMU_RUN 0x8000
-#define TIMER_BPER_EN 0x4000
-#define TIMER_BWID_EN 0x2000
-#define TIMER_BDLY_EN 0x1000
-#define TIMER_OUT_DIS 0x0800
-#define TIMER_TIN_SEL 0x0400
-#define TIMER_CLK_SEL 0x0300
-#define TIMER_CLK_SCLK 0x0000
-#define TIMER_CLK_ALT_CLK0 0x0100
-#define TIMER_CLK_ALT_CLK1 0x0300
-#define TIMER_PULSE_HI 0x0080
-#define TIMER_SLAVE_TRIG 0x0040
-#define TIMER_IRQ_MODE 0x0030
-#define TIMER_IRQ_ACT_EDGE 0x0000
-#define TIMER_IRQ_DLY 0x0010
-#define TIMER_IRQ_WID_DLY 0x0020
-#define TIMER_IRQ_PER 0x0030
-#define TIMER_MODE 0x000f
-#define TIMER_MODE_WDOG_P 0x0008
-#define TIMER_MODE_WDOG_W 0x0009
-#define TIMER_MODE_PWM_CONT 0x000c
-#define TIMER_MODE_PWM 0x000d
-#define TIMER_MODE_WDTH 0x000a
-#define TIMER_MODE_WDTH_D 0x000b
-#define TIMER_MODE_EXT_CLK 0x000e
-#define TIMER_MODE_PININT 0x000f
-
-/*
- * Timer Status Register Bits
- */
-#define TIMER_STATUS_TIMIL0 0x0001
-#define TIMER_STATUS_TIMIL1 0x0002
-#define TIMER_STATUS_TIMIL2 0x0004
-#define TIMER_STATUS_TIMIL3 0x0008
-#define TIMER_STATUS_TIMIL4 0x0010
-#define TIMER_STATUS_TIMIL5 0x0020
-#define TIMER_STATUS_TIMIL6 0x0040
-#define TIMER_STATUS_TIMIL7 0x0080
-
-#define TIMER_STATUS_TOVF0 0x0001 /* timer 0 overflow error */
-#define TIMER_STATUS_TOVF1 0x0002
-#define TIMER_STATUS_TOVF2 0x0004
-#define TIMER_STATUS_TOVF3 0x0008
-#define TIMER_STATUS_TOVF4 0x0010
-#define TIMER_STATUS_TOVF5 0x0020
-#define TIMER_STATUS_TOVF6 0x0040
-#define TIMER_STATUS_TOVF7 0x0080
-
-/*
- * Timer Slave Enable Status : write 1 to clear
- */
-#define TIMER_STATUS_TRUN0 0x0001
-#define TIMER_STATUS_TRUN1 0x0002
-#define TIMER_STATUS_TRUN2 0x0004
-#define TIMER_STATUS_TRUN3 0x0008
-#define TIMER_STATUS_TRUN4 0x0010
-#define TIMER_STATUS_TRUN5 0x0020
-#define TIMER_STATUS_TRUN6 0x0040
-#define TIMER_STATUS_TRUN7 0x0080
-
-#else
-
-/*
- * Timer Configuration Register Bits
- */
-#define TIMER_ERR 0xC000
-#define TIMER_ERR_OVFL 0x4000
-#define TIMER_ERR_PROG_PER 0x8000
-#define TIMER_ERR_PROG_PW 0xC000
-#define TIMER_EMU_RUN 0x0200
-#define TIMER_TOGGLE_HI 0x0100
-#define TIMER_CLK_SEL 0x0080
-#define TIMER_OUT_DIS 0x0040
-#define TIMER_TIN_SEL 0x0020
-#define TIMER_IRQ_ENA 0x0010
-#define TIMER_PERIOD_CNT 0x0008
-#define TIMER_PULSE_HI 0x0004
-#define TIMER_MODE 0x0003
-#define TIMER_MODE_PWM 0x0001
-#define TIMER_MODE_WDTH 0x0002
-#define TIMER_MODE_EXT_CLK 0x0003
-
-/*
- * Timer Status Register Bits
- */
-#define TIMER_STATUS_TIMIL0 0x0001
-#define TIMER_STATUS_TIMIL1 0x0002
-#define TIMER_STATUS_TIMIL2 0x0004
-#define TIMER_STATUS_TIMIL3 0x00000008
-#define TIMER_STATUS_TIMIL4 0x00010000
-#define TIMER_STATUS_TIMIL5 0x00020000
-#define TIMER_STATUS_TIMIL6 0x00040000
-#define TIMER_STATUS_TIMIL7 0x00080000
-#define TIMER_STATUS_TIMIL8 0x0001
-#define TIMER_STATUS_TIMIL9 0x0002
-#define TIMER_STATUS_TIMIL10 0x0004
-#define TIMER_STATUS_TIMIL11 0x0008
-
-#define TIMER_STATUS_TOVF0 0x0010 /* timer 0 overflow error */
-#define TIMER_STATUS_TOVF1 0x0020
-#define TIMER_STATUS_TOVF2 0x0040
-#define TIMER_STATUS_TOVF3 0x00000080
-#define TIMER_STATUS_TOVF4 0x00100000
-#define TIMER_STATUS_TOVF5 0x00200000
-#define TIMER_STATUS_TOVF6 0x00400000
-#define TIMER_STATUS_TOVF7 0x00800000
-#define TIMER_STATUS_TOVF8 0x0010
-#define TIMER_STATUS_TOVF9 0x0020
-#define TIMER_STATUS_TOVF10 0x0040
-#define TIMER_STATUS_TOVF11 0x0080
-
-/*
- * Timer Slave Enable Status : write 1 to clear
- */
-#define TIMER_STATUS_TRUN0 0x1000
-#define TIMER_STATUS_TRUN1 0x2000
-#define TIMER_STATUS_TRUN2 0x4000
-#define TIMER_STATUS_TRUN3 0x00008000
-#define TIMER_STATUS_TRUN4 0x10000000
-#define TIMER_STATUS_TRUN5 0x20000000
-#define TIMER_STATUS_TRUN6 0x40000000
-#define TIMER_STATUS_TRUN7 0x80000000
-#define TIMER_STATUS_TRUN 0xF000F000
-#define TIMER_STATUS_TRUN8 0x1000
-#define TIMER_STATUS_TRUN9 0x2000
-#define TIMER_STATUS_TRUN10 0x4000
-#define TIMER_STATUS_TRUN11 0x8000
-
-#endif
-
-/* The actual gptimer API */
-
-void set_gptimer_pwidth(unsigned int timer_id, uint32_t width);
-uint32_t get_gptimer_pwidth(unsigned int timer_id);
-void set_gptimer_period(unsigned int timer_id, uint32_t period);
-uint32_t get_gptimer_period(unsigned int timer_id);
-#ifdef CONFIG_BF60x
-void set_gptimer_delay(unsigned int timer_id, uint32_t delay);
-uint32_t get_gptimer_delay(unsigned int timer_id);
-#endif
-uint32_t get_gptimer_count(unsigned int timer_id);
-int get_gptimer_intr(unsigned int timer_id);
-void clear_gptimer_intr(unsigned int timer_id);
-int get_gptimer_over(unsigned int timer_id);
-void clear_gptimer_over(unsigned int timer_id);
-void set_gptimer_config(unsigned int timer_id, uint16_t config);
-uint16_t get_gptimer_config(unsigned int timer_id);
-int get_gptimer_run(unsigned int timer_id);
-void set_gptimer_pulse_hi(unsigned int timer_id);
-void clear_gptimer_pulse_hi(unsigned int timer_id);
-void enable_gptimers(uint16_t mask);
-void disable_gptimers(uint16_t mask);
-void disable_gptimers_sync(uint16_t mask);
-uint16_t get_enabled_gptimers(void);
-uint32_t get_gptimer_status(unsigned int group);
-void set_gptimer_status(unsigned int group, uint32_t value);
-
-static inline void enable_gptimer(unsigned int timer_id)
-{
- enable_gptimers(1 << timer_id);
-}
-
-static inline void disable_gptimer(unsigned int timer_id)
-{
- disable_gptimers(1 << timer_id);
-}
-
-/*
- * All Blackfin system MMRs are padded to 32bits even if the register
- * itself is only 16bits. So use a helper macro to streamline this.
- */
-#define __BFP(m) u16 m; u16 __pad_##m
-
-/*
- * bfin timer registers layout
- */
-struct bfin_gptimer_regs {
- __BFP(config);
- u32 counter;
- u32 period;
- u32 width;
-#ifdef CONFIG_BF60x
- u32 delay;
-#endif
-};
-
-/*
- * bfin group timer registers layout
- */
-#ifndef CONFIG_BF60x
-struct bfin_gptimer_group_regs {
- __BFP(enable);
- __BFP(disable);
- u32 status;
-};
-#else
-struct bfin_gptimer_group_regs {
- __BFP(run);
- __BFP(enable);
- __BFP(disable);
- __BFP(stop_cfg);
- __BFP(stop_cfg_set);
- __BFP(stop_cfg_clr);
- __BFP(data_imsk);
- __BFP(stat_imsk);
- __BFP(tr_msk);
- __BFP(tr_ie);
- __BFP(data_ilat);
- __BFP(stat_ilat);
- __BFP(err_status);
- __BFP(bcast_per);
- __BFP(bcast_wid);
- __BFP(bcast_dly);
-
-};
-#endif
-
-#undef __BFP
-
-#endif
+++ /dev/null
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_HARDIRQ_H
-#define __BFIN_HARDIRQ_H
-
-#define __ARCH_IRQ_EXIT_IRQS_DISABLED 1
-
-extern void ack_bad_irq(unsigned int irq);
-#define ack_bad_irq ack_bad_irq
-
-#include <asm-generic/hardirq.h>
-
-#endif
+++ /dev/null
-/*
- * Copyright 2004-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BFIN_IO_H
-#define _BFIN_IO_H
-
-#include <linux/compiler.h>
-#include <linux/types.h>
-#include <asm/byteorder.h>
-#include <asm/def_LPBlackfin.h>
-
-#define __raw_readb bfin_read8
-#define __raw_readw bfin_read16
-#define __raw_readl bfin_read32
-#define __raw_writeb(val, addr) bfin_write8(addr, val)
-#define __raw_writew(val, addr) bfin_write16(addr, val)
-#define __raw_writel(val, addr) bfin_write32(addr, val)
-
-extern void outsb(unsigned long port, const void *addr, unsigned long count);
-extern void outsw(unsigned long port, const void *addr, unsigned long count);
-extern void outsw_8(unsigned long port, const void *addr, unsigned long count);
-extern void outsl(unsigned long port, const void *addr, unsigned long count);
-#define outsb outsb
-#define outsw outsw
-#define outsl outsl
-
-extern void insb(unsigned long port, void *addr, unsigned long count);
-extern void insw(unsigned long port, void *addr, unsigned long count);
-extern void insw_8(unsigned long port, void *addr, unsigned long count);
-extern void insl(unsigned long port, void *addr, unsigned long count);
-extern void insl_16(unsigned long port, void *addr, unsigned long count);
-#define insb insb
-#define insw insw
-#define insl insl
-
-/**
- * I/O write barrier
- *
- * Ensure ordering of I/O space writes. This will make sure that writes
- * following the barrier will arrive after all previous writes.
- */
-#define mmiowb() do { SSYNC(); wmb(); } while (0)
-
-#include <asm-generic/io.h>
-
-#endif
+++ /dev/null
-/* -*- linux-c -*-
- * include/asm-blackfin/ipipe.h
- *
- * Copyright (C) 2002-2007 Philippe Gerum.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, Inc., 675 Mass Ave, Cambridge MA 02139,
- * USA; either version 2 of the License, or (at your option) any later
- * version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef __ASM_BLACKFIN_IPIPE_H
-#define __ASM_BLACKFIN_IPIPE_H
-
-#ifdef CONFIG_IPIPE
-
-#include <linux/cpumask.h>
-#include <linux/list.h>
-#include <linux/threads.h>
-#include <linux/irq.h>
-#include <linux/ipipe_percpu.h>
-#include <asm/ptrace.h>
-#include <asm/irq.h>
-#include <asm/bitops.h>
-#include <linux/atomic.h>
-#include <asm/traps.h>
-#include <asm/bitsperlong.h>
-
-#define IPIPE_ARCH_STRING "1.16-01"
-#define IPIPE_MAJOR_NUMBER 1
-#define IPIPE_MINOR_NUMBER 16
-#define IPIPE_PATCH_NUMBER 1
-
-#ifdef CONFIG_SMP
-#error "I-pipe/blackfin: SMP not implemented"
-#else /* !CONFIG_SMP */
-#define ipipe_processor_id() 0
-#endif /* CONFIG_SMP */
-
-#define prepare_arch_switch(next) \
-do { \
- ipipe_schedule_notify(current, next); \
- hard_local_irq_disable(); \
-} while (0)
-
-#define task_hijacked(p) \
- ({ \
- int __x__ = __ipipe_root_domain_p; \
- if (__x__) \
- hard_local_irq_enable(); \
- !__x__; \
- })
-
-struct ipipe_domain;
-
-struct ipipe_sysinfo {
- int sys_nr_cpus; /* Number of CPUs on board */
- int sys_hrtimer_irq; /* hrtimer device IRQ */
- u64 sys_hrtimer_freq; /* hrtimer device frequency */
- u64 sys_hrclock_freq; /* hrclock device frequency */
- u64 sys_cpu_freq; /* CPU frequency (Hz) */
-};
-
-#define ipipe_read_tsc(t) \
- ({ \
- unsigned long __cy2; \
- __asm__ __volatile__ ("1: %0 = CYCLES2\n" \
- "%1 = CYCLES\n" \
- "%2 = CYCLES2\n" \
- "CC = %2 == %0\n" \
- "if ! CC jump 1b\n" \
- : "=d,a" (((unsigned long *)&t)[1]), \
- "=d,a" (((unsigned long *)&t)[0]), \
- "=d,a" (__cy2) \
- : /*no input*/ : "CC"); \
- t; \
- })
-
-#define ipipe_cpu_freq() __ipipe_core_clock
-#define ipipe_tsc2ns(_t) (((unsigned long)(_t)) * __ipipe_freq_scale)
-#define ipipe_tsc2us(_t) (ipipe_tsc2ns(_t) / 1000 + 1)
-
-/* Private interface -- Internal use only */
-
-#define __ipipe_check_platform() do { } while (0)
-
-#define __ipipe_init_platform() do { } while (0)
-
-extern atomic_t __ipipe_irq_lvdepth[IVG15 + 1];
-
-extern unsigned long __ipipe_irq_lvmask;
-
-extern struct ipipe_domain ipipe_root;
-
-/* enable/disable_irqdesc _must_ be used in pairs. */
-
-void __ipipe_enable_irqdesc(struct ipipe_domain *ipd,
- unsigned irq);
-
-void __ipipe_disable_irqdesc(struct ipipe_domain *ipd,
- unsigned irq);
-
-#define __ipipe_enable_irq(irq) \
- do { \
- struct irq_desc *desc = irq_to_desc(irq); \
- struct irq_chip *chip = get_irq_desc_chip(desc); \
- chip->irq_unmask(&desc->irq_data); \
- } while (0)
-
-#define __ipipe_disable_irq(irq) \
- do { \
- struct irq_desc *desc = irq_to_desc(irq); \
- struct irq_chip *chip = get_irq_desc_chip(desc); \
- chip->irq_mask(&desc->irq_data); \
- } while (0)
-
-static inline int __ipipe_check_tickdev(const char *devname)
-{
- return 1;
-}
-
-void __ipipe_enable_pipeline(void);
-
-#define __ipipe_hook_critical_ipi(ipd) do { } while (0)
-
-void ___ipipe_sync_pipeline(void);
-
-void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs);
-
-int __ipipe_get_irq_priority(unsigned int irq);
-
-void __ipipe_serial_debug(const char *fmt, ...);
-
-asmlinkage void __ipipe_call_irqtail(unsigned long addr);
-
-DECLARE_PER_CPU(struct pt_regs, __ipipe_tick_regs);
-
-extern unsigned long __ipipe_core_clock;
-
-extern unsigned long __ipipe_freq_scale;
-
-extern unsigned long __ipipe_irq_tail_hook;
-
-static inline unsigned long __ipipe_ffnz(unsigned long ul)
-{
- return ffs(ul) - 1;
-}
-
-#define __ipipe_do_root_xirq(ipd, irq) \
- ((ipd)->irqs[irq].handler(irq, raw_cpu_ptr(&__ipipe_tick_regs)))
-
-#define __ipipe_run_irqtail(irq) /* Must be a macro */ \
- do { \
- unsigned long __pending; \
- CSYNC(); \
- __pending = bfin_read_IPEND(); \
- if (__pending & 0x8000) { \
- __pending &= ~0x8010; \
- if (__pending && (__pending & (__pending - 1)) == 0) \
- __ipipe_call_irqtail(__ipipe_irq_tail_hook); \
- } \
- } while (0)
-
-#define __ipipe_syscall_watched_p(p, sc) \
- (ipipe_notifier_enabled_p(p) || (unsigned long)sc >= NR_syscalls)
-
-#ifdef CONFIG_BF561
-#define bfin_write_TIMER_DISABLE(val) bfin_write_TMRS8_DISABLE(val)
-#define bfin_write_TIMER_ENABLE(val) bfin_write_TMRS8_ENABLE(val)
-#define bfin_write_TIMER_STATUS(val) bfin_write_TMRS8_STATUS(val)
-#define bfin_read_TIMER_STATUS() bfin_read_TMRS8_STATUS()
-#elif defined(CONFIG_BF54x)
-#define bfin_write_TIMER_DISABLE(val) bfin_write_TIMER_DISABLE0(val)
-#define bfin_write_TIMER_ENABLE(val) bfin_write_TIMER_ENABLE0(val)
-#define bfin_write_TIMER_STATUS(val) bfin_write_TIMER_STATUS0(val)
-#define bfin_read_TIMER_STATUS(val) bfin_read_TIMER_STATUS0(val)
-#endif
-
-#define __ipipe_root_tick_p(regs) ((regs->ipend & 0x10) != 0)
-
-#else /* !CONFIG_IPIPE */
-
-#define task_hijacked(p) 0
-#define ipipe_trap_notify(t, r) 0
-#define __ipipe_root_tick_p(regs) 1
-
-#endif /* !CONFIG_IPIPE */
-
-#ifdef CONFIG_TICKSOURCE_CORETMR
-#define IRQ_SYSTMR IRQ_CORETMR
-#define IRQ_PRIOTMR IRQ_CORETMR
-#else
-#define IRQ_SYSTMR IRQ_TIMER0
-#define IRQ_PRIOTMR CONFIG_IRQ_TIMER0
-#endif
-
-#define ipipe_update_tick_evtdev(evtdev) do { } while (0)
-
-#endif /* !__ASM_BLACKFIN_IPIPE_H */
+++ /dev/null
-/* -*- linux-c -*-
- * include/asm-blackfin/ipipe_base.h
- *
- * Copyright (C) 2007 Philippe Gerum.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, Inc., 675 Mass Ave, Cambridge MA 02139,
- * USA; either version 2 of the License, or (at your option) any later
- * version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef __ASM_BLACKFIN_IPIPE_BASE_H
-#define __ASM_BLACKFIN_IPIPE_BASE_H
-
-#ifdef CONFIG_IPIPE
-
-#include <asm/bitsperlong.h>
-#include <mach/irq.h>
-
-#define IPIPE_NR_XIRQS NR_IRQS
-
-/* Blackfin-specific, per-cpu pipeline status */
-#define IPIPE_SYNCDEFER_FLAG 15
-#define IPIPE_SYNCDEFER_MASK (1L << IPIPE_SYNCDEFER_MASK)
-
- /* Blackfin traps -- i.e. exception vector numbers */
-#define IPIPE_NR_FAULTS 52 /* We leave a gap after VEC_ILL_RES. */
-/* Pseudo-vectors used for kernel events */
-#define IPIPE_FIRST_EVENT IPIPE_NR_FAULTS
-#define IPIPE_EVENT_SYSCALL (IPIPE_FIRST_EVENT)
-#define IPIPE_EVENT_SCHEDULE (IPIPE_FIRST_EVENT + 1)
-#define IPIPE_EVENT_SIGWAKE (IPIPE_FIRST_EVENT + 2)
-#define IPIPE_EVENT_SETSCHED (IPIPE_FIRST_EVENT + 3)
-#define IPIPE_EVENT_INIT (IPIPE_FIRST_EVENT + 4)
-#define IPIPE_EVENT_EXIT (IPIPE_FIRST_EVENT + 5)
-#define IPIPE_EVENT_CLEANUP (IPIPE_FIRST_EVENT + 6)
-#define IPIPE_EVENT_RETURN (IPIPE_FIRST_EVENT + 7)
-#define IPIPE_LAST_EVENT IPIPE_EVENT_RETURN
-#define IPIPE_NR_EVENTS (IPIPE_LAST_EVENT + 1)
-
-#define IPIPE_TIMER_IRQ IRQ_CORETMR
-
-#define __IPIPE_FEATURE_SYSINFO_V2 1
-
-#ifndef __ASSEMBLY__
-
-extern unsigned long __ipipe_root_status; /* Alias to ipipe_root_cpudom_var(status) */
-
-void __ipipe_stall_root(void);
-
-unsigned long __ipipe_test_and_stall_root(void);
-
-unsigned long __ipipe_test_root(void);
-
-void __ipipe_lock_root(void);
-
-void __ipipe_unlock_root(void);
-
-#endif /* !__ASSEMBLY__ */
-
-#define __IPIPE_FEATURE_SYSINFO_V2 1
-
-#endif /* CONFIG_IPIPE */
-
-#endif /* !__ASM_BLACKFIN_IPIPE_BASE_H */
+++ /dev/null
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2003 HuTao
- * 2002 Arcturus Networks Inc. (www.arcturusnetworks.com
- * Ted Ma <mated@sympatico.ca>
- *
- * Licensed under the GPL-2
- */
-
-#ifndef _BFIN_IRQ_H_
-#define _BFIN_IRQ_H_
-
-#include <linux/irqflags.h>
-
-/* IRQs that may be used by external irq_chip controllers */
-#define NR_SPARE_IRQS 32
-
-#include <mach/anomaly.h>
-
-/* SYS_IRQS and NR_IRQS are defined in <mach-bf5xx/irq.h> */
-#include <mach/irq.h>
-
-#if ANOMALY_05000244 && defined(CONFIG_BFIN_ICACHE)
-# define NOP_PAD_ANOMALY_05000244 "nop; nop;"
-#else
-# define NOP_PAD_ANOMALY_05000244
-#endif
-
-#define idle_with_irq_disabled() \
- __asm__ __volatile__( \
- NOP_PAD_ANOMALY_05000244 \
- ".align 8;" \
- "sti %0;" \
- "idle;" \
- : \
- : "d" (bfin_irq_flags) \
- )
-
-#include <asm-generic/irq.h>
-
-#endif /* _BFIN_IRQ_H_ */
+++ /dev/null
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _IRQ_HANDLER_H
-#define _IRQ_HANDLER_H
-
-#include <linux/types.h>
-#include <linux/linkage.h>
-#include <mach/irq.h>
-
-/* init functions only */
-extern int init_arch_irq(void);
-extern void init_exception_vectors(void);
-extern void program_IAR(void);
-#ifdef init_mach_irq
-extern void init_mach_irq(void);
-#else
-# define init_mach_irq()
-#endif
-
-/* BASE LEVEL interrupt handler routines */
-asmlinkage void evt_exception(void);
-asmlinkage void trap(void);
-asmlinkage void evt_ivhw(void);
-asmlinkage void evt_timer(void);
-asmlinkage void evt_nmi(void);
-asmlinkage void evt_evt7(void);
-asmlinkage void evt_evt8(void);
-asmlinkage void evt_evt9(void);
-asmlinkage void evt_evt10(void);
-asmlinkage void evt_evt11(void);
-asmlinkage void evt_evt12(void);
-asmlinkage void evt_evt13(void);
-asmlinkage void evt_evt14(void);
-asmlinkage void evt_soft_int1(void);
-asmlinkage void evt_system_call(void);
-asmlinkage void init_exception_buff(void);
-asmlinkage void trap_c(struct pt_regs *fp);
-asmlinkage void ex_replaceable(void);
-asmlinkage void early_trap(void);
-
-extern void *ex_table[];
-extern void return_from_exception(void);
-
-extern int bfin_request_exception(unsigned int exception, void (*handler)(void));
-extern int bfin_free_exception(unsigned int exception, void (*handler)(void));
-
-extern asmlinkage void lower_to_irq14(void);
-extern asmlinkage void bfin_return_from_exception(void);
-extern asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs);
-extern int bfin_internal_set_wake(unsigned int irq, unsigned int state);
-
-struct irq_data;
-extern void bfin_handle_irq(unsigned irq);
-extern void bfin_ack_noop(struct irq_data *);
-extern void bfin_internal_mask_irq(unsigned int irq);
-extern void bfin_internal_unmask_irq(unsigned int irq);
-
-struct irq_desc;
-extern void bfin_demux_mac_status_irq(struct irq_desc *);
-extern void bfin_demux_gpio_irq(struct irq_desc *);
-
-#endif
+++ /dev/null
-/*
- * interface to Blackfin CEC
- *
- * Copyright 2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_BFIN_IRQFLAGS_H__
-#define __ASM_BFIN_IRQFLAGS_H__
-
-#include <mach/blackfin.h>
-
-#ifdef CONFIG_SMP
-# include <asm/pda.h>
-# include <asm/processor.h>
-# define bfin_irq_flags cpu_pda[blackfin_core_id()].imask
-#else
-extern unsigned long bfin_irq_flags;
-#endif
-
-static inline notrace void bfin_sti(unsigned long flags)
-{
- asm volatile("sti %0;" : : "d" (flags));
-}
-
-static inline notrace unsigned long bfin_cli(void)
-{
- unsigned long flags;
- asm volatile("cli %0;" : "=d" (flags));
- return flags;
-}
-
-#ifdef CONFIG_DEBUG_HWERR
-# define bfin_no_irqs 0x3f
-#else
-# define bfin_no_irqs 0x1f
-#endif
-
-/*****************************************************************************/
-/*
- * Hard, untraced CPU interrupt flag manipulation and access.
- */
-static inline notrace void __hard_local_irq_disable(void)
-{
- bfin_cli();
-}
-
-static inline notrace void __hard_local_irq_enable(void)
-{
- bfin_sti(bfin_irq_flags);
-}
-
-static inline notrace unsigned long hard_local_save_flags(void)
-{
- return bfin_read_IMASK();
-}
-
-static inline notrace unsigned long __hard_local_irq_save(void)
-{
- unsigned long flags;
- flags = bfin_cli();
-#ifdef CONFIG_DEBUG_HWERR
- bfin_sti(0x3f);
-#endif
- return flags;
-}
-
-static inline notrace int hard_irqs_disabled_flags(unsigned long flags)
-{
-#ifdef CONFIG_BF60x
- return (flags & IMASK_IVG11) == 0;
-#else
- return (flags & ~0x3f) == 0;
-#endif
-}
-
-static inline notrace int hard_irqs_disabled(void)
-{
- unsigned long flags = hard_local_save_flags();
- return hard_irqs_disabled_flags(flags);
-}
-
-static inline notrace void __hard_local_irq_restore(unsigned long flags)
-{
- if (!hard_irqs_disabled_flags(flags))
- __hard_local_irq_enable();
-}
-
-/*****************************************************************************/
-/*
- * Interrupt pipe handling.
- */
-#ifdef CONFIG_IPIPE
-
-#include <linux/compiler.h>
-#include <linux/ipipe_trace.h>
-/*
- * Way too many inter-deps between low-level headers in this port, so
- * we redeclare the required bits we cannot pick from
- * <asm/ipipe_base.h> to prevent circular dependencies.
- */
-void __ipipe_stall_root(void);
-void __ipipe_unstall_root(void);
-unsigned long __ipipe_test_root(void);
-unsigned long __ipipe_test_and_stall_root(void);
-void __ipipe_restore_root(unsigned long flags);
-
-#ifdef CONFIG_IPIPE_DEBUG_CONTEXT
-struct ipipe_domain;
-extern struct ipipe_domain ipipe_root;
-void ipipe_check_context(struct ipipe_domain *ipd);
-#define __check_irqop_context(ipd) ipipe_check_context(&ipipe_root)
-#else /* !CONFIG_IPIPE_DEBUG_CONTEXT */
-#define __check_irqop_context(ipd) do { } while (0)
-#endif /* !CONFIG_IPIPE_DEBUG_CONTEXT */
-
-/*
- * Interrupt pipe interface to linux/irqflags.h.
- */
-static inline notrace void arch_local_irq_disable(void)
-{
- __check_irqop_context();
- __ipipe_stall_root();
- barrier();
-}
-
-static inline notrace void arch_local_irq_enable(void)
-{
- barrier();
- __check_irqop_context();
- __ipipe_unstall_root();
-}
-
-static inline notrace unsigned long arch_local_save_flags(void)
-{
- return __ipipe_test_root() ? bfin_no_irqs : bfin_irq_flags;
-}
-
-static inline notrace int arch_irqs_disabled_flags(unsigned long flags)
-{
- return flags == bfin_no_irqs;
-}
-
-static inline notrace unsigned long arch_local_irq_save(void)
-{
- unsigned long flags;
-
- __check_irqop_context();
- flags = __ipipe_test_and_stall_root() ? bfin_no_irqs : bfin_irq_flags;
- barrier();
-
- return flags;
-}
-
-static inline notrace void arch_local_irq_restore(unsigned long flags)
-{
- __check_irqop_context();
- __ipipe_restore_root(flags == bfin_no_irqs);
-}
-
-static inline notrace unsigned long arch_mangle_irq_bits(int virt, unsigned long real)
-{
- /*
- * Merge virtual and real interrupt mask bits into a single
- * 32bit word.
- */
- return (real & ~(1 << 31)) | ((virt != 0) << 31);
-}
-
-static inline notrace int arch_demangle_irq_bits(unsigned long *x)
-{
- int virt = (*x & (1 << 31)) != 0;
- *x &= ~(1L << 31);
- return virt;
-}
-
-/*
- * Interface to various arch routines that may be traced.
- */
-#ifdef CONFIG_IPIPE_TRACE_IRQSOFF
-static inline notrace void hard_local_irq_disable(void)
-{
- if (!hard_irqs_disabled()) {
- __hard_local_irq_disable();
- ipipe_trace_begin(0x80000000);
- }
-}
-
-static inline notrace void hard_local_irq_enable(void)
-{
- if (hard_irqs_disabled()) {
- ipipe_trace_end(0x80000000);
- __hard_local_irq_enable();
- }
-}
-
-static inline notrace unsigned long hard_local_irq_save(void)
-{
- unsigned long flags = hard_local_save_flags();
- if (!hard_irqs_disabled_flags(flags)) {
- __hard_local_irq_disable();
- ipipe_trace_begin(0x80000001);
- }
- return flags;
-}
-
-static inline notrace void hard_local_irq_restore(unsigned long flags)
-{
- if (!hard_irqs_disabled_flags(flags)) {
- ipipe_trace_end(0x80000001);
- __hard_local_irq_enable();
- }
-}
-
-#else /* !CONFIG_IPIPE_TRACE_IRQSOFF */
-# define hard_local_irq_disable() __hard_local_irq_disable()
-# define hard_local_irq_enable() __hard_local_irq_enable()
-# define hard_local_irq_save() __hard_local_irq_save()
-# define hard_local_irq_restore(flags) __hard_local_irq_restore(flags)
-#endif /* !CONFIG_IPIPE_TRACE_IRQSOFF */
-
-#define hard_local_irq_save_cond() hard_local_irq_save()
-#define hard_local_irq_restore_cond(flags) hard_local_irq_restore(flags)
-
-#else /* !CONFIG_IPIPE */
-
-/*
- * Direct interface to linux/irqflags.h.
- */
-#define arch_local_save_flags() hard_local_save_flags()
-#define arch_local_irq_save() __hard_local_irq_save()
-#define arch_local_irq_restore(flags) __hard_local_irq_restore(flags)
-#define arch_local_irq_enable() __hard_local_irq_enable()
-#define arch_local_irq_disable() __hard_local_irq_disable()
-#define arch_irqs_disabled_flags(flags) hard_irqs_disabled_flags(flags)
-#define arch_irqs_disabled() hard_irqs_disabled()
-
-/*
- * Interface to various arch routines that may be traced.
- */
-#define hard_local_irq_save() __hard_local_irq_save()
-#define hard_local_irq_restore(flags) __hard_local_irq_restore(flags)
-#define hard_local_irq_enable() __hard_local_irq_enable()
-#define hard_local_irq_disable() __hard_local_irq_disable()
-#define hard_local_irq_save_cond() hard_local_save_flags()
-#define hard_local_irq_restore_cond(flags) do { (void)(flags); } while (0)
-
-#endif /* !CONFIG_IPIPE */
-
-#ifdef CONFIG_SMP
-#define hard_local_irq_save_smp() hard_local_irq_save()
-#define hard_local_irq_restore_smp(flags) hard_local_irq_restore(flags)
-#else
-#define hard_local_irq_save_smp() hard_local_save_flags()
-#define hard_local_irq_restore_smp(flags) do { (void)(flags); } while (0)
-#endif
-
-/*
- * Remap the arch-neutral IRQ state manipulation macros to the
- * blackfin-specific hard_local_irq_* API.
- */
-#define local_irq_save_hw(flags) \
- do { \
- (flags) = hard_local_irq_save(); \
- } while (0)
-#define local_irq_restore_hw(flags) \
- do { \
- hard_local_irq_restore(flags); \
- } while (0)
-#define local_irq_disable_hw() \
- do { \
- hard_local_irq_disable(); \
- } while (0)
-#define local_irq_enable_hw() \
- do { \
- hard_local_irq_enable(); \
- } while (0)
-#define local_irq_save_hw_notrace(flags) \
- do { \
- (flags) = __hard_local_irq_save(); \
- } while (0)
-#define local_irq_restore_hw_notrace(flags) \
- do { \
- __hard_local_irq_restore(flags); \
- } while (0)
-
-#define irqs_disabled_hw() hard_irqs_disabled()
-
-#endif
+++ /dev/null
-/* Blackfin KGDB header
- *
- * Copyright 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_BLACKFIN_KGDB_H__
-#define __ASM_BLACKFIN_KGDB_H__
-
-#include <linux/ptrace.h>
-
-/*
- * BUFMAX defines the maximum number of characters in inbound/outbound buffers.
- * At least NUMREGBYTES*2 are needed for register packets.
- * Longer buffer is needed to list all threads.
- */
-#define BUFMAX 2048
-
-/*
- * Note that this register image is different from
- * the register image that Linux produces at interrupt time.
- *
- * Linux's register image is defined by struct pt_regs in ptrace.h.
- */
-enum regnames {
- /* Core Registers */
- BFIN_R0 = 0,
- BFIN_R1,
- BFIN_R2,
- BFIN_R3,
- BFIN_R4,
- BFIN_R5,
- BFIN_R6,
- BFIN_R7,
- BFIN_P0,
- BFIN_P1,
- BFIN_P2,
- BFIN_P3,
- BFIN_P4,
- BFIN_P5,
- BFIN_SP,
- BFIN_FP,
- BFIN_I0,
- BFIN_I1,
- BFIN_I2,
- BFIN_I3,
- BFIN_M0,
- BFIN_M1,
- BFIN_M2,
- BFIN_M3,
- BFIN_B0,
- BFIN_B1,
- BFIN_B2,
- BFIN_B3,
- BFIN_L0,
- BFIN_L1,
- BFIN_L2,
- BFIN_L3,
- BFIN_A0_DOT_X,
- BFIN_A0_DOT_W,
- BFIN_A1_DOT_X,
- BFIN_A1_DOT_W,
- BFIN_ASTAT,
- BFIN_RETS,
- BFIN_LC0,
- BFIN_LT0,
- BFIN_LB0,
- BFIN_LC1,
- BFIN_LT1,
- BFIN_LB1,
- BFIN_CYCLES,
- BFIN_CYCLES2,
- BFIN_USP,
- BFIN_SEQSTAT,
- BFIN_SYSCFG,
- BFIN_RETI,
- BFIN_RETX,
- BFIN_RETN,
- BFIN_RETE,
-
- /* Pseudo Registers */
- BFIN_PC,
- BFIN_CC,
- BFIN_EXTRA1, /* Address of .text section. */
- BFIN_EXTRA2, /* Address of .data section. */
- BFIN_EXTRA3, /* Address of .bss section. */
- BFIN_FDPIC_EXEC,
- BFIN_FDPIC_INTERP,
-
- /* MMRs */
- BFIN_IPEND,
-
- /* LAST ENTRY SHOULD NOT BE CHANGED. */
- BFIN_NUM_REGS /* The number of all registers. */
-};
-
-/* Number of bytes of registers. */
-#define NUMREGBYTES BFIN_NUM_REGS*4
-
-static inline void arch_kgdb_breakpoint(void)
-{
- asm("EXCPT 2;");
-}
-#define BREAK_INSTR_SIZE 2
-#ifdef CONFIG_SMP
-# define CACHE_FLUSH_IS_SAFE 0
-#else
-# define CACHE_FLUSH_IS_SAFE 1
-#endif
-#define GDB_ADJUSTS_BREAK_OFFSET
-#define GDB_SKIP_HW_WATCH_TEST
-#define HW_INST_WATCHPOINT_NUM 6
-#define HW_WATCHPOINT_NUM 8
-#define TYPE_INST_WATCHPOINT 0
-#define TYPE_DATA_WATCHPOINT 1
-
-/* Instruction watchpoint address control register bits mask */
-#define WPPWR 0x1
-#define WPIREN01 0x2
-#define WPIRINV01 0x4
-#define WPIAEN0 0x8
-#define WPIAEN1 0x10
-#define WPICNTEN0 0x20
-#define WPICNTEN1 0x40
-#define EMUSW0 0x80
-#define EMUSW1 0x100
-#define WPIREN23 0x200
-#define WPIRINV23 0x400
-#define WPIAEN2 0x800
-#define WPIAEN3 0x1000
-#define WPICNTEN2 0x2000
-#define WPICNTEN3 0x4000
-#define EMUSW2 0x8000
-#define EMUSW3 0x10000
-#define WPIREN45 0x20000
-#define WPIRINV45 0x40000
-#define WPIAEN4 0x80000
-#define WPIAEN5 0x100000
-#define WPICNTEN4 0x200000
-#define WPICNTEN5 0x400000
-#define EMUSW4 0x800000
-#define EMUSW5 0x1000000
-#define WPAND 0x2000000
-
-/* Data watchpoint address control register bits mask */
-#define WPDREN01 0x1
-#define WPDRINV01 0x2
-#define WPDAEN0 0x4
-#define WPDAEN1 0x8
-#define WPDCNTEN0 0x10
-#define WPDCNTEN1 0x20
-
-#define WPDSRC0 0xc0
-#define WPDACC0_OFFSET 8
-#define WPDSRC1 0xc00
-#define WPDACC1_OFFSET 12
-
-/* Watchpoint status register bits mask */
-#define STATIA0 0x1
-#define STATIA1 0x2
-#define STATIA2 0x4
-#define STATIA3 0x8
-#define STATIA4 0x10
-#define STATIA5 0x20
-#define STATDA0 0x40
-#define STATDA1 0x80
-
-#endif
+++ /dev/null
-/*
- * Defines a layout of L1 scratchpad memory that userspace can rely on.
- *
- * Copyright 2006-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _L1LAYOUT_H_
-#define _L1LAYOUT_H_
-
-#include <asm/blackfin.h>
-
-#ifndef CONFIG_SMP
-#ifndef __ASSEMBLY__
-
-/* Data that is "mapped" into the process VM at the start of the L1 scratch
- memory, so that each process can access it at a fixed address. Used for
- stack checking. */
-struct l1_scratch_task_info
-{
- /* Points to the start of the stack. */
- void *stack_start;
- /* Not updated by the kernel; a user process can modify this to
- keep track of the lowest address of the stack pointer during its
- runtime. */
- void *lowest_sp;
-};
-
-/* A pointer to the structure in memory. */
-#define L1_SCRATCH_TASK_INFO ((struct l1_scratch_task_info *)\
- get_l1_scratch_start())
-
-#endif
-#endif
-
-#endif
+++ /dev/null
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_LINKAGE_H
-#define __ASM_LINKAGE_H
-
-#define __ALIGN .align 4
-#define __ALIGN_STR ".align 4"
-
-#endif
+++ /dev/null
-/*
- * arch/blackfin/include/asm/mem_init.h - reprogram clocks / memory
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __MEM_INIT_H__
-#define __MEM_INIT_H__
-
-#if defined(EBIU_SDGCTL)
-#if defined(CONFIG_MEM_MT48LC16M16A2TG_75) || \
- defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \
- defined(CONFIG_MEM_MT48LC16M8A2TG_75) || \
- defined(CONFIG_MEM_MT48LC32M8A2_75) || \
- defined(CONFIG_MEM_MT48LC8M32B2B5_7) || \
- defined(CONFIG_MEM_MT48LC32M16A2TG_75) || \
- defined(CONFIG_MEM_MT48LC32M8A2_75)
-#if (CONFIG_SCLK_HZ > 119402985)
-#define SDRAM_tRP TRP_2
-#define SDRAM_tRP_num 2
-#define SDRAM_tRAS TRAS_7
-#define SDRAM_tRAS_num 7
-#define SDRAM_tRCD TRCD_2
-#define SDRAM_tWR TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
-#define SDRAM_tRP TRP_2
-#define SDRAM_tRP_num 2
-#define SDRAM_tRAS TRAS_6
-#define SDRAM_tRAS_num 6
-#define SDRAM_tRCD TRCD_2
-#define SDRAM_tWR TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
-#define SDRAM_tRP TRP_2
-#define SDRAM_tRP_num 2
-#define SDRAM_tRAS TRAS_5
-#define SDRAM_tRAS_num 5
-#define SDRAM_tRCD TRCD_2
-#define SDRAM_tWR TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
-#define SDRAM_tRP TRP_2
-#define SDRAM_tRP_num 2
-#define SDRAM_tRAS TRAS_4
-#define SDRAM_tRAS_num 4
-#define SDRAM_tRCD TRCD_2
-#define SDRAM_tWR TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
-#define SDRAM_tRP TRP_2
-#define SDRAM_tRP_num 2
-#define SDRAM_tRAS TRAS_3
-#define SDRAM_tRAS_num 3
-#define SDRAM_tRCD TRCD_2
-#define SDRAM_tWR TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
-#define SDRAM_tRP TRP_1
-#define SDRAM_tRP_num 1
-#define SDRAM_tRAS TRAS_4
-#define SDRAM_tRAS_num 4
-#define SDRAM_tRCD TRCD_1
-#define SDRAM_tWR TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
-#define SDRAM_tRP TRP_1
-#define SDRAM_tRP_num 1
-#define SDRAM_tRAS TRAS_3
-#define SDRAM_tRAS_num 3
-#define SDRAM_tRCD TRCD_1
-#define SDRAM_tWR TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
-#define SDRAM_tRP TRP_1
-#define SDRAM_tRP_num 1
-#define SDRAM_tRAS TRAS_2
-#define SDRAM_tRAS_num 2
-#define SDRAM_tRCD TRCD_1
-#define SDRAM_tWR TWR_2
-#endif
-#if (CONFIG_SCLK_HZ <= 29850746)
-#define SDRAM_tRP TRP_1
-#define SDRAM_tRP_num 1
-#define SDRAM_tRAS TRAS_1
-#define SDRAM_tRAS_num 1
-#define SDRAM_tRCD TRCD_1
-#define SDRAM_tWR TWR_2
-#endif
-#endif
-
-/*
- * The BF526-EZ-Board changed SDRAM chips between revisions,
- * so we use below timings to accommodate both.
- */
-#if defined(CONFIG_MEM_MT48H32M16LFCJ_75)
-#if (CONFIG_SCLK_HZ > 119402985)
-#define SDRAM_tRP TRP_2
-#define SDRAM_tRP_num 2
-#define SDRAM_tRAS TRAS_8
-#define SDRAM_tRAS_num 8
-#define SDRAM_tRCD TRCD_2
-#define SDRAM_tWR TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
-#define SDRAM_tRP TRP_2
-#define SDRAM_tRP_num 2
-#define SDRAM_tRAS TRAS_7
-#define SDRAM_tRAS_num 7
-#define SDRAM_tRCD TRCD_2
-#define SDRAM_tWR TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
-#define SDRAM_tRP TRP_2
-#define SDRAM_tRP_num 2
-#define SDRAM_tRAS TRAS_6
-#define SDRAM_tRAS_num 6
-#define SDRAM_tRCD TRCD_2
-#define SDRAM_tWR TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
-#define SDRAM_tRP TRP_2
-#define SDRAM_tRP_num 2
-#define SDRAM_tRAS TRAS_5
-#define SDRAM_tRAS_num 5
-#define SDRAM_tRCD TRCD_2
-#define SDRAM_tWR TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
-#define SDRAM_tRP TRP_2
-#define SDRAM_tRP_num 2
-#define SDRAM_tRAS TRAS_4
-#define SDRAM_tRAS_num 4
-#define SDRAM_tRCD TRCD_2
-#define SDRAM_tWR TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
-#define SDRAM_tRP TRP_2
-#define SDRAM_tRP_num 2
-#define SDRAM_tRAS TRAS_4
-#define SDRAM_tRAS_num 4
-#define SDRAM_tRCD TRCD_1
-#define SDRAM_tWR TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
-#define SDRAM_tRP TRP_2
-#define SDRAM_tRP_num 2
-#define SDRAM_tRAS TRAS_3
-#define SDRAM_tRAS_num 3
-#define SDRAM_tRCD TRCD_1
-#define SDRAM_tWR TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
-#define SDRAM_tRP TRP_1
-#define SDRAM_tRP_num 1
-#define SDRAM_tRAS TRAS_3
-#define SDRAM_tRAS_num 3
-#define SDRAM_tRCD TRCD_1
-#define SDRAM_tWR TWR_2
-#endif
-#if (CONFIG_SCLK_HZ <= 29850746)
-#define SDRAM_tRP TRP_1
-#define SDRAM_tRP_num 1
-#define SDRAM_tRAS TRAS_2
-#define SDRAM_tRAS_num 2
-#define SDRAM_tRCD TRCD_1
-#define SDRAM_tWR TWR_2
-#endif
-#endif
-
-#if defined(CONFIG_MEM_MT48LC16M8A2TG_75) || \
- defined(CONFIG_MEM_MT48LC8M32B2B5_7)
- /*SDRAM INFORMATION: */
-#define SDRAM_Tref 64 /* Refresh period in milliseconds */
-#define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */
-#define SDRAM_CL CL_3
-#endif
-
-#if defined(CONFIG_MEM_MT48LC32M8A2_75) || \
- defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \
- defined(CONFIG_MEM_MT48LC32M16A2TG_75) || \
- defined(CONFIG_MEM_MT48LC16M16A2TG_75) || \
- defined(CONFIG_MEM_MT48LC32M8A2_75)
- /*SDRAM INFORMATION: */
-#define SDRAM_Tref 64 /* Refresh period in milliseconds */
-#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
-#define SDRAM_CL CL_3
-#endif
-
-#if defined(CONFIG_MEM_MT48H32M16LFCJ_75)
- /*SDRAM INFORMATION: */
-#define SDRAM_Tref 64 /* Refresh period in milliseconds */
-#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
-#define SDRAM_CL CL_2
-#endif
-
-
-#ifdef CONFIG_BFIN_KERNEL_CLOCK_MEMINIT_CALC
-/* Equation from section 17 (p17-46) of BF533 HRM */
-#define mem_SDRRC (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
-
-/* Enable SCLK Out */
-#define mem_SDGCTL (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS)
-#else
-#define mem_SDRRC CONFIG_MEM_SDRRC
-#define mem_SDGCTL CONFIG_MEM_SDGCTL
-#endif
-#endif
-
-
-#if defined(EBIU_DDRCTL0)
-#define MIN_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000 + 1)
-#define MAX_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000)
-#define DDR_CLK_HZ(x) (1000*1000*1000/x)
-
-#if defined(CONFIG_MEM_MT46V32M16_6T)
-#define DDR_SIZE DEVSZ_512
-#define DDR_WIDTH DEVWD_16
-#define DDR_MAX_tCK 13
-
-#define DDR_tRC DDR_TRC(MIN_DDR_SCLK(60))
-#define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(42))
-#define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15))
-#define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(72))
-#define DDR_tREFI DDR_TREFI(MAX_DDR_SCLK(7800))
-
-#define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15))
-#define DDR_tWTR DDR_TWTR(1)
-#define DDR_tMRD DDR_TMRD(MIN_DDR_SCLK(12))
-#define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15))
-#endif
-
-#if defined(CONFIG_MEM_MT46V32M16_5B)
-#define DDR_SIZE DEVSZ_512
-#define DDR_WIDTH DEVWD_16
-#define DDR_MAX_tCK 13
-
-#define DDR_tRC DDR_TRC(MIN_DDR_SCLK(55))
-#define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(40))
-#define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15))
-#define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(70))
-#define DDR_tREFI DDR_TREFI(MAX_DDR_SCLK(7800))
-
-#define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15))
-#define DDR_tWTR DDR_TWTR(2)
-#define DDR_tMRD DDR_TMRD(MIN_DDR_SCLK(10))
-#define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15))
-#endif
-
-#if (CONFIG_SCLK_HZ < DDR_CLK_HZ(DDR_MAX_tCK))
-# error "CONFIG_SCLK_HZ is too small (<DDR_CLK_HZ(DDR_MAX_tCK) Hz)."
-#elif(CONFIG_SCLK_HZ <= 133333333)
-# define DDR_CL CL_2
-#else
-# error "CONFIG_SCLK_HZ is too large (>133333333 Hz)."
-#endif
-
-#ifdef CONFIG_BFIN_KERNEL_CLOCK_MEMINIT_CALC
-#define mem_DDRCTL0 (DDR_tRP | DDR_tRAS | DDR_tRC | DDR_tRFC | DDR_tREFI)
-#define mem_DDRCTL1 (DDR_DATWIDTH | EXTBANK_1 | DDR_SIZE | DDR_WIDTH | DDR_tWTR \
- | DDR_tMRD | DDR_tWR | DDR_tRCD)
-#define mem_DDRCTL2 DDR_CL
-#else
-#define mem_DDRCTL0 CONFIG_MEM_DDRCTL0
-#define mem_DDRCTL1 CONFIG_MEM_DDRCTL1
-#define mem_DDRCTL2 CONFIG_MEM_DDRCTL2
-#endif
-#endif
-
-#if defined CONFIG_CLKIN_HALF
-#define CLKIN_HALF 1
-#else
-#define CLKIN_HALF 0
-#endif
-
-#if defined CONFIG_PLL_BYPASS
-#define PLL_BYPASS 1
-#else
-#define PLL_BYPASS 0
-#endif
-
-#ifdef CONFIG_BF60x
-
-/* DMC status bits */
-#define IDLE 0x1
-#define MEMINITDONE 0x4
-#define SRACK 0x8
-#define PDACK 0x10
-#define DPDACK 0x20
-#define DLLCALDONE 0x2000
-#define PENDREF 0xF0000
-#define PHYRDPHASE 0xF00000
-#define PHYRDPHASE_OFFSET 20
-
-/* DMC control bits */
-#define LPDDR 0x2
-#define INIT 0x4
-#define SRREQ 0x8
-#define PDREQ 0x10
-#define DPDREQ 0x20
-#define PREC 0x40
-#define ADDRMODE 0x100
-#define RDTOWR 0xE00
-#define PPREF 0x1000
-#define DLLCAL 0x2000
-
-/* DMC DLL control bits */
-#define DLLCALRDCNT 0xFF
-#define DATACYC 0xF00
-#define DATACYC_OFFSET 8
-
-/* CGU Divisor bits */
-#define CSEL_OFFSET 0
-#define S0SEL_OFFSET 5
-#define SYSSEL_OFFSET 8
-#define S1SEL_OFFSET 13
-#define DSEL_OFFSET 16
-#define OSEL_OFFSET 22
-#define ALGN 0x20000000
-#define UPDT 0x40000000
-#define LOCK 0x80000000
-
-/* CGU Status bits */
-#define PLLEN 0x1
-#define PLLBP 0x2
-#define PLOCK 0x4
-#define CLKSALGN 0x8
-
-/* CGU Control bits */
-#define MSEL_MASK 0x7F00
-#define DF_MASK 0x1
-
-struct ddr_config {
- u32 ddr_clk;
- u32 dmc_ddrctl;
- u32 dmc_effctl;
- u32 dmc_ddrcfg;
- u32 dmc_ddrtr0;
- u32 dmc_ddrtr1;
- u32 dmc_ddrtr2;
- u32 dmc_ddrmr;
- u32 dmc_ddrmr1;
-};
-
-#if defined(CONFIG_MEM_MT47H64M16)
-static struct ddr_config ddr_config_table[] __attribute__((section(".data_l1"))) = {
- [0] = {
- .ddr_clk = 125,
- .dmc_ddrctl = 0x00000904,
- .dmc_effctl = 0x004400C0,
- .dmc_ddrcfg = 0x00000422,
- .dmc_ddrtr0 = 0x20705212,
- .dmc_ddrtr1 = 0x201003CF,
- .dmc_ddrtr2 = 0x00320107,
- .dmc_ddrmr = 0x00000422,
- .dmc_ddrmr1 = 0x4,
- },
- [1] = {
- .ddr_clk = 133,
- .dmc_ddrctl = 0x00000904,
- .dmc_effctl = 0x004400C0,
- .dmc_ddrcfg = 0x00000422,
- .dmc_ddrtr0 = 0x20806313,
- .dmc_ddrtr1 = 0x2013040D,
- .dmc_ddrtr2 = 0x00320108,
- .dmc_ddrmr = 0x00000632,
- .dmc_ddrmr1 = 0x4,
- },
- [2] = {
- .ddr_clk = 150,
- .dmc_ddrctl = 0x00000904,
- .dmc_effctl = 0x004400C0,
- .dmc_ddrcfg = 0x00000422,
- .dmc_ddrtr0 = 0x20A07323,
- .dmc_ddrtr1 = 0x20160492,
- .dmc_ddrtr2 = 0x00320209,
- .dmc_ddrmr = 0x00000632,
- .dmc_ddrmr1 = 0x4,
- },
- [3] = {
- .ddr_clk = 166,
- .dmc_ddrctl = 0x00000904,
- .dmc_effctl = 0x004400C0,
- .dmc_ddrcfg = 0x00000422,
- .dmc_ddrtr0 = 0x20A07323,
- .dmc_ddrtr1 = 0x2016050E,
- .dmc_ddrtr2 = 0x00320209,
- .dmc_ddrmr = 0x00000632,
- .dmc_ddrmr1 = 0x4,
- },
- [4] = {
- .ddr_clk = 200,
- .dmc_ddrctl = 0x00000904,
- .dmc_effctl = 0x004400C0,
- .dmc_ddrcfg = 0x00000422,
- .dmc_ddrtr0 = 0x20a07323,
- .dmc_ddrtr1 = 0x2016050f,
- .dmc_ddrtr2 = 0x00320509,
- .dmc_ddrmr = 0x00000632,
- .dmc_ddrmr1 = 0x4,
- },
- [5] = {
- .ddr_clk = 225,
- .dmc_ddrctl = 0x00000904,
- .dmc_effctl = 0x004400C0,
- .dmc_ddrcfg = 0x00000422,
- .dmc_ddrtr0 = 0x20E0A424,
- .dmc_ddrtr1 = 0x302006DB,
- .dmc_ddrtr2 = 0x0032020D,
- .dmc_ddrmr = 0x00000842,
- .dmc_ddrmr1 = 0x4,
- },
- [6] = {
- .ddr_clk = 250,
- .dmc_ddrctl = 0x00000904,
- .dmc_effctl = 0x004400C0,
- .dmc_ddrcfg = 0x00000422,
- .dmc_ddrtr0 = 0x20E0A424,
- .dmc_ddrtr1 = 0x3020079E,
- .dmc_ddrtr2 = 0x0032050D,
- .dmc_ddrmr = 0x00000842,
- .dmc_ddrmr1 = 0x4,
- },
-};
-#endif
-
-static inline void dmc_enter_self_refresh(void)
-{
- if (bfin_read_DMC0_STAT() & MEMINITDONE) {
- bfin_write_DMC0_CTL(bfin_read_DMC0_CTL() | SRREQ);
- while (!(bfin_read_DMC0_STAT() & SRACK))
- continue;
- }
-}
-
-static inline void dmc_exit_self_refresh(void)
-{
- if (bfin_read_DMC0_STAT() & MEMINITDONE) {
- bfin_write_DMC0_CTL(bfin_read_DMC0_CTL() & ~SRREQ);
- while (bfin_read_DMC0_STAT() & SRACK)
- continue;
- }
-}
-
-static inline void init_cgu(u32 cgu_div, u32 cgu_ctl)
-{
- dmc_enter_self_refresh();
-
- /* Don't set the same value of MSEL and DF to CGU_CTL */
- if ((bfin_read32(CGU0_CTL) & (MSEL_MASK | DF_MASK))
- != cgu_ctl) {
- bfin_write32(CGU0_DIV, cgu_div);
- bfin_write32(CGU0_CTL, cgu_ctl);
- while ((bfin_read32(CGU0_STAT) & (CLKSALGN | PLLBP)) ||
- !(bfin_read32(CGU0_STAT) & PLOCK))
- continue;
- }
-
- bfin_write32(CGU0_DIV, cgu_div | UPDT);
- while (bfin_read32(CGU0_STAT) & CLKSALGN)
- continue;
-
- dmc_exit_self_refresh();
-}
-
-static inline void init_dmc(u32 dmc_clk)
-{
- int i, dlldatacycle, dll_ctl;
-
- for (i = 0; i < 7; i++) {
- if (ddr_config_table[i].ddr_clk == dmc_clk) {
- bfin_write_DMC0_CFG(ddr_config_table[i].dmc_ddrcfg);
- bfin_write_DMC0_TR0(ddr_config_table[i].dmc_ddrtr0);
- bfin_write_DMC0_TR1(ddr_config_table[i].dmc_ddrtr1);
- bfin_write_DMC0_TR2(ddr_config_table[i].dmc_ddrtr2);
- bfin_write_DMC0_MR(ddr_config_table[i].dmc_ddrmr);
- bfin_write_DMC0_EMR1(ddr_config_table[i].dmc_ddrmr1);
- bfin_write_DMC0_EFFCTL(ddr_config_table[i].dmc_effctl);
- bfin_write_DMC0_CTL(ddr_config_table[i].dmc_ddrctl);
- break;
- }
- }
-
- while (!(bfin_read_DMC0_STAT() & MEMINITDONE))
- continue;
-
- dlldatacycle = (bfin_read_DMC0_STAT() & PHYRDPHASE) >> PHYRDPHASE_OFFSET;
- dll_ctl = bfin_read_DMC0_DLLCTL();
- dll_ctl &= ~DATACYC;
- bfin_write_DMC0_DLLCTL(dll_ctl | (dlldatacycle << DATACYC_OFFSET));
-
- while (!(bfin_read_DMC0_STAT() & DLLCALDONE))
- continue;
-}
-#endif
-
-#endif /*__MEM_INIT_H__*/
-
+++ /dev/null
-/*
- * Common Blackfin memory map
- *
- * Copyright 2004-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MEM_MAP_H__
-#define __BFIN_MEM_MAP_H__
-
-#include <mach/mem_map.h>
-
-/* Every Blackfin so far has MMRs like this */
-#ifndef COREMMR_BASE
-# define COREMMR_BASE 0xFFE00000
-#endif
-#ifndef SYSMMR_BASE
-# define SYSMMR_BASE 0xFFC00000
-#endif
-
-/* Every Blackfin so far has on-chip Scratch Pad SRAM like this */
-#ifndef L1_SCRATCH_START
-# define L1_SCRATCH_START 0xFFB00000
-# define L1_SCRATCH_LENGTH 0x1000
-#endif
-
-/* Most parts lack on-chip L2 SRAM */
-#ifndef L2_START
-# define L2_START 0
-# define L2_LENGTH 0
-#endif
-
-/* Most parts lack on-chip L1 ROM */
-#ifndef L1_ROM_START
-# define L1_ROM_START 0
-# define L1_ROM_LENGTH 0
-#endif
-
-/* Allow wonky SMP ports to override this */
-#ifndef GET_PDA_SAFE
-# define GET_PDA_SAFE(preg) \
- preg.l = _cpu_pda; \
- preg.h = _cpu_pda;
-# define GET_PDA(preg, dreg) GET_PDA_SAFE(preg)
-
-# ifndef __ASSEMBLY__
-
-static inline unsigned long get_l1_scratch_start_cpu(int cpu)
-{
- return L1_SCRATCH_START;
-}
-static inline unsigned long get_l1_code_start_cpu(int cpu)
-{
- return L1_CODE_START;
-}
-static inline unsigned long get_l1_data_a_start_cpu(int cpu)
-{
- return L1_DATA_A_START;
-}
-static inline unsigned long get_l1_data_b_start_cpu(int cpu)
-{
- return L1_DATA_B_START;
-}
-static inline unsigned long get_l1_scratch_start(void)
-{
- return get_l1_scratch_start_cpu(0);
-}
-static inline unsigned long get_l1_code_start(void)
-{
- return get_l1_code_start_cpu(0);
-}
-static inline unsigned long get_l1_data_a_start(void)
-{
- return get_l1_data_a_start_cpu(0);
-}
-static inline unsigned long get_l1_data_b_start(void)
-{
- return get_l1_data_b_start_cpu(0);
-}
-
-# endif /* __ASSEMBLY__ */
-#endif /* !GET_PDA_SAFE */
-
-#endif
+++ /dev/null
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2002 David McCullough <davidm@snapgear.com>
- *
- * Licensed under the GPL-2.
- */
-
-#ifndef __MMU_H
-#define __MMU_H
-
-struct sram_list_struct {
- struct sram_list_struct *next;
- void *addr;
- size_t length;
-};
-
-typedef struct {
- unsigned long end_brk;
- unsigned long stack_start;
-
- /* Points to the location in SDRAM where the L1 stack is normally
- saved, or NULL if the stack is always in SDRAM. */
- void *l1_stack_save;
-
- struct sram_list_struct *sram_list;
-
-#ifdef CONFIG_BINFMT_ELF_FDPIC
- unsigned long exec_fdpic_loadmap;
- unsigned long interp_fdpic_loadmap;
-#endif
-#ifdef CONFIG_MPU
- unsigned long *page_rwx_mask;
-#endif
-} mm_context_t;
-
-#endif
+++ /dev/null
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BLACKFIN_MMU_CONTEXT_H__
-#define __BLACKFIN_MMU_CONTEXT_H__
-
-#include <linux/slab.h>
-#include <linux/sched.h>
-#include <linux/mm_types.h>
-
-#include <asm/setup.h>
-#include <asm/page.h>
-#include <asm/pgalloc.h>
-#include <asm/cplbinit.h>
-#include <asm/sections.h>
-
-/* Note: L1 stacks are CPU-private things, so we bluntly disable this
- feature in SMP mode, and use the per-CPU scratch SRAM bank only to
- store the PDA instead. */
-
-extern void *current_l1_stack_save;
-extern int nr_l1stack_tasks;
-extern void *l1_stack_base;
-extern unsigned long l1_stack_len;
-
-extern int l1sram_free(const void*);
-extern void *l1sram_alloc_max(void*);
-
-static inline void free_l1stack(void)
-{
- nr_l1stack_tasks--;
- if (nr_l1stack_tasks == 0) {
- l1sram_free(l1_stack_base);
- l1_stack_base = NULL;
- l1_stack_len = 0;
- }
-}
-
-static inline unsigned long
-alloc_l1stack(unsigned long length, unsigned long *stack_base)
-{
- if (nr_l1stack_tasks == 0) {
- l1_stack_base = l1sram_alloc_max(&l1_stack_len);
- if (!l1_stack_base)
- return 0;
- }
-
- if (l1_stack_len < length) {
- if (nr_l1stack_tasks == 0)
- l1sram_free(l1_stack_base);
- return 0;
- }
- *stack_base = (unsigned long)l1_stack_base;
- nr_l1stack_tasks++;
- return l1_stack_len;
-}
-
-static inline int
-activate_l1stack(struct mm_struct *mm, unsigned long sp_base)
-{
- if (current_l1_stack_save)
- memcpy(current_l1_stack_save, l1_stack_base, l1_stack_len);
- mm->context.l1_stack_save = current_l1_stack_save = (void*)sp_base;
- memcpy(l1_stack_base, current_l1_stack_save, l1_stack_len);
- return 1;
-}
-
-#define deactivate_mm(tsk,mm) do { } while (0)
-
-#define activate_mm(prev, next) switch_mm(prev, next, NULL)
-
-static inline void __switch_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm,
- struct task_struct *tsk)
-{
-#ifdef CONFIG_MPU
- unsigned int cpu = smp_processor_id();
-#endif
- if (prev_mm == next_mm)
- return;
-#ifdef CONFIG_MPU
- if (prev_mm->context.page_rwx_mask == current_rwx_mask[cpu]) {
- flush_switched_cplbs(cpu);
- set_mask_dcplbs(next_mm->context.page_rwx_mask, cpu);
- }
-#endif
-
-#ifdef CONFIG_APP_STACK_L1
- /* L1 stack switching. */
- if (!next_mm->context.l1_stack_save)
- return;
- if (next_mm->context.l1_stack_save == current_l1_stack_save)
- return;
- if (current_l1_stack_save) {
- memcpy(current_l1_stack_save, l1_stack_base, l1_stack_len);
- }
- current_l1_stack_save = next_mm->context.l1_stack_save;
- memcpy(l1_stack_base, current_l1_stack_save, l1_stack_len);
-#endif
-}
-
-#ifdef CONFIG_IPIPE
-#define lock_mm_switch(flags) flags = hard_local_irq_save_cond()
-#define unlock_mm_switch(flags) hard_local_irq_restore_cond(flags)
-#else
-#define lock_mm_switch(flags) do { (void)(flags); } while (0)
-#define unlock_mm_switch(flags) do { (void)(flags); } while (0)
-#endif /* CONFIG_IPIPE */
-
-#ifdef CONFIG_MPU
-static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
- struct task_struct *tsk)
-{
- unsigned long flags;
- lock_mm_switch(flags);
- __switch_mm(prev, next, tsk);
- unlock_mm_switch(flags);
-}
-
-static inline void protect_page(struct mm_struct *mm, unsigned long addr,
- unsigned long flags)
-{
- unsigned long *mask = mm->context.page_rwx_mask;
- unsigned long page;
- unsigned long idx;
- unsigned long bit;
-
- if (unlikely(addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE))
- page = (addr - (ASYNC_BANK0_BASE - _ramend)) >> 12;
- else
- page = addr >> 12;
- idx = page >> 5;
- bit = 1 << (page & 31);
-
- if (flags & VM_READ)
- mask[idx] |= bit;
- else
- mask[idx] &= ~bit;
- mask += page_mask_nelts;
- if (flags & VM_WRITE)
- mask[idx] |= bit;
- else
- mask[idx] &= ~bit;
- mask += page_mask_nelts;
- if (flags & VM_EXEC)
- mask[idx] |= bit;
- else
- mask[idx] &= ~bit;
-}
-
-static inline void update_protections(struct mm_struct *mm)
-{
- unsigned int cpu = smp_processor_id();
- if (mm->context.page_rwx_mask == current_rwx_mask[cpu]) {
- flush_switched_cplbs(cpu);
- set_mask_dcplbs(mm->context.page_rwx_mask, cpu);
- }
-}
-#else /* !CONFIG_MPU */
-static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
- struct task_struct *tsk)
-{
- __switch_mm(prev, next, tsk);
-}
-#endif
-
-static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
-{
-}
-
-/* Called when creating a new context during fork() or execve(). */
-static inline int
-init_new_context(struct task_struct *tsk, struct mm_struct *mm)
-{
-#ifdef CONFIG_MPU
- unsigned long p = __get_free_pages(GFP_KERNEL, page_mask_order);
- mm->context.page_rwx_mask = (unsigned long *)p;
- memset(mm->context.page_rwx_mask, 0,
- page_mask_nelts * 3 * sizeof(long));
-#endif
- return 0;
-}
-
-static inline void destroy_context(struct mm_struct *mm)
-{
- struct sram_list_struct *tmp;
-#ifdef CONFIG_MPU
- unsigned int cpu = smp_processor_id();
-#endif
-
-#ifdef CONFIG_APP_STACK_L1
- if (current_l1_stack_save == mm->context.l1_stack_save)
- current_l1_stack_save = 0;
- if (mm->context.l1_stack_save)
- free_l1stack();
-#endif
-
- while ((tmp = mm->context.sram_list)) {
- mm->context.sram_list = tmp->next;
- sram_free(tmp->addr);
- kfree(tmp);
- }
-#ifdef CONFIG_MPU
- if (current_rwx_mask[cpu] == mm->context.page_rwx_mask)
- current_rwx_mask[cpu] = NULL;
- free_pages((unsigned long)mm->context.page_rwx_mask, page_mask_order);
-#endif
-}
-
-#define ipipe_mm_switch_protect(flags) \
- flags = hard_local_irq_save_cond()
-
-#define ipipe_mm_switch_unprotect(flags) \
- hard_local_irq_restore_cond(flags)
-
-#endif
+++ /dev/null
-/*
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _ASM_BFIN_MODULE_H
-#define _ASM_BFIN_MODULE_H
-
-#include <asm-generic/module.h>
-
-struct mod_arch_specific {
- Elf_Shdr *text_l1;
- Elf_Shdr *data_a_l1;
- Elf_Shdr *bss_a_l1;
- Elf_Shdr *data_b_l1;
- Elf_Shdr *bss_b_l1;
- Elf_Shdr *text_l2;
- Elf_Shdr *data_l2;
- Elf_Shdr *bss_l2;
-};
-#endif /* _ASM_BFIN_MODULE_H */
+++ /dev/null
-/*
- * BF5XX - NAND flash controller platform_device info
- *
- * Copyright 2007-2008 Analog Devices, Inc.
- *
- * Licensed under the GPL-2
- */
-
-/* struct bf5xx_nand_platform
- *
- * define a interface between platform board specific code and
- * bf54x NFC driver.
- *
- * nr_partitions = number of partitions pointed to be partitoons (or zero)
- * partitions = mtd partition list
- */
-
-#define NFC_PG_SIZE_OFFSET 9
-
-#define NFC_NWIDTH_8 0
-#define NFC_NWIDTH_16 1
-#define NFC_NWIDTH_OFFSET 8
-
-#define NFC_RDDLY_OFFSET 4
-#define NFC_WRDLY_OFFSET 0
-
-#define NFC_STAT_NBUSY 1
-
-struct bf5xx_nand_platform {
- /* NAND chip information */
- unsigned short data_width;
-
- /* RD/WR strobe delay timing information, all times in SCLK cycles */
- unsigned short rd_dly;
- unsigned short wr_dly;
-
- /* NAND MTD partition information */
- int nr_partitions;
- struct mtd_partition *partitions;
-};
+++ /dev/null
-/*
- * Copyright 2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2
- */
-
-#ifndef _BFIN_NMI_H_
-#define _BFIN_NMI_H_
-
-#include <linux/nmi.h>
-
-extern void arch_touch_nmi_watchdog(void);
-
-#endif
+++ /dev/null
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BLACKFIN_PAGE_H
-#define _BLACKFIN_PAGE_H
-
-#define ARCH_PFN_OFFSET (CONFIG_PHY_RAM_BASE_ADDRESS >> PAGE_SHIFT)
-#define MAP_NR(addr) ((unsigned long)(addr) >> PAGE_SHIFT)
-
-#define VM_DATA_DEFAULT_FLAGS \
- (VM_READ | VM_WRITE | \
- ((current->personality & READ_IMPLIES_EXEC) ? VM_EXEC : 0 ) | \
- VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
-
-#include <asm-generic/page.h>
-#include <asm-generic/memory_model.h>
-#include <asm-generic/getorder.h>
-
-#endif
+++ /dev/null
-/*
- * This handles the memory map
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifdef CONFIG_BLACKFIN
-#define PAGE_OFFSET_RAW 0x00000000
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/* Changed from asm-m68k version, Lineo Inc. May 2001 */
-
-#ifndef _ASM_BFIN_PCI_H
-#define _ASM_BFIN_PCI_H
-
-#include <linux/scatterlist.h>
-#include <asm-generic/pci.h>
-
-#define PCIBIOS_MIN_IO 0x00001000
-#define PCIBIOS_MIN_MEM 0x10000000
-
-#endif /* _ASM_BFIN_PCI_H */
+++ /dev/null
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- * Philippe Gerum <rpm@xenomai.org>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _ASM_BLACKFIN_PDA_H
-#define _ASM_BLACKFIN_PDA_H
-
-#include <mach/anomaly.h>
-
-#ifndef __ASSEMBLY__
-
-struct blackfin_pda { /* Per-processor Data Area */
-#ifdef CONFIG_SMP
- struct blackfin_pda *next;
-#endif
-
- unsigned long syscfg;
-#ifdef CONFIG_SMP
- unsigned long imask; /* Current IMASK value */
-#endif
-
- unsigned long *ipdt; /* Start of switchable I-CPLB table */
- unsigned long *ipdt_swapcount; /* Number of swaps in ipdt */
- unsigned long *dpdt; /* Start of switchable D-CPLB table */
- unsigned long *dpdt_swapcount; /* Number of swaps in dpdt */
-
- /*
- * Single instructions can have multiple faults, which
- * need to be handled by traps.c, in irq5. We store
- * the exception cause to ensure we don't miss a
- * double fault condition
- */
- unsigned long ex_iptr;
- unsigned long ex_optr;
- unsigned long ex_buf[4];
- unsigned long ex_imask; /* Saved imask from exception */
- unsigned long ex_ipend; /* Saved IPEND from exception */
- unsigned long *ex_stack; /* Exception stack space */
-
-#ifdef ANOMALY_05000261
- unsigned long last_cplb_fault_retx;
-#endif
- unsigned long dcplb_fault_addr;
- unsigned long icplb_fault_addr;
- unsigned long retx;
- unsigned long seqstat;
- unsigned int __nmi_count; /* number of times NMI asserted on this CPU */
-#ifdef CONFIG_DEBUG_DOUBLEFAULT
- unsigned long dcplb_doublefault_addr;
- unsigned long icplb_doublefault_addr;
- unsigned long retx_doublefault;
- unsigned long seqstat_doublefault;
-#endif
-};
-
-struct blackfin_initial_pda {
- void *retx;
-#ifdef CONFIG_DEBUG_DOUBLEFAULT
- void *dcplb_doublefault_addr;
- void *icplb_doublefault_addr;
- void *retx_doublefault;
- unsigned seqstat_doublefault;
-#endif
-};
-
-extern struct blackfin_pda cpu_pda[];
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* _ASM_BLACKFIN_PDA_H */
+++ /dev/null
-#define MAX_HWEVENTS 2
+++ /dev/null
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BLACKFIN_PGTABLE_H
-#define _BLACKFIN_PGTABLE_H
-
-#include <asm-generic/4level-fixup.h>
-
-#include <asm/page.h>
-#include <asm/def_LPBlackfin.h>
-
-typedef pte_t *pte_addr_t;
-/*
-* Trivial page table functions.
-*/
-#define pgd_present(pgd) (1)
-#define pgd_none(pgd) (0)
-#define pgd_bad(pgd) (0)
-#define pgd_clear(pgdp)
-#define kern_addr_valid(addr) (1)
-
-#define pmd_offset(a, b) ((void *)0)
-#define pmd_none(x) (!pmd_val(x))
-#define pmd_present(x) (pmd_val(x))
-#define pmd_clear(xp) do { set_pmd(xp, __pmd(0)); } while (0)
-#define pmd_bad(x) (pmd_val(x) & ~PAGE_MASK)
-
-#define kern_addr_valid(addr) (1)
-
-#define PAGE_NONE __pgprot(0) /* these mean nothing to NO_MM */
-#define PAGE_SHARED __pgprot(0) /* these mean nothing to NO_MM */
-#define PAGE_COPY __pgprot(0) /* these mean nothing to NO_MM */
-#define PAGE_READONLY __pgprot(0) /* these mean nothing to NO_MM */
-#define PAGE_KERNEL __pgprot(0) /* these mean nothing to NO_MM */
-#define pgprot_noncached(prot) (prot)
-
-extern void paging_init(void);
-
-#define __swp_type(x) (0)
-#define __swp_offset(x) (0)
-#define __swp_entry(typ,off) ((swp_entry_t) { ((typ) | ((off) << 7)) })
-#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
-#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
-
-#define set_pte(pteptr, pteval) (*(pteptr) = pteval)
-#define set_pte_at(mm, addr, ptep, pteval) set_pte(ptep, pteval)
-
-/*
- * Page assess control based on Blackfin CPLB management
- */
-#define _PAGE_RD (CPLB_USER_RD)
-#define _PAGE_WR (CPLB_USER_WR)
-#define _PAGE_USER (CPLB_USER_RD | CPLB_USER_WR)
-#define _PAGE_ACCESSED CPLB_ALL_ACCESS
-#define _PAGE_DIRTY (CPLB_DIRTY)
-
-#define PTE_BIT_FUNC(fn, op) \
- static inline pte_t pte_##fn(pte_t _pte) { _pte.pte op; return _pte; }
-
-PTE_BIT_FUNC(rdprotect, &= ~_PAGE_RD);
-PTE_BIT_FUNC(mkread, |= _PAGE_RD);
-PTE_BIT_FUNC(wrprotect, &= ~_PAGE_WR);
-PTE_BIT_FUNC(mkwrite, |= _PAGE_WR);
-PTE_BIT_FUNC(exprotect, &= ~_PAGE_USER);
-PTE_BIT_FUNC(mkexec, |= _PAGE_USER);
-PTE_BIT_FUNC(mkclean, &= ~_PAGE_DIRTY);
-PTE_BIT_FUNC(mkdirty, |= _PAGE_DIRTY);
-PTE_BIT_FUNC(mkold, &= ~_PAGE_ACCESSED);
-PTE_BIT_FUNC(mkyoung, |= _PAGE_ACCESSED);
-
-/*
- * ZERO_PAGE is a global shared page that is always zero: used
- * for zero-mapped memory areas etc..
- */
-#define ZERO_PAGE(vaddr) virt_to_page(empty_zero_page)
-extern char empty_zero_page[];
-
-#define swapper_pg_dir ((pgd_t *) 0)
-/*
- * No page table caches to initialise.
- */
-#define pgtable_cache_init() do { } while (0)
-
-/*
- * All 32bit addresses are effectively valid for vmalloc...
- * Sort of meaningless for non-VM targets.
- */
-#define VMALLOC_START 0
-#define VMALLOC_END 0xffffffff
-
-/* provide a special get_unmapped_area for framebuffer mmaps of nommu */
-extern unsigned long get_fb_unmapped_area(struct file *filp, unsigned long,
- unsigned long, unsigned long,
- unsigned long);
-#define HAVE_ARCH_FB_UNMAPPED_AREA
-
-#define pgprot_writecombine pgprot_noncached
-
-#include <asm-generic/pgtable.h>
-
-#endif /* _BLACKFIN_PGTABLE_H */
+++ /dev/null
-/*
- * Blackfin bf609 power management
- *
- * Copyright 2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2
- */
-
-#ifndef __PM_H__
-#define __PM_H__
-
-#include <linux/suspend.h>
-
-struct bfin_cpu_pm_fns {
- void (*save)(unsigned long *);
- void (*restore)(unsigned long *);
- int (*valid)(suspend_state_t state);
- void (*enter)(suspend_state_t state);
- int (*prepare)(void);
- void (*finish)(void);
-};
-
-extern struct bfin_cpu_pm_fns *bfin_cpu_pm;
-
-# ifdef CONFIG_BFIN_COREB
-void bfin_coreb_start(void);
-void bfin_coreb_stop(void);
-void bfin_coreb_reset(void);
-# endif
-
-#endif
+++ /dev/null
-/*
- * Common header file for Blackfin family of processors
- *
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _PORTMUX_H_
-#define _PORTMUX_H_
-
-#define P_IDENT(x) ((x) & 0x1FF)
-#define P_FUNCT(x) (((x) & 0x3) << 9)
-#define P_FUNCT2MUX(x) (((x) >> 9) & 0x3)
-#define P_DEFINED 0x8000
-#define P_UNDEF 0x4000
-#define P_MAYSHARE 0x2000
-#define P_DONTCARE 0x1000
-
-#ifdef CONFIG_PINCTRL
-int bfin_internal_set_wake(unsigned int irq, unsigned int state);
-
-#define gpio_pint_regs bfin_pint_regs
-#define adi_internal_set_wake bfin_internal_set_wake
-
-#define peripheral_request(per, label) (0)
-#define peripheral_free(per)
-#define peripheral_request_list(per, label) (0)
-#define peripheral_free_list(per)
-#else
-int peripheral_request(unsigned short per, const char *label);
-void peripheral_free(unsigned short per);
-int peripheral_request_list(const unsigned short per[], const char *label);
-void peripheral_free_list(const unsigned short per[]);
-#endif
-
-#include <linux/err.h>
-#include <linux/pinctrl/pinctrl.h>
-#include <mach/portmux.h>
-#include <mach/gpio.h>
-
-#ifndef P_SPORT2_TFS
-#define P_SPORT2_TFS P_UNDEF
-#endif
-
-#ifndef P_SPORT2_DTSEC
-#define P_SPORT2_DTSEC P_UNDEF
-#endif
-
-#ifndef P_SPORT2_DTPRI
-#define P_SPORT2_DTPRI P_UNDEF
-#endif
-
-#ifndef P_SPORT2_TSCLK
-#define P_SPORT2_TSCLK P_UNDEF
-#endif
-
-#ifndef P_SPORT2_RFS
-#define P_SPORT2_RFS P_UNDEF
-#endif
-
-#ifndef P_SPORT2_DRSEC
-#define P_SPORT2_DRSEC P_UNDEF
-#endif
-
-#ifndef P_SPORT2_DRPRI
-#define P_SPORT2_DRPRI P_UNDEF
-#endif
-
-#ifndef P_SPORT2_RSCLK
-#define P_SPORT2_RSCLK P_UNDEF
-#endif
-
-#ifndef P_SPORT3_TFS
-#define P_SPORT3_TFS P_UNDEF
-#endif
-
-#ifndef P_SPORT3_DTSEC
-#define P_SPORT3_DTSEC P_UNDEF
-#endif
-
-#ifndef P_SPORT3_DTPRI
-#define P_SPORT3_DTPRI P_UNDEF
-#endif
-
-#ifndef P_SPORT3_TSCLK
-#define P_SPORT3_TSCLK P_UNDEF
-#endif
-
-#ifndef P_SPORT3_RFS
-#define P_SPORT3_RFS P_UNDEF
-#endif
-
-#ifndef P_SPORT3_DRSEC
-#define P_SPORT3_DRSEC P_UNDEF
-#endif
-
-#ifndef P_SPORT3_DRPRI
-#define P_SPORT3_DRPRI P_UNDEF
-#endif
-
-#ifndef P_SPORT3_RSCLK
-#define P_SPORT3_RSCLK P_UNDEF
-#endif
-
-#ifndef P_TMR4
-#define P_TMR4 P_UNDEF
-#endif
-
-#ifndef P_TMR5
-#define P_TMR5 P_UNDEF
-#endif
-
-#ifndef P_TMR6
-#define P_TMR6 P_UNDEF
-#endif
-
-#ifndef P_TMR7
-#define P_TMR7 P_UNDEF
-#endif
-
-#ifndef P_TWI1_SCL
-#define P_TWI1_SCL P_UNDEF
-#endif
-
-#ifndef P_TWI1_SDA
-#define P_TWI1_SDA P_UNDEF
-#endif
-
-#ifndef P_UART3_RTS
-#define P_UART3_RTS P_UNDEF
-#endif
-
-#ifndef P_UART3_CTS
-#define P_UART3_CTS P_UNDEF
-#endif
-
-#ifndef P_UART2_TX
-#define P_UART2_TX P_UNDEF
-#endif
-
-#ifndef P_UART2_RX
-#define P_UART2_RX P_UNDEF
-#endif
-
-#ifndef P_UART3_TX
-#define P_UART3_TX P_UNDEF
-#endif
-
-#ifndef P_UART3_RX
-#define P_UART3_RX P_UNDEF
-#endif
-
-#ifndef P_SPI2_SS
-#define P_SPI2_SS P_UNDEF
-#endif
-
-#ifndef P_SPI2_SSEL1
-#define P_SPI2_SSEL1 P_UNDEF
-#endif
-
-#ifndef P_SPI2_SSEL2
-#define P_SPI2_SSEL2 P_UNDEF
-#endif
-
-#ifndef P_SPI2_SSEL3
-#define P_SPI2_SSEL3 P_UNDEF
-#endif
-
-#ifndef P_SPI2_SSEL4
-#define P_SPI2_SSEL4 P_UNDEF
-#endif
-
-#ifndef P_SPI2_SSEL5
-#define P_SPI2_SSEL5 P_UNDEF
-#endif
-
-#ifndef P_SPI2_SSEL6
-#define P_SPI2_SSEL6 P_UNDEF
-#endif
-
-#ifndef P_SPI2_SSEL7
-#define P_SPI2_SSEL7 P_UNDEF
-#endif
-
-#ifndef P_SPI2_SCK
-#define P_SPI2_SCK P_UNDEF
-#endif
-
-#ifndef P_SPI2_MOSI
-#define P_SPI2_MOSI P_UNDEF
-#endif
-
-#ifndef P_SPI2_MISO
-#define P_SPI2_MISO P_UNDEF
-#endif
-
-#ifndef P_TMR0
-#define P_TMR0 P_UNDEF
-#endif
-
-#ifndef P_TMR1
-#define P_TMR1 P_UNDEF
-#endif
-
-#ifndef P_TMR2
-#define P_TMR2 P_UNDEF
-#endif
-
-#ifndef P_TMR3
-#define P_TMR3 P_UNDEF
-#endif
-
-#ifndef P_SPORT0_TFS
-#define P_SPORT0_TFS P_UNDEF
-#endif
-
-#ifndef P_SPORT0_DTSEC
-#define P_SPORT0_DTSEC P_UNDEF
-#endif
-
-#ifndef P_SPORT0_DTPRI
-#define P_SPORT0_DTPRI P_UNDEF
-#endif
-
-#ifndef P_SPORT0_TSCLK
-#define P_SPORT0_TSCLK P_UNDEF
-#endif
-
-#ifndef P_SPORT0_RFS
-#define P_SPORT0_RFS P_UNDEF
-#endif
-
-#ifndef P_SPORT0_DRSEC
-#define P_SPORT0_DRSEC P_UNDEF
-#endif
-
-#ifndef P_SPORT0_DRPRI
-#define P_SPORT0_DRPRI P_UNDEF
-#endif
-
-#ifndef P_SPORT0_RSCLK
-#define P_SPORT0_RSCLK P_UNDEF
-#endif
-
-#ifndef P_SD_D0
-#define P_SD_D0 P_UNDEF
-#endif
-
-#ifndef P_SD_D1
-#define P_SD_D1 P_UNDEF
-#endif
-
-#ifndef P_SD_D2
-#define P_SD_D2 P_UNDEF
-#endif
-
-#ifndef P_SD_D3
-#define P_SD_D3 P_UNDEF
-#endif
-
-#ifndef P_SD_CLK
-#define P_SD_CLK P_UNDEF
-#endif
-
-#ifndef P_SD_CMD
-#define P_SD_CMD P_UNDEF
-#endif
-
-#ifndef P_MMCLK
-#define P_MMCLK P_UNDEF
-#endif
-
-#ifndef P_MBCLK
-#define P_MBCLK P_UNDEF
-#endif
-
-#ifndef P_PPI1_D0
-#define P_PPI1_D0 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D1
-#define P_PPI1_D1 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D2
-#define P_PPI1_D2 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D3
-#define P_PPI1_D3 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D4
-#define P_PPI1_D4 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D5
-#define P_PPI1_D5 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D6
-#define P_PPI1_D6 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D7
-#define P_PPI1_D7 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D8
-#define P_PPI1_D8 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D9
-#define P_PPI1_D9 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D10
-#define P_PPI1_D10 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D11
-#define P_PPI1_D11 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D12
-#define P_PPI1_D12 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D13
-#define P_PPI1_D13 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D14
-#define P_PPI1_D14 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D15
-#define P_PPI1_D15 P_UNDEF
-#endif
-
-#ifndef P_HOST_D8
-#define P_HOST_D8 P_UNDEF
-#endif
-
-#ifndef P_HOST_D9
-#define P_HOST_D9 P_UNDEF
-#endif
-
-#ifndef P_HOST_D10
-#define P_HOST_D10 P_UNDEF
-#endif
-
-#ifndef P_HOST_D11
-#define P_HOST_D11 P_UNDEF
-#endif
-
-#ifndef P_HOST_D12
-#define P_HOST_D12 P_UNDEF
-#endif
-
-#ifndef P_HOST_D13
-#define P_HOST_D13 P_UNDEF
-#endif
-
-#ifndef P_HOST_D14
-#define P_HOST_D14 P_UNDEF
-#endif
-
-#ifndef P_HOST_D15
-#define P_HOST_D15 P_UNDEF
-#endif
-
-#ifndef P_HOST_D0
-#define P_HOST_D0 P_UNDEF
-#endif
-
-#ifndef P_HOST_D1
-#define P_HOST_D1 P_UNDEF
-#endif
-
-#ifndef P_HOST_D2
-#define P_HOST_D2 P_UNDEF
-#endif
-
-#ifndef P_HOST_D3
-#define P_HOST_D3 P_UNDEF
-#endif
-
-#ifndef P_HOST_D4
-#define P_HOST_D4 P_UNDEF
-#endif
-
-#ifndef P_HOST_D5
-#define P_HOST_D5 P_UNDEF
-#endif
-
-#ifndef P_HOST_D6
-#define P_HOST_D6 P_UNDEF
-#endif
-
-#ifndef P_HOST_D7
-#define P_HOST_D7 P_UNDEF
-#endif
-
-#ifndef P_SPORT1_TFS
-#define P_SPORT1_TFS P_UNDEF
-#endif
-
-#ifndef P_SPORT1_DTSEC
-#define P_SPORT1_DTSEC P_UNDEF
-#endif
-
-#ifndef P_SPORT1_DTPRI
-#define P_SPORT1_DTPRI P_UNDEF
-#endif
-
-#ifndef P_SPORT1_TSCLK
-#define P_SPORT1_TSCLK P_UNDEF
-#endif
-
-#ifndef P_SPORT1_RFS
-#define P_SPORT1_RFS P_UNDEF
-#endif
-
-#ifndef P_SPORT1_DRSEC
-#define P_SPORT1_DRSEC P_UNDEF
-#endif
-
-#ifndef P_SPORT1_DRPRI
-#define P_SPORT1_DRPRI P_UNDEF
-#endif
-
-#ifndef P_SPORT1_RSCLK
-#define P_SPORT1_RSCLK P_UNDEF
-#endif
-
-#ifndef P_PPI2_D0
-#define P_PPI2_D0 P_UNDEF
-#endif
-
-#ifndef P_PPI2_D1
-#define P_PPI2_D1 P_UNDEF
-#endif
-
-#ifndef P_PPI2_D2
-#define P_PPI2_D2 P_UNDEF
-#endif
-
-#ifndef P_PPI2_D3
-#define P_PPI2_D3 P_UNDEF
-#endif
-
-#ifndef P_PPI2_D4
-#define P_PPI2_D4 P_UNDEF
-#endif
-
-#ifndef P_PPI2_D5
-#define P_PPI2_D5 P_UNDEF
-#endif
-
-#ifndef P_PPI2_D6
-#define P_PPI2_D6 P_UNDEF
-#endif
-
-#ifndef P_PPI2_D7
-#define P_PPI2_D7 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D18
-#define P_PPI0_D18 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D19
-#define P_PPI0_D19 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D20
-#define P_PPI0_D20 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D21
-#define P_PPI0_D21 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D22
-#define P_PPI0_D22 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D23
-#define P_PPI0_D23 P_UNDEF
-#endif
-
-#ifndef P_KEY_ROW0
-#define P_KEY_ROW0 P_UNDEF
-#endif
-
-#ifndef P_KEY_ROW1
-#define P_KEY_ROW1 P_UNDEF
-#endif
-
-#ifndef P_KEY_ROW2
-#define P_KEY_ROW2 P_UNDEF
-#endif
-
-#ifndef P_KEY_ROW3
-#define P_KEY_ROW3 P_UNDEF
-#endif
-
-#ifndef P_KEY_COL0
-#define P_KEY_COL0 P_UNDEF
-#endif
-
-#ifndef P_KEY_COL1
-#define P_KEY_COL1 P_UNDEF
-#endif
-
-#ifndef P_KEY_COL2
-#define P_KEY_COL2 P_UNDEF
-#endif
-
-#ifndef P_KEY_COL3
-#define P_KEY_COL3 P_UNDEF
-#endif
-
-#ifndef P_SPI0_SCK
-#define P_SPI0_SCK P_UNDEF
-#endif
-
-#ifndef P_SPI0_MISO
-#define P_SPI0_MISO P_UNDEF
-#endif
-
-#ifndef P_SPI0_MOSI
-#define P_SPI0_MOSI P_UNDEF
-#endif
-
-#ifndef P_SPI0_SS
-#define P_SPI0_SS P_UNDEF
-#endif
-
-#ifndef P_SPI0_SSEL1
-#define P_SPI0_SSEL1 P_UNDEF
-#endif
-
-#ifndef P_SPI0_SSEL2
-#define P_SPI0_SSEL2 P_UNDEF
-#endif
-
-#ifndef P_SPI0_SSEL3
-#define P_SPI0_SSEL3 P_UNDEF
-#endif
-
-#ifndef P_SPI0_SSEL4
-#define P_SPI0_SSEL4 P_UNDEF
-#endif
-
-#ifndef P_SPI0_SSEL5
-#define P_SPI0_SSEL5 P_UNDEF
-#endif
-
-#ifndef P_SPI0_SSEL6
-#define P_SPI0_SSEL6 P_UNDEF
-#endif
-
-#ifndef P_SPI0_SSEL7
-#define P_SPI0_SSEL7 P_UNDEF
-#endif
-
-#ifndef P_UART0_TX
-#define P_UART0_TX P_UNDEF
-#endif
-
-#ifndef P_UART0_RX
-#define P_UART0_RX P_UNDEF
-#endif
-
-#ifndef P_UART1_RTS
-#define P_UART1_RTS P_UNDEF
-#endif
-
-#ifndef P_UART1_CTS
-#define P_UART1_CTS P_UNDEF
-#endif
-
-#ifndef P_PPI1_CLK
-#define P_PPI1_CLK P_UNDEF
-#endif
-
-#ifndef P_PPI1_FS1
-#define P_PPI1_FS1 P_UNDEF
-#endif
-
-#ifndef P_PPI1_FS2
-#define P_PPI1_FS2 P_UNDEF
-#endif
-
-#ifndef P_TWI0_SCL
-#define P_TWI0_SCL P_UNDEF
-#endif
-
-#ifndef P_TWI0_SDA
-#define P_TWI0_SDA P_UNDEF
-#endif
-
-#ifndef P_KEY_COL7
-#define P_KEY_COL7 P_UNDEF
-#endif
-
-#ifndef P_KEY_ROW6
-#define P_KEY_ROW6 P_UNDEF
-#endif
-
-#ifndef P_KEY_COL6
-#define P_KEY_COL6 P_UNDEF
-#endif
-
-#ifndef P_KEY_ROW5
-#define P_KEY_ROW5 P_UNDEF
-#endif
-
-#ifndef P_KEY_COL5
-#define P_KEY_COL5 P_UNDEF
-#endif
-
-#ifndef P_KEY_ROW4
-#define P_KEY_ROW4 P_UNDEF
-#endif
-
-#ifndef P_KEY_COL4
-#define P_KEY_COL4 P_UNDEF
-#endif
-
-#ifndef P_KEY_ROW7
-#define P_KEY_ROW7 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D0
-#define P_PPI0_D0 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D1
-#define P_PPI0_D1 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D2
-#define P_PPI0_D2 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D3
-#define P_PPI0_D3 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D4
-#define P_PPI0_D4 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D5
-#define P_PPI0_D5 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D6
-#define P_PPI0_D6 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D7
-#define P_PPI0_D7 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D8
-#define P_PPI0_D8 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D9
-#define P_PPI0_D9 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D10
-#define P_PPI0_D10 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D11
-#define P_PPI0_D11 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D12
-#define P_PPI0_D12 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D13
-#define P_PPI0_D13 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D14
-#define P_PPI0_D14 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D15
-#define P_PPI0_D15 P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D0A
-#define P_ATAPI_D0A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D1A
-#define P_ATAPI_D1A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D2A
-#define P_ATAPI_D2A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D3A
-#define P_ATAPI_D3A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D4A
-#define P_ATAPI_D4A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D5A
-#define P_ATAPI_D5A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D6A
-#define P_ATAPI_D6A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D7A
-#define P_ATAPI_D7A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D8A
-#define P_ATAPI_D8A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D9A
-#define P_ATAPI_D9A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D10A
-#define P_ATAPI_D10A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D11A
-#define P_ATAPI_D11A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D12A
-#define P_ATAPI_D12A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D13A
-#define P_ATAPI_D13A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D14A
-#define P_ATAPI_D14A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D15A
-#define P_ATAPI_D15A P_UNDEF
-#endif
-
-#ifndef P_PPI0_CLK
-#define P_PPI0_CLK P_UNDEF
-#endif
-
-#ifndef P_PPI0_FS1
-#define P_PPI0_FS1 P_UNDEF
-#endif
-
-#ifndef P_PPI0_FS2
-#define P_PPI0_FS2 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D16
-#define P_PPI0_D16 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D17
-#define P_PPI0_D17 P_UNDEF
-#endif
-
-#ifndef P_SPI1_SSEL1
-#define P_SPI1_SSEL1 P_UNDEF
-#endif
-
-#ifndef P_SPI1_SSEL2
-#define P_SPI1_SSEL2 P_UNDEF
-#endif
-
-#ifndef P_SPI1_SSEL3
-#define P_SPI1_SSEL3 P_UNDEF
-#endif
-
-
-#ifndef P_SPI1_SSEL4
-#define P_SPI1_SSEL4 P_UNDEF
-#endif
-
-#ifndef P_SPI1_SSEL5
-#define P_SPI1_SSEL5 P_UNDEF
-#endif
-
-#ifndef P_SPI1_SSEL6
-#define P_SPI1_SSEL6 P_UNDEF
-#endif
-
-#ifndef P_SPI1_SSEL7
-#define P_SPI1_SSEL7 P_UNDEF
-#endif
-
-#ifndef P_SPI1_SCK
-#define P_SPI1_SCK P_UNDEF
-#endif
-
-#ifndef P_SPI1_MISO
-#define P_SPI1_MISO P_UNDEF
-#endif
-
-#ifndef P_SPI1_MOSI
-#define P_SPI1_MOSI P_UNDEF
-#endif
-
-#ifndef P_SPI1_SS
-#define P_SPI1_SS P_UNDEF
-#endif
-
-#ifndef P_CAN0_TX
-#define P_CAN0_TX P_UNDEF
-#endif
-
-#ifndef P_CAN0_RX
-#define P_CAN0_RX P_UNDEF
-#endif
-
-#ifndef P_CAN1_TX
-#define P_CAN1_TX P_UNDEF
-#endif
-
-#ifndef P_CAN1_RX
-#define P_CAN1_RX P_UNDEF
-#endif
-
-#ifndef P_ATAPI_A0A
-#define P_ATAPI_A0A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_A1A
-#define P_ATAPI_A1A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_A2A
-#define P_ATAPI_A2A P_UNDEF
-#endif
-
-#ifndef P_HOST_CE
-#define P_HOST_CE P_UNDEF
-#endif
-
-#ifndef P_HOST_RD
-#define P_HOST_RD P_UNDEF
-#endif
-
-#ifndef P_HOST_WR
-#define P_HOST_WR P_UNDEF
-#endif
-
-#ifndef P_MTXONB
-#define P_MTXONB P_UNDEF
-#endif
-
-#ifndef P_PPI2_FS2
-#define P_PPI2_FS2 P_UNDEF
-#endif
-
-#ifndef P_PPI2_FS1
-#define P_PPI2_FS1 P_UNDEF
-#endif
-
-#ifndef P_PPI2_CLK
-#define P_PPI2_CLK P_UNDEF
-#endif
-
-#ifndef P_CNT_CZM
-#define P_CNT_CZM P_UNDEF
-#endif
-
-#ifndef P_UART1_TX
-#define P_UART1_TX P_UNDEF
-#endif
-
-#ifndef P_UART1_RX
-#define P_UART1_RX P_UNDEF
-#endif
-
-#ifndef P_ATAPI_RESET
-#define P_ATAPI_RESET P_UNDEF
-#endif
-
-#ifndef P_HOST_ADDR
-#define P_HOST_ADDR P_UNDEF
-#endif
-
-#ifndef P_HOST_ACK
-#define P_HOST_ACK P_UNDEF
-#endif
-
-#ifndef P_MTX
-#define P_MTX P_UNDEF
-#endif
-
-#ifndef P_MRX
-#define P_MRX P_UNDEF
-#endif
-
-#ifndef P_MRXONB
-#define P_MRXONB P_UNDEF
-#endif
-
-#ifndef P_A4
-#define P_A4 P_UNDEF
-#endif
-
-#ifndef P_A5
-#define P_A5 P_UNDEF
-#endif
-
-#ifndef P_A6
-#define P_A6 P_UNDEF
-#endif
-
-#ifndef P_A7
-#define P_A7 P_UNDEF
-#endif
-
-#ifndef P_A8
-#define P_A8 P_UNDEF
-#endif
-
-#ifndef P_A9
-#define P_A9 P_UNDEF
-#endif
-
-#ifndef P_PPI1_FS3
-#define P_PPI1_FS3 P_UNDEF
-#endif
-
-#ifndef P_PPI2_FS3
-#define P_PPI2_FS3 P_UNDEF
-#endif
-
-#ifndef P_TMR8
-#define P_TMR8 P_UNDEF
-#endif
-
-#ifndef P_TMR9
-#define P_TMR9 P_UNDEF
-#endif
-
-#ifndef P_TMR10
-#define P_TMR10 P_UNDEF
-#endif
-#ifndef P_TMR11
-#define P_TMR11 P_UNDEF
-#endif
-
-#ifndef P_DMAR0
-#define P_DMAR0 P_UNDEF
-#endif
-
-#ifndef P_DMAR1
-#define P_DMAR1 P_UNDEF
-#endif
-
-#ifndef P_PPI0_FS3
-#define P_PPI0_FS3 P_UNDEF
-#endif
-
-#ifndef P_CNT_CDG
-#define P_CNT_CDG P_UNDEF
-#endif
-
-#ifndef P_CNT_CUD
-#define P_CNT_CUD P_UNDEF
-#endif
-
-#ifndef P_A10
-#define P_A10 P_UNDEF
-#endif
-
-#ifndef P_A11
-#define P_A11 P_UNDEF
-#endif
-
-#ifndef P_A12
-#define P_A12 P_UNDEF
-#endif
-
-#ifndef P_A13
-#define P_A13 P_UNDEF
-#endif
-
-#ifndef P_A14
-#define P_A14 P_UNDEF
-#endif
-
-#ifndef P_A15
-#define P_A15 P_UNDEF
-#endif
-
-#ifndef P_A16
-#define P_A16 P_UNDEF
-#endif
-
-#ifndef P_A17
-#define P_A17 P_UNDEF
-#endif
-
-#ifndef P_A18
-#define P_A18 P_UNDEF
-#endif
-
-#ifndef P_A19
-#define P_A19 P_UNDEF
-#endif
-
-#ifndef P_A20
-#define P_A20 P_UNDEF
-#endif
-
-#ifndef P_A21
-#define P_A21 P_UNDEF
-#endif
-
-#ifndef P_A22
-#define P_A22 P_UNDEF
-#endif
-
-#ifndef P_A23
-#define P_A23 P_UNDEF
-#endif
-
-#ifndef P_A24
-#define P_A24 P_UNDEF
-#endif
-
-#ifndef P_A25
-#define P_A25 P_UNDEF
-#endif
-
-#ifndef P_NOR_CLK
-#define P_NOR_CLK P_UNDEF
-#endif
-
-#ifndef P_TMRCLK
-#define P_TMRCLK P_UNDEF
-#endif
-
-#ifndef P_AMC_ARDY_NOR_WAIT
-#define P_AMC_ARDY_NOR_WAIT P_UNDEF
-#endif
-
-#ifndef P_NAND_CE
-#define P_NAND_CE P_UNDEF
-#endif
-
-#ifndef P_NAND_RB
-#define P_NAND_RB P_UNDEF
-#endif
-
-#ifndef P_ATAPI_DIOR
-#define P_ATAPI_DIOR P_UNDEF
-#endif
-
-#ifndef P_ATAPI_DIOW
-#define P_ATAPI_DIOW P_UNDEF
-#endif
-
-#ifndef P_ATAPI_CS0
-#define P_ATAPI_CS0 P_UNDEF
-#endif
-
-#ifndef P_ATAPI_CS1
-#define P_ATAPI_CS1 P_UNDEF
-#endif
-
-#ifndef P_ATAPI_DMACK
-#define P_ATAPI_DMACK P_UNDEF
-#endif
-
-#ifndef P_ATAPI_DMARQ
-#define P_ATAPI_DMARQ P_UNDEF
-#endif
-
-#ifndef P_ATAPI_INTRQ
-#define P_ATAPI_INTRQ P_UNDEF
-#endif
-
-#ifndef P_ATAPI_IORDY
-#define P_ATAPI_IORDY P_UNDEF
-#endif
-
-#ifndef P_AMC_BR
-#define P_AMC_BR P_UNDEF
-#endif
-
-#ifndef P_AMC_BG
-#define P_AMC_BG P_UNDEF
-#endif
-
-#ifndef P_AMC_BGH
-#define P_AMC_BGH P_UNDEF
-#endif
-
-/* EMAC */
-
-#ifndef P_MII0_ETxD0
-#define P_MII0_ETxD0 P_UNDEF
-#endif
-
-#ifndef P_MII0_ETxD1
-#define P_MII0_ETxD1 P_UNDEF
-#endif
-
-#ifndef P_MII0_ETxD2
-#define P_MII0_ETxD2 P_UNDEF
-#endif
-
-#ifndef P_MII0_ETxD3
-#define P_MII0_ETxD3 P_UNDEF
-#endif
-
-#ifndef P_MII0_ETxEN
-#define P_MII0_ETxEN P_UNDEF
-#endif
-
-#ifndef P_MII0_TxCLK
-#define P_MII0_TxCLK P_UNDEF
-#endif
-
-#ifndef P_MII0_PHYINT
-#define P_MII0_PHYINT P_UNDEF
-#endif
-
-#ifndef P_MII0_COL
-#define P_MII0_COL P_UNDEF
-#endif
-
-#ifndef P_MII0_ERxD0
-#define P_MII0_ERxD0 P_UNDEF
-#endif
-
-#ifndef P_MII0_ERxD1
-#define P_MII0_ERxD1 P_UNDEF
-#endif
-
-#ifndef P_MII0_ERxD2
-#define P_MII0_ERxD2 P_UNDEF
-#endif
-
-#ifndef P_MII0_ERxD3
-#define P_MII0_ERxD3 P_UNDEF
-#endif
-
-#ifndef P_MII0_ERxDV
-#define P_MII0_ERxDV P_UNDEF
-#endif
-
-#ifndef P_MII0_ERxCLK
-#define P_MII0_ERxCLK P_UNDEF
-#endif
-
-#ifndef P_MII0_ERxER
-#define P_MII0_ERxER P_UNDEF
-#endif
-
-#ifndef P_MII0_CRS
-#define P_MII0_CRS P_UNDEF
-#endif
-
-#ifndef P_RMII0_REF_CLK
-#define P_RMII0_REF_CLK P_UNDEF
-#endif
-
-#ifndef P_RMII0_MDINT
-#define P_RMII0_MDINT P_UNDEF
-#endif
-
-#ifndef P_RMII0_CRS_DV
-#define P_RMII0_CRS_DV P_UNDEF
-#endif
-
-#ifndef P_MDC
-#define P_MDC P_UNDEF
-#endif
-
-#ifndef P_MDIO
-#define P_MDIO P_UNDEF
-#endif
-
-#endif /* _PORTMUX_H_ */
+++ /dev/null
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_BFIN_PROCESSOR_H
-#define __ASM_BFIN_PROCESSOR_H
-
-/*
- * Default implementation of macro that returns current
- * instruction pointer ("program counter").
- */
-#define current_text_addr() ({ __label__ _l; _l: &&_l;})
-
-#include <asm/ptrace.h>
-#include <mach/blackfin.h>
-
-static inline unsigned long rdusp(void)
-{
- unsigned long usp;
-
- __asm__ __volatile__("%0 = usp;\n\t":"=da"(usp));
- return usp;
-}
-
-static inline void wrusp(unsigned long usp)
-{
- __asm__ __volatile__("usp = %0;\n\t"::"da"(usp));
-}
-
-static inline unsigned long __get_SP(void)
-{
- unsigned long sp;
-
- __asm__ __volatile__("%0 = sp;\n\t" : "=da"(sp));
- return sp;
-}
-
-/*
- * User space process size: 1st byte beyond user address space.
- * Fairly meaningless on nommu. Parts of user programs can be scattered
- * in a lot of places, so just disable this by setting it to 0xFFFFFFFF.
- */
-#define TASK_SIZE 0xFFFFFFFF
-
-#ifdef __KERNEL__
-#define STACK_TOP TASK_SIZE
-#endif
-
-#define TASK_UNMAPPED_BASE 0
-
-struct thread_struct {
- unsigned long ksp; /* kernel stack pointer */
- unsigned long usp; /* user stack pointer */
- unsigned short seqstat; /* saved status register */
- unsigned long esp0; /* points to SR of stack frame pt_regs */
- unsigned long pc; /* instruction pointer */
- void * debuggerinfo;
-};
-
-#define INIT_THREAD { \
- sizeof(init_stack) + (unsigned long) init_stack, 0, \
- PS_S, 0, 0 \
-}
-
-extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
- unsigned long new_sp);
-
-/* Forward declaration, a strange C thing */
-struct task_struct;
-
-/* Free all resources held by a thread. */
-static inline void release_thread(struct task_struct *dead_task)
-{
-}
-
-unsigned long get_wchan(struct task_struct *p);
-
-#define KSTK_EIP(tsk) \
- ({ \
- unsigned long eip = 0; \
- if ((tsk)->thread.esp0 > PAGE_SIZE && \
- MAP_NR((tsk)->thread.esp0) < max_mapnr) \
- eip = ((struct pt_regs *) (tsk)->thread.esp0)->pc; \
- eip; })
-#define KSTK_ESP(tsk) ((tsk) == current ? rdusp() : (tsk)->thread.usp)
-
-#define cpu_relax() smp_mb()
-
-/* Get the Silicon Revision of the chip */
-static inline uint32_t __pure bfin_revid(void)
-{
- /* Always use CHIPID, to work around ANOMALY_05000234 */
- uint32_t revid = (bfin_read_CHIPID() & CHIPID_VERSION) >> 28;
-
-#ifdef _BOOTROM_GET_DXE_ADDRESS_TWI
- /*
- * ANOMALY_05000364
- * Incorrect Revision Number in DSPID Register
- */
- if (ANOMALY_05000364 &&
- bfin_read16(_BOOTROM_GET_DXE_ADDRESS_TWI) == 0x2796)
- revid = 1;
-#endif
-
- return revid;
-}
-
-static inline uint16_t __pure bfin_cpuid(void)
-{
- return (bfin_read_CHIPID() & CHIPID_FAMILY) >> 12;
-}
-
-static inline uint32_t __pure bfin_dspid(void)
-{
- return bfin_read_DSPID();
-}
-
-#define blackfin_core_id() (bfin_dspid() & 0xff)
-
-static inline uint32_t __pure bfin_compiled_revid(void)
-{
-#if defined(CONFIG_BF_REV_0_0)
- return 0;
-#elif defined(CONFIG_BF_REV_0_1)
- return 1;
-#elif defined(CONFIG_BF_REV_0_2)
- return 2;
-#elif defined(CONFIG_BF_REV_0_3)
- return 3;
-#elif defined(CONFIG_BF_REV_0_4)
- return 4;
-#elif defined(CONFIG_BF_REV_0_5)
- return 5;
-#elif defined(CONFIG_BF_REV_0_6)
- return 6;
-#elif defined(CONFIG_BF_REV_ANY)
- return 0xffff;
-#else
- return -1;
-#endif
-}
-
-#endif
+++ /dev/null
-/*
- * header file for pseudo instructions
- *
- * Copyright 2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BLACKFIN_PSEUDO_
-#define _BLACKFIN_PSEUDO_
-
-#include <linux/types.h>
-#include <asm/ptrace.h>
-
-extern bool execute_pseudodbg_assert(struct pt_regs *fp, unsigned int opcode);
-extern bool execute_pseudodbg(struct pt_regs *fp, unsigned int opcode);
-
-#endif
+++ /dev/null
-/*
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-#ifndef _BFIN_PTRACE_H
-#define _BFIN_PTRACE_H
-
-#include <uapi/asm/ptrace.h>
-
-#ifndef __ASSEMBLY__
-
-/* user_mode returns true if only one bit is set in IPEND, other than the
- master interrupt enable. */
-#define user_mode(regs) (!(((regs)->ipend & ~0x10) & (((regs)->ipend & ~0x10) - 1)))
-
-#define arch_has_single_step() (1)
-/* common code demands this function */
-#define ptrace_disable(child) user_disable_single_step(child)
-#define current_user_stack_pointer() rdusp()
-
-extern int is_user_addr_valid(struct task_struct *child,
- unsigned long start, unsigned long len);
-
-/*
- * Get the address of the live pt_regs for the specified task.
- * These are saved onto the top kernel stack when the process
- * is not running.
- *
- * Note: if a user thread is execve'd from kernel space, the
- * kernel stack will not be empty on entry to the kernel, so
- * ptracing these tasks will fail.
- */
-#define task_pt_regs(task) \
- (struct pt_regs *) \
- ((unsigned long)task_stack_page(task) + \
- (THREAD_SIZE - sizeof(struct pt_regs)))
-
-#include <asm-generic/ptrace.h>
-
-#endif /* __ASSEMBLY__ */
-#endif /* _BFIN_PTRACE_H */
+++ /dev/null
-/*
- * reboot.h - shutdown/reboot header
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_REBOOT_H__
-#define __ASM_REBOOT_H__
-
-/* optional board specific hooks */
-extern void native_machine_restart(char *cmd);
-extern void native_machine_halt(void);
-extern void native_machine_power_off(void);
-
-/* common reboot workarounds */
-extern void bfin_reset_boot_spi_cs(unsigned short pin);
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_BLACKFIN_RWLOCK_H
-#define _ASM_BLACKFIN_RWLOCK_H
-
-#define RW_LOCK_BIAS 0x01000000
-
-#endif
+++ /dev/null
-/*
- * arch/blackfin/mach-common/scb-init.c - reprogram system cross bar priority
- *
- * Copyright 2012 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#define SCB_SLOT_OFFSET 24
-#define SCB_MI_MAX_SLOT 32
-
-struct scb_mi_prio {
- unsigned long scb_mi_arbr;
- unsigned long scb_mi_arbw;
- unsigned char scb_mi_slots;
- unsigned char scb_mi_prio[SCB_MI_MAX_SLOT];
-};
-
-extern struct scb_mi_prio scb_data[];
-
-extern void init_scb(void);
+++ /dev/null
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BLACKFIN_SECTIONS_H
-#define _BLACKFIN_SECTIONS_H
-
-/* only used when MTD_UCLINUX */
-extern unsigned long memory_mtd_start, memory_mtd_end, mtd_size;
-
-extern unsigned long _ramstart, _ramend, _rambase;
-extern unsigned long memory_start, memory_end, physical_mem_end;
-
-/*
- * The weak markings on the lengths might seem weird, but this is required
- * in order to make gcc accept the fact that these may actually have a value
- * of 0 (since they aren't actually addresses, but sizes of sections).
- */
-extern char _stext_l1[], _etext_l1[], _text_l1_lma[], __weak _text_l1_len[];
-extern char _sdata_l1[], _edata_l1[], _sbss_l1[], _ebss_l1[],
- _data_l1_lma[], __weak _data_l1_len[];
-#ifdef CONFIG_ROMKERNEL
-extern char _data_lma[], _data_len[], _sinitdata[], _einitdata[], _init_data_lma[], _init_data_len[];
-#endif
-extern char _sdata_b_l1[], _edata_b_l1[], _sbss_b_l1[], _ebss_b_l1[],
- _data_b_l1_lma[], __weak _data_b_l1_len[];
-extern char _stext_l2[], _etext_l2[], _sdata_l2[], _edata_l2[],
- _sbss_l2[], _ebss_l2[], _l2_lma[], __weak _l2_len[];
-
-#include <asm/mem_map.h>
-
-/* Blackfin systems have discontinuous memory map and no virtualized memory */
-static inline int arch_is_kernel_text(unsigned long addr)
-{
- return
- (L1_CODE_LENGTH &&
- addr >= (unsigned long)_stext_l1 &&
- addr < (unsigned long)_etext_l1)
- ||
- (L2_LENGTH &&
- addr >= (unsigned long)_stext_l2 &&
- addr < (unsigned long)_etext_l2);
-}
-#define arch_is_kernel_text(addr) arch_is_kernel_text(addr)
-
-static inline int arch_is_kernel_data(unsigned long addr)
-{
- return
- (L1_DATA_A_LENGTH &&
- addr >= (unsigned long)_sdata_l1 &&
- addr < (unsigned long)_ebss_l1)
- ||
- (L1_DATA_B_LENGTH &&
- addr >= (unsigned long)_sdata_b_l1 &&
- addr < (unsigned long)_ebss_b_l1)
- ||
- (L2_LENGTH &&
- addr >= (unsigned long)_sdata_l2 &&
- addr < (unsigned long)_ebss_l2);
-}
-#define arch_is_kernel_data(addr) arch_is_kernel_data(addr)
-
-#include <asm-generic/sections.h>
-
-#endif
+++ /dev/null
-/*
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BFIN_SEGMENT_H
-#define _BFIN_SEGMENT_H
-
-#define KERNEL_DS (0x5)
-#define USER_DS (0x1)
-
-#endif /* _BFIN_SEGMENT_H */
+++ /dev/null
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- * Philippe Gerum <rpm@xenomai.org>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_BLACKFIN_SMP_H
-#define __ASM_BLACKFIN_SMP_H
-
-#include <linux/kernel.h>
-#include <linux/threads.h>
-#include <linux/cpumask.h>
-#include <linux/cache.h>
-#include <asm/blackfin.h>
-#include <mach/smp.h>
-
-#define raw_smp_processor_id() blackfin_core_id()
-
-extern void bfin_relocate_coreb_l1_mem(void);
-extern void arch_send_call_function_single_ipi(int cpu);
-extern void arch_send_call_function_ipi_mask(const struct cpumask *mask);
-
-#if defined(CONFIG_SMP) && defined(CONFIG_ICACHE_FLUSH_L1)
-asmlinkage void blackfin_icache_flush_range_l1(unsigned long *ptr);
-extern unsigned long blackfin_iflush_l1_entry[NR_CPUS];
-#endif
-
-struct corelock_slot {
- int lock;
-};
-extern struct corelock_slot corelock;
-
-#ifdef __ARCH_SYNC_CORE_ICACHE
-extern unsigned long icache_invld_count[NR_CPUS];
-#endif
-#ifdef __ARCH_SYNC_CORE_DCACHE
-extern unsigned long dcache_invld_count[NR_CPUS];
-#endif
-
-void smp_icache_flush_range_others(unsigned long start,
- unsigned long end);
-#ifdef CONFIG_HOTPLUG_CPU
-void coreb_die(void);
-void cpu_die(void);
-void platform_cpu_die(void);
-int __cpu_disable(void);
-int __cpu_die(unsigned int cpu);
-#endif
-
-void smp_timer_broadcast(const struct cpumask *mask);
-
-
-#endif /* !__ASM_BLACKFIN_SMP_H */
+++ /dev/null
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_SPINLOCK_H
-#define __BFIN_SPINLOCK_H
-
-#ifndef CONFIG_SMP
-# include <asm-generic/spinlock.h>
-#else
-
-#include <linux/atomic.h>
-#include <asm/processor.h>
-#include <asm/barrier.h>
-
-asmlinkage int __raw_spin_is_locked_asm(volatile int *ptr);
-asmlinkage void __raw_spin_lock_asm(volatile int *ptr);
-asmlinkage int __raw_spin_trylock_asm(volatile int *ptr);
-asmlinkage void __raw_spin_unlock_asm(volatile int *ptr);
-asmlinkage void __raw_read_lock_asm(volatile int *ptr);
-asmlinkage int __raw_read_trylock_asm(volatile int *ptr);
-asmlinkage void __raw_read_unlock_asm(volatile int *ptr);
-asmlinkage void __raw_write_lock_asm(volatile int *ptr);
-asmlinkage int __raw_write_trylock_asm(volatile int *ptr);
-asmlinkage void __raw_write_unlock_asm(volatile int *ptr);
-
-static inline int arch_spin_is_locked(arch_spinlock_t *lock)
-{
- return __raw_spin_is_locked_asm(&lock->lock);
-}
-
-static inline void arch_spin_lock(arch_spinlock_t *lock)
-{
- __raw_spin_lock_asm(&lock->lock);
-}
-
-static inline int arch_spin_trylock(arch_spinlock_t *lock)
-{
- return __raw_spin_trylock_asm(&lock->lock);
-}
-
-static inline void arch_spin_unlock(arch_spinlock_t *lock)
-{
- __raw_spin_unlock_asm(&lock->lock);
-}
-
-static inline void arch_read_lock(arch_rwlock_t *rw)
-{
- __raw_read_lock_asm(&rw->lock);
-}
-
-static inline int arch_read_trylock(arch_rwlock_t *rw)
-{
- return __raw_read_trylock_asm(&rw->lock);
-}
-
-static inline void arch_read_unlock(arch_rwlock_t *rw)
-{
- __raw_read_unlock_asm(&rw->lock);
-}
-
-static inline void arch_write_lock(arch_rwlock_t *rw)
-{
- __raw_write_lock_asm(&rw->lock);
-}
-
-static inline int arch_write_trylock(arch_rwlock_t *rw)
-{
- return __raw_write_trylock_asm(&rw->lock);
-}
-
-static inline void arch_write_unlock(arch_rwlock_t *rw)
-{
- __raw_write_unlock_asm(&rw->lock);
-}
-
-#endif
-
-#endif /* !__BFIN_SPINLOCK_H */
+++ /dev/null
-/*
- * Copyright 2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_SPINLOCK_TYPES_H
-#define __ASM_SPINLOCK_TYPES_H
-
-#ifndef __LINUX_SPINLOCK_TYPES_H
-# error "please don't include this file directly"
-#endif
-
-#include <asm/rwlock.h>
-
-typedef struct {
- volatile unsigned int lock;
-} arch_spinlock_t;
-
-#define __ARCH_SPIN_LOCK_UNLOCKED { 0 }
-
-typedef struct {
- volatile unsigned int lock;
-} arch_rwlock_t;
-
-#define __ARCH_RW_LOCK_UNLOCKED { RW_LOCK_BIAS }
-
-#endif
+++ /dev/null
-/*
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BLACKFIN_STRING_H_
-#define _BLACKFIN_STRING_H_
-
-#include <linux/types.h>
-
-#ifdef __KERNEL__ /* only set these up for kernel code */
-
-#define __HAVE_ARCH_STRCPY
-extern char *strcpy(char *dest, const char *src);
-
-#define __HAVE_ARCH_STRNCPY
-extern char *strncpy(char *dest, const char *src, size_t n);
-
-#define __HAVE_ARCH_STRCMP
-extern int strcmp(const char *cs, const char *ct);
-
-#define __HAVE_ARCH_STRNCMP
-extern int strncmp(const char *cs, const char *ct, size_t count);
-
-#define __HAVE_ARCH_MEMSET
-extern void *memset(void *s, int c, size_t count);
-#define __HAVE_ARCH_MEMCPY
-extern void *memcpy(void *d, const void *s, size_t count);
-#define __HAVE_ARCH_MEMCMP
-extern int memcmp(const void *, const void *, __kernel_size_t);
-#define __HAVE_ARCH_MEMCHR
-extern void *memchr(const void *s, int c, size_t n);
-#define __HAVE_ARCH_MEMMOVE
-extern void *memmove(void *dest, const void *src, size_t count);
-
-#endif /*__KERNEL__*/
-#endif /* _BLACKFIN_STRING_H_ */
+++ /dev/null
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * Tony Kou (tonyko@lineo.ca)
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _BLACKFIN_SWITCH_TO_H
-#define _BLACKFIN_SWITCH_TO_H
-
-#define prepare_to_switch() do { } while(0)
-
-/*
- * switch_to(n) should switch tasks to task ptr, first checking that
- * ptr isn't the current task, in which case it does nothing.
- */
-
-#include <asm/l1layout.h>
-#include <asm/mem_map.h>
-
-asmlinkage struct task_struct *resume(struct task_struct *prev, struct task_struct *next);
-
-#ifndef CONFIG_SMP
-#define switch_to(prev,next,last) \
-do { \
- memcpy (&task_thread_info(prev)->l1_task_info, L1_SCRATCH_TASK_INFO, \
- sizeof *L1_SCRATCH_TASK_INFO); \
- memcpy (L1_SCRATCH_TASK_INFO, &task_thread_info(next)->l1_task_info, \
- sizeof *L1_SCRATCH_TASK_INFO); \
- (last) = resume (prev, next); \
-} while (0)
-#else
-#define switch_to(prev, next, last) \
-do { \
- (last) = resume(prev, next); \
-} while (0)
-#endif
-
-#endif /* _BLACKFIN_SWITCH_TO_H */
+++ /dev/null
-/*
- * Magic syscall break down functions
- *
- * Copyright 2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_BLACKFIN_SYSCALL_H__
-#define __ASM_BLACKFIN_SYSCALL_H__
-
-/*
- * Blackfin syscalls are simple:
- * enter:
- * p0: syscall number
- * r{0,1,2,3,4,5}: syscall args 0,1,2,3,4,5
- * exit:
- * r0: return/error value
- */
-
-#include <linux/err.h>
-#include <linux/sched.h>
-#include <asm/ptrace.h>
-
-static inline long
-syscall_get_nr(struct task_struct *task, struct pt_regs *regs)
-{
- return regs->p0;
-}
-
-static inline void
-syscall_rollback(struct task_struct *task, struct pt_regs *regs)
-{
- regs->p0 = regs->orig_p0;
-}
-
-static inline long
-syscall_get_error(struct task_struct *task, struct pt_regs *regs)
-{
- return IS_ERR_VALUE(regs->r0) ? regs->r0 : 0;
-}
-
-static inline long
-syscall_get_return_value(struct task_struct *task, struct pt_regs *regs)
-{
- return regs->r0;
-}
-
-static inline void
-syscall_set_return_value(struct task_struct *task, struct pt_regs *regs,
- int error, long val)
-{
- regs->r0 = error ? -error : val;
-}
-
-/**
- * syscall_get_arguments()
- * @task: unused
- * @regs: the register layout to extract syscall arguments from
- * @i: first syscall argument to extract
- * @n: number of syscall arguments to extract
- * @args: array to return the syscall arguments in
- *
- * args[0] gets i'th argument, args[n - 1] gets the i+n-1'th argument
- */
-static inline void
-syscall_get_arguments(struct task_struct *task, struct pt_regs *regs,
- unsigned int i, unsigned int n, unsigned long *args)
-{
- /*
- * Assume the ptrace layout doesn't change -- r5 is first in memory,
- * then r4, ..., then r0. So we simply reverse the ptrace register
- * array in memory to store into the args array.
- */
- long *aregs = ®s->r0 - i;
-
- BUG_ON(i > 5 || i + n > 6);
-
- while (n--)
- *args++ = *aregs--;
-}
-
-/* See syscall_get_arguments() comments */
-static inline void
-syscall_set_arguments(struct task_struct *task, struct pt_regs *regs,
- unsigned int i, unsigned int n, const unsigned long *args)
-{
- long *aregs = ®s->r0 - i;
-
- BUG_ON(i > 5 || i + n > 6);
-
- while (n--)
- *aregs-- = *args++;
-}
-
-#endif
+++ /dev/null
-/*
- * Copyright 2004-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _ASM_THREAD_INFO_H
-#define _ASM_THREAD_INFO_H
-
-#include <asm/page.h>
-#include <asm/entry.h>
-#include <asm/l1layout.h>
-#include <linux/compiler.h>
-
-#ifdef __KERNEL__
-
-/* Thread Align Mask to reach to the top of the stack
- * for any process
- */
-#define ALIGN_PAGE_MASK 0xffffe000
-
-/*
- * Size of kernel stack for each process. This must be a power of 2...
- */
-#define THREAD_SIZE_ORDER 1
-#define THREAD_SIZE 8192 /* 2 pages */
-#define STACK_WARN (THREAD_SIZE/8)
-
-#ifndef __ASSEMBLY__
-
-typedef unsigned long mm_segment_t;
-
-/*
- * low level task data.
- * If you change this, change the TI_* offsets below to match.
- */
-
-struct thread_info {
- struct task_struct *task; /* main task structure */
- unsigned long flags; /* low level flags */
- int cpu; /* cpu we're on */
- int preempt_count; /* 0 => preemptable, <0 => BUG */
- mm_segment_t addr_limit; /* address limit */
-#ifndef CONFIG_SMP
- struct l1_scratch_task_info l1_task_info;
-#endif
-};
-
-/*
- * macros/functions for gaining access to the thread information structure
- */
-#define INIT_THREAD_INFO(tsk) \
-{ \
- .task = &tsk, \
- .flags = 0, \
- .cpu = 0, \
- .preempt_count = INIT_PREEMPT_COUNT, \
-}
-
-/* Given a task stack pointer, you can find its corresponding
- * thread_info structure just by masking it to the THREAD_SIZE
- * boundary (currently 8K as you can see above).
- */
-__attribute_const__
-static inline struct thread_info *current_thread_info(void)
-{
- struct thread_info *ti;
- __asm__("%0 = sp;" : "=da"(ti));
- return (struct thread_info *)((long)ti & ~((long)THREAD_SIZE-1));
-}
-
-#endif /* __ASSEMBLY__ */
-
-/*
- * thread information flag bit numbers
- */
-#define TIF_SYSCALL_TRACE 0 /* syscall trace active */
-#define TIF_SIGPENDING 1 /* signal pending */
-#define TIF_NEED_RESCHED 2 /* rescheduling necessary */
-#define TIF_MEMDIE 4 /* is terminating due to OOM killer */
-#define TIF_RESTORE_SIGMASK 5 /* restore signal mask in do_signal() */
-#define TIF_IRQ_SYNC 7 /* sync pipeline stage */
-#define TIF_NOTIFY_RESUME 8 /* callback before returning to user */
-#define TIF_SINGLESTEP 9
-
-/* as above, but as bit values */
-#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE)
-#define _TIF_SIGPENDING (1<<TIF_SIGPENDING)
-#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED)
-#define _TIF_IRQ_SYNC (1<<TIF_IRQ_SYNC)
-#define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME)
-#define _TIF_SINGLESTEP (1<<TIF_SINGLESTEP)
-
-#define _TIF_WORK_MASK 0x0000FFFE /* work to do on interrupt/exception return */
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_THREAD_INFO_H */
+++ /dev/null
-/*
- * asm-blackfin/time.h:
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _ASM_BLACKFIN_TIME_H
-#define _ASM_BLACKFIN_TIME_H
-
-/*
- * The way that the Blackfin core timer works is:
- * - CCLK is divided by a programmable 8-bit pre-scaler (TSCALE)
- * - Every time TSCALE ticks, a 32bit is counted down (TCOUNT)
- *
- * If you take the fastest clock (1ns, or 1GHz to make the math work easier)
- * 10ms is 10,000,000 clock ticks, which fits easy into a 32-bit counter
- * (32 bit counter is 4,294,967,296ns or 4.2 seconds) so, we don't need
- * to use TSCALE, and program it to zero (which is pass CCLK through).
- * If you feel like using it, try to keep HZ * TIMESCALE to some
- * value that divides easy (like power of 2).
- */
-
-#ifndef CONFIG_CPU_FREQ
-# define TIME_SCALE 1
-#else
-/*
- * Blackfin CPU frequency scaling supports max Core Clock 1, 1/2 and 1/4 .
- * Whenever we change the Core Clock frequency changes we immediately
- * adjust the Core Timer Presale Register. This way we don't lose time.
- */
-#define TIME_SCALE 4
-
-# ifdef CONFIG_CYCLES_CLOCKSOURCE
-extern unsigned long long __bfin_cycles_off;
-extern unsigned int __bfin_cycles_mod;
-# endif
-#endif
-
-#if defined(CONFIG_TICKSOURCE_CORETMR)
-extern void bfin_coretmr_init(void);
-extern void bfin_coretmr_clockevent_init(void);
-#endif
-
-#endif
+++ /dev/null
-/*
- * asm-blackfin/timex.h: cpu cycles!
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _ASM_BLACKFIN_TIMEX_H
-#define _ASM_BLACKFIN_TIMEX_H
-
-#define CLOCK_TICK_RATE 1000000 /* Underlying HZ */
-
-typedef unsigned long long cycles_t;
-
-static inline cycles_t get_cycles(void)
-{
- unsigned long tmp, tmp2;
- __asm__ __volatile__("%0 = cycles; %1 = cycles2;" : "=d"(tmp), "=d"(tmp2));
- return tmp | ((cycles_t)tmp2 << 32);
-}
-
-#endif
+++ /dev/null
-/*
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BLACKFIN_TLB_H
-#define _BLACKFIN_TLB_H
-
-#define tlb_start_vma(tlb, vma) do { } while (0)
-#define tlb_end_vma(tlb, vma) do { } while (0)
-#define __tlb_remove_tlb_entry(tlb, ptep, address) do { } while (0)
-
-/*
- * .. because we flush the whole mm when it
- * fills up.
- */
-#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm)
-
-#include <asm-generic/tlb.h>
-
-#endif /* _BLACKFIN_TLB_H */
+++ /dev/null
-#include <asm-generic/tlbflush.h>
-#define flush_tlb_kernel_range(s, e) do { } while (0)
+++ /dev/null
-/*
- * header file for hardware trace functions
- *
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BLACKFIN_TRACE_
-#define _BLACKFIN_TRACE_
-
-/* Normally, we use ON, but you can't turn on software expansion until
- * interrupts subsystem is ready
- */
-
-#define BFIN_TRACE_INIT ((CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION << 4) | 0x03)
-#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND
-#define BFIN_TRACE_ON (BFIN_TRACE_INIT | (CONFIG_DEBUG_BFIN_HWTRACE_EXPAND << 2))
-#else
-#define BFIN_TRACE_ON (BFIN_TRACE_INIT)
-#endif
-
-#ifndef __ASSEMBLY__
-extern unsigned long trace_buff_offset;
-extern unsigned long software_trace_buff[];
-#if defined(CONFIG_DEBUG_VERBOSE)
-extern void decode_address(char *buf, unsigned long address);
-extern bool get_instruction(unsigned int *val, unsigned short *address);
-#else
-static inline void decode_address(char *buf, unsigned long address) { }
-static inline bool get_instruction(unsigned int *val, unsigned short *address) { return false; }
-#endif
-
-/* Trace Macros for C files */
-
-#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON
-
-#define trace_buffer_init() bfin_write_TBUFCTL(BFIN_TRACE_INIT)
-
-#define trace_buffer_save(x) \
- do { \
- (x) = bfin_read_TBUFCTL(); \
- bfin_write_TBUFCTL((x) & ~TBUFEN); \
- } while (0)
-
-#define trace_buffer_restore(x) \
- do { \
- bfin_write_TBUFCTL((x)); \
- } while (0)
-#else /* DEBUG_BFIN_HWTRACE_ON */
-
-#define trace_buffer_save(x)
-#define trace_buffer_restore(x)
-#endif /* CONFIG_DEBUG_BFIN_HWTRACE_ON */
-
-#else
-/* Trace Macros for Assembly files */
-
-#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON
-
-#define trace_buffer_stop(preg, dreg) \
- preg.L = LO(TBUFCTL); \
- preg.H = HI(TBUFCTL); \
- dreg = 0x1; \
- [preg] = dreg;
-
-#define trace_buffer_init(preg, dreg) \
- preg.L = LO(TBUFCTL); \
- preg.H = HI(TBUFCTL); \
- dreg = BFIN_TRACE_INIT; \
- [preg] = dreg;
-
-#define trace_buffer_save(preg, dreg) \
- preg.L = LO(TBUFCTL); \
- preg.H = HI(TBUFCTL); \
- dreg = [preg]; \
- [--sp] = dreg; \
- dreg = 0x1; \
- [preg] = dreg;
-
-#define trace_buffer_restore(preg, dreg) \
- preg.L = LO(TBUFCTL); \
- preg.H = HI(TBUFCTL); \
- dreg = [sp++]; \
- [preg] = dreg;
-
-#else /* CONFIG_DEBUG_BFIN_HWTRACE_ON */
-
-#define trace_buffer_stop(preg, dreg)
-#define trace_buffer_init(preg, dreg)
-#define trace_buffer_save(preg, dreg)
-#define trace_buffer_restore(preg, dreg)
-
-#endif /* CONFIG_DEBUG_BFIN_HWTRACE_ON */
-
-#ifdef CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE
-# define DEBUG_HWTRACE_SAVE(preg, dreg) trace_buffer_save(preg, dreg)
-# define DEBUG_HWTRACE_RESTORE(preg, dreg) trace_buffer_restore(preg, dreg)
-#else
-# define DEBUG_HWTRACE_SAVE(preg, dreg)
-# define DEBUG_HWTRACE_RESTORE(preg, dreg)
-#endif
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* _BLACKFIN_TRACE_ */
+++ /dev/null
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2001 Lineo, Inc
- * Tony Kou
- * 1993 Hamish Macdonald
- *
- * Licensed under the GPL-2
- */
-
-#ifndef _BFIN_TRAPS_H
-#define _BFIN_TRAPS_H
-
-#define VEC_SYS (0)
-#define VEC_EXCPT01 (1)
-#define VEC_EXCPT02 (2)
-#define VEC_EXCPT03 (3)
-#define VEC_EXCPT04 (4)
-#define VEC_EXCPT05 (5)
-#define VEC_EXCPT06 (6)
-#define VEC_EXCPT07 (7)
-#define VEC_EXCPT08 (8)
-#define VEC_EXCPT09 (9)
-#define VEC_EXCPT10 (10)
-#define VEC_EXCPT11 (11)
-#define VEC_EXCPT12 (12)
-#define VEC_EXCPT13 (13)
-#define VEC_EXCPT14 (14)
-#define VEC_EXCPT15 (15)
-#define VEC_STEP (16)
-#define VEC_OVFLOW (17)
-#define VEC_UNDEF_I (33)
-#define VEC_ILGAL_I (34)
-#define VEC_CPLB_VL (35)
-#define VEC_MISALI_D (36)
-#define VEC_UNCOV (37)
-#define VEC_CPLB_M (38)
-#define VEC_CPLB_MHIT (39)
-#define VEC_WATCH (40)
-#define VEC_ISTRU_VL (41) /*ADSP-BF535 only (MH) */
-#define VEC_MISALI_I (42)
-#define VEC_CPLB_I_VL (43)
-#define VEC_CPLB_I_M (44)
-#define VEC_CPLB_I_MHIT (45)
-#define VEC_ILL_RES (46) /* including unvalid supervisor mode insn */
-/* The hardware reserves (63) for future use - we use it to tell our
- * normal exception handling code we have a hardware error
- */
-#define VEC_HWERR (63)
-
-#ifndef __ASSEMBLY__
-
-#define HWC_x2(level) \
- "System MMR Error\n" \
- level " - An error occurred due to an invalid access to an System MMR location\n" \
- level " Possible reason: a 32-bit register is accessed with a 16-bit instruction\n" \
- level " or a 16-bit register is accessed with a 32-bit instruction.\n"
-#define HWC_x3(level) \
- "External Memory Addressing Error\n"
-#define EXC_0x04(level) \
- "Unimplmented exception occurred\n" \
- level " - Maybe you forgot to install a custom exception handler?\n"
-#define HWC_x12(level) \
- "Performance Monitor Overflow\n"
-#define HWC_x18(level) \
- "RAISE 5 instruction\n" \
- level " Software issued a RAISE 5 instruction to invoke the Hardware\n"
-#define HWC_default(level) \
- "Reserved\n"
-#define EXC_0x03(level) \
- "Application stack overflow\n" \
- level " - Please increase the stack size of the application using elf2flt -s option,\n" \
- level " and/or reduce the stack use of the application.\n"
-#define EXC_0x10(level) \
- "Single step\n" \
- level " - When the processor is in single step mode, every instruction\n" \
- level " generates an exception. Primarily used for debugging.\n"
-#define EXC_0x11(level) \
- "Exception caused by a trace buffer full condition\n" \
- level " - The processor takes this exception when the trace\n" \
- level " buffer overflows (only when enabled by the Trace Unit Control register).\n"
-#define EXC_0x21(level) \
- "Undefined instruction\n" \
- level " - May be used to emulate instructions that are not defined for\n" \
- level " a particular processor implementation.\n"
-#define EXC_0x22(level) \
- "Illegal instruction combination\n" \
- level " - See section for multi-issue rules in the Blackfin\n" \
- level " Processor Instruction Set Reference.\n"
-#define EXC_0x23(level) \
- "Data access CPLB protection violation\n" \
- level " - Attempted read or write to Supervisor resource,\n" \
- level " or illegal data memory access. \n"
-#define EXC_0x24(level) \
- "Data access misaligned address violation\n" \
- level " - Attempted misaligned data memory or data cache access.\n"
-#define EXC_0x25(level) \
- "Unrecoverable event\n" \
- level " - For example, an exception generated while processing a previous exception.\n"
-#define EXC_0x26(level) \
- "Data access CPLB miss\n" \
- level " - Used by the MMU to signal a CPLB miss on a data access.\n"
-#define EXC_0x27(level) \
- "Data access multiple CPLB hits\n" \
- level " - More than one CPLB entry matches data fetch address.\n"
-#define EXC_0x28(level) \
- "Program Sequencer Exception caused by an emulation watchpoint match\n" \
- level " - There is a watchpoint match, and one of the EMUSW\n" \
- level " bits in the Watchpoint Instruction Address Control register (WPIACTL) is set.\n"
-#define EXC_0x2A(level) \
- "Instruction fetch misaligned address violation\n" \
- level " - Attempted misaligned instruction cache fetch.\n"
-#define EXC_0x2B(level) \
- "CPLB protection violation\n" \
- level " - Illegal instruction fetch access (memory protection violation).\n"
-#define EXC_0x2C(level) \
- "Instruction fetch CPLB miss\n" \
- level " - CPLB miss on an instruction fetch.\n"
-#define EXC_0x2D(level) \
- "Instruction fetch multiple CPLB hits\n" \
- level " - More than one CPLB entry matches instruction fetch address.\n"
-#define EXC_0x2E(level) \
- "Illegal use of supervisor resource\n" \
- level " - Attempted to use a Supervisor register or instruction from User mode.\n" \
- level " Supervisor resources are registers and instructions that are reserved\n" \
- level " for Supervisor use: Supervisor only registers, all MMRs, and Supervisor\n" \
- level " only instructions.\n"
-
-extern void double_fault_c(struct pt_regs *fp);
-
-#endif /* __ASSEMBLY__ */
-#endif /* _BFIN_TRAPS_H */
+++ /dev/null
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- *
- * Based on: include/asm-m68knommu/uaccess.h
- */
-
-#ifndef __BLACKFIN_UACCESS_H
-#define __BLACKFIN_UACCESS_H
-
-/*
- * User space memory access functions
- */
-#include <linux/mm.h>
-#include <linux/string.h>
-
-#include <asm/segment.h>
-#include <asm/sections.h>
-
-#define get_ds() (KERNEL_DS)
-#define get_fs() (current_thread_info()->addr_limit)
-
-static inline void set_fs(mm_segment_t fs)
-{
- current_thread_info()->addr_limit = fs;
-}
-
-#define segment_eq(a, b) ((a) == (b))
-
-#define access_ok(type, addr, size) _access_ok((unsigned long)(addr), (size))
-
-/*
- * The fs value determines whether argument validity checking should be
- * performed or not. If get_fs() == USER_DS, checking is performed, with
- * get_fs() == KERNEL_DS, checking is bypassed.
- */
-
-#ifndef CONFIG_ACCESS_CHECK
-static inline int _access_ok(unsigned long addr, unsigned long size) { return 1; }
-#else
-extern int _access_ok(unsigned long addr, unsigned long size);
-#endif
-
-#include <asm/extable.h>
-
-/*
- * These are the main single-value transfer routines. They automatically
- * use the right size if we just have the right pointer type.
- */
-
-#define put_user(x, p) \
- ({ \
- int _err = 0; \
- typeof(*(p)) _x = (x); \
- typeof(*(p)) __user *_p = (p); \
- if (!access_ok(VERIFY_WRITE, _p, sizeof(*(_p)))) {\
- _err = -EFAULT; \
- } \
- else { \
- switch (sizeof (*(_p))) { \
- case 1: \
- __put_user_asm(_x, _p, B); \
- break; \
- case 2: \
- __put_user_asm(_x, _p, W); \
- break; \
- case 4: \
- __put_user_asm(_x, _p, ); \
- break; \
- case 8: { \
- long _xl, _xh; \
- _xl = ((__force long *)&_x)[0]; \
- _xh = ((__force long *)&_x)[1]; \
- __put_user_asm(_xl, ((__force long __user *)_p)+0, );\
- __put_user_asm(_xh, ((__force long __user *)_p)+1, );\
- } break; \
- default: \
- _err = __put_user_bad(); \
- break; \
- } \
- } \
- _err; \
- })
-
-#define __put_user(x, p) put_user(x, p)
-static inline int bad_user_access_length(void)
-{
- panic("bad_user_access_length");
- return -1;
-}
-
-#define __put_user_bad() (printk(KERN_INFO "put_user_bad %s:%d %s\n",\
- __FILE__, __LINE__, __func__),\
- bad_user_access_length(), (-EFAULT))
-
-/*
- * Tell gcc we read from memory instead of writing: this is because
- * we do not write to any memory gcc knows about, so there are no
- * aliasing issues.
- */
-
-#define __ptr(x) ((unsigned long __force *)(x))
-
-#define __put_user_asm(x, p, bhw) \
- __asm__ (#bhw"[%1] = %0;\n\t" \
- : /* no outputs */ \
- :"d" (x), "a" (__ptr(p)) : "memory")
-
-#define get_user(x, ptr) \
-({ \
- int _err = 0; \
- unsigned long _val = 0; \
- const typeof(*(ptr)) __user *_p = (ptr); \
- const size_t ptr_size = sizeof(*(_p)); \
- if (likely(access_ok(VERIFY_READ, _p, ptr_size))) { \
- BUILD_BUG_ON(ptr_size >= 8); \
- switch (ptr_size) { \
- case 1: \
- __get_user_asm(_val, _p, B, (Z)); \
- break; \
- case 2: \
- __get_user_asm(_val, _p, W, (Z)); \
- break; \
- case 4: \
- __get_user_asm(_val, _p, , ); \
- break; \
- } \
- } else \
- _err = -EFAULT; \
- x = (__force typeof(*(ptr)))_val; \
- _err; \
-})
-
-#define __get_user(x, p) get_user(x, p)
-
-#define __get_user_bad() (bad_user_access_length(), (-EFAULT))
-
-#define __get_user_asm(x, ptr, bhw, option) \
-({ \
- __asm__ __volatile__ ( \
- "%0 =" #bhw "[%1]" #option ";" \
- : "=d" (x) \
- : "a" (__ptr(ptr))); \
-})
-
-static inline unsigned long __must_check
-raw_copy_from_user(void *to, const void __user *from, unsigned long n)
-{
- memcpy(to, (const void __force *)from, n);
- return 0;
-}
-
-static inline unsigned long __must_check
-raw_copy_to_user(void __user *to, const void *from, unsigned long n)
-{
- memcpy((void __force *)to, from, n);
- SSYNC();
- return 0;
-}
-
-#define INLINE_COPY_FROM_USER
-#define INLINE_COPY_TO_USER
-/*
- * Copy a null terminated string from userspace.
- */
-
-static inline long __must_check
-strncpy_from_user(char *dst, const char __user *src, long count)
-{
- char *tmp;
- if (!access_ok(VERIFY_READ, src, 1))
- return -EFAULT;
- strncpy(dst, (const char __force *)src, count);
- for (tmp = dst; *tmp && count > 0; tmp++, count--) ;
- return (tmp - dst);
-}
-
-/*
- * Get the size of a string in user space.
- * src: The string to measure
- * n: The maximum valid length
- *
- * Get the size of a NUL-terminated string in user space.
- *
- * Returns the size of the string INCLUDING the terminating NUL.
- * On exception, returns 0.
- * If the string is too long, returns a value greater than n.
- */
-static inline long __must_check strnlen_user(const char __user *src, long n)
-{
- if (!access_ok(VERIFY_READ, src, 1))
- return 0;
- return strnlen((const char __force *)src, n) + 1;
-}
-
-/*
- * Zero Userspace
- */
-
-static inline unsigned long __must_check
-__clear_user(void __user *to, unsigned long n)
-{
- if (!access_ok(VERIFY_WRITE, to, n))
- return n;
- memset((void __force *)to, 0, n);
- return 0;
-}
-
-#define clear_user(to, n) __clear_user(to, n)
-
-/* How to interpret these return values:
- * CORE: can be accessed by core load or dma memcpy
- * CORE_ONLY: can only be accessed by core load
- * DMA: can only be accessed by dma memcpy
- * IDMA: can only be accessed by interprocessor dma memcpy (BF561)
- * ITEST: can be accessed by isram memcpy or dma memcpy
- */
-enum {
- BFIN_MEM_ACCESS_CORE = 0,
- BFIN_MEM_ACCESS_CORE_ONLY,
- BFIN_MEM_ACCESS_DMA,
- BFIN_MEM_ACCESS_IDMA,
- BFIN_MEM_ACCESS_ITEST,
-};
-/**
- * bfin_mem_access_type() - what kind of memory access is required
- * @addr: the address to check
- * @size: number of bytes needed
- * @return: <0 is error, >=0 is BFIN_MEM_ACCESS_xxx enum (see above)
- */
-int bfin_mem_access_type(unsigned long addr, unsigned long size);
-
-#endif /* _BLACKFIN_UACCESS_H */
+++ /dev/null
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-#ifndef __ASM_BFIN_UNISTD_H
-#define __ASM_BFIN_UNISTD_H
-
-#include <uapi/asm/unistd.h>
-
-#define __ARCH_WANT_STAT64
-#define __ARCH_WANT_SYS_ALARM
-#define __ARCH_WANT_SYS_GETHOSTNAME
-#define __ARCH_WANT_SYS_PAUSE
-#define __ARCH_WANT_SYS_TIME
-#define __ARCH_WANT_SYS_FADVISE64
-#define __ARCH_WANT_SYS_GETPGRP
-#define __ARCH_WANT_SYS_LLSEEK
-#define __ARCH_WANT_SYS_NICE
-#define __ARCH_WANT_SYS_VFORK
-
-#endif /* __ASM_BFIN_UNISTD_H */
+++ /dev/null
-#include <asm-generic/vga.h>
+++ /dev/null
-/*
- * Common Blackfin IRQ definitions (i.e. the CEC)
- *
- * Copyright 2005-2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _MACH_COMMON_IRQ_H_
-#define _MACH_COMMON_IRQ_H_
-
-/*
- * Core events interrupt source definitions
- *
- * Event Source Event Name
- * Emulation EMU 0 (highest priority)
- * Reset RST 1
- * NMI NMI 2
- * Exception EVX 3
- * Reserved -- 4
- * Hardware Error IVHW 5
- * Core Timer IVTMR 6
- * Peripherals IVG7 7
- * Peripherals IVG8 8
- * Peripherals IVG9 9
- * Peripherals IVG10 10
- * Peripherals IVG11 11
- * Peripherals IVG12 12
- * Peripherals IVG13 13
- * Softirq IVG14 14
- * System Call IVG15 15 (lowest priority)
- */
-
-/* The ABSTRACT IRQ definitions */
-#define IRQ_EMU 0 /* Emulation */
-#define IRQ_RST 1 /* reset */
-#define IRQ_NMI 2 /* Non Maskable */
-#define IRQ_EVX 3 /* Exception */
-#define IRQ_UNUSED 4 /* - unused interrupt */
-#define IRQ_HWERR 5 /* Hardware Error */
-#define IRQ_CORETMR 6 /* Core timer */
-
-#define IVG7 7
-#define IVG8 8
-#define IVG9 9
-#define IVG10 10
-#define IVG11 11
-#define IVG12 12
-#define IVG13 13
-#define IVG14 14
-#define IVG15 15
-
-#define BFIN_IRQ(x) ((x) + IVG7)
-#define BFIN_SYSIRQ(x) ((x) - IVG7)
-
-#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS)
-
-#endif
+++ /dev/null
-/*
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_COMMON_PLL_H
-#define _MACH_COMMON_PLL_H
-
-#ifndef __ASSEMBLY__
-
-#include <asm/blackfin.h>
-#include <asm/irqflags.h>
-
-#ifndef bfin_iwr_restore
-static inline void
-bfin_iwr_restore(unsigned long iwr0, unsigned long iwr1, unsigned long iwr2)
-{
-#ifdef SIC_IWR
- bfin_write_SIC_IWR(iwr0);
-#else
- bfin_write_SIC_IWR0(iwr0);
-# ifdef SIC_IWR1
- bfin_write_SIC_IWR1(iwr1);
-# endif
-# ifdef SIC_IWR2
- bfin_write_SIC_IWR2(iwr2);
-# endif
-#endif
-}
-#endif
-
-#ifndef bfin_iwr_save
-static inline void
-bfin_iwr_save(unsigned long niwr0, unsigned long niwr1, unsigned long niwr2,
- unsigned long *iwr0, unsigned long *iwr1, unsigned long *iwr2)
-{
-#ifdef SIC_IWR
- *iwr0 = bfin_read_SIC_IWR();
-#else
- *iwr0 = bfin_read_SIC_IWR0();
-# ifdef SIC_IWR1
- *iwr1 = bfin_read_SIC_IWR1();
-# endif
-# ifdef SIC_IWR2
- *iwr2 = bfin_read_SIC_IWR2();
-# endif
-#endif
- bfin_iwr_restore(niwr0, niwr1, niwr2);
-}
-#endif
-
-static inline void _bfin_write_pll_relock(u32 addr, unsigned int val)
-{
- unsigned long flags, iwr0, iwr1, iwr2;
-
- if (val == bfin_read_PLL_CTL())
- return;
-
- flags = hard_local_irq_save();
- /* Enable the PLL Wakeup bit in SIC IWR */
- bfin_iwr_save(IWR_ENABLE(0), 0, 0, &iwr0, &iwr1, &iwr2);
-
- bfin_write16(addr, val);
- SSYNC();
- asm("IDLE;");
-
- bfin_iwr_restore(iwr0, iwr1, iwr2);
- hard_local_irq_restore(flags);
-}
-
-/* Writing to PLL_CTL initiates a PLL relock sequence */
-static inline void bfin_write_PLL_CTL(unsigned int val)
-{
- _bfin_write_pll_relock(PLL_CTL, val);
-}
-
-/* Writing to VR_CTL initiates a PLL relock sequence */
-static inline void bfin_write_VR_CTL(unsigned int val)
-{
- _bfin_write_pll_relock(VR_CTL, val);
-}
-
-#endif
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Port A Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT_A__
-#define __BFIN_PERIPHERAL_PORT_A__
-
-#define PA0 (1 << 0)
-#define PA1 (1 << 1)
-#define PA2 (1 << 2)
-#define PA3 (1 << 3)
-#define PA4 (1 << 4)
-#define PA5 (1 << 5)
-#define PA6 (1 << 6)
-#define PA7 (1 << 7)
-#define PA8 (1 << 8)
-#define PA9 (1 << 9)
-#define PA10 (1 << 10)
-#define PA11 (1 << 11)
-#define PA12 (1 << 12)
-#define PA13 (1 << 13)
-#define PA14 (1 << 14)
-#define PA15 (1 << 15)
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Port B Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT_B__
-#define __BFIN_PERIPHERAL_PORT_B__
-
-#define PB0 (1 << 0)
-#define PB1 (1 << 1)
-#define PB2 (1 << 2)
-#define PB3 (1 << 3)
-#define PB4 (1 << 4)
-#define PB5 (1 << 5)
-#define PB6 (1 << 6)
-#define PB7 (1 << 7)
-#define PB8 (1 << 8)
-#define PB9 (1 << 9)
-#define PB10 (1 << 10)
-#define PB11 (1 << 11)
-#define PB12 (1 << 12)
-#define PB13 (1 << 13)
-#define PB14 (1 << 14)
-#define PB15 (1 << 15)
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Port C Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT_C__
-#define __BFIN_PERIPHERAL_PORT_C__
-
-#define PC0 (1 << 0)
-#define PC1 (1 << 1)
-#define PC2 (1 << 2)
-#define PC3 (1 << 3)
-#define PC4 (1 << 4)
-#define PC5 (1 << 5)
-#define PC6 (1 << 6)
-#define PC7 (1 << 7)
-#define PC8 (1 << 8)
-#define PC9 (1 << 9)
-#define PC10 (1 << 10)
-#define PC11 (1 << 11)
-#define PC12 (1 << 12)
-#define PC13 (1 << 13)
-#define PC14 (1 << 14)
-#define PC15 (1 << 15)
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Port D Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT_D__
-#define __BFIN_PERIPHERAL_PORT_D__
-
-#define PD0 (1 << 0)
-#define PD1 (1 << 1)
-#define PD2 (1 << 2)
-#define PD3 (1 << 3)
-#define PD4 (1 << 4)
-#define PD5 (1 << 5)
-#define PD6 (1 << 6)
-#define PD7 (1 << 7)
-#define PD8 (1 << 8)
-#define PD9 (1 << 9)
-#define PD10 (1 << 10)
-#define PD11 (1 << 11)
-#define PD12 (1 << 12)
-#define PD13 (1 << 13)
-#define PD14 (1 << 14)
-#define PD15 (1 << 15)
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Port E Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT_E__
-#define __BFIN_PERIPHERAL_PORT_E__
-
-#define PE0 (1 << 0)
-#define PE1 (1 << 1)
-#define PE2 (1 << 2)
-#define PE3 (1 << 3)
-#define PE4 (1 << 4)
-#define PE5 (1 << 5)
-#define PE6 (1 << 6)
-#define PE7 (1 << 7)
-#define PE8 (1 << 8)
-#define PE9 (1 << 9)
-#define PE10 (1 << 10)
-#define PE11 (1 << 11)
-#define PE12 (1 << 12)
-#define PE13 (1 << 13)
-#define PE14 (1 << 14)
-#define PE15 (1 << 15)
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Port F Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT_F__
-#define __BFIN_PERIPHERAL_PORT_F__
-
-#define PF0 (1 << 0)
-#define PF1 (1 << 1)
-#define PF2 (1 << 2)
-#define PF3 (1 << 3)
-#define PF4 (1 << 4)
-#define PF5 (1 << 5)
-#define PF6 (1 << 6)
-#define PF7 (1 << 7)
-#define PF8 (1 << 8)
-#define PF9 (1 << 9)
-#define PF10 (1 << 10)
-#define PF11 (1 << 11)
-#define PF12 (1 << 12)
-#define PF13 (1 << 13)
-#define PF14 (1 << 14)
-#define PF15 (1 << 15)
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Port G Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT_G__
-#define __BFIN_PERIPHERAL_PORT_G__
-
-#define PG0 (1 << 0)
-#define PG1 (1 << 1)
-#define PG2 (1 << 2)
-#define PG3 (1 << 3)
-#define PG4 (1 << 4)
-#define PG5 (1 << 5)
-#define PG6 (1 << 6)
-#define PG7 (1 << 7)
-#define PG8 (1 << 8)
-#define PG9 (1 << 9)
-#define PG10 (1 << 10)
-#define PG11 (1 << 11)
-#define PG12 (1 << 12)
-#define PG13 (1 << 13)
-#define PG14 (1 << 14)
-#define PG15 (1 << 15)
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Port H Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT_H__
-#define __BFIN_PERIPHERAL_PORT_H__
-
-#define PH0 (1 << 0)
-#define PH1 (1 << 1)
-#define PH2 (1 << 2)
-#define PH3 (1 << 3)
-#define PH4 (1 << 4)
-#define PH5 (1 << 5)
-#define PH6 (1 << 6)
-#define PH7 (1 << 7)
-#define PH8 (1 << 8)
-#define PH9 (1 << 9)
-#define PH10 (1 << 10)
-#define PH11 (1 << 11)
-#define PH12 (1 << 12)
-#define PH13 (1 << 13)
-#define PH14 (1 << 14)
-#define PH15 (1 << 15)
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Port I Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT_I__
-#define __BFIN_PERIPHERAL_PORT_I__
-
-#define PI0 (1 << 0)
-#define PI1 (1 << 1)
-#define PI2 (1 << 2)
-#define PI3 (1 << 3)
-#define PI4 (1 << 4)
-#define PI5 (1 << 5)
-#define PI6 (1 << 6)
-#define PI7 (1 << 7)
-#define PI8 (1 << 8)
-#define PI9 (1 << 9)
-#define PI10 (1 << 10)
-#define PI11 (1 << 11)
-#define PI12 (1 << 12)
-#define PI13 (1 << 13)
-#define PI14 (1 << 14)
-#define PI15 (1 << 15)
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Port J Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT_J__
-#define __BFIN_PERIPHERAL_PORT_J__
-
-#define PJ0 (1 << 0)
-#define PJ1 (1 << 1)
-#define PJ2 (1 << 2)
-#define PJ3 (1 << 3)
-#define PJ4 (1 << 4)
-#define PJ5 (1 << 5)
-#define PJ6 (1 << 6)
-#define PJ7 (1 << 7)
-#define PJ8 (1 << 8)
-#define PJ9 (1 << 9)
-#define PJ10 (1 << 10)
-#define PJ11 (1 << 11)
-#define PJ12 (1 << 12)
-#define PJ13 (1 << 13)
-#define PJ14 (1 << 14)
-#define PJ15 (1 << 15)
-
-#endif
+++ /dev/null
-# UAPI Header export list
-include include/uapi/asm-generic/Kbuild.asm
-
-generic-y += auxvec.h
-generic-y += bitsperlong.h
-generic-y += bpf_perf_event.h
-generic-y += errno.h
-generic-y += ioctl.h
-generic-y += ipcbuf.h
-generic-y += kvm_para.h
-generic-y += mman.h
-generic-y += msgbuf.h
-generic-y += param.h
-generic-y += resource.h
-generic-y += sembuf.h
-generic-y += setup.h
-generic-y += shmbuf.h
-generic-y += shmparam.h
-generic-y += socket.h
-generic-y += sockios.h
-generic-y += statfs.h
-generic-y += termbits.h
-generic-y += termios.h
-generic-y += types.h
-generic-y += ucontext.h
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
-/*
- * bfin_sport.h - interface to Blackfin SPORTs
- *
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _UAPI__BFIN_SPORT_H__
-#define _UAPI__BFIN_SPORT_H__
-
-/* Sport mode: it can be set to TDM, i2s or others */
-#define NORM_MODE 0x0
-#define TDM_MODE 0x1
-#define I2S_MODE 0x2
-#define NDSO_MODE 0x3
-
-/* Data format, normal, a-law or u-law */
-#define NORM_FORMAT 0x0
-#define ALAW_FORMAT 0x2
-#define ULAW_FORMAT 0x3
-
-/* Function driver which use sport must initialize the structure */
-struct sport_config {
- /* TDM (multichannels), I2S or other mode */
- unsigned int mode:3;
- unsigned int polled; /* use poll instead of irq when set */
-
- /* if TDM mode is selected, channels must be set */
- int channels; /* Must be in 8 units */
- unsigned int frame_delay:4; /* Delay between frame sync pulse and first bit */
-
- /* I2S mode */
- unsigned int right_first:1; /* Right stereo channel first */
-
- /* In mormal mode, the following item need to be set */
- unsigned int lsb_first:1; /* order of transmit or receive data */
- unsigned int fsync:1; /* Frame sync required */
- unsigned int data_indep:1; /* data independent frame sync generated */
- unsigned int act_low:1; /* Active low TFS */
- unsigned int late_fsync:1; /* Late frame sync */
- unsigned int tckfe:1;
- unsigned int sec_en:1; /* Secondary side enabled */
-
- /* Choose clock source */
- unsigned int int_clk:1; /* Internal or external clock */
-
- /* If external clock is used, the following fields are ignored */
- int serial_clk;
- int fsync_clk;
-
- unsigned int data_format:2; /* Normal, u-law or a-law */
-
- int word_len; /* How length of the word in bits, 3-32 bits */
- int dma_enabled;
-};
-
-/* Userspace interface */
-#define SPORT_IOC_MAGIC 'P'
-#define SPORT_IOC_CONFIG _IOWR('P', 0x01, struct sport_config)
-#define SPORT_IOC_GET_SYSTEMCLOCK _IOR('P', 0x02, unsigned long)
-#define SPORT_IOC_SET_BAUDRATE _IOW('P', 0x03, unsigned long)
-
-
-/* SPORT_TCR1 Masks */
-#define TSPEN 0x0001 /* TX enable */
-#define ITCLK 0x0002 /* Internal TX Clock Select */
-#define TDTYPE 0x000C /* TX Data Formatting Select */
-#define DTYPE_NORM 0x0000 /* Data Format Normal */
-#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
-#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
-#define TLSBIT 0x0010 /* TX Bit Order */
-#define ITFS 0x0200 /* Internal TX Frame Sync Select */
-#define TFSR 0x0400 /* TX Frame Sync Required Select */
-#define DITFS 0x0800 /* Data Independent TX Frame Sync Select */
-#define LTFS 0x1000 /* Low TX Frame Sync Select */
-#define LATFS 0x2000 /* Late TX Frame Sync Select */
-#define TCKFE 0x4000 /* TX Clock Falling Edge Select */
-
-/* SPORT_TCR2 Masks */
-#define SLEN 0x001F /* SPORT TX Word Length (2 - 31) */
-#define DP_SLEN(x) BFIN_DEPOSIT(SLEN, x)
-#define EX_SLEN(x) BFIN_EXTRACT(SLEN, x)
-#define TXSE 0x0100 /* TX Secondary Enable */
-#define TSFSE 0x0200 /* TX Stereo Frame Sync Enable */
-#define TRFST 0x0400 /* TX Right-First Data Order */
-
-/* SPORT_RCR1 Masks */
-#define RSPEN 0x0001 /* RX enable */
-#define IRCLK 0x0002 /* Internal RX Clock Select */
-#define RDTYPE 0x000C /* RX Data Formatting Select */
-/* DTYPE_* defined above */
-#define RLSBIT 0x0010 /* RX Bit Order */
-#define IRFS 0x0200 /* Internal RX Frame Sync Select */
-#define RFSR 0x0400 /* RX Frame Sync Required Select */
-#define LRFS 0x1000 /* Low RX Frame Sync Select */
-#define LARFS 0x2000 /* Late RX Frame Sync Select */
-#define RCKFE 0x4000 /* RX Clock Falling Edge Select */
-
-/* SPORT_RCR2 Masks */
-/* SLEN defined above */
-#define RXSE 0x0100 /* RX Secondary Enable */
-#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */
-#define RRFST 0x0400 /* Right-First Data Order */
-
-/* SPORT_STAT Masks */
-#define RXNE 0x0001 /* RX FIFO Not Empty Status */
-#define RUVF 0x0002 /* RX Underflow Status */
-#define ROVF 0x0004 /* RX Overflow Status */
-#define TXF 0x0008 /* TX FIFO Full Status */
-#define TUVF 0x0010 /* TX Underflow Status */
-#define TOVF 0x0020 /* TX Overflow Status */
-#define TXHRE 0x0040 /* TX Hold Register Empty */
-
-/* SPORT_MCMC1 Masks */
-#define SP_WOFF 0x03FF /* Multichannel Window Offset Field */
-#define DP_SP_WOFF(x) BFIN_DEPOSIT(SP_WOFF, x)
-#define EX_SP_WOFF(x) BFIN_EXTRACT(SP_WOFF, x)
-#define SP_WSIZE 0xF000 /* Multichannel Window Size Field */
-#define DP_SP_WSIZE(x) BFIN_DEPOSIT(SP_WSIZE, x)
-#define EX_SP_WSIZE(x) BFIN_EXTRACT(SP_WSIZE, x)
-
-/* SPORT_MCMC2 Masks */
-#define MCCRM 0x0003 /* Multichannel Clock Recovery Mode */
-#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
-#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */
-#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */
-#define MCDTXPE 0x0004 /* Multichannel DMA Transmit Packing */
-#define MCDRXPE 0x0008 /* Multichannel DMA Receive Packing */
-#define MCMEN 0x0010 /* Multichannel Frame Mode Enable */
-#define FSDR 0x0080 /* Multichannel Frame Sync to Data Relationship */
-#define MFD 0xF000 /* Multichannel Frame Delay */
-#define DP_MFD(x) BFIN_DEPOSIT(MFD, x)
-#define EX_MFD(x) BFIN_EXTRACT(MFD, x)
-
-#endif /* _UAPI__BFIN_SPORT_H__ */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _UAPI__BFIN_ASM_BYTEORDER_H
-#define _UAPI__BFIN_ASM_BYTEORDER_H
-
-#include <linux/byteorder/little_endian.h>
-
-#endif /* _UAPI__BFIN_ASM_BYTEORDER_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
-/*
- * based on the mips/cachectl.h
- *
- * Copyright 2010 Analog Devices Inc.
- * Copyright (C) 1994, 1995, 1996 by Ralf Baechle
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _UAPI_ASM_CACHECTL
-#define _UAPI_ASM_CACHECTL
-
-/*
- * Options for cacheflush system call
- */
-#define ICACHE (1<<0) /* flush instruction cache */
-#define DCACHE (1<<1) /* writeback and flush data cache */
-#define BCACHE (ICACHE|DCACHE) /* flush both caches */
-
-#endif /* _UAPI_ASM_CACHECTL */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
-/*
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _UAPI_BFIN_FCNTL_H
-#define _UAPI_BFIN_FCNTL_H
-
-#define O_DIRECTORY 040000 /* must be a directory */
-#define O_NOFOLLOW 0100000 /* don't follow links */
-#define O_DIRECT 0200000 /* direct disk access hint - currently ignored */
-#define O_LARGEFILE 0400000
-
-#include <asm-generic/fcntl.h>
-
-#endif /* _UAPI_BFIN_FCNTL_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
-/*
- * This file defines the fixed addresses where userspace programs
- * can find atomic code sequences.
- *
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _UAPI__BFIN_ASM_FIXED_CODE_H__
-#define _UAPI__BFIN_ASM_FIXED_CODE_H__
-
-
-#ifndef CONFIG_PHY_RAM_BASE_ADDRESS
-#define CONFIG_PHY_RAM_BASE_ADDRESS 0x0
-#endif
-
-#define FIXED_CODE_START (CONFIG_PHY_RAM_BASE_ADDRESS + 0x400)
-
-#define SIGRETURN_STUB (CONFIG_PHY_RAM_BASE_ADDRESS + 0x400)
-
-#define ATOMIC_SEQS_START (CONFIG_PHY_RAM_BASE_ADDRESS + 0x410)
-
-#define ATOMIC_XCHG32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x410)
-#define ATOMIC_CAS32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x420)
-#define ATOMIC_ADD32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x430)
-#define ATOMIC_SUB32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x440)
-#define ATOMIC_IOR32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x450)
-#define ATOMIC_AND32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x460)
-#define ATOMIC_XOR32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x470)
-
-#define ATOMIC_SEQS_END (CONFIG_PHY_RAM_BASE_ADDRESS + 0x480)
-
-#define SAFE_USER_INSTRUCTION (CONFIG_PHY_RAM_BASE_ADDRESS + 0x480)
-
-#define FIXED_CODE_END (CONFIG_PHY_RAM_BASE_ADDRESS + 0x490)
-
-#endif /* _UAPI__BFIN_ASM_FIXED_CODE_H__ */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _UAPI__ARCH_BFIN_IOCTLS_H__
-#define _UAPI__ARCH_BFIN_IOCTLS_H__
-
-#define FIOQSIZE 0x545E
-#include <asm-generic/ioctls.h>
-
-#endif /* _UAPI__ARCH_BFIN_IOCTLS_H__ */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- *
- */
-
-#ifndef _UAPI__BFIN_POLL_H
-#define _UAPI__BFIN_POLL_H
-
-#define POLLWRNORM POLLOUT
-#define POLLWRBAND 256
-
-#include <asm-generic/poll.h>
-
-#endif /* _UAPI__BFIN_POLL_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _UAPI__ARCH_BFIN_POSIX_TYPES_H
-#define _UAPI__ARCH_BFIN_POSIX_TYPES_H
-
-typedef unsigned short __kernel_mode_t;
-#define __kernel_mode_t __kernel_mode_t
-
-typedef unsigned int __kernel_ipc_pid_t;
-#define __kernel_ipc_pid_t __kernel_ipc_pid_t
-
-typedef unsigned long __kernel_size_t;
-typedef long __kernel_ssize_t;
-typedef int __kernel_ptrdiff_t;
-#define __kernel_size_t __kernel_size_t
-
-typedef unsigned short __kernel_old_uid_t;
-typedef unsigned short __kernel_old_gid_t;
-#define __kernel_old_uid_t __kernel_old_uid_t
-
-typedef unsigned short __kernel_old_dev_t;
-#define __kernel_old_dev_t __kernel_old_dev_t
-
-#include <asm-generic/posix_types.h>
-
-#endif /* _UAPI__ARCH_BFIN_POSIX_TYPES_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
-/*
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _UAPI_BFIN_PTRACE_H
-#define _UAPI_BFIN_PTRACE_H
-
-/*
- * GCC defines register number like this:
- * -----------------------------
- * 0 - 7 are data registers R0-R7
- * 8 - 15 are address registers P0-P7
- * 16 - 31 dsp registers I/B/L0 -- I/B/L3 & M0--M3
- * 32 - 33 A registers A0 & A1
- * 34 - status register
- * -----------------------------
- *
- * We follows above, except:
- * 32-33 --- Low 32-bit of A0&1
- * 34-35 --- High 8-bit of A0&1
- */
-
-#ifndef __ASSEMBLY__
-
-struct task_struct;
-
-/* this struct defines the way the registers are stored on the
- stack during a system call. */
-
-struct pt_regs {
- long orig_pc;
- long ipend;
- long seqstat;
- long rete;
- long retn;
- long retx;
- long pc; /* PC == RETI */
- long rets;
- long reserved; /* Used as scratch during system calls */
- long astat;
- long lb1;
- long lb0;
- long lt1;
- long lt0;
- long lc1;
- long lc0;
- long a1w;
- long a1x;
- long a0w;
- long a0x;
- long b3;
- long b2;
- long b1;
- long b0;
- long l3;
- long l2;
- long l1;
- long l0;
- long m3;
- long m2;
- long m1;
- long m0;
- long i3;
- long i2;
- long i1;
- long i0;
- long usp;
- long fp;
- long p5;
- long p4;
- long p3;
- long p2;
- long p1;
- long p0;
- long r7;
- long r6;
- long r5;
- long r4;
- long r3;
- long r2;
- long r1;
- long r0;
- long orig_r0;
- long orig_p0;
- long syscfg;
-};
-
-/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
-#define PTRACE_GETREGS 12
-#define PTRACE_SETREGS 13 /* ptrace signal */
-
-#define PTRACE_GETFDPIC 31 /* get the ELF fdpic loadmap address */
-#define PTRACE_GETFDPIC_EXEC 0 /* [addr] request the executable loadmap */
-#define PTRACE_GETFDPIC_INTERP 1 /* [addr] request the interpreter loadmap */
-
-#define PS_S (0x0002)
-
-
-#endif /* __ASSEMBLY__ */
-
-/*
- * Offsets used by 'ptrace' system call interface.
- */
-
-#define PT_R0 204
-#define PT_R1 200
-#define PT_R2 196
-#define PT_R3 192
-#define PT_R4 188
-#define PT_R5 184
-#define PT_R6 180
-#define PT_R7 176
-#define PT_P0 172
-#define PT_P1 168
-#define PT_P2 164
-#define PT_P3 160
-#define PT_P4 156
-#define PT_P5 152
-#define PT_FP 148
-#define PT_USP 144
-#define PT_I0 140
-#define PT_I1 136
-#define PT_I2 132
-#define PT_I3 128
-#define PT_M0 124
-#define PT_M1 120
-#define PT_M2 116
-#define PT_M3 112
-#define PT_L0 108
-#define PT_L1 104
-#define PT_L2 100
-#define PT_L3 96
-#define PT_B0 92
-#define PT_B1 88
-#define PT_B2 84
-#define PT_B3 80
-#define PT_A0X 76
-#define PT_A0W 72
-#define PT_A1X 68
-#define PT_A1W 64
-#define PT_LC0 60
-#define PT_LC1 56
-#define PT_LT0 52
-#define PT_LT1 48
-#define PT_LB0 44
-#define PT_LB1 40
-#define PT_ASTAT 36
-#define PT_RESERVED 32
-#define PT_RETS 28
-#define PT_PC 24
-#define PT_RETX 20
-#define PT_RETN 16
-#define PT_RETE 12
-#define PT_SEQSTAT 8
-#define PT_IPEND 4
-
-#define PT_ORIG_R0 208
-#define PT_ORIG_P0 212
-#define PT_SYSCFG 216
-#define PT_TEXT_ADDR 220
-#define PT_TEXT_END_ADDR 224
-#define PT_DATA_ADDR 228
-#define PT_FDPIC_EXEC 232
-#define PT_FDPIC_INTERP 236
-
-#define PT_LAST_PSEUDO PT_FDPIC_INTERP
-
-#endif /* _UAPI_BFIN_PTRACE_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
-/*
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _UAPI_ASM_BLACKFIN_SIGCONTEXT_H
-#define _UAPI_ASM_BLACKFIN_SIGCONTEXT_H
-
-/* Add new entries at the end of the structure only. */
-struct sigcontext {
- unsigned long sc_r0;
- unsigned long sc_r1;
- unsigned long sc_r2;
- unsigned long sc_r3;
- unsigned long sc_r4;
- unsigned long sc_r5;
- unsigned long sc_r6;
- unsigned long sc_r7;
- unsigned long sc_p0;
- unsigned long sc_p1;
- unsigned long sc_p2;
- unsigned long sc_p3;
- unsigned long sc_p4;
- unsigned long sc_p5;
- unsigned long sc_usp;
- unsigned long sc_a0w;
- unsigned long sc_a1w;
- unsigned long sc_a0x;
- unsigned long sc_a1x;
- unsigned long sc_astat;
- unsigned long sc_rets;
- unsigned long sc_pc;
- unsigned long sc_retx;
- unsigned long sc_fp;
- unsigned long sc_i0;
- unsigned long sc_i1;
- unsigned long sc_i2;
- unsigned long sc_i3;
- unsigned long sc_m0;
- unsigned long sc_m1;
- unsigned long sc_m2;
- unsigned long sc_m3;
- unsigned long sc_l0;
- unsigned long sc_l1;
- unsigned long sc_l2;
- unsigned long sc_l3;
- unsigned long sc_b0;
- unsigned long sc_b1;
- unsigned long sc_b2;
- unsigned long sc_b3;
- unsigned long sc_lc0;
- unsigned long sc_lc1;
- unsigned long sc_lt0;
- unsigned long sc_lt1;
- unsigned long sc_lb0;
- unsigned long sc_lb1;
- unsigned long sc_seqstat;
-};
-
-#endif /* _UAPI_ASM_BLACKFIN_SIGCONTEXT_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
-/*
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _UAPI_BFIN_SIGINFO_H
-#define _UAPI_BFIN_SIGINFO_H
-
-#include <linux/types.h>
-#include <asm-generic/siginfo.h>
-
-#define si_uid16 _sifields._kill._uid
-
-#endif /* _UAPI_BFIN_SIGINFO_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _UAPI_BLACKFIN_SIGNAL_H
-#define _UAPI_BLACKFIN_SIGNAL_H
-
-#define SA_RESTORER 0x04000000
-#include <asm-generic/signal.h>
-
-#endif /* _UAPI_BLACKFIN_SIGNAL_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * Copyright 2004-2006 Analog Devices Inc.
- *
- * Licensed under the GPL-2.
- */
-
-#ifndef _UAPI_BFIN_STAT_H
-#define _UAPI_BFIN_STAT_H
-
-struct stat {
- unsigned short st_dev;
- unsigned short __pad1;
- unsigned long st_ino;
- unsigned short st_mode;
- unsigned short st_nlink;
- unsigned short st_uid;
- unsigned short st_gid;
- unsigned short st_rdev;
- unsigned short __pad2;
- unsigned long st_size;
- unsigned long st_blksize;
- unsigned long st_blocks;
- unsigned long st_atime;
- unsigned long __unused1;
- unsigned long st_mtime;
- unsigned long __unused2;
- unsigned long st_ctime;
- unsigned long __unused3;
- unsigned long __unused4;
- unsigned long __unused5;
-};
-
-/* This matches struct stat64 in glibc2.1, hence the absolutely
- * insane amounts of padding around dev_t's.
- */
-struct stat64 {
- unsigned long long st_dev;
- unsigned char __pad1[4];
-
-#define STAT64_HAS_BROKEN_ST_INO 1
- unsigned long __st_ino;
-
- unsigned int st_mode;
- unsigned int st_nlink;
-
- unsigned long st_uid;
- unsigned long st_gid;
-
- unsigned long long st_rdev;
- unsigned char __pad2[4];
-
- long long st_size;
- unsigned long st_blksize;
-
- long long st_blocks; /* Number 512-byte blocks allocated. */
-
- unsigned long st_atime;
- unsigned long st_atime_nsec;
-
- unsigned long st_mtime;
- unsigned long st_mtime_nsec;
-
- unsigned long st_ctime;
- unsigned long st_ctime_nsec;
-
- unsigned long long st_ino;
-};
-
-#endif /* _UAPI_BFIN_STAT_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
-/*
- * Copyright 2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _UAPI_BLACKFIN_SWAB_H
-#define _UAPI_BLACKFIN_SWAB_H
-
-#include <linux/types.h>
-#include <asm-generic/swab.h>
-
-#ifdef __GNUC__
-
-static __inline__ __attribute_const__ __u32 __arch_swahb32(__u32 xx)
-{
- __u32 tmp;
- __asm__("%1 = %0 >> 8 (V);\n\t"
- "%0 = %0 << 8 (V);\n\t"
- "%0 = %0 | %1;\n\t"
- : "+d"(xx), "=&d"(tmp));
- return xx;
-}
-#define __arch_swahb32 __arch_swahb32
-
-static __inline__ __attribute_const__ __u32 __arch_swahw32(__u32 xx)
-{
- __u32 rv;
- __asm__("%0 = PACK(%1.L, %1.H);\n\t": "=d"(rv): "d"(xx));
- return rv;
-}
-#define __arch_swahw32 __arch_swahw32
-
-static __inline__ __attribute_const__ __u32 __arch_swab32(__u32 xx)
-{
- return __arch_swahb32(__arch_swahw32(xx));
-}
-#define __arch_swab32 __arch_swab32
-
-static __inline__ __attribute_const__ __u16 __arch_swab16(__u16 xx)
-{
- __u32 xw = xx;
- __asm__("%0 <<= 8;\n %0.L = %0.L + %0.H (NS);\n": "+d"(xw));
- return (__u16)xw;
-}
-#define __arch_swab16 __arch_swab16
-
-#endif /* __GNUC__ */
-
-#endif /* _UAPI_BLACKFIN_SWAB_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _UAPI__ASM_BFIN_UNISTD_H
-#define _UAPI__ASM_BFIN_UNISTD_H
-/*
- * This file contains the system call numbers.
- */
-#define __NR_restart_syscall 0
-#define __NR_exit 1
- /* 2 __NR_fork not supported on nommu */
-#define __NR_read 3
-#define __NR_write 4
-#define __NR_open 5
-#define __NR_close 6
- /* 7 __NR_waitpid obsolete */
-#define __NR_creat 8
-#define __NR_link 9
-#define __NR_unlink 10
-#define __NR_execve 11
-#define __NR_chdir 12
-#define __NR_time 13
-#define __NR_mknod 14
-#define __NR_chmod 15
-#define __NR_chown 16
- /* 17 __NR_break obsolete */
- /* 18 __NR_oldstat obsolete */
-#define __NR_lseek 19
-#define __NR_getpid 20
-#define __NR_mount 21
- /* 22 __NR_umount obsolete */
-#define __NR_setuid 23
-#define __NR_getuid 24
-#define __NR_stime 25
-#define __NR_ptrace 26
-#define __NR_alarm 27
- /* 28 __NR_oldfstat obsolete */
-#define __NR_pause 29
- /* 30 __NR_utime obsolete */
- /* 31 __NR_stty obsolete */
- /* 32 __NR_gtty obsolete */
-#define __NR_access 33
-#define __NR_nice 34
- /* 35 __NR_ftime obsolete */
-#define __NR_sync 36
-#define __NR_kill 37
-#define __NR_rename 38
-#define __NR_mkdir 39
-#define __NR_rmdir 40
-#define __NR_dup 41
-#define __NR_pipe 42
-#define __NR_times 43
- /* 44 __NR_prof obsolete */
-#define __NR_brk 45
-#define __NR_setgid 46
-#define __NR_getgid 47
- /* 48 __NR_signal obsolete */
-#define __NR_geteuid 49
-#define __NR_getegid 50
-#define __NR_acct 51
-#define __NR_umount2 52
- /* 53 __NR_lock obsolete */
-#define __NR_ioctl 54
-#define __NR_fcntl 55
- /* 56 __NR_mpx obsolete */
-#define __NR_setpgid 57
- /* 58 __NR_ulimit obsolete */
- /* 59 __NR_oldolduname obsolete */
-#define __NR_umask 60
-#define __NR_chroot 61
-#define __NR_ustat 62
-#define __NR_dup2 63
-#define __NR_getppid 64
-#define __NR_getpgrp 65
-#define __NR_setsid 66
- /* 67 __NR_sigaction obsolete */
-#define __NR_sgetmask 68
-#define __NR_ssetmask 69
-#define __NR_setreuid 70
-#define __NR_setregid 71
- /* 72 __NR_sigsuspend obsolete */
- /* 73 __NR_sigpending obsolete */
-#define __NR_sethostname 74
-#define __NR_setrlimit 75
- /* 76 __NR_old_getrlimit obsolete */
-#define __NR_getrusage 77
-#define __NR_gettimeofday 78
-#define __NR_settimeofday 79
-#define __NR_getgroups 80
-#define __NR_setgroups 81
- /* 82 __NR_select obsolete */
-#define __NR_symlink 83
- /* 84 __NR_oldlstat obsolete */
-#define __NR_readlink 85
- /* 86 __NR_uselib obsolete */
- /* 87 __NR_swapon obsolete */
-#define __NR_reboot 88
- /* 89 __NR_readdir obsolete */
- /* 90 __NR_mmap obsolete */
-#define __NR_munmap 91
-#define __NR_truncate 92
-#define __NR_ftruncate 93
-#define __NR_fchmod 94
-#define __NR_fchown 95
-#define __NR_getpriority 96
-#define __NR_setpriority 97
- /* 98 __NR_profil obsolete */
-#define __NR_statfs 99
-#define __NR_fstatfs 100
- /* 101 __NR_ioperm */
- /* 102 __NR_socketcall obsolete */
-#define __NR_syslog 103
-#define __NR_setitimer 104
-#define __NR_getitimer 105
-#define __NR_stat 106
-#define __NR_lstat 107
-#define __NR_fstat 108
- /* 109 __NR_olduname obsolete */
- /* 110 __NR_iopl obsolete */
-#define __NR_vhangup 111
- /* 112 __NR_idle obsolete */
- /* 113 __NR_vm86old */
-#define __NR_wait4 114
- /* 115 __NR_swapoff obsolete */
-#define __NR_sysinfo 116
- /* 117 __NR_ipc oboslete */
-#define __NR_fsync 118
- /* 119 __NR_sigreturn obsolete */
-#define __NR_clone 120
-#define __NR_setdomainname 121
-#define __NR_uname 122
- /* 123 __NR_modify_ldt obsolete */
-#define __NR_adjtimex 124
-#define __NR_mprotect 125
- /* 126 __NR_sigprocmask obsolete */
- /* 127 __NR_create_module obsolete */
-#define __NR_init_module 128
-#define __NR_delete_module 129
- /* 130 __NR_get_kernel_syms obsolete */
-#define __NR_quotactl 131
-#define __NR_getpgid 132
-#define __NR_fchdir 133
-#define __NR_bdflush 134
- /* 135 was sysfs */
-#define __NR_personality 136
- /* 137 __NR_afs_syscall */
-#define __NR_setfsuid 138
-#define __NR_setfsgid 139
-#define __NR__llseek 140
-#define __NR_getdents 141
- /* 142 __NR__newselect obsolete */
-#define __NR_flock 143
- /* 144 __NR_msync obsolete */
-#define __NR_readv 145
-#define __NR_writev 146
-#define __NR_getsid 147
-#define __NR_fdatasync 148
-#define __NR__sysctl 149
- /* 150 __NR_mlock */
- /* 151 __NR_munlock */
- /* 152 __NR_mlockall */
- /* 153 __NR_munlockall */
-#define __NR_sched_setparam 154
-#define __NR_sched_getparam 155
-#define __NR_sched_setscheduler 156
-#define __NR_sched_getscheduler 157
-#define __NR_sched_yield 158
-#define __NR_sched_get_priority_max 159
-#define __NR_sched_get_priority_min 160
-#define __NR_sched_rr_get_interval 161
-#define __NR_nanosleep 162
-#define __NR_mremap 163
-#define __NR_setresuid 164
-#define __NR_getresuid 165
- /* 166 __NR_vm86 */
- /* 167 __NR_query_module */
- /* 168 __NR_poll */
-#define __NR_nfsservctl 169
-#define __NR_setresgid 170
-#define __NR_getresgid 171
-#define __NR_prctl 172
-#define __NR_rt_sigreturn 173
-#define __NR_rt_sigaction 174
-#define __NR_rt_sigprocmask 175
-#define __NR_rt_sigpending 176
-#define __NR_rt_sigtimedwait 177
-#define __NR_rt_sigqueueinfo 178
-#define __NR_rt_sigsuspend 179
-#define __NR_pread 180
-#define __NR_pwrite 181
-#define __NR_lchown 182
-#define __NR_getcwd 183
-#define __NR_capget 184
-#define __NR_capset 185
-#define __NR_sigaltstack 186
-#define __NR_sendfile 187
- /* 188 __NR_getpmsg */
- /* 189 __NR_putpmsg */
-#define __NR_vfork 190
-#define __NR_getrlimit 191
-#define __NR_mmap2 192
-#define __NR_truncate64 193
-#define __NR_ftruncate64 194
-#define __NR_stat64 195
-#define __NR_lstat64 196
-#define __NR_fstat64 197
-#define __NR_chown32 198
-#define __NR_getuid32 199
-#define __NR_getgid32 200
-#define __NR_geteuid32 201
-#define __NR_getegid32 202
-#define __NR_setreuid32 203
-#define __NR_setregid32 204
-#define __NR_getgroups32 205
-#define __NR_setgroups32 206
-#define __NR_fchown32 207
-#define __NR_setresuid32 208
-#define __NR_getresuid32 209
-#define __NR_setresgid32 210
-#define __NR_getresgid32 211
-#define __NR_lchown32 212
-#define __NR_setuid32 213
-#define __NR_setgid32 214
-#define __NR_setfsuid32 215
-#define __NR_setfsgid32 216
-#define __NR_pivot_root 217
- /* 218 __NR_mincore */
- /* 219 __NR_madvise */
-#define __NR_getdents64 220
-#define __NR_fcntl64 221
- /* 222 reserved for TUX */
- /* 223 reserved for TUX */
-#define __NR_gettid 224
-#define __NR_readahead 225
-#define __NR_setxattr 226
-#define __NR_lsetxattr 227
-#define __NR_fsetxattr 228
-#define __NR_getxattr 229
-#define __NR_lgetxattr 230
-#define __NR_fgetxattr 231
-#define __NR_listxattr 232
-#define __NR_llistxattr 233
-#define __NR_flistxattr 234
-#define __NR_removexattr 235
-#define __NR_lremovexattr 236
-#define __NR_fremovexattr 237
-#define __NR_tkill 238
-#define __NR_sendfile64 239
-#define __NR_futex 240
-#define __NR_sched_setaffinity 241
-#define __NR_sched_getaffinity 242
- /* 243 __NR_set_thread_area */
- /* 244 __NR_get_thread_area */
-#define __NR_io_setup 245
-#define __NR_io_destroy 246
-#define __NR_io_getevents 247
-#define __NR_io_submit 248
-#define __NR_io_cancel 249
- /* 250 __NR_alloc_hugepages */
- /* 251 __NR_free_hugepages */
-#define __NR_exit_group 252
-#define __NR_lookup_dcookie 253
-#define __NR_bfin_spinlock 254
-
-#define __NR_epoll_create 255
-#define __NR_epoll_ctl 256
-#define __NR_epoll_wait 257
- /* 258 __NR_remap_file_pages */
-#define __NR_set_tid_address 259
-#define __NR_timer_create 260
-#define __NR_timer_settime 261
-#define __NR_timer_gettime 262
-#define __NR_timer_getoverrun 263
-#define __NR_timer_delete 264
-#define __NR_clock_settime 265
-#define __NR_clock_gettime 266
-#define __NR_clock_getres 267
-#define __NR_clock_nanosleep 268
-#define __NR_statfs64 269
-#define __NR_fstatfs64 270
-#define __NR_tgkill 271
-#define __NR_utimes 272
-#define __NR_fadvise64_64 273
- /* 274 __NR_vserver */
- /* 275 __NR_mbind */
- /* 276 __NR_get_mempolicy */
- /* 277 __NR_set_mempolicy */
-#define __NR_mq_open 278
-#define __NR_mq_unlink 279
-#define __NR_mq_timedsend 280
-#define __NR_mq_timedreceive 281
-#define __NR_mq_notify 282
-#define __NR_mq_getsetattr 283
-#define __NR_kexec_load 284
-#define __NR_waitid 285
-#define __NR_add_key 286
-#define __NR_request_key 287
-#define __NR_keyctl 288
-#define __NR_ioprio_set 289
-#define __NR_ioprio_get 290
-#define __NR_inotify_init 291
-#define __NR_inotify_add_watch 292
-#define __NR_inotify_rm_watch 293
- /* 294 __NR_migrate_pages */
-#define __NR_openat 295
-#define __NR_mkdirat 296
-#define __NR_mknodat 297
-#define __NR_fchownat 298
-#define __NR_futimesat 299
-#define __NR_fstatat64 300
-#define __NR_unlinkat 301
-#define __NR_renameat 302
-#define __NR_linkat 303
-#define __NR_symlinkat 304
-#define __NR_readlinkat 305
-#define __NR_fchmodat 306
-#define __NR_faccessat 307
-#define __NR_pselect6 308
-#define __NR_ppoll 309
-#define __NR_unshare 310
-
-/* Blackfin private syscalls */
-#define __NR_sram_alloc 311
-#define __NR_sram_free 312
-#define __NR_dma_memcpy 313
-
-/* socket syscalls */
-#define __NR_accept 314
-#define __NR_bind 315
-#define __NR_connect 316
-#define __NR_getpeername 317
-#define __NR_getsockname 318
-#define __NR_getsockopt 319
-#define __NR_listen 320
-#define __NR_recv 321
-#define __NR_recvfrom 322
-#define __NR_recvmsg 323
-#define __NR_send 324
-#define __NR_sendmsg 325
-#define __NR_sendto 326
-#define __NR_setsockopt 327
-#define __NR_shutdown 328
-#define __NR_socket 329
-#define __NR_socketpair 330
-
-/* sysv ipc syscalls */
-#define __NR_semctl 331
-#define __NR_semget 332
-#define __NR_semop 333
-#define __NR_msgctl 334
-#define __NR_msgget 335
-#define __NR_msgrcv 336
-#define __NR_msgsnd 337
-#define __NR_shmat 338
-#define __NR_shmctl 339
-#define __NR_shmdt 340
-#define __NR_shmget 341
-
-#define __NR_splice 342
-#define __NR_sync_file_range 343
-#define __NR_tee 344
-#define __NR_vmsplice 345
-
-#define __NR_epoll_pwait 346
-#define __NR_utimensat 347
-#define __NR_signalfd 348
-#define __NR_timerfd_create 349
-#define __NR_eventfd 350
-#define __NR_pread64 351
-#define __NR_pwrite64 352
-#define __NR_fadvise64 353
-#define __NR_set_robust_list 354
-#define __NR_get_robust_list 355
-#define __NR_fallocate 356
-#define __NR_semtimedop 357
-#define __NR_timerfd_settime 358
-#define __NR_timerfd_gettime 359
-#define __NR_signalfd4 360
-#define __NR_eventfd2 361
-#define __NR_epoll_create1 362
-#define __NR_dup3 363
-#define __NR_pipe2 364
-#define __NR_inotify_init1 365
-#define __NR_preadv 366
-#define __NR_pwritev 367
-#define __NR_rt_tgsigqueueinfo 368
-#define __NR_perf_event_open 369
-#define __NR_recvmmsg 370
-#define __NR_fanotify_init 371
-#define __NR_fanotify_mark 372
-#define __NR_prlimit64 373
-#define __NR_cacheflush 374
-#define __NR_name_to_handle_at 375
-#define __NR_open_by_handle_at 376
-#define __NR_clock_adjtime 377
-#define __NR_syncfs 378
-#define __NR_setns 379
-#define __NR_sendmmsg 380
-#define __NR_process_vm_readv 381
-#define __NR_process_vm_writev 382
-#define __NR_kcmp 383
-#define __NR_finit_module 384
-#define __NR_sched_setattr 385
-#define __NR_sched_getattr 386
-#define __NR_renameat2 387
-#define __NR_seccomp 388
-#define __NR_getrandom 389
-#define __NR_memfd_create 390
-#define __NR_bpf 391
-#define __NR_execveat 392
-
-#define __NR_syscall 393 /* For internal using, not implemented */
-#define NR_syscalls __NR_syscall
-
-/* Old optional stuff no one actually uses */
-#define __IGNORE_sysfs
-#define __IGNORE_uselib
-
-/* Implement the newer interfaces */
-#define __IGNORE_mmap
-#define __IGNORE_poll
-#define __IGNORE_select
-#define __IGNORE_utime
-
-/* Not relevant on no-mmu */
-#define __IGNORE_swapon
-#define __IGNORE_swapoff
-#define __IGNORE_msync
-#define __IGNORE_mlock
-#define __IGNORE_munlock
-#define __IGNORE_mlockall
-#define __IGNORE_munlockall
-#define __IGNORE_mincore
-#define __IGNORE_madvise
-#define __IGNORE_remap_file_pages
-#define __IGNORE_mbind
-#define __IGNORE_get_mempolicy
-#define __IGNORE_set_mempolicy
-#define __IGNORE_migrate_pages
-#define __IGNORE_move_pages
-#define __IGNORE_getcpu
-
-
-#endif /* _UAPI__ASM_BFIN_UNISTD_H */
+++ /dev/null
-vmlinux.lds
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0
-#
-# arch/blackfin/kernel/Makefile
-#
-
-extra-y := vmlinux.lds
-
-obj-y := \
- entry.o process.o bfin_ksyms.o ptrace.o setup.o signal.o \
- sys_bfin.o traps.o irqchip.o dma-mapping.o flat.o \
- fixed_code.o reboot.o bfin_dma.o \
- exception.o dumpstack.o
-
-ifeq ($(CONFIG_GENERIC_CLOCKEVENTS),y)
- obj-y += time-ts.o
-else
- obj-y += time.o
-endif
-
-obj-$(CONFIG_GPIO_ADI) += bfin_gpio.o
-obj-$(CONFIG_DYNAMIC_FTRACE) += ftrace.o
-obj-$(CONFIG_FUNCTION_TRACER) += ftrace-entry.o
-obj-$(CONFIG_FUNCTION_GRAPH_TRACER) += ftrace.o
-CFLAGS_REMOVE_ftrace.o = -pg
-
-obj-$(CONFIG_IPIPE) += ipipe.o
-obj-$(CONFIG_BFIN_GPTIMERS) += gptimers.o
-obj-$(CONFIG_CPLB_INFO) += cplbinfo.o
-obj-$(CONFIG_MODULES) += module.o
-obj-$(CONFIG_KGDB) += kgdb.o
-obj-$(CONFIG_KGDB_TESTS) += kgdb_test.o
-obj-$(CONFIG_NMI_WATCHDOG) += nmi.o
-obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
-obj-$(CONFIG_EARLY_PRINTK) += shadow_console.o
-obj-$(CONFIG_STACKTRACE) += stacktrace.o
-obj-$(CONFIG_DEBUG_VERBOSE) += trace.o
-obj-$(CONFIG_BFIN_PSEUDODBG_INSNS) += pseudodbg.o
-obj-$(CONFIG_PERF_EVENTS) += perf_event.o
-
-# the kgdb test puts code into L2 and without linker
-# relaxation, we need to force long calls to/from it
-CFLAGS_kgdb_test.o := -mlong-calls
-
-obj-$(CONFIG_DEBUG_MMRS) += debug-mmrs.o
+++ /dev/null
-/*
- * generate definitions needed by assembly language modules
- *
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <linux/stddef.h>
-#include <linux/sched.h>
-#include <linux/kernel_stat.h>
-#include <linux/ptrace.h>
-#include <linux/hardirq.h>
-#include <linux/irq.h>
-#include <linux/thread_info.h>
-#include <linux/kbuild.h>
-#include <asm/pda.h>
-
-int main(void)
-{
- /* offsets into the task struct */
- DEFINE(TASK_STATE, offsetof(struct task_struct, state));
- DEFINE(TASK_FLAGS, offsetof(struct task_struct, flags));
- DEFINE(TASK_PTRACE, offsetof(struct task_struct, ptrace));
- DEFINE(TASK_BLOCKED, offsetof(struct task_struct, blocked));
- DEFINE(TASK_THREAD, offsetof(struct task_struct, thread));
- DEFINE(TASK_THREAD_INFO, offsetof(struct task_struct, stack));
- DEFINE(TASK_MM, offsetof(struct task_struct, mm));
- DEFINE(TASK_ACTIVE_MM, offsetof(struct task_struct, active_mm));
- DEFINE(TASK_SIGPENDING, offsetof(struct task_struct, pending));
-
- /* offsets into the irq_cpustat_t struct */
- DEFINE(CPUSTAT_SOFTIRQ_PENDING,
- offsetof(irq_cpustat_t, __softirq_pending));
-
- /* offsets into the thread struct */
- DEFINE(THREAD_KSP, offsetof(struct thread_struct, ksp));
- DEFINE(THREAD_USP, offsetof(struct thread_struct, usp));
- DEFINE(THREAD_SR, offsetof(struct thread_struct, seqstat));
- DEFINE(PT_SR, offsetof(struct thread_struct, seqstat));
- DEFINE(THREAD_ESP0, offsetof(struct thread_struct, esp0));
- DEFINE(THREAD_PC, offsetof(struct thread_struct, pc));
- DEFINE(KERNEL_STACK_SIZE, THREAD_SIZE);
-
- /* offsets in thread_info struct */
- OFFSET(TI_TASK, thread_info, task);
- OFFSET(TI_FLAGS, thread_info, flags);
- OFFSET(TI_CPU, thread_info, cpu);
- OFFSET(TI_PREEMPT, thread_info, preempt_count);
-
- /* offsets into the pt_regs */
- DEFINE(PT_ORIG_R0, offsetof(struct pt_regs, orig_r0));
- DEFINE(PT_ORIG_P0, offsetof(struct pt_regs, orig_p0));
- DEFINE(PT_ORIG_PC, offsetof(struct pt_regs, orig_pc));
- DEFINE(PT_R0, offsetof(struct pt_regs, r0));
- DEFINE(PT_R1, offsetof(struct pt_regs, r1));
- DEFINE(PT_R2, offsetof(struct pt_regs, r2));
- DEFINE(PT_R3, offsetof(struct pt_regs, r3));
- DEFINE(PT_R4, offsetof(struct pt_regs, r4));
- DEFINE(PT_R5, offsetof(struct pt_regs, r5));
- DEFINE(PT_R6, offsetof(struct pt_regs, r6));
- DEFINE(PT_R7, offsetof(struct pt_regs, r7));
-
- DEFINE(PT_P0, offsetof(struct pt_regs, p0));
- DEFINE(PT_P1, offsetof(struct pt_regs, p1));
- DEFINE(PT_P2, offsetof(struct pt_regs, p2));
- DEFINE(PT_P3, offsetof(struct pt_regs, p3));
- DEFINE(PT_P4, offsetof(struct pt_regs, p4));
- DEFINE(PT_P5, offsetof(struct pt_regs, p5));
-
- DEFINE(PT_FP, offsetof(struct pt_regs, fp));
- DEFINE(PT_USP, offsetof(struct pt_regs, usp));
- DEFINE(PT_I0, offsetof(struct pt_regs, i0));
- DEFINE(PT_I1, offsetof(struct pt_regs, i1));
- DEFINE(PT_I2, offsetof(struct pt_regs, i2));
- DEFINE(PT_I3, offsetof(struct pt_regs, i3));
- DEFINE(PT_M0, offsetof(struct pt_regs, m0));
- DEFINE(PT_M1, offsetof(struct pt_regs, m1));
- DEFINE(PT_M2, offsetof(struct pt_regs, m2));
- DEFINE(PT_M3, offsetof(struct pt_regs, m3));
- DEFINE(PT_L0, offsetof(struct pt_regs, l0));
- DEFINE(PT_L1, offsetof(struct pt_regs, l1));
- DEFINE(PT_L2, offsetof(struct pt_regs, l2));
- DEFINE(PT_L3, offsetof(struct pt_regs, l3));
- DEFINE(PT_B0, offsetof(struct pt_regs, b0));
- DEFINE(PT_B1, offsetof(struct pt_regs, b1));
- DEFINE(PT_B2, offsetof(struct pt_regs, b2));
- DEFINE(PT_B3, offsetof(struct pt_regs, b3));
- DEFINE(PT_A0X, offsetof(struct pt_regs, a0x));
- DEFINE(PT_A0W, offsetof(struct pt_regs, a0w));
- DEFINE(PT_A1X, offsetof(struct pt_regs, a1x));
- DEFINE(PT_A1W, offsetof(struct pt_regs, a1w));
- DEFINE(PT_LC0, offsetof(struct pt_regs, lc0));
- DEFINE(PT_LC1, offsetof(struct pt_regs, lc1));
- DEFINE(PT_LT0, offsetof(struct pt_regs, lt0));
- DEFINE(PT_LT1, offsetof(struct pt_regs, lt1));
- DEFINE(PT_LB0, offsetof(struct pt_regs, lb0));
- DEFINE(PT_LB1, offsetof(struct pt_regs, lb1));
- DEFINE(PT_ASTAT, offsetof(struct pt_regs, astat));
- DEFINE(PT_RESERVED, offsetof(struct pt_regs, reserved));
- DEFINE(PT_RETS, offsetof(struct pt_regs, rets));
- DEFINE(PT_PC, offsetof(struct pt_regs, pc));
- DEFINE(PT_RETX, offsetof(struct pt_regs, retx));
- DEFINE(PT_RETN, offsetof(struct pt_regs, retn));
- DEFINE(PT_RETE, offsetof(struct pt_regs, rete));
- DEFINE(PT_SEQSTAT, offsetof(struct pt_regs, seqstat));
- DEFINE(PT_SYSCFG, offsetof(struct pt_regs, syscfg));
- DEFINE(PT_IPEND, offsetof(struct pt_regs, ipend));
- DEFINE(SIZEOF_PTREGS, sizeof(struct pt_regs));
- DEFINE(PT_TEXT_ADDR, sizeof(struct pt_regs)); /* Needed by gdb */
- DEFINE(PT_TEXT_END_ADDR, 4 + sizeof(struct pt_regs));/* Needed by gdb */
- DEFINE(PT_DATA_ADDR, 8 + sizeof(struct pt_regs)); /* Needed by gdb */
- DEFINE(PT_FDPIC_EXEC, 12 + sizeof(struct pt_regs)); /* Needed by gdb */
- DEFINE(PT_FDPIC_INTERP, 16 + sizeof(struct pt_regs));/* Needed by gdb */
-
- /* signal defines */
- DEFINE(SIGSEGV, SIGSEGV);
- DEFINE(SIGTRAP, SIGTRAP);
-
- /* PDA management (in L1 scratchpad) */
- DEFINE(PDA_SYSCFG, offsetof(struct blackfin_pda, syscfg));
-#ifdef CONFIG_SMP
- DEFINE(PDA_IRQFLAGS, offsetof(struct blackfin_pda, imask));
-#endif
- DEFINE(PDA_IPDT, offsetof(struct blackfin_pda, ipdt));
- DEFINE(PDA_IPDT_SWAPCOUNT, offsetof(struct blackfin_pda, ipdt_swapcount));
- DEFINE(PDA_DPDT, offsetof(struct blackfin_pda, dpdt));
- DEFINE(PDA_DPDT_SWAPCOUNT, offsetof(struct blackfin_pda, dpdt_swapcount));
- DEFINE(PDA_EXIPTR, offsetof(struct blackfin_pda, ex_iptr));
- DEFINE(PDA_EXOPTR, offsetof(struct blackfin_pda, ex_optr));
- DEFINE(PDA_EXBUF, offsetof(struct blackfin_pda, ex_buf));
- DEFINE(PDA_EXIMASK, offsetof(struct blackfin_pda, ex_imask));
- DEFINE(PDA_EXSTACK, offsetof(struct blackfin_pda, ex_stack));
- DEFINE(PDA_EXIPEND, offsetof(struct blackfin_pda, ex_ipend));
-#ifdef ANOMALY_05000261
- DEFINE(PDA_LFRETX, offsetof(struct blackfin_pda, last_cplb_fault_retx));
-#endif
- DEFINE(PDA_DCPLB, offsetof(struct blackfin_pda, dcplb_fault_addr));
- DEFINE(PDA_ICPLB, offsetof(struct blackfin_pda, icplb_fault_addr));
- DEFINE(PDA_RETX, offsetof(struct blackfin_pda, retx));
- DEFINE(PDA_SEQSTAT, offsetof(struct blackfin_pda, seqstat));
-#ifdef CONFIG_DEBUG_DOUBLEFAULT
- DEFINE(PDA_DF_DCPLB, offsetof(struct blackfin_pda, dcplb_doublefault_addr));
- DEFINE(PDA_DF_ICPLB, offsetof(struct blackfin_pda, icplb_doublefault_addr));
- DEFINE(PDA_DF_SEQSTAT, offsetof(struct blackfin_pda, seqstat_doublefault));
- DEFINE(PDA_DF_RETX, offsetof(struct blackfin_pda, retx_doublefault));
-#endif
-
- /* PDA initial management */
- DEFINE(PDA_INIT_RETX, offsetof(struct blackfin_initial_pda, retx));
-#ifdef CONFIG_DEBUG_DOUBLEFAULT
- DEFINE(PDA_INIT_DF_DCPLB, offsetof(struct blackfin_initial_pda, dcplb_doublefault_addr));
- DEFINE(PDA_INIT_DF_ICPLB, offsetof(struct blackfin_initial_pda, icplb_doublefault_addr));
- DEFINE(PDA_INIT_DF_SEQSTAT, offsetof(struct blackfin_initial_pda, seqstat_doublefault));
- DEFINE(PDA_INIT_DF_RETX, offsetof(struct blackfin_initial_pda, retx_doublefault));
-#endif
-
-#ifdef CONFIG_SMP
- /* Inter-core lock (in L2 SRAM) */
- DEFINE(SIZEOF_CORELOCK, sizeof(struct corelock_slot));
-#endif
-
- return 0;
-}
+++ /dev/null
-/*
- * bfin_dma.c - Blackfin DMA implementation
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/errno.h>
-#include <linux/interrupt.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/param.h>
-#include <linux/proc_fs.h>
-#include <linux/sched.h>
-#include <linux/seq_file.h>
-#include <linux/spinlock.h>
-
-#include <asm/blackfin.h>
-#include <asm/cacheflush.h>
-#include <asm/dma.h>
-#include <linux/uaccess.h>
-#include <asm/early_printk.h>
-
-/*
- * To make sure we work around 05000119 - we always check DMA_DONE bit,
- * never the DMA_RUN bit
- */
-
-struct dma_channel dma_ch[MAX_DMA_CHANNELS];
-EXPORT_SYMBOL(dma_ch);
-
-static int __init blackfin_dma_init(void)
-{
- int i;
-
- printk(KERN_INFO "Blackfin DMA Controller\n");
-
-
-#if ANOMALY_05000480
- bfin_write_DMAC_TC_PER(0x0111);
-#endif
-
- for (i = 0; i < MAX_DMA_CHANNELS; i++) {
- atomic_set(&dma_ch[i].chan_status, 0);
- dma_ch[i].regs = dma_io_base_addr[i];
- }
-#if defined(CH_MEM_STREAM3_SRC) && defined(CONFIG_BF60x)
- /* Mark MEMDMA Channel 3 as requested since we're using it internally */
- request_dma(CH_MEM_STREAM3_DEST, "Blackfin dma_memcpy");
- request_dma(CH_MEM_STREAM3_SRC, "Blackfin dma_memcpy");
-#else
- /* Mark MEMDMA Channel 0 as requested since we're using it internally */
- request_dma(CH_MEM_STREAM0_DEST, "Blackfin dma_memcpy");
- request_dma(CH_MEM_STREAM0_SRC, "Blackfin dma_memcpy");
-#endif
-
-#if defined(CONFIG_DEB_DMA_URGENT)
- bfin_write_EBIU_DDRQUE(bfin_read_EBIU_DDRQUE()
- | DEB1_URGENT | DEB2_URGENT | DEB3_URGENT);
-#endif
-
- return 0;
-}
-arch_initcall(blackfin_dma_init);
-
-#ifdef CONFIG_PROC_FS
-static int proc_dma_show(struct seq_file *m, void *v)
-{
- int i;
-
- for (i = 0; i < MAX_DMA_CHANNELS; ++i)
- if (dma_channel_active(i))
- seq_printf(m, "%2d: %s\n", i, dma_ch[i].device_id);
-
- return 0;
-}
-
-static int proc_dma_open(struct inode *inode, struct file *file)
-{
- return single_open(file, proc_dma_show, NULL);
-}
-
-static const struct file_operations proc_dma_operations = {
- .open = proc_dma_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = single_release,
-};
-
-static int __init proc_dma_init(void)
-{
- proc_create("dma", 0, NULL, &proc_dma_operations);
- return 0;
-}
-late_initcall(proc_dma_init);
-#endif
-
-static void set_dma_peripheral_map(unsigned int channel, const char *device_id)
-{
-#ifdef CONFIG_BF54x
- unsigned int per_map;
-
- switch (channel) {
- case CH_UART2_RX: per_map = 0xC << 12; break;
- case CH_UART2_TX: per_map = 0xD << 12; break;
- case CH_UART3_RX: per_map = 0xE << 12; break;
- case CH_UART3_TX: per_map = 0xF << 12; break;
- default: return;
- }
-
- if (strncmp(device_id, "BFIN_UART", 9) == 0)
- dma_ch[channel].regs->peripheral_map = per_map;
-#endif
-}
-
-/**
- * request_dma - request a DMA channel
- *
- * Request the specific DMA channel from the system if it's available.
- */
-int request_dma(unsigned int channel, const char *device_id)
-{
- pr_debug("request_dma() : BEGIN\n");
-
- if (device_id == NULL)
- printk(KERN_WARNING "request_dma(%u): no device_id given\n", channel);
-
-#if defined(CONFIG_BF561) && ANOMALY_05000182
- if (channel >= CH_IMEM_STREAM0_DEST && channel <= CH_IMEM_STREAM1_DEST) {
- if (get_cclk() > 500000000) {
- printk(KERN_WARNING
- "Request IMDMA failed due to ANOMALY 05000182\n");
- return -EFAULT;
- }
- }
-#endif
-
- if (atomic_cmpxchg(&dma_ch[channel].chan_status, 0, 1)) {
- pr_debug("DMA CHANNEL IN USE\n");
- return -EBUSY;
- }
-
- set_dma_peripheral_map(channel, device_id);
- dma_ch[channel].device_id = device_id;
- dma_ch[channel].irq = 0;
-
- /* This is to be enabled by putting a restriction -
- * you have to request DMA, before doing any operations on
- * descriptor/channel
- */
- pr_debug("request_dma() : END\n");
- return 0;
-}
-EXPORT_SYMBOL(request_dma);
-
-int set_dma_callback(unsigned int channel, irq_handler_t callback, void *data)
-{
- int ret;
- unsigned int irq;
-
- BUG_ON(channel >= MAX_DMA_CHANNELS || !callback ||
- !atomic_read(&dma_ch[channel].chan_status));
-
- irq = channel2irq(channel);
- ret = request_irq(irq, callback, 0, dma_ch[channel].device_id, data);
- if (ret)
- return ret;
-
- dma_ch[channel].irq = irq;
- dma_ch[channel].data = data;
-
- return 0;
-}
-EXPORT_SYMBOL(set_dma_callback);
-
-/**
- * clear_dma_buffer - clear DMA fifos for specified channel
- *
- * Set the Buffer Clear bit in the Configuration register of specific DMA
- * channel. This will stop the descriptor based DMA operation.
- */
-static void clear_dma_buffer(unsigned int channel)
-{
- dma_ch[channel].regs->cfg |= RESTART;
- SSYNC();
- dma_ch[channel].regs->cfg &= ~RESTART;
-}
-
-void free_dma(unsigned int channel)
-{
- pr_debug("freedma() : BEGIN\n");
- BUG_ON(channel >= MAX_DMA_CHANNELS ||
- !atomic_read(&dma_ch[channel].chan_status));
-
- /* Halt the DMA */
- disable_dma(channel);
- clear_dma_buffer(channel);
-
- if (dma_ch[channel].irq)
- free_irq(dma_ch[channel].irq, dma_ch[channel].data);
-
- /* Clear the DMA Variable in the Channel */
- atomic_set(&dma_ch[channel].chan_status, 0);
-
- pr_debug("freedma() : END\n");
-}
-EXPORT_SYMBOL(free_dma);
-
-#ifdef CONFIG_PM
-# ifndef MAX_DMA_SUSPEND_CHANNELS
-# define MAX_DMA_SUSPEND_CHANNELS MAX_DMA_CHANNELS
-# endif
-# ifndef CONFIG_BF60x
-int blackfin_dma_suspend(void)
-{
- int i;
-
- for (i = 0; i < MAX_DMA_CHANNELS; ++i) {
- if (dma_ch[i].regs->cfg & DMAEN) {
- printk(KERN_ERR "DMA Channel %d failed to suspend\n", i);
- return -EBUSY;
- }
- if (i < MAX_DMA_SUSPEND_CHANNELS)
- dma_ch[i].saved_peripheral_map = dma_ch[i].regs->peripheral_map;
- }
-
-#if ANOMALY_05000480
- bfin_write_DMAC_TC_PER(0x0);
-#endif
- return 0;
-}
-
-void blackfin_dma_resume(void)
-{
- int i;
-
- for (i = 0; i < MAX_DMA_CHANNELS; ++i) {
- dma_ch[i].regs->cfg = 0;
- if (i < MAX_DMA_SUSPEND_CHANNELS)
- dma_ch[i].regs->peripheral_map = dma_ch[i].saved_peripheral_map;
- }
-#if ANOMALY_05000480
- bfin_write_DMAC_TC_PER(0x0111);
-#endif
-}
-# else
-int blackfin_dma_suspend(void)
-{
- return 0;
-}
-
-void blackfin_dma_resume(void)
-{
-}
-#endif
-#endif
-
-/**
- * blackfin_dma_early_init - minimal DMA init
- *
- * Setup a few DMA registers so we can safely do DMA transfers early on in
- * the kernel booting process. Really this just means using dma_memcpy().
- */
-void __init blackfin_dma_early_init(void)
-{
- early_shadow_stamp();
- bfin_write_MDMA_S0_CONFIG(0);
- bfin_write_MDMA_S1_CONFIG(0);
-}
-
-void __init early_dma_memcpy(void *pdst, const void *psrc, size_t size)
-{
- unsigned long dst = (unsigned long)pdst;
- unsigned long src = (unsigned long)psrc;
- struct dma_register *dst_ch, *src_ch;
-
- early_shadow_stamp();
-
- /* We assume that everything is 4 byte aligned, so include
- * a basic sanity check
- */
- BUG_ON(dst % 4);
- BUG_ON(src % 4);
- BUG_ON(size % 4);
-
- src_ch = 0;
- /* Find an avalible memDMA channel */
- while (1) {
- if (src_ch == (struct dma_register *)MDMA_S0_NEXT_DESC_PTR) {
- dst_ch = (struct dma_register *)MDMA_D1_NEXT_DESC_PTR;
- src_ch = (struct dma_register *)MDMA_S1_NEXT_DESC_PTR;
- } else {
- dst_ch = (struct dma_register *)MDMA_D0_NEXT_DESC_PTR;
- src_ch = (struct dma_register *)MDMA_S0_NEXT_DESC_PTR;
- }
-
- if (!DMA_MMR_READ(&src_ch->cfg))
- break;
- else if (DMA_MMR_READ(&dst_ch->irq_status) & DMA_DONE) {
- DMA_MMR_WRITE(&src_ch->cfg, 0);
- break;
- }
- }
-
- /* Force a sync in case a previous config reset on this channel
- * occurred. This is needed so subsequent writes to DMA registers
- * are not spuriously lost/corrupted.
- */
- __builtin_bfin_ssync();
-
- /* Destination */
- bfin_write32(&dst_ch->start_addr, dst);
- DMA_MMR_WRITE(&dst_ch->x_count, size >> 2);
- DMA_MMR_WRITE(&dst_ch->x_modify, 1 << 2);
- DMA_MMR_WRITE(&dst_ch->irq_status, DMA_DONE | DMA_ERR);
-
- /* Source */
- bfin_write32(&src_ch->start_addr, src);
- DMA_MMR_WRITE(&src_ch->x_count, size >> 2);
- DMA_MMR_WRITE(&src_ch->x_modify, 1 << 2);
- DMA_MMR_WRITE(&src_ch->irq_status, DMA_DONE | DMA_ERR);
-
- /* Enable */
- DMA_MMR_WRITE(&src_ch->cfg, DMAEN | WDSIZE_32);
- DMA_MMR_WRITE(&dst_ch->cfg, WNR | DI_EN_X | DMAEN | WDSIZE_32);
-
- /* Since we are atomic now, don't use the workaround ssync */
- __builtin_bfin_ssync();
-
-#ifdef CONFIG_BF60x
- /* Work around a possible MDMA anomaly. Running 2 MDMA channels to
- * transfer DDR data to L1 SRAM may corrupt data.
- * Should be reverted after this issue is root caused.
- */
- while (!(DMA_MMR_READ(&dst_ch->irq_status) & DMA_DONE))
- continue;
-#endif
-}
-
-void __init early_dma_memcpy_done(void)
-{
- early_shadow_stamp();
-
- while ((bfin_read_MDMA_S0_CONFIG() && !(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE)) ||
- (bfin_read_MDMA_S1_CONFIG() && !(bfin_read_MDMA_D1_IRQ_STATUS() & DMA_DONE)))
- continue;
-
- bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
- bfin_write_MDMA_D1_IRQ_STATUS(DMA_DONE | DMA_ERR);
- /*
- * Now that DMA is done, we would normally flush cache, but
- * i/d cache isn't running this early, so we don't bother,
- * and just clear out the DMA channel for next time
- */
- bfin_write_MDMA_S0_CONFIG(0);
- bfin_write_MDMA_S1_CONFIG(0);
- bfin_write_MDMA_D0_CONFIG(0);
- bfin_write_MDMA_D1_CONFIG(0);
-
- __builtin_bfin_ssync();
-}
-
-#if defined(CH_MEM_STREAM3_SRC) && defined(CONFIG_BF60x)
-#define bfin_read_MDMA_S_CONFIG bfin_read_MDMA_S3_CONFIG
-#define bfin_write_MDMA_S_CONFIG bfin_write_MDMA_S3_CONFIG
-#define bfin_write_MDMA_S_START_ADDR bfin_write_MDMA_S3_START_ADDR
-#define bfin_write_MDMA_S_IRQ_STATUS bfin_write_MDMA_S3_IRQ_STATUS
-#define bfin_write_MDMA_S_X_COUNT bfin_write_MDMA_S3_X_COUNT
-#define bfin_write_MDMA_S_X_MODIFY bfin_write_MDMA_S3_X_MODIFY
-#define bfin_write_MDMA_S_Y_COUNT bfin_write_MDMA_S3_Y_COUNT
-#define bfin_write_MDMA_S_Y_MODIFY bfin_write_MDMA_S3_Y_MODIFY
-#define bfin_write_MDMA_D_CONFIG bfin_write_MDMA_D3_CONFIG
-#define bfin_write_MDMA_D_START_ADDR bfin_write_MDMA_D3_START_ADDR
-#define bfin_read_MDMA_D_IRQ_STATUS bfin_read_MDMA_D3_IRQ_STATUS
-#define bfin_write_MDMA_D_IRQ_STATUS bfin_write_MDMA_D3_IRQ_STATUS
-#define bfin_write_MDMA_D_X_COUNT bfin_write_MDMA_D3_X_COUNT
-#define bfin_write_MDMA_D_X_MODIFY bfin_write_MDMA_D3_X_MODIFY
-#define bfin_write_MDMA_D_Y_COUNT bfin_write_MDMA_D3_Y_COUNT
-#define bfin_write_MDMA_D_Y_MODIFY bfin_write_MDMA_D3_Y_MODIFY
-#else
-#define bfin_read_MDMA_S_CONFIG bfin_read_MDMA_S0_CONFIG
-#define bfin_write_MDMA_S_CONFIG bfin_write_MDMA_S0_CONFIG
-#define bfin_write_MDMA_S_START_ADDR bfin_write_MDMA_S0_START_ADDR
-#define bfin_write_MDMA_S_IRQ_STATUS bfin_write_MDMA_S0_IRQ_STATUS
-#define bfin_write_MDMA_S_X_COUNT bfin_write_MDMA_S0_X_COUNT
-#define bfin_write_MDMA_S_X_MODIFY bfin_write_MDMA_S0_X_MODIFY
-#define bfin_write_MDMA_S_Y_COUNT bfin_write_MDMA_S0_Y_COUNT
-#define bfin_write_MDMA_S_Y_MODIFY bfin_write_MDMA_S0_Y_MODIFY
-#define bfin_write_MDMA_D_CONFIG bfin_write_MDMA_D0_CONFIG
-#define bfin_write_MDMA_D_START_ADDR bfin_write_MDMA_D0_START_ADDR
-#define bfin_read_MDMA_D_IRQ_STATUS bfin_read_MDMA_D0_IRQ_STATUS
-#define bfin_write_MDMA_D_IRQ_STATUS bfin_write_MDMA_D0_IRQ_STATUS
-#define bfin_write_MDMA_D_X_COUNT bfin_write_MDMA_D0_X_COUNT
-#define bfin_write_MDMA_D_X_MODIFY bfin_write_MDMA_D0_X_MODIFY
-#define bfin_write_MDMA_D_Y_COUNT bfin_write_MDMA_D0_Y_COUNT
-#define bfin_write_MDMA_D_Y_MODIFY bfin_write_MDMA_D0_Y_MODIFY
-#endif
-
-/**
- * __dma_memcpy - program the MDMA registers
- *
- * Actually program MDMA0 and wait for the transfer to finish. Disable IRQs
- * while programming registers so that everything is fully configured. Wait
- * for DMA to finish with IRQs enabled. If interrupted, the initial DMA_DONE
- * check will make sure we don't clobber any existing transfer.
- */
-static void __dma_memcpy(u32 daddr, s16 dmod, u32 saddr, s16 smod, size_t cnt, u32 conf)
-{
- static DEFINE_SPINLOCK(mdma_lock);
- unsigned long flags;
-
- spin_lock_irqsave(&mdma_lock, flags);
-
- /* Force a sync in case a previous config reset on this channel
- * occurred. This is needed so subsequent writes to DMA registers
- * are not spuriously lost/corrupted. Do it under irq lock and
- * without the anomaly version (because we are atomic already).
- */
- __builtin_bfin_ssync();
-
- if (bfin_read_MDMA_S_CONFIG())
- while (!(bfin_read_MDMA_D_IRQ_STATUS() & DMA_DONE))
- continue;
-
- if (conf & DMA2D) {
- /* For larger bit sizes, we've already divided down cnt so it
- * is no longer a multiple of 64k. So we have to break down
- * the limit here so it is a multiple of the incoming size.
- * There is no limitation here in terms of total size other
- * than the hardware though as the bits lost in the shift are
- * made up by MODIFY (== we can hit the whole address space).
- * X: (2^(16 - 0)) * 1 == (2^(16 - 1)) * 2 == (2^(16 - 2)) * 4
- */
- u32 shift = abs(dmod) >> 1;
- size_t ycnt = cnt >> (16 - shift);
- cnt = 1 << (16 - shift);
- bfin_write_MDMA_D_Y_COUNT(ycnt);
- bfin_write_MDMA_S_Y_COUNT(ycnt);
- bfin_write_MDMA_D_Y_MODIFY(dmod);
- bfin_write_MDMA_S_Y_MODIFY(smod);
- }
-
- bfin_write_MDMA_D_START_ADDR(daddr);
- bfin_write_MDMA_D_X_COUNT(cnt);
- bfin_write_MDMA_D_X_MODIFY(dmod);
- bfin_write_MDMA_D_IRQ_STATUS(DMA_DONE | DMA_ERR);
-
- bfin_write_MDMA_S_START_ADDR(saddr);
- bfin_write_MDMA_S_X_COUNT(cnt);
- bfin_write_MDMA_S_X_MODIFY(smod);
- bfin_write_MDMA_S_IRQ_STATUS(DMA_DONE | DMA_ERR);
-
- bfin_write_MDMA_S_CONFIG(DMAEN | conf);
- if (conf & DMA2D)
- bfin_write_MDMA_D_CONFIG(WNR | DI_EN_Y | DMAEN | conf);
- else
- bfin_write_MDMA_D_CONFIG(WNR | DI_EN_X | DMAEN | conf);
-
- spin_unlock_irqrestore(&mdma_lock, flags);
-
- SSYNC();
-
- while (!(bfin_read_MDMA_D_IRQ_STATUS() & DMA_DONE))
- if (bfin_read_MDMA_S_CONFIG())
- continue;
- else
- return;
-
- bfin_write_MDMA_D_IRQ_STATUS(DMA_DONE | DMA_ERR);
-
- bfin_write_MDMA_S_CONFIG(0);
- bfin_write_MDMA_D_CONFIG(0);
-}
-
-/**
- * _dma_memcpy - translate C memcpy settings into MDMA settings
- *
- * Handle all the high level steps before we touch the MDMA registers. So
- * handle direction, tweaking of sizes, and formatting of addresses.
- */
-static void *_dma_memcpy(void *pdst, const void *psrc, size_t size)
-{
- u32 conf, shift;
- s16 mod;
- unsigned long dst = (unsigned long)pdst;
- unsigned long src = (unsigned long)psrc;
-
- if (size == 0)
- return NULL;
-
- if (dst % 4 == 0 && src % 4 == 0 && size % 4 == 0) {
- conf = WDSIZE_32;
- shift = 2;
- } else if (dst % 2 == 0 && src % 2 == 0 && size % 2 == 0) {
- conf = WDSIZE_16;
- shift = 1;
- } else {
- conf = WDSIZE_8;
- shift = 0;
- }
-
- /* If the two memory regions have a chance of overlapping, make
- * sure the memcpy still works as expected. Do this by having the
- * copy run backwards instead.
- */
- mod = 1 << shift;
- if (src < dst) {
- mod *= -1;
- dst += size + mod;
- src += size + mod;
- }
- size >>= shift;
-
-#ifndef DMA_MMR_SIZE_32
- if (size > 0x10000)
- conf |= DMA2D;
-#endif
-
- __dma_memcpy(dst, mod, src, mod, size, conf);
-
- return pdst;
-}
-
-/**
- * dma_memcpy - DMA memcpy under mutex lock
- *
- * Do not check arguments before starting the DMA memcpy. Break the transfer
- * up into two pieces. The first transfer is in multiples of 64k and the
- * second transfer is the piece smaller than 64k.
- */
-void *dma_memcpy(void *pdst, const void *psrc, size_t size)
-{
- unsigned long dst = (unsigned long)pdst;
- unsigned long src = (unsigned long)psrc;
-
- if (bfin_addr_dcacheable(src))
- blackfin_dcache_flush_range(src, src + size);
-
- if (bfin_addr_dcacheable(dst))
- blackfin_dcache_invalidate_range(dst, dst + size);
-
- return dma_memcpy_nocache(pdst, psrc, size);
-}
-EXPORT_SYMBOL(dma_memcpy);
-
-/**
- * dma_memcpy_nocache - DMA memcpy under mutex lock
- * - No cache flush/invalidate
- *
- * Do not check arguments before starting the DMA memcpy. Break the transfer
- * up into two pieces. The first transfer is in multiples of 64k and the
- * second transfer is the piece smaller than 64k.
- */
-void *dma_memcpy_nocache(void *pdst, const void *psrc, size_t size)
-{
-#ifdef DMA_MMR_SIZE_32
- _dma_memcpy(pdst, psrc, size);
-#else
- size_t bulk, rest;
-
- bulk = size & ~0xffff;
- rest = size - bulk;
- if (bulk)
- _dma_memcpy(pdst, psrc, bulk);
- _dma_memcpy(pdst + bulk, psrc + bulk, rest);
-#endif
- return pdst;
-}
-EXPORT_SYMBOL(dma_memcpy_nocache);
-
-/**
- * safe_dma_memcpy - DMA memcpy w/argument checking
- *
- * Verify arguments are safe before heading to dma_memcpy().
- */
-void *safe_dma_memcpy(void *dst, const void *src, size_t size)
-{
- if (!access_ok(VERIFY_WRITE, dst, size))
- return NULL;
- if (!access_ok(VERIFY_READ, src, size))
- return NULL;
- return dma_memcpy(dst, src, size);
-}
-EXPORT_SYMBOL(safe_dma_memcpy);
-
-static void _dma_out(unsigned long addr, unsigned long buf, unsigned DMA_MMR_SIZE_TYPE len,
- u16 size, u16 dma_size)
-{
- blackfin_dcache_flush_range(buf, buf + len * size);
- __dma_memcpy(addr, 0, buf, size, len, dma_size);
-}
-
-static void _dma_in(unsigned long addr, unsigned long buf, unsigned DMA_MMR_SIZE_TYPE len,
- u16 size, u16 dma_size)
-{
- blackfin_dcache_invalidate_range(buf, buf + len * size);
- __dma_memcpy(buf, size, addr, 0, len, dma_size);
-}
-
-#define MAKE_DMA_IO(io, bwl, isize, dmasize, cnst) \
-void dma_##io##s##bwl(unsigned long addr, cnst void *buf, unsigned DMA_MMR_SIZE_TYPE len) \
-{ \
- _dma_##io(addr, (unsigned long)buf, len, isize, WDSIZE_##dmasize); \
-} \
-EXPORT_SYMBOL(dma_##io##s##bwl)
-MAKE_DMA_IO(out, b, 1, 8, const);
-MAKE_DMA_IO(in, b, 1, 8, );
-MAKE_DMA_IO(out, w, 2, 16, const);
-MAKE_DMA_IO(in, w, 2, 16, );
-MAKE_DMA_IO(out, l, 4, 32, const);
-MAKE_DMA_IO(in, l, 4, 32, );
+++ /dev/null
-/*
- * GPIO Abstraction Layer
- *
- * Copyright 2006-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <linux/delay.h>
-#include <linux/module.h>
-#include <linux/err.h>
-#include <linux/proc_fs.h>
-#include <linux/seq_file.h>
-#include <linux/gpio/driver.h>
-/* FIXME: consumer API required for gpio_set_value() etc, get rid of this */
-#include <linux/gpio.h>
-#include <linux/irq.h>
-#include <asm/gpio.h>
-#include <asm/irq_handler.h>
-#include <asm/portmux.h>
-
-#if ANOMALY_05000311 || ANOMALY_05000323
-enum {
- AWA_data = SYSCR,
- AWA_data_clear = SYSCR,
- AWA_data_set = SYSCR,
- AWA_toggle = SYSCR,
- AWA_maska = BFIN_UART_SCR,
- AWA_maska_clear = BFIN_UART_SCR,
- AWA_maska_set = BFIN_UART_SCR,
- AWA_maska_toggle = BFIN_UART_SCR,
- AWA_maskb = BFIN_UART_GCTL,
- AWA_maskb_clear = BFIN_UART_GCTL,
- AWA_maskb_set = BFIN_UART_GCTL,
- AWA_maskb_toggle = BFIN_UART_GCTL,
- AWA_dir = SPORT1_STAT,
- AWA_polar = SPORT1_STAT,
- AWA_edge = SPORT1_STAT,
- AWA_both = SPORT1_STAT,
-#if ANOMALY_05000311
- AWA_inen = TIMER_ENABLE,
-#elif ANOMALY_05000323
- AWA_inen = DMA1_1_CONFIG,
-#endif
-};
- /* Anomaly Workaround */
-#define AWA_DUMMY_READ(name) bfin_read16(AWA_ ## name)
-#else
-#define AWA_DUMMY_READ(...) do { } while (0)
-#endif
-
-static struct gpio_port_t * const gpio_array[] = {
-#if defined(BF533_FAMILY) || defined(BF538_FAMILY)
- (struct gpio_port_t *) FIO_FLAG_D,
-#elif defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x)
- (struct gpio_port_t *) PORTFIO,
- (struct gpio_port_t *) PORTGIO,
- (struct gpio_port_t *) PORTHIO,
-#elif defined(BF561_FAMILY)
- (struct gpio_port_t *) FIO0_FLAG_D,
- (struct gpio_port_t *) FIO1_FLAG_D,
- (struct gpio_port_t *) FIO2_FLAG_D,
-#else
-# error no gpio arrays defined
-#endif
-};
-
-#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x)
-static unsigned short * const port_fer[] = {
- (unsigned short *) PORTF_FER,
- (unsigned short *) PORTG_FER,
- (unsigned short *) PORTH_FER,
-};
-
-# if !defined(BF537_FAMILY)
-static unsigned short * const port_mux[] = {
- (unsigned short *) PORTF_MUX,
- (unsigned short *) PORTG_MUX,
- (unsigned short *) PORTH_MUX,
-};
-
-static const
-u8 pmux_offset[][16] = {
-# if defined(CONFIG_BF52x)
- { 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 4, 6, 8, 8, 10, 10 }, /* PORTF */
- { 0, 0, 0, 0, 0, 2, 2, 4, 4, 6, 8, 10, 10, 10, 12, 12 }, /* PORTG */
- { 0, 0, 0, 0, 0, 0, 0, 0, 2, 4, 4, 4, 4, 4, 4, 4 }, /* PORTH */
-# elif defined(CONFIG_BF51x)
- { 0, 2, 2, 2, 2, 2, 2, 4, 6, 6, 6, 8, 8, 8, 8, 10 }, /* PORTF */
- { 0, 0, 0, 2, 4, 6, 6, 6, 8, 10, 10, 12, 14, 14, 14, 14 }, /* PORTG */
- { 0, 0, 0, 0, 2, 2, 4, 6, 10, 10, 10, 10, 10, 10, 10, 10 }, /* PORTH */
-# endif
-};
-# endif
-
-#elif defined(BF538_FAMILY)
-static unsigned short * const port_fer[] = {
- (unsigned short *) PORTCIO_FER,
- (unsigned short *) PORTDIO_FER,
- (unsigned short *) PORTEIO_FER,
-};
-#endif
-
-#define RESOURCE_LABEL_SIZE 16
-
-static struct str_ident {
- char name[RESOURCE_LABEL_SIZE];
-} str_ident[MAX_RESOURCES];
-
-#if defined(CONFIG_PM)
-static struct gpio_port_s gpio_bank_saved[GPIO_BANK_NUM];
-# ifdef BF538_FAMILY
-static unsigned short port_fer_saved[3];
-# endif
-#endif
-
-static void gpio_error(unsigned gpio)
-{
- printk(KERN_ERR "bfin-gpio: GPIO %d wasn't requested!\n", gpio);
-}
-
-static void set_label(unsigned short ident, const char *label)
-{
- if (label) {
- strncpy(str_ident[ident].name, label,
- RESOURCE_LABEL_SIZE);
- str_ident[ident].name[RESOURCE_LABEL_SIZE - 1] = 0;
- }
-}
-
-static char *get_label(unsigned short ident)
-{
- return (*str_ident[ident].name ? str_ident[ident].name : "UNKNOWN");
-}
-
-static int cmp_label(unsigned short ident, const char *label)
-{
- if (label == NULL) {
- dump_stack();
- printk(KERN_ERR "Please provide none-null label\n");
- }
-
- if (label)
- return strcmp(str_ident[ident].name, label);
- else
- return -EINVAL;
-}
-
-#define map_entry(m, i) reserved_##m##_map[gpio_bank(i)]
-#define is_reserved(m, i, e) (map_entry(m, i) & gpio_bit(i))
-#define reserve(m, i) (map_entry(m, i) |= gpio_bit(i))
-#define unreserve(m, i) (map_entry(m, i) &= ~gpio_bit(i))
-#define DECLARE_RESERVED_MAP(m, c) static unsigned short reserved_##m##_map[c]
-
-DECLARE_RESERVED_MAP(gpio, GPIO_BANK_NUM);
-DECLARE_RESERVED_MAP(peri, DIV_ROUND_UP(MAX_RESOURCES, GPIO_BANKSIZE));
-DECLARE_RESERVED_MAP(gpio_irq, GPIO_BANK_NUM);
-
-inline int check_gpio(unsigned gpio)
-{
- if (gpio >= MAX_BLACKFIN_GPIOS)
- return -EINVAL;
- return 0;
-}
-
-static void port_setup(unsigned gpio, unsigned short usage)
-{
-#if defined(BF538_FAMILY)
- /*
- * BF538/9 Port C,D and E are special.
- * Inverted PORT_FER polarity on CDE and no PORF_FER on F
- * Regular PORT F GPIOs are handled here, CDE are exclusively
- * managed by GPIOLIB
- */
-
- if (gpio < MAX_BLACKFIN_GPIOS || gpio >= MAX_RESOURCES)
- return;
-
- gpio -= MAX_BLACKFIN_GPIOS;
-
- if (usage == GPIO_USAGE)
- *port_fer[gpio_bank(gpio)] |= gpio_bit(gpio);
- else
- *port_fer[gpio_bank(gpio)] &= ~gpio_bit(gpio);
- SSYNC();
- return;
-#endif
-
- if (check_gpio(gpio))
- return;
-
-#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x)
- if (usage == GPIO_USAGE)
- *port_fer[gpio_bank(gpio)] &= ~gpio_bit(gpio);
- else
- *port_fer[gpio_bank(gpio)] |= gpio_bit(gpio);
- SSYNC();
-#endif
-}
-
-#ifdef BF537_FAMILY
-static const s8 port_mux[] = {
- [GPIO_PF0] = 3,
- [GPIO_PF1] = 3,
- [GPIO_PF2] = 4,
- [GPIO_PF3] = 4,
- [GPIO_PF4] = 5,
- [GPIO_PF5] = 6,
- [GPIO_PF6] = 7,
- [GPIO_PF7] = 8,
- [GPIO_PF8 ... GPIO_PF15] = -1,
- [GPIO_PG0 ... GPIO_PG7] = -1,
- [GPIO_PG8] = 9,
- [GPIO_PG9] = 9,
- [GPIO_PG10] = 10,
- [GPIO_PG11] = 10,
- [GPIO_PG12] = 10,
- [GPIO_PG13] = 11,
- [GPIO_PG14] = 11,
- [GPIO_PG15] = 11,
- [GPIO_PH0 ... GPIO_PH15] = -1,
- [PORT_PJ0 ... PORT_PJ3] = -1,
- [PORT_PJ4] = 1,
- [PORT_PJ5] = 1,
- [PORT_PJ6 ... PORT_PJ9] = -1,
- [PORT_PJ10] = 0,
- [PORT_PJ11] = 0,
-};
-
-static int portmux_group_check(unsigned short per)
-{
- u16 ident = P_IDENT(per);
- u16 function = P_FUNCT2MUX(per);
- s8 offset = port_mux[ident];
- u16 m, pmux, pfunc, mask;
-
- if (offset < 0)
- return 0;
-
- pmux = bfin_read_PORT_MUX();
- for (m = 0; m < ARRAY_SIZE(port_mux); ++m) {
- if (m == ident)
- continue;
- if (port_mux[m] != offset)
- continue;
- if (!is_reserved(peri, m, 1))
- continue;
-
- if (offset == 1)
- mask = 3;
- else
- mask = 1;
-
- pfunc = (pmux >> offset) & mask;
- if (pfunc != (function & mask)) {
- pr_err("pin group conflict! request pin %d func %d conflict with pin %d func %d\n",
- ident, function, m, pfunc);
- return -EINVAL;
- }
- }
-
- return 0;
-}
-
-static void portmux_setup(unsigned short per)
-{
- u16 ident = P_IDENT(per);
- u16 function = P_FUNCT2MUX(per);
- s8 offset = port_mux[ident];
- u16 pmux, mask;
-
- if (offset == -1)
- return;
-
- pmux = bfin_read_PORT_MUX();
- if (offset == 1)
- mask = 3;
- else
- mask = 1;
-
- pmux &= ~(mask << offset);
- pmux |= ((function & mask) << offset);
-
- bfin_write_PORT_MUX(pmux);
-}
-#elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
-static int portmux_group_check(unsigned short per)
-{
- u16 ident = P_IDENT(per);
- u16 function = P_FUNCT2MUX(per);
- u8 offset = pmux_offset[gpio_bank(ident)][gpio_sub_n(ident)];
- u16 pin, gpiopin, pfunc;
-
- for (pin = 0; pin < GPIO_BANKSIZE; ++pin) {
- if (offset != pmux_offset[gpio_bank(ident)][pin])
- continue;
-
- gpiopin = gpio_bank(ident) * GPIO_BANKSIZE + pin;
- if (gpiopin == ident)
- continue;
- if (!is_reserved(peri, gpiopin, 1))
- continue;
-
- pfunc = *port_mux[gpio_bank(ident)];
- pfunc = (pfunc >> offset) & 3;
- if (pfunc != function) {
- pr_err("pin group conflict! request pin %d func %d conflict with pin %d func %d\n",
- ident, function, gpiopin, pfunc);
- return -EINVAL;
- }
- }
-
- return 0;
-}
-
-inline void portmux_setup(unsigned short per)
-{
- u16 ident = P_IDENT(per);
- u16 function = P_FUNCT2MUX(per);
- u8 offset = pmux_offset[gpio_bank(ident)][gpio_sub_n(ident)];
- u16 pmux;
-
- pmux = *port_mux[gpio_bank(ident)];
- if (((pmux >> offset) & 3) == function)
- return;
- pmux &= ~(3 << offset);
- pmux |= (function & 3) << offset;
- *port_mux[gpio_bank(ident)] = pmux;
- SSYNC();
-}
-#else
-# define portmux_setup(...) do { } while (0)
-static int portmux_group_check(unsigned short per)
-{
- return 0;
-}
-#endif
-
-/***********************************************************
-*
-* FUNCTIONS: Blackfin General Purpose Ports Access Functions
-*
-* INPUTS/OUTPUTS:
-* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS
-*
-*
-* DESCRIPTION: These functions abstract direct register access
-* to Blackfin processor General Purpose
-* Ports Regsiters
-*
-* CAUTION: These functions do not belong to the GPIO Driver API
-*************************************************************
-* MODIFICATION HISTORY :
-**************************************************************/
-
-/* Set a specific bit */
-
-#define SET_GPIO(name) \
-void set_gpio_ ## name(unsigned gpio, unsigned short arg) \
-{ \
- unsigned long flags; \
- flags = hard_local_irq_save(); \
- if (arg) \
- gpio_array[gpio_bank(gpio)]->name |= gpio_bit(gpio); \
- else \
- gpio_array[gpio_bank(gpio)]->name &= ~gpio_bit(gpio); \
- AWA_DUMMY_READ(name); \
- hard_local_irq_restore(flags); \
-} \
-EXPORT_SYMBOL(set_gpio_ ## name);
-
-SET_GPIO(dir) /* set_gpio_dir() */
-SET_GPIO(inen) /* set_gpio_inen() */
-SET_GPIO(polar) /* set_gpio_polar() */
-SET_GPIO(edge) /* set_gpio_edge() */
-SET_GPIO(both) /* set_gpio_both() */
-
-
-#define SET_GPIO_SC(name) \
-void set_gpio_ ## name(unsigned gpio, unsigned short arg) \
-{ \
- unsigned long flags; \
- if (ANOMALY_05000311 || ANOMALY_05000323) \
- flags = hard_local_irq_save(); \
- if (arg) \
- gpio_array[gpio_bank(gpio)]->name ## _set = gpio_bit(gpio); \
- else \
- gpio_array[gpio_bank(gpio)]->name ## _clear = gpio_bit(gpio); \
- if (ANOMALY_05000311 || ANOMALY_05000323) { \
- AWA_DUMMY_READ(name); \
- hard_local_irq_restore(flags); \
- } \
-} \
-EXPORT_SYMBOL(set_gpio_ ## name);
-
-SET_GPIO_SC(maska)
-SET_GPIO_SC(maskb)
-SET_GPIO_SC(data)
-
-void set_gpio_toggle(unsigned gpio)
-{
- unsigned long flags;
- if (ANOMALY_05000311 || ANOMALY_05000323)
- flags = hard_local_irq_save();
- gpio_array[gpio_bank(gpio)]->toggle = gpio_bit(gpio);
- if (ANOMALY_05000311 || ANOMALY_05000323) {
- AWA_DUMMY_READ(toggle);
- hard_local_irq_restore(flags);
- }
-}
-EXPORT_SYMBOL(set_gpio_toggle);
-
-
-/*Set current PORT date (16-bit word)*/
-
-#define SET_GPIO_P(name) \
-void set_gpiop_ ## name(unsigned gpio, unsigned short arg) \
-{ \
- unsigned long flags; \
- if (ANOMALY_05000311 || ANOMALY_05000323) \
- flags = hard_local_irq_save(); \
- gpio_array[gpio_bank(gpio)]->name = arg; \
- if (ANOMALY_05000311 || ANOMALY_05000323) { \
- AWA_DUMMY_READ(name); \
- hard_local_irq_restore(flags); \
- } \
-} \
-EXPORT_SYMBOL(set_gpiop_ ## name);
-
-SET_GPIO_P(data)
-SET_GPIO_P(dir)
-SET_GPIO_P(inen)
-SET_GPIO_P(polar)
-SET_GPIO_P(edge)
-SET_GPIO_P(both)
-SET_GPIO_P(maska)
-SET_GPIO_P(maskb)
-
-/* Get a specific bit */
-#define GET_GPIO(name) \
-unsigned short get_gpio_ ## name(unsigned gpio) \
-{ \
- unsigned long flags; \
- unsigned short ret; \
- if (ANOMALY_05000311 || ANOMALY_05000323) \
- flags = hard_local_irq_save(); \
- ret = 0x01 & (gpio_array[gpio_bank(gpio)]->name >> gpio_sub_n(gpio)); \
- if (ANOMALY_05000311 || ANOMALY_05000323) { \
- AWA_DUMMY_READ(name); \
- hard_local_irq_restore(flags); \
- } \
- return ret; \
-} \
-EXPORT_SYMBOL(get_gpio_ ## name);
-
-GET_GPIO(data)
-GET_GPIO(dir)
-GET_GPIO(inen)
-GET_GPIO(polar)
-GET_GPIO(edge)
-GET_GPIO(both)
-GET_GPIO(maska)
-GET_GPIO(maskb)
-
-/*Get current PORT date (16-bit word)*/
-
-#define GET_GPIO_P(name) \
-unsigned short get_gpiop_ ## name(unsigned gpio) \
-{ \
- unsigned long flags; \
- unsigned short ret; \
- if (ANOMALY_05000311 || ANOMALY_05000323) \
- flags = hard_local_irq_save(); \
- ret = (gpio_array[gpio_bank(gpio)]->name); \
- if (ANOMALY_05000311 || ANOMALY_05000323) { \
- AWA_DUMMY_READ(name); \
- hard_local_irq_restore(flags); \
- } \
- return ret; \
-} \
-EXPORT_SYMBOL(get_gpiop_ ## name);
-
-GET_GPIO_P(data)
-GET_GPIO_P(dir)
-GET_GPIO_P(inen)
-GET_GPIO_P(polar)
-GET_GPIO_P(edge)
-GET_GPIO_P(both)
-GET_GPIO_P(maska)
-GET_GPIO_P(maskb)
-
-
-#ifdef CONFIG_PM
-DECLARE_RESERVED_MAP(wakeup, GPIO_BANK_NUM);
-
-static const unsigned int sic_iwr_irqs[] = {
-#if defined(BF533_FAMILY)
- IRQ_PROG_INTB
-#elif defined(BF537_FAMILY)
- IRQ_PF_INTB_WATCH, IRQ_PORTG_INTB, IRQ_PH_INTB_MAC_TX
-#elif defined(BF538_FAMILY)
- IRQ_PORTF_INTB
-#elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
- IRQ_PORTF_INTB, IRQ_PORTG_INTB, IRQ_PORTH_INTB
-#elif defined(BF561_FAMILY)
- IRQ_PROG0_INTB, IRQ_PROG1_INTB, IRQ_PROG2_INTB
-#else
-# error no SIC_IWR defined
-#endif
-};
-
-/***********************************************************
-*
-* FUNCTIONS: Blackfin PM Setup API
-*
-* INPUTS/OUTPUTS:
-* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS
-* type -
-* PM_WAKE_RISING
-* PM_WAKE_FALLING
-* PM_WAKE_HIGH
-* PM_WAKE_LOW
-* PM_WAKE_BOTH_EDGES
-*
-* DESCRIPTION: Blackfin PM Driver API
-*
-* CAUTION:
-*************************************************************
-* MODIFICATION HISTORY :
-**************************************************************/
-int bfin_gpio_pm_wakeup_ctrl(unsigned gpio, unsigned ctrl)
-{
- unsigned long flags;
-
- if (check_gpio(gpio) < 0)
- return -EINVAL;
-
- flags = hard_local_irq_save();
- if (ctrl)
- reserve(wakeup, gpio);
- else
- unreserve(wakeup, gpio);
-
- set_gpio_maskb(gpio, ctrl);
- hard_local_irq_restore(flags);
-
- return 0;
-}
-
-int bfin_gpio_pm_standby_ctrl(unsigned ctrl)
-{
- u16 bank, mask, i;
-
- for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
- mask = map_entry(wakeup, i);
- bank = gpio_bank(i);
-
- if (mask)
- bfin_internal_set_wake(sic_iwr_irqs[bank], ctrl);
- }
- return 0;
-}
-
-void bfin_gpio_pm_hibernate_suspend(void)
-{
- int i, bank;
-
-#ifdef BF538_FAMILY
- for (i = 0; i < ARRAY_SIZE(port_fer_saved); ++i)
- port_fer_saved[i] = *port_fer[i];
-#endif
-
- for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
- bank = gpio_bank(i);
-
-#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x)
- gpio_bank_saved[bank].fer = *port_fer[bank];
-#if defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
- gpio_bank_saved[bank].mux = *port_mux[bank];
-#else
- if (bank == 0)
- gpio_bank_saved[bank].mux = bfin_read_PORT_MUX();
-#endif
-#endif
- gpio_bank_saved[bank].data = gpio_array[bank]->data;
- gpio_bank_saved[bank].inen = gpio_array[bank]->inen;
- gpio_bank_saved[bank].polar = gpio_array[bank]->polar;
- gpio_bank_saved[bank].dir = gpio_array[bank]->dir;
- gpio_bank_saved[bank].edge = gpio_array[bank]->edge;
- gpio_bank_saved[bank].both = gpio_array[bank]->both;
- gpio_bank_saved[bank].maska = gpio_array[bank]->maska;
- }
-
-#ifdef BFIN_SPECIAL_GPIO_BANKS
- bfin_special_gpio_pm_hibernate_suspend();
-#endif
-
- AWA_DUMMY_READ(maska);
-}
-
-void bfin_gpio_pm_hibernate_restore(void)
-{
- int i, bank;
-
-#ifdef BF538_FAMILY
- for (i = 0; i < ARRAY_SIZE(port_fer_saved); ++i)
- *port_fer[i] = port_fer_saved[i];
-#endif
-
- for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
- bank = gpio_bank(i);
-
-#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x)
-#if defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
- *port_mux[bank] = gpio_bank_saved[bank].mux;
-#else
- if (bank == 0)
- bfin_write_PORT_MUX(gpio_bank_saved[bank].mux);
-#endif
- *port_fer[bank] = gpio_bank_saved[bank].fer;
-#endif
- gpio_array[bank]->inen = gpio_bank_saved[bank].inen;
- gpio_array[bank]->data_set = gpio_bank_saved[bank].data
- & gpio_bank_saved[bank].dir;
- gpio_array[bank]->dir = gpio_bank_saved[bank].dir;
- gpio_array[bank]->polar = gpio_bank_saved[bank].polar;
- gpio_array[bank]->edge = gpio_bank_saved[bank].edge;
- gpio_array[bank]->both = gpio_bank_saved[bank].both;
- gpio_array[bank]->maska = gpio_bank_saved[bank].maska;
- }
-
-#ifdef BFIN_SPECIAL_GPIO_BANKS
- bfin_special_gpio_pm_hibernate_restore();
-#endif
-
- AWA_DUMMY_READ(maska);
-}
-
-
-#endif
-
-/***********************************************************
-*
-* FUNCTIONS: Blackfin Peripheral Resource Allocation
-* and PortMux Setup
-*
-* INPUTS/OUTPUTS:
-* per Peripheral Identifier
-* label String
-*
-* DESCRIPTION: Blackfin Peripheral Resource Allocation and Setup API
-*
-* CAUTION:
-*************************************************************
-* MODIFICATION HISTORY :
-**************************************************************/
-
-int peripheral_request(unsigned short per, const char *label)
-{
- unsigned long flags;
- unsigned short ident = P_IDENT(per);
-
- /*
- * Don't cares are pins with only one dedicated function
- */
-
- if (per & P_DONTCARE)
- return 0;
-
- if (!(per & P_DEFINED))
- return -ENODEV;
-
- BUG_ON(ident >= MAX_RESOURCES);
-
- flags = hard_local_irq_save();
-
- /* If a pin can be muxed as either GPIO or peripheral, make
- * sure it is not already a GPIO pin when we request it.
- */
- if (unlikely(!check_gpio(ident) && is_reserved(gpio, ident, 1))) {
- if (system_state == SYSTEM_BOOTING)
- dump_stack();
- printk(KERN_ERR
- "%s: Peripheral %d is already reserved as GPIO by %s !\n",
- __func__, ident, get_label(ident));
- hard_local_irq_restore(flags);
- return -EBUSY;
- }
-
- if (unlikely(is_reserved(peri, ident, 1))) {
-
- /*
- * Pin functions like AMC address strobes my
- * be requested and used by several drivers
- */
-
- if (!(per & P_MAYSHARE)) {
- /*
- * Allow that the identical pin function can
- * be requested from the same driver twice
- */
-
- if (cmp_label(ident, label) == 0)
- goto anyway;
-
- if (system_state == SYSTEM_BOOTING)
- dump_stack();
- printk(KERN_ERR
- "%s: Peripheral %d function %d is already reserved by %s !\n",
- __func__, ident, P_FUNCT2MUX(per), get_label(ident));
- hard_local_irq_restore(flags);
- return -EBUSY;
- }
- }
-
- if (unlikely(portmux_group_check(per))) {
- hard_local_irq_restore(flags);
- return -EBUSY;
- }
- anyway:
- reserve(peri, ident);
-
- portmux_setup(per);
- port_setup(ident, PERIPHERAL_USAGE);
-
- hard_local_irq_restore(flags);
- set_label(ident, label);
-
- return 0;
-}
-EXPORT_SYMBOL(peripheral_request);
-
-int peripheral_request_list(const unsigned short per[], const char *label)
-{
- u16 cnt;
- int ret;
-
- for (cnt = 0; per[cnt] != 0; cnt++) {
-
- ret = peripheral_request(per[cnt], label);
-
- if (ret < 0) {
- for ( ; cnt > 0; cnt--)
- peripheral_free(per[cnt - 1]);
-
- return ret;
- }
- }
-
- return 0;
-}
-EXPORT_SYMBOL(peripheral_request_list);
-
-void peripheral_free(unsigned short per)
-{
- unsigned long flags;
- unsigned short ident = P_IDENT(per);
-
- if (per & P_DONTCARE)
- return;
-
- if (!(per & P_DEFINED))
- return;
-
- flags = hard_local_irq_save();
-
- if (unlikely(!is_reserved(peri, ident, 0))) {
- hard_local_irq_restore(flags);
- return;
- }
-
- if (!(per & P_MAYSHARE))
- port_setup(ident, GPIO_USAGE);
-
- unreserve(peri, ident);
-
- set_label(ident, "free");
-
- hard_local_irq_restore(flags);
-}
-EXPORT_SYMBOL(peripheral_free);
-
-void peripheral_free_list(const unsigned short per[])
-{
- u16 cnt;
- for (cnt = 0; per[cnt] != 0; cnt++)
- peripheral_free(per[cnt]);
-}
-EXPORT_SYMBOL(peripheral_free_list);
-
-/***********************************************************
-*
-* FUNCTIONS: Blackfin GPIO Driver
-*
-* INPUTS/OUTPUTS:
-* gpio PIO Number between 0 and MAX_BLACKFIN_GPIOS
-* label String
-*
-* DESCRIPTION: Blackfin GPIO Driver API
-*
-* CAUTION:
-*************************************************************
-* MODIFICATION HISTORY :
-**************************************************************/
-
-int bfin_gpio_request(unsigned gpio, const char *label)
-{
- unsigned long flags;
-
- if (check_gpio(gpio) < 0)
- return -EINVAL;
-
- flags = hard_local_irq_save();
-
- /*
- * Allow that the identical GPIO can
- * be requested from the same driver twice
- * Do nothing and return -
- */
-
- if (cmp_label(gpio, label) == 0) {
- hard_local_irq_restore(flags);
- return 0;
- }
-
- if (unlikely(is_reserved(gpio, gpio, 1))) {
- if (system_state == SYSTEM_BOOTING)
- dump_stack();
- printk(KERN_ERR "bfin-gpio: GPIO %d is already reserved by %s !\n",
- gpio, get_label(gpio));
- hard_local_irq_restore(flags);
- return -EBUSY;
- }
- if (unlikely(is_reserved(peri, gpio, 1))) {
- if (system_state == SYSTEM_BOOTING)
- dump_stack();
- printk(KERN_ERR
- "bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n",
- gpio, get_label(gpio));
- hard_local_irq_restore(flags);
- return -EBUSY;
- }
- if (unlikely(is_reserved(gpio_irq, gpio, 1))) {
- printk(KERN_NOTICE "bfin-gpio: GPIO %d is already reserved as gpio-irq!"
- " (Documentation/blackfin/bfin-gpio-notes.txt)\n", gpio);
- } else { /* Reset POLAR setting when acquiring a gpio for the first time */
- set_gpio_polar(gpio, 0);
- }
-
- reserve(gpio, gpio);
- set_label(gpio, label);
-
- hard_local_irq_restore(flags);
-
- port_setup(gpio, GPIO_USAGE);
-
- return 0;
-}
-EXPORT_SYMBOL(bfin_gpio_request);
-
-void bfin_gpio_free(unsigned gpio)
-{
- unsigned long flags;
-
- if (check_gpio(gpio) < 0)
- return;
-
- might_sleep();
-
- flags = hard_local_irq_save();
-
- if (unlikely(!is_reserved(gpio, gpio, 0))) {
- if (system_state == SYSTEM_BOOTING)
- dump_stack();
- gpio_error(gpio);
- hard_local_irq_restore(flags);
- return;
- }
-
- unreserve(gpio, gpio);
-
- set_label(gpio, "free");
-
- hard_local_irq_restore(flags);
-}
-EXPORT_SYMBOL(bfin_gpio_free);
-
-#ifdef BFIN_SPECIAL_GPIO_BANKS
-DECLARE_RESERVED_MAP(special_gpio, gpio_bank(MAX_RESOURCES));
-
-int bfin_special_gpio_request(unsigned gpio, const char *label)
-{
- unsigned long flags;
-
- flags = hard_local_irq_save();
-
- /*
- * Allow that the identical GPIO can
- * be requested from the same driver twice
- * Do nothing and return -
- */
-
- if (cmp_label(gpio, label) == 0) {
- hard_local_irq_restore(flags);
- return 0;
- }
-
- if (unlikely(is_reserved(special_gpio, gpio, 1))) {
- hard_local_irq_restore(flags);
- printk(KERN_ERR "bfin-gpio: GPIO %d is already reserved by %s !\n",
- gpio, get_label(gpio));
-
- return -EBUSY;
- }
- if (unlikely(is_reserved(peri, gpio, 1))) {
- hard_local_irq_restore(flags);
- printk(KERN_ERR
- "bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n",
- gpio, get_label(gpio));
-
- return -EBUSY;
- }
-
- reserve(special_gpio, gpio);
- reserve(peri, gpio);
-
- set_label(gpio, label);
- hard_local_irq_restore(flags);
- port_setup(gpio, GPIO_USAGE);
-
- return 0;
-}
-EXPORT_SYMBOL(bfin_special_gpio_request);
-
-void bfin_special_gpio_free(unsigned gpio)
-{
- unsigned long flags;
-
- might_sleep();
-
- flags = hard_local_irq_save();
-
- if (unlikely(!is_reserved(special_gpio, gpio, 0))) {
- gpio_error(gpio);
- hard_local_irq_restore(flags);
- return;
- }
-
- unreserve(special_gpio, gpio);
- unreserve(peri, gpio);
- set_label(gpio, "free");
- hard_local_irq_restore(flags);
-}
-EXPORT_SYMBOL(bfin_special_gpio_free);
-#endif
-
-
-int bfin_gpio_irq_request(unsigned gpio, const char *label)
-{
- unsigned long flags;
-
- if (check_gpio(gpio) < 0)
- return -EINVAL;
-
- flags = hard_local_irq_save();
-
- if (unlikely(is_reserved(peri, gpio, 1))) {
- if (system_state == SYSTEM_BOOTING)
- dump_stack();
- printk(KERN_ERR
- "bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n",
- gpio, get_label(gpio));
- hard_local_irq_restore(flags);
- return -EBUSY;
- }
- if (unlikely(is_reserved(gpio, gpio, 1)))
- printk(KERN_NOTICE "bfin-gpio: GPIO %d is already reserved by %s! "
- "(Documentation/blackfin/bfin-gpio-notes.txt)\n",
- gpio, get_label(gpio));
-
- reserve(gpio_irq, gpio);
- set_label(gpio, label);
-
- hard_local_irq_restore(flags);
-
- port_setup(gpio, GPIO_USAGE);
-
- return 0;
-}
-
-void bfin_gpio_irq_free(unsigned gpio)
-{
- unsigned long flags;
-
- if (check_gpio(gpio) < 0)
- return;
-
- flags = hard_local_irq_save();
-
- if (unlikely(!is_reserved(gpio_irq, gpio, 0))) {
- if (system_state == SYSTEM_BOOTING)
- dump_stack();
- gpio_error(gpio);
- hard_local_irq_restore(flags);
- return;
- }
-
- unreserve(gpio_irq, gpio);
-
- set_label(gpio, "free");
-
- hard_local_irq_restore(flags);
-}
-
-static inline void __bfin_gpio_direction_input(unsigned gpio)
-{
- gpio_array[gpio_bank(gpio)]->dir &= ~gpio_bit(gpio);
- gpio_array[gpio_bank(gpio)]->inen |= gpio_bit(gpio);
-}
-
-int bfin_gpio_direction_input(unsigned gpio)
-{
- unsigned long flags;
-
- if (unlikely(!is_reserved(gpio, gpio, 0))) {
- gpio_error(gpio);
- return -EINVAL;
- }
-
- flags = hard_local_irq_save();
- __bfin_gpio_direction_input(gpio);
- AWA_DUMMY_READ(inen);
- hard_local_irq_restore(flags);
-
- return 0;
-}
-EXPORT_SYMBOL(bfin_gpio_direction_input);
-
-void bfin_gpio_irq_prepare(unsigned gpio)
-{
- port_setup(gpio, GPIO_USAGE);
-}
-
-void bfin_gpio_set_value(unsigned gpio, int arg)
-{
- if (arg)
- gpio_array[gpio_bank(gpio)]->data_set = gpio_bit(gpio);
- else
- gpio_array[gpio_bank(gpio)]->data_clear = gpio_bit(gpio);
-}
-EXPORT_SYMBOL(bfin_gpio_set_value);
-
-int bfin_gpio_direction_output(unsigned gpio, int value)
-{
- unsigned long flags;
-
- if (unlikely(!is_reserved(gpio, gpio, 0))) {
- gpio_error(gpio);
- return -EINVAL;
- }
-
- flags = hard_local_irq_save();
-
- gpio_array[gpio_bank(gpio)]->inen &= ~gpio_bit(gpio);
- gpio_set_value(gpio, value);
- gpio_array[gpio_bank(gpio)]->dir |= gpio_bit(gpio);
-
- AWA_DUMMY_READ(dir);
- hard_local_irq_restore(flags);
-
- return 0;
-}
-EXPORT_SYMBOL(bfin_gpio_direction_output);
-
-int bfin_gpio_get_value(unsigned gpio)
-{
- unsigned long flags;
-
- if (unlikely(get_gpio_edge(gpio))) {
- int ret;
- flags = hard_local_irq_save();
- set_gpio_edge(gpio, 0);
- ret = get_gpio_data(gpio);
- set_gpio_edge(gpio, 1);
- hard_local_irq_restore(flags);
- return ret;
- } else
- return get_gpio_data(gpio);
-}
-EXPORT_SYMBOL(bfin_gpio_get_value);
-
-/* If we are booting from SPI and our board lacks a strong enough pull up,
- * the core can reset and execute the bootrom faster than the resistor can
- * pull the signal logically high. To work around this (common) error in
- * board design, we explicitly set the pin back to GPIO mode, force /CS
- * high, and wait for the electrons to do their thing.
- *
- * This function only makes sense to be called from reset code, but it
- * lives here as we need to force all the GPIO states w/out going through
- * BUG() checks and such.
- */
-void bfin_reset_boot_spi_cs(unsigned short pin)
-{
- unsigned short gpio = P_IDENT(pin);
- port_setup(gpio, GPIO_USAGE);
- gpio_array[gpio_bank(gpio)]->data_set = gpio_bit(gpio);
- AWA_DUMMY_READ(data_set);
- udelay(1);
-}
-
-#if defined(CONFIG_PROC_FS)
-static int gpio_proc_show(struct seq_file *m, void *v)
-{
- int c, irq, gpio;
-
- for (c = 0; c < MAX_RESOURCES; c++) {
- irq = is_reserved(gpio_irq, c, 1);
- gpio = is_reserved(gpio, c, 1);
- if (!check_gpio(c) && (gpio || irq))
- seq_printf(m, "GPIO_%d: \t%s%s \t\tGPIO %s\n", c,
- get_label(c), (gpio && irq) ? " *" : "",
- get_gpio_dir(c) ? "OUTPUT" : "INPUT");
- else if (is_reserved(peri, c, 1))
- seq_printf(m, "GPIO_%d: \t%s \t\tPeripheral\n", c, get_label(c));
- else
- continue;
- }
-
- return 0;
-}
-
-static int gpio_proc_open(struct inode *inode, struct file *file)
-{
- return single_open(file, gpio_proc_show, NULL);
-}
-
-static const struct file_operations gpio_proc_ops = {
- .open = gpio_proc_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = single_release,
-};
-
-static __init int gpio_register_proc(void)
-{
- struct proc_dir_entry *proc_gpio;
-
- proc_gpio = proc_create("gpio", 0, NULL, &gpio_proc_ops);
- return proc_gpio == NULL;
-}
-__initcall(gpio_register_proc);
-#endif
-
-#ifdef CONFIG_GPIOLIB
-static int bfin_gpiolib_direction_input(struct gpio_chip *chip, unsigned gpio)
-{
- return bfin_gpio_direction_input(gpio);
-}
-
-static int bfin_gpiolib_direction_output(struct gpio_chip *chip, unsigned gpio, int level)
-{
- return bfin_gpio_direction_output(gpio, level);
-}
-
-static int bfin_gpiolib_get_value(struct gpio_chip *chip, unsigned gpio)
-{
- return !!bfin_gpio_get_value(gpio);
-}
-
-static void bfin_gpiolib_set_value(struct gpio_chip *chip, unsigned gpio, int value)
-{
- return bfin_gpio_set_value(gpio, value);
-}
-
-static int bfin_gpiolib_gpio_request(struct gpio_chip *chip, unsigned gpio)
-{
- return bfin_gpio_request(gpio, chip->label);
-}
-
-static void bfin_gpiolib_gpio_free(struct gpio_chip *chip, unsigned gpio)
-{
- return bfin_gpio_free(gpio);
-}
-
-static int bfin_gpiolib_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
-{
- return gpio + GPIO_IRQ_BASE;
-}
-
-static struct gpio_chip bfin_chip = {
- .label = "BFIN-GPIO",
- .direction_input = bfin_gpiolib_direction_input,
- .get = bfin_gpiolib_get_value,
- .direction_output = bfin_gpiolib_direction_output,
- .set = bfin_gpiolib_set_value,
- .request = bfin_gpiolib_gpio_request,
- .free = bfin_gpiolib_gpio_free,
- .to_irq = bfin_gpiolib_gpio_to_irq,
- .base = 0,
- .ngpio = MAX_BLACKFIN_GPIOS,
-};
-
-static int __init bfin_gpiolib_setup(void)
-{
- return gpiochip_add_data(&bfin_chip, NULL);
-}
-arch_initcall(bfin_gpiolib_setup);
-#endif
+++ /dev/null
-/*
- * arch/blackfin/kernel/bfin_ksyms.c - exports for random symbols
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-#include <linux/uaccess.h>
-
-#include <asm/cacheflush.h>
-#include <asm/io.h>
-#include <asm/irq_handler.h>
-
-/* Allow people to have their own Blackfin exception handler in a module */
-EXPORT_SYMBOL(bfin_return_from_exception);
-
-/* All the Blackfin cache functions: mach-common/cache.S */
-EXPORT_SYMBOL(blackfin_dcache_invalidate_range);
-EXPORT_SYMBOL(blackfin_icache_flush_range);
-EXPORT_SYMBOL(blackfin_dcache_flush_range);
-EXPORT_SYMBOL(blackfin_dflush_page);
-
-/* The following are special because they're not called
- * explicitly (the C compiler generates them). Fortunately,
- * their interface isn't gonna change any time soon now, so
- * it's OK to leave it out of version control.
- */
-EXPORT_SYMBOL(memcpy);
-EXPORT_SYMBOL(memset);
-EXPORT_SYMBOL(memcmp);
-EXPORT_SYMBOL(memmove);
-EXPORT_SYMBOL(memchr);
-
-/*
- * Because string functions are both inline and exported functions and
- * folder arch/blackfin/lib is configured as a library path in Makefile,
- * symbols exported in folder lib is not linked into built-in.o but
- * inlined only. In order to export string symbols to kernel module
- * properly, they should be exported here.
- */
-EXPORT_SYMBOL(strcpy);
-EXPORT_SYMBOL(strncpy);
-EXPORT_SYMBOL(strcmp);
-EXPORT_SYMBOL(strncmp);
-
-/*
- * libgcc functions - functions that are used internally by the
- * compiler... (prototypes are not correct though, but that
- * doesn't really matter since they're not versioned).
- */
-extern void __ashldi3(void);
-extern void __ashrdi3(void);
-extern void __smulsi3_highpart(void);
-extern void __umulsi3_highpart(void);
-extern void __divsi3(void);
-extern void __lshrdi3(void);
-extern void __modsi3(void);
-extern void __muldi3(void);
-extern void __udivsi3(void);
-extern void __umodsi3(void);
-EXPORT_SYMBOL(__ashldi3);
-EXPORT_SYMBOL(__ashrdi3);
-EXPORT_SYMBOL(__umulsi3_highpart);
-EXPORT_SYMBOL(__smulsi3_highpart);
-EXPORT_SYMBOL(__divsi3);
-EXPORT_SYMBOL(__lshrdi3);
-EXPORT_SYMBOL(__modsi3);
-EXPORT_SYMBOL(__muldi3);
-EXPORT_SYMBOL(__udivsi3);
-EXPORT_SYMBOL(__umodsi3);
-
-/* Input/output symbols: lib/{in,out}s.S */
-EXPORT_SYMBOL(outsb);
-EXPORT_SYMBOL(insb);
-EXPORT_SYMBOL(outsw);
-EXPORT_SYMBOL(outsw_8);
-EXPORT_SYMBOL(insw);
-EXPORT_SYMBOL(insw_8);
-EXPORT_SYMBOL(outsl);
-EXPORT_SYMBOL(insl);
-EXPORT_SYMBOL(insl_16);
-
-#ifdef CONFIG_SMP
-EXPORT_SYMBOL(__raw_atomic_add_asm);
-EXPORT_SYMBOL(__raw_atomic_xadd_asm);
-EXPORT_SYMBOL(__raw_atomic_and_asm);
-EXPORT_SYMBOL(__raw_atomic_or_asm);
-EXPORT_SYMBOL(__raw_atomic_xor_asm);
-EXPORT_SYMBOL(__raw_atomic_test_asm);
-
-EXPORT_SYMBOL(__raw_xchg_1_asm);
-EXPORT_SYMBOL(__raw_xchg_2_asm);
-EXPORT_SYMBOL(__raw_xchg_4_asm);
-EXPORT_SYMBOL(__raw_cmpxchg_1_asm);
-EXPORT_SYMBOL(__raw_cmpxchg_2_asm);
-EXPORT_SYMBOL(__raw_cmpxchg_4_asm);
-EXPORT_SYMBOL(__raw_spin_is_locked_asm);
-EXPORT_SYMBOL(__raw_spin_lock_asm);
-EXPORT_SYMBOL(__raw_spin_trylock_asm);
-EXPORT_SYMBOL(__raw_spin_unlock_asm);
-EXPORT_SYMBOL(__raw_read_lock_asm);
-EXPORT_SYMBOL(__raw_read_trylock_asm);
-EXPORT_SYMBOL(__raw_read_unlock_asm);
-EXPORT_SYMBOL(__raw_write_lock_asm);
-EXPORT_SYMBOL(__raw_write_trylock_asm);
-EXPORT_SYMBOL(__raw_write_unlock_asm);
-EXPORT_SYMBOL(__raw_bit_set_asm);
-EXPORT_SYMBOL(__raw_bit_clear_asm);
-EXPORT_SYMBOL(__raw_bit_toggle_asm);
-EXPORT_SYMBOL(__raw_bit_test_asm);
-EXPORT_SYMBOL(__raw_bit_test_set_asm);
-EXPORT_SYMBOL(__raw_bit_test_clear_asm);
-EXPORT_SYMBOL(__raw_bit_test_toggle_asm);
-EXPORT_SYMBOL(__raw_uncached_fetch_asm);
-#ifdef __ARCH_SYNC_CORE_DCACHE
-EXPORT_SYMBOL(__raw_smp_mark_barrier_asm);
-EXPORT_SYMBOL(__raw_smp_check_barrier_asm);
-#endif
-#endif
-
-#ifdef CONFIG_FUNCTION_TRACER
-extern void _mcount(void);
-EXPORT_SYMBOL(_mcount);
-#endif
+++ /dev/null
-#
-# arch/blackfin/kernel/cplb-nompu/Makefile
-#
-
-obj-y := cplbinit.o cplbmgr.o
-
-CFLAGS_cplbmgr.o := -ffixed-I0 -ffixed-I1 -ffixed-I2 -ffixed-I3 \
- -ffixed-L0 -ffixed-L1 -ffixed-L2 -ffixed-L3 \
- -ffixed-M0 -ffixed-M1 -ffixed-M2 -ffixed-M3 \
- -ffixed-B0 -ffixed-B1 -ffixed-B2 -ffixed-B3
+++ /dev/null
-/*
- * Blackfin CPLB initialization
- *
- * Copyright 2008-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-
-#include <asm/blackfin.h>
-#include <asm/cplb.h>
-#include <asm/cplbinit.h>
-#include <asm/mem_map.h>
-
-struct cplb_entry icplb_tbl[NR_CPUS][MAX_CPLBS];
-struct cplb_entry dcplb_tbl[NR_CPUS][MAX_CPLBS];
-
-int first_switched_icplb, first_switched_dcplb;
-int first_mask_dcplb;
-
-void __init generate_cplb_tables_cpu(unsigned int cpu)
-{
- int i_d, i_i;
- unsigned long addr;
- unsigned long d_data, i_data;
- unsigned long d_cache = 0, i_cache = 0;
-
- printk(KERN_INFO "MPU: setting up cplb tables with memory protection\n");
-
-#ifdef CONFIG_BFIN_EXTMEM_ICACHEABLE
- i_cache = CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND;
-#endif
-
-#ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE
- d_cache = CPLB_L1_CHBL;
-#ifdef CONFIG_BFIN_EXTMEM_WRITETHROUGH
- d_cache |= CPLB_L1_AOW | CPLB_WT;
-#endif
-#endif
-
- i_d = i_i = 0;
-
- /* Set up the zero page. */
- dcplb_tbl[cpu][i_d].addr = 0;
- dcplb_tbl[cpu][i_d++].data = SDRAM_OOPS | PAGE_SIZE_1KB;
-
- icplb_tbl[cpu][i_i].addr = 0;
- icplb_tbl[cpu][i_i++].data = CPLB_VALID | i_cache | CPLB_USER_RD | PAGE_SIZE_1KB;
-
- /* Cover kernel memory with 4M pages. */
- addr = 0;
- d_data = d_cache | CPLB_SUPV_WR | CPLB_VALID | PAGE_SIZE_4MB | CPLB_DIRTY;
- i_data = i_cache | CPLB_VALID | CPLB_PORTPRIO | PAGE_SIZE_4MB;
-
- for (; addr < memory_start; addr += 4 * 1024 * 1024) {
- dcplb_tbl[cpu][i_d].addr = addr;
- dcplb_tbl[cpu][i_d++].data = d_data;
- icplb_tbl[cpu][i_i].addr = addr;
- icplb_tbl[cpu][i_i++].data = i_data | (addr == 0 ? CPLB_USER_RD : 0);
- }
-
-#ifdef CONFIG_ROMKERNEL
- /* Cover kernel XIP flash area */
- addr = CONFIG_ROM_BASE & ~(4 * 1024 * 1024 - 1);
- dcplb_tbl[cpu][i_d].addr = addr;
- dcplb_tbl[cpu][i_d++].data = d_data | CPLB_USER_RD;
- icplb_tbl[cpu][i_i].addr = addr;
- icplb_tbl[cpu][i_i++].data = i_data | CPLB_USER_RD;
-#endif
-
- /* Cover L1 memory. One 4M area for code and data each is enough. */
-#if L1_DATA_A_LENGTH > 0 || L1_DATA_B_LENGTH > 0
- dcplb_tbl[cpu][i_d].addr = get_l1_data_a_start_cpu(cpu);
- dcplb_tbl[cpu][i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB;
-#endif
-#if L1_CODE_LENGTH > 0
- icplb_tbl[cpu][i_i].addr = get_l1_code_start_cpu(cpu);
- icplb_tbl[cpu][i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB;
-#endif
-
- /* Cover L2 memory */
-#if L2_LENGTH > 0
- dcplb_tbl[cpu][i_d].addr = L2_START;
- dcplb_tbl[cpu][i_d++].data = L2_DMEMORY;
- icplb_tbl[cpu][i_i].addr = L2_START;
- icplb_tbl[cpu][i_i++].data = L2_IMEMORY;
-#endif
-
- first_mask_dcplb = i_d;
- first_switched_dcplb = i_d + (1 << page_mask_order);
- first_switched_icplb = i_i;
-
- while (i_d < MAX_CPLBS)
- dcplb_tbl[cpu][i_d++].data = 0;
- while (i_i < MAX_CPLBS)
- icplb_tbl[cpu][i_i++].data = 0;
-}
-
-void __init generate_cplb_tables_all(void)
-{
-}
+++ /dev/null
-/*
- * Blackfin CPLB exception handling for when MPU in on
- *
- * Copyright 2008-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-#include <linux/mm.h>
-
-#include <asm/blackfin.h>
-#include <asm/cacheflush.h>
-#include <asm/cplb.h>
-#include <asm/cplbinit.h>
-#include <asm/mmu_context.h>
-
-/*
- * WARNING
- *
- * This file is compiled with certain -ffixed-reg options. We have to
- * make sure not to call any functions here that could clobber these
- * registers.
- */
-
-int page_mask_nelts;
-int page_mask_order;
-unsigned long *current_rwx_mask[NR_CPUS];
-
-int nr_dcplb_miss[NR_CPUS], nr_icplb_miss[NR_CPUS];
-int nr_icplb_supv_miss[NR_CPUS], nr_dcplb_prot[NR_CPUS];
-int nr_cplb_flush[NR_CPUS];
-
-#ifdef CONFIG_EXCPT_IRQ_SYSC_L1
-#define MGR_ATTR __attribute__((l1_text))
-#else
-#define MGR_ATTR
-#endif
-
-/*
- * Given the contents of the status register, return the index of the
- * CPLB that caused the fault.
- */
-static inline int faulting_cplb_index(int status)
-{
- int signbits = __builtin_bfin_norm_fr1x32(status & 0xFFFF);
- return 30 - signbits;
-}
-
-/*
- * Given the contents of the status register and the DCPLB_DATA contents,
- * return true if a write access should be permitted.
- */
-static inline int write_permitted(int status, unsigned long data)
-{
- if (status & FAULT_USERSUPV)
- return !!(data & CPLB_SUPV_WR);
- else
- return !!(data & CPLB_USER_WR);
-}
-
-/* Counters to implement round-robin replacement. */
-static int icplb_rr_index[NR_CPUS], dcplb_rr_index[NR_CPUS];
-
-/*
- * Find an ICPLB entry to be evicted and return its index.
- */
-MGR_ATTR static int evict_one_icplb(unsigned int cpu)
-{
- int i;
- for (i = first_switched_icplb; i < MAX_CPLBS; i++)
- if ((icplb_tbl[cpu][i].data & CPLB_VALID) == 0)
- return i;
- i = first_switched_icplb + icplb_rr_index[cpu];
- if (i >= MAX_CPLBS) {
- i -= MAX_CPLBS - first_switched_icplb;
- icplb_rr_index[cpu] -= MAX_CPLBS - first_switched_icplb;
- }
- icplb_rr_index[cpu]++;
- return i;
-}
-
-MGR_ATTR static int evict_one_dcplb(unsigned int cpu)
-{
- int i;
- for (i = first_switched_dcplb; i < MAX_CPLBS; i++)
- if ((dcplb_tbl[cpu][i].data & CPLB_VALID) == 0)
- return i;
- i = first_switched_dcplb + dcplb_rr_index[cpu];
- if (i >= MAX_CPLBS) {
- i -= MAX_CPLBS - first_switched_dcplb;
- dcplb_rr_index[cpu] -= MAX_CPLBS - first_switched_dcplb;
- }
- dcplb_rr_index[cpu]++;
- return i;
-}
-
-MGR_ATTR static noinline int dcplb_miss(unsigned int cpu)
-{
- unsigned long addr = bfin_read_DCPLB_FAULT_ADDR();
- int status = bfin_read_DCPLB_STATUS();
- unsigned long *mask;
- int idx;
- unsigned long d_data;
-
- nr_dcplb_miss[cpu]++;
-
- d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB;
-#ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE
- if (bfin_addr_dcacheable(addr)) {
- d_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND;
-# ifdef CONFIG_BFIN_EXTMEM_WRITETHROUGH
- d_data |= CPLB_L1_AOW | CPLB_WT;
-# endif
- }
-#endif
-
- if (L2_LENGTH && addr >= L2_START && addr < L2_START + L2_LENGTH) {
- addr = L2_START;
- d_data = L2_DMEMORY;
- } else if (addr >= physical_mem_end) {
- if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) {
-#if defined(CONFIG_ROMFS_ON_MTD) && defined(CONFIG_MTD_ROM)
- mask = current_rwx_mask[cpu];
- if (mask) {
- int page = (addr - (ASYNC_BANK0_BASE - _ramend)) >> PAGE_SHIFT;
- int idx = page >> 5;
- int bit = 1 << (page & 31);
-
- if (mask[idx] & bit)
- d_data |= CPLB_USER_RD;
- }
-#endif
- } else if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH
- && (status & (FAULT_RW | FAULT_USERSUPV)) == FAULT_USERSUPV) {
- addr &= ~(1 * 1024 * 1024 - 1);
- d_data &= ~PAGE_SIZE_4KB;
- d_data |= PAGE_SIZE_1MB;
- } else
- return CPLB_PROT_VIOL;
- } else if (addr >= _ramend) {
- d_data |= CPLB_USER_RD | CPLB_USER_WR;
- if (reserved_mem_dcache_on)
- d_data |= CPLB_L1_CHBL;
- } else {
- mask = current_rwx_mask[cpu];
- if (mask) {
- int page = addr >> PAGE_SHIFT;
- int idx = page >> 5;
- int bit = 1 << (page & 31);
-
- if (mask[idx] & bit)
- d_data |= CPLB_USER_RD;
-
- mask += page_mask_nelts;
- if (mask[idx] & bit)
- d_data |= CPLB_USER_WR;
- }
- }
- idx = evict_one_dcplb(cpu);
-
- addr &= PAGE_MASK;
- dcplb_tbl[cpu][idx].addr = addr;
- dcplb_tbl[cpu][idx].data = d_data;
-
- _disable_dcplb();
- bfin_write32(DCPLB_DATA0 + idx * 4, d_data);
- bfin_write32(DCPLB_ADDR0 + idx * 4, addr);
- _enable_dcplb();
-
- return 0;
-}
-
-MGR_ATTR static noinline int icplb_miss(unsigned int cpu)
-{
- unsigned long addr = bfin_read_ICPLB_FAULT_ADDR();
- int status = bfin_read_ICPLB_STATUS();
- int idx;
- unsigned long i_data;
-
- nr_icplb_miss[cpu]++;
-
- /* If inside the uncached DMA region, fault. */
- if (addr >= _ramend - DMA_UNCACHED_REGION && addr < _ramend)
- return CPLB_PROT_VIOL;
-
- if (status & FAULT_USERSUPV)
- nr_icplb_supv_miss[cpu]++;
-
- /*
- * First, try to find a CPLB that matches this address. If we
- * find one, then the fact that we're in the miss handler means
- * that the instruction crosses a page boundary.
- */
- for (idx = first_switched_icplb; idx < MAX_CPLBS; idx++) {
- if (icplb_tbl[cpu][idx].data & CPLB_VALID) {
- unsigned long this_addr = icplb_tbl[cpu][idx].addr;
- if (this_addr <= addr && this_addr + PAGE_SIZE > addr) {
- addr += PAGE_SIZE;
- break;
- }
- }
- }
-
- i_data = CPLB_VALID | CPLB_PORTPRIO | PAGE_SIZE_4KB;
-
-#ifdef CONFIG_BFIN_EXTMEM_ICACHEABLE
- /*
- * Normal RAM, and possibly the reserved memory area, are
- * cacheable.
- */
- if (addr < _ramend ||
- (addr < physical_mem_end && reserved_mem_icache_on))
- i_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND;
-#endif
-
- if (L2_LENGTH && addr >= L2_START && addr < L2_START + L2_LENGTH) {
- addr = L2_START;
- i_data = L2_IMEMORY;
- } else if (addr >= physical_mem_end) {
- if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) {
- if (!(status & FAULT_USERSUPV)) {
- unsigned long *mask = current_rwx_mask[cpu];
-
- if (mask) {
- int page = (addr - (ASYNC_BANK0_BASE - _ramend)) >> PAGE_SHIFT;
- int idx = page >> 5;
- int bit = 1 << (page & 31);
-
- mask += 2 * page_mask_nelts;
- if (mask[idx] & bit)
- i_data |= CPLB_USER_RD;
- }
- }
- } else if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH
- && (status & FAULT_USERSUPV)) {
- addr &= ~(1 * 1024 * 1024 - 1);
- i_data &= ~PAGE_SIZE_4KB;
- i_data |= PAGE_SIZE_1MB;
- } else
- return CPLB_PROT_VIOL;
- } else if (addr >= _ramend) {
- i_data |= CPLB_USER_RD;
- if (reserved_mem_icache_on)
- i_data |= CPLB_L1_CHBL;
- } else {
- /*
- * Two cases to distinguish - a supervisor access must
- * necessarily be for a module page; we grant it
- * unconditionally (could do better here in the future).
- * Otherwise, check the x bitmap of the current process.
- */
- if (!(status & FAULT_USERSUPV)) {
- unsigned long *mask = current_rwx_mask[cpu];
-
- if (mask) {
- int page = addr >> PAGE_SHIFT;
- int idx = page >> 5;
- int bit = 1 << (page & 31);
-
- mask += 2 * page_mask_nelts;
- if (mask[idx] & bit)
- i_data |= CPLB_USER_RD;
- }
- }
- }
- idx = evict_one_icplb(cpu);
- addr &= PAGE_MASK;
- icplb_tbl[cpu][idx].addr = addr;
- icplb_tbl[cpu][idx].data = i_data;
-
- _disable_icplb();
- bfin_write32(ICPLB_DATA0 + idx * 4, i_data);
- bfin_write32(ICPLB_ADDR0 + idx * 4, addr);
- _enable_icplb();
-
- return 0;
-}
-
-MGR_ATTR static noinline int dcplb_protection_fault(unsigned int cpu)
-{
- int status = bfin_read_DCPLB_STATUS();
-
- nr_dcplb_prot[cpu]++;
-
- if (status & FAULT_RW) {
- int idx = faulting_cplb_index(status);
- unsigned long data = dcplb_tbl[cpu][idx].data;
- if (!(data & CPLB_WT) && !(data & CPLB_DIRTY) &&
- write_permitted(status, data)) {
- data |= CPLB_DIRTY;
- dcplb_tbl[cpu][idx].data = data;
- bfin_write32(DCPLB_DATA0 + idx * 4, data);
- return 0;
- }
- }
- return CPLB_PROT_VIOL;
-}
-
-MGR_ATTR int cplb_hdr(int seqstat, struct pt_regs *regs)
-{
- int cause = seqstat & 0x3f;
- unsigned int cpu = raw_smp_processor_id();
- switch (cause) {
- case 0x23:
- return dcplb_protection_fault(cpu);
- case 0x2C:
- return icplb_miss(cpu);
- case 0x26:
- return dcplb_miss(cpu);
- default:
- return 1;
- }
-}
-
-void flush_switched_cplbs(unsigned int cpu)
-{
- int i;
- unsigned long flags;
-
- nr_cplb_flush[cpu]++;
-
- flags = hard_local_irq_save();
- _disable_icplb();
- for (i = first_switched_icplb; i < MAX_CPLBS; i++) {
- icplb_tbl[cpu][i].data = 0;
- bfin_write32(ICPLB_DATA0 + i * 4, 0);
- }
- _enable_icplb();
-
- _disable_dcplb();
- for (i = first_switched_dcplb; i < MAX_CPLBS; i++) {
- dcplb_tbl[cpu][i].data = 0;
- bfin_write32(DCPLB_DATA0 + i * 4, 0);
- }
- _enable_dcplb();
- hard_local_irq_restore(flags);
-
-}
-
-void set_mask_dcplbs(unsigned long *masks, unsigned int cpu)
-{
- int i;
- unsigned long addr = (unsigned long)masks;
- unsigned long d_data;
- unsigned long flags;
-
- if (!masks) {
- current_rwx_mask[cpu] = masks;
- return;
- }
-
- flags = hard_local_irq_save();
- current_rwx_mask[cpu] = masks;
-
- if (L2_LENGTH && addr >= L2_START && addr < L2_START + L2_LENGTH) {
- addr = L2_START;
- d_data = L2_DMEMORY;
- } else {
- d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB;
-#ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE
- d_data |= CPLB_L1_CHBL;
-# ifdef CONFIG_BFIN_EXTMEM_WRITETHROUGH
- d_data |= CPLB_L1_AOW | CPLB_WT;
-# endif
-#endif
- }
-
- _disable_dcplb();
- for (i = first_mask_dcplb; i < first_switched_dcplb; i++) {
- dcplb_tbl[cpu][i].addr = addr;
- dcplb_tbl[cpu][i].data = d_data;
- bfin_write32(DCPLB_DATA0 + i * 4, d_data);
- bfin_write32(DCPLB_ADDR0 + i * 4, addr);
- addr += PAGE_SIZE;
- }
- _enable_dcplb();
- hard_local_irq_restore(flags);
-}
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0
-#
-# arch/blackfin/kernel/cplb-nompu/Makefile
-#
-
-obj-y := cplbinit.o cplbmgr.o
-
-CFLAGS_cplbmgr.o := -ffixed-I0 -ffixed-I1 -ffixed-I2 -ffixed-I3 \
- -ffixed-L0 -ffixed-L1 -ffixed-L2 -ffixed-L3 \
- -ffixed-M0 -ffixed-M1 -ffixed-M2 -ffixed-M3 \
- -ffixed-B0 -ffixed-B1 -ffixed-B2 -ffixed-B3
+++ /dev/null
-/*
- * Blackfin CPLB initialization
- *
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-
-#include <asm/blackfin.h>
-#include <asm/cacheflush.h>
-#include <asm/cplb.h>
-#include <asm/cplbinit.h>
-#include <asm/mem_map.h>
-
-struct cplb_entry icplb_tbl[NR_CPUS][MAX_CPLBS] PDT_ATTR;
-struct cplb_entry dcplb_tbl[NR_CPUS][MAX_CPLBS] PDT_ATTR;
-
-int first_switched_icplb PDT_ATTR;
-int first_switched_dcplb PDT_ATTR;
-
-struct cplb_boundary dcplb_bounds[9] PDT_ATTR;
-struct cplb_boundary icplb_bounds[9] PDT_ATTR;
-
-int icplb_nr_bounds PDT_ATTR;
-int dcplb_nr_bounds PDT_ATTR;
-
-void __init generate_cplb_tables_cpu(unsigned int cpu)
-{
- int i_d, i_i;
- unsigned long addr;
- unsigned long cplb_pageflags, cplb_pagesize;
-
- struct cplb_entry *d_tbl = dcplb_tbl[cpu];
- struct cplb_entry *i_tbl = icplb_tbl[cpu];
-
- printk(KERN_INFO "NOMPU: setting up cplb tables\n");
-
- i_d = i_i = 0;
-
-#ifdef CONFIG_DEBUG_HUNT_FOR_ZERO
- /* Set up the zero page. */
- d_tbl[i_d].addr = 0;
- d_tbl[i_d++].data = SDRAM_OOPS | PAGE_SIZE_1KB;
- i_tbl[i_i].addr = 0;
- i_tbl[i_i++].data = SDRAM_OOPS | PAGE_SIZE_1KB;
-#endif
-
- /* Cover kernel memory with 4M pages. */
- addr = 0;
-
-#ifdef PAGE_SIZE_16MB
- cplb_pageflags = PAGE_SIZE_16MB;
- cplb_pagesize = SIZE_16M;
-#else
- cplb_pageflags = PAGE_SIZE_4MB;
- cplb_pagesize = SIZE_4M;
-#endif
-
-
- for (; addr < memory_start; addr += cplb_pagesize) {
- d_tbl[i_d].addr = addr;
- d_tbl[i_d++].data = SDRAM_DGENERIC | cplb_pageflags;
- i_tbl[i_i].addr = addr;
- i_tbl[i_i++].data = SDRAM_IGENERIC | cplb_pageflags;
- }
-
-#ifdef CONFIG_ROMKERNEL
- /* Cover kernel XIP flash area */
-#ifdef CONFIG_BF60x
- addr = CONFIG_ROM_BASE & ~(16 * 1024 * 1024 - 1);
- d_tbl[i_d].addr = addr;
- d_tbl[i_d++].data = SDRAM_DGENERIC | PAGE_SIZE_16MB;
- i_tbl[i_i].addr = addr;
- i_tbl[i_i++].data = SDRAM_IGENERIC | PAGE_SIZE_16MB;
-#else
- addr = CONFIG_ROM_BASE & ~(4 * 1024 * 1024 - 1);
- d_tbl[i_d].addr = addr;
- d_tbl[i_d++].data = SDRAM_DGENERIC | PAGE_SIZE_4MB;
- i_tbl[i_i].addr = addr;
- i_tbl[i_i++].data = SDRAM_IGENERIC | PAGE_SIZE_4MB;
-#endif
-#endif
-
- /* Cover L1 memory. One 4M area for code and data each is enough. */
- if (cpu == 0) {
- if (L1_DATA_A_LENGTH || L1_DATA_B_LENGTH) {
- d_tbl[i_d].addr = L1_DATA_A_START;
- d_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB;
- }
- i_tbl[i_i].addr = L1_CODE_START;
- i_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB;
- }
-#ifdef CONFIG_SMP
- else {
- if (L1_DATA_A_LENGTH || L1_DATA_B_LENGTH) {
- d_tbl[i_d].addr = COREB_L1_DATA_A_START;
- d_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB;
- }
- i_tbl[i_i].addr = COREB_L1_CODE_START;
- i_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB;
- }
-#endif
- first_switched_dcplb = i_d;
- first_switched_icplb = i_i;
-
- BUG_ON(first_switched_dcplb > MAX_CPLBS);
- BUG_ON(first_switched_icplb > MAX_CPLBS);
-
- while (i_d < MAX_CPLBS)
- d_tbl[i_d++].data = 0;
- while (i_i < MAX_CPLBS)
- i_tbl[i_i++].data = 0;
-}
-
-void __init generate_cplb_tables_all(void)
-{
- unsigned long uncached_end;
- int i_d, i_i;
-
- i_d = 0;
- /* Normal RAM, including MTD FS. */
-#ifdef CONFIG_MTD_UCLINUX
- uncached_end = memory_mtd_start + mtd_size;
-#else
- uncached_end = memory_end;
-#endif
- /*
- * if DMA uncached is less than 1MB, mark the 1MB chunk as uncached
- * so that we don't have to use 4kB pages and cause CPLB thrashing
- */
- if ((DMA_UNCACHED_REGION >= 1 * 1024 * 1024) || !DMA_UNCACHED_REGION ||
- ((_ramend - uncached_end) >= 1 * 1024 * 1024))
- dcplb_bounds[i_d].eaddr = uncached_end;
- else
- dcplb_bounds[i_d].eaddr = uncached_end & ~(1 * 1024 * 1024 - 1);
- dcplb_bounds[i_d++].data = SDRAM_DGENERIC;
- /* DMA uncached region. */
- if (DMA_UNCACHED_REGION) {
- dcplb_bounds[i_d].eaddr = _ramend;
- dcplb_bounds[i_d++].data = SDRAM_DNON_CHBL;
- }
- if (_ramend != physical_mem_end) {
- /* Reserved memory. */
- dcplb_bounds[i_d].eaddr = physical_mem_end;
- dcplb_bounds[i_d++].data = (reserved_mem_dcache_on ?
- SDRAM_DGENERIC : SDRAM_DNON_CHBL);
- }
- /* Addressing hole up to the async bank. */
- dcplb_bounds[i_d].eaddr = ASYNC_BANK0_BASE;
- dcplb_bounds[i_d++].data = 0;
- /* ASYNC banks. */
- dcplb_bounds[i_d].eaddr = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE;
- dcplb_bounds[i_d++].data = SDRAM_EBIU;
- /* Addressing hole up to BootROM. */
- dcplb_bounds[i_d].eaddr = BOOT_ROM_START;
- dcplb_bounds[i_d++].data = 0;
- /* BootROM -- largest one should be less than 1 meg. */
- dcplb_bounds[i_d].eaddr = BOOT_ROM_START + BOOT_ROM_LENGTH;
- dcplb_bounds[i_d++].data = SDRAM_DGENERIC;
- if (L2_LENGTH) {
- /* Addressing hole up to L2 SRAM. */
- dcplb_bounds[i_d].eaddr = L2_START;
- dcplb_bounds[i_d++].data = 0;
- /* L2 SRAM. */
- dcplb_bounds[i_d].eaddr = L2_START + L2_LENGTH;
- dcplb_bounds[i_d++].data = L2_DMEMORY;
- }
- dcplb_nr_bounds = i_d;
- BUG_ON(dcplb_nr_bounds > ARRAY_SIZE(dcplb_bounds));
-
- i_i = 0;
- /* Normal RAM, including MTD FS. */
- icplb_bounds[i_i].eaddr = uncached_end;
- icplb_bounds[i_i++].data = SDRAM_IGENERIC;
- if (_ramend != physical_mem_end) {
- /* DMA uncached region. */
- if (DMA_UNCACHED_REGION) {
- /* Normally this hole is caught by the async below. */
- icplb_bounds[i_i].eaddr = _ramend;
- icplb_bounds[i_i++].data = 0;
- }
- /* Reserved memory. */
- icplb_bounds[i_i].eaddr = physical_mem_end;
- icplb_bounds[i_i++].data = (reserved_mem_icache_on ?
- SDRAM_IGENERIC : SDRAM_INON_CHBL);
- }
- /* Addressing hole up to the async bank. */
- icplb_bounds[i_i].eaddr = ASYNC_BANK0_BASE;
- icplb_bounds[i_i++].data = 0;
- /* ASYNC banks. */
- icplb_bounds[i_i].eaddr = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE;
- icplb_bounds[i_i++].data = SDRAM_EBIU;
- /* Addressing hole up to BootROM. */
- icplb_bounds[i_i].eaddr = BOOT_ROM_START;
- icplb_bounds[i_i++].data = 0;
- /* BootROM -- largest one should be less than 1 meg. */
- icplb_bounds[i_i].eaddr = BOOT_ROM_START + BOOT_ROM_LENGTH;
- icplb_bounds[i_i++].data = SDRAM_IGENERIC;
-
- if (L2_LENGTH) {
- /* Addressing hole up to L2 SRAM. */
- icplb_bounds[i_i].eaddr = L2_START;
- icplb_bounds[i_i++].data = 0;
- /* L2 SRAM. */
- icplb_bounds[i_i].eaddr = L2_START + L2_LENGTH;
- icplb_bounds[i_i++].data = L2_IMEMORY;
- }
- icplb_nr_bounds = i_i;
- BUG_ON(icplb_nr_bounds > ARRAY_SIZE(icplb_bounds));
-}
+++ /dev/null
-/*
- * Based on: arch/blackfin/kernel/cplb-mpu/cplbmgr.c
- * Author: Michael McTernan <mmcternan@airvana.com>
- *
- * Description: CPLB miss handler.
- *
- * Modified:
- * Copyright 2008 Airvana Inc.
- * Copyright 2008-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <linux/kernel.h>
-#include <asm/blackfin.h>
-#include <asm/cplbinit.h>
-#include <asm/cplb.h>
-#include <asm/mmu_context.h>
-#include <asm/traps.h>
-
-/*
- * WARNING
- *
- * This file is compiled with certain -ffixed-reg options. We have to
- * make sure not to call any functions here that could clobber these
- * registers.
- */
-
-int nr_dcplb_miss[NR_CPUS], nr_icplb_miss[NR_CPUS];
-int nr_dcplb_supv_miss[NR_CPUS], nr_icplb_supv_miss[NR_CPUS];
-int nr_cplb_flush[NR_CPUS], nr_dcplb_prot[NR_CPUS];
-
-#ifdef CONFIG_EXCPT_IRQ_SYSC_L1
-#define MGR_ATTR __attribute__((l1_text))
-#else
-#define MGR_ATTR
-#endif
-
-static inline void write_dcplb_data(int cpu, int idx, unsigned long data,
- unsigned long addr)
-{
- _disable_dcplb();
- bfin_write32(DCPLB_DATA0 + idx * 4, data);
- bfin_write32(DCPLB_ADDR0 + idx * 4, addr);
- _enable_dcplb();
-
-#ifdef CONFIG_CPLB_INFO
- dcplb_tbl[cpu][idx].addr = addr;
- dcplb_tbl[cpu][idx].data = data;
-#endif
-}
-
-static inline void write_icplb_data(int cpu, int idx, unsigned long data,
- unsigned long addr)
-{
- _disable_icplb();
- bfin_write32(ICPLB_DATA0 + idx * 4, data);
- bfin_write32(ICPLB_ADDR0 + idx * 4, addr);
- _enable_icplb();
-
-#ifdef CONFIG_CPLB_INFO
- icplb_tbl[cpu][idx].addr = addr;
- icplb_tbl[cpu][idx].data = data;
-#endif
-}
-
-/* Counters to implement round-robin replacement. */
-static int icplb_rr_index[NR_CPUS] PDT_ATTR;
-static int dcplb_rr_index[NR_CPUS] PDT_ATTR;
-
-/*
- * Find an ICPLB entry to be evicted and return its index.
- */
-static int evict_one_icplb(int cpu)
-{
- int i = first_switched_icplb + icplb_rr_index[cpu];
- if (i >= MAX_CPLBS) {
- i -= MAX_CPLBS - first_switched_icplb;
- icplb_rr_index[cpu] -= MAX_CPLBS - first_switched_icplb;
- }
- icplb_rr_index[cpu]++;
- return i;
-}
-
-static int evict_one_dcplb(int cpu)
-{
- int i = first_switched_dcplb + dcplb_rr_index[cpu];
- if (i >= MAX_CPLBS) {
- i -= MAX_CPLBS - first_switched_dcplb;
- dcplb_rr_index[cpu] -= MAX_CPLBS - first_switched_dcplb;
- }
- dcplb_rr_index[cpu]++;
- return i;
-}
-
-MGR_ATTR static int icplb_miss(int cpu)
-{
- unsigned long addr = bfin_read_ICPLB_FAULT_ADDR();
- int status = bfin_read_ICPLB_STATUS();
- int idx;
- unsigned long i_data, base, addr1, eaddr;
-
- nr_icplb_miss[cpu]++;
- if (unlikely(status & FAULT_USERSUPV))
- nr_icplb_supv_miss[cpu]++;
-
- base = 0;
- idx = 0;
- do {
- eaddr = icplb_bounds[idx].eaddr;
- if (addr < eaddr)
- break;
- base = eaddr;
- } while (++idx < icplb_nr_bounds);
-
- if (unlikely(idx == icplb_nr_bounds))
- return CPLB_NO_ADDR_MATCH;
-
- i_data = icplb_bounds[idx].data;
- if (unlikely(i_data == 0))
- return CPLB_NO_ADDR_MATCH;
-
- addr1 = addr & ~(SIZE_4M - 1);
- addr &= ~(SIZE_1M - 1);
- i_data |= PAGE_SIZE_1MB;
- if (addr1 >= base && (addr1 + SIZE_4M) <= eaddr) {
- /*
- * This works because
- * (PAGE_SIZE_4MB & PAGE_SIZE_1MB) == PAGE_SIZE_1MB.
- */
- i_data |= PAGE_SIZE_4MB;
- addr = addr1;
- }
-
- /* Pick entry to evict */
- idx = evict_one_icplb(cpu);
-
- write_icplb_data(cpu, idx, i_data, addr);
-
- return CPLB_RELOADED;
-}
-
-MGR_ATTR static int dcplb_miss(int cpu)
-{
- unsigned long addr = bfin_read_DCPLB_FAULT_ADDR();
- int status = bfin_read_DCPLB_STATUS();
- int idx;
- unsigned long d_data, base, addr1, eaddr, cplb_pagesize, cplb_pageflags;
-
- nr_dcplb_miss[cpu]++;
- if (unlikely(status & FAULT_USERSUPV))
- nr_dcplb_supv_miss[cpu]++;
-
- base = 0;
- idx = 0;
- do {
- eaddr = dcplb_bounds[idx].eaddr;
- if (addr < eaddr)
- break;
- base = eaddr;
- } while (++idx < dcplb_nr_bounds);
-
- if (unlikely(idx == dcplb_nr_bounds))
- return CPLB_NO_ADDR_MATCH;
-
- d_data = dcplb_bounds[idx].data;
- if (unlikely(d_data == 0))
- return CPLB_NO_ADDR_MATCH;
-
- addr &= ~(SIZE_1M - 1);
- d_data |= PAGE_SIZE_1MB;
-
- /* BF60x support large than 4M CPLB page size */
-#ifdef PAGE_SIZE_16MB
- cplb_pageflags = PAGE_SIZE_16MB;
- cplb_pagesize = SIZE_16M;
-#else
- cplb_pageflags = PAGE_SIZE_4MB;
- cplb_pagesize = SIZE_4M;
-#endif
-
-find_pagesize:
- addr1 = addr & ~(cplb_pagesize - 1);
- if (addr1 >= base && (addr1 + cplb_pagesize) <= eaddr) {
- /*
- * This works because
- * (PAGE_SIZE_4MB & PAGE_SIZE_1MB) == PAGE_SIZE_1MB.
- */
- d_data |= cplb_pageflags;
- addr = addr1;
- goto found_pagesize;
- } else {
- if (cplb_pagesize > SIZE_4M) {
- cplb_pageflags = PAGE_SIZE_4MB;
- cplb_pagesize = SIZE_4M;
- goto find_pagesize;
- }
- }
-
-found_pagesize:
-#ifdef CONFIG_BF60x
- if ((addr >= ASYNC_BANK0_BASE)
- && (addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE))
- d_data |= PAGE_SIZE_64MB;
-#endif
-
- /* Pick entry to evict */
- idx = evict_one_dcplb(cpu);
-
- write_dcplb_data(cpu, idx, d_data, addr);
-
- return CPLB_RELOADED;
-}
-
-MGR_ATTR int cplb_hdr(int seqstat, struct pt_regs *regs)
-{
- int cause = seqstat & 0x3f;
- unsigned int cpu = raw_smp_processor_id();
- switch (cause) {
- case VEC_CPLB_I_M:
- return icplb_miss(cpu);
- case VEC_CPLB_M:
- return dcplb_miss(cpu);
- default:
- return CPLB_UNKNOWN_ERR;
- }
-}
+++ /dev/null
-/*
- * arch/blackfin/kernel/cplbinfo.c - display CPLB status
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/ctype.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/proc_fs.h>
-#include <linux/seq_file.h>
-#include <linux/uaccess.h>
-
-#include <asm/cplbinit.h>
-#include <asm/blackfin.h>
-
-static char const page_strtbl[][4] = {
- "1K", "4K", "1M", "4M",
-#ifdef CONFIG_BF60x
- "16K", "64K", "16M", "64M",
-#endif
-};
-#define page(flags) (((flags) & 0x70000) >> 16)
-#define strpage(flags) page_strtbl[page(flags)]
-
-struct cplbinfo_data {
- loff_t pos;
- char cplb_type;
- u32 mem_control;
- struct cplb_entry *tbl;
- int switched;
-};
-
-static void cplbinfo_print_header(struct seq_file *m)
-{
- seq_printf(m, "Index\tAddress\t\tData\tSize\tU/RD\tU/WR\tS/WR\tSwitch\n");
-}
-
-static int cplbinfo_nomore(struct cplbinfo_data *cdata)
-{
- return cdata->pos >= MAX_CPLBS;
-}
-
-static int cplbinfo_show(struct seq_file *m, void *p)
-{
- struct cplbinfo_data *cdata;
- unsigned long data, addr;
- loff_t pos;
-
- cdata = p;
- pos = cdata->pos;
- addr = cdata->tbl[pos].addr;
- data = cdata->tbl[pos].data;
-
- seq_printf(m,
- "%d\t0x%08lx\t%05lx\t%s\t%c\t%c\t%c\t%c\n",
- (int)pos, addr, data, strpage(data),
- (data & CPLB_USER_RD) ? 'Y' : 'N',
- (data & CPLB_USER_WR) ? 'Y' : 'N',
- (data & CPLB_SUPV_WR) ? 'Y' : 'N',
- pos < cdata->switched ? 'N' : 'Y');
-
- return 0;
-}
-
-static void cplbinfo_seq_init(struct cplbinfo_data *cdata, unsigned int cpu)
-{
- if (cdata->cplb_type == 'I') {
- cdata->mem_control = bfin_read_IMEM_CONTROL();
- cdata->tbl = icplb_tbl[cpu];
- cdata->switched = first_switched_icplb;
- } else {
- cdata->mem_control = bfin_read_DMEM_CONTROL();
- cdata->tbl = dcplb_tbl[cpu];
- cdata->switched = first_switched_dcplb;
- }
-}
-
-static void *cplbinfo_start(struct seq_file *m, loff_t *pos)
-{
- struct cplbinfo_data *cdata = m->private;
-
- if (!*pos) {
- seq_printf(m, "%cCPLBs are %sabled: 0x%x\n", cdata->cplb_type,
- (cdata->mem_control & ENDCPLB ? "en" : "dis"),
- cdata->mem_control);
- cplbinfo_print_header(m);
- } else if (cplbinfo_nomore(cdata))
- return NULL;
-
- get_cpu();
- return cdata;
-}
-
-static void *cplbinfo_next(struct seq_file *m, void *p, loff_t *pos)
-{
- struct cplbinfo_data *cdata = p;
- cdata->pos = ++(*pos);
- if (cplbinfo_nomore(cdata))
- return NULL;
- else
- return cdata;
-}
-
-static void cplbinfo_stop(struct seq_file *m, void *p)
-{
- put_cpu();
-}
-
-static const struct seq_operations cplbinfo_sops = {
- .start = cplbinfo_start,
- .next = cplbinfo_next,
- .stop = cplbinfo_stop,
- .show = cplbinfo_show,
-};
-
-#define CPLBINFO_DCPLB_FLAG 0x80000000
-
-static int cplbinfo_open(struct inode *inode, struct file *file)
-{
- char cplb_type;
- unsigned int cpu = (unsigned long)PDE_DATA(file_inode(file));
- int ret;
- struct seq_file *m;
- struct cplbinfo_data *cdata;
-
- cplb_type = cpu & CPLBINFO_DCPLB_FLAG ? 'D' : 'I';
- cpu &= ~CPLBINFO_DCPLB_FLAG;
-
- if (!cpu_online(cpu))
- return -ENODEV;
-
- ret = seq_open_private(file, &cplbinfo_sops, sizeof(*cdata));
- if (ret)
- return ret;
- m = file->private_data;
- cdata = m->private;
-
- cdata->pos = 0;
- cdata->cplb_type = cplb_type;
- cplbinfo_seq_init(cdata, cpu);
-
- return 0;
-}
-
-static const struct file_operations cplbinfo_fops = {
- .open = cplbinfo_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = seq_release_private,
-};
-
-static int __init cplbinfo_init(void)
-{
- struct proc_dir_entry *cplb_dir, *cpu_dir;
- char buf[10];
- unsigned int cpu;
-
- cplb_dir = proc_mkdir("cplbinfo", NULL);
- if (!cplb_dir)
- return -ENOMEM;
-
- for_each_possible_cpu(cpu) {
- sprintf(buf, "cpu%i", cpu);
- cpu_dir = proc_mkdir(buf, cplb_dir);
- if (!cpu_dir)
- return -ENOMEM;
-
- proc_create_data("icplb", S_IRUGO, cpu_dir, &cplbinfo_fops,
- (void *)cpu);
- proc_create_data("dcplb", S_IRUGO, cpu_dir, &cplbinfo_fops,
- (void *)(cpu | CPLBINFO_DCPLB_FLAG));
- }
-
- return 0;
-}
-late_initcall(cplbinfo_init);
+++ /dev/null
-/*
- * debugfs interface to core/system MMRs
- *
- * Copyright 2007-2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <linux/debugfs.h>
-#include <linux/fs.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-
-#include <asm/blackfin.h>
-#include <asm/gptimers.h>
-#include <asm/bfin_can.h>
-#include <asm/bfin_dma.h>
-#include <asm/bfin_ppi.h>
-#include <asm/bfin_serial.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/bfin_twi.h>
-#include <asm/gpio.h>
-
-/* Common code defines PORT_MUX on us, so redirect the MMR back locally */
-#ifdef BFIN_PORT_MUX
-#undef PORT_MUX
-#define PORT_MUX BFIN_PORT_MUX
-#endif
-
-#define _d(name, bits, addr, perms) debugfs_create_x##bits(name, perms, parent, (u##bits *)(addr))
-#define d(name, bits, addr) _d(name, bits, addr, S_IRUSR|S_IWUSR)
-#define d_RO(name, bits, addr) _d(name, bits, addr, S_IRUSR)
-#define d_WO(name, bits, addr) _d(name, bits, addr, S_IWUSR)
-
-#define D_RO(name, bits) d_RO(#name, bits, name)
-#define D_WO(name, bits) d_WO(#name, bits, name)
-#define D32(name) d(#name, 32, name)
-#define D16(name) d(#name, 16, name)
-
-#define REGS_OFF(peri, mmr) offsetof(struct bfin_##peri##_regs, mmr)
-#define __REGS(peri, sname, rname) \
- do { \
- struct bfin_##peri##_regs r; \
- void *addr = (void *)(base + REGS_OFF(peri, rname)); \
- strcpy(_buf, sname); \
- if (sizeof(r.rname) == 2) \
- debugfs_create_x16(buf, S_IRUSR|S_IWUSR, parent, addr); \
- else \
- debugfs_create_x32(buf, S_IRUSR|S_IWUSR, parent, addr); \
- } while (0)
-#define REGS_STR_PFX(buf, pfx, num) \
- ({ \
- buf + (num >= 0 ? \
- sprintf(buf, #pfx "%i_", num) : \
- sprintf(buf, #pfx "_")); \
- })
-#define REGS_STR_PFX_C(buf, pfx, num) \
- ({ \
- buf + (num >= 0 ? \
- sprintf(buf, #pfx "%c_", 'A' + num) : \
- sprintf(buf, #pfx "_")); \
- })
-
-/*
- * Core registers (not memory mapped)
- */
-extern u32 last_seqstat;
-
-static int debug_cclk_get(void *data, u64 *val)
-{
- *val = get_cclk();
- return 0;
-}
-DEFINE_SIMPLE_ATTRIBUTE(fops_debug_cclk, debug_cclk_get, NULL, "0x%08llx\n");
-
-static int debug_sclk_get(void *data, u64 *val)
-{
- *val = get_sclk();
- return 0;
-}
-DEFINE_SIMPLE_ATTRIBUTE(fops_debug_sclk, debug_sclk_get, NULL, "0x%08llx\n");
-
-#define DEFINE_SYSREG(sr, pre, post) \
-static int sysreg_##sr##_get(void *data, u64 *val) \
-{ \
- unsigned long tmp; \
- pre; \
- __asm__ __volatile__("%0 = " #sr ";" : "=d"(tmp)); \
- *val = tmp; \
- return 0; \
-} \
-static int sysreg_##sr##_set(void *data, u64 val) \
-{ \
- unsigned long tmp = val; \
- __asm__ __volatile__(#sr " = %0;" : : "d"(tmp)); \
- post; \
- return 0; \
-} \
-DEFINE_SIMPLE_ATTRIBUTE(fops_sysreg_##sr, sysreg_##sr##_get, sysreg_##sr##_set, "0x%08llx\n")
-
-DEFINE_SYSREG(cycles, , );
-DEFINE_SYSREG(cycles2, __asm__ __volatile__("%0 = cycles;" : "=d"(tmp)), );
-DEFINE_SYSREG(emudat, , );
-DEFINE_SYSREG(seqstat, , );
-DEFINE_SYSREG(syscfg, , CSYNC());
-#define D_SYSREG(sr) debugfs_create_file(#sr, S_IRUSR|S_IWUSR, parent, NULL, &fops_sysreg_##sr)
-
-#ifndef CONFIG_BF60x
-/*
- * CAN
- */
-#define CAN_OFF(mmr) REGS_OFF(can, mmr)
-#define __CAN(uname, lname) __REGS(can, #uname, lname)
-static void __init __maybe_unused
-bfin_debug_mmrs_can(struct dentry *parent, unsigned long base, int num)
-{
- static struct dentry *am, *mb;
- int i, j;
- char buf[32], *_buf = REGS_STR_PFX(buf, CAN, num);
-
- if (!am) {
- am = debugfs_create_dir("am", parent);
- mb = debugfs_create_dir("mb", parent);
- }
-
- __CAN(MC1, mc1);
- __CAN(MD1, md1);
- __CAN(TRS1, trs1);
- __CAN(TRR1, trr1);
- __CAN(TA1, ta1);
- __CAN(AA1, aa1);
- __CAN(RMP1, rmp1);
- __CAN(RML1, rml1);
- __CAN(MBTIF1, mbtif1);
- __CAN(MBRIF1, mbrif1);
- __CAN(MBIM1, mbim1);
- __CAN(RFH1, rfh1);
- __CAN(OPSS1, opss1);
-
- __CAN(MC2, mc2);
- __CAN(MD2, md2);
- __CAN(TRS2, trs2);
- __CAN(TRR2, trr2);
- __CAN(TA2, ta2);
- __CAN(AA2, aa2);
- __CAN(RMP2, rmp2);
- __CAN(RML2, rml2);
- __CAN(MBTIF2, mbtif2);
- __CAN(MBRIF2, mbrif2);
- __CAN(MBIM2, mbim2);
- __CAN(RFH2, rfh2);
- __CAN(OPSS2, opss2);
-
- __CAN(CLOCK, clock);
- __CAN(TIMING, timing);
- __CAN(DEBUG, debug);
- __CAN(STATUS, status);
- __CAN(CEC, cec);
- __CAN(GIS, gis);
- __CAN(GIM, gim);
- __CAN(GIF, gif);
- __CAN(CONTROL, control);
- __CAN(INTR, intr);
- __CAN(VERSION, version);
- __CAN(MBTD, mbtd);
- __CAN(EWR, ewr);
- __CAN(ESR, esr);
- /*__CAN(UCREG, ucreg); no longer exists */
- __CAN(UCCNT, uccnt);
- __CAN(UCRC, ucrc);
- __CAN(UCCNF, uccnf);
- __CAN(VERSION2, version2);
-
- for (i = 0; i < 32; ++i) {
- sprintf(_buf, "AM%02iL", i);
- debugfs_create_x16(buf, S_IRUSR|S_IWUSR, am,
- (u16 *)(base + CAN_OFF(msk[i].aml)));
- sprintf(_buf, "AM%02iH", i);
- debugfs_create_x16(buf, S_IRUSR|S_IWUSR, am,
- (u16 *)(base + CAN_OFF(msk[i].amh)));
-
- for (j = 0; j < 3; ++j) {
- sprintf(_buf, "MB%02i_DATA%i", i, j);
- debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
- (u16 *)(base + CAN_OFF(chl[i].data[j*2])));
- }
- sprintf(_buf, "MB%02i_LENGTH", i);
- debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
- (u16 *)(base + CAN_OFF(chl[i].dlc)));
- sprintf(_buf, "MB%02i_TIMESTAMP", i);
- debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
- (u16 *)(base + CAN_OFF(chl[i].tsv)));
- sprintf(_buf, "MB%02i_ID0", i);
- debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
- (u16 *)(base + CAN_OFF(chl[i].id0)));
- sprintf(_buf, "MB%02i_ID1", i);
- debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
- (u16 *)(base + CAN_OFF(chl[i].id1)));
- }
-}
-#define CAN(num) bfin_debug_mmrs_can(parent, CAN##num##_MC1, num)
-
-/*
- * DMA
- */
-#define __DMA(uname, lname) __REGS(dma, #uname, lname)
-static void __init __maybe_unused
-bfin_debug_mmrs_dma(struct dentry *parent, unsigned long base, int num, char mdma, const char *pfx)
-{
- char buf[32], *_buf;
-
- if (mdma)
- _buf = buf + sprintf(buf, "%s_%c%i_", pfx, mdma, num);
- else
- _buf = buf + sprintf(buf, "%s%i_", pfx, num);
-
- __DMA(NEXT_DESC_PTR, next_desc_ptr);
- __DMA(START_ADDR, start_addr);
- __DMA(CONFIG, config);
- __DMA(X_COUNT, x_count);
- __DMA(X_MODIFY, x_modify);
- __DMA(Y_COUNT, y_count);
- __DMA(Y_MODIFY, y_modify);
- __DMA(CURR_DESC_PTR, curr_desc_ptr);
- __DMA(CURR_ADDR, curr_addr);
- __DMA(IRQ_STATUS, irq_status);
-#ifndef CONFIG_BF60x
- if (strcmp(pfx, "IMDMA") != 0)
- __DMA(PERIPHERAL_MAP, peripheral_map);
-#endif
- __DMA(CURR_X_COUNT, curr_x_count);
- __DMA(CURR_Y_COUNT, curr_y_count);
-}
-#define _DMA(num, base, mdma, pfx) bfin_debug_mmrs_dma(parent, base, num, mdma, pfx "DMA")
-#define DMA(num) _DMA(num, DMA##num##_NEXT_DESC_PTR, 0, "")
-#define _MDMA(num, x) \
- do { \
- _DMA(num, x##DMA_D##num##_NEXT_DESC_PTR, 'D', #x); \
- _DMA(num, x##DMA_S##num##_NEXT_DESC_PTR, 'S', #x); \
- } while (0)
-#define MDMA(num) _MDMA(num, M)
-#define IMDMA(num) _MDMA(num, IM)
-
-/*
- * EPPI
- */
-#define __EPPI(uname, lname) __REGS(eppi, #uname, lname)
-static void __init __maybe_unused
-bfin_debug_mmrs_eppi(struct dentry *parent, unsigned long base, int num)
-{
- char buf[32], *_buf = REGS_STR_PFX(buf, EPPI, num);
- __EPPI(STATUS, status);
- __EPPI(HCOUNT, hcount);
- __EPPI(HDELAY, hdelay);
- __EPPI(VCOUNT, vcount);
- __EPPI(VDELAY, vdelay);
- __EPPI(FRAME, frame);
- __EPPI(LINE, line);
- __EPPI(CLKDIV, clkdiv);
- __EPPI(CONTROL, control);
- __EPPI(FS1W_HBL, fs1w_hbl);
- __EPPI(FS1P_AVPL, fs1p_avpl);
- __EPPI(FS2W_LVB, fs2w_lvb);
- __EPPI(FS2P_LAVF, fs2p_lavf);
- __EPPI(CLIP, clip);
-}
-#define EPPI(num) bfin_debug_mmrs_eppi(parent, EPPI##num##_STATUS, num)
-
-/*
- * General Purpose Timers
- */
-#define __GPTIMER(uname, lname) __REGS(gptimer, #uname, lname)
-static void __init __maybe_unused
-bfin_debug_mmrs_gptimer(struct dentry *parent, unsigned long base, int num)
-{
- char buf[32], *_buf = REGS_STR_PFX(buf, TIMER, num);
- __GPTIMER(CONFIG, config);
- __GPTIMER(COUNTER, counter);
- __GPTIMER(PERIOD, period);
- __GPTIMER(WIDTH, width);
-}
-#define GPTIMER(num) bfin_debug_mmrs_gptimer(parent, TIMER##num##_CONFIG, num)
-
-#define GPTIMER_GROUP_OFF(mmr) REGS_OFF(gptimer_group, mmr)
-#define __GPTIMER_GROUP(uname, lname) __REGS(gptimer_group, #uname, lname)
-static void __init __maybe_unused
-bfin_debug_mmrs_gptimer_group(struct dentry *parent, unsigned long base, int num)
-{
- char buf[32], *_buf;
-
- if (num == -1) {
- _buf = buf + sprintf(buf, "TIMER_");
- __GPTIMER_GROUP(ENABLE, enable);
- __GPTIMER_GROUP(DISABLE, disable);
- __GPTIMER_GROUP(STATUS, status);
- } else {
- /* These MMRs are a bit odd as the group # is a suffix */
- _buf = buf + sprintf(buf, "TIMER_ENABLE%i", num);
- d(buf, 16, base + GPTIMER_GROUP_OFF(enable));
-
- _buf = buf + sprintf(buf, "TIMER_DISABLE%i", num);
- d(buf, 16, base + GPTIMER_GROUP_OFF(disable));
-
- _buf = buf + sprintf(buf, "TIMER_STATUS%i", num);
- d(buf, 32, base + GPTIMER_GROUP_OFF(status));
- }
-}
-#define GPTIMER_GROUP(mmr, num) bfin_debug_mmrs_gptimer_group(parent, mmr, num)
-
-/*
- * Handshake MDMA
- */
-#define __HMDMA(uname, lname) __REGS(hmdma, #uname, lname)
-static void __init __maybe_unused
-bfin_debug_mmrs_hmdma(struct dentry *parent, unsigned long base, int num)
-{
- char buf[32], *_buf = REGS_STR_PFX(buf, HMDMA, num);
- __HMDMA(CONTROL, control);
- __HMDMA(ECINIT, ecinit);
- __HMDMA(BCINIT, bcinit);
- __HMDMA(ECURGENT, ecurgent);
- __HMDMA(ECOVERFLOW, ecoverflow);
- __HMDMA(ECOUNT, ecount);
- __HMDMA(BCOUNT, bcount);
-}
-#define HMDMA(num) bfin_debug_mmrs_hmdma(parent, HMDMA##num##_CONTROL, num)
-
-/*
- * Peripheral Interrupts (PINT/GPIO)
- */
-#ifdef PINT0_MASK_SET
-#define __PINT(uname, lname) __REGS(pint, #uname, lname)
-static void __init __maybe_unused
-bfin_debug_mmrs_pint(struct dentry *parent, unsigned long base, int num)
-{
- char buf[32], *_buf = REGS_STR_PFX(buf, PINT, num);
- __PINT(MASK_SET, mask_set);
- __PINT(MASK_CLEAR, mask_clear);
- __PINT(REQUEST, request);
- __PINT(ASSIGN, assign);
- __PINT(EDGE_SET, edge_set);
- __PINT(EDGE_CLEAR, edge_clear);
- __PINT(INVERT_SET, invert_set);
- __PINT(INVERT_CLEAR, invert_clear);
- __PINT(PINSTATE, pinstate);
- __PINT(LATCH, latch);
-}
-#define PINT(num) bfin_debug_mmrs_pint(parent, PINT##num##_MASK_SET, num)
-#endif
-
-/*
- * Port/GPIO
- */
-#define bfin_gpio_regs gpio_port_t
-#define __PORT(uname, lname) __REGS(gpio, #uname, lname)
-static void __init __maybe_unused
-bfin_debug_mmrs_port(struct dentry *parent, unsigned long base, int num)
-{
- char buf[32], *_buf;
-#ifdef __ADSPBF54x__
- _buf = REGS_STR_PFX_C(buf, PORT, num);
- __PORT(FER, port_fer);
- __PORT(SET, data_set);
- __PORT(CLEAR, data_clear);
- __PORT(DIR_SET, dir_set);
- __PORT(DIR_CLEAR, dir_clear);
- __PORT(INEN, inen);
- __PORT(MUX, port_mux);
-#else
- _buf = buf + sprintf(buf, "PORT%cIO_", num);
- __PORT(CLEAR, data_clear);
- __PORT(SET, data_set);
- __PORT(TOGGLE, toggle);
- __PORT(MASKA, maska);
- __PORT(MASKA_CLEAR, maska_clear);
- __PORT(MASKA_SET, maska_set);
- __PORT(MASKA_TOGGLE, maska_toggle);
- __PORT(MASKB, maskb);
- __PORT(MASKB_CLEAR, maskb_clear);
- __PORT(MASKB_SET, maskb_set);
- __PORT(MASKB_TOGGLE, maskb_toggle);
- __PORT(DIR, dir);
- __PORT(POLAR, polar);
- __PORT(EDGE, edge);
- __PORT(BOTH, both);
- __PORT(INEN, inen);
-#endif
- _buf[-1] = '\0';
- d(buf, 16, base + REGS_OFF(gpio, data));
-}
-#define PORT(base, num) bfin_debug_mmrs_port(parent, base, num)
-
-/*
- * PPI
- */
-#define __PPI(uname, lname) __REGS(ppi, #uname, lname)
-static void __init __maybe_unused
-bfin_debug_mmrs_ppi(struct dentry *parent, unsigned long base, int num)
-{
- char buf[32], *_buf = REGS_STR_PFX(buf, PPI, num);
- __PPI(CONTROL, control);
- __PPI(STATUS, status);
- __PPI(COUNT, count);
- __PPI(DELAY, delay);
- __PPI(FRAME, frame);
-}
-#define PPI(num) bfin_debug_mmrs_ppi(parent, PPI##num##_CONTROL, num)
-
-/*
- * SPI
- */
-#define __SPI(uname, lname) __REGS(spi, #uname, lname)
-static void __init __maybe_unused
-bfin_debug_mmrs_spi(struct dentry *parent, unsigned long base, int num)
-{
- char buf[32], *_buf = REGS_STR_PFX(buf, SPI, num);
- __SPI(CTL, ctl);
- __SPI(FLG, flg);
- __SPI(STAT, stat);
- __SPI(TDBR, tdbr);
- __SPI(RDBR, rdbr);
- __SPI(BAUD, baud);
- __SPI(SHADOW, shadow);
-}
-#define SPI(num) bfin_debug_mmrs_spi(parent, SPI##num##_REGBASE, num)
-
-/*
- * SPORT
- */
-static inline int sport_width(void *mmr)
-{
- unsigned long lmmr = (unsigned long)mmr;
- if ((lmmr & 0xff) == 0x10)
- /* SPORT#_TX has 0x10 offset -> SPORT#_TCR2 has 0x04 offset */
- lmmr -= 0xc;
- else
- /* SPORT#_RX has 0x18 offset -> SPORT#_RCR2 has 0x24 offset */
- lmmr += 0xc;
- /* extract SLEN field from control register 2 and add 1 */
- return (bfin_read16(lmmr) & 0x1f) + 1;
-}
-static int sport_set(void *mmr, u64 val)
-{
- unsigned long flags;
- local_irq_save(flags);
- if (sport_width(mmr) <= 16)
- bfin_write16(mmr, val);
- else
- bfin_write32(mmr, val);
- local_irq_restore(flags);
- return 0;
-}
-static int sport_get(void *mmr, u64 *val)
-{
- unsigned long flags;
- local_irq_save(flags);
- if (sport_width(mmr) <= 16)
- *val = bfin_read16(mmr);
- else
- *val = bfin_read32(mmr);
- local_irq_restore(flags);
- return 0;
-}
-DEFINE_SIMPLE_ATTRIBUTE(fops_sport, sport_get, sport_set, "0x%08llx\n");
-/*DEFINE_SIMPLE_ATTRIBUTE(fops_sport_ro, sport_get, NULL, "0x%08llx\n");*/
-DEFINE_SIMPLE_ATTRIBUTE(fops_sport_wo, NULL, sport_set, "0x%08llx\n");
-#define SPORT_OFF(mmr) (SPORT0_##mmr - SPORT0_TCR1)
-#define _D_SPORT(name, perms, fops) \
- do { \
- strcpy(_buf, #name); \
- debugfs_create_file(buf, perms, parent, (void *)(base + SPORT_OFF(name)), fops); \
- } while (0)
-#define __SPORT_RW(name) _D_SPORT(name, S_IRUSR|S_IWUSR, &fops_sport)
-#define __SPORT_RO(name) _D_SPORT(name, S_IRUSR, &fops_sport_ro)
-#define __SPORT_WO(name) _D_SPORT(name, S_IWUSR, &fops_sport_wo)
-#define __SPORT(name, bits) \
- do { \
- strcpy(_buf, #name); \
- debugfs_create_x##bits(buf, S_IRUSR|S_IWUSR, parent, (u##bits *)(base + SPORT_OFF(name))); \
- } while (0)
-static void __init __maybe_unused
-bfin_debug_mmrs_sport(struct dentry *parent, unsigned long base, int num)
-{
- char buf[32], *_buf = REGS_STR_PFX(buf, SPORT, num);
- __SPORT(CHNL, 16);
- __SPORT(MCMC1, 16);
- __SPORT(MCMC2, 16);
- __SPORT(MRCS0, 32);
- __SPORT(MRCS1, 32);
- __SPORT(MRCS2, 32);
- __SPORT(MRCS3, 32);
- __SPORT(MTCS0, 32);
- __SPORT(MTCS1, 32);
- __SPORT(MTCS2, 32);
- __SPORT(MTCS3, 32);
- __SPORT(RCLKDIV, 16);
- __SPORT(RCR1, 16);
- __SPORT(RCR2, 16);
- __SPORT(RFSDIV, 16);
- __SPORT_RW(RX);
- __SPORT(STAT, 16);
- __SPORT(TCLKDIV, 16);
- __SPORT(TCR1, 16);
- __SPORT(TCR2, 16);
- __SPORT(TFSDIV, 16);
- __SPORT_WO(TX);
-}
-#define SPORT(num) bfin_debug_mmrs_sport(parent, SPORT##num##_TCR1, num)
-
-/*
- * TWI
- */
-#define __TWI(uname, lname) __REGS(twi, #uname, lname)
-static void __init __maybe_unused
-bfin_debug_mmrs_twi(struct dentry *parent, unsigned long base, int num)
-{
- char buf[32], *_buf = REGS_STR_PFX(buf, TWI, num);
- __TWI(CLKDIV, clkdiv);
- __TWI(CONTROL, control);
- __TWI(SLAVE_CTL, slave_ctl);
- __TWI(SLAVE_STAT, slave_stat);
- __TWI(SLAVE_ADDR, slave_addr);
- __TWI(MASTER_CTL, master_ctl);
- __TWI(MASTER_STAT, master_stat);
- __TWI(MASTER_ADDR, master_addr);
- __TWI(INT_STAT, int_stat);
- __TWI(INT_MASK, int_mask);
- __TWI(FIFO_CTL, fifo_ctl);
- __TWI(FIFO_STAT, fifo_stat);
- __TWI(XMT_DATA8, xmt_data8);
- __TWI(XMT_DATA16, xmt_data16);
- __TWI(RCV_DATA8, rcv_data8);
- __TWI(RCV_DATA16, rcv_data16);
-}
-#define TWI(num) bfin_debug_mmrs_twi(parent, TWI##num##_CLKDIV, num)
-
-/*
- * UART
- */
-#define __UART(uname, lname) __REGS(uart, #uname, lname)
-static void __init __maybe_unused
-bfin_debug_mmrs_uart(struct dentry *parent, unsigned long base, int num)
-{
- char buf[32], *_buf = REGS_STR_PFX(buf, UART, num);
-#ifdef BFIN_UART_BF54X_STYLE
- __UART(DLL, dll);
- __UART(DLH, dlh);
- __UART(GCTL, gctl);
- __UART(LCR, lcr);
- __UART(MCR, mcr);
- __UART(LSR, lsr);
- __UART(MSR, msr);
- __UART(SCR, scr);
- __UART(IER_SET, ier_set);
- __UART(IER_CLEAR, ier_clear);
- __UART(THR, thr);
- __UART(RBR, rbr);
-#else
- __UART(DLL, dll);
- __UART(THR, thr);
- __UART(RBR, rbr);
- __UART(DLH, dlh);
- __UART(IER, ier);
- __UART(IIR, iir);
- __UART(LCR, lcr);
- __UART(MCR, mcr);
- __UART(LSR, lsr);
- __UART(MSR, msr);
- __UART(SCR, scr);
- __UART(GCTL, gctl);
-#endif
-}
-#define UART(num) bfin_debug_mmrs_uart(parent, UART##num##_DLL, num)
-#endif /* CONFIG_BF60x */
-/*
- * The actual debugfs generation
- */
-static struct dentry *debug_mmrs_dentry;
-
-static int __init bfin_debug_mmrs_init(void)
-{
- struct dentry *top, *parent;
-
- pr_info("debug-mmrs: setting up Blackfin MMR debugfs\n");
-
- top = debugfs_create_dir("blackfin", NULL);
- if (top == NULL)
- return -1;
-
- parent = debugfs_create_dir("core_regs", top);
- debugfs_create_file("cclk", S_IRUSR, parent, NULL, &fops_debug_cclk);
- debugfs_create_file("sclk", S_IRUSR, parent, NULL, &fops_debug_sclk);
- debugfs_create_x32("last_seqstat", S_IRUSR, parent, &last_seqstat);
- D_SYSREG(cycles);
- D_SYSREG(cycles2);
- D_SYSREG(emudat);
- D_SYSREG(seqstat);
- D_SYSREG(syscfg);
-
- /* Core MMRs */
- parent = debugfs_create_dir("ctimer", top);
- D32(TCNTL);
- D32(TCOUNT);
- D32(TPERIOD);
- D32(TSCALE);
-
- parent = debugfs_create_dir("cec", top);
- D32(EVT0);
- D32(EVT1);
- D32(EVT2);
- D32(EVT3);
- D32(EVT4);
- D32(EVT5);
- D32(EVT6);
- D32(EVT7);
- D32(EVT8);
- D32(EVT9);
- D32(EVT10);
- D32(EVT11);
- D32(EVT12);
- D32(EVT13);
- D32(EVT14);
- D32(EVT15);
- D32(EVT_OVERRIDE);
- D32(IMASK);
- D32(IPEND);
- D32(ILAT);
- D32(IPRIO);
-
- parent = debugfs_create_dir("debug", top);
- D32(DBGSTAT);
- D32(DSPID);
-
- parent = debugfs_create_dir("mmu", top);
- D32(SRAM_BASE_ADDRESS);
- D32(DCPLB_ADDR0);
- D32(DCPLB_ADDR10);
- D32(DCPLB_ADDR11);
- D32(DCPLB_ADDR12);
- D32(DCPLB_ADDR13);
- D32(DCPLB_ADDR14);
- D32(DCPLB_ADDR15);
- D32(DCPLB_ADDR1);
- D32(DCPLB_ADDR2);
- D32(DCPLB_ADDR3);
- D32(DCPLB_ADDR4);
- D32(DCPLB_ADDR5);
- D32(DCPLB_ADDR6);
- D32(DCPLB_ADDR7);
- D32(DCPLB_ADDR8);
- D32(DCPLB_ADDR9);
- D32(DCPLB_DATA0);
- D32(DCPLB_DATA10);
- D32(DCPLB_DATA11);
- D32(DCPLB_DATA12);
- D32(DCPLB_DATA13);
- D32(DCPLB_DATA14);
- D32(DCPLB_DATA15);
- D32(DCPLB_DATA1);
- D32(DCPLB_DATA2);
- D32(DCPLB_DATA3);
- D32(DCPLB_DATA4);
- D32(DCPLB_DATA5);
- D32(DCPLB_DATA6);
- D32(DCPLB_DATA7);
- D32(DCPLB_DATA8);
- D32(DCPLB_DATA9);
- D32(DCPLB_FAULT_ADDR);
- D32(DCPLB_STATUS);
- D32(DMEM_CONTROL);
- D32(DTEST_COMMAND);
- D32(DTEST_DATA0);
- D32(DTEST_DATA1);
-
- D32(ICPLB_ADDR0);
- D32(ICPLB_ADDR1);
- D32(ICPLB_ADDR2);
- D32(ICPLB_ADDR3);
- D32(ICPLB_ADDR4);
- D32(ICPLB_ADDR5);
- D32(ICPLB_ADDR6);
- D32(ICPLB_ADDR7);
- D32(ICPLB_ADDR8);
- D32(ICPLB_ADDR9);
- D32(ICPLB_ADDR10);
- D32(ICPLB_ADDR11);
- D32(ICPLB_ADDR12);
- D32(ICPLB_ADDR13);
- D32(ICPLB_ADDR14);
- D32(ICPLB_ADDR15);
- D32(ICPLB_DATA0);
- D32(ICPLB_DATA1);
- D32(ICPLB_DATA2);
- D32(ICPLB_DATA3);
- D32(ICPLB_DATA4);
- D32(ICPLB_DATA5);
- D32(ICPLB_DATA6);
- D32(ICPLB_DATA7);
- D32(ICPLB_DATA8);
- D32(ICPLB_DATA9);
- D32(ICPLB_DATA10);
- D32(ICPLB_DATA11);
- D32(ICPLB_DATA12);
- D32(ICPLB_DATA13);
- D32(ICPLB_DATA14);
- D32(ICPLB_DATA15);
- D32(ICPLB_FAULT_ADDR);
- D32(ICPLB_STATUS);
- D32(IMEM_CONTROL);
- if (!ANOMALY_05000481) {
- D32(ITEST_COMMAND);
- D32(ITEST_DATA0);
- D32(ITEST_DATA1);
- }
-
- parent = debugfs_create_dir("perf", top);
- D32(PFCNTR0);
- D32(PFCNTR1);
- D32(PFCTL);
-
- parent = debugfs_create_dir("trace", top);
- D32(TBUF);
- D32(TBUFCTL);
- D32(TBUFSTAT);
-
- parent = debugfs_create_dir("watchpoint", top);
- D32(WPIACTL);
- D32(WPIA0);
- D32(WPIA1);
- D32(WPIA2);
- D32(WPIA3);
- D32(WPIA4);
- D32(WPIA5);
- D32(WPIACNT0);
- D32(WPIACNT1);
- D32(WPIACNT2);
- D32(WPIACNT3);
- D32(WPIACNT4);
- D32(WPIACNT5);
- D32(WPDACTL);
- D32(WPDA0);
- D32(WPDA1);
- D32(WPDACNT0);
- D32(WPDACNT1);
- D32(WPSTAT);
-#ifndef CONFIG_BF60x
- /* System MMRs */
-#ifdef ATAPI_CONTROL
- parent = debugfs_create_dir("atapi", top);
- D16(ATAPI_CONTROL);
- D16(ATAPI_DEV_ADDR);
- D16(ATAPI_DEV_RXBUF);
- D16(ATAPI_DEV_TXBUF);
- D16(ATAPI_DMA_TFRCNT);
- D16(ATAPI_INT_MASK);
- D16(ATAPI_INT_STATUS);
- D16(ATAPI_LINE_STATUS);
- D16(ATAPI_MULTI_TIM_0);
- D16(ATAPI_MULTI_TIM_1);
- D16(ATAPI_MULTI_TIM_2);
- D16(ATAPI_PIO_TFRCNT);
- D16(ATAPI_PIO_TIM_0);
- D16(ATAPI_PIO_TIM_1);
- D16(ATAPI_REG_TIM_0);
- D16(ATAPI_SM_STATE);
- D16(ATAPI_STATUS);
- D16(ATAPI_TERMINATE);
- D16(ATAPI_UDMAOUT_TFRCNT);
- D16(ATAPI_ULTRA_TIM_0);
- D16(ATAPI_ULTRA_TIM_1);
- D16(ATAPI_ULTRA_TIM_2);
- D16(ATAPI_ULTRA_TIM_3);
- D16(ATAPI_UMAIN_TFRCNT);
- D16(ATAPI_XFER_LEN);
-#endif
-
-#if defined(CAN_MC1) || defined(CAN0_MC1) || defined(CAN1_MC1)
- parent = debugfs_create_dir("can", top);
-# ifdef CAN_MC1
- bfin_debug_mmrs_can(parent, CAN_MC1, -1);
-# endif
-# ifdef CAN0_MC1
- CAN(0);
-# endif
-# ifdef CAN1_MC1
- CAN(1);
-# endif
-#endif
-
-#ifdef CNT_COMMAND
- parent = debugfs_create_dir("counter", top);
- D16(CNT_COMMAND);
- D16(CNT_CONFIG);
- D32(CNT_COUNTER);
- D16(CNT_DEBOUNCE);
- D16(CNT_IMASK);
- D32(CNT_MAX);
- D32(CNT_MIN);
- D16(CNT_STATUS);
-#endif
-
- parent = debugfs_create_dir("dmac", top);
-#ifdef DMAC_TC_CNT
- D16(DMAC_TC_CNT);
- D16(DMAC_TC_PER);
-#endif
-#ifdef DMAC0_TC_CNT
- D16(DMAC0_TC_CNT);
- D16(DMAC0_TC_PER);
-#endif
-#ifdef DMAC1_TC_CNT
- D16(DMAC1_TC_CNT);
- D16(DMAC1_TC_PER);
-#endif
-#ifdef DMAC1_PERIMUX
- D16(DMAC1_PERIMUX);
-#endif
-
-#ifdef __ADSPBF561__
- /* XXX: should rewrite the MMR map */
-# define DMA0_NEXT_DESC_PTR DMA2_0_NEXT_DESC_PTR
-# define DMA1_NEXT_DESC_PTR DMA2_1_NEXT_DESC_PTR
-# define DMA2_NEXT_DESC_PTR DMA2_2_NEXT_DESC_PTR
-# define DMA3_NEXT_DESC_PTR DMA2_3_NEXT_DESC_PTR
-# define DMA4_NEXT_DESC_PTR DMA2_4_NEXT_DESC_PTR
-# define DMA5_NEXT_DESC_PTR DMA2_5_NEXT_DESC_PTR
-# define DMA6_NEXT_DESC_PTR DMA2_6_NEXT_DESC_PTR
-# define DMA7_NEXT_DESC_PTR DMA2_7_NEXT_DESC_PTR
-# define DMA8_NEXT_DESC_PTR DMA2_8_NEXT_DESC_PTR
-# define DMA9_NEXT_DESC_PTR DMA2_9_NEXT_DESC_PTR
-# define DMA10_NEXT_DESC_PTR DMA2_10_NEXT_DESC_PTR
-# define DMA11_NEXT_DESC_PTR DMA2_11_NEXT_DESC_PTR
-# define DMA12_NEXT_DESC_PTR DMA1_0_NEXT_DESC_PTR
-# define DMA13_NEXT_DESC_PTR DMA1_1_NEXT_DESC_PTR
-# define DMA14_NEXT_DESC_PTR DMA1_2_NEXT_DESC_PTR
-# define DMA15_NEXT_DESC_PTR DMA1_3_NEXT_DESC_PTR
-# define DMA16_NEXT_DESC_PTR DMA1_4_NEXT_DESC_PTR
-# define DMA17_NEXT_DESC_PTR DMA1_5_NEXT_DESC_PTR
-# define DMA18_NEXT_DESC_PTR DMA1_6_NEXT_DESC_PTR
-# define DMA19_NEXT_DESC_PTR DMA1_7_NEXT_DESC_PTR
-# define DMA20_NEXT_DESC_PTR DMA1_8_NEXT_DESC_PTR
-# define DMA21_NEXT_DESC_PTR DMA1_9_NEXT_DESC_PTR
-# define DMA22_NEXT_DESC_PTR DMA1_10_NEXT_DESC_PTR
-# define DMA23_NEXT_DESC_PTR DMA1_11_NEXT_DESC_PTR
-#endif
- parent = debugfs_create_dir("dma", top);
- DMA(0);
- DMA(1);
- DMA(1);
- DMA(2);
- DMA(3);
- DMA(4);
- DMA(5);
- DMA(6);
- DMA(7);
-#ifdef DMA8_NEXT_DESC_PTR
- DMA(8);
- DMA(9);
- DMA(10);
- DMA(11);
-#endif
-#ifdef DMA12_NEXT_DESC_PTR
- DMA(12);
- DMA(13);
- DMA(14);
- DMA(15);
- DMA(16);
- DMA(17);
- DMA(18);
- DMA(19);
-#endif
-#ifdef DMA20_NEXT_DESC_PTR
- DMA(20);
- DMA(21);
- DMA(22);
- DMA(23);
-#endif
-
- parent = debugfs_create_dir("ebiu_amc", top);
- D32(EBIU_AMBCTL0);
- D32(EBIU_AMBCTL1);
- D16(EBIU_AMGCTL);
-#ifdef EBIU_MBSCTL
- D16(EBIU_MBSCTL);
- D32(EBIU_ARBSTAT);
- D32(EBIU_MODE);
- D16(EBIU_FCTL);
-#endif
-
-#ifdef EBIU_SDGCTL
- parent = debugfs_create_dir("ebiu_sdram", top);
-# ifdef __ADSPBF561__
- D32(EBIU_SDBCTL);
-# else
- D16(EBIU_SDBCTL);
-# endif
- D32(EBIU_SDGCTL);
- D16(EBIU_SDRRC);
- D16(EBIU_SDSTAT);
-#endif
-
-#ifdef EBIU_DDRACCT
- parent = debugfs_create_dir("ebiu_ddr", top);
- D32(EBIU_DDRACCT);
- D32(EBIU_DDRARCT);
- D32(EBIU_DDRBRC0);
- D32(EBIU_DDRBRC1);
- D32(EBIU_DDRBRC2);
- D32(EBIU_DDRBRC3);
- D32(EBIU_DDRBRC4);
- D32(EBIU_DDRBRC5);
- D32(EBIU_DDRBRC6);
- D32(EBIU_DDRBRC7);
- D32(EBIU_DDRBWC0);
- D32(EBIU_DDRBWC1);
- D32(EBIU_DDRBWC2);
- D32(EBIU_DDRBWC3);
- D32(EBIU_DDRBWC4);
- D32(EBIU_DDRBWC5);
- D32(EBIU_DDRBWC6);
- D32(EBIU_DDRBWC7);
- D32(EBIU_DDRCTL0);
- D32(EBIU_DDRCTL1);
- D32(EBIU_DDRCTL2);
- D32(EBIU_DDRCTL3);
- D32(EBIU_DDRGC0);
- D32(EBIU_DDRGC1);
- D32(EBIU_DDRGC2);
- D32(EBIU_DDRGC3);
- D32(EBIU_DDRMCCL);
- D32(EBIU_DDRMCEN);
- D32(EBIU_DDRQUE);
- D32(EBIU_DDRTACT);
- D32(EBIU_ERRADD);
- D16(EBIU_ERRMST);
- D16(EBIU_RSTCTL);
-#endif
-
-#ifdef EMAC_ADDRHI
- parent = debugfs_create_dir("emac", top);
- D32(EMAC_ADDRHI);
- D32(EMAC_ADDRLO);
- D32(EMAC_FLC);
- D32(EMAC_HASHHI);
- D32(EMAC_HASHLO);
- D32(EMAC_MMC_CTL);
- D32(EMAC_MMC_RIRQE);
- D32(EMAC_MMC_RIRQS);
- D32(EMAC_MMC_TIRQE);
- D32(EMAC_MMC_TIRQS);
- D32(EMAC_OPMODE);
- D32(EMAC_RXC_ALIGN);
- D32(EMAC_RXC_ALLFRM);
- D32(EMAC_RXC_ALLOCT);
- D32(EMAC_RXC_BROAD);
- D32(EMAC_RXC_DMAOVF);
- D32(EMAC_RXC_EQ64);
- D32(EMAC_RXC_FCS);
- D32(EMAC_RXC_GE1024);
- D32(EMAC_RXC_LNERRI);
- D32(EMAC_RXC_LNERRO);
- D32(EMAC_RXC_LONG);
- D32(EMAC_RXC_LT1024);
- D32(EMAC_RXC_LT128);
- D32(EMAC_RXC_LT256);
- D32(EMAC_RXC_LT512);
- D32(EMAC_RXC_MACCTL);
- D32(EMAC_RXC_MULTI);
- D32(EMAC_RXC_OCTET);
- D32(EMAC_RXC_OK);
- D32(EMAC_RXC_OPCODE);
- D32(EMAC_RXC_PAUSE);
- D32(EMAC_RXC_SHORT);
- D32(EMAC_RXC_TYPED);
- D32(EMAC_RXC_UNICST);
- D32(EMAC_RX_IRQE);
- D32(EMAC_RX_STAT);
- D32(EMAC_RX_STKY);
- D32(EMAC_STAADD);
- D32(EMAC_STADAT);
- D32(EMAC_SYSCTL);
- D32(EMAC_SYSTAT);
- D32(EMAC_TXC_1COL);
- D32(EMAC_TXC_ABORT);
- D32(EMAC_TXC_ALLFRM);
- D32(EMAC_TXC_ALLOCT);
- D32(EMAC_TXC_BROAD);
- D32(EMAC_TXC_CRSERR);
- D32(EMAC_TXC_DEFER);
- D32(EMAC_TXC_DMAUND);
- D32(EMAC_TXC_EQ64);
- D32(EMAC_TXC_GE1024);
- D32(EMAC_TXC_GT1COL);
- D32(EMAC_TXC_LATECL);
- D32(EMAC_TXC_LT1024);
- D32(EMAC_TXC_LT128);
- D32(EMAC_TXC_LT256);
- D32(EMAC_TXC_LT512);
- D32(EMAC_TXC_MACCTL);
- D32(EMAC_TXC_MULTI);
- D32(EMAC_TXC_OCTET);
- D32(EMAC_TXC_OK);
- D32(EMAC_TXC_UNICST);
- D32(EMAC_TXC_XS_COL);
- D32(EMAC_TXC_XS_DFR);
- D32(EMAC_TX_IRQE);
- D32(EMAC_TX_STAT);
- D32(EMAC_TX_STKY);
- D32(EMAC_VLAN1);
- D32(EMAC_VLAN2);
- D32(EMAC_WKUP_CTL);
- D32(EMAC_WKUP_FFCMD);
- D32(EMAC_WKUP_FFCRC0);
- D32(EMAC_WKUP_FFCRC1);
- D32(EMAC_WKUP_FFMSK0);
- D32(EMAC_WKUP_FFMSK1);
- D32(EMAC_WKUP_FFMSK2);
- D32(EMAC_WKUP_FFMSK3);
- D32(EMAC_WKUP_FFOFF);
-# ifdef EMAC_PTP_ACCR
- D32(EMAC_PTP_ACCR);
- D32(EMAC_PTP_ADDEND);
- D32(EMAC_PTP_ALARMHI);
- D32(EMAC_PTP_ALARMLO);
- D16(EMAC_PTP_CTL);
- D32(EMAC_PTP_FOFF);
- D32(EMAC_PTP_FV1);
- D32(EMAC_PTP_FV2);
- D32(EMAC_PTP_FV3);
- D16(EMAC_PTP_ID_OFF);
- D32(EMAC_PTP_ID_SNAP);
- D16(EMAC_PTP_IE);
- D16(EMAC_PTP_ISTAT);
- D32(EMAC_PTP_OFFSET);
- D32(EMAC_PTP_PPS_PERIOD);
- D32(EMAC_PTP_PPS_STARTHI);
- D32(EMAC_PTP_PPS_STARTLO);
- D32(EMAC_PTP_RXSNAPHI);
- D32(EMAC_PTP_RXSNAPLO);
- D32(EMAC_PTP_TIMEHI);
- D32(EMAC_PTP_TIMELO);
- D32(EMAC_PTP_TXSNAPHI);
- D32(EMAC_PTP_TXSNAPLO);
-# endif
-#endif
-
-#if defined(EPPI0_STATUS) || defined(EPPI1_STATUS) || defined(EPPI2_STATUS)
- parent = debugfs_create_dir("eppi", top);
-# ifdef EPPI0_STATUS
- EPPI(0);
-# endif
-# ifdef EPPI1_STATUS
- EPPI(1);
-# endif
-# ifdef EPPI2_STATUS
- EPPI(2);
-# endif
-#endif
-
- parent = debugfs_create_dir("gptimer", top);
-#ifdef TIMER_ENABLE
- GPTIMER_GROUP(TIMER_ENABLE, -1);
-#endif
-#ifdef TIMER_ENABLE0
- GPTIMER_GROUP(TIMER_ENABLE0, 0);
-#endif
-#ifdef TIMER_ENABLE1
- GPTIMER_GROUP(TIMER_ENABLE1, 1);
-#endif
- /* XXX: Should convert BF561 MMR names */
-#ifdef TMRS4_DISABLE
- GPTIMER_GROUP(TMRS4_ENABLE, 0);
- GPTIMER_GROUP(TMRS8_ENABLE, 1);
-#endif
- GPTIMER(0);
- GPTIMER(1);
- GPTIMER(2);
-#ifdef TIMER3_CONFIG
- GPTIMER(3);
- GPTIMER(4);
- GPTIMER(5);
- GPTIMER(6);
- GPTIMER(7);
-#endif
-#ifdef TIMER8_CONFIG
- GPTIMER(8);
- GPTIMER(9);
- GPTIMER(10);
-#endif
-#ifdef TIMER11_CONFIG
- GPTIMER(11);
-#endif
-
-#ifdef HMDMA0_CONTROL
- parent = debugfs_create_dir("hmdma", top);
- HMDMA(0);
- HMDMA(1);
-#endif
-
-#ifdef HOST_CONTROL
- parent = debugfs_create_dir("hostdp", top);
- D16(HOST_CONTROL);
- D16(HOST_STATUS);
- D16(HOST_TIMEOUT);
-#endif
-
-#ifdef IMDMA_S0_CONFIG
- parent = debugfs_create_dir("imdma", top);
- IMDMA(0);
- IMDMA(1);
-#endif
-
-#ifdef KPAD_CTL
- parent = debugfs_create_dir("keypad", top);
- D16(KPAD_CTL);
- D16(KPAD_PRESCALE);
- D16(KPAD_MSEL);
- D16(KPAD_ROWCOL);
- D16(KPAD_STAT);
- D16(KPAD_SOFTEVAL);
-#endif
-
- parent = debugfs_create_dir("mdma", top);
- MDMA(0);
- MDMA(1);
-#ifdef MDMA_D2_CONFIG
- MDMA(2);
- MDMA(3);
-#endif
-
-#ifdef MXVR_CONFIG
- parent = debugfs_create_dir("mxvr", top);
- D16(MXVR_CONFIG);
-# ifdef MXVR_PLL_CTL_0
- D32(MXVR_PLL_CTL_0);
-# endif
- D32(MXVR_STATE_0);
- D32(MXVR_STATE_1);
- D32(MXVR_INT_STAT_0);
- D32(MXVR_INT_STAT_1);
- D32(MXVR_INT_EN_0);
- D32(MXVR_INT_EN_1);
- D16(MXVR_POSITION);
- D16(MXVR_MAX_POSITION);
- D16(MXVR_DELAY);
- D16(MXVR_MAX_DELAY);
- D32(MXVR_LADDR);
- D16(MXVR_GADDR);
- D32(MXVR_AADDR);
- D32(MXVR_ALLOC_0);
- D32(MXVR_ALLOC_1);
- D32(MXVR_ALLOC_2);
- D32(MXVR_ALLOC_3);
- D32(MXVR_ALLOC_4);
- D32(MXVR_ALLOC_5);
- D32(MXVR_ALLOC_6);
- D32(MXVR_ALLOC_7);
- D32(MXVR_ALLOC_8);
- D32(MXVR_ALLOC_9);
- D32(MXVR_ALLOC_10);
- D32(MXVR_ALLOC_11);
- D32(MXVR_ALLOC_12);
- D32(MXVR_ALLOC_13);
- D32(MXVR_ALLOC_14);
- D32(MXVR_SYNC_LCHAN_0);
- D32(MXVR_SYNC_LCHAN_1);
- D32(MXVR_SYNC_LCHAN_2);
- D32(MXVR_SYNC_LCHAN_3);
- D32(MXVR_SYNC_LCHAN_4);
- D32(MXVR_SYNC_LCHAN_5);
- D32(MXVR_SYNC_LCHAN_6);
- D32(MXVR_SYNC_LCHAN_7);
- D32(MXVR_DMA0_CONFIG);
- D32(MXVR_DMA0_START_ADDR);
- D16(MXVR_DMA0_COUNT);
- D32(MXVR_DMA0_CURR_ADDR);
- D16(MXVR_DMA0_CURR_COUNT);
- D32(MXVR_DMA1_CONFIG);
- D32(MXVR_DMA1_START_ADDR);
- D16(MXVR_DMA1_COUNT);
- D32(MXVR_DMA1_CURR_ADDR);
- D16(MXVR_DMA1_CURR_COUNT);
- D32(MXVR_DMA2_CONFIG);
- D32(MXVR_DMA2_START_ADDR);
- D16(MXVR_DMA2_COUNT);
- D32(MXVR_DMA2_CURR_ADDR);
- D16(MXVR_DMA2_CURR_COUNT);
- D32(MXVR_DMA3_CONFIG);
- D32(MXVR_DMA3_START_ADDR);
- D16(MXVR_DMA3_COUNT);
- D32(MXVR_DMA3_CURR_ADDR);
- D16(MXVR_DMA3_CURR_COUNT);
- D32(MXVR_DMA4_CONFIG);
- D32(MXVR_DMA4_START_ADDR);
- D16(MXVR_DMA4_COUNT);
- D32(MXVR_DMA4_CURR_ADDR);
- D16(MXVR_DMA4_CURR_COUNT);
- D32(MXVR_DMA5_CONFIG);
- D32(MXVR_DMA5_START_ADDR);
- D16(MXVR_DMA5_COUNT);
- D32(MXVR_DMA5_CURR_ADDR);
- D16(MXVR_DMA5_CURR_COUNT);
- D32(MXVR_DMA6_CONFIG);
- D32(MXVR_DMA6_START_ADDR);
- D16(MXVR_DMA6_COUNT);
- D32(MXVR_DMA6_CURR_ADDR);
- D16(MXVR_DMA6_CURR_COUNT);
- D32(MXVR_DMA7_CONFIG);
- D32(MXVR_DMA7_START_ADDR);
- D16(MXVR_DMA7_COUNT);
- D32(MXVR_DMA7_CURR_ADDR);
- D16(MXVR_DMA7_CURR_COUNT);
- D16(MXVR_AP_CTL);
- D32(MXVR_APRB_START_ADDR);
- D32(MXVR_APRB_CURR_ADDR);
- D32(MXVR_APTB_START_ADDR);
- D32(MXVR_APTB_CURR_ADDR);
- D32(MXVR_CM_CTL);
- D32(MXVR_CMRB_START_ADDR);
- D32(MXVR_CMRB_CURR_ADDR);
- D32(MXVR_CMTB_START_ADDR);
- D32(MXVR_CMTB_CURR_ADDR);
- D32(MXVR_RRDB_START_ADDR);
- D32(MXVR_RRDB_CURR_ADDR);
- D32(MXVR_PAT_DATA_0);
- D32(MXVR_PAT_EN_0);
- D32(MXVR_PAT_DATA_1);
- D32(MXVR_PAT_EN_1);
- D16(MXVR_FRAME_CNT_0);
- D16(MXVR_FRAME_CNT_1);
- D32(MXVR_ROUTING_0);
- D32(MXVR_ROUTING_1);
- D32(MXVR_ROUTING_2);
- D32(MXVR_ROUTING_3);
- D32(MXVR_ROUTING_4);
- D32(MXVR_ROUTING_5);
- D32(MXVR_ROUTING_6);
- D32(MXVR_ROUTING_7);
- D32(MXVR_ROUTING_8);
- D32(MXVR_ROUTING_9);
- D32(MXVR_ROUTING_10);
- D32(MXVR_ROUTING_11);
- D32(MXVR_ROUTING_12);
- D32(MXVR_ROUTING_13);
- D32(MXVR_ROUTING_14);
-# ifdef MXVR_PLL_CTL_1
- D32(MXVR_PLL_CTL_1);
-# endif
- D16(MXVR_BLOCK_CNT);
-# ifdef MXVR_CLK_CTL
- D32(MXVR_CLK_CTL);
-# endif
-# ifdef MXVR_CDRPLL_CTL
- D32(MXVR_CDRPLL_CTL);
-# endif
-# ifdef MXVR_FMPLL_CTL
- D32(MXVR_FMPLL_CTL);
-# endif
-# ifdef MXVR_PIN_CTL
- D16(MXVR_PIN_CTL);
-# endif
-# ifdef MXVR_SCLK_CNT
- D16(MXVR_SCLK_CNT);
-# endif
-#endif
-
-#ifdef NFC_ADDR
- parent = debugfs_create_dir("nfc", top);
- D_WO(NFC_ADDR, 16);
- D_WO(NFC_CMD, 16);
- D_RO(NFC_COUNT, 16);
- D16(NFC_CTL);
- D_WO(NFC_DATA_RD, 16);
- D_WO(NFC_DATA_WR, 16);
- D_RO(NFC_ECC0, 16);
- D_RO(NFC_ECC1, 16);
- D_RO(NFC_ECC2, 16);
- D_RO(NFC_ECC3, 16);
- D16(NFC_IRQMASK);
- D16(NFC_IRQSTAT);
- D_WO(NFC_PGCTL, 16);
- D_RO(NFC_READ, 16);
- D16(NFC_RST);
- D_RO(NFC_STAT, 16);
-#endif
-
-#ifdef OTP_CONTROL
- parent = debugfs_create_dir("otp", top);
- D16(OTP_CONTROL);
- D16(OTP_BEN);
- D16(OTP_STATUS);
- D32(OTP_TIMING);
- D32(OTP_DATA0);
- D32(OTP_DATA1);
- D32(OTP_DATA2);
- D32(OTP_DATA3);
-#endif
-
-#ifdef PINT0_MASK_SET
- parent = debugfs_create_dir("pint", top);
- PINT(0);
- PINT(1);
- PINT(2);
- PINT(3);
-#endif
-
-#ifdef PIXC_CTL
- parent = debugfs_create_dir("pixc", top);
- D16(PIXC_CTL);
- D16(PIXC_PPL);
- D16(PIXC_LPF);
- D16(PIXC_AHSTART);
- D16(PIXC_AHEND);
- D16(PIXC_AVSTART);
- D16(PIXC_AVEND);
- D16(PIXC_ATRANSP);
- D16(PIXC_BHSTART);
- D16(PIXC_BHEND);
- D16(PIXC_BVSTART);
- D16(PIXC_BVEND);
- D16(PIXC_BTRANSP);
- D16(PIXC_INTRSTAT);
- D32(PIXC_RYCON);
- D32(PIXC_GUCON);
- D32(PIXC_BVCON);
- D32(PIXC_CCBIAS);
- D32(PIXC_TC);
-#endif
-
- parent = debugfs_create_dir("pll", top);
- D16(PLL_CTL);
- D16(PLL_DIV);
- D16(PLL_LOCKCNT);
- D16(PLL_STAT);
- D16(VR_CTL);
- D32(CHIPID); /* it's part of this hardware block */
-
-#if defined(PPI_CONTROL) || defined(PPI0_CONTROL) || defined(PPI1_CONTROL)
- parent = debugfs_create_dir("ppi", top);
-# ifdef PPI_CONTROL
- bfin_debug_mmrs_ppi(parent, PPI_CONTROL, -1);
-# endif
-# ifdef PPI0_CONTROL
- PPI(0);
-# endif
-# ifdef PPI1_CONTROL
- PPI(1);
-# endif
-#endif
-
-#ifdef PWM_CTRL
- parent = debugfs_create_dir("pwm", top);
- D16(PWM_CTRL);
- D16(PWM_STAT);
- D16(PWM_TM);
- D16(PWM_DT);
- D16(PWM_GATE);
- D16(PWM_CHA);
- D16(PWM_CHB);
- D16(PWM_CHC);
- D16(PWM_SEG);
- D16(PWM_SYNCWT);
- D16(PWM_CHAL);
- D16(PWM_CHBL);
- D16(PWM_CHCL);
- D16(PWM_LSI);
- D16(PWM_STAT2);
-#endif
-
-#ifdef RSI_CONFIG
- parent = debugfs_create_dir("rsi", top);
- D32(RSI_ARGUMENT);
- D16(RSI_CEATA_CONTROL);
- D16(RSI_CLK_CONTROL);
- D16(RSI_COMMAND);
- D16(RSI_CONFIG);
- D16(RSI_DATA_CNT);
- D16(RSI_DATA_CONTROL);
- D16(RSI_DATA_LGTH);
- D32(RSI_DATA_TIMER);
- D16(RSI_EMASK);
- D16(RSI_ESTAT);
- D32(RSI_FIFO);
- D16(RSI_FIFO_CNT);
- D32(RSI_MASK0);
- D32(RSI_MASK1);
- D16(RSI_PID0);
- D16(RSI_PID1);
- D16(RSI_PID2);
- D16(RSI_PID3);
- D16(RSI_PID4);
- D16(RSI_PID5);
- D16(RSI_PID6);
- D16(RSI_PID7);
- D16(RSI_PWR_CONTROL);
- D16(RSI_RD_WAIT_EN);
- D32(RSI_RESPONSE0);
- D32(RSI_RESPONSE1);
- D32(RSI_RESPONSE2);
- D32(RSI_RESPONSE3);
- D16(RSI_RESP_CMD);
- D32(RSI_STATUS);
- D_WO(RSI_STATUSCL, 16);
-#endif
-
-#ifdef RTC_ALARM
- parent = debugfs_create_dir("rtc", top);
- D32(RTC_ALARM);
- D16(RTC_ICTL);
- D16(RTC_ISTAT);
- D16(RTC_PREN);
- D32(RTC_STAT);
- D16(RTC_SWCNT);
-#endif
-
-#ifdef SDH_CFG
- parent = debugfs_create_dir("sdh", top);
- D32(SDH_ARGUMENT);
- D16(SDH_CFG);
- D16(SDH_CLK_CTL);
- D16(SDH_COMMAND);
- D_RO(SDH_DATA_CNT, 16);
- D16(SDH_DATA_CTL);
- D16(SDH_DATA_LGTH);
- D32(SDH_DATA_TIMER);
- D16(SDH_E_MASK);
- D16(SDH_E_STATUS);
- D32(SDH_FIFO);
- D_RO(SDH_FIFO_CNT, 16);
- D32(SDH_MASK0);
- D32(SDH_MASK1);
- D_RO(SDH_PID0, 16);
- D_RO(SDH_PID1, 16);
- D_RO(SDH_PID2, 16);
- D_RO(SDH_PID3, 16);
- D_RO(SDH_PID4, 16);
- D_RO(SDH_PID5, 16);
- D_RO(SDH_PID6, 16);
- D_RO(SDH_PID7, 16);
- D16(SDH_PWR_CTL);
- D16(SDH_RD_WAIT_EN);
- D_RO(SDH_RESPONSE0, 32);
- D_RO(SDH_RESPONSE1, 32);
- D_RO(SDH_RESPONSE2, 32);
- D_RO(SDH_RESPONSE3, 32);
- D_RO(SDH_RESP_CMD, 16);
- D_RO(SDH_STATUS, 32);
- D_WO(SDH_STATUS_CLR, 16);
-#endif
-
-#ifdef SECURE_CONTROL
- parent = debugfs_create_dir("security", top);
- D16(SECURE_CONTROL);
- D16(SECURE_STATUS);
- D32(SECURE_SYSSWT);
-#endif
-
- parent = debugfs_create_dir("sic", top);
- D16(SWRST);
- D16(SYSCR);
- D16(SIC_RVECT);
- D32(SIC_IAR0);
- D32(SIC_IAR1);
- D32(SIC_IAR2);
-#ifdef SIC_IAR3
- D32(SIC_IAR3);
-#endif
-#ifdef SIC_IAR4
- D32(SIC_IAR4);
- D32(SIC_IAR5);
- D32(SIC_IAR6);
-#endif
-#ifdef SIC_IAR7
- D32(SIC_IAR7);
-#endif
-#ifdef SIC_IAR8
- D32(SIC_IAR8);
- D32(SIC_IAR9);
- D32(SIC_IAR10);
- D32(SIC_IAR11);
-#endif
-#ifdef SIC_IMASK
- D32(SIC_IMASK);
- D32(SIC_ISR);
- D32(SIC_IWR);
-#endif
-#ifdef SIC_IMASK0
- D32(SIC_IMASK0);
- D32(SIC_IMASK1);
- D32(SIC_ISR0);
- D32(SIC_ISR1);
- D32(SIC_IWR0);
- D32(SIC_IWR1);
-#endif
-#ifdef SIC_IMASK2
- D32(SIC_IMASK2);
- D32(SIC_ISR2);
- D32(SIC_IWR2);
-#endif
-#ifdef SICB_RVECT
- D16(SICB_SWRST);
- D16(SICB_SYSCR);
- D16(SICB_RVECT);
- D32(SICB_IAR0);
- D32(SICB_IAR1);
- D32(SICB_IAR2);
- D32(SICB_IAR3);
- D32(SICB_IAR4);
- D32(SICB_IAR5);
- D32(SICB_IAR6);
- D32(SICB_IAR7);
- D32(SICB_IMASK0);
- D32(SICB_IMASK1);
- D32(SICB_ISR0);
- D32(SICB_ISR1);
- D32(SICB_IWR0);
- D32(SICB_IWR1);
-#endif
-
- parent = debugfs_create_dir("spi", top);
-#ifdef SPI0_REGBASE
- SPI(0);
-#endif
-#ifdef SPI1_REGBASE
- SPI(1);
-#endif
-#ifdef SPI2_REGBASE
- SPI(2);
-#endif
-
- parent = debugfs_create_dir("sport", top);
-#ifdef SPORT0_STAT
- SPORT(0);
-#endif
-#ifdef SPORT1_STAT
- SPORT(1);
-#endif
-#ifdef SPORT2_STAT
- SPORT(2);
-#endif
-#ifdef SPORT3_STAT
- SPORT(3);
-#endif
-
-#if defined(TWI_CLKDIV) || defined(TWI0_CLKDIV) || defined(TWI1_CLKDIV)
- parent = debugfs_create_dir("twi", top);
-# ifdef TWI_CLKDIV
- bfin_debug_mmrs_twi(parent, TWI_CLKDIV, -1);
-# endif
-# ifdef TWI0_CLKDIV
- TWI(0);
-# endif
-# ifdef TWI1_CLKDIV
- TWI(1);
-# endif
-#endif
-
- parent = debugfs_create_dir("uart", top);
-#ifdef BFIN_UART_DLL
- bfin_debug_mmrs_uart(parent, BFIN_UART_DLL, -1);
-#endif
-#ifdef UART0_DLL
- UART(0);
-#endif
-#ifdef UART1_DLL
- UART(1);
-#endif
-#ifdef UART2_DLL
- UART(2);
-#endif
-#ifdef UART3_DLL
- UART(3);
-#endif
-
-#ifdef USB_FADDR
- parent = debugfs_create_dir("usb", top);
- D16(USB_FADDR);
- D16(USB_POWER);
- D16(USB_INTRTX);
- D16(USB_INTRRX);
- D16(USB_INTRTXE);
- D16(USB_INTRRXE);
- D16(USB_INTRUSB);
- D16(USB_INTRUSBE);
- D16(USB_FRAME);
- D16(USB_INDEX);
- D16(USB_TESTMODE);
- D16(USB_GLOBINTR);
- D16(USB_GLOBAL_CTL);
- D16(USB_TX_MAX_PACKET);
- D16(USB_CSR0);
- D16(USB_TXCSR);
- D16(USB_RX_MAX_PACKET);
- D16(USB_RXCSR);
- D16(USB_COUNT0);
- D16(USB_RXCOUNT);
- D16(USB_TXTYPE);
- D16(USB_NAKLIMIT0);
- D16(USB_TXINTERVAL);
- D16(USB_RXTYPE);
- D16(USB_RXINTERVAL);
- D16(USB_TXCOUNT);
- D16(USB_EP0_FIFO);
- D16(USB_EP1_FIFO);
- D16(USB_EP2_FIFO);
- D16(USB_EP3_FIFO);
- D16(USB_EP4_FIFO);
- D16(USB_EP5_FIFO);
- D16(USB_EP6_FIFO);
- D16(USB_EP7_FIFO);
- D16(USB_OTG_DEV_CTL);
- D16(USB_OTG_VBUS_IRQ);
- D16(USB_OTG_VBUS_MASK);
- D16(USB_LINKINFO);
- D16(USB_VPLEN);
- D16(USB_HS_EOF1);
- D16(USB_FS_EOF1);
- D16(USB_LS_EOF1);
- D16(USB_APHY_CNTRL);
- D16(USB_APHY_CALIB);
- D16(USB_APHY_CNTRL2);
- D16(USB_PLLOSC_CTRL);
- D16(USB_SRP_CLKDIV);
- D16(USB_EP_NI0_TXMAXP);
- D16(USB_EP_NI0_TXCSR);
- D16(USB_EP_NI0_RXMAXP);
- D16(USB_EP_NI0_RXCSR);
- D16(USB_EP_NI0_RXCOUNT);
- D16(USB_EP_NI0_TXTYPE);
- D16(USB_EP_NI0_TXINTERVAL);
- D16(USB_EP_NI0_RXTYPE);
- D16(USB_EP_NI0_RXINTERVAL);
- D16(USB_EP_NI0_TXCOUNT);
- D16(USB_EP_NI1_TXMAXP);
- D16(USB_EP_NI1_TXCSR);
- D16(USB_EP_NI1_RXMAXP);
- D16(USB_EP_NI1_RXCSR);
- D16(USB_EP_NI1_RXCOUNT);
- D16(USB_EP_NI1_TXTYPE);
- D16(USB_EP_NI1_TXINTERVAL);
- D16(USB_EP_NI1_RXTYPE);
- D16(USB_EP_NI1_RXINTERVAL);
- D16(USB_EP_NI1_TXCOUNT);
- D16(USB_EP_NI2_TXMAXP);
- D16(USB_EP_NI2_TXCSR);
- D16(USB_EP_NI2_RXMAXP);
- D16(USB_EP_NI2_RXCSR);
- D16(USB_EP_NI2_RXCOUNT);
- D16(USB_EP_NI2_TXTYPE);
- D16(USB_EP_NI2_TXINTERVAL);
- D16(USB_EP_NI2_RXTYPE);
- D16(USB_EP_NI2_RXINTERVAL);
- D16(USB_EP_NI2_TXCOUNT);
- D16(USB_EP_NI3_TXMAXP);
- D16(USB_EP_NI3_TXCSR);
- D16(USB_EP_NI3_RXMAXP);
- D16(USB_EP_NI3_RXCSR);
- D16(USB_EP_NI3_RXCOUNT);
- D16(USB_EP_NI3_TXTYPE);
- D16(USB_EP_NI3_TXINTERVAL);
- D16(USB_EP_NI3_RXTYPE);
- D16(USB_EP_NI3_RXINTERVAL);
- D16(USB_EP_NI3_TXCOUNT);
- D16(USB_EP_NI4_TXMAXP);
- D16(USB_EP_NI4_TXCSR);
- D16(USB_EP_NI4_RXMAXP);
- D16(USB_EP_NI4_RXCSR);
- D16(USB_EP_NI4_RXCOUNT);
- D16(USB_EP_NI4_TXTYPE);
- D16(USB_EP_NI4_TXINTERVAL);
- D16(USB_EP_NI4_RXTYPE);
- D16(USB_EP_NI4_RXINTERVAL);
- D16(USB_EP_NI4_TXCOUNT);
- D16(USB_EP_NI5_TXMAXP);
- D16(USB_EP_NI5_TXCSR);
- D16(USB_EP_NI5_RXMAXP);
- D16(USB_EP_NI5_RXCSR);
- D16(USB_EP_NI5_RXCOUNT);
- D16(USB_EP_NI5_TXTYPE);
- D16(USB_EP_NI5_TXINTERVAL);
- D16(USB_EP_NI5_RXTYPE);
- D16(USB_EP_NI5_RXINTERVAL);
- D16(USB_EP_NI5_TXCOUNT);
- D16(USB_EP_NI6_TXMAXP);
- D16(USB_EP_NI6_TXCSR);
- D16(USB_EP_NI6_RXMAXP);
- D16(USB_EP_NI6_RXCSR);
- D16(USB_EP_NI6_RXCOUNT);
- D16(USB_EP_NI6_TXTYPE);
- D16(USB_EP_NI6_TXINTERVAL);
- D16(USB_EP_NI6_RXTYPE);
- D16(USB_EP_NI6_RXINTERVAL);
- D16(USB_EP_NI6_TXCOUNT);
- D16(USB_EP_NI7_TXMAXP);
- D16(USB_EP_NI7_TXCSR);
- D16(USB_EP_NI7_RXMAXP);
- D16(USB_EP_NI7_RXCSR);
- D16(USB_EP_NI7_RXCOUNT);
- D16(USB_EP_NI7_TXTYPE);
- D16(USB_EP_NI7_TXINTERVAL);
- D16(USB_EP_NI7_RXTYPE);
- D16(USB_EP_NI7_RXINTERVAL);
- D16(USB_EP_NI7_TXCOUNT);
- D16(USB_DMA_INTERRUPT);
- D16(USB_DMA0CONTROL);
- D16(USB_DMA0ADDRLOW);
- D16(USB_DMA0ADDRHIGH);
- D16(USB_DMA0COUNTLOW);
- D16(USB_DMA0COUNTHIGH);
- D16(USB_DMA1CONTROL);
- D16(USB_DMA1ADDRLOW);
- D16(USB_DMA1ADDRHIGH);
- D16(USB_DMA1COUNTLOW);
- D16(USB_DMA1COUNTHIGH);
- D16(USB_DMA2CONTROL);
- D16(USB_DMA2ADDRLOW);
- D16(USB_DMA2ADDRHIGH);
- D16(USB_DMA2COUNTLOW);
- D16(USB_DMA2COUNTHIGH);
- D16(USB_DMA3CONTROL);
- D16(USB_DMA3ADDRLOW);
- D16(USB_DMA3ADDRHIGH);
- D16(USB_DMA3COUNTLOW);
- D16(USB_DMA3COUNTHIGH);
- D16(USB_DMA4CONTROL);
- D16(USB_DMA4ADDRLOW);
- D16(USB_DMA4ADDRHIGH);
- D16(USB_DMA4COUNTLOW);
- D16(USB_DMA4COUNTHIGH);
- D16(USB_DMA5CONTROL);
- D16(USB_DMA5ADDRLOW);
- D16(USB_DMA5ADDRHIGH);
- D16(USB_DMA5COUNTLOW);
- D16(USB_DMA5COUNTHIGH);
- D16(USB_DMA6CONTROL);
- D16(USB_DMA6ADDRLOW);
- D16(USB_DMA6ADDRHIGH);
- D16(USB_DMA6COUNTLOW);
- D16(USB_DMA6COUNTHIGH);
- D16(USB_DMA7CONTROL);
- D16(USB_DMA7ADDRLOW);
- D16(USB_DMA7ADDRHIGH);
- D16(USB_DMA7COUNTLOW);
- D16(USB_DMA7COUNTHIGH);
-#endif
-
-#ifdef WDOG_CNT
- parent = debugfs_create_dir("watchdog", top);
- D32(WDOG_CNT);
- D16(WDOG_CTL);
- D32(WDOG_STAT);
-#endif
-#ifdef WDOGA_CNT
- parent = debugfs_create_dir("watchdog", top);
- D32(WDOGA_CNT);
- D16(WDOGA_CTL);
- D32(WDOGA_STAT);
- D32(WDOGB_CNT);
- D16(WDOGB_CTL);
- D32(WDOGB_STAT);
-#endif
-
- /* BF533 glue */
-#ifdef FIO_FLAG_D
-#define PORTFIO FIO_FLAG_D
-#endif
- /* BF561 glue */
-#ifdef FIO0_FLAG_D
-#define PORTFIO FIO0_FLAG_D
-#endif
-#ifdef FIO1_FLAG_D
-#define PORTGIO FIO1_FLAG_D
-#endif
-#ifdef FIO2_FLAG_D
-#define PORTHIO FIO2_FLAG_D
-#endif
- parent = debugfs_create_dir("port", top);
-#ifdef PORTFIO
- PORT(PORTFIO, 'F');
-#endif
-#ifdef PORTGIO
- PORT(PORTGIO, 'G');
-#endif
-#ifdef PORTHIO
- PORT(PORTHIO, 'H');
-#endif
-
-#ifdef __ADSPBF51x__
- D16(PORTF_FER);
- D16(PORTF_DRIVE);
- D16(PORTF_HYSTERESIS);
- D16(PORTF_MUX);
-
- D16(PORTG_FER);
- D16(PORTG_DRIVE);
- D16(PORTG_HYSTERESIS);
- D16(PORTG_MUX);
-
- D16(PORTH_FER);
- D16(PORTH_DRIVE);
- D16(PORTH_HYSTERESIS);
- D16(PORTH_MUX);
-
- D16(MISCPORT_DRIVE);
- D16(MISCPORT_HYSTERESIS);
-#endif /* BF51x */
-
-#ifdef __ADSPBF52x__
- D16(PORTF_FER);
- D16(PORTF_DRIVE);
- D16(PORTF_HYSTERESIS);
- D16(PORTF_MUX);
- D16(PORTF_SLEW);
-
- D16(PORTG_FER);
- D16(PORTG_DRIVE);
- D16(PORTG_HYSTERESIS);
- D16(PORTG_MUX);
- D16(PORTG_SLEW);
-
- D16(PORTH_FER);
- D16(PORTH_DRIVE);
- D16(PORTH_HYSTERESIS);
- D16(PORTH_MUX);
- D16(PORTH_SLEW);
-
- D16(MISCPORT_DRIVE);
- D16(MISCPORT_HYSTERESIS);
- D16(MISCPORT_SLEW);
-#endif /* BF52x */
-
-#ifdef BF537_FAMILY
- D16(PORTF_FER);
- D16(PORTG_FER);
- D16(PORTH_FER);
- D16(PORT_MUX);
-#endif /* BF534 BF536 BF537 */
-
-#ifdef BF538_FAMILY
- D16(PORTCIO_FER);
- D16(PORTCIO);
- D16(PORTCIO_CLEAR);
- D16(PORTCIO_SET);
- D16(PORTCIO_TOGGLE);
- D16(PORTCIO_DIR);
- D16(PORTCIO_INEN);
-
- D16(PORTDIO);
- D16(PORTDIO_CLEAR);
- D16(PORTDIO_DIR);
- D16(PORTDIO_FER);
- D16(PORTDIO_INEN);
- D16(PORTDIO_SET);
- D16(PORTDIO_TOGGLE);
-
- D16(PORTEIO);
- D16(PORTEIO_CLEAR);
- D16(PORTEIO_DIR);
- D16(PORTEIO_FER);
- D16(PORTEIO_INEN);
- D16(PORTEIO_SET);
- D16(PORTEIO_TOGGLE);
-#endif /* BF538 BF539 */
-
-#ifdef __ADSPBF54x__
- {
- int num;
- unsigned long base;
-
- base = PORTA_FER;
- for (num = 0; num < 10; ++num) {
- PORT(base, num);
- base += sizeof(struct bfin_gpio_regs);
- }
-
- }
-#endif /* BF54x */
-#endif /* CONFIG_BF60x */
- debug_mmrs_dentry = top;
-
- return 0;
-}
-module_init(bfin_debug_mmrs_init);
-
-static void __exit bfin_debug_mmrs_exit(void)
-{
- debugfs_remove_recursive(debug_mmrs_dentry);
-}
-module_exit(bfin_debug_mmrs_exit);
-
-MODULE_LICENSE("GPL");
+++ /dev/null
-/*
- * Dynamic DMA mapping support
- *
- * Copyright 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <linux/types.h>
-#include <linux/gfp.h>
-#include <linux/string.h>
-#include <linux/spinlock.h>
-#include <linux/dma-mapping.h>
-#include <linux/scatterlist.h>
-#include <linux/export.h>
-#include <linux/bitmap.h>
-
-static spinlock_t dma_page_lock;
-static unsigned long *dma_page;
-static unsigned int dma_pages;
-static unsigned long dma_base;
-static unsigned long dma_size;
-static unsigned int dma_initialized;
-
-static void dma_alloc_init(unsigned long start, unsigned long end)
-{
- spin_lock_init(&dma_page_lock);
- dma_initialized = 0;
-
- dma_page = (unsigned long *)__get_free_page(GFP_KERNEL);
- memset(dma_page, 0, PAGE_SIZE);
- dma_base = PAGE_ALIGN(start);
- dma_size = PAGE_ALIGN(end) - PAGE_ALIGN(start);
- dma_pages = dma_size >> PAGE_SHIFT;
- memset((void *)dma_base, 0, DMA_UNCACHED_REGION);
- dma_initialized = 1;
-
- printk(KERN_INFO "%s: dma_page @ 0x%p - %d pages at 0x%08lx\n", __func__,
- dma_page, dma_pages, dma_base);
-}
-
-static inline unsigned int get_pages(size_t size)
-{
- return ((size - 1) >> PAGE_SHIFT) + 1;
-}
-
-static unsigned long __alloc_dma_pages(unsigned int pages)
-{
- unsigned long ret = 0, flags;
- unsigned long start;
-
- if (dma_initialized == 0)
- dma_alloc_init(_ramend - DMA_UNCACHED_REGION, _ramend);
-
- spin_lock_irqsave(&dma_page_lock, flags);
-
- start = bitmap_find_next_zero_area(dma_page, dma_pages, 0, pages, 0);
- if (start < dma_pages) {
- ret = dma_base + (start << PAGE_SHIFT);
- bitmap_set(dma_page, start, pages);
- }
- spin_unlock_irqrestore(&dma_page_lock, flags);
- return ret;
-}
-
-static void __free_dma_pages(unsigned long addr, unsigned int pages)
-{
- unsigned long page = (addr - dma_base) >> PAGE_SHIFT;
- unsigned long flags;
-
- if ((page + pages) > dma_pages) {
- printk(KERN_ERR "%s: freeing outside range.\n", __func__);
- BUG();
- }
-
- spin_lock_irqsave(&dma_page_lock, flags);
- bitmap_clear(dma_page, page, pages);
- spin_unlock_irqrestore(&dma_page_lock, flags);
-}
-
-static void *bfin_dma_alloc(struct device *dev, size_t size,
- dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs)
-{
- void *ret;
-
- ret = (void *)__alloc_dma_pages(get_pages(size));
-
- if (ret) {
- memset(ret, 0, size);
- *dma_handle = virt_to_phys(ret);
- }
-
- return ret;
-}
-
-static void bfin_dma_free(struct device *dev, size_t size, void *vaddr,
- dma_addr_t dma_handle, unsigned long attrs)
-{
- __free_dma_pages((unsigned long)vaddr, get_pages(size));
-}
-
-/*
- * Streaming DMA mappings
- */
-void __dma_sync(dma_addr_t addr, size_t size,
- enum dma_data_direction dir)
-{
- __dma_sync_inline(addr, size, dir);
-}
-EXPORT_SYMBOL(__dma_sync);
-
-static int bfin_dma_map_sg(struct device *dev, struct scatterlist *sg_list,
- int nents, enum dma_data_direction direction,
- unsigned long attrs)
-{
- struct scatterlist *sg;
- int i;
-
- for_each_sg(sg_list, sg, nents, i) {
- sg->dma_address = (dma_addr_t) sg_virt(sg);
-
- if (attrs & DMA_ATTR_SKIP_CPU_SYNC)
- continue;
-
- __dma_sync(sg_dma_address(sg), sg_dma_len(sg), direction);
- }
-
- return nents;
-}
-
-static void bfin_dma_sync_sg_for_device(struct device *dev,
- struct scatterlist *sg_list, int nelems,
- enum dma_data_direction direction)
-{
- struct scatterlist *sg;
- int i;
-
- for_each_sg(sg_list, sg, nelems, i) {
- sg->dma_address = (dma_addr_t) sg_virt(sg);
- __dma_sync(sg_dma_address(sg), sg_dma_len(sg), direction);
- }
-}
-
-static dma_addr_t bfin_dma_map_page(struct device *dev, struct page *page,
- unsigned long offset, size_t size, enum dma_data_direction dir,
- unsigned long attrs)
-{
- dma_addr_t handle = (dma_addr_t)(page_address(page) + offset);
-
- if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC))
- _dma_sync(handle, size, dir);
-
- return handle;
-}
-
-static inline void bfin_dma_sync_single_for_device(struct device *dev,
- dma_addr_t handle, size_t size, enum dma_data_direction dir)
-{
- _dma_sync(handle, size, dir);
-}
-
-const struct dma_map_ops bfin_dma_ops = {
- .alloc = bfin_dma_alloc,
- .free = bfin_dma_free,
-
- .map_page = bfin_dma_map_page,
- .map_sg = bfin_dma_map_sg,
-
- .sync_single_for_device = bfin_dma_sync_single_for_device,
- .sync_sg_for_device = bfin_dma_sync_sg_for_device,
-};
-EXPORT_SYMBOL(bfin_dma_ops);
+++ /dev/null
-/* Provide basic stack dumping functions
- *
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <linux/kernel.h>
-#include <linux/thread_info.h>
-#include <linux/mm.h>
-#include <linux/uaccess.h>
-#include <linux/module.h>
-#include <linux/sched/debug.h>
-
-#include <asm/trace.h>
-
-/*
- * Checks to see if the address pointed to is either a
- * 16-bit CALL instruction, or a 32-bit CALL instruction
- */
-static bool is_bfin_call(unsigned short *addr)
-{
- unsigned int opcode;
-
- if (!get_instruction(&opcode, addr))
- return false;
-
- if ((opcode >= 0x0060 && opcode <= 0x0067) ||
- (opcode >= 0x0070 && opcode <= 0x0077) ||
- (opcode >= 0xE3000000 && opcode <= 0xE3FFFFFF))
- return true;
-
- return false;
-
-}
-
-void show_stack(struct task_struct *task, unsigned long *stack)
-{
-#ifdef CONFIG_PRINTK
- unsigned int *addr, *endstack, *fp = 0, *frame;
- unsigned short *ins_addr;
- char buf[150];
- unsigned int i, j, ret_addr, frame_no = 0;
-
- /*
- * If we have been passed a specific stack, use that one otherwise
- * if we have been passed a task structure, use that, otherwise
- * use the stack of where the variable "stack" exists
- */
-
- if (stack == NULL) {
- if (task) {
- /* We know this is a kernel stack, so this is the start/end */
- stack = (unsigned long *)task->thread.ksp;
- endstack = (unsigned int *)(((unsigned int)(stack) & ~(THREAD_SIZE - 1)) + THREAD_SIZE);
- } else {
- /* print out the existing stack info */
- stack = (unsigned long *)&stack;
- endstack = (unsigned int *)PAGE_ALIGN((unsigned int)stack);
- }
- } else
- endstack = (unsigned int *)PAGE_ALIGN((unsigned int)stack);
-
- printk(KERN_NOTICE "Stack info:\n");
- decode_address(buf, (unsigned int)stack);
- printk(KERN_NOTICE " SP: [0x%p] %s\n", stack, buf);
-
- if (!access_ok(VERIFY_READ, stack, (unsigned int)endstack - (unsigned int)stack)) {
- printk(KERN_NOTICE "Invalid stack pointer\n");
- return;
- }
-
- /* First thing is to look for a frame pointer */
- for (addr = (unsigned int *)((unsigned int)stack & ~0xF); addr < endstack; addr++) {
- if (*addr & 0x1)
- continue;
- ins_addr = (unsigned short *)*addr;
- ins_addr--;
- if (is_bfin_call(ins_addr))
- fp = addr - 1;
-
- if (fp) {
- /* Let's check to see if it is a frame pointer */
- while (fp >= (addr - 1) && fp < endstack
- && fp && ((unsigned int) fp & 0x3) == 0)
- fp = (unsigned int *)*fp;
- if (fp == 0 || fp == endstack) {
- fp = addr - 1;
- break;
- }
- fp = 0;
- }
- }
- if (fp) {
- frame = fp;
- printk(KERN_NOTICE " FP: (0x%p)\n", fp);
- } else
- frame = 0;
-
- /*
- * Now that we think we know where things are, we
- * walk the stack again, this time printing things out
- * incase there is no frame pointer, we still look for
- * valid return addresses
- */
-
- /* First time print out data, next time, print out symbols */
- for (j = 0; j <= 1; j++) {
- if (j)
- printk(KERN_NOTICE "Return addresses in stack:\n");
- else
- printk(KERN_NOTICE " Memory from 0x%08lx to %p", ((long unsigned int)stack & ~0xF), endstack);
-
- fp = frame;
- frame_no = 0;
-
- for (addr = (unsigned int *)((unsigned int)stack & ~0xF), i = 0;
- addr < endstack; addr++, i++) {
-
- ret_addr = 0;
- if (!j && i % 8 == 0)
- printk(KERN_NOTICE "%p:", addr);
-
- /* if it is an odd address, or zero, just skip it */
- if (*addr & 0x1 || !*addr)
- goto print;
-
- ins_addr = (unsigned short *)*addr;
-
- /* Go back one instruction, and see if it is a CALL */
- ins_addr--;
- ret_addr = is_bfin_call(ins_addr);
- print:
- if (!j && stack == (unsigned long *)addr)
- printk("[%08x]", *addr);
- else if (ret_addr)
- if (j) {
- decode_address(buf, (unsigned int)*addr);
- if (frame == addr) {
- printk(KERN_NOTICE " frame %2i : %s\n", frame_no, buf);
- continue;
- }
- printk(KERN_NOTICE " address : %s\n", buf);
- } else
- printk("<%08x>", *addr);
- else if (fp == addr) {
- if (j)
- frame = addr+1;
- else
- printk("(%08x)", *addr);
-
- fp = (unsigned int *)*addr;
- frame_no++;
-
- } else if (!j)
- printk(" %08x ", *addr);
- }
- if (!j)
- printk("\n");
- }
-#endif
-}
-EXPORT_SYMBOL(show_stack);
-
-void dump_stack(void)
-{
- unsigned long stack;
-#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON
- int tflags;
-#endif
- trace_buffer_save(tflags);
- dump_bfin_trace_buffer();
- dump_stack_print_info(KERN_DEFAULT);
- show_stack(current, &stack);
- trace_buffer_restore(tflags);
-}
-EXPORT_SYMBOL(dump_stack);
+++ /dev/null
-/*
- * allow a console to be used for early printk
- * derived from arch/x86/kernel/early_printk.c
- *
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2
- */
-
-#include <linux/kernel.h>
-#include <linux/sched/debug.h>
-#include <linux/init.h>
-#include <linux/serial_core.h>
-#include <linux/console.h>
-#include <linux/string.h>
-#include <linux/reboot.h>
-#include <asm/blackfin.h>
-#include <asm/irq_handler.h>
-#include <asm/early_printk.h>
-
-#ifdef CONFIG_SERIAL_BFIN
-extern struct console *bfin_earlyserial_init(unsigned int port,
- unsigned int cflag);
-#endif
-#ifdef CONFIG_BFIN_JTAG_COMM
-extern struct console *bfin_jc_early_init(void);
-#endif
-
-/* Default console */
-#define DEFAULT_PORT 0
-#define DEFAULT_CFLAG CS8|B57600
-
-/* Default console for early crashes */
-#define DEFAULT_EARLY_PORT "serial,uart0,57600"
-
-#ifdef CONFIG_SERIAL_CORE
-/* What should get here is "0,57600" */
-static struct console * __init earlyserial_init(char *buf)
-{
- int baud, bit;
- char parity;
- unsigned int serial_port = DEFAULT_PORT;
- unsigned int cflag = DEFAULT_CFLAG;
-
- serial_port = simple_strtoul(buf, &buf, 10);
- buf++;
-
- cflag = 0;
- baud = simple_strtoul(buf, &buf, 10);
- switch (baud) {
- case 1200:
- cflag |= B1200;
- break;
- case 2400:
- cflag |= B2400;
- break;
- case 4800:
- cflag |= B4800;
- break;
- case 9600:
- cflag |= B9600;
- break;
- case 19200:
- cflag |= B19200;
- break;
- case 38400:
- cflag |= B38400;
- break;
- case 115200:
- cflag |= B115200;
- break;
- default:
- cflag |= B57600;
- }
-
- parity = buf[0];
- buf++;
- switch (parity) {
- case 'e':
- cflag |= PARENB;
- break;
- case 'o':
- cflag |= PARODD;
- break;
- }
-
- bit = simple_strtoul(buf, &buf, 10);
- switch (bit) {
- case 5:
- cflag |= CS5;
- break;
- case 6:
- cflag |= CS6;
- break;
- case 7:
- cflag |= CS7;
- break;
- default:
- cflag |= CS8;
- }
-
-#ifdef CONFIG_SERIAL_BFIN
- return bfin_earlyserial_init(serial_port, cflag);
-#else
- return NULL;
-#endif
-
-}
-#endif
-
-int __init setup_early_printk(char *buf)
-{
-
- /* Crashing in here would be really bad, so check both the var
- and the pointer before we start using it
- */
- if (!buf)
- return 0;
-
- if (!*buf)
- return 0;
-
- if (early_console != NULL)
- return 0;
-
-#ifdef CONFIG_SERIAL_BFIN
- /* Check for Blackfin Serial */
- if (!strncmp(buf, "serial,uart", 11)) {
- buf += 11;
- early_console = earlyserial_init(buf);
- }
-#endif
-
-#ifdef CONFIG_BFIN_JTAG_COMM
- /* Check for Blackfin JTAG */
- if (!strncmp(buf, "jtag", 4)) {
- buf += 4;
- early_console = bfin_jc_early_init();
- }
-#endif
-
-#ifdef CONFIG_FB
- /* TODO: add framebuffer console support */
-#endif
-
- if (likely(early_console)) {
- early_console->flags |= CON_BOOT;
-
- register_console(early_console);
- printk(KERN_INFO "early printk enabled on %s%d\n",
- early_console->name,
- early_console->index);
- }
-
- return 0;
-}
-
-/*
- * Set up a temporary Event Vector Table, so if something bad happens before
- * the kernel is fully started, it doesn't vector off into somewhere we don't
- * know
- */
-
-asmlinkage void __init init_early_exception_vectors(void)
-{
- u32 evt;
- SSYNC();
-
- /*
- * This starts up the shadow buffer, incase anything crashes before
- * setup arch
- */
- mark_shadow_error();
- early_shadow_puts(linux_banner);
- early_shadow_stamp();
-
- if (CPUID != bfin_cpuid()) {
- early_shadow_puts("Running on wrong machine type, expected");
- early_shadow_reg(CPUID, 16);
- early_shadow_puts(", but running on");
- early_shadow_reg(bfin_cpuid(), 16);
- early_shadow_puts("\n");
- }
-
- /* cannot program in software:
- * evt0 - emulation (jtag)
- * evt1 - reset
- */
- for (evt = EVT2; evt <= EVT15; evt += 4)
- bfin_write32(evt, early_trap);
- CSYNC();
-
- /* Set all the return from interrupt, exception, NMI to a known place
- * so if we do a RETI, RETX or RETN by mistake - we go somewhere known
- * Note - don't change RETS - we are in a subroutine, or
- * RETE - since it might screw up if emulator is attached
- */
- asm("\tRETI = %0; RETX = %0; RETN = %0;\n"
- : : "p"(early_trap));
-
-}
-
-__attribute__((__noreturn__))
-asmlinkage void __init early_trap_c(struct pt_regs *fp, void *retaddr)
-{
- /* This can happen before the uart is initialized, so initialize
- * the UART now (but only if we are running on the processor we think
- * we are compiled for - otherwise we write to MMRs that don't exist,
- * and cause other problems. Nothing comes out the UART, but it does
- * end up in the __buf_log.
- */
- if (likely(early_console == NULL) && CPUID == bfin_cpuid())
- setup_early_printk(DEFAULT_EARLY_PORT);
-
- if (!shadow_console_enabled()) {
- /* crap - we crashed before setup_arch() */
- early_shadow_puts("panic before setup_arch\n");
- early_shadow_puts("IPEND:");
- early_shadow_reg(fp->ipend, 16);
- if (fp->seqstat & SEQSTAT_EXCAUSE) {
- early_shadow_puts("\nEXCAUSE:");
- early_shadow_reg(fp->seqstat & SEQSTAT_EXCAUSE, 8);
- }
- if (fp->seqstat & SEQSTAT_HWERRCAUSE) {
- early_shadow_puts("\nHWERRCAUSE:");
- early_shadow_reg(
- (fp->seqstat & SEQSTAT_HWERRCAUSE) >> 14, 8);
- }
- early_shadow_puts("\nErr @");
- if (fp->ipend & EVT_EVX)
- early_shadow_reg(fp->retx, 32);
- else
- early_shadow_reg(fp->pc, 32);
-#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON
- early_shadow_puts("\nTrace:");
- if (likely(bfin_read_TBUFSTAT() & TBUFCNT)) {
- while (bfin_read_TBUFSTAT() & TBUFCNT) {
- early_shadow_puts("\nT :");
- early_shadow_reg(bfin_read_TBUF(), 32);
- early_shadow_puts("\n S :");
- early_shadow_reg(bfin_read_TBUF(), 32);
- }
- }
-#endif
- early_shadow_puts("\nUse bfin-elf-addr2line to determine "
- "function names\n");
- /*
- * We should panic(), but we can't - since panic calls printk,
- * and printk uses memcpy.
- * we want to reboot, but if the machine type is different,
- * can't due to machine specific reboot sequences
- */
- if (CPUID == bfin_cpuid()) {
- early_shadow_puts("Trying to restart\n");
- machine_restart("");
- }
-
- early_shadow_puts("Halting, since it is not safe to restart\n");
- while (1)
- asm volatile ("EMUEXCPT; IDLE;\n");
-
- } else {
- printk(KERN_EMERG "Early panic\n");
- show_regs(fp);
- dump_bfin_trace_buffer();
- }
-
- panic("Died early");
-}
-
-early_param("earlyprintk", setup_early_printk);
+++ /dev/null
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <linux/linkage.h>
-#include <asm/thread_info.h>
-#include <asm/errno.h>
-#include <asm/blackfin.h>
-#include <asm/asm-offsets.h>
-
-#include <asm/context.S>
-
-#ifdef CONFIG_EXCPT_IRQ_SYSC_L1
-.section .l1.text
-#else
-.text
-#endif
-
-ENTRY(_ret_from_fork)
-#ifdef CONFIG_IPIPE
- /*
- * Hw IRQs are off on entry, and we don't want the scheduling tail
- * code to starve high priority domains from interrupts while it
- * runs. Therefore we first stall the root stage to have the
- * virtual interrupt state reflect IMASK.
- */
- p0.l = ___ipipe_root_status;
- p0.h = ___ipipe_root_status;
- r4 = [p0];
- bitset(r4, 0);
- [p0] = r4;
- /*
- * Then we may enable hw IRQs, allowing preemption from high
- * priority domains. schedule_tail() will do local_irq_enable()
- * since Blackfin does not define __ARCH_WANT_UNLOCKED_CTXSW, so
- * there is no need to unstall the root domain by ourselves
- * afterwards.
- */
- p0.l = _bfin_irq_flags;
- p0.h = _bfin_irq_flags;
- r4 = [p0];
- sti r4;
-#endif /* CONFIG_IPIPE */
- SP += -12;
- pseudo_long_call _schedule_tail, p5;
- SP += 12;
- p1 = [sp++];
- r0 = [sp++];
- cc = p1 == 0;
- if cc jump .Lfork;
- sp += -12;
- call (p1);
- sp += 12;
-.Lfork:
- RESTORE_CONTEXT
- rti;
-ENDPROC(_ret_from_fork)
+++ /dev/null
-/* Basic functions for adding/removing custom exception handlers
- *
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <linux/module.h>
-#include <asm/irq_handler.h>
-
-int bfin_request_exception(unsigned int exception, void (*handler)(void))
-{
- void (*curr_handler)(void);
-
- if (exception > 0x3F)
- return -EINVAL;
-
- curr_handler = ex_table[exception];
-
- if (curr_handler != ex_replaceable)
- return -EBUSY;
-
- ex_table[exception] = handler;
-
- return 0;
-}
-EXPORT_SYMBOL(bfin_request_exception);
-
-int bfin_free_exception(unsigned int exception, void (*handler)(void))
-{
- void (*curr_handler)(void);
-
- if (exception > 0x3F)
- return -EINVAL;
-
- curr_handler = ex_table[exception];
-
- if (curr_handler != handler)
- return -EBUSY;
-
- ex_table[exception] = ex_replaceable;
-
- return 0;
-}
-EXPORT_SYMBOL(bfin_free_exception);
+++ /dev/null
-/*
- * This file contains sequences of code that will be copied to a
- * fixed location, defined in <asm/fixed_code.h>. The interrupt
- * handlers ensure that these sequences appear to be atomic when
- * executed from userspace.
- * These are aligned to 16 bytes, so that we have some space to replace
- * these sequences with something else (e.g. kernel traps if we ever do
- * BF561 SMP).
- *
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/linkage.h>
-#include <linux/init.h>
-#include <linux/unistd.h>
-#include <asm/entry.h>
-
-__INIT
-
-ENTRY(_fixed_code_start)
-
-.align 16
-ENTRY(_sigreturn_stub)
- P0 = __NR_rt_sigreturn;
- EXCPT 0;
- /* Speculative execution paranoia. */
-0: JUMP.S 0b;
-ENDPROC (_sigreturn_stub)
-
-.align 16
- /*
- * Atomic swap, 8 bit.
- * Inputs: P0: memory address to use
- * R1: value to store
- * Output: R0: old contents of the memory address, zero extended.
- */
-ENTRY(_atomic_xchg32)
- R0 = [P0];
- [P0] = R1;
- rts;
-ENDPROC (_atomic_xchg32)
-
-.align 16
- /*
- * Compare and swap, 32 bit.
- * Inputs: P0: memory address to use
- * R1: compare value
- * R2: new value to store
- * The new value is stored if the contents of the memory
- * address is equal to the compare value.
- * Output: R0: old contents of the memory address.
- */
-ENTRY(_atomic_cas32)
- R0 = [P0];
- CC = R0 == R1;
- IF !CC JUMP 1f;
- [P0] = R2;
-1:
- rts;
-ENDPROC (_atomic_cas32)
-
-.align 16
- /*
- * Atomic add, 32 bit.
- * Inputs: P0: memory address to use
- * R0: value to add
- * Outputs: R0: new contents of the memory address.
- * R1: previous contents of the memory address.
- */
-ENTRY(_atomic_add32)
- R1 = [P0];
- R0 = R1 + R0;
- [P0] = R0;
- rts;
-ENDPROC (_atomic_add32)
-
-.align 16
- /*
- * Atomic sub, 32 bit.
- * Inputs: P0: memory address to use
- * R0: value to subtract
- * Outputs: R0: new contents of the memory address.
- * R1: previous contents of the memory address.
- */
-ENTRY(_atomic_sub32)
- R1 = [P0];
- R0 = R1 - R0;
- [P0] = R0;
- rts;
-ENDPROC (_atomic_sub32)
-
-.align 16
- /*
- * Atomic ior, 32 bit.
- * Inputs: P0: memory address to use
- * R0: value to ior
- * Outputs: R0: new contents of the memory address.
- * R1: previous contents of the memory address.
- */
-ENTRY(_atomic_ior32)
- R1 = [P0];
- R0 = R1 | R0;
- [P0] = R0;
- rts;
-ENDPROC (_atomic_ior32)
-
-.align 16
- /*
- * Atomic and, 32 bit.
- * Inputs: P0: memory address to use
- * R0: value to and
- * Outputs: R0: new contents of the memory address.
- * R1: previous contents of the memory address.
- */
-ENTRY(_atomic_and32)
- R1 = [P0];
- R0 = R1 & R0;
- [P0] = R0;
- rts;
-ENDPROC (_atomic_and32)
-
-.align 16
- /*
- * Atomic xor, 32 bit.
- * Inputs: P0: memory address to use
- * R0: value to xor
- * Outputs: R0: new contents of the memory address.
- * R1: previous contents of the memory address.
- */
-ENTRY(_atomic_xor32)
- R1 = [P0];
- R0 = R1 ^ R0;
- [P0] = R0;
- rts;
-ENDPROC (_atomic_xor32)
-
-.align 16
- /*
- * safe_user_instruction
- * Four NOPS are enough to allow the pipeline to speculativily load
- * execute anything it wants. After that, things have gone bad, and
- * we are stuck - so panic. Since we might be in user space, we can't
- * call panic, so just cause a unhandled exception, this should cause
- * a dump of the trace buffer so we can tell were we are, and a reboot
- */
-ENTRY(_safe_user_instruction)
- NOP; NOP; NOP; NOP;
- EXCPT 0x4;
-ENDPROC(_safe_user_instruction)
-
-ENTRY(_fixed_code_end)
-
-__FINIT
+++ /dev/null
-/*
- * Copyright 2007 Analog Devices Inc.
- *
- * Licensed under the GPL-2.
- */
-
-#include <linux/module.h>
-#include <linux/sched.h>
-#include <linux/mm_types.h>
-#include <linux/flat.h>
-
-#define FLAT_BFIN_RELOC_TYPE_16_BIT 0
-#define FLAT_BFIN_RELOC_TYPE_16H_BIT 1
-#define FLAT_BFIN_RELOC_TYPE_32_BIT 2
-
-unsigned long bfin_get_addr_from_rp(u32 *ptr,
- u32 relval,
- u32 flags,
- u32 *persistent)
-{
- unsigned short *usptr = (unsigned short *)ptr;
- int type = (relval >> 26) & 7;
- u32 val;
-
- switch (type) {
- case FLAT_BFIN_RELOC_TYPE_16_BIT:
- case FLAT_BFIN_RELOC_TYPE_16H_BIT:
- usptr = (unsigned short *)ptr;
- pr_debug("*usptr = %x", get_unaligned(usptr));
- val = get_unaligned(usptr);
- val += *persistent;
- break;
-
- case FLAT_BFIN_RELOC_TYPE_32_BIT:
- pr_debug("*ptr = %x", get_unaligned(ptr));
- val = get_unaligned(ptr);
- break;
-
- default:
- pr_debug("BINFMT_FLAT: Unknown relocation type %x\n", type);
- return 0;
- }
-
- /*
- * Stack-relative relocs contain the offset into the stack, we
- * have to add the stack's start address here and return 1 from
- * flat_addr_absolute to prevent the normal address calculations
- */
- if (relval & (1 << 29))
- return val + current->mm->context.end_brk;
-
- if ((flags & FLAT_FLAG_GOTPIC) == 0)
- val = htonl(val);
- return val;
-}
-EXPORT_SYMBOL(bfin_get_addr_from_rp);
-
-/*
- * Insert the address ADDR into the symbol reference at RP;
- * RELVAL is the raw relocation-table entry from which RP is derived
- */
-void bfin_put_addr_at_rp(u32 *ptr, u32 addr, u32 relval)
-{
- unsigned short *usptr = (unsigned short *)ptr;
- int type = (relval >> 26) & 7;
-
- switch (type) {
- case FLAT_BFIN_RELOC_TYPE_16_BIT:
- put_unaligned(addr, usptr);
- pr_debug("new value %x at %p", get_unaligned(usptr), usptr);
- break;
-
- case FLAT_BFIN_RELOC_TYPE_16H_BIT:
- put_unaligned(addr >> 16, usptr);
- pr_debug("new value %x", get_unaligned(usptr));
- break;
-
- case FLAT_BFIN_RELOC_TYPE_32_BIT:
- put_unaligned(addr, ptr);
- pr_debug("new ptr =%x", get_unaligned(ptr));
- break;
- }
-}
-EXPORT_SYMBOL(bfin_put_addr_at_rp);
+++ /dev/null
-/*
- * mcount and friends -- ftrace stuff
- *
- * Copyright (C) 2009-2010 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/linkage.h>
-#include <asm/ftrace.h>
-
-.text
-
-#ifdef CONFIG_DYNAMIC_FTRACE
-
-/* Simple stub so we can boot the kernel until runtime patching has
- * disabled all calls to this. Then it'll be unused.
- */
-ENTRY(__mcount)
-# if ANOMALY_05000371
- nop; nop; nop; nop;
-# endif
- rts;
-ENDPROC(__mcount)
-
-/* GCC will have called us before setting up the function prologue, so we
- * can clobber the normal scratch registers, but we need to make sure to
- * save/restore the registers used for argument passing (R0-R2) in case
- * the profiled function is using them. With data registers, R3 is the
- * only one we can blow away. With pointer registers, we have P0-P2.
- *
- * Upon entry, the RETS will point to the top of the current profiled
- * function. And since GCC pushed the previous RETS for us, the previous
- * function will be waiting there. mmmm pie.
- */
-ENTRY(_ftrace_caller)
- /* save first/second/third function arg and the return register */
- [--sp] = r2;
- [--sp] = r0;
- [--sp] = r1;
- [--sp] = rets;
-
- /* function_trace_call(unsigned long ip, unsigned long parent_ip):
- * ip: this point was called by ...
- * parent_ip: ... this function
- * the ip itself will need adjusting for the mcount call
- */
- r0 = rets;
- r1 = [sp + 16]; /* skip the 4 local regs on stack */
- r0 += -MCOUNT_INSN_SIZE;
-
-.globl _ftrace_call
-_ftrace_call:
- call _ftrace_stub
-
-# ifdef CONFIG_FUNCTION_GRAPH_TRACER
-.globl _ftrace_graph_call
-_ftrace_graph_call:
- nop; /* jump _ftrace_graph_caller; */
-# endif
-
- /* restore state and get out of dodge */
-.Lfinish_trace:
- rets = [sp++];
- r1 = [sp++];
- r0 = [sp++];
- r2 = [sp++];
-
-.globl _ftrace_stub
-_ftrace_stub:
- rts;
-ENDPROC(_ftrace_caller)
-
-#else
-
-/* See documentation for _ftrace_caller */
-ENTRY(__mcount)
- /* save third function arg early so we can do testing below */
- [--sp] = r2;
-
- /* load the function pointer to the tracer */
- p0.l = _ftrace_trace_function;
- p0.h = _ftrace_trace_function;
- r3 = [p0];
-
- /* optional micro optimization: don't call the stub tracer */
- r2.l = _ftrace_stub;
- r2.h = _ftrace_stub;
- cc = r2 == r3;
- if ! cc jump .Ldo_trace;
-
-# ifdef CONFIG_FUNCTION_GRAPH_TRACER
- /* if the ftrace_graph_return function pointer is not set to
- * the ftrace_stub entry, call prepare_ftrace_return().
- */
- p0.l = _ftrace_graph_return;
- p0.h = _ftrace_graph_return;
- r3 = [p0];
- cc = r2 == r3;
- if ! cc jump _ftrace_graph_caller;
-
- /* similarly, if the ftrace_graph_entry function pointer is not
- * set to the ftrace_graph_entry_stub entry, ...
- */
- p0.l = _ftrace_graph_entry;
- p0.h = _ftrace_graph_entry;
- r2.l = _ftrace_graph_entry_stub;
- r2.h = _ftrace_graph_entry_stub;
- r3 = [p0];
- cc = r2 == r3;
- if ! cc jump _ftrace_graph_caller;
-# endif
-
- r2 = [sp++];
- rts;
-
-.Ldo_trace:
-
- /* save first/second function arg and the return register */
- [--sp] = r0;
- [--sp] = r1;
- [--sp] = rets;
-
- /* setup the tracer function */
- p0 = r3;
-
- /* function_trace_call(unsigned long ip, unsigned long parent_ip):
- * ip: this point was called by ...
- * parent_ip: ... this function
- * the ip itself will need adjusting for the mcount call
- */
- r0 = rets;
- r1 = [sp + 16]; /* skip the 4 local regs on stack */
- r0 += -MCOUNT_INSN_SIZE;
-
- /* call the tracer */
- call (p0);
-
- /* restore state and get out of dodge */
-.Lfinish_trace:
- rets = [sp++];
- r1 = [sp++];
- r0 = [sp++];
- r2 = [sp++];
-
-.globl _ftrace_stub
-_ftrace_stub:
- rts;
-ENDPROC(__mcount)
-
-#endif
-
-#ifdef CONFIG_FUNCTION_GRAPH_TRACER
-/* The prepare_ftrace_return() function is similar to the trace function
- * except it takes a pointer to the location of the frompc. This is so
- * the prepare_ftrace_return() can hijack it temporarily for probing
- * purposes.
- */
-ENTRY(_ftrace_graph_caller)
-# ifndef CONFIG_DYNAMIC_FTRACE
- /* save first/second function arg and the return register */
- [--sp] = r0;
- [--sp] = r1;
- [--sp] = rets;
-
- /* prepare_ftrace_return(parent, self_addr, frame_pointer) */
- r0 = sp; /* unsigned long *parent */
- r1 = rets; /* unsigned long self_addr */
-# else
- r0 = sp; /* unsigned long *parent */
- r1 = [sp]; /* unsigned long self_addr */
-# endif
-# ifdef HAVE_FUNCTION_GRAPH_FP_TEST
- r2 = fp; /* unsigned long frame_pointer */
-# endif
- r0 += 16; /* skip the 4 local regs on stack */
- r1 += -MCOUNT_INSN_SIZE;
- call _prepare_ftrace_return;
-
- jump .Lfinish_trace;
-ENDPROC(_ftrace_graph_caller)
-
-/* Undo the rewrite caused by ftrace_graph_caller(). The common function
- * ftrace_return_to_handler() will return the original rets so we can
- * restore it and be on our way.
- */
-ENTRY(_return_to_handler)
- /* make sure original return values are saved */
- [--sp] = p0;
- [--sp] = r0;
- [--sp] = r1;
-
- /* get original return address */
-# ifdef HAVE_FUNCTION_GRAPH_FP_TEST
- r0 = fp; /* Blackfin is sane, so omit this */
-# endif
- call _ftrace_return_to_handler;
- rets = r0;
-
- /* anomaly 05000371 - make sure we have at least three instructions
- * between rets setting and the return
- */
- r1 = [sp++];
- r0 = [sp++];
- p0 = [sp++];
- rts;
-ENDPROC(_return_to_handler)
-#endif
+++ /dev/null
-/*
- * ftrace graph code
- *
- * Copyright (C) 2009-2010 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/ftrace.h>
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/uaccess.h>
-#include <linux/atomic.h>
-#include <asm/cacheflush.h>
-
-#ifdef CONFIG_DYNAMIC_FTRACE
-
-static const unsigned char mnop[] = {
- 0x03, 0xc0, 0x00, 0x18, /* MNOP; */
- 0x03, 0xc0, 0x00, 0x18, /* MNOP; */
-};
-
-static void bfin_make_pcrel24(unsigned char *insn, unsigned long src,
- unsigned long dst)
-{
- uint32_t pcrel = (dst - src) >> 1;
- insn[0] = pcrel >> 16;
- insn[1] = 0xe3;
- insn[2] = pcrel;
- insn[3] = pcrel >> 8;
-}
-#define bfin_make_pcrel24(insn, src, dst) bfin_make_pcrel24(insn, src, (unsigned long)(dst))
-
-static int ftrace_modify_code(unsigned long ip, const unsigned char *code,
- unsigned long len)
-{
- int ret = probe_kernel_write((void *)ip, (void *)code, len);
- flush_icache_range(ip, ip + len);
- return ret;
-}
-
-int ftrace_make_nop(struct module *mod, struct dyn_ftrace *rec,
- unsigned long addr)
-{
- /* Turn the mcount call site into two MNOPs as those are 32bit insns */
- return ftrace_modify_code(rec->ip, mnop, sizeof(mnop));
-}
-
-int ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr)
-{
- /* Restore the mcount call site */
- unsigned char call[8];
- call[0] = 0x67; /* [--SP] = RETS; */
- call[1] = 0x01;
- bfin_make_pcrel24(&call[2], rec->ip + 2, addr);
- call[6] = 0x27; /* RETS = [SP++]; */
- call[7] = 0x01;
- return ftrace_modify_code(rec->ip, call, sizeof(call));
-}
-
-int ftrace_update_ftrace_func(ftrace_func_t func)
-{
- unsigned char call[4];
- unsigned long ip = (unsigned long)&ftrace_call;
- bfin_make_pcrel24(call, ip, func);
- return ftrace_modify_code(ip, call, sizeof(call));
-}
-
-int __init ftrace_dyn_arch_init(void)
-{
- return 0;
-}
-
-#endif
-
-#ifdef CONFIG_FUNCTION_GRAPH_TRACER
-
-# ifdef CONFIG_DYNAMIC_FTRACE
-
-extern void ftrace_graph_call(void);
-
-int ftrace_enable_ftrace_graph_caller(void)
-{
- unsigned long ip = (unsigned long)&ftrace_graph_call;
- uint16_t jump_pcrel12 = ((unsigned long)&ftrace_graph_caller - ip) >> 1;
- jump_pcrel12 |= 0x2000;
- return ftrace_modify_code(ip, (void *)&jump_pcrel12, sizeof(jump_pcrel12));
-}
-
-int ftrace_disable_ftrace_graph_caller(void)
-{
- return ftrace_modify_code((unsigned long)&ftrace_graph_call, empty_zero_page, 2);
-}
-
-# endif
-
-/*
- * Hook the return address and push it in the stack of return addrs
- * in current thread info.
- */
-void prepare_ftrace_return(unsigned long *parent, unsigned long self_addr,
- unsigned long frame_pointer)
-{
- struct ftrace_graph_ent trace;
- unsigned long return_hooker = (unsigned long)&return_to_handler;
-
- if (unlikely(atomic_read(¤t->tracing_graph_pause)))
- return;
-
- if (ftrace_push_return_trace(*parent, self_addr, &trace.depth,
- frame_pointer, NULL) == -EBUSY)
- return;
-
- trace.func = self_addr;
-
- /* Only trace if the calling function expects to */
- if (!ftrace_graph_entry(&trace)) {
- current->curr_ret_stack--;
- return;
- }
-
- /* all is well in the world ! hijack RETS ... */
- *parent = return_hooker;
-}
-
-#endif
+++ /dev/null
-/*
- * gptimers.c - Blackfin General Purpose Timer core API
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- * Copyright (C) 2005 John DeHority
- * Copyright (C) 2006 Hella Aglaia GmbH (awe@aglaia-gmbh.de)
- *
- * Licensed under the GPLv2.
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/io.h>
-
-#include <asm/blackfin.h>
-#include <asm/gptimers.h>
-
-#ifdef DEBUG
-# define tassert(expr)
-#else
-# define tassert(expr) \
- if (!(expr)) \
- printk(KERN_DEBUG "%s:%s:%i: Assertion failed: " #expr "\n", __FILE__, __func__, __LINE__);
-#endif
-
-#ifndef CONFIG_BF60x
-# define BFIN_TIMER_NUM_GROUP (BFIN_TIMER_OCTET(MAX_BLACKFIN_GPTIMERS - 1) + 1)
-#else
-# define BFIN_TIMER_NUM_GROUP 1
-#endif
-
-static struct bfin_gptimer_regs * const timer_regs[MAX_BLACKFIN_GPTIMERS] =
-{
- (void *)TIMER0_CONFIG,
- (void *)TIMER1_CONFIG,
- (void *)TIMER2_CONFIG,
-#if (MAX_BLACKFIN_GPTIMERS > 3)
- (void *)TIMER3_CONFIG,
- (void *)TIMER4_CONFIG,
- (void *)TIMER5_CONFIG,
- (void *)TIMER6_CONFIG,
- (void *)TIMER7_CONFIG,
-# if (MAX_BLACKFIN_GPTIMERS > 8)
- (void *)TIMER8_CONFIG,
- (void *)TIMER9_CONFIG,
- (void *)TIMER10_CONFIG,
-# if (MAX_BLACKFIN_GPTIMERS > 11)
- (void *)TIMER11_CONFIG,
-# endif
-# endif
-#endif
-};
-
-static struct bfin_gptimer_group_regs * const group_regs[BFIN_TIMER_NUM_GROUP] =
-{
- (void *)TIMER0_GROUP_REG,
-#if (MAX_BLACKFIN_GPTIMERS > 8)
- (void *)TIMER8_GROUP_REG,
-#endif
-};
-
-static uint32_t const trun_mask[MAX_BLACKFIN_GPTIMERS] =
-{
- TIMER_STATUS_TRUN0,
- TIMER_STATUS_TRUN1,
- TIMER_STATUS_TRUN2,
-#if (MAX_BLACKFIN_GPTIMERS > 3)
- TIMER_STATUS_TRUN3,
- TIMER_STATUS_TRUN4,
- TIMER_STATUS_TRUN5,
- TIMER_STATUS_TRUN6,
- TIMER_STATUS_TRUN7,
-# if (MAX_BLACKFIN_GPTIMERS > 8)
- TIMER_STATUS_TRUN8,
- TIMER_STATUS_TRUN9,
- TIMER_STATUS_TRUN10,
-# if (MAX_BLACKFIN_GPTIMERS > 11)
- TIMER_STATUS_TRUN11,
-# endif
-# endif
-#endif
-};
-
-static uint32_t const tovf_mask[MAX_BLACKFIN_GPTIMERS] =
-{
- TIMER_STATUS_TOVF0,
- TIMER_STATUS_TOVF1,
- TIMER_STATUS_TOVF2,
-#if (MAX_BLACKFIN_GPTIMERS > 3)
- TIMER_STATUS_TOVF3,
- TIMER_STATUS_TOVF4,
- TIMER_STATUS_TOVF5,
- TIMER_STATUS_TOVF6,
- TIMER_STATUS_TOVF7,
-# if (MAX_BLACKFIN_GPTIMERS > 8)
- TIMER_STATUS_TOVF8,
- TIMER_STATUS_TOVF9,
- TIMER_STATUS_TOVF10,
-# if (MAX_BLACKFIN_GPTIMERS > 11)
- TIMER_STATUS_TOVF11,
-# endif
-# endif
-#endif
-};
-
-static uint32_t const timil_mask[MAX_BLACKFIN_GPTIMERS] =
-{
- TIMER_STATUS_TIMIL0,
- TIMER_STATUS_TIMIL1,
- TIMER_STATUS_TIMIL2,
-#if (MAX_BLACKFIN_GPTIMERS > 3)
- TIMER_STATUS_TIMIL3,
- TIMER_STATUS_TIMIL4,
- TIMER_STATUS_TIMIL5,
- TIMER_STATUS_TIMIL6,
- TIMER_STATUS_TIMIL7,
-# if (MAX_BLACKFIN_GPTIMERS > 8)
- TIMER_STATUS_TIMIL8,
- TIMER_STATUS_TIMIL9,
- TIMER_STATUS_TIMIL10,
-# if (MAX_BLACKFIN_GPTIMERS > 11)
- TIMER_STATUS_TIMIL11,
-# endif
-# endif
-#endif
-};
-
-void set_gptimer_pwidth(unsigned int timer_id, uint32_t value)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- bfin_write(&timer_regs[timer_id]->width, value);
- SSYNC();
-}
-EXPORT_SYMBOL(set_gptimer_pwidth);
-
-uint32_t get_gptimer_pwidth(unsigned int timer_id)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- return bfin_read(&timer_regs[timer_id]->width);
-}
-EXPORT_SYMBOL(get_gptimer_pwidth);
-
-void set_gptimer_period(unsigned int timer_id, uint32_t period)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- bfin_write(&timer_regs[timer_id]->period, period);
- SSYNC();
-}
-EXPORT_SYMBOL(set_gptimer_period);
-
-uint32_t get_gptimer_period(unsigned int timer_id)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- return bfin_read(&timer_regs[timer_id]->period);
-}
-EXPORT_SYMBOL(get_gptimer_period);
-
-uint32_t get_gptimer_count(unsigned int timer_id)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- return bfin_read(&timer_regs[timer_id]->counter);
-}
-EXPORT_SYMBOL(get_gptimer_count);
-
-#ifdef CONFIG_BF60x
-void set_gptimer_delay(unsigned int timer_id, uint32_t delay)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- bfin_write(&timer_regs[timer_id]->delay, delay);
- SSYNC();
-}
-EXPORT_SYMBOL(set_gptimer_delay);
-
-uint32_t get_gptimer_delay(unsigned int timer_id)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- return bfin_read(&timer_regs[timer_id]->delay);
-}
-EXPORT_SYMBOL(get_gptimer_delay);
-#endif
-
-#ifdef CONFIG_BF60x
-int get_gptimer_intr(unsigned int timer_id)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- return !!(bfin_read(&group_regs[BFIN_TIMER_OCTET(timer_id)]->data_ilat) & timil_mask[timer_id]);
-}
-EXPORT_SYMBOL(get_gptimer_intr);
-
-void clear_gptimer_intr(unsigned int timer_id)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- bfin_write(&group_regs[BFIN_TIMER_OCTET(timer_id)]->data_ilat, timil_mask[timer_id]);
-}
-EXPORT_SYMBOL(clear_gptimer_intr);
-
-int get_gptimer_over(unsigned int timer_id)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- return !!(bfin_read(&group_regs[BFIN_TIMER_OCTET(timer_id)]->stat_ilat) & tovf_mask[timer_id]);
-}
-EXPORT_SYMBOL(get_gptimer_over);
-
-void clear_gptimer_over(unsigned int timer_id)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- bfin_write(&group_regs[BFIN_TIMER_OCTET(timer_id)]->stat_ilat, tovf_mask[timer_id]);
-}
-EXPORT_SYMBOL(clear_gptimer_over);
-
-int get_gptimer_run(unsigned int timer_id)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- return !!(bfin_read(&group_regs[BFIN_TIMER_OCTET(timer_id)]->run) & trun_mask[timer_id]);
-}
-EXPORT_SYMBOL(get_gptimer_run);
-
-uint32_t get_gptimer_status(unsigned int group)
-{
- tassert(group < BFIN_TIMER_NUM_GROUP);
- return bfin_read(&group_regs[group]->data_ilat);
-}
-EXPORT_SYMBOL(get_gptimer_status);
-
-void set_gptimer_status(unsigned int group, uint32_t value)
-{
- tassert(group < BFIN_TIMER_NUM_GROUP);
- bfin_write(&group_regs[group]->data_ilat, value);
- SSYNC();
-}
-EXPORT_SYMBOL(set_gptimer_status);
-#else
-uint32_t get_gptimer_status(unsigned int group)
-{
- tassert(group < BFIN_TIMER_NUM_GROUP);
- return bfin_read(&group_regs[group]->status);
-}
-EXPORT_SYMBOL(get_gptimer_status);
-
-void set_gptimer_status(unsigned int group, uint32_t value)
-{
- tassert(group < BFIN_TIMER_NUM_GROUP);
- bfin_write(&group_regs[group]->status, value);
- SSYNC();
-}
-EXPORT_SYMBOL(set_gptimer_status);
-
-static uint32_t read_gptimer_status(unsigned int timer_id)
-{
- return bfin_read(&group_regs[BFIN_TIMER_OCTET(timer_id)]->status);
-}
-
-int get_gptimer_intr(unsigned int timer_id)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- return !!(read_gptimer_status(timer_id) & timil_mask[timer_id]);
-}
-EXPORT_SYMBOL(get_gptimer_intr);
-
-void clear_gptimer_intr(unsigned int timer_id)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- bfin_write(&group_regs[BFIN_TIMER_OCTET(timer_id)]->status, timil_mask[timer_id]);
-}
-EXPORT_SYMBOL(clear_gptimer_intr);
-
-int get_gptimer_over(unsigned int timer_id)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- return !!(read_gptimer_status(timer_id) & tovf_mask[timer_id]);
-}
-EXPORT_SYMBOL(get_gptimer_over);
-
-void clear_gptimer_over(unsigned int timer_id)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- bfin_write(&group_regs[BFIN_TIMER_OCTET(timer_id)]->status, tovf_mask[timer_id]);
-}
-EXPORT_SYMBOL(clear_gptimer_over);
-
-int get_gptimer_run(unsigned int timer_id)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- return !!(read_gptimer_status(timer_id) & trun_mask[timer_id]);
-}
-EXPORT_SYMBOL(get_gptimer_run);
-#endif
-
-void set_gptimer_config(unsigned int timer_id, uint16_t config)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- bfin_write(&timer_regs[timer_id]->config, config);
- SSYNC();
-}
-EXPORT_SYMBOL(set_gptimer_config);
-
-uint16_t get_gptimer_config(unsigned int timer_id)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- return bfin_read(&timer_regs[timer_id]->config);
-}
-EXPORT_SYMBOL(get_gptimer_config);
-
-void enable_gptimers(uint16_t mask)
-{
- int i;
-#ifdef CONFIG_BF60x
- uint16_t imask;
- imask = bfin_read16(TIMER_DATA_IMSK);
- imask &= ~mask;
- bfin_write16(TIMER_DATA_IMSK, imask);
-#endif
- tassert((mask & ~BLACKFIN_GPTIMER_IDMASK) == 0);
- for (i = 0; i < BFIN_TIMER_NUM_GROUP; ++i) {
- bfin_write(&group_regs[i]->enable, mask & 0xFF);
- mask >>= 8;
- }
- SSYNC();
-}
-EXPORT_SYMBOL(enable_gptimers);
-
-static void _disable_gptimers(uint16_t mask)
-{
- int i;
- uint16_t m = mask;
- tassert((mask & ~BLACKFIN_GPTIMER_IDMASK) == 0);
- for (i = 0; i < BFIN_TIMER_NUM_GROUP; ++i) {
- bfin_write(&group_regs[i]->disable, m & 0xFF);
- m >>= 8;
- }
-}
-
-void disable_gptimers(uint16_t mask)
-{
-#ifndef CONFIG_BF60x
- int i;
- _disable_gptimers(mask);
- for (i = 0; i < MAX_BLACKFIN_GPTIMERS; ++i)
- if (mask & (1 << i))
- bfin_write(&group_regs[BFIN_TIMER_OCTET(i)]->status, trun_mask[i]);
- SSYNC();
-#else
- _disable_gptimers(mask);
-#endif
-}
-EXPORT_SYMBOL(disable_gptimers);
-
-void disable_gptimers_sync(uint16_t mask)
-{
- _disable_gptimers(mask);
- SSYNC();
-}
-EXPORT_SYMBOL(disable_gptimers_sync);
-
-void set_gptimer_pulse_hi(unsigned int timer_id)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- bfin_write_or(&timer_regs[timer_id]->config, TIMER_PULSE_HI);
- SSYNC();
-}
-EXPORT_SYMBOL(set_gptimer_pulse_hi);
-
-void clear_gptimer_pulse_hi(unsigned int timer_id)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- bfin_write_and(&timer_regs[timer_id]->config, ~TIMER_PULSE_HI);
- SSYNC();
-}
-EXPORT_SYMBOL(clear_gptimer_pulse_hi);
-
-uint16_t get_enabled_gptimers(void)
-{
- int i;
- uint16_t result = 0;
- for (i = 0; i < BFIN_TIMER_NUM_GROUP; ++i)
- result |= (bfin_read(&group_regs[i]->enable) << (i << 3));
- return result;
-}
-EXPORT_SYMBOL(get_enabled_gptimers);
-
-MODULE_AUTHOR("Axel Weiss (awe@aglaia-gmbh.de)");
-MODULE_DESCRIPTION("Blackfin General Purpose Timers API");
-MODULE_LICENSE("GPL");
+++ /dev/null
-/* -*- linux-c -*-
- * linux/arch/blackfin/kernel/ipipe.c
- *
- * Copyright (C) 2005-2007 Philippe Gerum.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, Inc., 675 Mass Ave, Cambridge MA 02139,
- * USA; either version 2 of the License, or (at your option) any later
- * version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Architecture-dependent I-pipe support for the Blackfin.
- */
-
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/percpu.h>
-#include <linux/bitops.h>
-#include <linux/errno.h>
-#include <linux/kthread.h>
-#include <linux/unistd.h>
-#include <linux/io.h>
-#include <linux/atomic.h>
-#include <asm/irq_handler.h>
-
-DEFINE_PER_CPU(struct pt_regs, __ipipe_tick_regs);
-
-asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs);
-
-static void __ipipe_no_irqtail(void);
-
-unsigned long __ipipe_irq_tail_hook = (unsigned long)&__ipipe_no_irqtail;
-EXPORT_SYMBOL(__ipipe_irq_tail_hook);
-
-unsigned long __ipipe_core_clock;
-EXPORT_SYMBOL(__ipipe_core_clock);
-
-unsigned long __ipipe_freq_scale;
-EXPORT_SYMBOL(__ipipe_freq_scale);
-
-atomic_t __ipipe_irq_lvdepth[IVG15 + 1];
-
-unsigned long __ipipe_irq_lvmask = bfin_no_irqs;
-EXPORT_SYMBOL(__ipipe_irq_lvmask);
-
-static void __ipipe_ack_irq(unsigned irq, struct irq_desc *desc)
-{
- desc->ipipe_ack(irq, desc);
-}
-
-/*
- * __ipipe_enable_pipeline() -- We are running on the boot CPU, hw
- * interrupts are off, and secondary CPUs are still lost in space.
- */
-void __ipipe_enable_pipeline(void)
-{
- unsigned irq;
-
- __ipipe_core_clock = get_cclk(); /* Fetch this once. */
- __ipipe_freq_scale = 1000000000UL / __ipipe_core_clock;
-
- for (irq = 0; irq < NR_IRQS; ++irq)
- ipipe_virtualize_irq(ipipe_root_domain,
- irq,
- (ipipe_irq_handler_t)&asm_do_IRQ,
- NULL,
- &__ipipe_ack_irq,
- IPIPE_HANDLE_MASK | IPIPE_PASS_MASK);
-}
-
-/*
- * __ipipe_handle_irq() -- IPIPE's generic IRQ handler. An optimistic
- * interrupt protection log is maintained here for each domain. Hw
- * interrupts are masked on entry.
- */
-void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs)
-{
- struct ipipe_percpu_domain_data *p = ipipe_root_cpudom_ptr();
- struct ipipe_domain *this_domain, *next_domain;
- struct list_head *head, *pos;
- struct ipipe_irqdesc *idesc;
- int m_ack, s = -1;
-
- /*
- * Software-triggered IRQs do not need any ack. The contents
- * of the register frame should only be used when processing
- * the timer interrupt, but not for handling any other
- * interrupt.
- */
- m_ack = (regs == NULL || irq == IRQ_SYSTMR || irq == IRQ_CORETMR);
- this_domain = __ipipe_current_domain;
- idesc = &this_domain->irqs[irq];
-
- if (unlikely(test_bit(IPIPE_STICKY_FLAG, &idesc->control)))
- head = &this_domain->p_link;
- else {
- head = __ipipe_pipeline.next;
- next_domain = list_entry(head, struct ipipe_domain, p_link);
- idesc = &next_domain->irqs[irq];
- if (likely(test_bit(IPIPE_WIRED_FLAG, &idesc->control))) {
- if (!m_ack && idesc->acknowledge != NULL)
- idesc->acknowledge(irq, irq_to_desc(irq));
- if (test_bit(IPIPE_SYNCDEFER_FLAG, &p->status))
- s = __test_and_set_bit(IPIPE_STALL_FLAG,
- &p->status);
- __ipipe_dispatch_wired(next_domain, irq);
- goto out;
- }
- }
-
- /* Ack the interrupt. */
-
- pos = head;
- while (pos != &__ipipe_pipeline) {
- next_domain = list_entry(pos, struct ipipe_domain, p_link);
- idesc = &next_domain->irqs[irq];
- if (test_bit(IPIPE_HANDLE_FLAG, &idesc->control)) {
- __ipipe_set_irq_pending(next_domain, irq);
- if (!m_ack && idesc->acknowledge != NULL) {
- idesc->acknowledge(irq, irq_to_desc(irq));
- m_ack = 1;
- }
- }
- if (!test_bit(IPIPE_PASS_FLAG, &idesc->control))
- break;
- pos = next_domain->p_link.next;
- }
-
- /*
- * Now walk the pipeline, yielding control to the highest
- * priority domain that has pending interrupt(s) or
- * immediately to the current domain if the interrupt has been
- * marked as 'sticky'. This search does not go beyond the
- * current domain in the pipeline. We also enforce the
- * additional root stage lock (blackfin-specific).
- */
- if (test_bit(IPIPE_SYNCDEFER_FLAG, &p->status))
- s = __test_and_set_bit(IPIPE_STALL_FLAG, &p->status);
-
- /*
- * If the interrupt preempted the head domain, then do not
- * even try to walk the pipeline, unless an interrupt is
- * pending for it.
- */
- if (test_bit(IPIPE_AHEAD_FLAG, &this_domain->flags) &&
- !__ipipe_ipending_p(ipipe_head_cpudom_ptr()))
- goto out;
-
- __ipipe_walk_pipeline(head);
-out:
- if (!s)
- __clear_bit(IPIPE_STALL_FLAG, &p->status);
-}
-
-void __ipipe_enable_irqdesc(struct ipipe_domain *ipd, unsigned irq)
-{
- struct irq_desc *desc = irq_to_desc(irq);
- int prio = __ipipe_get_irq_priority(irq);
-
- desc->depth = 0;
- if (ipd != &ipipe_root &&
- atomic_inc_return(&__ipipe_irq_lvdepth[prio]) == 1)
- __set_bit(prio, &__ipipe_irq_lvmask);
-}
-EXPORT_SYMBOL(__ipipe_enable_irqdesc);
-
-void __ipipe_disable_irqdesc(struct ipipe_domain *ipd, unsigned irq)
-{
- int prio = __ipipe_get_irq_priority(irq);
-
- if (ipd != &ipipe_root &&
- atomic_dec_and_test(&__ipipe_irq_lvdepth[prio]))
- __clear_bit(prio, &__ipipe_irq_lvmask);
-}
-EXPORT_SYMBOL(__ipipe_disable_irqdesc);
-
-asmlinkage int __ipipe_syscall_root(struct pt_regs *regs)
-{
- struct ipipe_percpu_domain_data *p;
- void (*hook)(void);
- int ret;
-
- WARN_ON_ONCE(irqs_disabled_hw());
-
- /*
- * We need to run the IRQ tail hook each time we intercept a
- * syscall, because we know that important operations might be
- * pending there (e.g. Xenomai deferred rescheduling).
- */
- hook = (__typeof__(hook))__ipipe_irq_tail_hook;
- hook();
-
- /*
- * This routine either returns:
- * 0 -- if the syscall is to be passed to Linux;
- * >0 -- if the syscall should not be passed to Linux, and no
- * tail work should be performed;
- * <0 -- if the syscall should not be passed to Linux but the
- * tail work has to be performed (for handling signals etc).
- */
-
- if (!__ipipe_syscall_watched_p(current, regs->orig_p0) ||
- !__ipipe_event_monitored_p(IPIPE_EVENT_SYSCALL))
- return 0;
-
- ret = __ipipe_dispatch_event(IPIPE_EVENT_SYSCALL, regs);
-
- hard_local_irq_disable();
-
- /*
- * This is the end of the syscall path, so we may
- * safely assume a valid Linux task stack here.
- */
- if (current->ipipe_flags & PF_EVTRET) {
- current->ipipe_flags &= ~PF_EVTRET;
- __ipipe_dispatch_event(IPIPE_EVENT_RETURN, regs);
- }
-
- if (!__ipipe_root_domain_p)
- ret = -1;
- else {
- p = ipipe_root_cpudom_ptr();
- if (__ipipe_ipending_p(p))
- __ipipe_sync_pipeline();
- }
-
- hard_local_irq_enable();
-
- return -ret;
-}
-
-static void __ipipe_no_irqtail(void)
-{
-}
-
-int ipipe_get_sysinfo(struct ipipe_sysinfo *info)
-{
- info->sys_nr_cpus = num_online_cpus();
- info->sys_cpu_freq = ipipe_cpu_freq();
- info->sys_hrtimer_irq = IPIPE_TIMER_IRQ;
- info->sys_hrtimer_freq = __ipipe_core_clock;
- info->sys_hrclock_freq = __ipipe_core_clock;
-
- return 0;
-}
-
-/*
- * ipipe_trigger_irq() -- Push the interrupt at front of the pipeline
- * just like if it has been actually received from a hw source. Also
- * works for virtual interrupts.
- */
-int ipipe_trigger_irq(unsigned irq)
-{
- unsigned long flags;
-
-#ifdef CONFIG_IPIPE_DEBUG
- if (irq >= IPIPE_NR_IRQS ||
- (ipipe_virtual_irq_p(irq)
- && !test_bit(irq - IPIPE_VIRQ_BASE, &__ipipe_virtual_irq_map)))
- return -EINVAL;
-#endif
-
- flags = hard_local_irq_save();
- __ipipe_handle_irq(irq, NULL);
- hard_local_irq_restore(flags);
-
- return 1;
-}
-
-asmlinkage void __ipipe_sync_root(void)
-{
- void (*irq_tail_hook)(void) = (void (*)(void))__ipipe_irq_tail_hook;
- struct ipipe_percpu_domain_data *p;
- unsigned long flags;
-
- BUG_ON(irqs_disabled());
-
- flags = hard_local_irq_save();
-
- if (irq_tail_hook)
- irq_tail_hook();
-
- clear_thread_flag(TIF_IRQ_SYNC);
-
- p = ipipe_root_cpudom_ptr();
- if (__ipipe_ipending_p(p))
- __ipipe_sync_pipeline();
-
- hard_local_irq_restore(flags);
-}
-
-void ___ipipe_sync_pipeline(void)
-{
- if (__ipipe_root_domain_p &&
- test_bit(IPIPE_SYNCDEFER_FLAG, &ipipe_root_cpudom_var(status)))
- return;
-
- __ipipe_sync_stage();
-}
-
-void __ipipe_disable_root_irqs_hw(void)
-{
- /*
- * This code is called by the ins{bwl} routines (see
- * arch/blackfin/lib/ins.S), which are heavily used by the
- * network stack. It masks all interrupts but those handled by
- * non-root domains, so that we keep decent network transfer
- * rates for Linux without inducing pathological jitter for
- * the real-time domain.
- */
- bfin_sti(__ipipe_irq_lvmask);
- __set_bit(IPIPE_STALL_FLAG, &ipipe_root_cpudom_var(status));
-}
-
-void __ipipe_enable_root_irqs_hw(void)
-{
- __clear_bit(IPIPE_STALL_FLAG, &ipipe_root_cpudom_var(status));
- bfin_sti(bfin_irq_flags);
-}
-
-/*
- * We could use standard atomic bitops in the following root status
- * manipulation routines, but let's prepare for SMP support in the
- * same move, preventing CPU migration as required.
- */
-void __ipipe_stall_root(void)
-{
- unsigned long *p, flags;
-
- flags = hard_local_irq_save();
- p = &__ipipe_root_status;
- __set_bit(IPIPE_STALL_FLAG, p);
- hard_local_irq_restore(flags);
-}
-EXPORT_SYMBOL(__ipipe_stall_root);
-
-unsigned long __ipipe_test_and_stall_root(void)
-{
- unsigned long *p, flags;
- int x;
-
- flags = hard_local_irq_save();
- p = &__ipipe_root_status;
- x = __test_and_set_bit(IPIPE_STALL_FLAG, p);
- hard_local_irq_restore(flags);
-
- return x;
-}
-EXPORT_SYMBOL(__ipipe_test_and_stall_root);
-
-unsigned long __ipipe_test_root(void)
-{
- const unsigned long *p;
- unsigned long flags;
- int x;
-
- flags = hard_local_irq_save_smp();
- p = &__ipipe_root_status;
- x = test_bit(IPIPE_STALL_FLAG, p);
- hard_local_irq_restore_smp(flags);
-
- return x;
-}
-EXPORT_SYMBOL(__ipipe_test_root);
-
-void __ipipe_lock_root(void)
-{
- unsigned long *p, flags;
-
- flags = hard_local_irq_save();
- p = &__ipipe_root_status;
- __set_bit(IPIPE_SYNCDEFER_FLAG, p);
- hard_local_irq_restore(flags);
-}
-EXPORT_SYMBOL(__ipipe_lock_root);
-
-void __ipipe_unlock_root(void)
-{
- unsigned long *p, flags;
-
- flags = hard_local_irq_save();
- p = &__ipipe_root_status;
- __clear_bit(IPIPE_SYNCDEFER_FLAG, p);
- hard_local_irq_restore(flags);
-}
-EXPORT_SYMBOL(__ipipe_unlock_root);
+++ /dev/null
-/*
- * Copyright 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <linux/kernel_stat.h>
-#include <linux/module.h>
-#include <linux/random.h>
-#include <linux/seq_file.h>
-#include <linux/kallsyms.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/seq_file.h>
-#include <asm/irq_handler.h>
-#include <asm/trace.h>
-#include <asm/pda.h>
-
-static atomic_t irq_err_count;
-void ack_bad_irq(unsigned int irq)
-{
- atomic_inc(&irq_err_count);
- printk(KERN_ERR "IRQ: spurious interrupt %d\n", irq);
-}
-
-static struct irq_desc bad_irq_desc = {
- .handle_irq = handle_bad_irq,
- .lock = __RAW_SPIN_LOCK_UNLOCKED(bad_irq_desc.lock),
-};
-
-#ifdef CONFIG_CPUMASK_OFFSTACK
-/* We are not allocating a variable-sized bad_irq_desc.affinity */
-#error "Blackfin architecture does not support CONFIG_CPUMASK_OFFSTACK."
-#endif
-
-#ifdef CONFIG_PROC_FS
-int arch_show_interrupts(struct seq_file *p, int prec)
-{
- int j;
-
- seq_printf(p, "%*s: ", prec, "NMI");
- for_each_online_cpu(j)
- seq_printf(p, "%10u ", cpu_pda[j].__nmi_count);
- seq_printf(p, " CORE Non Maskable Interrupt\n");
- seq_printf(p, "%*s: %10u\n", prec, "ERR", atomic_read(&irq_err_count));
- return 0;
-}
-#endif
-
-#ifdef CONFIG_DEBUG_STACKOVERFLOW
-static void check_stack_overflow(int irq)
-{
- /* Debugging check for stack overflow: is there less than STACK_WARN free? */
- long sp = __get_SP() & (THREAD_SIZE - 1);
-
- if (unlikely(sp < (sizeof(struct thread_info) + STACK_WARN))) {
- dump_stack();
- pr_emerg("irq%i: possible stack overflow only %ld bytes free\n",
- irq, sp - sizeof(struct thread_info));
- }
-}
-#else
-static inline void check_stack_overflow(int irq) { }
-#endif
-
-#ifndef CONFIG_IPIPE
-static void maybe_lower_to_irq14(void)
-{
- unsigned short pending, other_ints;
-
- /*
- * If we're the only interrupt running (ignoring IRQ15 which
- * is for syscalls), lower our priority to IRQ14 so that
- * softirqs run at that level. If there's another,
- * lower-level interrupt, irq_exit will defer softirqs to
- * that. If the interrupt pipeline is enabled, we are already
- * running at IRQ14 priority, so we don't need this code.
- */
- CSYNC();
- pending = bfin_read_IPEND() & ~0x8000;
- other_ints = pending & (pending - 1);
- if (other_ints == 0)
- lower_to_irq14();
-}
-#else
-static inline void maybe_lower_to_irq14(void) { }
-#endif
-
-/*
- * do_IRQ handles all hardware IRQs. Decoded IRQs should not
- * come via this function. Instead, they should provide their
- * own 'handler'
- */
-#ifdef CONFIG_DO_IRQ_L1
-__attribute__((l1_text))
-#endif
-asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
-{
- struct pt_regs *old_regs = set_irq_regs(regs);
-
- irq_enter();
-
- check_stack_overflow(irq);
-
- /*
- * Some hardware gives randomly wrong interrupts. Rather
- * than crashing, do something sensible.
- */
- if (irq >= NR_IRQS)
- handle_bad_irq(&bad_irq_desc);
- else
- generic_handle_irq(irq);
-
- maybe_lower_to_irq14();
-
- irq_exit();
-
- set_irq_regs(old_regs);
-}
-
-void __init init_IRQ(void)
-{
- init_arch_irq();
-
-#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND
- /* Now that evt_ivhw is set up, turn this on */
- trace_buff_offset = 0;
- bfin_write_TBUFCTL(BFIN_TRACE_ON);
- printk(KERN_INFO "Hardware Trace expanded to %ik\n",
- 1 << CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN);
-#endif
-}
+++ /dev/null
-/*
- * arch/blackfin/kernel/kgdb.c - Blackfin kgdb pieces
- *
- * Copyright 2005-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/ptrace.h> /* for linux pt_regs struct */
-#include <linux/kgdb.h>
-#include <linux/uaccess.h>
-#include <asm/irq_regs.h>
-
-void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs)
-{
- gdb_regs[BFIN_R0] = regs->r0;
- gdb_regs[BFIN_R1] = regs->r1;
- gdb_regs[BFIN_R2] = regs->r2;
- gdb_regs[BFIN_R3] = regs->r3;
- gdb_regs[BFIN_R4] = regs->r4;
- gdb_regs[BFIN_R5] = regs->r5;
- gdb_regs[BFIN_R6] = regs->r6;
- gdb_regs[BFIN_R7] = regs->r7;
- gdb_regs[BFIN_P0] = regs->p0;
- gdb_regs[BFIN_P1] = regs->p1;
- gdb_regs[BFIN_P2] = regs->p2;
- gdb_regs[BFIN_P3] = regs->p3;
- gdb_regs[BFIN_P4] = regs->p4;
- gdb_regs[BFIN_P5] = regs->p5;
- gdb_regs[BFIN_SP] = regs->reserved;
- gdb_regs[BFIN_FP] = regs->fp;
- gdb_regs[BFIN_I0] = regs->i0;
- gdb_regs[BFIN_I1] = regs->i1;
- gdb_regs[BFIN_I2] = regs->i2;
- gdb_regs[BFIN_I3] = regs->i3;
- gdb_regs[BFIN_M0] = regs->m0;
- gdb_regs[BFIN_M1] = regs->m1;
- gdb_regs[BFIN_M2] = regs->m2;
- gdb_regs[BFIN_M3] = regs->m3;
- gdb_regs[BFIN_B0] = regs->b0;
- gdb_regs[BFIN_B1] = regs->b1;
- gdb_regs[BFIN_B2] = regs->b2;
- gdb_regs[BFIN_B3] = regs->b3;
- gdb_regs[BFIN_L0] = regs->l0;
- gdb_regs[BFIN_L1] = regs->l1;
- gdb_regs[BFIN_L2] = regs->l2;
- gdb_regs[BFIN_L3] = regs->l3;
- gdb_regs[BFIN_A0_DOT_X] = regs->a0x;
- gdb_regs[BFIN_A0_DOT_W] = regs->a0w;
- gdb_regs[BFIN_A1_DOT_X] = regs->a1x;
- gdb_regs[BFIN_A1_DOT_W] = regs->a1w;
- gdb_regs[BFIN_ASTAT] = regs->astat;
- gdb_regs[BFIN_RETS] = regs->rets;
- gdb_regs[BFIN_LC0] = regs->lc0;
- gdb_regs[BFIN_LT0] = regs->lt0;
- gdb_regs[BFIN_LB0] = regs->lb0;
- gdb_regs[BFIN_LC1] = regs->lc1;
- gdb_regs[BFIN_LT1] = regs->lt1;
- gdb_regs[BFIN_LB1] = regs->lb1;
- gdb_regs[BFIN_CYCLES] = 0;
- gdb_regs[BFIN_CYCLES2] = 0;
- gdb_regs[BFIN_USP] = regs->usp;
- gdb_regs[BFIN_SEQSTAT] = regs->seqstat;
- gdb_regs[BFIN_SYSCFG] = regs->syscfg;
- gdb_regs[BFIN_RETI] = regs->pc;
- gdb_regs[BFIN_RETX] = regs->retx;
- gdb_regs[BFIN_RETN] = regs->retn;
- gdb_regs[BFIN_RETE] = regs->rete;
- gdb_regs[BFIN_PC] = regs->pc;
- gdb_regs[BFIN_CC] = (regs->astat >> 5) & 1;
- gdb_regs[BFIN_EXTRA1] = 0;
- gdb_regs[BFIN_EXTRA2] = 0;
- gdb_regs[BFIN_EXTRA3] = 0;
- gdb_regs[BFIN_IPEND] = regs->ipend;
-}
-
-/*
- * Extracts ebp, esp and eip values understandable by gdb from the values
- * saved by switch_to.
- * thread.esp points to ebp. flags and ebp are pushed in switch_to hence esp
- * prior to entering switch_to is 8 greater than the value that is saved.
- * If switch_to changes, change following code appropriately.
- */
-void sleeping_thread_to_gdb_regs(unsigned long *gdb_regs, struct task_struct *p)
-{
- gdb_regs[BFIN_SP] = p->thread.ksp;
- gdb_regs[BFIN_PC] = p->thread.pc;
- gdb_regs[BFIN_SEQSTAT] = p->thread.seqstat;
-}
-
-void gdb_regs_to_pt_regs(unsigned long *gdb_regs, struct pt_regs *regs)
-{
- regs->r0 = gdb_regs[BFIN_R0];
- regs->r1 = gdb_regs[BFIN_R1];
- regs->r2 = gdb_regs[BFIN_R2];
- regs->r3 = gdb_regs[BFIN_R3];
- regs->r4 = gdb_regs[BFIN_R4];
- regs->r5 = gdb_regs[BFIN_R5];
- regs->r6 = gdb_regs[BFIN_R6];
- regs->r7 = gdb_regs[BFIN_R7];
- regs->p0 = gdb_regs[BFIN_P0];
- regs->p1 = gdb_regs[BFIN_P1];
- regs->p2 = gdb_regs[BFIN_P2];
- regs->p3 = gdb_regs[BFIN_P3];
- regs->p4 = gdb_regs[BFIN_P4];
- regs->p5 = gdb_regs[BFIN_P5];
- regs->fp = gdb_regs[BFIN_FP];
- regs->i0 = gdb_regs[BFIN_I0];
- regs->i1 = gdb_regs[BFIN_I1];
- regs->i2 = gdb_regs[BFIN_I2];
- regs->i3 = gdb_regs[BFIN_I3];
- regs->m0 = gdb_regs[BFIN_M0];
- regs->m1 = gdb_regs[BFIN_M1];
- regs->m2 = gdb_regs[BFIN_M2];
- regs->m3 = gdb_regs[BFIN_M3];
- regs->b0 = gdb_regs[BFIN_B0];
- regs->b1 = gdb_regs[BFIN_B1];
- regs->b2 = gdb_regs[BFIN_B2];
- regs->b3 = gdb_regs[BFIN_B3];
- regs->l0 = gdb_regs[BFIN_L0];
- regs->l1 = gdb_regs[BFIN_L1];
- regs->l2 = gdb_regs[BFIN_L2];
- regs->l3 = gdb_regs[BFIN_L3];
- regs->a0x = gdb_regs[BFIN_A0_DOT_X];
- regs->a0w = gdb_regs[BFIN_A0_DOT_W];
- regs->a1x = gdb_regs[BFIN_A1_DOT_X];
- regs->a1w = gdb_regs[BFIN_A1_DOT_W];
- regs->rets = gdb_regs[BFIN_RETS];
- regs->lc0 = gdb_regs[BFIN_LC0];
- regs->lt0 = gdb_regs[BFIN_LT0];
- regs->lb0 = gdb_regs[BFIN_LB0];
- regs->lc1 = gdb_regs[BFIN_LC1];
- regs->lt1 = gdb_regs[BFIN_LT1];
- regs->lb1 = gdb_regs[BFIN_LB1];
- regs->usp = gdb_regs[BFIN_USP];
- regs->syscfg = gdb_regs[BFIN_SYSCFG];
- regs->retx = gdb_regs[BFIN_RETX];
- regs->retn = gdb_regs[BFIN_RETN];
- regs->rete = gdb_regs[BFIN_RETE];
- regs->pc = gdb_regs[BFIN_PC];
-
-#if 0 /* can't change these */
- regs->astat = gdb_regs[BFIN_ASTAT];
- regs->seqstat = gdb_regs[BFIN_SEQSTAT];
- regs->ipend = gdb_regs[BFIN_IPEND];
-#endif
-}
-
-static struct hw_breakpoint {
- unsigned int occupied:1;
- unsigned int skip:1;
- unsigned int enabled:1;
- unsigned int type:1;
- unsigned int dataacc:2;
- unsigned short count;
- unsigned int addr;
-} breakinfo[HW_WATCHPOINT_NUM];
-
-static int bfin_set_hw_break(unsigned long addr, int len, enum kgdb_bptype type)
-{
- int breakno;
- int bfin_type;
- int dataacc = 0;
-
- switch (type) {
- case BP_HARDWARE_BREAKPOINT:
- bfin_type = TYPE_INST_WATCHPOINT;
- break;
- case BP_WRITE_WATCHPOINT:
- dataacc = 1;
- bfin_type = TYPE_DATA_WATCHPOINT;
- break;
- case BP_READ_WATCHPOINT:
- dataacc = 2;
- bfin_type = TYPE_DATA_WATCHPOINT;
- break;
- case BP_ACCESS_WATCHPOINT:
- dataacc = 3;
- bfin_type = TYPE_DATA_WATCHPOINT;
- break;
- default:
- return -ENOSPC;
- }
-
- /* Because hardware data watchpoint impelemented in current
- * Blackfin can not trigger an exception event as the hardware
- * instrction watchpoint does, we ignaore all data watch point here.
- * They can be turned on easily after future blackfin design
- * supports this feature.
- */
- for (breakno = 0; breakno < HW_INST_WATCHPOINT_NUM; breakno++)
- if (bfin_type == breakinfo[breakno].type
- && !breakinfo[breakno].occupied) {
- breakinfo[breakno].occupied = 1;
- breakinfo[breakno].skip = 0;
- breakinfo[breakno].enabled = 1;
- breakinfo[breakno].addr = addr;
- breakinfo[breakno].dataacc = dataacc;
- breakinfo[breakno].count = 0;
- return 0;
- }
-
- return -ENOSPC;
-}
-
-static int bfin_remove_hw_break(unsigned long addr, int len, enum kgdb_bptype type)
-{
- int breakno;
- int bfin_type;
-
- switch (type) {
- case BP_HARDWARE_BREAKPOINT:
- bfin_type = TYPE_INST_WATCHPOINT;
- break;
- case BP_WRITE_WATCHPOINT:
- case BP_READ_WATCHPOINT:
- case BP_ACCESS_WATCHPOINT:
- bfin_type = TYPE_DATA_WATCHPOINT;
- break;
- default:
- return 0;
- }
- for (breakno = 0; breakno < HW_WATCHPOINT_NUM; breakno++)
- if (bfin_type == breakinfo[breakno].type
- && breakinfo[breakno].occupied
- && breakinfo[breakno].addr == addr) {
- breakinfo[breakno].occupied = 0;
- breakinfo[breakno].enabled = 0;
- }
-
- return 0;
-}
-
-static void bfin_remove_all_hw_break(void)
-{
- int breakno;
-
- memset(breakinfo, 0, sizeof(struct hw_breakpoint)*HW_WATCHPOINT_NUM);
-
- for (breakno = 0; breakno < HW_INST_WATCHPOINT_NUM; breakno++)
- breakinfo[breakno].type = TYPE_INST_WATCHPOINT;
- for (; breakno < HW_WATCHPOINT_NUM; breakno++)
- breakinfo[breakno].type = TYPE_DATA_WATCHPOINT;
-}
-
-static void bfin_correct_hw_break(void)
-{
- int breakno;
- unsigned int wpiactl = 0;
- unsigned int wpdactl = 0;
- int enable_wp = 0;
-
- for (breakno = 0; breakno < HW_WATCHPOINT_NUM; breakno++)
- if (breakinfo[breakno].enabled) {
- enable_wp = 1;
-
- switch (breakno) {
- case 0:
- wpiactl |= WPIAEN0|WPICNTEN0;
- bfin_write_WPIA0(breakinfo[breakno].addr);
- bfin_write_WPIACNT0(breakinfo[breakno].count
- + breakinfo->skip);
- break;
- case 1:
- wpiactl |= WPIAEN1|WPICNTEN1;
- bfin_write_WPIA1(breakinfo[breakno].addr);
- bfin_write_WPIACNT1(breakinfo[breakno].count
- + breakinfo->skip);
- break;
- case 2:
- wpiactl |= WPIAEN2|WPICNTEN2;
- bfin_write_WPIA2(breakinfo[breakno].addr);
- bfin_write_WPIACNT2(breakinfo[breakno].count
- + breakinfo->skip);
- break;
- case 3:
- wpiactl |= WPIAEN3|WPICNTEN3;
- bfin_write_WPIA3(breakinfo[breakno].addr);
- bfin_write_WPIACNT3(breakinfo[breakno].count
- + breakinfo->skip);
- break;
- case 4:
- wpiactl |= WPIAEN4|WPICNTEN4;
- bfin_write_WPIA4(breakinfo[breakno].addr);
- bfin_write_WPIACNT4(breakinfo[breakno].count
- + breakinfo->skip);
- break;
- case 5:
- wpiactl |= WPIAEN5|WPICNTEN5;
- bfin_write_WPIA5(breakinfo[breakno].addr);
- bfin_write_WPIACNT5(breakinfo[breakno].count
- + breakinfo->skip);
- break;
- case 6:
- wpdactl |= WPDAEN0|WPDCNTEN0|WPDSRC0;
- wpdactl |= breakinfo[breakno].dataacc
- << WPDACC0_OFFSET;
- bfin_write_WPDA0(breakinfo[breakno].addr);
- bfin_write_WPDACNT0(breakinfo[breakno].count
- + breakinfo->skip);
- break;
- case 7:
- wpdactl |= WPDAEN1|WPDCNTEN1|WPDSRC1;
- wpdactl |= breakinfo[breakno].dataacc
- << WPDACC1_OFFSET;
- bfin_write_WPDA1(breakinfo[breakno].addr);
- bfin_write_WPDACNT1(breakinfo[breakno].count
- + breakinfo->skip);
- break;
- }
- }
-
- /* Should enable WPPWR bit first before set any other
- * WPIACTL and WPDACTL bits */
- if (enable_wp) {
- bfin_write_WPIACTL(WPPWR);
- CSYNC();
- bfin_write_WPIACTL(wpiactl|WPPWR);
- bfin_write_WPDACTL(wpdactl);
- CSYNC();
- }
-}
-
-static void bfin_disable_hw_debug(struct pt_regs *regs)
-{
- /* Disable hardware debugging while we are in kgdb */
- bfin_write_WPIACTL(0);
- bfin_write_WPDACTL(0);
- CSYNC();
-}
-
-#ifdef CONFIG_SMP
-void kgdb_passive_cpu_callback(void *info)
-{
- kgdb_nmicallback(raw_smp_processor_id(), get_irq_regs());
-}
-
-void kgdb_roundup_cpus(unsigned long flags)
-{
- unsigned int cpu;
-
- for (cpu = cpumask_first(cpu_online_mask); cpu < nr_cpu_ids;
- cpu = cpumask_next(cpu, cpu_online_mask))
- smp_call_function_single(cpu, kgdb_passive_cpu_callback,
- NULL, 0);
-}
-
-void kgdb_roundup_cpu(int cpu, unsigned long flags)
-{
- smp_call_function_single(cpu, kgdb_passive_cpu_callback, NULL, 0);
-}
-#endif
-
-#ifdef CONFIG_IPIPE
-static unsigned long kgdb_arch_imask;
-#endif
-
-int kgdb_arch_handle_exception(int vector, int signo,
- int err_code, char *remcom_in_buffer,
- char *remcom_out_buffer,
- struct pt_regs *regs)
-{
- long addr;
- char *ptr;
- int newPC;
- int i;
-
- switch (remcom_in_buffer[0]) {
- case 'c':
- case 's':
- if (kgdb_contthread && kgdb_contthread != current) {
- strcpy(remcom_out_buffer, "E00");
- break;
- }
-
- kgdb_contthread = NULL;
-
- /* try to read optional parameter, pc unchanged if no parm */
- ptr = &remcom_in_buffer[1];
- if (kgdb_hex2long(&ptr, &addr)) {
- regs->retx = addr;
- }
- newPC = regs->retx;
-
- /* clear the trace bit */
- regs->syscfg &= 0xfffffffe;
-
- /* set the trace bit if we're stepping */
- if (remcom_in_buffer[0] == 's') {
- regs->syscfg |= 0x1;
- kgdb_single_step = regs->ipend;
- kgdb_single_step >>= 6;
- for (i = 10; i > 0; i--, kgdb_single_step >>= 1)
- if (kgdb_single_step & 1)
- break;
- /* i indicate event priority of current stopped instruction
- * user space instruction is 0, IVG15 is 1, IVTMR is 10.
- * kgdb_single_step > 0 means in single step mode
- */
- kgdb_single_step = i + 1;
-
- preempt_disable();
-#ifdef CONFIG_IPIPE
- kgdb_arch_imask = cpu_pda[raw_smp_processor_id()].ex_imask;
- cpu_pda[raw_smp_processor_id()].ex_imask = 0;
-#endif
- }
-
- bfin_correct_hw_break();
-
- return 0;
- } /* switch */
- return -1; /* this means that we do not want to exit from the handler */
-}
-
-struct kgdb_arch arch_kgdb_ops = {
- .gdb_bpt_instr = {0xa1},
- .flags = KGDB_HW_BREAKPOINT,
- .set_hw_breakpoint = bfin_set_hw_break,
- .remove_hw_breakpoint = bfin_remove_hw_break,
- .disable_hw_break = bfin_disable_hw_debug,
- .remove_all_hw_break = bfin_remove_all_hw_break,
- .correct_hw_break = bfin_correct_hw_break,
-};
-
-#define IN_MEM(addr, size, l1_addr, l1_size) \
-({ \
- unsigned long __addr = (unsigned long)(addr); \
- (l1_size && __addr >= l1_addr && __addr + (size) <= l1_addr + l1_size); \
-})
-#define ASYNC_BANK_SIZE \
- (ASYNC_BANK0_SIZE + ASYNC_BANK1_SIZE + \
- ASYNC_BANK2_SIZE + ASYNC_BANK3_SIZE)
-
-int kgdb_validate_break_address(unsigned long addr)
-{
- int cpu = raw_smp_processor_id();
-
- if (addr >= 0x1000 && (addr + BREAK_INSTR_SIZE) <= physical_mem_end)
- return 0;
- if (IN_MEM(addr, BREAK_INSTR_SIZE, ASYNC_BANK0_BASE, ASYNC_BANK_SIZE))
- return 0;
- if (cpu == 0 && IN_MEM(addr, BREAK_INSTR_SIZE, L1_CODE_START, L1_CODE_LENGTH))
- return 0;
-#ifdef CONFIG_SMP
- else if (cpu == 1 && IN_MEM(addr, BREAK_INSTR_SIZE, COREB_L1_CODE_START, L1_CODE_LENGTH))
- return 0;
-#endif
- if (IN_MEM(addr, BREAK_INSTR_SIZE, L2_START, L2_LENGTH))
- return 0;
-
- return -EFAULT;
-}
-
-void kgdb_arch_set_pc(struct pt_regs *regs, unsigned long ip)
-{
- regs->retx = ip;
-}
-
-int kgdb_arch_init(void)
-{
- kgdb_single_step = 0;
-#ifdef CONFIG_IPIPE
- kgdb_arch_imask = 0;
-#endif
-
- bfin_remove_all_hw_break();
- return 0;
-}
-
-void kgdb_arch_exit(void)
-{
-}
+++ /dev/null
-/*
- * arch/blackfin/kernel/kgdb_test.c - Blackfin kgdb tests
- *
- * Copyright 2005-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/proc_fs.h>
-
-#include <asm/current.h>
-#include <linux/uaccess.h>
-
-#include <asm/blackfin.h>
-
-/* Symbols are here for kgdb test to poke directly */
-static char cmdline[256];
-static size_t len;
-
-#ifndef CONFIG_SMP
-static int num1 __attribute__((l1_data));
-
-void kgdb_l1_test(void) __attribute__((l1_text));
-
-void kgdb_l1_test(void)
-{
- pr_alert("L1(before change) : data variable addr = 0x%p, data value is %d\n", &num1, num1);
- pr_alert("L1 : code function addr = 0x%p\n", kgdb_l1_test);
- num1 = num1 + 10;
- pr_alert("L1(after change) : data variable addr = 0x%p, data value is %d\n", &num1, num1);
-}
-#endif
-
-#if L2_LENGTH
-
-static int num2 __attribute__((l2));
-void kgdb_l2_test(void) __attribute__((l2));
-
-void kgdb_l2_test(void)
-{
- pr_alert("L2(before change) : data variable addr = 0x%p, data value is %d\n", &num2, num2);
- pr_alert("L2 : code function addr = 0x%p\n", kgdb_l2_test);
- num2 = num2 + 20;
- pr_alert("L2(after change) : data variable addr = 0x%p, data value is %d\n", &num2, num2);
-}
-
-#endif
-
-noinline int kgdb_test(char *name, int len, int count, int z)
-{
- pr_alert("kgdb name(%d): %s, %d, %d\n", len, name, count, z);
- count = z;
- return count;
-}
-
-static ssize_t
-kgdb_test_proc_read(struct file *file, char __user *buf,
- size_t count, loff_t *ppos)
-{
- kgdb_test("hello world!", 12, 0x55, 0x10);
-#ifndef CONFIG_SMP
- kgdb_l1_test();
-#endif
-#if L2_LENGTH
- kgdb_l2_test();
-#endif
-
- return 0;
-}
-
-static ssize_t
-kgdb_test_proc_write(struct file *file, const char __user *buffer,
- size_t count, loff_t *pos)
-{
- len = min_t(size_t, 255, count);
- memcpy(cmdline, buffer, count);
- cmdline[len] = 0;
-
- return len;
-}
-
-static const struct file_operations kgdb_test_proc_fops = {
- .owner = THIS_MODULE,
- .read = kgdb_test_proc_read,
- .write = kgdb_test_proc_write,
- .llseek = noop_llseek,
-};
-
-static int __init kgdbtest_init(void)
-{
- struct proc_dir_entry *entry;
-
-#if L2_LENGTH
- num2 = 0;
-#endif
-
- entry = proc_create("kgdbtest", 0, NULL, &kgdb_test_proc_fops);
- if (entry == NULL)
- return -ENOMEM;
-
- return 0;
-}
-
-static void __exit kgdbtest_exit(void)
-{
- remove_proc_entry("kgdbtest", NULL);
-}
-
-module_init(kgdbtest_init);
-module_exit(kgdbtest_exit);
-MODULE_LICENSE("GPL");
+++ /dev/null
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <linux/moduleloader.h>
-#include <linux/elf.h>
-#include <linux/vmalloc.h>
-#include <linux/fs.h>
-#include <linux/string.h>
-#include <linux/kernel.h>
-#include <asm/dma.h>
-#include <asm/cacheflush.h>
-#include <linux/uaccess.h>
-
-#define mod_err(mod, fmt, ...) \
- pr_err("module %s: " fmt, (mod)->name, ##__VA_ARGS__)
-#define mod_debug(mod, fmt, ...) \
- pr_debug("module %s: " fmt, (mod)->name, ##__VA_ARGS__)
-
-/* Transfer the section to the L1 memory */
-int
-module_frob_arch_sections(Elf_Ehdr *hdr, Elf_Shdr *sechdrs,
- char *secstrings, struct module *mod)
-{
- /*
- * XXX: sechdrs are vmalloced in kernel/module.c
- * and would be vfreed just after module is loaded,
- * so we hack to keep the only information we needed
- * in mod->arch to correctly free L1 I/D sram later.
- * NOTE: this breaks the semantic of mod->arch structure.
- */
- Elf_Shdr *s, *sechdrs_end = sechdrs + hdr->e_shnum;
- void *dest;
-
- for (s = sechdrs; s < sechdrs_end; ++s) {
- const char *shname = secstrings + s->sh_name;
-
- if (s->sh_size == 0)
- continue;
-
- if (!strcmp(".l1.text", shname) ||
- (!strcmp(".text", shname) &&
- (hdr->e_flags & EF_BFIN_CODE_IN_L1))) {
-
- dest = l1_inst_sram_alloc(s->sh_size);
- mod->arch.text_l1 = dest;
- if (dest == NULL) {
- mod_err(mod, "L1 inst memory allocation failed\n");
- return -1;
- }
- dma_memcpy(dest, (void *)s->sh_addr, s->sh_size);
-
- } else if (!strcmp(".l1.data", shname) ||
- (!strcmp(".data", shname) &&
- (hdr->e_flags & EF_BFIN_DATA_IN_L1))) {
-
- dest = l1_data_sram_alloc(s->sh_size);
- mod->arch.data_a_l1 = dest;
- if (dest == NULL) {
- mod_err(mod, "L1 data memory allocation failed\n");
- return -1;
- }
- memcpy(dest, (void *)s->sh_addr, s->sh_size);
-
- } else if (!strcmp(".l1.bss", shname) ||
- (!strcmp(".bss", shname) &&
- (hdr->e_flags & EF_BFIN_DATA_IN_L1))) {
-
- dest = l1_data_sram_zalloc(s->sh_size);
- mod->arch.bss_a_l1 = dest;
- if (dest == NULL) {
- mod_err(mod, "L1 data memory allocation failed\n");
- return -1;
- }
-
- } else if (!strcmp(".l1.data.B", shname)) {
-
- dest = l1_data_B_sram_alloc(s->sh_size);
- mod->arch.data_b_l1 = dest;
- if (dest == NULL) {
- mod_err(mod, "L1 data memory allocation failed\n");
- return -1;
- }
- memcpy(dest, (void *)s->sh_addr, s->sh_size);
-
- } else if (!strcmp(".l1.bss.B", shname)) {
-
- dest = l1_data_B_sram_alloc(s->sh_size);
- mod->arch.bss_b_l1 = dest;
- if (dest == NULL) {
- mod_err(mod, "L1 data memory allocation failed\n");
- return -1;
- }
- memset(dest, 0, s->sh_size);
-
- } else if (!strcmp(".l2.text", shname) ||
- (!strcmp(".text", shname) &&
- (hdr->e_flags & EF_BFIN_CODE_IN_L2))) {
-
- dest = l2_sram_alloc(s->sh_size);
- mod->arch.text_l2 = dest;
- if (dest == NULL) {
- mod_err(mod, "L2 SRAM allocation failed\n");
- return -1;
- }
- memcpy(dest, (void *)s->sh_addr, s->sh_size);
-
- } else if (!strcmp(".l2.data", shname) ||
- (!strcmp(".data", shname) &&
- (hdr->e_flags & EF_BFIN_DATA_IN_L2))) {
-
- dest = l2_sram_alloc(s->sh_size);
- mod->arch.data_l2 = dest;
- if (dest == NULL) {
- mod_err(mod, "L2 SRAM allocation failed\n");
- return -1;
- }
- memcpy(dest, (void *)s->sh_addr, s->sh_size);
-
- } else if (!strcmp(".l2.bss", shname) ||
- (!strcmp(".bss", shname) &&
- (hdr->e_flags & EF_BFIN_DATA_IN_L2))) {
-
- dest = l2_sram_zalloc(s->sh_size);
- mod->arch.bss_l2 = dest;
- if (dest == NULL) {
- mod_err(mod, "L2 SRAM allocation failed\n");
- return -1;
- }
-
- } else
- continue;
-
- s->sh_flags &= ~SHF_ALLOC;
- s->sh_addr = (unsigned long)dest;
- }
-
- return 0;
-}
-
-/*************************************************************************/
-/* FUNCTION : apply_relocate_add */
-/* ABSTRACT : Blackfin specific relocation handling for the loadable */
-/* modules. Modules are expected to be .o files. */
-/* Arithmetic relocations are handled. */
-/* We do not expect LSETUP to be split and hence is not */
-/* handled. */
-/* R_BFIN_BYTE and R_BFIN_BYTE2 are also not handled as the */
-/* gas does not generate it. */
-/*************************************************************************/
-int
-apply_relocate_add(Elf_Shdr *sechdrs, const char *strtab,
- unsigned int symindex, unsigned int relsec,
- struct module *mod)
-{
- unsigned int i;
- Elf32_Rela *rel = (void *)sechdrs[relsec].sh_addr;
- Elf32_Sym *sym;
- unsigned long location, value, size;
-
- mod_debug(mod, "applying relocate section %u to %u\n",
- relsec, sechdrs[relsec].sh_info);
-
- for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) {
- /* This is where to make the change */
- location = sechdrs[sechdrs[relsec].sh_info].sh_addr +
- rel[i].r_offset;
-
- /* This is the symbol it is referring to. Note that all
- undefined symbols have been resolved. */
- sym = (Elf32_Sym *) sechdrs[symindex].sh_addr
- + ELF32_R_SYM(rel[i].r_info);
- value = sym->st_value;
- value += rel[i].r_addend;
-
-#ifdef CONFIG_SMP
- if (location >= COREB_L1_DATA_A_START) {
- mod_err(mod, "cannot relocate in L1: %u (SMP kernel)\n",
- ELF32_R_TYPE(rel[i].r_info));
- return -ENOEXEC;
- }
-#endif
-
- mod_debug(mod, "location is %lx, value is %lx type is %d\n",
- location, value, ELF32_R_TYPE(rel[i].r_info));
-
- switch (ELF32_R_TYPE(rel[i].r_info)) {
-
- case R_BFIN_HUIMM16:
- value >>= 16;
- case R_BFIN_LUIMM16:
- case R_BFIN_RIMM16:
- size = 2;
- break;
- case R_BFIN_BYTE4_DATA:
- size = 4;
- break;
-
- case R_BFIN_PCREL24:
- case R_BFIN_PCREL24_JUMP_L:
- case R_BFIN_PCREL12_JUMP:
- case R_BFIN_PCREL12_JUMP_S:
- case R_BFIN_PCREL10:
- mod_err(mod, "unsupported relocation: %u (no -mlong-calls?)\n",
- ELF32_R_TYPE(rel[i].r_info));
- return -ENOEXEC;
-
- default:
- mod_err(mod, "unknown relocation: %u\n",
- ELF32_R_TYPE(rel[i].r_info));
- return -ENOEXEC;
- }
-
- switch (bfin_mem_access_type(location, size)) {
- case BFIN_MEM_ACCESS_CORE:
- case BFIN_MEM_ACCESS_CORE_ONLY:
- memcpy((void *)location, &value, size);
- break;
- case BFIN_MEM_ACCESS_DMA:
- dma_memcpy((void *)location, &value, size);
- break;
- case BFIN_MEM_ACCESS_ITEST:
- isram_memcpy((void *)location, &value, size);
- break;
- default:
- mod_err(mod, "invalid relocation for %#lx\n", location);
- return -ENOEXEC;
- }
- }
-
- return 0;
-}
-
-int
-module_finalize(const Elf_Ehdr * hdr,
- const Elf_Shdr * sechdrs, struct module *mod)
-{
- unsigned int i, strindex = 0, symindex = 0;
- char *secstrings;
- long err = 0;
-
- secstrings = (void *)hdr + sechdrs[hdr->e_shstrndx].sh_offset;
-
- for (i = 1; i < hdr->e_shnum; i++) {
- /* Internal symbols and strings. */
- if (sechdrs[i].sh_type == SHT_SYMTAB) {
- symindex = i;
- strindex = sechdrs[i].sh_link;
- }
- }
-
- for (i = 1; i < hdr->e_shnum; i++) {
- const char *strtab = (char *)sechdrs[strindex].sh_addr;
- unsigned int info = sechdrs[i].sh_info;
- const char *shname = secstrings + sechdrs[i].sh_name;
-
- /* Not a valid relocation section? */
- if (info >= hdr->e_shnum)
- continue;
-
- /* Only support RELA relocation types */
- if (sechdrs[i].sh_type != SHT_RELA)
- continue;
-
- if (!strcmp(".rela.l2.text", shname) ||
- !strcmp(".rela.l1.text", shname) ||
- (!strcmp(".rela.text", shname) &&
- (hdr->e_flags & (EF_BFIN_CODE_IN_L1 | EF_BFIN_CODE_IN_L2)))) {
-
- err = apply_relocate_add((Elf_Shdr *) sechdrs, strtab,
- symindex, i, mod);
- if (err < 0)
- return -ENOEXEC;
- }
- }
-
- return 0;
-}
-
-void module_arch_cleanup(struct module *mod)
-{
- l1_inst_sram_free(mod->arch.text_l1);
- l1_data_A_sram_free(mod->arch.data_a_l1);
- l1_data_A_sram_free(mod->arch.bss_a_l1);
- l1_data_B_sram_free(mod->arch.data_b_l1);
- l1_data_B_sram_free(mod->arch.bss_b_l1);
- l2_sram_free(mod->arch.text_l2);
- l2_sram_free(mod->arch.data_l2);
- l2_sram_free(mod->arch.bss_l2);
-}
+++ /dev/null
-/*
- * Blackfin nmi_watchdog Driver
- *
- * Originally based on bfin_wdt.c
- * Copyright 2010-2010 Analog Devices Inc.
- * Graff Yang <graf.yang@analog.com>
- *
- * Enter bugs at http://blackfin.uclinux.org/
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/bitops.h>
-#include <linux/hardirq.h>
-#include <linux/syscore_ops.h>
-#include <linux/pm.h>
-#include <linux/nmi.h>
-#include <linux/smp.h>
-#include <linux/timer.h>
-#include <linux/sched/debug.h>
-#include <asm/blackfin.h>
-#include <linux/atomic.h>
-#include <asm/cacheflush.h>
-#include <asm/bfin_watchdog.h>
-
-#define DRV_NAME "nmi-wdt"
-
-#define NMI_WDT_TIMEOUT 5 /* 5 seconds */
-#define NMI_CHECK_TIMEOUT (4 * HZ) /* 4 seconds in jiffies */
-static int nmi_wdt_cpu = 1;
-
-static unsigned int timeout = NMI_WDT_TIMEOUT;
-static int nmi_active;
-
-static unsigned short wdoga_ctl;
-static unsigned int wdoga_cnt;
-static struct corelock_slot saved_corelock;
-static atomic_t nmi_touched[NR_CPUS];
-static struct timer_list ntimer;
-
-enum {
- COREA_ENTER_NMI = 0,
- COREA_EXIT_NMI,
- COREB_EXIT_NMI,
-
- NMI_EVENT_NR,
-};
-static unsigned long nmi_event __attribute__ ((__section__(".l2.bss")));
-
-/* we are in nmi, non-atomic bit ops is safe */
-static inline void set_nmi_event(int event)
-{
- __set_bit(event, &nmi_event);
-}
-
-static inline void wait_nmi_event(int event)
-{
- while (!test_bit(event, &nmi_event))
- barrier();
- __clear_bit(event, &nmi_event);
-}
-
-static inline void send_corea_nmi(void)
-{
- wdoga_ctl = bfin_read_WDOGA_CTL();
- wdoga_cnt = bfin_read_WDOGA_CNT();
-
- bfin_write_WDOGA_CTL(WDEN_DISABLE);
- bfin_write_WDOGA_CNT(0);
- bfin_write_WDOGA_CTL(WDEN_ENABLE | ICTL_NMI);
-}
-
-static inline void restore_corea_nmi(void)
-{
- bfin_write_WDOGA_CTL(WDEN_DISABLE);
- bfin_write_WDOGA_CTL(WDOG_EXPIRED | WDEN_DISABLE | ICTL_NONE);
-
- bfin_write_WDOGA_CNT(wdoga_cnt);
- bfin_write_WDOGA_CTL(wdoga_ctl);
-}
-
-static inline void save_corelock(void)
-{
- saved_corelock = corelock;
- corelock.lock = 0;
-}
-
-static inline void restore_corelock(void)
-{
- corelock = saved_corelock;
-}
-
-
-static inline void nmi_wdt_keepalive(void)
-{
- bfin_write_WDOGB_STAT(0);
-}
-
-static inline void nmi_wdt_stop(void)
-{
- bfin_write_WDOGB_CTL(WDEN_DISABLE);
-}
-
-/* before calling this function, you must stop the WDT */
-static inline void nmi_wdt_clear(void)
-{
- /* clear TRO bit, disable event generation */
- bfin_write_WDOGB_CTL(WDOG_EXPIRED | WDEN_DISABLE | ICTL_NONE);
-}
-
-static inline void nmi_wdt_start(void)
-{
- bfin_write_WDOGB_CTL(WDEN_ENABLE | ICTL_NMI);
-}
-
-static inline int nmi_wdt_running(void)
-{
- return ((bfin_read_WDOGB_CTL() & WDEN_MASK) != WDEN_DISABLE);
-}
-
-static inline int nmi_wdt_set_timeout(unsigned long t)
-{
- u32 cnt, max_t, sclk;
- int run;
-
- sclk = get_sclk();
- max_t = -1 / sclk;
- cnt = t * sclk;
- if (t > max_t) {
- pr_warning("NMI: timeout value is too large\n");
- return -EINVAL;
- }
-
- run = nmi_wdt_running();
- nmi_wdt_stop();
- bfin_write_WDOGB_CNT(cnt);
- if (run)
- nmi_wdt_start();
-
- timeout = t;
-
- return 0;
-}
-
-int check_nmi_wdt_touched(void)
-{
- unsigned int this_cpu = smp_processor_id();
- unsigned int cpu;
- cpumask_t mask;
-
- cpumask_copy(&mask, cpu_online_mask);
- if (!atomic_read(&nmi_touched[this_cpu]))
- return 0;
-
- atomic_set(&nmi_touched[this_cpu], 0);
-
- cpumask_clear_cpu(this_cpu, &mask);
- for_each_cpu(cpu, &mask) {
- invalidate_dcache_range((unsigned long)(&nmi_touched[cpu]),
- (unsigned long)(&nmi_touched[cpu]));
- if (!atomic_read(&nmi_touched[cpu]))
- return 0;
- atomic_set(&nmi_touched[cpu], 0);
- }
-
- return 1;
-}
-
-static void nmi_wdt_timer(struct timer_list *unused)
-{
- if (check_nmi_wdt_touched())
- nmi_wdt_keepalive();
-
- mod_timer(&ntimer, jiffies + NMI_CHECK_TIMEOUT);
-}
-
-static int __init init_nmi_wdt(void)
-{
- nmi_wdt_set_timeout(timeout);
- nmi_wdt_start();
- nmi_active = true;
-
- timer_setup(&ntimer, nmi_wdt_timer, 0);
- ntimer.expires = jiffies + NMI_CHECK_TIMEOUT;
- add_timer(&ntimer);
-
- pr_info("nmi_wdt: initialized: timeout=%d sec\n", timeout);
- return 0;
-}
-device_initcall(init_nmi_wdt);
-
-void arch_touch_nmi_watchdog(void)
-{
- atomic_set(&nmi_touched[smp_processor_id()], 1);
-}
-
-/* Suspend/resume support */
-#ifdef CONFIG_PM
-static int nmi_wdt_suspend(void)
-{
- nmi_wdt_stop();
- return 0;
-}
-
-static void nmi_wdt_resume(void)
-{
- if (nmi_active)
- nmi_wdt_start();
-}
-
-static struct syscore_ops nmi_syscore_ops = {
- .resume = nmi_wdt_resume,
- .suspend = nmi_wdt_suspend,
-};
-
-static int __init init_nmi_wdt_syscore(void)
-{
- if (nmi_active)
- register_syscore_ops(&nmi_syscore_ops);
-
- return 0;
-}
-late_initcall(init_nmi_wdt_syscore);
-
-#endif /* CONFIG_PM */
-
-
-asmlinkage notrace void do_nmi(struct pt_regs *fp)
-{
- unsigned int cpu = smp_processor_id();
- nmi_enter();
-
- cpu_pda[cpu].__nmi_count += 1;
-
- if (cpu == nmi_wdt_cpu) {
- /* CoreB goes here first */
-
- /* reload the WDOG_STAT */
- nmi_wdt_keepalive();
-
- /* clear nmi interrupt for CoreB */
- nmi_wdt_stop();
- nmi_wdt_clear();
-
- /* trigger NMI interrupt of CoreA */
- send_corea_nmi();
-
- /* waiting CoreB to enter NMI */
- wait_nmi_event(COREA_ENTER_NMI);
-
- /* recover WDOGA's settings */
- restore_corea_nmi();
-
- save_corelock();
-
- /* corelock is save/cleared, CoreA is dummping messages */
-
- wait_nmi_event(COREA_EXIT_NMI);
- } else {
- /* OK, CoreA entered NMI */
- set_nmi_event(COREA_ENTER_NMI);
- }
-
- pr_emerg("\nNMI Watchdog detected LOCKUP, dump for CPU %d\n", cpu);
- dump_bfin_process(fp);
- dump_bfin_mem(fp);
- show_regs(fp);
- dump_bfin_trace_buffer();
- show_stack(current, (unsigned long *)fp);
-
- if (cpu == nmi_wdt_cpu) {
- pr_emerg("This fault is not recoverable, sorry!\n");
-
- /* CoreA dump finished, restore the corelock */
- restore_corelock();
-
- set_nmi_event(COREB_EXIT_NMI);
- } else {
- /* CoreB dump finished, notice the CoreA we are done */
- set_nmi_event(COREA_EXIT_NMI);
-
- /* synchronize with CoreA */
- wait_nmi_event(COREB_EXIT_NMI);
- }
-
- nmi_exit();
-}
+++ /dev/null
-/*
- * Blackfin performance counters
- *
- * Copyright 2011 Analog Devices Inc.
- *
- * Ripped from SuperH version:
- *
- * Copyright (C) 2009 Paul Mundt
- *
- * Heavily based on the x86 and PowerPC implementations.
- *
- * x86:
- * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
- * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
- * Copyright (C) 2009 Jaswinder Singh Rajput
- * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
- * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra
- * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
- *
- * ppc:
- * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/kernel.h>
-#include <linux/export.h>
-#include <linux/init.h>
-#include <linux/perf_event.h>
-#include <asm/bfin_pfmon.h>
-
-/*
- * We have two counters, and each counter can support an event type.
- * The 'o' is PFCNTx=1 and 's' is PFCNTx=0
- *
- * 0x04 o pc invariant branches
- * 0x06 o mispredicted branches
- * 0x09 o predicted branches taken
- * 0x0B o EXCPT insn
- * 0x0C o CSYNC/SSYNC insn
- * 0x0D o Insns committed
- * 0x0E o Interrupts taken
- * 0x0F o Misaligned address exceptions
- * 0x80 o Code memory fetches stalled due to DMA
- * 0x83 o 64bit insn fetches delivered
- * 0x9A o data cache fills (bank a)
- * 0x9B o data cache fills (bank b)
- * 0x9C o data cache lines evicted (bank a)
- * 0x9D o data cache lines evicted (bank b)
- * 0x9E o data cache high priority fills
- * 0x9F o data cache low priority fills
- * 0x00 s loop 0 iterations
- * 0x01 s loop 1 iterations
- * 0x0A s CSYNC/SSYNC stalls
- * 0x10 s DAG read/after write hazards
- * 0x13 s RAW data hazards
- * 0x81 s code TAG stalls
- * 0x82 s code fill stalls
- * 0x90 s processor to memory stalls
- * 0x91 s data memory stalls not hidden by 0x90
- * 0x92 s data store buffer full stalls
- * 0x93 s data memory write buffer full stalls due to high->low priority
- * 0x95 s data memory fill buffer stalls
- * 0x96 s data TAG collision stalls
- * 0x97 s data collision stalls
- * 0x98 s data stalls
- * 0x99 s data stalls sent to processor
- */
-
-static const int event_map[] = {
- /* use CYCLES cpu register */
- [PERF_COUNT_HW_CPU_CYCLES] = -1,
- [PERF_COUNT_HW_INSTRUCTIONS] = 0x0D,
- [PERF_COUNT_HW_CACHE_REFERENCES] = -1,
- [PERF_COUNT_HW_CACHE_MISSES] = 0x83,
- [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x09,
- [PERF_COUNT_HW_BRANCH_MISSES] = 0x06,
- [PERF_COUNT_HW_BUS_CYCLES] = -1,
-};
-
-#define C(x) PERF_COUNT_HW_CACHE_##x
-
-static const int cache_events[PERF_COUNT_HW_CACHE_MAX]
- [PERF_COUNT_HW_CACHE_OP_MAX]
- [PERF_COUNT_HW_CACHE_RESULT_MAX] =
-{
- [C(L1D)] = { /* Data bank A */
- [C(OP_READ)] = {
- [C(RESULT_ACCESS)] = 0,
- [C(RESULT_MISS) ] = 0x9A,
- },
- [C(OP_WRITE)] = {
- [C(RESULT_ACCESS)] = 0,
- [C(RESULT_MISS) ] = 0,
- },
- [C(OP_PREFETCH)] = {
- [C(RESULT_ACCESS)] = 0,
- [C(RESULT_MISS) ] = 0,
- },
- },
-
- [C(L1I)] = {
- [C(OP_READ)] = {
- [C(RESULT_ACCESS)] = 0,
- [C(RESULT_MISS) ] = 0x83,
- },
- [C(OP_WRITE)] = {
- [C(RESULT_ACCESS)] = -1,
- [C(RESULT_MISS) ] = -1,
- },
- [C(OP_PREFETCH)] = {
- [C(RESULT_ACCESS)] = 0,
- [C(RESULT_MISS) ] = 0,
- },
- },
-
- [C(LL)] = {
- [C(OP_READ)] = {
- [C(RESULT_ACCESS)] = -1,
- [C(RESULT_MISS) ] = -1,
- },
- [C(OP_WRITE)] = {
- [C(RESULT_ACCESS)] = -1,
- [C(RESULT_MISS) ] = -1,
- },
- [C(OP_PREFETCH)] = {
- [C(RESULT_ACCESS)] = -1,
- [C(RESULT_MISS) ] = -1,
- },
- },
-
- [C(DTLB)] = {
- [C(OP_READ)] = {
- [C(RESULT_ACCESS)] = -1,
- [C(RESULT_MISS) ] = -1,
- },
- [C(OP_WRITE)] = {
- [C(RESULT_ACCESS)] = -1,
- [C(RESULT_MISS) ] = -1,
- },
- [C(OP_PREFETCH)] = {
- [C(RESULT_ACCESS)] = -1,
- [C(RESULT_MISS) ] = -1,
- },
- },
-
- [C(ITLB)] = {
- [C(OP_READ)] = {
- [C(RESULT_ACCESS)] = -1,
- [C(RESULT_MISS) ] = -1,
- },
- [C(OP_WRITE)] = {
- [C(RESULT_ACCESS)] = -1,
- [C(RESULT_MISS) ] = -1,
- },
- [C(OP_PREFETCH)] = {
- [C(RESULT_ACCESS)] = -1,
- [C(RESULT_MISS) ] = -1,
- },
- },
-
- [C(BPU)] = {
- [C(OP_READ)] = {
- [C(RESULT_ACCESS)] = -1,
- [C(RESULT_MISS) ] = -1,
- },
- [C(OP_WRITE)] = {
- [C(RESULT_ACCESS)] = -1,
- [C(RESULT_MISS) ] = -1,
- },
- [C(OP_PREFETCH)] = {
- [C(RESULT_ACCESS)] = -1,
- [C(RESULT_MISS) ] = -1,
- },
- },
-};
-
-const char *perf_pmu_name(void)
-{
- return "bfin";
-}
-EXPORT_SYMBOL(perf_pmu_name);
-
-int perf_num_counters(void)
-{
- return ARRAY_SIZE(event_map);
-}
-EXPORT_SYMBOL(perf_num_counters);
-
-static u64 bfin_pfmon_read(int idx)
-{
- return bfin_read32(PFCNTR0 + (idx * 4));
-}
-
-static void bfin_pfmon_disable(struct hw_perf_event *hwc, int idx)
-{
- bfin_write_PFCTL(bfin_read_PFCTL() & ~PFCEN(idx, PFCEN_MASK));
-}
-
-static void bfin_pfmon_enable(struct hw_perf_event *hwc, int idx)
-{
- u32 val, mask;
-
- val = PFPWR;
- if (idx) {
- mask = ~(PFCNT1 | PFMON1 | PFCEN1 | PEMUSW1);
- /* The packed config is for event0, so shift it to event1 slots */
- val |= (hwc->config << (PFMON1_P - PFMON0_P));
- val |= (hwc->config & PFCNT0) << (PFCNT1_P - PFCNT0_P);
- bfin_write_PFCNTR1(0);
- } else {
- mask = ~(PFCNT0 | PFMON0 | PFCEN0 | PEMUSW0);
- val |= hwc->config;
- bfin_write_PFCNTR0(0);
- }
-
- bfin_write_PFCTL((bfin_read_PFCTL() & mask) | val);
-}
-
-static void bfin_pfmon_disable_all(void)
-{
- bfin_write_PFCTL(bfin_read_PFCTL() & ~PFPWR);
-}
-
-static void bfin_pfmon_enable_all(void)
-{
- bfin_write_PFCTL(bfin_read_PFCTL() | PFPWR);
-}
-
-struct cpu_hw_events {
- struct perf_event *events[MAX_HWEVENTS];
- unsigned long used_mask[BITS_TO_LONGS(MAX_HWEVENTS)];
-};
-DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
-
-static int hw_perf_cache_event(int config, int *evp)
-{
- unsigned long type, op, result;
- int ev;
-
- /* unpack config */
- type = config & 0xff;
- op = (config >> 8) & 0xff;
- result = (config >> 16) & 0xff;
-
- if (type >= PERF_COUNT_HW_CACHE_MAX ||
- op >= PERF_COUNT_HW_CACHE_OP_MAX ||
- result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
- return -EINVAL;
-
- ev = cache_events[type][op][result];
- if (ev == 0)
- return -EOPNOTSUPP;
- if (ev == -1)
- return -EINVAL;
- *evp = ev;
- return 0;
-}
-
-static void bfin_perf_event_update(struct perf_event *event,
- struct hw_perf_event *hwc, int idx)
-{
- u64 prev_raw_count, new_raw_count;
- s64 delta;
- int shift = 0;
-
- /*
- * Depending on the counter configuration, they may or may not
- * be chained, in which case the previous counter value can be
- * updated underneath us if the lower-half overflows.
- *
- * Our tactic to handle this is to first atomically read and
- * exchange a new raw count - then add that new-prev delta
- * count to the generic counter atomically.
- *
- * As there is no interrupt associated with the overflow events,
- * this is the simplest approach for maintaining consistency.
- */
-again:
- prev_raw_count = local64_read(&hwc->prev_count);
- new_raw_count = bfin_pfmon_read(idx);
-
- if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
- new_raw_count) != prev_raw_count)
- goto again;
-
- /*
- * Now we have the new raw value and have updated the prev
- * timestamp already. We can now calculate the elapsed delta
- * (counter-)time and add that to the generic counter.
- *
- * Careful, not all hw sign-extends above the physical width
- * of the count.
- */
- delta = (new_raw_count << shift) - (prev_raw_count << shift);
- delta >>= shift;
-
- local64_add(delta, &event->count);
-}
-
-static void bfin_pmu_stop(struct perf_event *event, int flags)
-{
- struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
- struct hw_perf_event *hwc = &event->hw;
- int idx = hwc->idx;
-
- if (!(event->hw.state & PERF_HES_STOPPED)) {
- bfin_pfmon_disable(hwc, idx);
- cpuc->events[idx] = NULL;
- event->hw.state |= PERF_HES_STOPPED;
- }
-
- if ((flags & PERF_EF_UPDATE) && !(event->hw.state & PERF_HES_UPTODATE)) {
- bfin_perf_event_update(event, &event->hw, idx);
- event->hw.state |= PERF_HES_UPTODATE;
- }
-}
-
-static void bfin_pmu_start(struct perf_event *event, int flags)
-{
- struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
- struct hw_perf_event *hwc = &event->hw;
- int idx = hwc->idx;
-
- if (WARN_ON_ONCE(idx == -1))
- return;
-
- if (flags & PERF_EF_RELOAD)
- WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
-
- cpuc->events[idx] = event;
- event->hw.state = 0;
- bfin_pfmon_enable(hwc, idx);
-}
-
-static void bfin_pmu_del(struct perf_event *event, int flags)
-{
- struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
-
- bfin_pmu_stop(event, PERF_EF_UPDATE);
- __clear_bit(event->hw.idx, cpuc->used_mask);
-
- perf_event_update_userpage(event);
-}
-
-static int bfin_pmu_add(struct perf_event *event, int flags)
-{
- struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
- struct hw_perf_event *hwc = &event->hw;
- int idx = hwc->idx;
- int ret = -EAGAIN;
-
- perf_pmu_disable(event->pmu);
-
- if (__test_and_set_bit(idx, cpuc->used_mask)) {
- idx = find_first_zero_bit(cpuc->used_mask, MAX_HWEVENTS);
- if (idx == MAX_HWEVENTS)
- goto out;
-
- __set_bit(idx, cpuc->used_mask);
- hwc->idx = idx;
- }
-
- bfin_pfmon_disable(hwc, idx);
-
- event->hw.state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
- if (flags & PERF_EF_START)
- bfin_pmu_start(event, PERF_EF_RELOAD);
-
- perf_event_update_userpage(event);
- ret = 0;
-out:
- perf_pmu_enable(event->pmu);
- return ret;
-}
-
-static void bfin_pmu_read(struct perf_event *event)
-{
- bfin_perf_event_update(event, &event->hw, event->hw.idx);
-}
-
-static int bfin_pmu_event_init(struct perf_event *event)
-{
- struct perf_event_attr *attr = &event->attr;
- struct hw_perf_event *hwc = &event->hw;
- int config = -1;
- int ret;
-
- if (attr->exclude_hv || attr->exclude_idle)
- return -EPERM;
-
- ret = 0;
- switch (attr->type) {
- case PERF_TYPE_RAW:
- config = PFMON(0, attr->config & PFMON_MASK) |
- PFCNT(0, !(attr->config & 0x100));
- break;
- case PERF_TYPE_HW_CACHE:
- ret = hw_perf_cache_event(attr->config, &config);
- break;
- case PERF_TYPE_HARDWARE:
- if (attr->config >= ARRAY_SIZE(event_map))
- return -EINVAL;
-
- config = event_map[attr->config];
- break;
- }
-
- if (config == -1)
- return -EINVAL;
-
- if (!attr->exclude_kernel)
- config |= PFCEN(0, PFCEN_ENABLE_SUPV);
- if (!attr->exclude_user)
- config |= PFCEN(0, PFCEN_ENABLE_USER);
-
- hwc->config |= config;
-
- return ret;
-}
-
-static void bfin_pmu_enable(struct pmu *pmu)
-{
- struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
- struct perf_event *event;
- struct hw_perf_event *hwc;
- int i;
-
- for (i = 0; i < MAX_HWEVENTS; ++i) {
- event = cpuc->events[i];
- if (!event)
- continue;
- hwc = &event->hw;
- bfin_pfmon_enable(hwc, hwc->idx);
- }
-
- bfin_pfmon_enable_all();
-}
-
-static void bfin_pmu_disable(struct pmu *pmu)
-{
- bfin_pfmon_disable_all();
-}
-
-static struct pmu pmu = {
- .pmu_enable = bfin_pmu_enable,
- .pmu_disable = bfin_pmu_disable,
- .event_init = bfin_pmu_event_init,
- .add = bfin_pmu_add,
- .del = bfin_pmu_del,
- .start = bfin_pmu_start,
- .stop = bfin_pmu_stop,
- .read = bfin_pmu_read,
-};
-
-static int bfin_pmu_prepare_cpu(unsigned int cpu)
-{
- struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu);
-
- bfin_write_PFCTL(0);
- memset(cpuhw, 0, sizeof(struct cpu_hw_events));
- return 0;
-}
-
-static int __init bfin_pmu_init(void)
-{
- int ret;
-
- /*
- * All of the on-chip counters are "limited", in that they have
- * no interrupts, and are therefore unable to do sampling without
- * further work and timer assistance.
- */
- pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
-
- ret = perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
- if (!ret)
- cpuhp_setup_state(CPUHP_PERF_BFIN,"perf/bfin:starting",
- bfin_pmu_prepare_cpu, NULL);
- return ret;
-}
-early_initcall(bfin_pmu_init);
+++ /dev/null
-/*
- * Blackfin architecture-dependent process handling
- *
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <linux/module.h>
-#include <linux/unistd.h>
-#include <linux/user.h>
-#include <linux/uaccess.h>
-#include <linux/slab.h>
-#include <linux/sched.h>
-#include <linux/sched/debug.h>
-#include <linux/sched/task.h>
-#include <linux/sched/task_stack.h>
-#include <linux/mm_types.h>
-#include <linux/tick.h>
-#include <linux/fs.h>
-#include <linux/err.h>
-
-#include <asm/blackfin.h>
-#include <asm/fixed_code.h>
-#include <asm/mem_map.h>
-#include <asm/irq.h>
-
-asmlinkage void ret_from_fork(void);
-
-/* Points to the SDRAM backup memory for the stack that is currently in
- * L1 scratchpad memory.
- */
-void *current_l1_stack_save;
-
-/* The number of tasks currently using a L1 stack area. The SRAM is
- * allocated/deallocated whenever this changes from/to zero.
- */
-int nr_l1stack_tasks;
-
-/* Start and length of the area in L1 scratchpad memory which we've allocated
- * for process stacks.
- */
-void *l1_stack_base;
-unsigned long l1_stack_len;
-
-void (*pm_power_off)(void) = NULL;
-EXPORT_SYMBOL(pm_power_off);
-
-/*
- * The idle loop on BFIN
- */
-#ifdef CONFIG_IDLE_L1
-void arch_cpu_idle(void)__attribute__((l1_text));
-#endif
-
-/*
- * This is our default idle handler. We need to disable
- * interrupts here to ensure we don't miss a wakeup call.
- */
-void arch_cpu_idle(void)
-{
-#ifdef CONFIG_IPIPE
- ipipe_suspend_domain();
-#endif
- hard_local_irq_disable();
- if (!need_resched())
- idle_with_irq_disabled();
-
- hard_local_irq_enable();
-}
-
-#ifdef CONFIG_HOTPLUG_CPU
-void arch_cpu_idle_dead(void)
-{
- cpu_die();
-}
-#endif
-
-/*
- * Do necessary setup to start up a newly executed thread.
- *
- * pass the data segment into user programs if it exists,
- * it can't hurt anything as far as I can tell
- */
-void start_thread(struct pt_regs *regs, unsigned long new_ip, unsigned long new_sp)
-{
- regs->pc = new_ip;
- if (current->mm)
- regs->p5 = current->mm->start_data;
-#ifndef CONFIG_SMP
- task_thread_info(current)->l1_task_info.stack_start =
- (void *)current->mm->context.stack_start;
- task_thread_info(current)->l1_task_info.lowest_sp = (void *)new_sp;
- memcpy(L1_SCRATCH_TASK_INFO, &task_thread_info(current)->l1_task_info,
- sizeof(*L1_SCRATCH_TASK_INFO));
-#endif
- wrusp(new_sp);
-}
-EXPORT_SYMBOL_GPL(start_thread);
-
-void flush_thread(void)
-{
-}
-
-asmlinkage int bfin_clone(unsigned long clone_flags, unsigned long newsp)
-{
-#ifdef __ARCH_SYNC_CORE_DCACHE
- if (current->nr_cpus_allowed == num_possible_cpus())
- set_cpus_allowed_ptr(current, cpumask_of(smp_processor_id()));
-#endif
- if (newsp)
- newsp -= 12;
- return do_fork(clone_flags, newsp, 0, NULL, NULL);
-}
-
-int
-copy_thread(unsigned long clone_flags,
- unsigned long usp, unsigned long topstk,
- struct task_struct *p)
-{
- struct pt_regs *childregs;
- unsigned long *v;
-
- childregs = (struct pt_regs *) (task_stack_page(p) + THREAD_SIZE) - 1;
- v = ((unsigned long *)childregs) - 2;
- if (unlikely(p->flags & PF_KTHREAD)) {
- memset(childregs, 0, sizeof(struct pt_regs));
- v[0] = usp;
- v[1] = topstk;
- childregs->orig_p0 = -1;
- childregs->ipend = 0x8000;
- __asm__ __volatile__("%0 = syscfg;":"=da"(childregs->syscfg):);
- p->thread.usp = 0;
- } else {
- *childregs = *current_pt_regs();
- childregs->r0 = 0;
- p->thread.usp = usp ? : rdusp();
- v[0] = v[1] = 0;
- }
-
- p->thread.ksp = (unsigned long)v;
- p->thread.pc = (unsigned long)ret_from_fork;
-
- return 0;
-}
-
-unsigned long get_wchan(struct task_struct *p)
-{
- unsigned long fp, pc;
- unsigned long stack_page;
- int count = 0;
- if (!p || p == current || p->state == TASK_RUNNING)
- return 0;
-
- stack_page = (unsigned long)p;
- fp = p->thread.usp;
- do {
- if (fp < stack_page + sizeof(struct thread_info) ||
- fp >= 8184 + stack_page)
- return 0;
- pc = ((unsigned long *)fp)[1];
- if (!in_sched_functions(pc))
- return pc;
- fp = *(unsigned long *)fp;
- }
- while (count++ < 16);
- return 0;
-}
-
-void finish_atomic_sections (struct pt_regs *regs)
-{
- int __user *up0 = (int __user *)regs->p0;
-
- switch (regs->pc) {
- default:
- /* not in middle of an atomic step, so resume like normal */
- return;
-
- case ATOMIC_XCHG32 + 2:
- put_user(regs->r1, up0);
- break;
-
- case ATOMIC_CAS32 + 2:
- case ATOMIC_CAS32 + 4:
- if (regs->r0 == regs->r1)
- case ATOMIC_CAS32 + 6:
- put_user(regs->r2, up0);
- break;
-
- case ATOMIC_ADD32 + 2:
- regs->r0 = regs->r1 + regs->r0;
- /* fall through */
- case ATOMIC_ADD32 + 4:
- put_user(regs->r0, up0);
- break;
-
- case ATOMIC_SUB32 + 2:
- regs->r0 = regs->r1 - regs->r0;
- /* fall through */
- case ATOMIC_SUB32 + 4:
- put_user(regs->r0, up0);
- break;
-
- case ATOMIC_IOR32 + 2:
- regs->r0 = regs->r1 | regs->r0;
- /* fall through */
- case ATOMIC_IOR32 + 4:
- put_user(regs->r0, up0);
- break;
-
- case ATOMIC_AND32 + 2:
- regs->r0 = regs->r1 & regs->r0;
- /* fall through */
- case ATOMIC_AND32 + 4:
- put_user(regs->r0, up0);
- break;
-
- case ATOMIC_XOR32 + 2:
- regs->r0 = regs->r1 ^ regs->r0;
- /* fall through */
- case ATOMIC_XOR32 + 4:
- put_user(regs->r0, up0);
- break;
- }
-
- /*
- * We've finished the atomic section, and the only thing left for
- * userspace is to do a RTS, so we might as well handle that too
- * since we need to update the PC anyways.
- */
- regs->pc = regs->rets;
-}
-
-static inline
-int in_mem(unsigned long addr, unsigned long size,
- unsigned long start, unsigned long end)
-{
- return addr >= start && addr + size <= end;
-}
-static inline
-int in_mem_const_off(unsigned long addr, unsigned long size, unsigned long off,
- unsigned long const_addr, unsigned long const_size)
-{
- return const_size &&
- in_mem(addr, size, const_addr + off, const_addr + const_size);
-}
-static inline
-int in_mem_const(unsigned long addr, unsigned long size,
- unsigned long const_addr, unsigned long const_size)
-{
- return in_mem_const_off(addr, size, 0, const_addr, const_size);
-}
-#ifdef CONFIG_BF60x
-#define ASYNC_ENABLED(bnum, bctlnum) 1
-#else
-#define ASYNC_ENABLED(bnum, bctlnum) \
-({ \
- (bfin_read_EBIU_AMGCTL() & 0xe) < ((bnum + 1) << 1) ? 0 : \
- bfin_read_EBIU_AMBCTL##bctlnum() & B##bnum##RDYEN ? 0 : \
- 1; \
-})
-#endif
-/*
- * We can't read EBIU banks that aren't enabled or we end up hanging
- * on the access to the async space. Make sure we validate accesses
- * that cross async banks too.
- * 0 - found, but unusable
- * 1 - found & usable
- * 2 - not found
- */
-static
-int in_async(unsigned long addr, unsigned long size)
-{
- if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE) {
- if (!ASYNC_ENABLED(0, 0))
- return 0;
- if (addr + size <= ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE)
- return 1;
- size -= ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE - addr;
- addr = ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE;
- }
- if (addr >= ASYNC_BANK1_BASE && addr < ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE) {
- if (!ASYNC_ENABLED(1, 0))
- return 0;
- if (addr + size <= ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE)
- return 1;
- size -= ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE - addr;
- addr = ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE;
- }
- if (addr >= ASYNC_BANK2_BASE && addr < ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE) {
- if (!ASYNC_ENABLED(2, 1))
- return 0;
- if (addr + size <= ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE)
- return 1;
- size -= ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE - addr;
- addr = ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE;
- }
- if (addr >= ASYNC_BANK3_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) {
- if (ASYNC_ENABLED(3, 1))
- return 0;
- if (addr + size <= ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE)
- return 1;
- return 0;
- }
-
- /* not within async bounds */
- return 2;
-}
-
-int bfin_mem_access_type(unsigned long addr, unsigned long size)
-{
- int cpu = raw_smp_processor_id();
-
- /* Check that things do not wrap around */
- if (addr > ULONG_MAX - size)
- return -EFAULT;
-
- if (in_mem(addr, size, FIXED_CODE_START, physical_mem_end))
- return BFIN_MEM_ACCESS_CORE;
-
- if (in_mem_const(addr, size, L1_CODE_START, L1_CODE_LENGTH))
- return cpu == 0 ? BFIN_MEM_ACCESS_ITEST : BFIN_MEM_ACCESS_IDMA;
- if (in_mem_const(addr, size, L1_SCRATCH_START, L1_SCRATCH_LENGTH))
- return cpu == 0 ? BFIN_MEM_ACCESS_CORE_ONLY : -EFAULT;
- if (in_mem_const(addr, size, L1_DATA_A_START, L1_DATA_A_LENGTH))
- return cpu == 0 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
- if (in_mem_const(addr, size, L1_DATA_B_START, L1_DATA_B_LENGTH))
- return cpu == 0 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
-#ifdef COREB_L1_CODE_START
- if (in_mem_const(addr, size, COREB_L1_CODE_START, COREB_L1_CODE_LENGTH))
- return cpu == 1 ? BFIN_MEM_ACCESS_ITEST : BFIN_MEM_ACCESS_IDMA;
- if (in_mem_const(addr, size, COREB_L1_SCRATCH_START, L1_SCRATCH_LENGTH))
- return cpu == 1 ? BFIN_MEM_ACCESS_CORE_ONLY : -EFAULT;
- if (in_mem_const(addr, size, COREB_L1_DATA_A_START, COREB_L1_DATA_A_LENGTH))
- return cpu == 1 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
- if (in_mem_const(addr, size, COREB_L1_DATA_B_START, COREB_L1_DATA_B_LENGTH))
- return cpu == 1 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
-#endif
- if (in_mem_const(addr, size, L2_START, L2_LENGTH))
- return BFIN_MEM_ACCESS_CORE;
-
- if (addr >= SYSMMR_BASE)
- return BFIN_MEM_ACCESS_CORE_ONLY;
-
- switch (in_async(addr, size)) {
- case 0: return -EFAULT;
- case 1: return BFIN_MEM_ACCESS_CORE;
- case 2: /* fall through */;
- }
-
- if (in_mem_const(addr, size, BOOT_ROM_START, BOOT_ROM_LENGTH))
- return BFIN_MEM_ACCESS_CORE;
- if (in_mem_const(addr, size, L1_ROM_START, L1_ROM_LENGTH))
- return BFIN_MEM_ACCESS_DMA;
-
- return -EFAULT;
-}
-
-#if defined(CONFIG_ACCESS_CHECK)
-#ifdef CONFIG_ACCESS_OK_L1
-__attribute__((l1_text))
-#endif
-/* Return 1 if access to memory range is OK, 0 otherwise */
-int _access_ok(unsigned long addr, unsigned long size)
-{
- int aret;
-
- if (size == 0)
- return 1;
- /* Check that things do not wrap around */
- if (addr > ULONG_MAX - size)
- return 0;
- if (uaccess_kernel())
- return 1;
-#ifdef CONFIG_MTD_UCLINUX
- if (1)
-#else
- if (0)
-#endif
- {
- if (in_mem(addr, size, memory_start, memory_end))
- return 1;
- if (in_mem(addr, size, memory_mtd_end, physical_mem_end))
- return 1;
-# ifndef CONFIG_ROMFS_ON_MTD
- if (0)
-# endif
- /* For XIP, allow user space to use pointers within the ROMFS. */
- if (in_mem(addr, size, memory_mtd_start, memory_mtd_end))
- return 1;
- } else {
- if (in_mem(addr, size, memory_start, physical_mem_end))
- return 1;
- }
-
- if (in_mem(addr, size, (unsigned long)__init_begin, (unsigned long)__init_end))
- return 1;
-
- if (in_mem_const(addr, size, L1_CODE_START, L1_CODE_LENGTH))
- return 1;
- if (in_mem_const_off(addr, size, _etext_l1 - _stext_l1, L1_CODE_START, L1_CODE_LENGTH))
- return 1;
- if (in_mem_const_off(addr, size, _ebss_l1 - _sdata_l1, L1_DATA_A_START, L1_DATA_A_LENGTH))
- return 1;
- if (in_mem_const_off(addr, size, _ebss_b_l1 - _sdata_b_l1, L1_DATA_B_START, L1_DATA_B_LENGTH))
- return 1;
-#ifdef COREB_L1_CODE_START
- if (in_mem_const(addr, size, COREB_L1_CODE_START, COREB_L1_CODE_LENGTH))
- return 1;
- if (in_mem_const(addr, size, COREB_L1_SCRATCH_START, L1_SCRATCH_LENGTH))
- return 1;
- if (in_mem_const(addr, size, COREB_L1_DATA_A_START, COREB_L1_DATA_A_LENGTH))
- return 1;
- if (in_mem_const(addr, size, COREB_L1_DATA_B_START, COREB_L1_DATA_B_LENGTH))
- return 1;
-#endif
-
-#ifndef CONFIG_EXCEPTION_L1_SCRATCH
- if (in_mem_const(addr, size, (unsigned long)l1_stack_base, l1_stack_len))
- return 1;
-#endif
-
- aret = in_async(addr, size);
- if (aret < 2)
- return aret;
-
- if (in_mem_const_off(addr, size, _ebss_l2 - _stext_l2, L2_START, L2_LENGTH))
- return 1;
-
- if (in_mem_const(addr, size, BOOT_ROM_START, BOOT_ROM_LENGTH))
- return 1;
- if (in_mem_const(addr, size, L1_ROM_START, L1_ROM_LENGTH))
- return 1;
-
- return 0;
-}
-EXPORT_SYMBOL(_access_ok);
-#endif /* CONFIG_ACCESS_CHECK */
+++ /dev/null
-/* The fake debug assert instructions
- *
- * Copyright 2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/ptrace.h>
-
-const char * const greg_names[] = {
- "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7",
- "P0", "P1", "P2", "P3", "P4", "P5", "SP", "FP",
- "I0", "I1", "I2", "I3", "M0", "M1", "M2", "M3",
- "B0", "B1", "B2", "B3", "L0", "L1", "L2", "L3",
- "A0.X", "A0.W", "A1.X", "A1.W", "<res>", "<res>", "ASTAT", "RETS",
- "<res>", "<res>", "<res>", "<res>", "<res>", "<res>", "<res>", "<res>",
- "LC0", "LT0", "LB0", "LC1", "LT1", "LB1", "CYCLES", "CYCLES2",
- "USP", "SEQSTAT", "SYSCFG", "RETI", "RETX", "RETN", "RETE", "EMUDAT",
-};
-
-static const char *get_allreg_name(int grp, int reg)
-{
- return greg_names[(grp << 3) | reg];
-}
-
-/*
- * Unfortunately, the pt_regs structure is not laid out the same way as the
- * hardware register file, so we need to do some fix ups.
- *
- * CYCLES is not stored in the pt_regs structure - so, we just read it from
- * the hardware.
- *
- * Don't support:
- * - All reserved registers
- * - All in group 7 are (supervisors only)
- */
-
-static bool fix_up_reg(struct pt_regs *fp, long *value, int grp, int reg)
-{
- long *val = &fp->r0;
- unsigned long tmp;
-
- /* Only do Dregs and Pregs for now */
- if (grp == 5 ||
- (grp == 4 && (reg == 4 || reg == 5)) ||
- (grp == 7))
- return false;
-
- if (grp == 0 || (grp == 1 && reg < 6))
- val -= (reg + 8 * grp);
- else if (grp == 1 && reg == 6)
- val = &fp->usp;
- else if (grp == 1 && reg == 7)
- val = &fp->fp;
- else if (grp == 2) {
- val = &fp->i0;
- val -= reg;
- } else if (grp == 3 && reg >= 4) {
- val = &fp->l0;
- val -= (reg - 4);
- } else if (grp == 3 && reg < 4) {
- val = &fp->b0;
- val -= reg;
- } else if (grp == 4 && reg < 4) {
- val = &fp->a0x;
- val -= reg;
- } else if (grp == 4 && reg == 6)
- val = &fp->astat;
- else if (grp == 4 && reg == 7)
- val = &fp->rets;
- else if (grp == 6 && reg < 6) {
- val = &fp->lc0;
- val -= reg;
- } else if (grp == 6 && reg == 6) {
- __asm__ __volatile__("%0 = cycles;\n" : "=d"(tmp));
- val = &tmp;
- } else if (grp == 6 && reg == 7) {
- __asm__ __volatile__("%0 = cycles2;\n" : "=d"(tmp));
- val = &tmp;
- }
-
- *value = *val;
- return true;
-
-}
-
-#define PseudoDbg_Assert_opcode 0xf0000000
-#define PseudoDbg_Assert_expected_bits 0
-#define PseudoDbg_Assert_expected_mask 0xffff
-#define PseudoDbg_Assert_regtest_bits 16
-#define PseudoDbg_Assert_regtest_mask 0x7
-#define PseudoDbg_Assert_grp_bits 19
-#define PseudoDbg_Assert_grp_mask 0x7
-#define PseudoDbg_Assert_dbgop_bits 22
-#define PseudoDbg_Assert_dbgop_mask 0x3
-#define PseudoDbg_Assert_dontcare_bits 24
-#define PseudoDbg_Assert_dontcare_mask 0x7
-#define PseudoDbg_Assert_code_bits 27
-#define PseudoDbg_Assert_code_mask 0x1f
-
-/*
- * DBGA - debug assert
- */
-bool execute_pseudodbg_assert(struct pt_regs *fp, unsigned int opcode)
-{
- int expected = ((opcode >> PseudoDbg_Assert_expected_bits) & PseudoDbg_Assert_expected_mask);
- int dbgop = ((opcode >> (PseudoDbg_Assert_dbgop_bits)) & PseudoDbg_Assert_dbgop_mask);
- int grp = ((opcode >> (PseudoDbg_Assert_grp_bits)) & PseudoDbg_Assert_grp_mask);
- int regtest = ((opcode >> (PseudoDbg_Assert_regtest_bits)) & PseudoDbg_Assert_regtest_mask);
- long value;
-
- if ((opcode & 0xFF000000) != PseudoDbg_Assert_opcode)
- return false;
-
- if (!fix_up_reg(fp, &value, grp, regtest))
- return false;
-
- if (dbgop == 0 || dbgop == 2) {
- /* DBGA ( regs_lo , uimm16 ) */
- /* DBGAL ( regs , uimm16 ) */
- if (expected != (value & 0xFFFF)) {
- pr_notice("DBGA (%s.L,0x%x) failure, got 0x%x\n",
- get_allreg_name(grp, regtest),
- expected, (unsigned int)(value & 0xFFFF));
- return false;
- }
-
- } else if (dbgop == 1 || dbgop == 3) {
- /* DBGA ( regs_hi , uimm16 ) */
- /* DBGAH ( regs , uimm16 ) */
- if (expected != ((value >> 16) & 0xFFFF)) {
- pr_notice("DBGA (%s.H,0x%x) failure, got 0x%x\n",
- get_allreg_name(grp, regtest),
- expected, (unsigned int)((value >> 16) & 0xFFFF));
- return false;
- }
- }
-
- fp->pc += 4;
- return true;
-}
-
-#define PseudoDbg_opcode 0xf8000000
-#define PseudoDbg_reg_bits 0
-#define PseudoDbg_reg_mask 0x7
-#define PseudoDbg_grp_bits 3
-#define PseudoDbg_grp_mask 0x7
-#define PseudoDbg_fn_bits 6
-#define PseudoDbg_fn_mask 0x3
-#define PseudoDbg_code_bits 8
-#define PseudoDbg_code_mask 0xff
-
-/*
- * DBG - debug (dump a register value out)
- */
-bool execute_pseudodbg(struct pt_regs *fp, unsigned int opcode)
-{
- int grp, fn, reg;
- long value, value1;
-
- if ((opcode & 0xFF000000) != PseudoDbg_opcode)
- return false;
-
- opcode >>= 16;
- grp = ((opcode >> PseudoDbg_grp_bits) & PseudoDbg_reg_mask);
- fn = ((opcode >> PseudoDbg_fn_bits) & PseudoDbg_fn_mask);
- reg = ((opcode >> PseudoDbg_reg_bits) & PseudoDbg_reg_mask);
-
- if (fn == 3 && (reg == 0 || reg == 1)) {
- if (!fix_up_reg(fp, &value, 4, 2 * reg))
- return false;
- if (!fix_up_reg(fp, &value1, 4, 2 * reg + 1))
- return false;
-
- pr_notice("DBG A%i = %02lx%08lx\n", reg, value & 0xFF, value1);
- fp->pc += 2;
- return true;
-
- } else if (fn == 0) {
- if (!fix_up_reg(fp, &value, grp, reg))
- return false;
-
- pr_notice("DBG %s = %08lx\n", get_allreg_name(grp, reg), value);
- fp->pc += 2;
- return true;
- }
-
- return false;
-}
+++ /dev/null
-/*
- * linux/kernel/ptrace.c is by Ross Biro 1/23/92, edited by Linus Torvalds
- * these modifications are Copyright 2004-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2
- */
-
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/sched/task_stack.h>
-#include <linux/mm.h>
-#include <linux/smp.h>
-#include <linux/elf.h>
-#include <linux/errno.h>
-#include <linux/ptrace.h>
-#include <linux/user.h>
-#include <linux/regset.h>
-#include <linux/signal.h>
-#include <linux/tracehook.h>
-#include <linux/uaccess.h>
-
-#include <asm/page.h>
-#include <asm/pgtable.h>
-#include <asm/processor.h>
-#include <asm/asm-offsets.h>
-#include <asm/dma.h>
-#include <asm/fixed_code.h>
-#include <asm/cacheflush.h>
-#include <asm/mem_map.h>
-#include <asm/mmu_context.h>
-
-/*
- * does not yet catch signals sent when the child dies.
- * in exit.c or in signal.c.
- */
-
-/*
- * Get contents of register REGNO in task TASK.
- */
-static inline long
-get_reg(struct task_struct *task, unsigned long regno,
- unsigned long __user *datap)
-{
- long tmp;
- struct pt_regs *regs = task_pt_regs(task);
-
- if (regno & 3 || regno > PT_LAST_PSEUDO)
- return -EIO;
-
- switch (regno) {
- case PT_TEXT_ADDR:
- tmp = task->mm->start_code;
- break;
- case PT_TEXT_END_ADDR:
- tmp = task->mm->end_code;
- break;
- case PT_DATA_ADDR:
- tmp = task->mm->start_data;
- break;
- case PT_USP:
- tmp = task->thread.usp;
- break;
- default:
- if (regno < sizeof(*regs)) {
- void *reg_ptr = regs;
- tmp = *(long *)(reg_ptr + regno);
- } else
- return -EIO;
- }
-
- return put_user(tmp, datap);
-}
-
-/*
- * Write contents of register REGNO in task TASK.
- */
-static inline int
-put_reg(struct task_struct *task, unsigned long regno, unsigned long data)
-{
- struct pt_regs *regs = task_pt_regs(task);
-
- if (regno & 3 || regno > PT_LAST_PSEUDO)
- return -EIO;
-
- switch (regno) {
- case PT_PC:
- /*********************************************************************/
- /* At this point the kernel is most likely in exception. */
- /* The RETX register will be used to populate the pc of the process. */
- /*********************************************************************/
- regs->retx = data;
- regs->pc = data;
- break;
- case PT_RETX:
- break; /* regs->retx = data; break; */
- case PT_USP:
- regs->usp = data;
- task->thread.usp = data;
- break;
- case PT_SYSCFG: /* don't let userspace screw with this */
- if ((data & ~1) != 0x6)
- pr_warning("ptrace: ignore syscfg write of %#lx\n", data);
- break; /* regs->syscfg = data; break; */
- default:
- if (regno < sizeof(*regs)) {
- void *reg_offset = regs;
- *(long *)(reg_offset + regno) = data;
- }
- /* Ignore writes to pseudo registers */
- }
-
- return 0;
-}
-
-/*
- * check that an address falls within the bounds of the target process's memory mappings
- */
-int
-is_user_addr_valid(struct task_struct *child, unsigned long start, unsigned long len)
-{
- bool valid;
- struct vm_area_struct *vma;
- struct sram_list_struct *sraml;
-
- /* overflow */
- if (start + len < start)
- return -EIO;
-
- down_read(&child->mm->mmap_sem);
- vma = find_vma(child->mm, start);
- valid = vma && start >= vma->vm_start && start + len <= vma->vm_end;
- up_read(&child->mm->mmap_sem);
- if (valid)
- return 0;
-
- for (sraml = child->mm->context.sram_list; sraml; sraml = sraml->next)
- if (start >= (unsigned long)sraml->addr
- && start + len < (unsigned long)sraml->addr + sraml->length)
- return 0;
-
- if (start >= FIXED_CODE_START && start + len < FIXED_CODE_END)
- return 0;
-
-#ifdef CONFIG_APP_STACK_L1
- if (child->mm->context.l1_stack_save)
- if (start >= (unsigned long)l1_stack_base &&
- start + len < (unsigned long)l1_stack_base + l1_stack_len)
- return 0;
-#endif
-
- return -EIO;
-}
-
-/*
- * retrieve the contents of Blackfin userspace general registers
- */
-static int genregs_get(struct task_struct *target,
- const struct user_regset *regset,
- unsigned int pos, unsigned int count,
- void *kbuf, void __user *ubuf)
-{
- struct pt_regs *regs = task_pt_regs(target);
- int ret;
-
- /* This sucks ... */
- regs->usp = target->thread.usp;
-
- ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
- regs, 0, sizeof(*regs));
- if (ret < 0)
- return ret;
-
- return user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf,
- sizeof(*regs), -1);
-}
-
-/*
- * update the contents of the Blackfin userspace general registers
- */
-static int genregs_set(struct task_struct *target,
- const struct user_regset *regset,
- unsigned int pos, unsigned int count,
- const void *kbuf, const void __user *ubuf)
-{
- struct pt_regs *regs = task_pt_regs(target);
- int ret;
-
- /* Don't let people set SYSCFG (it's at the end of pt_regs) */
- ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
- regs, 0, PT_SYSCFG);
- if (ret < 0)
- return ret;
-
- /* This sucks ... */
- target->thread.usp = regs->usp;
- /* regs->retx = regs->pc; */
-
- return user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf,
- PT_SYSCFG, -1);
-}
-
-/*
- * Define the register sets available on the Blackfin under Linux
- */
-enum bfin_regset {
- REGSET_GENERAL,
-};
-
-static const struct user_regset bfin_regsets[] = {
- [REGSET_GENERAL] = {
- .core_note_type = NT_PRSTATUS,
- .n = sizeof(struct pt_regs) / sizeof(long),
- .size = sizeof(long),
- .align = sizeof(long),
- .get = genregs_get,
- .set = genregs_set,
- },
-};
-
-static const struct user_regset_view user_bfin_native_view = {
- .name = "Blackfin",
- .e_machine = EM_BLACKFIN,
- .regsets = bfin_regsets,
- .n = ARRAY_SIZE(bfin_regsets),
-};
-
-const struct user_regset_view *task_user_regset_view(struct task_struct *task)
-{
- return &user_bfin_native_view;
-}
-
-void user_enable_single_step(struct task_struct *child)
-{
- struct pt_regs *regs = task_pt_regs(child);
- regs->syscfg |= SYSCFG_SSSTEP;
-
- set_tsk_thread_flag(child, TIF_SINGLESTEP);
-}
-
-void user_disable_single_step(struct task_struct *child)
-{
- struct pt_regs *regs = task_pt_regs(child);
- regs->syscfg &= ~SYSCFG_SSSTEP;
-
- clear_tsk_thread_flag(child, TIF_SINGLESTEP);
-}
-
-long arch_ptrace(struct task_struct *child, long request,
- unsigned long addr, unsigned long data)
-{
- int ret;
- unsigned long __user *datap = (unsigned long __user *)data;
- void *paddr = (void *)addr;
-
- switch (request) {
- /* when I and D space are separate, these will need to be fixed. */
- case PTRACE_PEEKDATA:
- pr_debug("ptrace: PEEKDATA\n");
- /* fall through */
- case PTRACE_PEEKTEXT: /* read word at location addr. */
- {
- unsigned long tmp = 0;
- int copied = 0, to_copy = sizeof(tmp);
-
- ret = -EIO;
- pr_debug("ptrace: PEEKTEXT at addr 0x%08lx + %i\n", addr, to_copy);
- if (is_user_addr_valid(child, addr, to_copy) < 0)
- break;
- pr_debug("ptrace: user address is valid\n");
-
- switch (bfin_mem_access_type(addr, to_copy)) {
- case BFIN_MEM_ACCESS_CORE:
- case BFIN_MEM_ACCESS_CORE_ONLY:
- copied = ptrace_access_vm(child, addr, &tmp,
- to_copy, FOLL_FORCE);
- if (copied)
- break;
-
- /* hrm, why didn't that work ... maybe no mapping */
- if (addr >= FIXED_CODE_START &&
- addr + to_copy <= FIXED_CODE_END) {
- copy_from_user_page(0, 0, 0, &tmp, paddr, to_copy);
- copied = to_copy;
- } else if (addr >= BOOT_ROM_START) {
- memcpy(&tmp, paddr, to_copy);
- copied = to_copy;
- }
-
- break;
- case BFIN_MEM_ACCESS_DMA:
- if (safe_dma_memcpy(&tmp, paddr, to_copy))
- copied = to_copy;
- break;
- case BFIN_MEM_ACCESS_ITEST:
- if (isram_memcpy(&tmp, paddr, to_copy))
- copied = to_copy;
- break;
- default:
- copied = 0;
- break;
- }
-
- pr_debug("ptrace: copied size %d [0x%08lx]\n", copied, tmp);
- if (copied == to_copy)
- ret = put_user(tmp, datap);
- break;
- }
-
- /* when I and D space are separate, this will have to be fixed. */
- case PTRACE_POKEDATA:
- pr_debug("ptrace: PTRACE_PEEKDATA\n");
- /* fall through */
- case PTRACE_POKETEXT: /* write the word at location addr. */
- {
- int copied = 0, to_copy = sizeof(data);
-
- ret = -EIO;
- pr_debug("ptrace: POKETEXT at addr 0x%08lx + %i bytes %lx\n",
- addr, to_copy, data);
- if (is_user_addr_valid(child, addr, to_copy) < 0)
- break;
- pr_debug("ptrace: user address is valid\n");
-
- switch (bfin_mem_access_type(addr, to_copy)) {
- case BFIN_MEM_ACCESS_CORE:
- case BFIN_MEM_ACCESS_CORE_ONLY:
- copied = ptrace_access_vm(child, addr, &data,
- to_copy,
- FOLL_FORCE | FOLL_WRITE);
- break;
- case BFIN_MEM_ACCESS_DMA:
- if (safe_dma_memcpy(paddr, &data, to_copy))
- copied = to_copy;
- break;
- case BFIN_MEM_ACCESS_ITEST:
- if (isram_memcpy(paddr, &data, to_copy))
- copied = to_copy;
- break;
- default:
- copied = 0;
- break;
- }
-
- pr_debug("ptrace: copied size %d\n", copied);
- if (copied == to_copy)
- ret = 0;
- break;
- }
-
- case PTRACE_PEEKUSR:
- switch (addr) {
-#ifdef CONFIG_BINFMT_ELF_FDPIC /* backwards compat */
- case PT_FDPIC_EXEC:
- request = PTRACE_GETFDPIC;
- addr = PTRACE_GETFDPIC_EXEC;
- goto case_default;
- case PT_FDPIC_INTERP:
- request = PTRACE_GETFDPIC;
- addr = PTRACE_GETFDPIC_INTERP;
- goto case_default;
-#endif
- default:
- ret = get_reg(child, addr, datap);
- }
- pr_debug("ptrace: PEEKUSR reg %li with %#lx = %i\n", addr, data, ret);
- break;
-
- case PTRACE_POKEUSR:
- ret = put_reg(child, addr, data);
- pr_debug("ptrace: POKEUSR reg %li with %li = %i\n", addr, data, ret);
- break;
-
- case PTRACE_GETREGS:
- pr_debug("ptrace: PTRACE_GETREGS\n");
- return copy_regset_to_user(child, &user_bfin_native_view,
- REGSET_GENERAL,
- 0, sizeof(struct pt_regs),
- datap);
-
- case PTRACE_SETREGS:
- pr_debug("ptrace: PTRACE_SETREGS\n");
- return copy_regset_from_user(child, &user_bfin_native_view,
- REGSET_GENERAL,
- 0, sizeof(struct pt_regs),
- datap);
-
- case_default:
- default:
- ret = ptrace_request(child, request, addr, data);
- break;
- }
-
- return ret;
-}
-
-asmlinkage int syscall_trace_enter(struct pt_regs *regs)
-{
- int ret = 0;
-
- if (test_thread_flag(TIF_SYSCALL_TRACE))
- ret = tracehook_report_syscall_entry(regs);
-
- return ret;
-}
-
-asmlinkage void syscall_trace_leave(struct pt_regs *regs)
-{
- int step;
-
- step = test_thread_flag(TIF_SINGLESTEP);
- if (step || test_thread_flag(TIF_SYSCALL_TRACE))
- tracehook_report_syscall_exit(regs, step);
-}
+++ /dev/null
-/*
- * arch/blackfin/kernel/reboot.c - handle shutdown/reboot
- *
- * Copyright 2004-2007 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/interrupt.h>
-#include <asm/bfin-global.h>
-#include <asm/reboot.h>
-#include <asm/bfrom.h>
-
-/* A system soft reset makes external memory unusable so force
- * this function into L1. We use the compiler ssync here rather
- * than SSYNC() because it's safe (no interrupts and such) and
- * we save some L1. We do not need to force sanity in the SYSCR
- * register as the BMODE selection bit is cleared by the soft
- * reset while the Core B bit (on dual core parts) is cleared by
- * the core reset.
- */
-__attribute__ ((__l1_text__, __noreturn__))
-static void bfin_reset(void)
-{
-#ifndef CONFIG_BF60x
- if (!ANOMALY_05000353 && !ANOMALY_05000386)
- bfrom_SoftReset((void *)(L1_SCRATCH_START + L1_SCRATCH_LENGTH - 20));
-
- /* Wait for completion of "system" events such as cache line
- * line fills so that we avoid infinite stalls later on as
- * much as possible. This code is in L1, so it won't trigger
- * any such event after this point in time.
- */
- __builtin_bfin_ssync();
-
- /* Initiate System software reset. */
- bfin_write_SWRST(0x7);
-
- /* Due to the way reset is handled in the hardware, we need
- * to delay for 10 SCLKS. The only reliable way to do this is
- * to calculate the CCLK/SCLK ratio and multiply 10. For now,
- * we'll assume worse case which is a 1:15 ratio.
- */
- asm(
- "LSETUP (1f, 1f) LC0 = %0\n"
- "1: nop;"
- :
- : "a" (15 * 10)
- : "LC0", "LB0", "LT0"
- );
-
- /* Clear System software reset */
- bfin_write_SWRST(0);
-
- /* The BF526 ROM will crash during reset */
-#if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__)
- /* Seems to be fixed with newer parts though ... */
- if (__SILICON_REVISION__ < 1 && bfin_revid() < 1)
- bfin_read_SWRST();
-#endif
- /* Wait for the SWRST write to complete. Cannot rely on SSYNC
- * though as the System state is all reset now.
- */
- asm(
- "LSETUP (1f, 1f) LC1 = %0\n"
- "1: nop;"
- :
- : "a" (15 * 1)
- : "LC1", "LB1", "LT1"
- );
-
- while (1)
- /* Issue core reset */
- asm("raise 1");
-#else
- while (1)
- bfin_write_RCU0_CTL(0x1);
-#endif
-}
-
-__attribute__((weak))
-void native_machine_restart(char *cmd)
-{
-}
-
-void machine_restart(char *cmd)
-{
- native_machine_restart(cmd);
- if (smp_processor_id())
- smp_call_function((void *)bfin_reset, 0, 1);
- else
- bfin_reset();
-}
-
-__attribute__((weak))
-void native_machine_halt(void)
-{
- idle_with_irq_disabled();
-}
-
-void machine_halt(void)
-{
- native_machine_halt();
-}
-
-__attribute__((weak))
-void native_machine_power_off(void)
-{
- idle_with_irq_disabled();
-}
-
-void machine_power_off(void)
-{
- native_machine_power_off();
-}
+++ /dev/null
-/*
- * Copyright 2004-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/delay.h>
-#include <linux/console.h>
-#include <linux/bootmem.h>
-#include <linux/seq_file.h>
-#include <linux/cpu.h>
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/tty.h>
-#include <linux/pfn.h>
-
-#ifdef CONFIG_MTD_UCLINUX
-#include <linux/mtd/map.h>
-#include <linux/ext2_fs.h>
-#include <uapi/linux/cramfs_fs.h>
-#include <linux/romfs_fs.h>
-#endif
-
-#include <asm/cplb.h>
-#include <asm/cacheflush.h>
-#include <asm/blackfin.h>
-#include <asm/cplbinit.h>
-#include <asm/clocks.h>
-#include <asm/div64.h>
-#include <asm/cpu.h>
-#include <asm/fixed_code.h>
-#include <asm/early_printk.h>
-#include <asm/irq_handler.h>
-#include <asm/pda.h>
-#ifdef CONFIG_BF60x
-#include <mach/pm.h>
-#endif
-#ifdef CONFIG_SCB_PRIORITY
-#include <asm/scb.h>
-#endif
-
-u16 _bfin_swrst;
-EXPORT_SYMBOL(_bfin_swrst);
-
-unsigned long memory_start, memory_end, physical_mem_end;
-unsigned long _rambase, _ramstart, _ramend;
-unsigned long reserved_mem_dcache_on;
-unsigned long reserved_mem_icache_on;
-EXPORT_SYMBOL(memory_start);
-EXPORT_SYMBOL(memory_end);
-EXPORT_SYMBOL(physical_mem_end);
-EXPORT_SYMBOL(_ramend);
-EXPORT_SYMBOL(reserved_mem_dcache_on);
-
-#ifdef CONFIG_MTD_UCLINUX
-extern struct map_info uclinux_ram_map;
-unsigned long memory_mtd_end, memory_mtd_start, mtd_size;
-EXPORT_SYMBOL(memory_mtd_end);
-EXPORT_SYMBOL(memory_mtd_start);
-EXPORT_SYMBOL(mtd_size);
-#endif
-
-char __initdata command_line[COMMAND_LINE_SIZE];
-struct blackfin_initial_pda __initdata initial_pda;
-
-/* boot memmap, for parsing "memmap=" */
-#define BFIN_MEMMAP_MAX 128 /* number of entries in bfin_memmap */
-#define BFIN_MEMMAP_RAM 1
-#define BFIN_MEMMAP_RESERVED 2
-static struct bfin_memmap {
- int nr_map;
- struct bfin_memmap_entry {
- unsigned long long addr; /* start of memory segment */
- unsigned long long size;
- unsigned long type;
- } map[BFIN_MEMMAP_MAX];
-} bfin_memmap __initdata;
-
-/* for memmap sanitization */
-struct change_member {
- struct bfin_memmap_entry *pentry; /* pointer to original entry */
- unsigned long long addr; /* address for this change point */
-};
-static struct change_member change_point_list[2*BFIN_MEMMAP_MAX] __initdata;
-static struct change_member *change_point[2*BFIN_MEMMAP_MAX] __initdata;
-static struct bfin_memmap_entry *overlap_list[BFIN_MEMMAP_MAX] __initdata;
-static struct bfin_memmap_entry new_map[BFIN_MEMMAP_MAX] __initdata;
-
-DEFINE_PER_CPU(struct blackfin_cpudata, cpu_data);
-
-static int early_init_clkin_hz(char *buf);
-
-#if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE)
-void __init generate_cplb_tables(void)
-{
- unsigned int cpu;
-
- generate_cplb_tables_all();
- /* Generate per-CPU I&D CPLB tables */
- for (cpu = 0; cpu < num_possible_cpus(); ++cpu)
- generate_cplb_tables_cpu(cpu);
-}
-#endif
-
-void bfin_setup_caches(unsigned int cpu)
-{
-#ifdef CONFIG_BFIN_ICACHE
- bfin_icache_init(icplb_tbl[cpu]);
-#endif
-
-#ifdef CONFIG_BFIN_DCACHE
- bfin_dcache_init(dcplb_tbl[cpu]);
-#endif
-
- bfin_setup_cpudata(cpu);
-
- /*
- * In cache coherence emulation mode, we need to have the
- * D-cache enabled before running any atomic operation which
- * might involve cache invalidation (i.e. spinlock, rwlock).
- * So printk's are deferred until then.
- */
-#ifdef CONFIG_BFIN_ICACHE
- printk(KERN_INFO "Instruction Cache Enabled for CPU%u\n", cpu);
- printk(KERN_INFO " External memory:"
-# ifdef CONFIG_BFIN_EXTMEM_ICACHEABLE
- " cacheable"
-# else
- " uncacheable"
-# endif
- " in instruction cache\n");
- if (L2_LENGTH)
- printk(KERN_INFO " L2 SRAM :"
-# ifdef CONFIG_BFIN_L2_ICACHEABLE
- " cacheable"
-# else
- " uncacheable"
-# endif
- " in instruction cache\n");
-
-#else
- printk(KERN_INFO "Instruction Cache Disabled for CPU%u\n", cpu);
-#endif
-
-#ifdef CONFIG_BFIN_DCACHE
- printk(KERN_INFO "Data Cache Enabled for CPU%u\n", cpu);
- printk(KERN_INFO " External memory:"
-# if defined CONFIG_BFIN_EXTMEM_WRITEBACK
- " cacheable (write-back)"
-# elif defined CONFIG_BFIN_EXTMEM_WRITETHROUGH
- " cacheable (write-through)"
-# else
- " uncacheable"
-# endif
- " in data cache\n");
- if (L2_LENGTH)
- printk(KERN_INFO " L2 SRAM :"
-# if defined CONFIG_BFIN_L2_WRITEBACK
- " cacheable (write-back)"
-# elif defined CONFIG_BFIN_L2_WRITETHROUGH
- " cacheable (write-through)"
-# else
- " uncacheable"
-# endif
- " in data cache\n");
-#else
- printk(KERN_INFO "Data Cache Disabled for CPU%u\n", cpu);
-#endif
-}
-
-void bfin_setup_cpudata(unsigned int cpu)
-{
- struct blackfin_cpudata *cpudata = &per_cpu(cpu_data, cpu);
-
- cpudata->imemctl = bfin_read_IMEM_CONTROL();
- cpudata->dmemctl = bfin_read_DMEM_CONTROL();
-}
-
-void __init bfin_cache_init(void)
-{
-#if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE)
- generate_cplb_tables();
-#endif
- bfin_setup_caches(0);
-}
-
-void __init bfin_relocate_l1_mem(void)
-{
- unsigned long text_l1_len = (unsigned long)_text_l1_len;
- unsigned long data_l1_len = (unsigned long)_data_l1_len;
- unsigned long data_b_l1_len = (unsigned long)_data_b_l1_len;
- unsigned long l2_len = (unsigned long)_l2_len;
-
- early_shadow_stamp();
-
- /*
- * due to the ALIGN(4) in the arch/blackfin/kernel/vmlinux.lds.S
- * we know that everything about l1 text/data is nice and aligned,
- * so copy by 4 byte chunks, and don't worry about overlapping
- * src/dest.
- *
- * We can't use the dma_memcpy functions, since they can call
- * scheduler functions which might be in L1 :( and core writes
- * into L1 instruction cause bad access errors, so we are stuck,
- * we are required to use DMA, but can't use the common dma
- * functions. We can't use memcpy either - since that might be
- * going to be in the relocated L1
- */
-
- blackfin_dma_early_init();
-
- /* if necessary, copy L1 text to L1 instruction SRAM */
- if (L1_CODE_LENGTH && text_l1_len)
- early_dma_memcpy(_stext_l1, _text_l1_lma, text_l1_len);
-
- /* if necessary, copy L1 data to L1 data bank A SRAM */
- if (L1_DATA_A_LENGTH && data_l1_len)
- early_dma_memcpy(_sdata_l1, _data_l1_lma, data_l1_len);
-
- /* if necessary, copy L1 data B to L1 data bank B SRAM */
- if (L1_DATA_B_LENGTH && data_b_l1_len)
- early_dma_memcpy(_sdata_b_l1, _data_b_l1_lma, data_b_l1_len);
-
- early_dma_memcpy_done();
-
-#if defined(CONFIG_SMP) && defined(CONFIG_ICACHE_FLUSH_L1)
- blackfin_iflush_l1_entry[0] = (unsigned long)blackfin_icache_flush_range_l1;
-#endif
-
- /* if necessary, copy L2 text/data to L2 SRAM */
- if (L2_LENGTH && l2_len)
- memcpy(_stext_l2, _l2_lma, l2_len);
-}
-
-#ifdef CONFIG_SMP
-void __init bfin_relocate_coreb_l1_mem(void)
-{
- unsigned long text_l1_len = (unsigned long)_text_l1_len;
- unsigned long data_l1_len = (unsigned long)_data_l1_len;
- unsigned long data_b_l1_len = (unsigned long)_data_b_l1_len;
-
- blackfin_dma_early_init();
-
- /* if necessary, copy L1 text to L1 instruction SRAM */
- if (L1_CODE_LENGTH && text_l1_len)
- early_dma_memcpy((void *)COREB_L1_CODE_START, _text_l1_lma,
- text_l1_len);
-
- /* if necessary, copy L1 data to L1 data bank A SRAM */
- if (L1_DATA_A_LENGTH && data_l1_len)
- early_dma_memcpy((void *)COREB_L1_DATA_A_START, _data_l1_lma,
- data_l1_len);
-
- /* if necessary, copy L1 data B to L1 data bank B SRAM */
- if (L1_DATA_B_LENGTH && data_b_l1_len)
- early_dma_memcpy((void *)COREB_L1_DATA_B_START, _data_b_l1_lma,
- data_b_l1_len);
-
- early_dma_memcpy_done();
-
-#ifdef CONFIG_ICACHE_FLUSH_L1
- blackfin_iflush_l1_entry[1] = (unsigned long)blackfin_icache_flush_range_l1 -
- (unsigned long)_stext_l1 + COREB_L1_CODE_START;
-#endif
-}
-#endif
-
-#ifdef CONFIG_ROMKERNEL
-void __init bfin_relocate_xip_data(void)
-{
- early_shadow_stamp();
-
- memcpy(_sdata, _data_lma, (unsigned long)_data_len - THREAD_SIZE + sizeof(struct thread_info));
- memcpy(_sinitdata, _init_data_lma, (unsigned long)_init_data_len);
-}
-#endif
-
-/* add_memory_region to memmap */
-static void __init add_memory_region(unsigned long long start,
- unsigned long long size, int type)
-{
- int i;
-
- i = bfin_memmap.nr_map;
-
- if (i == BFIN_MEMMAP_MAX) {
- printk(KERN_ERR "Ooops! Too many entries in the memory map!\n");
- return;
- }
-
- bfin_memmap.map[i].addr = start;
- bfin_memmap.map[i].size = size;
- bfin_memmap.map[i].type = type;
- bfin_memmap.nr_map++;
-}
-
-/*
- * Sanitize the boot memmap, removing overlaps.
- */
-static int __init sanitize_memmap(struct bfin_memmap_entry *map, int *pnr_map)
-{
- struct change_member *change_tmp;
- unsigned long current_type, last_type;
- unsigned long long last_addr;
- int chgidx, still_changing;
- int overlap_entries;
- int new_entry;
- int old_nr, new_nr, chg_nr;
- int i;
-
- /*
- Visually we're performing the following (1,2,3,4 = memory types)
-
- Sample memory map (w/overlaps):
- ____22__________________
- ______________________4_
- ____1111________________
- _44_____________________
- 11111111________________
- ____________________33__
- ___________44___________
- __________33333_________
- ______________22________
- ___________________2222_
- _________111111111______
- _____________________11_
- _________________4______
-
- Sanitized equivalent (no overlap):
- 1_______________________
- _44_____________________
- ___1____________________
- ____22__________________
- ______11________________
- _________1______________
- __________3_____________
- ___________44___________
- _____________33_________
- _______________2________
- ________________1_______
- _________________4______
- ___________________2____
- ____________________33__
- ______________________4_
- */
- /* if there's only one memory region, don't bother */
- if (*pnr_map < 2)
- return -1;
-
- old_nr = *pnr_map;
-
- /* bail out if we find any unreasonable addresses in memmap */
- for (i = 0; i < old_nr; i++)
- if (map[i].addr + map[i].size < map[i].addr)
- return -1;
-
- /* create pointers for initial change-point information (for sorting) */
- for (i = 0; i < 2*old_nr; i++)
- change_point[i] = &change_point_list[i];
-
- /* record all known change-points (starting and ending addresses),
- omitting those that are for empty memory regions */
- chgidx = 0;
- for (i = 0; i < old_nr; i++) {
- if (map[i].size != 0) {
- change_point[chgidx]->addr = map[i].addr;
- change_point[chgidx++]->pentry = &map[i];
- change_point[chgidx]->addr = map[i].addr + map[i].size;
- change_point[chgidx++]->pentry = &map[i];
- }
- }
- chg_nr = chgidx; /* true number of change-points */
-
- /* sort change-point list by memory addresses (low -> high) */
- still_changing = 1;
- while (still_changing) {
- still_changing = 0;
- for (i = 1; i < chg_nr; i++) {
- /* if <current_addr> > <last_addr>, swap */
- /* or, if current=<start_addr> & last=<end_addr>, swap */
- if ((change_point[i]->addr < change_point[i-1]->addr) ||
- ((change_point[i]->addr == change_point[i-1]->addr) &&
- (change_point[i]->addr == change_point[i]->pentry->addr) &&
- (change_point[i-1]->addr != change_point[i-1]->pentry->addr))
- ) {
- change_tmp = change_point[i];
- change_point[i] = change_point[i-1];
- change_point[i-1] = change_tmp;
- still_changing = 1;
- }
- }
- }
-
- /* create a new memmap, removing overlaps */
- overlap_entries = 0; /* number of entries in the overlap table */
- new_entry = 0; /* index for creating new memmap entries */
- last_type = 0; /* start with undefined memory type */
- last_addr = 0; /* start with 0 as last starting address */
- /* loop through change-points, determining affect on the new memmap */
- for (chgidx = 0; chgidx < chg_nr; chgidx++) {
- /* keep track of all overlapping memmap entries */
- if (change_point[chgidx]->addr == change_point[chgidx]->pentry->addr) {
- /* add map entry to overlap list (> 1 entry implies an overlap) */
- overlap_list[overlap_entries++] = change_point[chgidx]->pentry;
- } else {
- /* remove entry from list (order independent, so swap with last) */
- for (i = 0; i < overlap_entries; i++) {
- if (overlap_list[i] == change_point[chgidx]->pentry)
- overlap_list[i] = overlap_list[overlap_entries-1];
- }
- overlap_entries--;
- }
- /* if there are overlapping entries, decide which "type" to use */
- /* (larger value takes precedence -- 1=usable, 2,3,4,4+=unusable) */
- current_type = 0;
- for (i = 0; i < overlap_entries; i++)
- if (overlap_list[i]->type > current_type)
- current_type = overlap_list[i]->type;
- /* continue building up new memmap based on this information */
- if (current_type != last_type) {
- if (last_type != 0) {
- new_map[new_entry].size =
- change_point[chgidx]->addr - last_addr;
- /* move forward only if the new size was non-zero */
- if (new_map[new_entry].size != 0)
- if (++new_entry >= BFIN_MEMMAP_MAX)
- break; /* no more space left for new entries */
- }
- if (current_type != 0) {
- new_map[new_entry].addr = change_point[chgidx]->addr;
- new_map[new_entry].type = current_type;
- last_addr = change_point[chgidx]->addr;
- }
- last_type = current_type;
- }
- }
- new_nr = new_entry; /* retain count for new entries */
-
- /* copy new mapping into original location */
- memcpy(map, new_map, new_nr*sizeof(struct bfin_memmap_entry));
- *pnr_map = new_nr;
-
- return 0;
-}
-
-static void __init print_memory_map(char *who)
-{
- int i;
-
- for (i = 0; i < bfin_memmap.nr_map; i++) {
- printk(KERN_DEBUG " %s: %016Lx - %016Lx ", who,
- bfin_memmap.map[i].addr,
- bfin_memmap.map[i].addr + bfin_memmap.map[i].size);
- switch (bfin_memmap.map[i].type) {
- case BFIN_MEMMAP_RAM:
- printk(KERN_CONT "(usable)\n");
- break;
- case BFIN_MEMMAP_RESERVED:
- printk(KERN_CONT "(reserved)\n");
- break;
- default:
- printk(KERN_CONT "type %lu\n", bfin_memmap.map[i].type);
- break;
- }
- }
-}
-
-static __init int parse_memmap(char *arg)
-{
- unsigned long long start_at, mem_size;
-
- if (!arg)
- return -EINVAL;
-
- mem_size = memparse(arg, &arg);
- if (*arg == '@') {
- start_at = memparse(arg+1, &arg);
- add_memory_region(start_at, mem_size, BFIN_MEMMAP_RAM);
- } else if (*arg == '$') {
- start_at = memparse(arg+1, &arg);
- add_memory_region(start_at, mem_size, BFIN_MEMMAP_RESERVED);
- }
-
- return 0;
-}
-
-/*
- * Initial parsing of the command line. Currently, we support:
- * - Controlling the linux memory size: mem=xxx[KMG]
- * - Controlling the physical memory size: max_mem=xxx[KMG][$][#]
- * $ -> reserved memory is dcacheable
- * # -> reserved memory is icacheable
- * - "memmap=XXX[KkmM][@][$]XXX[KkmM]" defines a memory region
- * @ from <start> to <start>+<mem>, type RAM
- * $ from <start> to <start>+<mem>, type RESERVED
- */
-static __init void parse_cmdline_early(char *cmdline_p)
-{
- char c = ' ', *to = cmdline_p;
- unsigned int memsize;
- for (;;) {
- if (c == ' ') {
- if (!memcmp(to, "mem=", 4)) {
- to += 4;
- memsize = memparse(to, &to);
- if (memsize)
- _ramend = memsize;
-
- } else if (!memcmp(to, "max_mem=", 8)) {
- to += 8;
- memsize = memparse(to, &to);
- if (memsize) {
- physical_mem_end = memsize;
- if (*to != ' ') {
- if (*to == '$'
- || *(to + 1) == '$')
- reserved_mem_dcache_on = 1;
- if (*to == '#'
- || *(to + 1) == '#')
- reserved_mem_icache_on = 1;
- }
- }
- } else if (!memcmp(to, "clkin_hz=", 9)) {
- to += 9;
- early_init_clkin_hz(to);
-#ifdef CONFIG_EARLY_PRINTK
- } else if (!memcmp(to, "earlyprintk=", 12)) {
- to += 12;
- setup_early_printk(to);
-#endif
- } else if (!memcmp(to, "memmap=", 7)) {
- to += 7;
- parse_memmap(to);
- }
- }
- c = *(to++);
- if (!c)
- break;
- }
-}
-
-/*
- * Setup memory defaults from user config.
- * The physical memory layout looks like:
- *
- * [_rambase, _ramstart]: kernel image
- * [memory_start, memory_end]: dynamic memory managed by kernel
- * [memory_end, _ramend]: reserved memory
- * [memory_mtd_start(memory_end),
- * memory_mtd_start + mtd_size]: rootfs (if any)
- * [_ramend - DMA_UNCACHED_REGION,
- * _ramend]: uncached DMA region
- * [_ramend, physical_mem_end]: memory not managed by kernel
- */
-static __init void memory_setup(void)
-{
-#ifdef CONFIG_MTD_UCLINUX
- unsigned long mtd_phys = 0;
-#endif
- unsigned long max_mem;
-
- _rambase = CONFIG_BOOT_LOAD;
- _ramstart = (unsigned long)_end;
-
- if (DMA_UNCACHED_REGION > (_ramend - _ramstart)) {
- console_init();
- panic("DMA region exceeds memory limit: %lu.",
- _ramend - _ramstart);
- }
- max_mem = memory_end = _ramend - DMA_UNCACHED_REGION;
-
-#if (defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) && ANOMALY_05000263)
- /* Due to a Hardware Anomaly we need to limit the size of usable
- * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on
- * 05000263 - Hardware loop corrupted when taking an ICPLB exception
- */
-# if (defined(CONFIG_DEBUG_HUNT_FOR_ZERO))
- if (max_mem >= 56 * 1024 * 1024)
- max_mem = 56 * 1024 * 1024;
-# else
- if (max_mem >= 60 * 1024 * 1024)
- max_mem = 60 * 1024 * 1024;
-# endif /* CONFIG_DEBUG_HUNT_FOR_ZERO */
-#endif /* ANOMALY_05000263 */
-
-
-#ifdef CONFIG_MPU
- /* Round up to multiple of 4MB */
- memory_start = (_ramstart + 0x3fffff) & ~0x3fffff;
-#else
- memory_start = PAGE_ALIGN(_ramstart);
-#endif
-
-#if defined(CONFIG_MTD_UCLINUX)
- /* generic memory mapped MTD driver */
- memory_mtd_end = memory_end;
-
- mtd_phys = _ramstart;
- mtd_size = PAGE_ALIGN(*((unsigned long *)(mtd_phys + 8)));
-
-# if defined(CONFIG_EXT2_FS) || defined(CONFIG_EXT3_FS)
- if (*((unsigned short *)(mtd_phys + 0x438)) == EXT2_SUPER_MAGIC)
- mtd_size =
- PAGE_ALIGN(*((unsigned long *)(mtd_phys + 0x404)) << 10);
-# endif
-
-# if defined(CONFIG_CRAMFS)
- if (*((unsigned long *)(mtd_phys)) == CRAMFS_MAGIC)
- mtd_size = PAGE_ALIGN(*((unsigned long *)(mtd_phys + 0x4)));
-# endif
-
-# if defined(CONFIG_ROMFS_FS)
- if (((unsigned long *)mtd_phys)[0] == ROMSB_WORD0
- && ((unsigned long *)mtd_phys)[1] == ROMSB_WORD1) {
- mtd_size =
- PAGE_ALIGN(be32_to_cpu(((unsigned long *)mtd_phys)[2]));
-
- /* ROM_FS is XIP, so if we found it, we need to limit memory */
- if (memory_end > max_mem) {
- pr_info("Limiting kernel memory to %liMB due to anomaly 05000263\n",
- (max_mem - CONFIG_PHY_RAM_BASE_ADDRESS) >> 20);
- memory_end = max_mem;
- }
- }
-# endif /* CONFIG_ROMFS_FS */
-
- /* Since the default MTD_UCLINUX has no magic number, we just blindly
- * read 8 past the end of the kernel's image, and look at it.
- * When no image is attached, mtd_size is set to a random number
- * Do some basic sanity checks before operating on things
- */
- if (mtd_size == 0 || memory_end <= mtd_size) {
- pr_emerg("Could not find valid ram mtd attached.\n");
- } else {
- memory_end -= mtd_size;
-
- /* Relocate MTD image to the top of memory after the uncached memory area */
- uclinux_ram_map.phys = memory_mtd_start = memory_end;
- uclinux_ram_map.size = mtd_size;
- pr_info("Found mtd parition at 0x%p, (len=0x%lx), moving to 0x%p\n",
- _end, mtd_size, (void *)memory_mtd_start);
- dma_memcpy((void *)uclinux_ram_map.phys, _end, uclinux_ram_map.size);
- }
-#endif /* CONFIG_MTD_UCLINUX */
-
- /* We need lo limit memory, since everything could have a text section
- * of userspace in it, and expose anomaly 05000263. If the anomaly
- * doesn't exist, or we don't need to - then dont.
- */
- if (memory_end > max_mem) {
- pr_info("Limiting kernel memory to %liMB due to anomaly 05000263\n",
- (max_mem - CONFIG_PHY_RAM_BASE_ADDRESS) >> 20);
- memory_end = max_mem;
- }
-
-#ifdef CONFIG_MPU
-#if defined(CONFIG_ROMFS_ON_MTD) && defined(CONFIG_MTD_ROM)
- page_mask_nelts = (((_ramend + ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE -
- ASYNC_BANK0_BASE) >> PAGE_SHIFT) + 31) / 32;
-#else
- page_mask_nelts = ((_ramend >> PAGE_SHIFT) + 31) / 32;
-#endif
- page_mask_order = get_order(3 * page_mask_nelts * sizeof(long));
-#endif
-
- init_mm.start_code = (unsigned long)_stext;
- init_mm.end_code = (unsigned long)_etext;
- init_mm.end_data = (unsigned long)_edata;
- init_mm.brk = (unsigned long)0;
-
- printk(KERN_INFO "Board Memory: %ldMB\n", (physical_mem_end - CONFIG_PHY_RAM_BASE_ADDRESS) >> 20);
- printk(KERN_INFO "Kernel Managed Memory: %ldMB\n", (_ramend - CONFIG_PHY_RAM_BASE_ADDRESS) >> 20);
-
- printk(KERN_INFO "Memory map:\n"
- " fixedcode = 0x%p-0x%p\n"
- " text = 0x%p-0x%p\n"
- " rodata = 0x%p-0x%p\n"
- " bss = 0x%p-0x%p\n"
- " data = 0x%p-0x%p\n"
- " stack = 0x%p-0x%p\n"
- " init = 0x%p-0x%p\n"
- " available = 0x%p-0x%p\n"
-#ifdef CONFIG_MTD_UCLINUX
- " rootfs = 0x%p-0x%p\n"
-#endif
-#if DMA_UNCACHED_REGION > 0
- " DMA Zone = 0x%p-0x%p\n"
-#endif
- , (void *)FIXED_CODE_START, (void *)FIXED_CODE_END,
- _stext, _etext,
- __start_rodata, __end_rodata,
- __bss_start, __bss_stop,
- _sdata, _edata,
- (void *)&init_thread_union,
- (void *)((int)(&init_thread_union) + THREAD_SIZE),
- __init_begin, __init_end,
- (void *)_ramstart, (void *)memory_end
-#ifdef CONFIG_MTD_UCLINUX
- , (void *)memory_mtd_start, (void *)(memory_mtd_start + mtd_size)
-#endif
-#if DMA_UNCACHED_REGION > 0
- , (void *)(_ramend - DMA_UNCACHED_REGION), (void *)(_ramend)
-#endif
- );
-}
-
-/*
- * Find the lowest, highest page frame number we have available
- */
-void __init find_min_max_pfn(void)
-{
- int i;
-
- max_pfn = 0;
- min_low_pfn = PFN_DOWN(memory_end);
-
- for (i = 0; i < bfin_memmap.nr_map; i++) {
- unsigned long start, end;
- /* RAM? */
- if (bfin_memmap.map[i].type != BFIN_MEMMAP_RAM)
- continue;
- start = PFN_UP(bfin_memmap.map[i].addr);
- end = PFN_DOWN(bfin_memmap.map[i].addr +
- bfin_memmap.map[i].size);
- if (start >= end)
- continue;
- if (end > max_pfn)
- max_pfn = end;
- if (start < min_low_pfn)
- min_low_pfn = start;
- }
-}
-
-static __init void setup_bootmem_allocator(void)
-{
- int bootmap_size;
- int i;
- unsigned long start_pfn, end_pfn;
- unsigned long curr_pfn, last_pfn, size;
-
- /* mark memory between memory_start and memory_end usable */
- add_memory_region(memory_start,
- memory_end - memory_start, BFIN_MEMMAP_RAM);
- /* sanity check for overlap */
- sanitize_memmap(bfin_memmap.map, &bfin_memmap.nr_map);
- print_memory_map("boot memmap");
-
- /* initialize globals in linux/bootmem.h */
- find_min_max_pfn();
- /* pfn of the last usable page frame */
- if (max_pfn > memory_end >> PAGE_SHIFT)
- max_pfn = memory_end >> PAGE_SHIFT;
- /* pfn of last page frame directly mapped by kernel */
- max_low_pfn = max_pfn;
- /* pfn of the first usable page frame after kernel image*/
- if (min_low_pfn < memory_start >> PAGE_SHIFT)
- min_low_pfn = memory_start >> PAGE_SHIFT;
- start_pfn = CONFIG_PHY_RAM_BASE_ADDRESS >> PAGE_SHIFT;
- end_pfn = memory_end >> PAGE_SHIFT;
-
- /*
- * give all the memory to the bootmap allocator, tell it to put the
- * boot mem_map at the start of memory.
- */
- bootmap_size = init_bootmem_node(NODE_DATA(0),
- memory_start >> PAGE_SHIFT, /* map goes here */
- start_pfn, end_pfn);
-
- /* register the memmap regions with the bootmem allocator */
- for (i = 0; i < bfin_memmap.nr_map; i++) {
- /*
- * Reserve usable memory
- */
- if (bfin_memmap.map[i].type != BFIN_MEMMAP_RAM)
- continue;
- /*
- * We are rounding up the start address of usable memory:
- */
- curr_pfn = PFN_UP(bfin_memmap.map[i].addr);
- if (curr_pfn >= end_pfn)
- continue;
- /*
- * ... and at the end of the usable range downwards:
- */
- last_pfn = PFN_DOWN(bfin_memmap.map[i].addr +
- bfin_memmap.map[i].size);
-
- if (last_pfn > end_pfn)
- last_pfn = end_pfn;
-
- /*
- * .. finally, did all the rounding and playing
- * around just make the area go away?
- */
- if (last_pfn <= curr_pfn)
- continue;
-
- size = last_pfn - curr_pfn;
- free_bootmem(PFN_PHYS(curr_pfn), PFN_PHYS(size));
- }
-
- /* reserve memory before memory_start, including bootmap */
- reserve_bootmem(CONFIG_PHY_RAM_BASE_ADDRESS,
- memory_start + bootmap_size + PAGE_SIZE - 1 - CONFIG_PHY_RAM_BASE_ADDRESS,
- BOOTMEM_DEFAULT);
-}
-
-#define EBSZ_TO_MEG(ebsz) \
-({ \
- int meg = 0; \
- switch (ebsz & 0xf) { \
- case 0x1: meg = 16; break; \
- case 0x3: meg = 32; break; \
- case 0x5: meg = 64; break; \
- case 0x7: meg = 128; break; \
- case 0x9: meg = 256; break; \
- case 0xb: meg = 512; break; \
- } \
- meg; \
-})
-static inline int __init get_mem_size(void)
-{
-#if defined(EBIU_SDBCTL)
-# if defined(BF561_FAMILY)
- int ret = 0;
- u32 sdbctl = bfin_read_EBIU_SDBCTL();
- ret += EBSZ_TO_MEG(sdbctl >> 0);
- ret += EBSZ_TO_MEG(sdbctl >> 8);
- ret += EBSZ_TO_MEG(sdbctl >> 16);
- ret += EBSZ_TO_MEG(sdbctl >> 24);
- return ret;
-# else
- return EBSZ_TO_MEG(bfin_read_EBIU_SDBCTL());
-# endif
-#elif defined(EBIU_DDRCTL1)
- u32 ddrctl = bfin_read_EBIU_DDRCTL1();
- int ret = 0;
- switch (ddrctl & 0xc0000) {
- case DEVSZ_64:
- ret = 64 / 8;
- break;
- case DEVSZ_128:
- ret = 128 / 8;
- break;
- case DEVSZ_256:
- ret = 256 / 8;
- break;
- case DEVSZ_512:
- ret = 512 / 8;
- break;
- }
- switch (ddrctl & 0x30000) {
- case DEVWD_4:
- ret *= 2;
- case DEVWD_8:
- ret *= 2;
- case DEVWD_16:
- break;
- }
- if ((ddrctl & 0xc000) == 0x4000)
- ret *= 2;
- return ret;
-#elif defined(CONFIG_BF60x)
- u32 ddrctl = bfin_read_DMC0_CFG();
- int ret;
- switch (ddrctl & 0xf00) {
- case DEVSZ_64:
- ret = 64 / 8;
- break;
- case DEVSZ_128:
- ret = 128 / 8;
- break;
- case DEVSZ_256:
- ret = 256 / 8;
- break;
- case DEVSZ_512:
- ret = 512 / 8;
- break;
- case DEVSZ_1G:
- ret = 1024 / 8;
- break;
- case DEVSZ_2G:
- ret = 2048 / 8;
- break;
- }
- return ret;
-#endif
- BUG();
-}
-
-__attribute__((weak))
-void __init native_machine_early_platform_add_devices(void)
-{
-}
-
-#ifdef CONFIG_BF60x
-static inline u_long bfin_get_clk(char *name)
-{
- struct clk *clk;
- u_long clk_rate;
-
- clk = clk_get(NULL, name);
- if (IS_ERR(clk))
- return 0;
-
- clk_rate = clk_get_rate(clk);
- clk_put(clk);
- return clk_rate;
-}
-#endif
-
-void __init setup_arch(char **cmdline_p)
-{
- u32 mmr;
- unsigned long sclk, cclk;
-
- native_machine_early_platform_add_devices();
-
- enable_shadow_console();
-
- /* Check to make sure we are running on the right processor */
- mmr = bfin_cpuid();
- if (unlikely(CPUID != bfin_cpuid()))
- printk(KERN_ERR "ERROR: Not running on ADSP-%s: unknown CPUID 0x%04x Rev 0.%d\n",
- CPU, bfin_cpuid(), bfin_revid());
-
-#ifdef CONFIG_DUMMY_CONSOLE
- conswitchp = &dummy_con;
-#endif
-
-#if defined(CONFIG_CMDLINE_BOOL)
- strncpy(&command_line[0], CONFIG_CMDLINE, sizeof(command_line));
- command_line[sizeof(command_line) - 1] = 0;
-#endif
-
- /* Keep a copy of command line */
- *cmdline_p = &command_line[0];
- memcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
- boot_command_line[COMMAND_LINE_SIZE - 1] = '\0';
-
- memset(&bfin_memmap, 0, sizeof(bfin_memmap));
-
-#ifdef CONFIG_BF60x
- /* Should init clock device before parse command early */
- clk_init();
-#endif
- /* If the user does not specify things on the command line, use
- * what the bootloader set things up as
- */
- physical_mem_end = 0;
- parse_cmdline_early(&command_line[0]);
-
- if (_ramend == 0)
- _ramend = get_mem_size() * 1024 * 1024;
-
- if (physical_mem_end == 0)
- physical_mem_end = _ramend;
-
- memory_setup();
-
-#ifndef CONFIG_BF60x
- /* Initialize Async memory banks */
- bfin_write_EBIU_AMBCTL0(AMBCTL0VAL);
- bfin_write_EBIU_AMBCTL1(AMBCTL1VAL);
- bfin_write_EBIU_AMGCTL(AMGCTLVAL);
-#ifdef CONFIG_EBIU_MBSCTLVAL
- bfin_write_EBIU_MBSCTL(CONFIG_EBIU_MBSCTLVAL);
- bfin_write_EBIU_MODE(CONFIG_EBIU_MODEVAL);
- bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTLVAL);
-#endif
-#endif
-#ifdef CONFIG_BFIN_HYSTERESIS_CONTROL
- bfin_write_PORTF_HYSTERESIS(HYST_PORTF_0_15);
- bfin_write_PORTG_HYSTERESIS(HYST_PORTG_0_15);
- bfin_write_PORTH_HYSTERESIS(HYST_PORTH_0_15);
- bfin_write_MISCPORT_HYSTERESIS((bfin_read_MISCPORT_HYSTERESIS() &
- ~HYST_NONEGPIO_MASK) | HYST_NONEGPIO);
-#endif
-
- cclk = get_cclk();
- sclk = get_sclk();
-
- if ((ANOMALY_05000273 || ANOMALY_05000274) && (cclk >> 1) < sclk)
- panic("ANOMALY 05000273 or 05000274: CCLK must be >= 2*SCLK");
-
-#ifdef BF561_FAMILY
- if (ANOMALY_05000266) {
- bfin_read_IMDMA_D0_IRQ_STATUS();
- bfin_read_IMDMA_D1_IRQ_STATUS();
- }
-#endif
-
- mmr = bfin_read_TBUFCTL();
- printk(KERN_INFO "Hardware Trace %s and %sabled\n",
- (mmr & 0x1) ? "active" : "off",
- (mmr & 0x2) ? "en" : "dis");
-#ifndef CONFIG_BF60x
- mmr = bfin_read_SYSCR();
- printk(KERN_INFO "Boot Mode: %i\n", mmr & 0xF);
-
- /* Newer parts mirror SWRST bits in SYSCR */
-#if defined(CONFIG_BF53x) || defined(CONFIG_BF561) || \
- defined(CONFIG_BF538) || defined(CONFIG_BF539)
- _bfin_swrst = bfin_read_SWRST();
-#else
- /* Clear boot mode field */
- _bfin_swrst = mmr & ~0xf;
-#endif
-
-#ifdef CONFIG_DEBUG_DOUBLEFAULT_PRINT
- bfin_write_SWRST(_bfin_swrst & ~DOUBLE_FAULT);
-#endif
-#ifdef CONFIG_DEBUG_DOUBLEFAULT_RESET
- bfin_write_SWRST(_bfin_swrst | DOUBLE_FAULT);
-#endif
-
-#ifdef CONFIG_SMP
- if (_bfin_swrst & SWRST_DBL_FAULT_A) {
-#else
- if (_bfin_swrst & RESET_DOUBLE) {
-#endif
- printk(KERN_EMERG "Recovering from DOUBLE FAULT event\n");
-#ifdef CONFIG_DEBUG_DOUBLEFAULT
- /* We assume the crashing kernel, and the current symbol table match */
- printk(KERN_EMERG " While handling exception (EXCAUSE = %#x) at %pF\n",
- initial_pda.seqstat_doublefault & SEQSTAT_EXCAUSE,
- initial_pda.retx_doublefault);
- printk(KERN_NOTICE " DCPLB_FAULT_ADDR: %pF\n",
- initial_pda.dcplb_doublefault_addr);
- printk(KERN_NOTICE " ICPLB_FAULT_ADDR: %pF\n",
- initial_pda.icplb_doublefault_addr);
-#endif
- printk(KERN_NOTICE " The instruction at %pF caused a double exception\n",
- initial_pda.retx);
- } else if (_bfin_swrst & RESET_WDOG)
- printk(KERN_INFO "Recovering from Watchdog event\n");
- else if (_bfin_swrst & RESET_SOFTWARE)
- printk(KERN_NOTICE "Reset caused by Software reset\n");
-#endif
- printk(KERN_INFO "Blackfin support (C) 2004-2010 Analog Devices, Inc.\n");
- if (bfin_compiled_revid() == 0xffff)
- printk(KERN_INFO "Compiled for ADSP-%s Rev any, running on 0.%d\n", CPU, bfin_revid());
- else if (bfin_compiled_revid() == -1)
- printk(KERN_INFO "Compiled for ADSP-%s Rev none\n", CPU);
- else
- printk(KERN_INFO "Compiled for ADSP-%s Rev 0.%d\n", CPU, bfin_compiled_revid());
-
- if (likely(CPUID == bfin_cpuid())) {
- if (bfin_revid() != bfin_compiled_revid()) {
- if (bfin_compiled_revid() == -1)
- printk(KERN_ERR "Warning: Compiled for Rev none, but running on Rev %d\n",
- bfin_revid());
- else if (bfin_compiled_revid() != 0xffff) {
- printk(KERN_ERR "Warning: Compiled for Rev %d, but running on Rev %d\n",
- bfin_compiled_revid(), bfin_revid());
- if (bfin_compiled_revid() > bfin_revid())
- panic("Error: you are missing anomaly workarounds for this rev");
- }
- }
- if (bfin_revid() < CONFIG_BF_REV_MIN || bfin_revid() > CONFIG_BF_REV_MAX)
- printk(KERN_ERR "Warning: Unsupported Chip Revision ADSP-%s Rev 0.%d detected\n",
- CPU, bfin_revid());
- }
-
- printk(KERN_INFO "Blackfin Linux support by http://blackfin.uclinux.org/\n");
-
-#ifdef CONFIG_BF60x
- printk(KERN_INFO "Processor Speed: %lu MHz core clock, %lu MHz SCLk, %lu MHz SCLK0, %lu MHz SCLK1 and %lu MHz DCLK\n",
- cclk / 1000000, bfin_get_clk("SYSCLK") / 1000000, get_sclk0() / 1000000, get_sclk1() / 1000000, get_dclk() / 1000000);
-#else
- printk(KERN_INFO "Processor Speed: %lu MHz core clock and %lu MHz System Clock\n",
- cclk / 1000000, sclk / 1000000);
-#endif
-
- setup_bootmem_allocator();
-
- paging_init();
-
- /* Copy atomic sequences to their fixed location, and sanity check that
- these locations are the ones that we advertise to userspace. */
- memcpy((void *)FIXED_CODE_START, &fixed_code_start,
- FIXED_CODE_END - FIXED_CODE_START);
- BUG_ON((char *)&sigreturn_stub - (char *)&fixed_code_start
- != SIGRETURN_STUB - FIXED_CODE_START);
- BUG_ON((char *)&atomic_xchg32 - (char *)&fixed_code_start
- != ATOMIC_XCHG32 - FIXED_CODE_START);
- BUG_ON((char *)&atomic_cas32 - (char *)&fixed_code_start
- != ATOMIC_CAS32 - FIXED_CODE_START);
- BUG_ON((char *)&atomic_add32 - (char *)&fixed_code_start
- != ATOMIC_ADD32 - FIXED_CODE_START);
- BUG_ON((char *)&atomic_sub32 - (char *)&fixed_code_start
- != ATOMIC_SUB32 - FIXED_CODE_START);
- BUG_ON((char *)&atomic_ior32 - (char *)&fixed_code_start
- != ATOMIC_IOR32 - FIXED_CODE_START);
- BUG_ON((char *)&atomic_and32 - (char *)&fixed_code_start
- != ATOMIC_AND32 - FIXED_CODE_START);
- BUG_ON((char *)&atomic_xor32 - (char *)&fixed_code_start
- != ATOMIC_XOR32 - FIXED_CODE_START);
- BUG_ON((char *)&safe_user_instruction - (char *)&fixed_code_start
- != SAFE_USER_INSTRUCTION - FIXED_CODE_START);
-
-#ifdef CONFIG_SMP
- platform_init_cpus();
-#endif
- init_exception_vectors();
- bfin_cache_init(); /* Initialize caches for the boot CPU */
-#ifdef CONFIG_SCB_PRIORITY
- init_scb();
-#endif
-}
-
-static int __init topology_init(void)
-{
- unsigned int cpu;
-
- for_each_possible_cpu(cpu) {
- register_cpu(&per_cpu(cpu_data, cpu).cpu, cpu);
- }
-
- return 0;
-}
-
-subsys_initcall(topology_init);
-
-/* Get the input clock frequency */
-static u_long cached_clkin_hz = CONFIG_CLKIN_HZ;
-#ifndef CONFIG_BF60x
-static u_long get_clkin_hz(void)
-{
- return cached_clkin_hz;
-}
-#endif
-static int __init early_init_clkin_hz(char *buf)
-{
- cached_clkin_hz = simple_strtoul(buf, NULL, 0);
-#ifdef BFIN_KERNEL_CLOCK
- if (cached_clkin_hz != CONFIG_CLKIN_HZ)
- panic("cannot change clkin_hz when reprogramming clocks");
-#endif
- return 1;
-}
-early_param("clkin_hz=", early_init_clkin_hz);
-
-#ifndef CONFIG_BF60x
-/* Get the voltage input multiplier */
-static u_long get_vco(void)
-{
- static u_long cached_vco;
- u_long msel, pll_ctl;
-
- /* The assumption here is that VCO never changes at runtime.
- * If, someday, we support that, then we'll have to change this.
- */
- if (cached_vco)
- return cached_vco;
-
- pll_ctl = bfin_read_PLL_CTL();
- msel = (pll_ctl >> 9) & 0x3F;
- if (0 == msel)
- msel = 64;
-
- cached_vco = get_clkin_hz();
- cached_vco >>= (1 & pll_ctl); /* DF bit */
- cached_vco *= msel;
- return cached_vco;
-}
-#endif
-
-/* Get the Core clock */
-u_long get_cclk(void)
-{
-#ifdef CONFIG_BF60x
- return bfin_get_clk("CCLK");
-#else
- static u_long cached_cclk_pll_div, cached_cclk;
- u_long csel, ssel;
-
- if (bfin_read_PLL_STAT() & 0x1)
- return get_clkin_hz();
-
- ssel = bfin_read_PLL_DIV();
- if (ssel == cached_cclk_pll_div)
- return cached_cclk;
- else
- cached_cclk_pll_div = ssel;
-
- csel = ((ssel >> 4) & 0x03);
- ssel &= 0xf;
- if (ssel && ssel < (1 << csel)) /* SCLK > CCLK */
- cached_cclk = get_vco() / ssel;
- else
- cached_cclk = get_vco() >> csel;
- return cached_cclk;
-#endif
-}
-EXPORT_SYMBOL(get_cclk);
-
-#ifdef CONFIG_BF60x
-/* Get the bf60x clock of SCLK0 domain */
-u_long get_sclk0(void)
-{
- return bfin_get_clk("SCLK0");
-}
-EXPORT_SYMBOL(get_sclk0);
-
-/* Get the bf60x clock of SCLK1 domain */
-u_long get_sclk1(void)
-{
- return bfin_get_clk("SCLK1");
-}
-EXPORT_SYMBOL(get_sclk1);
-
-/* Get the bf60x DRAM clock */
-u_long get_dclk(void)
-{
- return bfin_get_clk("DCLK");
-}
-EXPORT_SYMBOL(get_dclk);
-#endif
-
-/* Get the default system clock */
-u_long get_sclk(void)
-{
-#ifdef CONFIG_BF60x
- return get_sclk0();
-#else
- static u_long cached_sclk;
- u_long ssel;
-
- /* The assumption here is that SCLK never changes at runtime.
- * If, someday, we support that, then we'll have to change this.
- */
- if (cached_sclk)
- return cached_sclk;
-
- if (bfin_read_PLL_STAT() & 0x1)
- return get_clkin_hz();
-
- ssel = bfin_read_PLL_DIV() & 0xf;
- if (0 == ssel) {
- printk(KERN_WARNING "Invalid System Clock\n");
- ssel = 1;
- }
-
- cached_sclk = get_vco() / ssel;
- return cached_sclk;
-#endif
-}
-EXPORT_SYMBOL(get_sclk);
-
-unsigned long sclk_to_usecs(unsigned long sclk)
-{
- u64 tmp = USEC_PER_SEC * (u64)sclk;
- do_div(tmp, get_sclk());
- return tmp;
-}
-EXPORT_SYMBOL(sclk_to_usecs);
-
-unsigned long usecs_to_sclk(unsigned long usecs)
-{
- u64 tmp = get_sclk() * (u64)usecs;
- do_div(tmp, USEC_PER_SEC);
- return tmp;
-}
-EXPORT_SYMBOL(usecs_to_sclk);
-
-/*
- * Get CPU information for use by the procfs.
- */
-static int show_cpuinfo(struct seq_file *m, void *v)
-{
- char *cpu, *mmu, *fpu, *vendor, *cache;
- uint32_t revid;
- int cpu_num = *(unsigned int *)v;
- u_long sclk, cclk;
- u_int icache_size = BFIN_ICACHESIZE / 1024, dcache_size = 0, dsup_banks = 0;
- struct blackfin_cpudata *cpudata = &per_cpu(cpu_data, cpu_num);
-
- cpu = CPU;
- mmu = "none";
- fpu = "none";
- revid = bfin_revid();
-
- sclk = get_sclk();
- cclk = get_cclk();
-
- switch (bfin_read_CHIPID() & CHIPID_MANUFACTURE) {
- case 0xca:
- vendor = "Analog Devices";
- break;
- default:
- vendor = "unknown";
- break;
- }
-
- seq_printf(m, "processor\t: %d\n" "vendor_id\t: %s\n", cpu_num, vendor);
-
- if (CPUID == bfin_cpuid())
- seq_printf(m, "cpu family\t: 0x%04x\n", CPUID);
- else
- seq_printf(m, "cpu family\t: Compiled for:0x%04x, running on:0x%04x\n",
- CPUID, bfin_cpuid());
-
- seq_printf(m, "model name\t: ADSP-%s %lu(MHz CCLK) %lu(MHz SCLK) (%s)\n"
- "stepping\t: %d ",
- cpu, cclk/1000000, sclk/1000000,
-#ifdef CONFIG_MPU
- "mpu on",
-#else
- "mpu off",
-#endif
- revid);
-
- if (bfin_revid() != bfin_compiled_revid()) {
- if (bfin_compiled_revid() == -1)
- seq_printf(m, "(Compiled for Rev none)");
- else if (bfin_compiled_revid() == 0xffff)
- seq_printf(m, "(Compiled for Rev any)");
- else
- seq_printf(m, "(Compiled for Rev %d)", bfin_compiled_revid());
- }
-
- seq_printf(m, "\ncpu MHz\t\t: %lu.%06lu/%lu.%06lu\n",
- cclk/1000000, cclk%1000000,
- sclk/1000000, sclk%1000000);
- seq_printf(m, "bogomips\t: %lu.%02lu\n"
- "Calibration\t: %lu loops\n",
- (loops_per_jiffy * HZ) / 500000,
- ((loops_per_jiffy * HZ) / 5000) % 100,
- (loops_per_jiffy * HZ));
-
- /* Check Cache configutation */
- switch (cpudata->dmemctl & (1 << DMC0_P | 1 << DMC1_P)) {
- case ACACHE_BSRAM:
- cache = "dbank-A/B\t: cache/sram";
- dcache_size = 16;
- dsup_banks = 1;
- break;
- case ACACHE_BCACHE:
- cache = "dbank-A/B\t: cache/cache";
- dcache_size = 32;
- dsup_banks = 2;
- break;
- case ASRAM_BSRAM:
- cache = "dbank-A/B\t: sram/sram";
- dcache_size = 0;
- dsup_banks = 0;
- break;
- default:
- cache = "unknown";
- dcache_size = 0;
- dsup_banks = 0;
- break;
- }
-
- /* Is it turned on? */
- if ((cpudata->dmemctl & (ENDCPLB | DMC_ENABLE)) != (ENDCPLB | DMC_ENABLE))
- dcache_size = 0;
-
- if ((cpudata->imemctl & (IMC | ENICPLB)) != (IMC | ENICPLB))
- icache_size = 0;
-
- seq_printf(m, "cache size\t: %d KB(L1 icache) "
- "%d KB(L1 dcache) %d KB(L2 cache)\n",
- icache_size, dcache_size, 0);
- seq_printf(m, "%s\n", cache);
- seq_printf(m, "external memory\t: "
-#if defined(CONFIG_BFIN_EXTMEM_ICACHEABLE)
- "cacheable"
-#else
- "uncacheable"
-#endif
- " in instruction cache\n");
- seq_printf(m, "external memory\t: "
-#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK)
- "cacheable (write-back)"
-#elif defined(CONFIG_BFIN_EXTMEM_WRITETHROUGH)
- "cacheable (write-through)"
-#else
- "uncacheable"
-#endif
- " in data cache\n");
-
- if (icache_size)
- seq_printf(m, "icache setup\t: %d Sub-banks/%d Ways, %d Lines/Way\n",
- BFIN_ISUBBANKS, BFIN_IWAYS, BFIN_ILINES);
- else
- seq_printf(m, "icache setup\t: off\n");
-
- seq_printf(m,
- "dcache setup\t: %d Super-banks/%d Sub-banks/%d Ways, %d Lines/Way\n",
- dsup_banks, BFIN_DSUBBANKS, BFIN_DWAYS,
- BFIN_DLINES);
-#ifdef __ARCH_SYNC_CORE_DCACHE
- seq_printf(m, "dcache flushes\t: %lu\n", dcache_invld_count[cpu_num]);
-#endif
-#ifdef __ARCH_SYNC_CORE_ICACHE
- seq_printf(m, "icache flushes\t: %lu\n", icache_invld_count[cpu_num]);
-#endif
-
- seq_printf(m, "\n");
-
- if (cpu_num != num_possible_cpus() - 1)
- return 0;
-
- if (L2_LENGTH) {
- seq_printf(m, "L2 SRAM\t\t: %dKB\n", L2_LENGTH/0x400);
- seq_printf(m, "L2 SRAM\t\t: "
-#if defined(CONFIG_BFIN_L2_ICACHEABLE)
- "cacheable"
-#else
- "uncacheable"
-#endif
- " in instruction cache\n");
- seq_printf(m, "L2 SRAM\t\t: "
-#if defined(CONFIG_BFIN_L2_WRITEBACK)
- "cacheable (write-back)"
-#elif defined(CONFIG_BFIN_L2_WRITETHROUGH)
- "cacheable (write-through)"
-#else
- "uncacheable"
-#endif
- " in data cache\n");
- }
- seq_printf(m, "board name\t: %s\n", bfin_board_name);
- seq_printf(m, "board memory\t: %ld kB (0x%08lx -> 0x%08lx)\n",
- physical_mem_end >> 10, 0ul, physical_mem_end);
- seq_printf(m, "kernel memory\t: %d kB (0x%08lx -> 0x%08lx)\n",
- ((int)memory_end - (int)_rambase) >> 10,
- _rambase, memory_end);
-
- return 0;
-}
-
-static void *c_start(struct seq_file *m, loff_t *pos)
-{
- if (*pos == 0)
- *pos = cpumask_first(cpu_online_mask);
- if (*pos >= num_online_cpus())
- return NULL;
-
- return pos;
-}
-
-static void *c_next(struct seq_file *m, void *v, loff_t *pos)
-{
- *pos = cpumask_next(*pos, cpu_online_mask);
-
- return c_start(m, pos);
-}
-
-static void c_stop(struct seq_file *m, void *v)
-{
-}
-
-const struct seq_operations cpuinfo_op = {
- .start = c_start,
- .next = c_next,
- .stop = c_stop,
- .show = show_cpuinfo,
-};
-
-void __init cmdline_init(const char *r0)
-{
- early_shadow_stamp();
- if (r0)
- strlcpy(command_line, r0, COMMAND_LINE_SIZE);
-}
+++ /dev/null
-/*
- * manage a small early shadow of the log buffer which we can pass between the
- * bootloader so early crash messages are communicated properly and easily
- *
- * Copyright 2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/console.h>
-#include <linux/string.h>
-#include <asm/blackfin.h>
-#include <asm/irq_handler.h>
-#include <asm/early_printk.h>
-
-#define SHADOW_CONSOLE_START (CONFIG_PHY_RAM_BASE_ADDRESS + 0x500)
-#define SHADOW_CONSOLE_END (CONFIG_PHY_RAM_BASE_ADDRESS + 0x1000)
-#define SHADOW_CONSOLE_MAGIC_LOC (CONFIG_PHY_RAM_BASE_ADDRESS + 0x4F0)
-#define SHADOW_CONSOLE_MAGIC (0xDEADBEEF)
-
-static __initdata char *shadow_console_buffer = (char *)SHADOW_CONSOLE_START;
-
-__init void early_shadow_write(struct console *con, const char *s,
- unsigned int n)
-{
- unsigned int i;
- /*
- * save 2 bytes for the double null at the end
- * once we fail on a long line, make sure we don't write a short line afterwards
- */
- if ((shadow_console_buffer + n) <= (char *)(SHADOW_CONSOLE_END - 2)) {
- /* can't use memcpy - it may not be relocated yet */
- for (i = 0; i <= n; i++)
- shadow_console_buffer[i] = s[i];
- shadow_console_buffer += n;
- shadow_console_buffer[0] = 0;
- shadow_console_buffer[1] = 0;
- } else
- shadow_console_buffer = (char *)SHADOW_CONSOLE_END;
-}
-
-static __initdata struct console early_shadow_console = {
- .name = "early_shadow",
- .write = early_shadow_write,
- .flags = CON_BOOT | CON_PRINTBUFFER,
- .index = -1,
- .device = 0,
-};
-
-__init int shadow_console_enabled(void)
-{
- return early_shadow_console.flags & CON_ENABLED;
-}
-
-__init void mark_shadow_error(void)
-{
- int *loc = (int *)SHADOW_CONSOLE_MAGIC_LOC;
- loc[0] = SHADOW_CONSOLE_MAGIC;
- loc[1] = SHADOW_CONSOLE_START;
-}
-
-__init void enable_shadow_console(void)
-{
- if (!shadow_console_enabled()) {
- register_console(&early_shadow_console);
- /* for now, assume things are going to fail */
- mark_shadow_error();
- }
-}
-
-static __init int disable_shadow_console(void)
-{
- /*
- * by the time pure_initcall runs, the standard console is enabled,
- * and the early_console is off, so unset the magic numbers
- * unregistering the console is taken care of in common code (See
- * ./kernel/printk:disable_boot_consoles() )
- */
- int *loc = (int *)SHADOW_CONSOLE_MAGIC_LOC;
-
- loc[0] = 0;
-
- return 0;
-}
-pure_initcall(disable_shadow_console);
-
-/*
- * since we can't use printk, dump numbers (as hex), n = # bits
- */
-__init void early_shadow_reg(unsigned long reg, unsigned int n)
-{
- /*
- * can't use any "normal" kernel features, since thay
- * may not be relocated to their execute address yet
- */
- int i;
- char ascii[11] = " 0x";
-
- n = n / 4;
- reg = reg << ((8 - n) * 4);
- n += 3;
-
- for (i = 3; i <= n ; i++) {
- ascii[i] = hex_asc_lo(reg >> 28);
- reg <<= 4;
- }
- early_shadow_write(NULL, ascii, n);
-
-}
+++ /dev/null
-/*
- * Copyright 2004-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <linux/signal.h>
-#include <linux/syscalls.h>
-#include <linux/ptrace.h>
-#include <linux/tty.h>
-#include <linux/personality.h>
-#include <linux/binfmts.h>
-#include <linux/uaccess.h>
-#include <linux/tracehook.h>
-#include <linux/sched/task_stack.h>
-
-#include <asm/cacheflush.h>
-#include <asm/ucontext.h>
-#include <asm/fixed_code.h>
-#include <asm/syscall.h>
-
-/* Location of the trace bit in SYSCFG. */
-#define TRACE_BITS 0x0001
-
-struct fdpic_func_descriptor {
- unsigned long text;
- unsigned long GOT;
-};
-
-struct rt_sigframe {
- int sig;
- struct siginfo *pinfo;
- void *puc;
- /* This is no longer needed by the kernel, but unfortunately userspace
- * code expects it to be there. */
- char retcode[8];
- struct siginfo info;
- struct ucontext uc;
-};
-
-static inline int
-rt_restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc, int *pr0)
-{
- unsigned long usp = 0;
- int err = 0;
-
- /* Always make any pending restarted system calls return -EINTR */
- current->restart_block.fn = do_no_restart_syscall;
-
-#define RESTORE(x) err |= __get_user(regs->x, &sc->sc_##x)
-
- /* restore passed registers */
- RESTORE(r0); RESTORE(r1); RESTORE(r2); RESTORE(r3);
- RESTORE(r4); RESTORE(r5); RESTORE(r6); RESTORE(r7);
- RESTORE(p0); RESTORE(p1); RESTORE(p2); RESTORE(p3);
- RESTORE(p4); RESTORE(p5);
- err |= __get_user(usp, &sc->sc_usp);
- wrusp(usp);
- RESTORE(a0w); RESTORE(a1w);
- RESTORE(a0x); RESTORE(a1x);
- RESTORE(astat);
- RESTORE(rets);
- RESTORE(pc);
- RESTORE(retx);
- RESTORE(fp);
- RESTORE(i0); RESTORE(i1); RESTORE(i2); RESTORE(i3);
- RESTORE(m0); RESTORE(m1); RESTORE(m2); RESTORE(m3);
- RESTORE(l0); RESTORE(l1); RESTORE(l2); RESTORE(l3);
- RESTORE(b0); RESTORE(b1); RESTORE(b2); RESTORE(b3);
- RESTORE(lc0); RESTORE(lc1);
- RESTORE(lt0); RESTORE(lt1);
- RESTORE(lb0); RESTORE(lb1);
- RESTORE(seqstat);
-
- regs->orig_p0 = -1; /* disable syscall checks */
-
- *pr0 = regs->r0;
- return err;
-}
-
-asmlinkage int sys_rt_sigreturn(void)
-{
- struct pt_regs *regs = current_pt_regs();
- unsigned long usp = rdusp();
- struct rt_sigframe *frame = (struct rt_sigframe *)(usp);
- sigset_t set;
- int r0;
-
- if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
- goto badframe;
- if (__copy_from_user(&set, &frame->uc.uc_sigmask, sizeof(set)))
- goto badframe;
-
- set_current_blocked(&set);
-
- if (rt_restore_sigcontext(regs, &frame->uc.uc_mcontext, &r0))
- goto badframe;
-
- if (restore_altstack(&frame->uc.uc_stack))
- goto badframe;
-
- return r0;
-
- badframe:
- force_sig(SIGSEGV, current);
- return 0;
-}
-
-static inline int rt_setup_sigcontext(struct sigcontext *sc, struct pt_regs *regs)
-{
- int err = 0;
-
-#define SETUP(x) err |= __put_user(regs->x, &sc->sc_##x)
-
- SETUP(r0); SETUP(r1); SETUP(r2); SETUP(r3);
- SETUP(r4); SETUP(r5); SETUP(r6); SETUP(r7);
- SETUP(p0); SETUP(p1); SETUP(p2); SETUP(p3);
- SETUP(p4); SETUP(p5);
- err |= __put_user(rdusp(), &sc->sc_usp);
- SETUP(a0w); SETUP(a1w);
- SETUP(a0x); SETUP(a1x);
- SETUP(astat);
- SETUP(rets);
- SETUP(pc);
- SETUP(retx);
- SETUP(fp);
- SETUP(i0); SETUP(i1); SETUP(i2); SETUP(i3);
- SETUP(m0); SETUP(m1); SETUP(m2); SETUP(m3);
- SETUP(l0); SETUP(l1); SETUP(l2); SETUP(l3);
- SETUP(b0); SETUP(b1); SETUP(b2); SETUP(b3);
- SETUP(lc0); SETUP(lc1);
- SETUP(lt0); SETUP(lt1);
- SETUP(lb0); SETUP(lb1);
- SETUP(seqstat);
-
- return err;
-}
-
-static inline void *get_sigframe(struct ksignal *ksig,
- size_t frame_size)
-{
- unsigned long usp = sigsp(rdusp(), ksig);
-
- return (void *)((usp - frame_size) & -8UL);
-}
-
-static int
-setup_rt_frame(struct ksignal *ksig, sigset_t *set, struct pt_regs *regs)
-{
- struct rt_sigframe *frame;
- int err = 0;
-
- frame = get_sigframe(ksig, sizeof(*frame));
-
- err |= __put_user(ksig->sig, &frame->sig);
-
- err |= __put_user(&frame->info, &frame->pinfo);
- err |= __put_user(&frame->uc, &frame->puc);
- err |= copy_siginfo_to_user(&frame->info, &ksig->info);
-
- /* Create the ucontext. */
- err |= __put_user(0, &frame->uc.uc_flags);
- err |= __put_user(0, &frame->uc.uc_link);
- err |= __save_altstack(&frame->uc.uc_stack, rdusp());
- err |= rt_setup_sigcontext(&frame->uc.uc_mcontext, regs);
- err |= copy_to_user(&frame->uc.uc_sigmask, set, sizeof(*set));
-
- if (err)
- return -EFAULT;
-
- /* Set up registers for signal handler */
- if (current->personality & FDPIC_FUNCPTRS) {
- struct fdpic_func_descriptor __user *funcptr =
- (struct fdpic_func_descriptor *) ksig->ka.sa.sa_handler;
- u32 pc, p3;
- err |= __get_user(pc, &funcptr->text);
- err |= __get_user(p3, &funcptr->GOT);
- if (err)
- return -EFAULT;
- regs->pc = pc;
- regs->p3 = p3;
- } else
- regs->pc = (unsigned long)ksig->ka.sa.sa_handler;
- wrusp((unsigned long)frame);
- regs->rets = SIGRETURN_STUB;
-
- regs->r0 = frame->sig;
- regs->r1 = (unsigned long)(&frame->info);
- regs->r2 = (unsigned long)(&frame->uc);
-
- return 0;
-}
-
-static inline void
-handle_restart(struct pt_regs *regs, struct k_sigaction *ka, int has_handler)
-{
- switch (regs->r0) {
- case -ERESTARTNOHAND:
- if (!has_handler)
- goto do_restart;
- regs->r0 = -EINTR;
- break;
-
- case -ERESTARTSYS:
- if (has_handler && !(ka->sa.sa_flags & SA_RESTART)) {
- regs->r0 = -EINTR;
- break;
- }
- /* fallthrough */
- case -ERESTARTNOINTR:
- do_restart:
- regs->p0 = regs->orig_p0;
- regs->r0 = regs->orig_r0;
- regs->pc -= 2;
- break;
-
- case -ERESTART_RESTARTBLOCK:
- regs->p0 = __NR_restart_syscall;
- regs->pc -= 2;
- break;
- }
-}
-
-/*
- * OK, we're invoking a handler
- */
-static void
-handle_signal(struct ksignal *ksig, struct pt_regs *regs)
-{
- int ret;
-
- /* are we from a system call? to see pt_regs->orig_p0 */
- if (regs->orig_p0 >= 0)
- /* If so, check system call restarting.. */
- handle_restart(regs, &ksig->ka, 1);
-
- /* set up the stack frame */
- ret = setup_rt_frame(ksig, sigmask_to_save(), regs);
-
- signal_setup_done(ret, ksig, test_thread_flag(TIF_SINGLESTEP));
-}
-
-/*
- * Note that 'init' is a special process: it doesn't get signals it doesn't
- * want to handle. Thus you cannot kill init even with a SIGKILL even by
- * mistake.
- *
- * Note that we go through the signals twice: once to check the signals
- * that the kernel can handle, and then we build all the user-level signal
- * handling stack-frames in one go after that.
- */
-asmlinkage void do_signal(struct pt_regs *regs)
-{
- struct ksignal ksig;
-
- current->thread.esp0 = (unsigned long)regs;
-
- if (get_signal(&ksig)) {
- /* Whee! Actually deliver the signal. */
- handle_signal(&ksig, regs);
- return;
- }
-
- /* Did we come from a system call? */
- if (regs->orig_p0 >= 0)
- /* Restart the system call - no handlers present */
- handle_restart(regs, NULL, 0);
-
- /* if there's no signal to deliver, we just put the saved sigmask
- * back */
- restore_saved_sigmask();
-}
-
-/*
- * notification of userspace execution resumption
- */
-asmlinkage void do_notify_resume(struct pt_regs *regs)
-{
- if (test_thread_flag(TIF_SIGPENDING))
- do_signal(regs);
-
- if (test_thread_flag(TIF_NOTIFY_RESUME)) {
- clear_thread_flag(TIF_NOTIFY_RESUME);
- tracehook_notify_resume(regs);
- }
-}
-
+++ /dev/null
-/*
- * Blackfin stacktrace code (mostly copied from avr32)
- *
- * Copyright 2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/sched.h>
-#include <linux/sched/task_stack.h>
-#include <linux/stacktrace.h>
-#include <linux/thread_info.h>
-#include <linux/module.h>
-
-register unsigned long current_frame_pointer asm("FP");
-
-struct stackframe {
- unsigned long fp;
- unsigned long rets;
-};
-
-/*
- * Save stack-backtrace addresses into a stack_trace buffer.
- */
-void save_stack_trace(struct stack_trace *trace)
-{
- unsigned long low, high;
- unsigned long fp;
- struct stackframe *frame;
- int skip = trace->skip;
-
- low = (unsigned long)task_stack_page(current);
- high = low + THREAD_SIZE;
- fp = current_frame_pointer;
-
- while (fp >= low && fp <= (high - sizeof(*frame))) {
- frame = (struct stackframe *)fp;
-
- if (skip) {
- skip--;
- } else {
- trace->entries[trace->nr_entries++] = frame->rets;
- if (trace->nr_entries >= trace->max_entries)
- break;
- }
-
- /*
- * The next frame must be at a higher address than the
- * current frame.
- */
- low = fp + sizeof(*frame);
- fp = frame->fp;
- }
-}
-EXPORT_SYMBOL_GPL(save_stack_trace);
+++ /dev/null
-/*
- * contains various random system calls that have a non-standard
- * calling sequence on the Linux/Blackfin platform.
- *
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <linux/spinlock.h>
-#include <linux/sem.h>
-#include <linux/msg.h>
-#include <linux/shm.h>
-#include <linux/syscalls.h>
-#include <linux/mman.h>
-#include <linux/file.h>
-#include <linux/fs.h>
-#include <linux/uaccess.h>
-#include <linux/ipc.h>
-#include <linux/unistd.h>
-
-#include <asm/cacheflush.h>
-#include <asm/dma.h>
-#include <asm/cachectl.h>
-#include <asm/ptrace.h>
-
-asmlinkage void *sys_sram_alloc(size_t size, unsigned long flags)
-{
- return sram_alloc_with_lsl(size, flags);
-}
-
-asmlinkage int sys_sram_free(const void *addr)
-{
- return sram_free_with_lsl(addr);
-}
-
-asmlinkage void *sys_dma_memcpy(void *dest, const void *src, size_t len)
-{
- return safe_dma_memcpy(dest, src, len);
-}
-
-#if defined(CONFIG_FB) || defined(CONFIG_FB_MODULE)
-#include <linux/fb.h>
-#include <linux/export.h>
-unsigned long get_fb_unmapped_area(struct file *filp, unsigned long orig_addr,
- unsigned long len, unsigned long pgoff, unsigned long flags)
-{
- struct fb_info *info = filp->private_data;
- return (unsigned long)info->screen_base;
-}
-EXPORT_SYMBOL(get_fb_unmapped_area);
-#endif
-
-/* Needed for legacy userspace atomic emulation */
-static DEFINE_SPINLOCK(bfin_spinlock_lock);
-
-#ifdef CONFIG_SYS_BFIN_SPINLOCK_L1
-__attribute__((l1_text))
-#endif
-asmlinkage int sys_bfin_spinlock(int *p)
-{
- int ret, tmp = 0;
-
- spin_lock(&bfin_spinlock_lock); /* This would also hold kernel preemption. */
- ret = get_user(tmp, p);
- if (likely(ret == 0)) {
- if (unlikely(tmp))
- ret = 1;
- else
- put_user(1, p);
- }
- spin_unlock(&bfin_spinlock_lock);
-
- return ret;
-}
-
-SYSCALL_DEFINE3(cacheflush, unsigned long, addr, unsigned long, len, int, op)
-{
- if (is_user_addr_valid(current, addr, len) != 0)
- return -EINVAL;
-
- if (op & DCACHE)
- blackfin_dcache_flush_range(addr, addr + len);
- if (op & ICACHE)
- blackfin_icache_flush_range(addr, addr + len);
-
- return 0;
-}
+++ /dev/null
-/*
- * Based on arm clockevents implementation and old bfin time tick.
- *
- * Copyright 2008-2009 Analog Devics Inc.
- * 2008 GeoTechnologies
- * Vitja Makarov
- *
- * Licensed under the GPL-2
- */
-
-#include <linux/module.h>
-#include <linux/profile.h>
-#include <linux/interrupt.h>
-#include <linux/time.h>
-#include <linux/timex.h>
-#include <linux/irq.h>
-#include <linux/clocksource.h>
-#include <linux/clockchips.h>
-#include <linux/cpufreq.h>
-
-#include <asm/blackfin.h>
-#include <asm/time.h>
-#include <asm/gptimers.h>
-#include <asm/nmi.h>
-
-
-#if defined(CONFIG_CYCLES_CLOCKSOURCE)
-
-static notrace u64 bfin_read_cycles(struct clocksource *cs)
-{
-#ifdef CONFIG_CPU_FREQ
- return __bfin_cycles_off + (get_cycles() << __bfin_cycles_mod);
-#else
- return get_cycles();
-#endif
-}
-
-static struct clocksource bfin_cs_cycles = {
- .name = "bfin_cs_cycles",
- .rating = 400,
- .read = bfin_read_cycles,
- .mask = CLOCKSOURCE_MASK(64),
- .flags = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-
-static inline unsigned long long bfin_cs_cycles_sched_clock(void)
-{
- return clocksource_cyc2ns(bfin_read_cycles(&bfin_cs_cycles),
- bfin_cs_cycles.mult, bfin_cs_cycles.shift);
-}
-
-static int __init bfin_cs_cycles_init(void)
-{
- if (clocksource_register_hz(&bfin_cs_cycles, get_cclk()))
- panic("failed to register clocksource");
-
- return 0;
-}
-#else
-# define bfin_cs_cycles_init()
-#endif
-
-#ifdef CONFIG_GPTMR0_CLOCKSOURCE
-
-void __init setup_gptimer0(void)
-{
- disable_gptimers(TIMER0bit);
-
-#ifdef CONFIG_BF60x
- bfin_write16(TIMER_DATA_IMSK, 0);
- set_gptimer_config(TIMER0_id, TIMER_OUT_DIS
- | TIMER_MODE_PWM_CONT | TIMER_PULSE_HI | TIMER_IRQ_PER);
-#else
- set_gptimer_config(TIMER0_id, \
- TIMER_OUT_DIS | TIMER_PERIOD_CNT | TIMER_MODE_PWM);
-#endif
- set_gptimer_period(TIMER0_id, -1);
- set_gptimer_pwidth(TIMER0_id, -2);
- SSYNC();
- enable_gptimers(TIMER0bit);
-}
-
-static u64 bfin_read_gptimer0(struct clocksource *cs)
-{
- return bfin_read_TIMER0_COUNTER();
-}
-
-static struct clocksource bfin_cs_gptimer0 = {
- .name = "bfin_cs_gptimer0",
- .rating = 350,
- .read = bfin_read_gptimer0,
- .mask = CLOCKSOURCE_MASK(32),
- .flags = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-
-static inline unsigned long long bfin_cs_gptimer0_sched_clock(void)
-{
- return clocksource_cyc2ns(bfin_read_TIMER0_COUNTER(),
- bfin_cs_gptimer0.mult, bfin_cs_gptimer0.shift);
-}
-
-static int __init bfin_cs_gptimer0_init(void)
-{
- setup_gptimer0();
-
- if (clocksource_register_hz(&bfin_cs_gptimer0, get_sclk()))
- panic("failed to register clocksource");
-
- return 0;
-}
-#else
-# define bfin_cs_gptimer0_init()
-#endif
-
-#if defined(CONFIG_GPTMR0_CLOCKSOURCE) || defined(CONFIG_CYCLES_CLOCKSOURCE)
-/* prefer to use cycles since it has higher rating */
-notrace unsigned long long sched_clock(void)
-{
-#if defined(CONFIG_CYCLES_CLOCKSOURCE)
- return bfin_cs_cycles_sched_clock();
-#else
- return bfin_cs_gptimer0_sched_clock();
-#endif
-}
-#endif
-
-#if defined(CONFIG_TICKSOURCE_GPTMR0)
-static int bfin_gptmr0_set_next_event(unsigned long cycles,
- struct clock_event_device *evt)
-{
- disable_gptimers(TIMER0bit);
-
- /* it starts counting three SCLK cycles after the TIMENx bit is set */
- set_gptimer_pwidth(TIMER0_id, cycles - 3);
- enable_gptimers(TIMER0bit);
- return 0;
-}
-
-static int bfin_gptmr0_set_periodic(struct clock_event_device *evt)
-{
-#ifndef CONFIG_BF60x
- set_gptimer_config(TIMER0_id,
- TIMER_OUT_DIS | TIMER_IRQ_ENA |
- TIMER_PERIOD_CNT | TIMER_MODE_PWM);
-#else
- set_gptimer_config(TIMER0_id,
- TIMER_OUT_DIS | TIMER_MODE_PWM_CONT |
- TIMER_PULSE_HI | TIMER_IRQ_PER);
-#endif
-
- set_gptimer_period(TIMER0_id, get_sclk() / HZ);
- set_gptimer_pwidth(TIMER0_id, get_sclk() / HZ - 1);
- enable_gptimers(TIMER0bit);
- return 0;
-}
-
-static int bfin_gptmr0_set_oneshot(struct clock_event_device *evt)
-{
- disable_gptimers(TIMER0bit);
-#ifndef CONFIG_BF60x
- set_gptimer_config(TIMER0_id,
- TIMER_OUT_DIS | TIMER_IRQ_ENA | TIMER_MODE_PWM);
-#else
- set_gptimer_config(TIMER0_id,
- TIMER_OUT_DIS | TIMER_MODE_PWM | TIMER_PULSE_HI |
- TIMER_IRQ_WID_DLY);
-#endif
-
- set_gptimer_period(TIMER0_id, 0);
- return 0;
-}
-
-static int bfin_gptmr0_shutdown(struct clock_event_device *evt)
-{
- disable_gptimers(TIMER0bit);
- return 0;
-}
-
-static void bfin_gptmr0_ack(void)
-{
- clear_gptimer_intr(TIMER0_id);
-}
-
-static void __init bfin_gptmr0_init(void)
-{
- disable_gptimers(TIMER0bit);
-}
-
-#ifdef CONFIG_CORE_TIMER_IRQ_L1
-__attribute__((l1_text))
-#endif
-irqreturn_t bfin_gptmr0_interrupt(int irq, void *dev_id)
-{
- struct clock_event_device *evt = dev_id;
- smp_mb();
- /*
- * We want to ACK before we handle so that we can handle smaller timer
- * intervals. This way if the timer expires again while we're handling
- * things, we're more likely to see that 2nd int rather than swallowing
- * it by ACKing the int at the end of this handler.
- */
- bfin_gptmr0_ack();
- evt->event_handler(evt);
- return IRQ_HANDLED;
-}
-
-static struct irqaction gptmr0_irq = {
- .name = "Blackfin GPTimer0",
- .flags = IRQF_TIMER | IRQF_IRQPOLL | IRQF_PERCPU,
- .handler = bfin_gptmr0_interrupt,
-};
-
-static struct clock_event_device clockevent_gptmr0 = {
- .name = "bfin_gptimer0",
- .rating = 300,
- .irq = IRQ_TIMER0,
- .shift = 32,
- .features = CLOCK_EVT_FEAT_PERIODIC |
- CLOCK_EVT_FEAT_ONESHOT,
- .set_next_event = bfin_gptmr0_set_next_event,
- .set_state_shutdown = bfin_gptmr0_shutdown,
- .set_state_periodic = bfin_gptmr0_set_periodic,
- .set_state_oneshot = bfin_gptmr0_set_oneshot,
-};
-
-static void __init bfin_gptmr0_clockevent_init(struct clock_event_device *evt)
-{
- unsigned long clock_tick;
-
- clock_tick = get_sclk();
- evt->mult = div_sc(clock_tick, NSEC_PER_SEC, evt->shift);
- evt->max_delta_ns = clockevent_delta2ns(-1, evt);
- evt->max_delta_ticks = (unsigned long)-1;
- evt->min_delta_ns = clockevent_delta2ns(100, evt);
- evt->min_delta_ticks = 100;
-
- evt->cpumask = cpumask_of(0);
-
- clockevents_register_device(evt);
-}
-#endif /* CONFIG_TICKSOURCE_GPTMR0 */
-
-#if defined(CONFIG_TICKSOURCE_CORETMR)
-/* per-cpu local core timer */
-DEFINE_PER_CPU(struct clock_event_device, coretmr_events);
-
-static int bfin_coretmr_set_next_event(unsigned long cycles,
- struct clock_event_device *evt)
-{
- bfin_write_TCNTL(TMPWR);
- CSYNC();
- bfin_write_TCOUNT(cycles);
- CSYNC();
- bfin_write_TCNTL(TMPWR | TMREN);
- return 0;
-}
-
-static int bfin_coretmr_set_periodic(struct clock_event_device *evt)
-{
- unsigned long tcount = ((get_cclk() / (HZ * TIME_SCALE)) - 1);
-
- bfin_write_TCNTL(TMPWR);
- CSYNC();
- bfin_write_TSCALE(TIME_SCALE - 1);
- bfin_write_TPERIOD(tcount);
- bfin_write_TCOUNT(tcount);
- CSYNC();
- bfin_write_TCNTL(TMPWR | TMREN | TAUTORLD);
- return 0;
-}
-
-static int bfin_coretmr_set_oneshot(struct clock_event_device *evt)
-{
- bfin_write_TCNTL(TMPWR);
- CSYNC();
- bfin_write_TSCALE(TIME_SCALE - 1);
- bfin_write_TPERIOD(0);
- bfin_write_TCOUNT(0);
- return 0;
-}
-
-static int bfin_coretmr_shutdown(struct clock_event_device *evt)
-{
- bfin_write_TCNTL(0);
- CSYNC();
- return 0;
-}
-
-void bfin_coretmr_init(void)
-{
- /* power up the timer, but don't enable it just yet */
- bfin_write_TCNTL(TMPWR);
- CSYNC();
-
- /* the TSCALE prescaler counter. */
- bfin_write_TSCALE(TIME_SCALE - 1);
- bfin_write_TPERIOD(0);
- bfin_write_TCOUNT(0);
-
- CSYNC();
-}
-
-#ifdef CONFIG_CORE_TIMER_IRQ_L1
-__attribute__((l1_text))
-#endif
-
-irqreturn_t bfin_coretmr_interrupt(int irq, void *dev_id)
-{
- int cpu = smp_processor_id();
- struct clock_event_device *evt = &per_cpu(coretmr_events, cpu);
-
- smp_mb();
- evt->event_handler(evt);
-
- touch_nmi_watchdog();
-
- return IRQ_HANDLED;
-}
-
-static struct irqaction coretmr_irq = {
- .name = "Blackfin CoreTimer",
- .flags = IRQF_TIMER | IRQF_IRQPOLL | IRQF_PERCPU,
- .handler = bfin_coretmr_interrupt,
-};
-
-void bfin_coretmr_clockevent_init(void)
-{
- unsigned long clock_tick;
- unsigned int cpu = smp_processor_id();
- struct clock_event_device *evt = &per_cpu(coretmr_events, cpu);
-
-#ifdef CONFIG_SMP
- evt->broadcast = smp_timer_broadcast;
-#endif
-
- evt->name = "bfin_core_timer";
- evt->rating = 350;
- evt->irq = -1;
- evt->shift = 32;
- evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
- evt->set_next_event = bfin_coretmr_set_next_event;
- evt->set_state_shutdown = bfin_coretmr_shutdown;
- evt->set_state_periodic = bfin_coretmr_set_periodic;
- evt->set_state_oneshot = bfin_coretmr_set_oneshot;
-
- clock_tick = get_cclk() / TIME_SCALE;
- evt->mult = div_sc(clock_tick, NSEC_PER_SEC, evt->shift);
- evt->max_delta_ns = clockevent_delta2ns(-1, evt);
- evt->max_delta_ticks = (unsigned long)-1;
- evt->min_delta_ns = clockevent_delta2ns(100, evt);
- evt->min_delta_ticks = 100;
-
- evt->cpumask = cpumask_of(cpu);
-
- clockevents_register_device(evt);
-}
-#endif /* CONFIG_TICKSOURCE_CORETMR */
-
-
-void read_persistent_clock(struct timespec *ts)
-{
- time_t secs_since_1970 = (365 * 37 + 9) * 24 * 60 * 60; /* 1 Jan 2007 */
- ts->tv_sec = secs_since_1970;
- ts->tv_nsec = 0;
-}
-
-void __init time_init(void)
-{
-
-#ifdef CONFIG_RTC_DRV_BFIN
- /* [#2663] hack to filter junk RTC values that would cause
- * userspace to have to deal with time values greater than
- * 2^31 seconds (which uClibc cannot cope with yet)
- */
- if ((bfin_read_RTC_STAT() & 0xC0000000) == 0xC0000000) {
- printk(KERN_NOTICE "bfin-rtc: invalid date; resetting\n");
- bfin_write_RTC_STAT(0);
- }
-#endif
-
- bfin_cs_cycles_init();
- bfin_cs_gptimer0_init();
-
-#if defined(CONFIG_TICKSOURCE_CORETMR)
- bfin_coretmr_init();
- setup_irq(IRQ_CORETMR, &coretmr_irq);
- bfin_coretmr_clockevent_init();
-#endif
-
-#if defined(CONFIG_TICKSOURCE_GPTMR0)
- bfin_gptmr0_init();
- setup_irq(IRQ_TIMER0, &gptmr0_irq);
- gptmr0_irq.dev_id = &clockevent_gptmr0;
- bfin_gptmr0_clockevent_init(&clockevent_gptmr0);
-#endif
-
-#if !defined(CONFIG_TICKSOURCE_CORETMR) && !defined(CONFIG_TICKSOURCE_GPTMR0)
-# error at least one clock event device is required
-#endif
-}
+++ /dev/null
-/*
- * arch/blackfin/kernel/time.c
- *
- * This file contains the Blackfin-specific time handling details.
- * Most of the stuff is located in the machine specific files.
- *
- * Copyright 2004-2008 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-#include <linux/profile.h>
-#include <linux/interrupt.h>
-#include <linux/time.h>
-#include <linux/irq.h>
-#include <linux/delay.h>
-#include <linux/sched.h>
-
-#include <asm/blackfin.h>
-#include <asm/time.h>
-#include <asm/gptimers.h>
-
-/* This is an NTP setting */
-#define TICK_SIZE (tick_nsec / 1000)
-
-static struct irqaction bfin_timer_irq = {
- .name = "Blackfin Timer Tick",
-};
-
-#if defined(CONFIG_IPIPE)
-void __init setup_system_timer0(void)
-{
- /* Power down the core timer, just to play safe. */
- bfin_write_TCNTL(0);
-
- disable_gptimers(TIMER0bit);
- set_gptimer_status(0, TIMER_STATUS_TRUN0);
- while (get_gptimer_status(0) & TIMER_STATUS_TRUN0)
- udelay(10);
-
- set_gptimer_config(0, 0x59); /* IRQ enable, periodic, PWM_OUT, SCLKed, OUT PAD disabled */
- set_gptimer_period(TIMER0_id, get_sclk() / HZ);
- set_gptimer_pwidth(TIMER0_id, 1);
- SSYNC();
- enable_gptimers(TIMER0bit);
-}
-#else
-void __init setup_core_timer(void)
-{
- u32 tcount;
-
- /* power up the timer, but don't enable it just yet */
- bfin_write_TCNTL(TMPWR);
- CSYNC();
-
- /* the TSCALE prescaler counter */
- bfin_write_TSCALE(TIME_SCALE - 1);
-
- tcount = ((get_cclk() / (HZ * TIME_SCALE)) - 1);
- bfin_write_TPERIOD(tcount);
- bfin_write_TCOUNT(tcount);
-
- /* now enable the timer */
- CSYNC();
-
- bfin_write_TCNTL(TAUTORLD | TMREN | TMPWR);
-}
-#endif
-
-static void __init
-time_sched_init(irqreturn_t(*timer_routine) (int, void *))
-{
-#if defined(CONFIG_IPIPE)
- setup_system_timer0();
- bfin_timer_irq.handler = timer_routine;
- setup_irq(IRQ_TIMER0, &bfin_timer_irq);
-#else
- setup_core_timer();
- bfin_timer_irq.handler = timer_routine;
- setup_irq(IRQ_CORETMR, &bfin_timer_irq);
-#endif
-}
-
-#ifdef CONFIG_ARCH_USES_GETTIMEOFFSET
-/*
- * Should return useconds since last timer tick
- */
-static u32 blackfin_gettimeoffset(void)
-{
- unsigned long offset;
- unsigned long clocks_per_jiffy;
-
-#if defined(CONFIG_IPIPE)
- clocks_per_jiffy = bfin_read_TIMER0_PERIOD();
- offset = bfin_read_TIMER0_COUNTER() / \
- (((clocks_per_jiffy + 1) * HZ) / USEC_PER_SEC);
-
- if ((get_gptimer_status(0) & TIMER_STATUS_TIMIL0) && offset < (100000 / HZ / 2))
- offset += (USEC_PER_SEC / HZ);
-#else
- clocks_per_jiffy = bfin_read_TPERIOD();
- offset = (clocks_per_jiffy - bfin_read_TCOUNT()) / \
- (((clocks_per_jiffy + 1) * HZ) / USEC_PER_SEC);
-
- /* Check if we just wrapped the counters and maybe missed a tick */
- if ((bfin_read_ILAT() & (1 << IRQ_CORETMR))
- && (offset < (100000 / HZ / 2)))
- offset += (USEC_PER_SEC / HZ);
-#endif
- return offset;
-}
-#endif
-
-/*
- * timer_interrupt() needs to keep up the real-time clock,
- * as well as call the "xtime_update()" routine every clocktick
- */
-#ifdef CONFIG_CORE_TIMER_IRQ_L1
-__attribute__((l1_text))
-#endif
-irqreturn_t timer_interrupt(int irq, void *dummy)
-{
- xtime_update(1);
-
-#ifdef CONFIG_IPIPE
- update_root_process_times(get_irq_regs());
-#else
- update_process_times(user_mode(get_irq_regs()));
-#endif
- profile_tick(CPU_PROFILING);
-
- return IRQ_HANDLED;
-}
-
-void read_persistent_clock(struct timespec *ts)
-{
- time_t secs_since_1970 = (365 * 37 + 9) * 24 * 60 * 60; /* 1 Jan 2007 */
- ts->tv_sec = secs_since_1970;
- ts->tv_nsec = 0;
-}
-
-void __init time_init(void)
-{
-#ifdef CONFIG_ARCH_USES_GETTIMEOFFSET
- arch_gettimeoffset = blackfin_gettimeoffset;
-#endif
-
-#ifdef CONFIG_RTC_DRV_BFIN
- /* [#2663] hack to filter junk RTC values that would cause
- * userspace to have to deal with time values greater than
- * 2^31 seconds (which uClibc cannot cope with yet)
- */
- if ((bfin_read_RTC_STAT() & 0xC0000000) == 0xC0000000) {
- printk(KERN_NOTICE "bfin-rtc: invalid date; resetting\n");
- bfin_write_RTC_STAT(0);
- }
-#endif
-
- time_sched_init(timer_interrupt);
-}
+++ /dev/null
-/* provide some functions which dump the trace buffer, in a nice way for people
- * to read it, and understand what is going on
- *
- * Copyright 2004-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <linux/kernel.h>
-#include <linux/hardirq.h>
-#include <linux/thread_info.h>
-#include <linux/mm.h>
-#include <linux/oom.h>
-#include <linux/sched/signal.h>
-#include <linux/sched/debug.h>
-#include <linux/sched/task.h>
-#include <linux/uaccess.h>
-#include <linux/module.h>
-#include <linux/kallsyms.h>
-#include <linux/err.h>
-#include <linux/fs.h>
-#include <linux/irq.h>
-#include <asm/dma.h>
-#include <asm/trace.h>
-#include <asm/fixed_code.h>
-#include <asm/traps.h>
-#include <asm/irq_handler.h>
-#include <asm/pda.h>
-
-void decode_address(char *buf, unsigned long address)
-{
- struct task_struct *p;
- struct mm_struct *mm;
- unsigned long offset;
- struct rb_node *n;
-
-#ifdef CONFIG_KALLSYMS
- unsigned long symsize;
- const char *symname;
- char *modname;
- char *delim = ":";
- char namebuf[128];
-#endif
-
- buf += sprintf(buf, "<0x%08lx> ", address);
-
-#ifdef CONFIG_KALLSYMS
- /* look up the address and see if we are in kernel space */
- symname = kallsyms_lookup(address, &symsize, &offset, &modname, namebuf);
-
- if (symname) {
- /* yeah! kernel space! */
- if (!modname)
- modname = delim = "";
- sprintf(buf, "{ %s%s%s%s + 0x%lx }",
- delim, modname, delim, symname,
- (unsigned long)offset);
- return;
- }
-#endif
-
- if (address >= FIXED_CODE_START && address < FIXED_CODE_END) {
- /* Problem in fixed code section? */
- strcat(buf, "/* Maybe fixed code section */");
- return;
-
- } else if (address < CONFIG_BOOT_LOAD) {
- /* Problem somewhere before the kernel start address */
- strcat(buf, "/* Maybe null pointer? */");
- return;
-
- } else if (address >= COREMMR_BASE) {
- strcat(buf, "/* core mmrs */");
- return;
-
- } else if (address >= SYSMMR_BASE) {
- strcat(buf, "/* system mmrs */");
- return;
-
- } else if (address >= L1_ROM_START && address < L1_ROM_START + L1_ROM_LENGTH) {
- strcat(buf, "/* on-chip L1 ROM */");
- return;
-
- } else if (address >= L1_SCRATCH_START && address < L1_SCRATCH_START + L1_SCRATCH_LENGTH) {
- strcat(buf, "/* on-chip scratchpad */");
- return;
-
- } else if (address >= physical_mem_end && address < ASYNC_BANK0_BASE) {
- strcat(buf, "/* unconnected memory */");
- return;
-
- } else if (address >= ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE && address < BOOT_ROM_START) {
- strcat(buf, "/* reserved memory */");
- return;
-
- } else if (address >= L1_DATA_A_START && address < L1_DATA_A_START + L1_DATA_A_LENGTH) {
- strcat(buf, "/* on-chip Data Bank A */");
- return;
-
- } else if (address >= L1_DATA_B_START && address < L1_DATA_B_START + L1_DATA_B_LENGTH) {
- strcat(buf, "/* on-chip Data Bank B */");
- return;
- }
-
- /*
- * Don't walk any of the vmas if we are oopsing, it has been known
- * to cause problems - corrupt vmas (kernel crashes) cause double faults
- */
- if (oops_in_progress) {
- strcat(buf, "/* kernel dynamic memory (maybe user-space) */");
- return;
- }
-
- /* looks like we're off in user-land, so let's walk all the
- * mappings of all our processes and see if we can't be a whee
- * bit more specific
- */
- read_lock(&tasklist_lock);
- for_each_process(p) {
- struct task_struct *t;
-
- t = find_lock_task_mm(p);
- if (!t)
- continue;
-
- mm = t->mm;
- if (!down_read_trylock(&mm->mmap_sem))
- goto __continue;
-
- for (n = rb_first(&mm->mm_rb); n; n = rb_next(n)) {
- struct vm_area_struct *vma;
-
- vma = rb_entry(n, struct vm_area_struct, vm_rb);
-
- if (address >= vma->vm_start && address < vma->vm_end) {
- char _tmpbuf[256];
- char *name = t->comm;
- struct file *file = vma->vm_file;
-
- if (file) {
- char *d_name = file_path(file, _tmpbuf,
- sizeof(_tmpbuf));
- if (!IS_ERR(d_name))
- name = d_name;
- }
-
- /* FLAT does not have its text aligned to the start of
- * the map while FDPIC ELF does ...
- */
-
- /* before we can check flat/fdpic, we need to
- * make sure current is valid
- */
- if ((unsigned long)current >= FIXED_CODE_START &&
- !((unsigned long)current & 0x3)) {
- if (current->mm &&
- (address > current->mm->start_code) &&
- (address < current->mm->end_code))
- offset = address - current->mm->start_code;
- else
- offset = (address - vma->vm_start) +
- (vma->vm_pgoff << PAGE_SHIFT);
-
- sprintf(buf, "[ %s + 0x%lx ]", name, offset);
- } else
- sprintf(buf, "[ %s vma:0x%lx-0x%lx]",
- name, vma->vm_start, vma->vm_end);
-
- up_read(&mm->mmap_sem);
- task_unlock(t);
-
- if (buf[0] == '\0')
- sprintf(buf, "[ %s ] dynamic memory", name);
-
- goto done;
- }
- }
-
- up_read(&mm->mmap_sem);
-__continue:
- task_unlock(t);
- }
-
- /*
- * we were unable to find this address anywhere,
- * or some MMs were skipped because they were in use.
- */
- sprintf(buf, "/* kernel dynamic memory */");
-
-done:
- read_unlock(&tasklist_lock);
-}
-
-#define EXPAND_LEN ((1 << CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN) * 256 - 1)
-
-/*
- * Similar to get_user, do some address checking, then dereference
- * Return true on success, false on bad address
- */
-bool get_mem16(unsigned short *val, unsigned short *address)
-{
- unsigned long addr = (unsigned long)address;
-
- /* Check for odd addresses */
- if (addr & 0x1)
- return false;
-
- switch (bfin_mem_access_type(addr, 2)) {
- case BFIN_MEM_ACCESS_CORE:
- case BFIN_MEM_ACCESS_CORE_ONLY:
- *val = *address;
- return true;
- case BFIN_MEM_ACCESS_DMA:
- dma_memcpy(val, address, 2);
- return true;
- case BFIN_MEM_ACCESS_ITEST:
- isram_memcpy(val, address, 2);
- return true;
- default: /* invalid access */
- return false;
- }
-}
-
-bool get_instruction(unsigned int *val, unsigned short *address)
-{
- unsigned long addr = (unsigned long)address;
- unsigned short opcode0, opcode1;
-
- /* Check for odd addresses */
- if (addr & 0x1)
- return false;
-
- /* MMR region will never have instructions */
- if (addr >= SYSMMR_BASE)
- return false;
-
- /* Scratchpad will never have instructions */
- if (addr >= L1_SCRATCH_START && addr < L1_SCRATCH_START + L1_SCRATCH_LENGTH)
- return false;
-
- /* Data banks will never have instructions */
- if (addr >= BOOT_ROM_START + BOOT_ROM_LENGTH && addr < L1_CODE_START)
- return false;
-
- if (!get_mem16(&opcode0, address))
- return false;
-
- /* was this a 32-bit instruction? If so, get the next 16 bits */
- if ((opcode0 & 0xc000) == 0xc000) {
- if (!get_mem16(&opcode1, address + 1))
- return false;
- *val = (opcode0 << 16) + opcode1;
- } else
- *val = opcode0;
-
- return true;
-}
-
-#if defined(CONFIG_DEBUG_BFIN_HWTRACE_ON)
-/*
- * decode the instruction if we are printing out the trace, as it
- * makes things easier to follow, without running it through objdump
- * Decode the change of flow, and the common load/store instructions
- * which are the main cause for faults, and discontinuities in the trace
- * buffer.
- */
-
-#define ProgCtrl_opcode 0x0000
-#define ProgCtrl_poprnd_bits 0
-#define ProgCtrl_poprnd_mask 0xf
-#define ProgCtrl_prgfunc_bits 4
-#define ProgCtrl_prgfunc_mask 0xf
-#define ProgCtrl_code_bits 8
-#define ProgCtrl_code_mask 0xff
-
-static void decode_ProgCtrl_0(unsigned int opcode)
-{
- int poprnd = ((opcode >> ProgCtrl_poprnd_bits) & ProgCtrl_poprnd_mask);
- int prgfunc = ((opcode >> ProgCtrl_prgfunc_bits) & ProgCtrl_prgfunc_mask);
-
- if (prgfunc == 0 && poprnd == 0)
- pr_cont("NOP");
- else if (prgfunc == 1 && poprnd == 0)
- pr_cont("RTS");
- else if (prgfunc == 1 && poprnd == 1)
- pr_cont("RTI");
- else if (prgfunc == 1 && poprnd == 2)
- pr_cont("RTX");
- else if (prgfunc == 1 && poprnd == 3)
- pr_cont("RTN");
- else if (prgfunc == 1 && poprnd == 4)
- pr_cont("RTE");
- else if (prgfunc == 2 && poprnd == 0)
- pr_cont("IDLE");
- else if (prgfunc == 2 && poprnd == 3)
- pr_cont("CSYNC");
- else if (prgfunc == 2 && poprnd == 4)
- pr_cont("SSYNC");
- else if (prgfunc == 2 && poprnd == 5)
- pr_cont("EMUEXCPT");
- else if (prgfunc == 3)
- pr_cont("CLI R%i", poprnd);
- else if (prgfunc == 4)
- pr_cont("STI R%i", poprnd);
- else if (prgfunc == 5)
- pr_cont("JUMP (P%i)", poprnd);
- else if (prgfunc == 6)
- pr_cont("CALL (P%i)", poprnd);
- else if (prgfunc == 7)
- pr_cont("CALL (PC + P%i)", poprnd);
- else if (prgfunc == 8)
- pr_cont("JUMP (PC + P%i", poprnd);
- else if (prgfunc == 9)
- pr_cont("RAISE %i", poprnd);
- else if (prgfunc == 10)
- pr_cont("EXCPT %i", poprnd);
- else
- pr_cont("0x%04x", opcode);
-
-}
-
-#define BRCC_opcode 0x1000
-#define BRCC_offset_bits 0
-#define BRCC_offset_mask 0x3ff
-#define BRCC_B_bits 10
-#define BRCC_B_mask 0x1
-#define BRCC_T_bits 11
-#define BRCC_T_mask 0x1
-#define BRCC_code_bits 12
-#define BRCC_code_mask 0xf
-
-static void decode_BRCC_0(unsigned int opcode)
-{
- int B = ((opcode >> BRCC_B_bits) & BRCC_B_mask);
- int T = ((opcode >> BRCC_T_bits) & BRCC_T_mask);
-
- pr_cont("IF %sCC JUMP pcrel %s", T ? "" : "!", B ? "(BP)" : "");
-}
-
-#define CALLa_opcode 0xe2000000
-#define CALLa_addr_bits 0
-#define CALLa_addr_mask 0xffffff
-#define CALLa_S_bits 24
-#define CALLa_S_mask 0x1
-#define CALLa_code_bits 25
-#define CALLa_code_mask 0x7f
-
-static void decode_CALLa_0(unsigned int opcode)
-{
- int S = ((opcode >> (CALLa_S_bits - 16)) & CALLa_S_mask);
-
- if (S)
- pr_cont("CALL pcrel");
- else
- pr_cont("JUMP.L");
-}
-
-#define LoopSetup_opcode 0xe0800000
-#define LoopSetup_eoffset_bits 0
-#define LoopSetup_eoffset_mask 0x3ff
-#define LoopSetup_dontcare_bits 10
-#define LoopSetup_dontcare_mask 0x3
-#define LoopSetup_reg_bits 12
-#define LoopSetup_reg_mask 0xf
-#define LoopSetup_soffset_bits 16
-#define LoopSetup_soffset_mask 0xf
-#define LoopSetup_c_bits 20
-#define LoopSetup_c_mask 0x1
-#define LoopSetup_rop_bits 21
-#define LoopSetup_rop_mask 0x3
-#define LoopSetup_code_bits 23
-#define LoopSetup_code_mask 0x1ff
-
-static void decode_LoopSetup_0(unsigned int opcode)
-{
- int c = ((opcode >> LoopSetup_c_bits) & LoopSetup_c_mask);
- int reg = ((opcode >> LoopSetup_reg_bits) & LoopSetup_reg_mask);
- int rop = ((opcode >> LoopSetup_rop_bits) & LoopSetup_rop_mask);
-
- pr_cont("LSETUP <> LC%i", c);
- if ((rop & 1) == 1)
- pr_cont("= P%i", reg);
- if ((rop & 2) == 2)
- pr_cont(" >> 0x1");
-}
-
-#define DspLDST_opcode 0x9c00
-#define DspLDST_reg_bits 0
-#define DspLDST_reg_mask 0x7
-#define DspLDST_i_bits 3
-#define DspLDST_i_mask 0x3
-#define DspLDST_m_bits 5
-#define DspLDST_m_mask 0x3
-#define DspLDST_aop_bits 7
-#define DspLDST_aop_mask 0x3
-#define DspLDST_W_bits 9
-#define DspLDST_W_mask 0x1
-#define DspLDST_code_bits 10
-#define DspLDST_code_mask 0x3f
-
-static void decode_dspLDST_0(unsigned int opcode)
-{
- int i = ((opcode >> DspLDST_i_bits) & DspLDST_i_mask);
- int m = ((opcode >> DspLDST_m_bits) & DspLDST_m_mask);
- int W = ((opcode >> DspLDST_W_bits) & DspLDST_W_mask);
- int aop = ((opcode >> DspLDST_aop_bits) & DspLDST_aop_mask);
- int reg = ((opcode >> DspLDST_reg_bits) & DspLDST_reg_mask);
-
- if (W == 0) {
- pr_cont("R%i", reg);
- switch (m) {
- case 0:
- pr_cont(" = ");
- break;
- case 1:
- pr_cont(".L = ");
- break;
- case 2:
- pr_cont(".W = ");
- break;
- }
- }
-
- pr_cont("[ I%i", i);
-
- switch (aop) {
- case 0:
- pr_cont("++ ]");
- break;
- case 1:
- pr_cont("-- ]");
- break;
- }
-
- if (W == 1) {
- pr_cont(" = R%i", reg);
- switch (m) {
- case 1:
- pr_cont(".L = ");
- break;
- case 2:
- pr_cont(".W = ");
- break;
- }
- }
-}
-
-#define LDST_opcode 0x9000
-#define LDST_reg_bits 0
-#define LDST_reg_mask 0x7
-#define LDST_ptr_bits 3
-#define LDST_ptr_mask 0x7
-#define LDST_Z_bits 6
-#define LDST_Z_mask 0x1
-#define LDST_aop_bits 7
-#define LDST_aop_mask 0x3
-#define LDST_W_bits 9
-#define LDST_W_mask 0x1
-#define LDST_sz_bits 10
-#define LDST_sz_mask 0x3
-#define LDST_code_bits 12
-#define LDST_code_mask 0xf
-
-static void decode_LDST_0(unsigned int opcode)
-{
- int Z = ((opcode >> LDST_Z_bits) & LDST_Z_mask);
- int W = ((opcode >> LDST_W_bits) & LDST_W_mask);
- int sz = ((opcode >> LDST_sz_bits) & LDST_sz_mask);
- int aop = ((opcode >> LDST_aop_bits) & LDST_aop_mask);
- int reg = ((opcode >> LDST_reg_bits) & LDST_reg_mask);
- int ptr = ((opcode >> LDST_ptr_bits) & LDST_ptr_mask);
-
- if (W == 0)
- pr_cont("%s%i = ", (sz == 0 && Z == 1) ? "P" : "R", reg);
-
- switch (sz) {
- case 1:
- pr_cont("W");
- break;
- case 2:
- pr_cont("B");
- break;
- }
-
- pr_cont("[P%i", ptr);
-
- switch (aop) {
- case 0:
- pr_cont("++");
- break;
- case 1:
- pr_cont("--");
- break;
- }
- pr_cont("]");
-
- if (W == 1)
- pr_cont(" = %s%i ", (sz == 0 && Z == 1) ? "P" : "R", reg);
-
- if (sz) {
- if (Z)
- pr_cont(" (X)");
- else
- pr_cont(" (Z)");
- }
-}
-
-#define LDSTii_opcode 0xa000
-#define LDSTii_reg_bit 0
-#define LDSTii_reg_mask 0x7
-#define LDSTii_ptr_bit 3
-#define LDSTii_ptr_mask 0x7
-#define LDSTii_offset_bit 6
-#define LDSTii_offset_mask 0xf
-#define LDSTii_op_bit 10
-#define LDSTii_op_mask 0x3
-#define LDSTii_W_bit 12
-#define LDSTii_W_mask 0x1
-#define LDSTii_code_bit 13
-#define LDSTii_code_mask 0x7
-
-static void decode_LDSTii_0(unsigned int opcode)
-{
- int reg = ((opcode >> LDSTii_reg_bit) & LDSTii_reg_mask);
- int ptr = ((opcode >> LDSTii_ptr_bit) & LDSTii_ptr_mask);
- int offset = ((opcode >> LDSTii_offset_bit) & LDSTii_offset_mask);
- int op = ((opcode >> LDSTii_op_bit) & LDSTii_op_mask);
- int W = ((opcode >> LDSTii_W_bit) & LDSTii_W_mask);
-
- if (W == 0) {
- pr_cont("%s%i = %s[P%i + %i]", op == 3 ? "R" : "P", reg,
- op == 1 || op == 2 ? "" : "W", ptr, offset);
- if (op == 2)
- pr_cont("(Z)");
- if (op == 3)
- pr_cont("(X)");
- } else {
- pr_cont("%s[P%i + %i] = %s%i", op == 0 ? "" : "W", ptr,
- offset, op == 3 ? "P" : "R", reg);
- }
-}
-
-#define LDSTidxI_opcode 0xe4000000
-#define LDSTidxI_offset_bits 0
-#define LDSTidxI_offset_mask 0xffff
-#define LDSTidxI_reg_bits 16
-#define LDSTidxI_reg_mask 0x7
-#define LDSTidxI_ptr_bits 19
-#define LDSTidxI_ptr_mask 0x7
-#define LDSTidxI_sz_bits 22
-#define LDSTidxI_sz_mask 0x3
-#define LDSTidxI_Z_bits 24
-#define LDSTidxI_Z_mask 0x1
-#define LDSTidxI_W_bits 25
-#define LDSTidxI_W_mask 0x1
-#define LDSTidxI_code_bits 26
-#define LDSTidxI_code_mask 0x3f
-
-static void decode_LDSTidxI_0(unsigned int opcode)
-{
- int Z = ((opcode >> LDSTidxI_Z_bits) & LDSTidxI_Z_mask);
- int W = ((opcode >> LDSTidxI_W_bits) & LDSTidxI_W_mask);
- int sz = ((opcode >> LDSTidxI_sz_bits) & LDSTidxI_sz_mask);
- int reg = ((opcode >> LDSTidxI_reg_bits) & LDSTidxI_reg_mask);
- int ptr = ((opcode >> LDSTidxI_ptr_bits) & LDSTidxI_ptr_mask);
- int offset = ((opcode >> LDSTidxI_offset_bits) & LDSTidxI_offset_mask);
-
- if (W == 0)
- pr_cont("%s%i = ", sz == 0 && Z == 1 ? "P" : "R", reg);
-
- if (sz == 1)
- pr_cont("W");
- if (sz == 2)
- pr_cont("B");
-
- pr_cont("[P%i + %s0x%x]", ptr, offset & 0x20 ? "-" : "",
- (offset & 0x1f) << 2);
-
- if (W == 0 && sz != 0) {
- if (Z)
- pr_cont("(X)");
- else
- pr_cont("(Z)");
- }
-
- if (W == 1)
- pr_cont("= %s%i", (sz == 0 && Z == 1) ? "P" : "R", reg);
-
-}
-
-static void decode_opcode(unsigned int opcode)
-{
-#ifdef CONFIG_BUG
- if (opcode == BFIN_BUG_OPCODE)
- pr_cont("BUG");
- else
-#endif
- if ((opcode & 0xffffff00) == ProgCtrl_opcode)
- decode_ProgCtrl_0(opcode);
- else if ((opcode & 0xfffff000) == BRCC_opcode)
- decode_BRCC_0(opcode);
- else if ((opcode & 0xfffff000) == 0x2000)
- pr_cont("JUMP.S");
- else if ((opcode & 0xfe000000) == CALLa_opcode)
- decode_CALLa_0(opcode);
- else if ((opcode & 0xff8000C0) == LoopSetup_opcode)
- decode_LoopSetup_0(opcode);
- else if ((opcode & 0xfffffc00) == DspLDST_opcode)
- decode_dspLDST_0(opcode);
- else if ((opcode & 0xfffff000) == LDST_opcode)
- decode_LDST_0(opcode);
- else if ((opcode & 0xffffe000) == LDSTii_opcode)
- decode_LDSTii_0(opcode);
- else if ((opcode & 0xfc000000) == LDSTidxI_opcode)
- decode_LDSTidxI_0(opcode);
- else if (opcode & 0xffff0000)
- pr_cont("0x%08x", opcode);
- else
- pr_cont("0x%04x", opcode);
-}
-
-#define BIT_MULTI_INS 0x08000000
-static void decode_instruction(unsigned short *address)
-{
- unsigned int opcode;
-
- if (!get_instruction(&opcode, address))
- return;
-
- decode_opcode(opcode);
-
- /* If things are a 32-bit instruction, it has the possibility of being
- * a multi-issue instruction (a 32-bit, and 2 16 bit instrucitions)
- * This test collidates with the unlink instruction, so disallow that
- */
- if ((opcode & 0xc0000000) == 0xc0000000 &&
- (opcode & BIT_MULTI_INS) &&
- (opcode & 0xe8000000) != 0xe8000000) {
- pr_cont(" || ");
- if (!get_instruction(&opcode, address + 2))
- return;
- decode_opcode(opcode);
- pr_cont(" || ");
- if (!get_instruction(&opcode, address + 3))
- return;
- decode_opcode(opcode);
- }
-}
-#endif
-
-void dump_bfin_trace_buffer(void)
-{
-#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON
- int tflags, i = 0, fault = 0;
- char buf[150];
- unsigned short *addr;
- unsigned int cpu = raw_smp_processor_id();
-#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND
- int j, index;
-#endif
-
- trace_buffer_save(tflags);
-
- pr_notice("Hardware Trace:\n");
-
-#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND
- pr_notice("WARNING: Expanded trace turned on - can not trace exceptions\n");
-#endif
-
- if (likely(bfin_read_TBUFSTAT() & TBUFCNT)) {
- for (; bfin_read_TBUFSTAT() & TBUFCNT; i++) {
- addr = (unsigned short *)bfin_read_TBUF();
- decode_address(buf, (unsigned long)addr);
- pr_notice("%4i Target : %s\n", i, buf);
- /* Normally, the faulting instruction doesn't go into
- * the trace buffer, (since it doesn't commit), so
- * we print out the fault address here
- */
- if (!fault && addr == ((unsigned short *)evt_ivhw)) {
- addr = (unsigned short *)bfin_read_TBUF();
- decode_address(buf, (unsigned long)addr);
- pr_notice(" FAULT : %s ", buf);
- decode_instruction(addr);
- pr_cont("\n");
- fault = 1;
- continue;
- }
- if (!fault && addr == (unsigned short *)trap &&
- (cpu_pda[cpu].seqstat & SEQSTAT_EXCAUSE) > VEC_EXCPT15) {
- decode_address(buf, cpu_pda[cpu].icplb_fault_addr);
- pr_notice(" FAULT : %s ", buf);
- decode_instruction((unsigned short *)cpu_pda[cpu].icplb_fault_addr);
- pr_cont("\n");
- fault = 1;
- }
- addr = (unsigned short *)bfin_read_TBUF();
- decode_address(buf, (unsigned long)addr);
- pr_notice(" Source : %s ", buf);
- decode_instruction(addr);
- pr_cont("\n");
- }
- }
-
-#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND
- if (trace_buff_offset)
- index = trace_buff_offset / 4;
- else
- index = EXPAND_LEN;
-
- j = (1 << CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN) * 128;
- while (j) {
- decode_address(buf, software_trace_buff[index]);
- pr_notice("%4i Target : %s\n", i, buf);
- index -= 1;
- if (index < 0)
- index = EXPAND_LEN;
- decode_address(buf, software_trace_buff[index]);
- pr_notice(" Source : %s ", buf);
- decode_instruction((unsigned short *)software_trace_buff[index]);
- pr_cont("\n");
- index -= 1;
- if (index < 0)
- index = EXPAND_LEN;
- j--;
- i++;
- }
-#endif
-
- trace_buffer_restore(tflags);
-#endif
-}
-EXPORT_SYMBOL(dump_bfin_trace_buffer);
-
-void dump_bfin_process(struct pt_regs *fp)
-{
- /* We should be able to look at fp->ipend, but we don't push it on the
- * stack all the time, so do this until we fix that */
- unsigned int context = bfin_read_IPEND();
-
- if (oops_in_progress)
- pr_emerg("Kernel OOPS in progress\n");
-
- if (context & 0x0020 && (fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR)
- pr_notice("HW Error context\n");
- else if (context & 0x0020)
- pr_notice("Deferred Exception context\n");
- else if (context & 0x3FC0)
- pr_notice("Interrupt context\n");
- else if (context & 0x4000)
- pr_notice("Deferred Interrupt context\n");
- else if (context & 0x8000)
- pr_notice("Kernel process context\n");
-
- /* Because we are crashing, and pointers could be bad, we check things
- * pretty closely before we use them
- */
- if ((unsigned long)current >= FIXED_CODE_START &&
- !((unsigned long)current & 0x3) && current->pid) {
- pr_notice("CURRENT PROCESS:\n");
- if (current->comm >= (char *)FIXED_CODE_START)
- pr_notice("COMM=%s PID=%d",
- current->comm, current->pid);
- else
- pr_notice("COMM= invalid");
-
- pr_cont(" CPU=%d\n", current_thread_info()->cpu);
- if (!((unsigned long)current->mm & 0x3) &&
- (unsigned long)current->mm >= FIXED_CODE_START) {
- pr_notice("TEXT = 0x%p-0x%p DATA = 0x%p-0x%p\n",
- (void *)current->mm->start_code,
- (void *)current->mm->end_code,
- (void *)current->mm->start_data,
- (void *)current->mm->end_data);
- pr_notice(" BSS = 0x%p-0x%p USER-STACK = 0x%p\n\n",
- (void *)current->mm->end_data,
- (void *)current->mm->brk,
- (void *)current->mm->start_stack);
- } else
- pr_notice("invalid mm\n");
- } else
- pr_notice("No Valid process in current context\n");
-}
-
-void dump_bfin_mem(struct pt_regs *fp)
-{
- unsigned short *addr, *erraddr, val = 0, err = 0;
- char sti = 0, buf[6];
-
- erraddr = (void *)fp->pc;
-
- pr_notice("return address: [0x%p]; contents of:", erraddr);
-
- for (addr = (unsigned short *)((unsigned long)erraddr & ~0xF) - 0x10;
- addr < (unsigned short *)((unsigned long)erraddr & ~0xF) + 0x10;
- addr++) {
- if (!((unsigned long)addr & 0xF))
- pr_notice("0x%p: ", addr);
-
- if (!get_mem16(&val, addr)) {
- val = 0;
- sprintf(buf, "????");
- } else
- sprintf(buf, "%04x", val);
-
- if (addr == erraddr) {
- pr_cont("[%s]", buf);
- err = val;
- } else
- pr_cont(" %s ", buf);
-
- /* Do any previous instructions turn on interrupts? */
- if (addr <= erraddr && /* in the past */
- ((val >= 0x0040 && val <= 0x0047) || /* STI instruction */
- val == 0x017b)) /* [SP++] = RETI */
- sti = 1;
- }
-
- pr_cont("\n");
-
- /* Hardware error interrupts can be deferred */
- if (unlikely(sti && (fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR &&
- oops_in_progress)){
- pr_notice("Looks like this was a deferred error - sorry\n");
-#ifndef CONFIG_DEBUG_HWERR
- pr_notice("The remaining message may be meaningless\n");
- pr_notice("You should enable CONFIG_DEBUG_HWERR to get a better idea where it came from\n");
-#else
- /* If we are handling only one peripheral interrupt
- * and current mm and pid are valid, and the last error
- * was in that user space process's text area
- * print it out - because that is where the problem exists
- */
- if ((!(((fp)->ipend & ~0x30) & (((fp)->ipend & ~0x30) - 1))) &&
- (current->pid && current->mm)) {
- /* And the last RETI points to the current userspace context */
- if ((fp + 1)->pc >= current->mm->start_code &&
- (fp + 1)->pc <= current->mm->end_code) {
- pr_notice("It might be better to look around here :\n");
- pr_notice("-------------------------------------------\n");
- show_regs(fp + 1);
- pr_notice("-------------------------------------------\n");
- }
- }
-#endif
- }
-}
-
-void show_regs(struct pt_regs *fp)
-{
- char buf[150];
- struct irqaction *action;
- unsigned int i;
- unsigned long flags = 0;
- unsigned int cpu = raw_smp_processor_id();
- unsigned char in_atomic = (bfin_read_IPEND() & 0x10) || in_atomic();
-
- pr_notice("\n");
- show_regs_print_info(KERN_NOTICE);
-
- if (CPUID != bfin_cpuid())
- pr_notice("Compiled for cpu family 0x%04x (Rev %d), "
- "but running on:0x%04x (Rev %d)\n",
- CPUID, bfin_compiled_revid(), bfin_cpuid(), bfin_revid());
-
- pr_notice("ADSP-%s-0.%d",
- CPU, bfin_compiled_revid());
-
- if (bfin_compiled_revid() != bfin_revid())
- pr_cont("(Detected 0.%d)", bfin_revid());
-
- pr_cont(" %lu(MHz CCLK) %lu(MHz SCLK) (%s)\n",
- get_cclk()/1000000, get_sclk()/1000000,
-#ifdef CONFIG_MPU
- "mpu on"
-#else
- "mpu off"
-#endif
- );
-
- pr_notice("%s", linux_banner);
-
- pr_notice("\nSEQUENCER STATUS:\t\t%s\n", print_tainted());
- pr_notice(" SEQSTAT: %08lx IPEND: %04lx IMASK: %04lx SYSCFG: %04lx\n",
- (long)fp->seqstat, fp->ipend, cpu_pda[raw_smp_processor_id()].ex_imask, fp->syscfg);
- if (fp->ipend & EVT_IRPTEN)
- pr_notice(" Global Interrupts Disabled (IPEND[4])\n");
- if (!(cpu_pda[raw_smp_processor_id()].ex_imask & (EVT_IVG13 | EVT_IVG12 | EVT_IVG11 |
- EVT_IVG10 | EVT_IVG9 | EVT_IVG8 | EVT_IVG7 | EVT_IVTMR)))
- pr_notice(" Peripheral interrupts masked off\n");
- if (!(cpu_pda[raw_smp_processor_id()].ex_imask & (EVT_IVG15 | EVT_IVG14)))
- pr_notice(" Kernel interrupts masked off\n");
- if ((fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR) {
- pr_notice(" HWERRCAUSE: 0x%lx\n",
- (fp->seqstat & SEQSTAT_HWERRCAUSE) >> 14);
-#ifdef EBIU_ERRMST
- /* If the error was from the EBIU, print it out */
- if (bfin_read_EBIU_ERRMST() & CORE_ERROR) {
- pr_notice(" EBIU Error Reason : 0x%04x\n",
- bfin_read_EBIU_ERRMST());
- pr_notice(" EBIU Error Address : 0x%08x\n",
- bfin_read_EBIU_ERRADD());
- }
-#endif
- }
- pr_notice(" EXCAUSE : 0x%lx\n",
- fp->seqstat & SEQSTAT_EXCAUSE);
- for (i = 2; i <= 15 ; i++) {
- if (fp->ipend & (1 << i)) {
- if (i != 4) {
- decode_address(buf, bfin_read32(EVT0 + 4*i));
- pr_notice(" physical IVG%i asserted : %s\n", i, buf);
- } else
- pr_notice(" interrupts disabled\n");
- }
- }
-
- /* if no interrupts are going off, don't print this out */
- if (fp->ipend & ~0x3F) {
- for (i = 0; i < (NR_IRQS - 1); i++) {
- struct irq_desc *desc = irq_to_desc(i);
- if (!in_atomic)
- raw_spin_lock_irqsave(&desc->lock, flags);
-
- action = desc->action;
- if (!action)
- goto unlock;
-
- decode_address(buf, (unsigned int)action->handler);
- pr_notice(" logical irq %3d mapped : %s", i, buf);
- for (action = action->next; action; action = action->next) {
- decode_address(buf, (unsigned int)action->handler);
- pr_cont(", %s", buf);
- }
- pr_cont("\n");
-unlock:
- if (!in_atomic)
- raw_spin_unlock_irqrestore(&desc->lock, flags);
- }
- }
-
- decode_address(buf, fp->rete);
- pr_notice(" RETE: %s\n", buf);
- decode_address(buf, fp->retn);
- pr_notice(" RETN: %s\n", buf);
- decode_address(buf, fp->retx);
- pr_notice(" RETX: %s\n", buf);
- decode_address(buf, fp->rets);
- pr_notice(" RETS: %s\n", buf);
- decode_address(buf, fp->pc);
- pr_notice(" PC : %s\n", buf);
-
- if (((long)fp->seqstat & SEQSTAT_EXCAUSE) &&
- (((long)fp->seqstat & SEQSTAT_EXCAUSE) != VEC_HWERR)) {
- decode_address(buf, cpu_pda[cpu].dcplb_fault_addr);
- pr_notice("DCPLB_FAULT_ADDR: %s\n", buf);
- decode_address(buf, cpu_pda[cpu].icplb_fault_addr);
- pr_notice("ICPLB_FAULT_ADDR: %s\n", buf);
- }
-
- pr_notice("PROCESSOR STATE:\n");
- pr_notice(" R0 : %08lx R1 : %08lx R2 : %08lx R3 : %08lx\n",
- fp->r0, fp->r1, fp->r2, fp->r3);
- pr_notice(" R4 : %08lx R5 : %08lx R6 : %08lx R7 : %08lx\n",
- fp->r4, fp->r5, fp->r6, fp->r7);
- pr_notice(" P0 : %08lx P1 : %08lx P2 : %08lx P3 : %08lx\n",
- fp->p0, fp->p1, fp->p2, fp->p3);
- pr_notice(" P4 : %08lx P5 : %08lx FP : %08lx SP : %08lx\n",
- fp->p4, fp->p5, fp->fp, (long)fp);
- pr_notice(" LB0: %08lx LT0: %08lx LC0: %08lx\n",
- fp->lb0, fp->lt0, fp->lc0);
- pr_notice(" LB1: %08lx LT1: %08lx LC1: %08lx\n",
- fp->lb1, fp->lt1, fp->lc1);
- pr_notice(" B0 : %08lx L0 : %08lx M0 : %08lx I0 : %08lx\n",
- fp->b0, fp->l0, fp->m0, fp->i0);
- pr_notice(" B1 : %08lx L1 : %08lx M1 : %08lx I1 : %08lx\n",
- fp->b1, fp->l1, fp->m1, fp->i1);
- pr_notice(" B2 : %08lx L2 : %08lx M2 : %08lx I2 : %08lx\n",
- fp->b2, fp->l2, fp->m2, fp->i2);
- pr_notice(" B3 : %08lx L3 : %08lx M3 : %08lx I3 : %08lx\n",
- fp->b3, fp->l3, fp->m3, fp->i3);
- pr_notice("A0.w: %08lx A0.x: %08lx A1.w: %08lx A1.x: %08lx\n",
- fp->a0w, fp->a0x, fp->a1w, fp->a1x);
-
- pr_notice("USP : %08lx ASTAT: %08lx\n",
- rdusp(), fp->astat);
-
- pr_notice("\n");
-}
+++ /dev/null
-/*
- * Main exception handling logic.
- *
- * Copyright 2004-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <linux/bug.h>
-#include <linux/uaccess.h>
-#include <linux/module.h>
-#include <linux/sched/signal.h>
-#include <linux/sched/debug.h>
-#include <asm/traps.h>
-#include <asm/cplb.h>
-#include <asm/blackfin.h>
-#include <asm/irq_handler.h>
-#include <linux/irq.h>
-#include <asm/trace.h>
-#include <asm/fixed_code.h>
-#include <asm/pseudo_instructions.h>
-#include <asm/pda.h>
-#include <asm/asm-offsets.h>
-
-#ifdef CONFIG_KGDB
-# include <linux/kgdb.h>
-
-# define CHK_DEBUGGER_TRAP() \
- do { \
- kgdb_handle_exception(trapnr, sig, info.si_code, fp); \
- } while (0)
-# define CHK_DEBUGGER_TRAP_MAYBE() \
- do { \
- if (kgdb_connected) \
- CHK_DEBUGGER_TRAP(); \
- } while (0)
-#else
-# define CHK_DEBUGGER_TRAP() do { } while (0)
-# define CHK_DEBUGGER_TRAP_MAYBE() do { } while (0)
-#endif
-
-
-#ifdef CONFIG_DEBUG_VERBOSE
-#define verbose_printk(fmt, arg...) \
- printk(fmt, ##arg)
-#else
-#define verbose_printk(fmt, arg...) \
- ({ if (0) printk(fmt, ##arg); 0; })
-#endif
-
-#if defined(CONFIG_DEBUG_MMRS) || defined(CONFIG_DEBUG_MMRS_MODULE)
-u32 last_seqstat;
-#ifdef CONFIG_DEBUG_MMRS_MODULE
-EXPORT_SYMBOL(last_seqstat);
-#endif
-#endif
-
-/* Initiate the event table handler */
-void __init trap_init(void)
-{
- CSYNC();
- bfin_write_EVT3(trap);
- CSYNC();
-}
-
-static int kernel_mode_regs(struct pt_regs *regs)
-{
- return regs->ipend & 0xffc0;
-}
-
-asmlinkage notrace void trap_c(struct pt_regs *fp)
-{
-#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON
- int j;
-#endif
-#ifdef CONFIG_BFIN_PSEUDODBG_INSNS
- int opcode;
-#endif
- unsigned int cpu = raw_smp_processor_id();
- const char *strerror = NULL;
- int sig = 0;
- siginfo_t info;
- unsigned long trapnr = fp->seqstat & SEQSTAT_EXCAUSE;
-
- trace_buffer_save(j);
-#if defined(CONFIG_DEBUG_MMRS) || defined(CONFIG_DEBUG_MMRS_MODULE)
- last_seqstat = (u32)fp->seqstat;
-#endif
-
- /* Important - be very careful dereferncing pointers - will lead to
- * double faults if the stack has become corrupt
- */
-
- /* trap_c() will be called for exceptions. During exceptions
- * processing, the pc value should be set with retx value.
- * With this change we can cleanup some code in signal.c- TODO
- */
- fp->orig_pc = fp->retx;
- /* printk("exception: 0x%x, ipend=%x, reti=%x, retx=%x\n",
- trapnr, fp->ipend, fp->pc, fp->retx); */
-
- /* send the appropriate signal to the user program */
- switch (trapnr) {
-
- /* This table works in conjunction with the one in ./mach-common/entry.S
- * Some exceptions are handled there (in assembly, in exception space)
- * Some are handled here, (in C, in interrupt space)
- * Some, like CPLB, are handled in both, where the normal path is
- * handled in assembly/exception space, and the error path is handled
- * here
- */
-
- /* 0x00 - Linux Syscall, getting here is an error */
- /* 0x01 - userspace gdb breakpoint, handled here */
- case VEC_EXCPT01:
- info.si_code = TRAP_ILLTRAP;
- sig = SIGTRAP;
- CHK_DEBUGGER_TRAP_MAYBE();
- /* Check if this is a breakpoint in kernel space */
- if (kernel_mode_regs(fp))
- goto traps_done;
- else
- break;
- /* 0x03 - User Defined, userspace stack overflow */
- case VEC_EXCPT03:
- info.si_code = SEGV_STACKFLOW;
- sig = SIGSEGV;
- strerror = KERN_NOTICE EXC_0x03(KERN_NOTICE);
- CHK_DEBUGGER_TRAP_MAYBE();
- break;
- /* 0x02 - KGDB initial connection and break signal trap */
- case VEC_EXCPT02:
-#ifdef CONFIG_KGDB
- info.si_code = TRAP_ILLTRAP;
- sig = SIGTRAP;
- CHK_DEBUGGER_TRAP();
- goto traps_done;
-#endif
- /* 0x04 - User Defined */
- /* 0x05 - User Defined */
- /* 0x06 - User Defined */
- /* 0x07 - User Defined */
- /* 0x08 - User Defined */
- /* 0x09 - User Defined */
- /* 0x0A - User Defined */
- /* 0x0B - User Defined */
- /* 0x0C - User Defined */
- /* 0x0D - User Defined */
- /* 0x0E - User Defined */
- /* 0x0F - User Defined */
- /* If we got here, it is most likely that someone was trying to use a
- * custom exception handler, and it is not actually installed properly
- */
- case VEC_EXCPT04 ... VEC_EXCPT15:
- info.si_code = ILL_ILLPARAOP;
- sig = SIGILL;
- strerror = KERN_NOTICE EXC_0x04(KERN_NOTICE);
- CHK_DEBUGGER_TRAP_MAYBE();
- break;
- /* 0x10 HW Single step, handled here */
- case VEC_STEP:
- info.si_code = TRAP_STEP;
- sig = SIGTRAP;
- CHK_DEBUGGER_TRAP_MAYBE();
- /* Check if this is a single step in kernel space */
- if (kernel_mode_regs(fp))
- goto traps_done;
- else
- break;
- /* 0x11 - Trace Buffer Full, handled here */
- case VEC_OVFLOW:
- info.si_code = TRAP_TRACEFLOW;
- sig = SIGTRAP;
- strerror = KERN_NOTICE EXC_0x11(KERN_NOTICE);
- CHK_DEBUGGER_TRAP_MAYBE();
- break;
- /* 0x12 - Reserved, Caught by default */
- /* 0x13 - Reserved, Caught by default */
- /* 0x14 - Reserved, Caught by default */
- /* 0x15 - Reserved, Caught by default */
- /* 0x16 - Reserved, Caught by default */
- /* 0x17 - Reserved, Caught by default */
- /* 0x18 - Reserved, Caught by default */
- /* 0x19 - Reserved, Caught by default */
- /* 0x1A - Reserved, Caught by default */
- /* 0x1B - Reserved, Caught by default */
- /* 0x1C - Reserved, Caught by default */
- /* 0x1D - Reserved, Caught by default */
- /* 0x1E - Reserved, Caught by default */
- /* 0x1F - Reserved, Caught by default */
- /* 0x20 - Reserved, Caught by default */
- /* 0x21 - Undefined Instruction, handled here */
- case VEC_UNDEF_I:
-#ifdef CONFIG_BUG
- if (kernel_mode_regs(fp)) {
- switch (report_bug(fp->pc, fp)) {
- case BUG_TRAP_TYPE_NONE:
- break;
- case BUG_TRAP_TYPE_WARN:
- dump_bfin_trace_buffer();
- fp->pc += 2;
- goto traps_done;
- case BUG_TRAP_TYPE_BUG:
- /* call to panic() will dump trace, and it is
- * off at this point, so it won't be clobbered
- */
- panic("BUG()");
- }
- }
-#endif
-#ifdef CONFIG_BFIN_PSEUDODBG_INSNS
- /*
- * Support for the fake instructions, if the instruction fails,
- * then just execute a illegal opcode failure (like normal).
- * Don't support these instructions inside the kernel
- */
- if (!kernel_mode_regs(fp) && get_instruction(&opcode, (unsigned short *)fp->pc)) {
- if (execute_pseudodbg_assert(fp, opcode))
- goto traps_done;
- if (execute_pseudodbg(fp, opcode))
- goto traps_done;
- }
-#endif
- info.si_code = ILL_ILLOPC;
- sig = SIGILL;
- strerror = KERN_NOTICE EXC_0x21(KERN_NOTICE);
- CHK_DEBUGGER_TRAP_MAYBE();
- break;
- /* 0x22 - Illegal Instruction Combination, handled here */
- case VEC_ILGAL_I:
- info.si_code = ILL_ILLPARAOP;
- sig = SIGILL;
- strerror = KERN_NOTICE EXC_0x22(KERN_NOTICE);
- CHK_DEBUGGER_TRAP_MAYBE();
- break;
- /* 0x23 - Data CPLB protection violation, handled here */
- case VEC_CPLB_VL:
- info.si_code = ILL_CPLB_VI;
- sig = SIGSEGV;
- strerror = KERN_NOTICE EXC_0x23(KERN_NOTICE);
- CHK_DEBUGGER_TRAP_MAYBE();
- break;
- /* 0x24 - Data access misaligned, handled here */
- case VEC_MISALI_D:
- info.si_code = BUS_ADRALN;
- sig = SIGBUS;
- strerror = KERN_NOTICE EXC_0x24(KERN_NOTICE);
- CHK_DEBUGGER_TRAP_MAYBE();
- break;
- /* 0x25 - Unrecoverable Event, handled here */
- case VEC_UNCOV:
- info.si_code = ILL_ILLEXCPT;
- sig = SIGILL;
- strerror = KERN_NOTICE EXC_0x25(KERN_NOTICE);
- CHK_DEBUGGER_TRAP_MAYBE();
- break;
- /* 0x26 - Data CPLB Miss, normal case is handled in _cplb_hdr,
- error case is handled here */
- case VEC_CPLB_M:
- info.si_code = BUS_ADRALN;
- sig = SIGBUS;
- strerror = KERN_NOTICE EXC_0x26(KERN_NOTICE);
- break;
- /* 0x27 - Data CPLB Multiple Hits - Linux Trap Zero, handled here */
- case VEC_CPLB_MHIT:
- info.si_code = ILL_CPLB_MULHIT;
- sig = SIGSEGV;
-#ifdef CONFIG_DEBUG_HUNT_FOR_ZERO
- if (cpu_pda[cpu].dcplb_fault_addr < FIXED_CODE_START)
- strerror = KERN_NOTICE "NULL pointer access\n";
- else
-#endif
- strerror = KERN_NOTICE EXC_0x27(KERN_NOTICE);
- CHK_DEBUGGER_TRAP_MAYBE();
- break;
- /* 0x28 - Emulation Watchpoint, handled here */
- case VEC_WATCH:
- info.si_code = TRAP_WATCHPT;
- sig = SIGTRAP;
- pr_debug(EXC_0x28(KERN_DEBUG));
- CHK_DEBUGGER_TRAP_MAYBE();
- /* Check if this is a watchpoint in kernel space */
- if (kernel_mode_regs(fp))
- goto traps_done;
- else
- break;
-#ifdef CONFIG_BF535
- /* 0x29 - Instruction fetch access error (535 only) */
- case VEC_ISTRU_VL: /* ADSP-BF535 only (MH) */
- info.si_code = BUS_OPFETCH;
- sig = SIGBUS;
- strerror = KERN_NOTICE "BF535: VEC_ISTRU_VL\n";
- CHK_DEBUGGER_TRAP_MAYBE();
- break;
-#else
- /* 0x29 - Reserved, Caught by default */
-#endif
- /* 0x2A - Instruction fetch misaligned, handled here */
- case VEC_MISALI_I:
- info.si_code = BUS_ADRALN;
- sig = SIGBUS;
- strerror = KERN_NOTICE EXC_0x2A(KERN_NOTICE);
- CHK_DEBUGGER_TRAP_MAYBE();
- break;
- /* 0x2B - Instruction CPLB protection violation, handled here */
- case VEC_CPLB_I_VL:
- info.si_code = ILL_CPLB_VI;
- sig = SIGBUS;
- strerror = KERN_NOTICE EXC_0x2B(KERN_NOTICE);
- CHK_DEBUGGER_TRAP_MAYBE();
- break;
- /* 0x2C - Instruction CPLB miss, handled in _cplb_hdr */
- case VEC_CPLB_I_M:
- info.si_code = ILL_CPLB_MISS;
- sig = SIGBUS;
- strerror = KERN_NOTICE EXC_0x2C(KERN_NOTICE);
- break;
- /* 0x2D - Instruction CPLB Multiple Hits, handled here */
- case VEC_CPLB_I_MHIT:
- info.si_code = ILL_CPLB_MULHIT;
- sig = SIGSEGV;
-#ifdef CONFIG_DEBUG_HUNT_FOR_ZERO
- if (cpu_pda[cpu].icplb_fault_addr < FIXED_CODE_START)
- strerror = KERN_NOTICE "Jump to NULL address\n";
- else
-#endif
- strerror = KERN_NOTICE EXC_0x2D(KERN_NOTICE);
- CHK_DEBUGGER_TRAP_MAYBE();
- break;
- /* 0x2E - Illegal use of Supervisor Resource, handled here */
- case VEC_ILL_RES:
- info.si_code = ILL_PRVOPC;
- sig = SIGILL;
- strerror = KERN_NOTICE EXC_0x2E(KERN_NOTICE);
- CHK_DEBUGGER_TRAP_MAYBE();
- break;
- /* 0x2F - Reserved, Caught by default */
- /* 0x30 - Reserved, Caught by default */
- /* 0x31 - Reserved, Caught by default */
- /* 0x32 - Reserved, Caught by default */
- /* 0x33 - Reserved, Caught by default */
- /* 0x34 - Reserved, Caught by default */
- /* 0x35 - Reserved, Caught by default */
- /* 0x36 - Reserved, Caught by default */
- /* 0x37 - Reserved, Caught by default */
- /* 0x38 - Reserved, Caught by default */
- /* 0x39 - Reserved, Caught by default */
- /* 0x3A - Reserved, Caught by default */
- /* 0x3B - Reserved, Caught by default */
- /* 0x3C - Reserved, Caught by default */
- /* 0x3D - Reserved, Caught by default */
- /* 0x3E - Reserved, Caught by default */
- /* 0x3F - Reserved, Caught by default */
- case VEC_HWERR:
- info.si_code = BUS_ADRALN;
- sig = SIGBUS;
- switch (fp->seqstat & SEQSTAT_HWERRCAUSE) {
- /* System MMR Error */
- case (SEQSTAT_HWERRCAUSE_SYSTEM_MMR):
- info.si_code = BUS_ADRALN;
- sig = SIGBUS;
- strerror = KERN_NOTICE HWC_x2(KERN_NOTICE);
- break;
- /* External Memory Addressing Error */
- case (SEQSTAT_HWERRCAUSE_EXTERN_ADDR):
- if (ANOMALY_05000310) {
- static unsigned long anomaly_rets;
-
- if ((fp->pc >= (L1_CODE_START + L1_CODE_LENGTH - 512)) &&
- (fp->pc < (L1_CODE_START + L1_CODE_LENGTH))) {
- /*
- * A false hardware error will happen while fetching at
- * the L1 instruction SRAM boundary. Ignore it.
- */
- anomaly_rets = fp->rets;
- goto traps_done;
- } else if (fp->rets == anomaly_rets) {
- /*
- * While boundary code returns to a function, at the ret
- * point, a new false hardware error might occur too based
- * on tests. Ignore it too.
- */
- goto traps_done;
- } else if ((fp->rets >= (L1_CODE_START + L1_CODE_LENGTH - 512)) &&
- (fp->rets < (L1_CODE_START + L1_CODE_LENGTH))) {
- /*
- * If boundary code calls a function, at the entry point,
- * a new false hardware error maybe happen based on tests.
- * Ignore it too.
- */
- goto traps_done;
- } else
- anomaly_rets = 0;
- }
-
- info.si_code = BUS_ADRERR;
- sig = SIGBUS;
- strerror = KERN_NOTICE HWC_x3(KERN_NOTICE);
- break;
- /* Performance Monitor Overflow */
- case (SEQSTAT_HWERRCAUSE_PERF_FLOW):
- strerror = KERN_NOTICE HWC_x12(KERN_NOTICE);
- break;
- /* RAISE 5 instruction */
- case (SEQSTAT_HWERRCAUSE_RAISE_5):
- printk(KERN_NOTICE HWC_x18(KERN_NOTICE));
- break;
- default: /* Reserved */
- printk(KERN_NOTICE HWC_default(KERN_NOTICE));
- break;
- }
- CHK_DEBUGGER_TRAP_MAYBE();
- break;
- /*
- * We should be handling all known exception types above,
- * if we get here we hit a reserved one, so panic
- */
- default:
- info.si_code = ILL_ILLPARAOP;
- sig = SIGILL;
- verbose_printk(KERN_EMERG "Caught Unhandled Exception, code = %08lx\n",
- (fp->seqstat & SEQSTAT_EXCAUSE));
- CHK_DEBUGGER_TRAP_MAYBE();
- break;
- }
-
- BUG_ON(sig == 0);
-
- /* If the fault was caused by a kernel thread, or interrupt handler
- * we will kernel panic, so the system reboots.
- */
- if (kernel_mode_regs(fp) || (current && !current->mm)) {
- console_verbose();
- oops_in_progress = 1;
- }
-
- if (sig != SIGTRAP) {
- if (strerror)
- verbose_printk(strerror);
-
- dump_bfin_process(fp);
- dump_bfin_mem(fp);
- show_regs(fp);
-
- /* Print out the trace buffer if it makes sense */
-#ifndef CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE
- if (trapnr == VEC_CPLB_I_M || trapnr == VEC_CPLB_M)
- verbose_printk(KERN_NOTICE "No trace since you do not have "
- "CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE enabled\n\n");
- else
-#endif
- dump_bfin_trace_buffer();
-
- if (oops_in_progress) {
- /* Dump the current kernel stack */
- verbose_printk(KERN_NOTICE "Kernel Stack\n");
- show_stack(current, NULL);
- print_modules();
-#ifndef CONFIG_ACCESS_CHECK
- verbose_printk(KERN_EMERG "Please turn on "
- "CONFIG_ACCESS_CHECK\n");
-#endif
- panic("Kernel exception");
- } else {
-#ifdef CONFIG_DEBUG_VERBOSE
- unsigned long *stack;
- /* Dump the user space stack */
- stack = (unsigned long *)rdusp();
- verbose_printk(KERN_NOTICE "Userspace Stack\n");
- show_stack(NULL, stack);
-#endif
- }
- }
-
-#ifdef CONFIG_IPIPE
- if (!ipipe_trap_notify(fp->seqstat & 0x3f, fp))
-#endif
- {
- info.si_signo = sig;
- info.si_errno = 0;
- switch (trapnr) {
- case VEC_CPLB_VL:
- case VEC_MISALI_D:
- case VEC_CPLB_M:
- case VEC_CPLB_MHIT:
- info.si_addr = (void __user *)cpu_pda[cpu].dcplb_fault_addr;
- break;
- default:
- info.si_addr = (void __user *)fp->pc;
- break;
- }
- force_sig_info(sig, &info, current);
- }
-
- if ((ANOMALY_05000461 && trapnr == VEC_HWERR && !access_ok(VERIFY_READ, fp->pc, 8)) ||
- (ANOMALY_05000281 && trapnr == VEC_HWERR) ||
- (ANOMALY_05000189 && (trapnr == VEC_CPLB_I_VL || trapnr == VEC_CPLB_VL)))
- fp->pc = SAFE_USER_INSTRUCTION;
-
- traps_done:
- trace_buffer_restore(j);
-}
-
-asmlinkage void double_fault_c(struct pt_regs *fp)
-{
-#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON
- int j;
- trace_buffer_save(j);
-#endif
-
- console_verbose();
- oops_in_progress = 1;
-#ifdef CONFIG_DEBUG_VERBOSE
- printk(KERN_EMERG "Double Fault\n");
-#ifdef CONFIG_DEBUG_DOUBLEFAULT_PRINT
- if (((long)fp->seqstat & SEQSTAT_EXCAUSE) == VEC_UNCOV) {
- unsigned int cpu = raw_smp_processor_id();
- char buf[150];
- decode_address(buf, cpu_pda[cpu].retx_doublefault);
- printk(KERN_EMERG "While handling exception (EXCAUSE = 0x%x) at %s:\n",
- (unsigned int)cpu_pda[cpu].seqstat_doublefault & SEQSTAT_EXCAUSE, buf);
- decode_address(buf, cpu_pda[cpu].dcplb_doublefault_addr);
- printk(KERN_NOTICE " DCPLB_FAULT_ADDR: %s\n", buf);
- decode_address(buf, cpu_pda[cpu].icplb_doublefault_addr);
- printk(KERN_NOTICE " ICPLB_FAULT_ADDR: %s\n", buf);
-
- decode_address(buf, fp->retx);
- printk(KERN_NOTICE "The instruction at %s caused a double exception\n", buf);
- } else
-#endif
- {
- dump_bfin_process(fp);
- dump_bfin_mem(fp);
- show_regs(fp);
- dump_bfin_trace_buffer();
- }
-#endif
- panic("Double Fault - unrecoverable event");
-
-}
-
-
-void panic_cplb_error(int cplb_panic, struct pt_regs *fp)
-{
- switch (cplb_panic) {
- case CPLB_NO_UNLOCKED:
- printk(KERN_EMERG "All CPLBs are locked\n");
- break;
- case CPLB_PROT_VIOL:
- return;
- case CPLB_NO_ADDR_MATCH:
- return;
- case CPLB_UNKNOWN_ERR:
- printk(KERN_EMERG "Unknown CPLB Exception\n");
- break;
- }
-
- oops_in_progress = 1;
-
- dump_bfin_process(fp);
- dump_bfin_mem(fp);
- show_regs(fp);
- dump_stack();
- panic("Unrecoverable event");
-}
-
-#ifdef CONFIG_BUG
-int is_valid_bugaddr(unsigned long addr)
-{
- unsigned int opcode;
-
- if (!get_instruction(&opcode, (unsigned short *)addr))
- return 0;
-
- return opcode == BFIN_BUG_OPCODE;
-}
-#endif
-
-/* stub this out */
-#ifndef CONFIG_DEBUG_VERBOSE
-void show_regs(struct pt_regs *fp)
-{
-
-}
-#endif
+++ /dev/null
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <asm-generic/vmlinux.lds.h>
-#include <asm/mem_map.h>
-#include <asm/page.h>
-#include <asm/thread_info.h>
-
-OUTPUT_FORMAT("elf32-bfin")
-ENTRY(__start)
-_jiffies = _jiffies_64;
-
-SECTIONS
-{
-#ifdef CONFIG_RAMKERNEL
- . = CONFIG_BOOT_LOAD;
-#else
- . = CONFIG_ROM_BASE;
-#endif
-
- /* Neither the text, ro_data or bss section need to be aligned
- * So pack them back to back
- */
- .text :
- {
- __text = .;
- _text = .;
- __stext = .;
- TEXT_TEXT
-#ifndef CONFIG_SCHEDULE_L1
- SCHED_TEXT
-#endif
- CPUIDLE_TEXT
- LOCK_TEXT
- IRQENTRY_TEXT
- SOFTIRQENTRY_TEXT
- KPROBES_TEXT
-#ifdef CONFIG_ROMKERNEL
- __sinittext = .;
- INIT_TEXT
- __einittext = .;
- EXIT_TEXT
-#endif
- *(.text.*)
- *(.fixup)
-
-#if !L1_CODE_LENGTH
- *(.l1.text)
-#endif
- __etext = .;
- }
-
- EXCEPTION_TABLE(4)
- NOTES
-
- /* Just in case the first read only is a 32-bit access */
- RO_DATA(4)
- __rodata_end = .;
-
-#ifdef CONFIG_ROMKERNEL
- . = CONFIG_BOOT_LOAD;
- .bss : AT(__rodata_end)
-#else
- .bss :
-#endif
- {
- . = ALIGN(4);
- ___bss_start = .;
- *(.bss .bss.*)
- *(COMMON)
-#if !L1_DATA_A_LENGTH
- *(.l1.bss)
-#endif
-#if !L1_DATA_B_LENGTH
- *(.l1.bss.B)
-#endif
- . = ALIGN(4);
- ___bss_stop = .;
- }
-
-#if defined(CONFIG_ROMKERNEL)
- .data : AT(LOADADDR(.bss) + SIZEOF(.bss))
-#else
- .data :
-#endif
- {
- __sdata = .;
- /* This gets done first, so the glob doesn't suck it in */
- CACHELINE_ALIGNED_DATA(32)
-
-#if !L1_DATA_A_LENGTH
- . = ALIGN(32);
- *(.data_l1.cacheline_aligned)
- *(.l1.data)
-#endif
-#if !L1_DATA_B_LENGTH
- *(.l1.data.B)
-#endif
-#if !L2_LENGTH
- . = ALIGN(32);
- *(.data_l2.cacheline_aligned)
- *(.l2.data)
-#endif
-
- DATA_DATA
- CONSTRUCTORS
-
- INIT_TASK_DATA(THREAD_SIZE)
-
- __edata = .;
- }
- __data_lma = LOADADDR(.data);
- __data_len = SIZEOF(.data);
-
- BUG_TABLE
-
- /* The init section should be last, so when we free it, it goes into
- * the general memory pool, and (hopefully) will decrease fragmentation
- * a tiny bit. The init section has a _requirement_ that it be
- * PAGE_SIZE aligned
- */
- . = ALIGN(PAGE_SIZE);
- ___init_begin = .;
-
-#ifdef CONFIG_RAMKERNEL
- INIT_TEXT_SECTION(PAGE_SIZE)
-
- /* We have to discard exit text and such at runtime, not link time, to
- * handle embedded cross-section references (alt instructions, bug
- * table, eh_frame, etc...). We need all of our .text up front and
- * .data after it for PCREL call issues.
- */
- .exit.text :
- {
- EXIT_TEXT
- }
-
- . = ALIGN(16);
- INIT_DATA_SECTION(16)
- PERCPU_SECTION(32)
-
- .exit.data :
- {
- EXIT_DATA
- }
-
- .text_l1 L1_CODE_START : AT(LOADADDR(.exit.data) + SIZEOF(.exit.data))
-#else
- .init.data : AT(__data_lma + __data_len + 32)
- {
- __sinitdata = .;
- INIT_DATA
- INIT_SETUP(16)
- INIT_CALLS
- CON_INITCALL
- SECURITY_INITCALL
- INIT_RAM_FS
-
- . = ALIGN(PAGE_SIZE);
- ___per_cpu_load = .;
- PERCPU_INPUT(32)
-
- EXIT_DATA
- __einitdata = .;
- }
- __init_data_lma = LOADADDR(.init.data);
- __init_data_len = SIZEOF(.init.data);
- __init_data_end = .;
-
- .text_l1 L1_CODE_START : AT(__init_data_lma + __init_data_len)
-#endif
- {
- . = ALIGN(4);
- __stext_l1 = .;
- *(.l1.text.head)
- *(.l1.text)
-#ifdef CONFIG_SCHEDULE_L1
- SCHED_TEXT
-#endif
- . = ALIGN(4);
- __etext_l1 = .;
- }
- __text_l1_lma = LOADADDR(.text_l1);
- __text_l1_len = SIZEOF(.text_l1);
- ASSERT (__text_l1_len <= L1_CODE_LENGTH, "L1 text overflow!")
-
- .data_l1 L1_DATA_A_START : AT(__text_l1_lma + __text_l1_len)
- {
- . = ALIGN(4);
- __sdata_l1 = .;
- *(.l1.data)
- __edata_l1 = .;
-
- . = ALIGN(32);
- *(.data_l1.cacheline_aligned)
-
- . = ALIGN(4);
- __sbss_l1 = .;
- *(.l1.bss)
- . = ALIGN(4);
- __ebss_l1 = .;
- }
- __data_l1_lma = LOADADDR(.data_l1);
- __data_l1_len = SIZEOF(.data_l1);
- ASSERT (__data_l1_len <= L1_DATA_A_LENGTH, "L1 data A overflow!")
-
- .data_b_l1 L1_DATA_B_START : AT(__data_l1_lma + __data_l1_len)
- {
- . = ALIGN(4);
- __sdata_b_l1 = .;
- *(.l1.data.B)
- __edata_b_l1 = .;
-
- . = ALIGN(4);
- __sbss_b_l1 = .;
- *(.l1.bss.B)
- . = ALIGN(4);
- __ebss_b_l1 = .;
- }
- __data_b_l1_lma = LOADADDR(.data_b_l1);
- __data_b_l1_len = SIZEOF(.data_b_l1);
- ASSERT (__data_b_l1_len <= L1_DATA_B_LENGTH, "L1 data B overflow!")
-
- .text_data_l2 L2_START : AT(__data_b_l1_lma + __data_b_l1_len)
- {
- . = ALIGN(4);
- __stext_l2 = .;
- *(.l2.text)
- . = ALIGN(4);
- __etext_l2 = .;
-
- . = ALIGN(4);
- __sdata_l2 = .;
- *(.l2.data)
- __edata_l2 = .;
-
- . = ALIGN(32);
- *(.data_l2.cacheline_aligned)
-
- . = ALIGN(4);
- __sbss_l2 = .;
- *(.l2.bss)
- . = ALIGN(4);
- __ebss_l2 = .;
- }
- __l2_lma = LOADADDR(.text_data_l2);
- __l2_len = SIZEOF(.text_data_l2);
- ASSERT (__l2_len <= L2_LENGTH, "L2 overflow!")
-
- /* Force trailing alignment of our init section so that when we
- * free our init memory, we don't leave behind a partial page.
- */
-#ifdef CONFIG_RAMKERNEL
- . = __l2_lma + __l2_len;
-#else
- . = __init_data_end;
-#endif
- . = ALIGN(PAGE_SIZE);
- ___init_end = .;
-
- __end =.;
-
- STABS_DEBUG
-
- DWARF_DEBUG
-
- DISCARDS
-}
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0
-#
-# arch/blackfin/lib/Makefile
-#
-
-lib-y := \
- ashldi3.o ashrdi3.o lshrdi3.o \
- muldi3.o divsi3.o udivsi3.o modsi3.o umodsi3.o \
- memcpy.o memset.o memcmp.o memchr.o memmove.o \
- strcmp.o strcpy.o strncmp.o strncpy.o \
- umulsi3_highpart.o smulsi3_highpart.o \
- ins.o outs.o
+++ /dev/null
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include "gcclib.h"
-
-#ifdef CONFIG_ARITHMETIC_OPS_L1
-DItype __ashldi3(DItype u, word_type b)__attribute__((l1_text));
-#endif
-
-DItype __ashldi3(DItype u, word_type b)
-{
- DIunion w;
- word_type bm;
- DIunion uu;
-
- if (b == 0)
- return u;
-
- uu.ll = u;
-
- bm = (sizeof(SItype) * BITS_PER_UNIT) - b;
- if (bm <= 0) {
- w.s.low = 0;
- w.s.high = (USItype) uu.s.low << -bm;
- } else {
- USItype carries = (USItype) uu.s.low >> bm;
- w.s.low = (USItype) uu.s.low << b;
- w.s.high = ((USItype) uu.s.high << b) | carries;
- }
-
- return w.ll;
-}
+++ /dev/null
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include "gcclib.h"
-
-#ifdef CONFIG_ARITHMETIC_OPS_L1
-DItype __ashrdi3(DItype u, word_type b)__attribute__((l1_text));
-#endif
-
-DItype __ashrdi3(DItype u, word_type b)
-{
- DIunion w;
- word_type bm;
- DIunion uu;
-
- if (b == 0)
- return u;
-
- uu.ll = u;
-
- bm = (sizeof(SItype) * BITS_PER_UNIT) - b;
- if (bm <= 0) {
- /* w.s.high = 1..1 or 0..0 */
- w.s.high = uu.s.high >> (sizeof(SItype) * BITS_PER_UNIT - 1);
- w.s.low = uu.s.high >> -bm;
- } else {
- USItype carries = (USItype) uu.s.high << bm;
- w.s.high = uu.s.high >> b;
- w.s.low = ((USItype) uu.s.low >> b) | carries;
- }
-
- return w.ll;
-}
+++ /dev/null
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- *
- * 16 / 32 bit signed division.
- * Special cases :
- * 1) If(numerator == 0)
- * return 0
- * 2) If(denominator ==0)
- * return positive max = 0x7fffffff
- * 3) If(numerator == denominator)
- * return 1
- * 4) If(denominator ==1)
- * return numerator
- * 5) If(denominator == -1)
- * return -numerator
- *
- * Operand : R0 - Numerator (i)
- * R1 - Denominator (i)
- * R0 - Quotient (o)
- * Registers Used : R2-R7,P0-P2
- *
- */
-
-.global ___divsi3;
-.type ___divsi3, STT_FUNC;
-
-#ifdef CONFIG_ARITHMETIC_OPS_L1
-.section .l1.text
-#else
-.text
-#endif
-
-.align 2;
-___divsi3 :
-
-
- R3 = R0 ^ R1;
- R0 = ABS R0;
-
- CC = V;
-
- r3 = rot r3 by -1;
- r1 = abs r1; /* now both positive, r3.30 means "negate result",
- ** r3.31 means overflow, add one to result
- */
- cc = r0 < r1;
- if cc jump .Lret_zero;
- r2 = r1 >> 15;
- cc = r2;
- if cc jump .Lidents;
- r2 = r1 << 16;
- cc = r2 <= r0;
- if cc jump .Lidents;
-
- DIVS(R0, R1);
- DIVQ(R0, R1);
- DIVQ(R0, R1);
- DIVQ(R0, R1);
- DIVQ(R0, R1);
- DIVQ(R0, R1);
- DIVQ(R0, R1);
- DIVQ(R0, R1);
- DIVQ(R0, R1);
- DIVQ(R0, R1);
- DIVQ(R0, R1);
- DIVQ(R0, R1);
- DIVQ(R0, R1);
- DIVQ(R0, R1);
- DIVQ(R0, R1);
- DIVQ(R0, R1);
- DIVQ(R0, R1);
-
- R0 = R0.L (Z);
- r1 = r3 >> 31; /* add overflow issue back in */
- r0 = r0 + r1;
- r1 = -r0;
- cc = bittst(r3, 30);
- if cc r0 = r1;
- RTS;
-
-/* Can't use the primitives. Test common identities.
-** If the identity is true, return the value in R2.
-*/
-
-.Lidents:
- CC = R1 == 0; /* check for divide by zero */
- IF CC JUMP .Lident_return;
-
- CC = R0 == 0; /* check for division of zero */
- IF CC JUMP .Lzero_return;
-
- CC = R0 == R1; /* check for identical operands */
- IF CC JUMP .Lident_return;
-
- CC = R1 == 1; /* check for divide by 1 */
- IF CC JUMP .Lident_return;
-
- R2.L = ONES R1;
- R2 = R2.L (Z);
- CC = R2 == 1;
- IF CC JUMP .Lpower_of_two;
-
- /* Identities haven't helped either.
- ** Perform the full division process.
- */
-
- P1 = 31; /* Set loop counter */
-
- [--SP] = (R7:5); /* Push registers R5-R7 */
- R2 = -R1;
- [--SP] = R2;
- R2 = R0 << 1; /* R2 lsw of dividend */
- R6 = R0 ^ R1; /* Get sign */
- R5 = R6 >> 31; /* Shift sign to LSB */
-
- R0 = 0 ; /* Clear msw partial remainder */
- R2 = R2 | R5; /* Shift quotient bit */
- R6 = R0 ^ R1; /* Get new quotient bit */
-
- LSETUP(.Llst,.Llend) LC0 = P1; /* Setup loop */
-.Llst: R7 = R2 >> 31; /* record copy of carry from R2 */
- R2 = R2 << 1; /* Shift 64 bit dividend up by 1 bit */
- R0 = R0 << 1 || R5 = [SP];
- R0 = R0 | R7; /* and add carry */
- CC = R6 < 0; /* Check quotient(AQ) */
- /* we might be subtracting divisor (AQ==0) */
- IF CC R5 = R1; /* or we might be adding divisor (AQ==1)*/
- R0 = R0 + R5; /* do add or subtract, as indicated by AQ */
- R6 = R0 ^ R1; /* Generate next quotient bit */
- R5 = R6 >> 31;
- /* Assume AQ==1, shift in zero */
- BITTGL(R5,0); /* tweak AQ to be what we want to shift in */
-.Llend: R2 = R2 + R5; /* and then set shifted-in value to
- ** tweaked AQ.
- */
- r1 = r3 >> 31;
- r2 = r2 + r1;
- cc = bittst(r3,30);
- r0 = -r2;
- if !cc r0 = r2;
- SP += 4;
- (R7:5)= [SP++]; /* Pop registers R6-R7 */
- RTS;
-
-.Lident_return:
- CC = R1 == 0; /* check for divide by zero => 0x7fffffff */
- R2 = -1 (X);
- R2 >>= 1;
- IF CC JUMP .Ltrue_ident_return;
-
- CC = R0 == R1; /* check for identical operands => 1 */
- R2 = 1 (Z);
- IF CC JUMP .Ltrue_ident_return;
-
- R2 = R0; /* assume divide by 1 => numerator */
- /*FALLTHRU*/
-
-.Ltrue_ident_return:
- R0 = R2; /* Return an identity value */
- R2 = -R2;
- CC = bittst(R3,30);
- IF CC R0 = R2;
-.Lzero_return:
- RTS; /* ...including zero */
-
-.Lpower_of_two:
- /* Y has a single bit set, which means it's a power of two.
- ** That means we can perform the division just by shifting
- ** X to the right the appropriate number of bits
- */
-
- /* signbits returns the number of sign bits, minus one.
- ** 1=>30, 2=>29, ..., 0x40000000=>0. Which means we need
- ** to shift right n-signbits spaces. It also means 0x80000000
- ** is a special case, because that *also* gives a signbits of 0
- */
-
- R2 = R0 >> 31;
- CC = R1 < 0;
- IF CC JUMP .Ltrue_ident_return;
-
- R1.l = SIGNBITS R1;
- R1 = R1.L (Z);
- R1 += -30;
- R0 = LSHIFT R0 by R1.L;
- r1 = r3 >> 31;
- r0 = r0 + r1;
- R2 = -R0; // negate result if necessary
- CC = bittst(R3,30);
- IF CC R0 = R2;
- RTS;
-
-.Lret_zero:
- R0 = 0;
- RTS;
-
-.size ___divsi3, .-___divsi3
+++ /dev/null
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#define BITS_PER_UNIT 8
-#define SI_TYPE_SIZE (sizeof (SItype) * BITS_PER_UNIT)
-
-typedef unsigned int UQItype __attribute__ ((mode(QI)));
-typedef int SItype __attribute__ ((mode(SI)));
-typedef unsigned int USItype __attribute__ ((mode(SI)));
-typedef int DItype __attribute__ ((mode(DI)));
-typedef int word_type __attribute__ ((mode(__word__)));
-typedef unsigned int UDItype __attribute__ ((mode(DI)));
-
-struct DIstruct {
- SItype low, high;
-};
-
-typedef union {
- struct DIstruct s;
- DItype ll;
-} DIunion;
+++ /dev/null
-/*
- * arch/blackfin/lib/ins.S - ins{bwl} using hardware loops
- *
- * Copyright 2004-2008 Analog Devices Inc.
- * Copyright (C) 2005 Bas Vermeulen, BuyWays BV <bas@buyways.nl>
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/linkage.h>
-#include <asm/blackfin.h>
-
-.align 2
-
-#ifdef CONFIG_IPIPE
-# define DO_CLI \
- [--sp] = rets; \
- [--sp] = (P5:0); \
- sp += -12; \
- call ___ipipe_disable_root_irqs_hw; \
- sp += 12; \
- (P5:0) = [sp++];
-# define CLI_INNER_NOP
-#else
-# define DO_CLI cli R3;
-# define CLI_INNER_NOP nop; nop; nop;
-#endif
-
-#ifdef CONFIG_IPIPE
-# define DO_STI \
- sp += -12; \
- call ___ipipe_enable_root_irqs_hw; \
- sp += 12; \
-2: rets = [sp++];
-#else
-# define DO_STI 2: sti R3;
-#endif
-
-#ifdef CONFIG_BFIN_INS_LOWOVERHEAD
-# define CLI_OUTER DO_CLI;
-# define STI_OUTER DO_STI;
-# define CLI_INNER 1:
-# if ANOMALY_05000416
-# define STI_INNER nop; 2: nop;
-# else
-# define STI_INNER 2:
-# endif
-#else
-# define CLI_OUTER
-# define STI_OUTER
-# define CLI_INNER 1: DO_CLI; CLI_INNER_NOP;
-# define STI_INNER DO_STI;
-#endif
-
-/*
- * Reads on the Blackfin are speculative. In Blackfin terms, this means they
- * can be interrupted at any time (even after they have been issued on to the
- * external bus), and re-issued after the interrupt occurs.
- *
- * If a FIFO is sitting on the end of the read, it will see two reads,
- * when the core only sees one. The FIFO receives the read which is cancelled,
- * and not delivered to the core.
- *
- * To solve this, interrupts are turned off before reads occur to I/O space.
- * There are 3 versions of all these functions
- * - turns interrupts off every read (higher overhead, but lower latency)
- * - turns interrupts off every loop (low overhead, but longer latency)
- * - DMA version, which do not suffer from this issue. DMA versions have
- * different name (prefixed by dma_ ), and are located in
- * ../kernel/bfin_dma.c
- * Using the dma related functions are recommended for transferring large
- * buffers in/out of FIFOs.
- */
-
-#define COMMON_INS(func, ops) \
-ENTRY(_ins##func) \
- P0 = R0; /* P0 = port */ \
- CLI_OUTER; /* 3 instructions before first read access */ \
- P1 = R1; /* P1 = address */ \
- P2 = R2; /* P2 = count */ \
- SSYNC; \
- \
- LSETUP(1f, 2f) LC0 = P2; \
- CLI_INNER; \
- ops; \
- STI_INNER; \
- \
- STI_OUTER; \
- RTS; \
-ENDPROC(_ins##func)
-
-COMMON_INS(l, \
- R0 = [P0]; \
- [P1++] = R0; \
-)
-
-COMMON_INS(w, \
- R0 = W[P0]; \
- W[P1++] = R0; \
-)
-
-COMMON_INS(w_8, \
- R0 = W[P0]; \
- B[P1++] = R0; \
- R0 = R0 >> 8; \
- B[P1++] = R0; \
-)
-
-COMMON_INS(b, \
- R0 = B[P0]; \
- B[P1++] = R0; \
-)
-
-COMMON_INS(l_16, \
- R0 = [P0]; \
- W[P1++] = R0; \
- R0 = R0 >> 16; \
- W[P1++] = R0; \
-)
+++ /dev/null
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include "gcclib.h"
-
-#ifdef CONFIG_ARITHMETIC_OPS_L1
-DItype __lshrdi3(DItype u, word_type b)__attribute__((l1_text));
-#endif
-
-DItype __lshrdi3(DItype u, word_type b)
-{
- DIunion w;
- word_type bm;
- DIunion uu;
-
- if (b == 0)
- return u;
-
- uu.ll = u;
-
- bm = (sizeof(SItype) * BITS_PER_UNIT) - b;
- if (bm <= 0) {
- w.s.high = 0;
- w.s.low = (USItype) uu.s.high >> -bm;
- } else {
- USItype carries = (USItype) uu.s.high << bm;
- w.s.high = (USItype) uu.s.high >> b;
- w.s.low = ((USItype) uu.s.low >> b) | carries;
- }
-
- return w.ll;
-}
+++ /dev/null
-/*
- * Copyright 2005-2009 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#include <linux/linkage.h>
-
-/* void *memchr(const void *s, int c, size_t n);
- * R0 = address (s)
- * R1 = sought byte (c)
- * R2 = count (n)
- *
- * Returns pointer to located character.
- */
-
-.text
-
-.align 2
-
-ENTRY(_memchr)
- P0 = R0; /* P0 = address */
- P2 = R2; /* P2 = count */
- R1 = R1.B(Z);
- CC = R2 == 0;
- IF CC JUMP .Lfailed;
-
-.Lbytes:
- LSETUP (.Lbyte_loop_s, .Lbyte_loop_e) LC0=P2;
-
-.Lbyte_loop_s:
- R3 = B[P0++](Z);
- CC = R3 == R1;
- IF CC JUMP .Lfound;
-.Lbyte_loop_e:
- NOP;
-
-.Lfailed:
- R0=0;
- RTS;
-
-.Lfound:
- R0 = P0;
- R0 += -1;
- RTS;
-
-ENDPROC(_memchr)
+++ /dev/null
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#include <linux/linkage.h>
-
-/* int memcmp(const void *s1, const void *s2, size_t n);
- * R0 = First Address (s1)
- * R1 = Second Address (s2)
- * R2 = count (n)
- *
- * Favours word aligned data.
- */
-
-.text
-
-.align 2
-
-ENTRY(_memcmp)
- I1 = P3;
- P0 = R0; /* P0 = s1 address */
- P3 = R1; /* P3 = s2 Address */
- P2 = R2 ; /* P2 = count */
- CC = R2 <= 7(IU);
- IF CC JUMP .Ltoo_small;
- I0 = R1; /* s2 */
- R1 = R1 | R0; /* OR addresses together */
- R1 <<= 30; /* check bottom two bits */
- CC = AZ; /* AZ set if zero. */
- IF !CC JUMP .Lbytes ; /* Jump if addrs not aligned. */
-
- P1 = P2 >> 2; /* count = n/4 */
- R3 = 3;
- R2 = R2 & R3; /* remainder */
- P2 = R2; /* set remainder */
-
- LSETUP (.Lquad_loop_s, .Lquad_loop_e) LC0=P1;
-.Lquad_loop_s:
-#if ANOMALY_05000202
- R0 = [P0++];
- R1 = [I0++];
-#else
- MNOP || R0 = [P0++] || R1 = [I0++];
-#endif
- CC = R0 == R1;
- IF !CC JUMP .Lquad_different;
-.Lquad_loop_e:
- NOP;
-
- P3 = I0; /* s2 */
-.Ltoo_small:
- CC = P2 == 0; /* Check zero count*/
- IF CC JUMP .Lfinished; /* very unlikely*/
-
-.Lbytes:
- LSETUP (.Lbyte_loop_s, .Lbyte_loop_e) LC0=P2;
-.Lbyte_loop_s:
- R1 = B[P3++](Z); /* *s2 */
- R0 = B[P0++](Z); /* *s1 */
- CC = R0 == R1;
- IF !CC JUMP .Ldifferent;
-.Lbyte_loop_e:
- NOP;
-
-.Ldifferent:
- R0 = R0 - R1;
- P3 = I1;
- RTS;
-
-.Lquad_different:
- /* We've read two quads which don't match.
- * Can't just compare them, because we're
- * a little-endian machine, so the MSBs of
- * the regs occur at later addresses in the
- * string.
- * Arrange to re-read those two quads again,
- * byte-by-byte.
- */
- P0 += -4; /* back up to the start of the */
- P3 = I0; /* quads, and increase the*/
- P2 += 4; /* remainder count*/
- P3 += -4;
- JUMP .Lbytes;
-
-.Lfinished:
- R0 = 0;
- P3 = I1;
- RTS;
-
-ENDPROC(_memcmp)
+++ /dev/null
-/*
- * internal version of memcpy(), issued by the compiler to copy blocks of
- * data around. This is really memmove() - it has to be able to deal with
- * possible overlaps, because that ambiguity is when the compiler gives up
- * and calls a function. We have our own, internal version so that we get
- * something we trust, even if the user has redefined the normal symbol.
- *
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#include <linux/linkage.h>
-
-/* void *memcpy(void *dest, const void *src, size_t n);
- * R0 = To Address (dest) (leave unchanged to form result)
- * R1 = From Address (src)
- * R2 = count
- *
- * Note: Favours word alignment
- */
-
-#ifdef CONFIG_MEMCPY_L1
-.section .l1.text
-#else
-.text
-#endif
-
-.align 2
-
-ENTRY(_memcpy)
- CC = R2 <= 0; /* length not positive? */
- IF CC JUMP .L_P1L2147483647; /* Nothing to do */
-
- P0 = R0 ; /* dst*/
- P1 = R1 ; /* src*/
- P2 = R2 ; /* length */
-
- /* check for overlapping data */
- CC = R1 < R0; /* src < dst */
- IF !CC JUMP .Lno_overlap;
- R3 = R1 + R2;
- CC = R0 < R3; /* and dst < src+len */
- IF CC JUMP .Lhas_overlap;
-
-.Lno_overlap:
- /* Check for aligned data.*/
-
- R3 = R1 | R0;
- R1 = 0x3;
- R3 = R3 & R1;
- CC = R3; /* low bits set on either address? */
- IF CC JUMP .Lnot_aligned;
-
- /* Both addresses are word-aligned, so we can copy
- at least part of the data using word copies.*/
- P2 = P2 >> 2;
- CC = P2 <= 2;
- IF !CC JUMP .Lmore_than_seven;
- /* less than eight bytes... */
- P2 = R2;
- LSETUP(.Lthree_start, .Lthree_end) LC0=P2;
-.Lthree_start:
- R3 = B[P1++] (X);
-.Lthree_end:
- B[P0++] = R3;
-
- RTS;
-
-.Lmore_than_seven:
- /* There's at least eight bytes to copy. */
- P2 += -1; /* because we unroll one iteration */
- LSETUP(.Lword_loops, .Lword_loope) LC0=P2;
- I1 = P1;
- R3 = [I1++];
-#if ANOMALY_05000202
-.Lword_loops:
- [P0++] = R3;
-.Lword_loope:
- R3 = [I1++];
-#else
-.Lword_loops:
-.Lword_loope:
- MNOP || [P0++] = R3 || R3 = [I1++];
-#endif
- [P0++] = R3;
- /* Any remaining bytes to copy? */
- R3 = 0x3;
- R3 = R2 & R3;
- CC = R3 == 0;
- P1 = I1; /* in case there's something left, */
- IF !CC JUMP .Lbytes_left;
- RTS;
-.Lbytes_left: P2 = R3;
-.Lnot_aligned:
- /* From here, we're copying byte-by-byte. */
- LSETUP (.Lbyte_start, .Lbyte_end) LC0=P2;
-.Lbyte_start:
- R1 = B[P1++] (X);
-.Lbyte_end:
- B[P0++] = R1;
-
-.L_P1L2147483647:
- RTS;
-
-.Lhas_overlap:
- /* Need to reverse the copying, because the
- * dst would clobber the src.
- * Don't bother to work out alignment for
- * the reverse case.
- */
- P0 = P0 + P2;
- P0 += -1;
- P1 = P1 + P2;
- P1 += -1;
- LSETUP(.Lover_start, .Lover_end) LC0=P2;
-.Lover_start:
- R1 = B[P1--] (X);
-.Lover_end:
- B[P0--] = R1;
-
- RTS;
-
-ENDPROC(_memcpy)
+++ /dev/null
-/*
- * Copyright 2005-2009 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#include <linux/linkage.h>
-
-.align 2
-
-/*
- * C Library function MEMMOVE
- * R0 = To Address (leave unchanged to form result)
- * R1 = From Address
- * R2 = count
- * Data may overlap
- */
-
-ENTRY(_memmove)
- I1 = P3;
- P0 = R0; /* P0 = To address */
- P3 = R1; /* P3 = From Address */
- P2 = R2; /* P2 = count */
- CC = P2 == 0; /* Check zero count*/
- IF CC JUMP .Lfinished; /* very unlikely */
-
- CC = R1 < R0 (IU); /* From < To */
- IF !CC JUMP .Lno_overlap;
- R3 = R1 + R2;
- CC = R0 <= R3 (IU); /* (From+len) >= To */
- IF CC JUMP .Loverlap;
-.Lno_overlap:
- R3 = 11;
- CC = R2 <= R3;
- IF CC JUMP .Lbytes;
- R3 = R1 | R0; /* OR addresses together */
- R3 <<= 30; /* check bottom two bits */
- CC = AZ; /* AZ set if zero.*/
- IF !CC JUMP .Lbytes; /* Jump if addrs not aligned.*/
-
- I0 = P3;
- P1 = P2 >> 2; /* count = n/4 */
- P1 += -1;
- R3 = 3;
- R2 = R2 & R3; /* remainder */
- P2 = R2; /* set remainder */
- R1 = [I0++];
-
- LSETUP (.Lquad_loops, .Lquad_loope) LC0=P1;
-#if ANOMALY_05000202
-.Lquad_loops:
- [P0++] = R1;
-.Lquad_loope:
- R1 = [I0++];
-#else
-.Lquad_loops:
-.Lquad_loope:
- MNOP || [P0++] = R1 || R1 = [I0++];
-#endif
- [P0++] = R1;
-
- CC = P2 == 0; /* any remaining bytes? */
- P3 = I0; /* Amend P3 to updated ptr. */
- IF !CC JUMP .Lbytes;
- P3 = I1;
- RTS;
-
-.Lbytes: LSETUP (.Lbyte2_s, .Lbyte2_e) LC0=P2;
-.Lbyte2_s: R1 = B[P3++](Z);
-.Lbyte2_e: B[P0++] = R1;
-
-.Lfinished: P3 = I1;
- RTS;
-
-.Loverlap:
- P2 += -1;
- P0 = P0 + P2;
- P3 = P3 + P2;
- R1 = B[P3--] (Z);
- CC = P2 == 0;
- IF CC JUMP .Lno_loop;
-#if ANOMALY_05000245
- NOP;
- NOP;
-#endif
- LSETUP (.Lol_s, .Lol_e) LC0 = P2;
-.Lol_s: B[P0--] = R1;
-.Lol_e: R1 = B[P3--] (Z);
-.Lno_loop: B[P0] = R1;
- P3 = I1;
- RTS;
-
-ENDPROC(_memmove)
+++ /dev/null
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#include <linux/linkage.h>
-
-.align 2
-
-#ifdef CONFIG_MEMSET_L1
-.section .l1.text
-#else
-.text
-#endif
-
-/*
- * C Library function MEMSET
- * R0 = address (leave unchanged to form result)
- * R1 = filler byte
- * R2 = count
- * Favours word aligned data.
- * The strncpy assumes that I0 and I1 are not used in this function
- */
-
-ENTRY(_memset)
- P0 = R0 ; /* P0 = address */
- P2 = R2 ; /* P2 = count */
- R3 = R0 + R2; /* end */
- CC = R2 <= 7(IU);
- IF CC JUMP .Ltoo_small;
- R1 = R1.B (Z); /* R1 = fill char */
- R2 = 3;
- R2 = R0 & R2; /* addr bottom two bits */
- CC = R2 == 0; /* AZ set if zero. */
- IF !CC JUMP .Lforce_align ; /* Jump if addr not aligned. */
-
-.Laligned:
- P1 = P2 >> 2; /* count = n/4 */
- R2 = R1 << 8; /* create quad filler */
- R2.L = R2.L + R1.L(NS);
- R2.H = R2.L + R1.H(NS);
- P2 = R3;
-
- LSETUP (.Lquad_loop , .Lquad_loop) LC0=P1;
-.Lquad_loop:
- [P0++] = R2;
-
- CC = P0 == P2;
- IF !CC JUMP .Lbytes_left;
- RTS;
-
-.Lbytes_left:
- R2 = R3; /* end point */
- R3 = P0; /* current position */
- R2 = R2 - R3; /* bytes left */
- P2 = R2;
-
-.Ltoo_small:
- CC = P2 == 0; /* Check zero count */
- IF CC JUMP .Lfinished; /* Unusual */
-
-.Lbytes:
- LSETUP (.Lbyte_loop , .Lbyte_loop) LC0=P2;
-.Lbyte_loop:
- B[P0++] = R1;
-
-.Lfinished:
- RTS;
-
-.Lforce_align:
- CC = BITTST (R0, 0); /* odd byte */
- R0 = 4;
- R0 = R0 - R2;
- P1 = R0;
- R0 = P0; /* Recover return address */
- IF !CC JUMP .Lskip1;
- B[P0++] = R1;
-.Lskip1:
- CC = R2 <= 2; /* 2 bytes */
- P2 -= P1; /* reduce count */
- IF !CC JUMP .Laligned;
- B[P0++] = R1;
- B[P0++] = R1;
- JUMP .Laligned;
-
-ENDPROC(_memset)
+++ /dev/null
-/*
- * This program computes 32 bit signed remainder. It calls div32 function
- * for quotient estimation.
- * Registers in: R0, R1 = Numerator/ Denominator
- * Registers out: R0 = Remainder
- *
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-.global ___modsi3;
-.type ___modsi3, STT_FUNC;
-.extern ___divsi3;
-.type ___divsi3, STT_FUNC;
-
-#ifdef CONFIG_ARITHMETIC_OPS_L1
-.section .l1.text
-#else
-.text
-#endif
-
-___modsi3:
-
- CC=R0==0;
- IF CC JUMP .LRETURN_R0; /* Return 0, if numerator == 0 */
- CC=R1==0;
- IF CC JUMP .LRETURN_ZERO; /* Return 0, if denominator == 0 */
- CC=R0==R1;
- IF CC JUMP .LRETURN_ZERO; /* Return 0, if numerator == denominator */
- CC = R1 == 1;
- IF CC JUMP .LRETURN_ZERO; /* Return 0, if denominator == 1 */
- CC = R1 == -1;
- IF CC JUMP .LRETURN_ZERO; /* Return 0, if denominator == -1 */
-
- /* Valid input. Use __divsi3() to compute the quotient, and then
- * derive the remainder from that. */
-
- [--SP] = (R7:6); /* Push R7 and R6 */
- [--SP] = RETS; /* and return address */
- R7 = R0; /* Copy of R0 */
- R6 = R1; /* Save for later */
- SP += -12; /* Should always provide this space */
- CALL ___divsi3; /* Compute signed quotient using ___divsi3()*/
- SP += 12;
- R0 *= R6; /* Quotient * divisor */
- R0 = R7 - R0; /* Dividend - (quotient * divisor) */
- RETS = [SP++]; /* Get back return address */
- (R7:6) = [SP++]; /* Pop registers R7 and R4 */
- RTS; /* Store remainder */
-
-.LRETURN_ZERO:
- R0 = 0;
-.LRETURN_R0:
- RTS;
-
-.size ___modsi3, .-___modsi3
+++ /dev/null
-/*
- * Copyright 2008 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-.align 2
-.global ___muldi3;
-.type ___muldi3, STT_FUNC;
-
-#ifdef CONFIG_ARITHMETIC_OPS_L1
-.section .l1.text
-#else
-.text
-#endif
-
-/*
- R1:R0 * R3:R2
- = R1.h:R1.l:R0.h:R0.l * R3.h:R3.l:R2.h:R2.l
-[X] = (R1.h * R3.h) * 2^96
-[X] + (R1.h * R3.l + R1.l * R3.h) * 2^80
-[X] + (R1.h * R2.h + R1.l * R3.l + R3.h * R0.h) * 2^64
-[T1] + (R1.h * R2.l + R3.h * R0.l + R1.l * R2.h + R3.l * R0.h) * 2^48
-[T2] + (R1.l * R2.l + R3.l * R0.l + R0.h * R2.h) * 2^32
-[T3] + (R0.l * R2.h + R2.l * R0.h) * 2^16
-[T4] + (R0.l * R2.l)
-
- We can discard the first three lines marked "X" since we produce
- only a 64 bit result. So, we need ten 16-bit multiplies.
-
- Individual mul-acc results:
-[E1] = R1.h * R2.l + R3.h * R0.l + R1.l * R2.h + R3.l * R0.h
-[E2] = R1.l * R2.l + R3.l * R0.l + R0.h * R2.h
-[E3] = R0.l * R2.h + R2.l * R0.h
-[E4] = R0.l * R2.l
-
- We also need to add high parts from lower-level results to higher ones:
- E[n]c = E[n] + (E[n+1]c >> 16), where E4c := E4
-
- One interesting property is that all parts of the result that depend
- on the sign of the multiplication are discarded. Those would be the
- multiplications involving R1.h and R3.h, but only the top 16 bit of
- the 32 bit result depend on the sign, and since R1.h and R3.h only
- occur in E1, the top half of these results is cut off.
- So, we can just use FU mode for all of the 16-bit multiplies, and
- ignore questions of when to use mixed mode. */
-
-___muldi3:
- /* [SP] technically is part of the caller's frame, but we can
- use it as scratch space. */
- A0 = R2.H * R1.L, A1 = R2.L * R1.H (FU) || R3 = [SP + 12]; /* E1 */
- A0 += R3.H * R0.L, A1 += R3.L * R0.H (FU) || [SP] = R4; /* E1 */
- A0 += A1; /* E1 */
- R4 = A0.w;
- A0 = R0.l * R3.l (FU); /* E2 */
- A0 += R2.l * R1.l (FU); /* E2 */
-
- A1 = R2.L * R0.L (FU); /* E4 */
- R3 = A1.w;
- A1 = A1 >> 16; /* E3c */
- A0 += R2.H * R0.H, A1 += R2.L * R0.H (FU); /* E2, E3c */
- A1 += R0.L * R2.H (FU); /* E3c */
- R0 = A1.w;
- A1 = A1 >> 16; /* E2c */
- A0 += A1; /* E2c */
- R1 = A0.w;
-
- /* low(result) = low(E3c):low(E4) */
- R0 = PACK (R0.l, R3.l);
- /* high(result) = E2c + (E1 << 16) */
- R1.h = R1.h + R4.l (NS) || R4 = [SP];
- RTS;
-
-.size ___muldi3, .-___muldi3
+++ /dev/null
-/*
- * Implementation of outs{bwl} for BlackFin processors using zero overhead loops.
- *
- * Copyright 2005-2009 Analog Devices Inc.
- * 2005 BuyWays BV
- * Bas Vermeulen <bas@buyways.nl>
- *
- * Licensed under the GPL-2.
- */
-
-#include <linux/linkage.h>
-
-.align 2
-
-ENTRY(_outsl)
- CC = R2 == 0;
- IF CC JUMP 1f;
- P0 = R0; /* P0 = port */
- P1 = R1; /* P1 = address */
- P2 = R2; /* P2 = count */
-
- LSETUP( .Llong_loop_s, .Llong_loop_e) LC0 = P2;
-.Llong_loop_s: R0 = [P1++];
-.Llong_loop_e: [P0] = R0;
-1: RTS;
-ENDPROC(_outsl)
-
-ENTRY(_outsw)
- CC = R2 == 0;
- IF CC JUMP 1f;
- P0 = R0; /* P0 = port */
- P1 = R1; /* P1 = address */
- P2 = R2; /* P2 = count */
-
- LSETUP( .Lword_loop_s, .Lword_loop_e) LC0 = P2;
-.Lword_loop_s: R0 = W[P1++];
-.Lword_loop_e: W[P0] = R0;
-1: RTS;
-ENDPROC(_outsw)
-
-ENTRY(_outsb)
- CC = R2 == 0;
- IF CC JUMP 1f;
- P0 = R0; /* P0 = port */
- P1 = R1; /* P1 = address */
- P2 = R2; /* P2 = count */
-
- LSETUP( .Lbyte_loop_s, .Lbyte_loop_e) LC0 = P2;
-.Lbyte_loop_s: R0 = B[P1++];
-.Lbyte_loop_e: B[P0] = R0;
-1: RTS;
-ENDPROC(_outsb)
-
-ENTRY(_outsw_8)
- CC = R2 == 0;
- IF CC JUMP 1f;
- P0 = R0; /* P0 = port */
- P1 = R1; /* P1 = address */
- P2 = R2; /* P2 = count */
-
- LSETUP( .Lword8_loop_s, .Lword8_loop_e) LC0 = P2;
-.Lword8_loop_s: R1 = B[P1++];
- R0 = B[P1++];
- R0 = R0 << 8;
- R0 = R0 + R1;
-.Lword8_loop_e: W[P0] = R0;
-1: RTS;
-ENDPROC(_outsw_8)
+++ /dev/null
-/*
- * Copyright 2007 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-.align 2
-.global ___smulsi3_highpart;
-.type ___smulsi3_highpart, STT_FUNC;
-
-#ifdef CONFIG_ARITHMETIC_OPS_L1
-.section .l1.text
-#else
-.text
-#endif
-
-___smulsi3_highpart:
- R2 = R1.L * R0.L (FU);
- R3 = R1.H * R0.L (IS,M);
- R0 = R0.H * R1.H, R1 = R0.H * R1.L (IS,M);
-
- R1.L = R2.H + R1.L;
- cc = ac0;
- R2 = cc;
-
- R1.L = R1.L + R3.L;
- cc = ac0;
- R1 >>>= 16;
- R3 >>>= 16;
- R1 = R1 + R3;
- R1 = R1 + R2;
- R2 = cc;
- R1 = R1 + R2;
-
- R0 = R0 + R1;
- RTS;
-
-.size ___smulsi3_highpart, .-___smulsi3_highpart
+++ /dev/null
-/*
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#include <linux/linkage.h>
-
-/* void *strcmp(char *s1, const char *s2);
- * R0 = address (s1)
- * R1 = address (s2)
- *
- * Returns an integer less than, equal to, or greater than zero if s1
- * (or the first n bytes thereof) is found, respectively, to be less
- * than, to match, or be greater than s2.
- */
-
-#ifdef CONFIG_STRCMP_L1
-.section .l1.text
-#else
-.text
-#endif
-
-.align 2
-
-ENTRY(_strcmp)
- P0 = R0 ; /* s1 */
- P1 = R1 ; /* s2 */
-
-1:
- R0 = B[P0++] (Z); /* get *s1 */
- R1 = B[P1++] (Z); /* get *s2 */
- CC = R0 == R1; /* compare a byte */
- if ! cc jump 2f; /* not equal, break out */
- CC = R0; /* at end of s1? */
- if cc jump 1b (bp); /* no, keep going */
- jump.s 3f; /* strings are equal */
-2:
- R0 = R0 - R1; /* *s1 - *s2 */
-3:
- RTS;
-
-ENDPROC(_strcmp)
+++ /dev/null
-/*
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#include <linux/linkage.h>
-
-/* void *strcpy(char *dest, const char *src);
- * R0 = address (dest)
- * R1 = address (src)
- *
- * Returns a pointer to the destination string dest
- */
-
-#ifdef CONFIG_STRCPY_L1
-.section .l1.text
-#else
-.text
-#endif
-
-.align 2
-
-ENTRY(_strcpy)
- P0 = R0 ; /* dst*/
- P1 = R1 ; /* src*/
-
-1:
- R1 = B [P1++] (Z);
- B [P0++] = R1;
- CC = R1;
- if cc jump 1b (bp);
- RTS;
-
-ENDPROC(_strcpy)
+++ /dev/null
-/*
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#include <linux/linkage.h>
-
-/* void *strncpy(char *s1, const char *s2, size_t n);
- * R0 = address (dest)
- * R1 = address (src)
- * R2 = size (n)
- * Returns a pointer to the destination string dest
- */
-
-#ifdef CONFIG_STRNCMP_L1
-.section .l1.text
-#else
-.text
-#endif
-
-.align 2
-
-ENTRY(_strncmp)
- CC = R2 == 0;
- if CC JUMP 5f;
-
- P0 = R0 ; /* s1 */
- P1 = R1 ; /* s2 */
-1:
- R0 = B[P0++] (Z); /* get *s1 */
- R1 = B[P1++] (Z); /* get *s2 */
- CC = R0 == R1; /* compare a byte */
- if ! cc jump 3f; /* not equal, break out */
- CC = R0; /* at end of s1? */
- if ! cc jump 4f; /* yes, all done */
- R2 += -1; /* no, adjust count */
- CC = R2 == 0;
- if ! cc jump 1b (bp); /* more to do, keep going */
-2:
- R0 = 0; /* strings are equal */
- jump.s 4f;
-3:
- R0 = R0 - R1; /* *s1 - *s2 */
-4:
- RTS;
-
-5:
- R0 = 0;
- RTS;
-
-ENDPROC(_strncmp)
+++ /dev/null
-/*
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#include <linux/linkage.h>
-#include <asm/context.S>
-
-/* void *strncpy(char *dest, const char *src, size_t n);
- * R0 = address (dest)
- * R1 = address (src)
- * R2 = size
- * Returns a pointer (R0) to the destination string dest
- * we do this by not changing R0
- */
-
-#ifdef CONFIG_STRNCPY_L1
-.section .l1.text
-#else
-.text
-#endif
-
-.align 2
-
-ENTRY(_strncpy)
- CC = R2 == 0;
- if CC JUMP 6f;
-
- P2 = R2 ; /* size */
- P0 = R0 ; /* dst*/
- P1 = R1 ; /* src*/
-
- LSETUP (1f, 2f) LC0 = P2;
-1:
- R1 = B [P1++] (Z);
- B [P0++] = R1;
- CC = R1 == 0;
-2:
- if CC jump 3f;
-
- RTS;
-
- /* if src is shorter than n, we need to null pad bytes in dest
- * but, we can get here when the last byte is zero, and we don't
- * want to copy an extra byte at the end, so we need to check
- */
-3:
- R2 = LC0;
- CC = R2
- if ! CC jump 6f;
-
- /* if the required null padded portion is small, do it here, rather than
- * handling the overhead of memset (which is OK when things are big).
- */
- R3 = 0x20;
- CC = R2 < R3;
- IF CC jump 4f;
-
- R2 += -1;
-
- /* Set things up for memset
- * R0 = address
- * R1 = filler byte (this case it's zero, set above)
- * R2 = count (set above)
- */
-
- I1 = R0;
- R0 = RETS;
- I0 = R0;
- R0 = P0;
- pseudo_long_call _memset, p0;
- R0 = I0;
- RETS = R0;
- R0 = I1;
- RTS;
-
-4:
- LSETUP(5f, 5f) LC0;
-5:
- B [P0++] = R1;
-6:
- RTS;
-
-ENDPROC(_strncpy)
+++ /dev/null
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#include <linux/linkage.h>
-
-#define CARRY AC0
-
-#ifdef CONFIG_ARITHMETIC_OPS_L1
-.section .l1.text
-#else
-.text
-#endif
-
-
-ENTRY(___udivsi3)
-
- CC = R0 < R1 (IU); /* If X < Y, always return 0 */
- IF CC JUMP .Lreturn_ident;
-
- R2 = R1 << 16;
- CC = R2 <= R0 (IU);
- IF CC JUMP .Lidents;
-
- R2 = R0 >> 31; /* if X is a 31-bit number */
- R3 = R1 >> 15; /* and Y is a 15-bit number */
- R2 = R2 | R3; /* then it's okay to use the DIVQ builtins (fallthrough to fast)*/
- CC = R2;
- IF CC JUMP .Ly_16bit;
-
-/* METHOD 1: FAST DIVQ
- We know we have a 31-bit dividend, and 15-bit divisor so we can use the
- simple divq approach (first setting AQ to 0 - implying unsigned division,
- then 16 DIVQ's).
-*/
-
- AQ = CC; /* Clear AQ (CC==0) */
-
-/* ISR States: When dividing two integers (32.0/16.0) using divide primitives,
- we need to shift the dividend one bit to the left.
- We have already checked that we have a 31-bit number so we are safe to do
- that.
-*/
- R0 <<= 1;
- DIVQ(R0, R1); // 1
- DIVQ(R0, R1); // 2
- DIVQ(R0, R1); // 3
- DIVQ(R0, R1); // 4
- DIVQ(R0, R1); // 5
- DIVQ(R0, R1); // 6
- DIVQ(R0, R1); // 7
- DIVQ(R0, R1); // 8
- DIVQ(R0, R1); // 9
- DIVQ(R0, R1); // 10
- DIVQ(R0, R1); // 11
- DIVQ(R0, R1); // 12
- DIVQ(R0, R1); // 13
- DIVQ(R0, R1); // 14
- DIVQ(R0, R1); // 15
- DIVQ(R0, R1); // 16
- R0 = R0.L (Z);
- RTS;
-
-.Ly_16bit:
- /* We know that the upper 17 bits of Y might have bits set,
- ** or that the sign bit of X might have a bit. If Y is a
- ** 16-bit number, but not bigger, then we can use the builtins
- ** with a post-divide correction.
- ** R3 currently holds Y>>15, which means R3's LSB is the
- ** bit we're interested in.
- */
-
- /* According to the ISR, to use the Divide primitives for
- ** unsigned integer divide, the useable range is 31 bits
- */
- CC = ! BITTST(R0, 31);
-
- /* IF condition is true we can scale our inputs and use the divide primitives,
- ** with some post-adjustment
- */
- R3 += -1; /* if so, Y is 0x00008nnn */
- CC &= AZ;
-
- /* If condition is true we can scale our inputs and use the divide primitives,
- ** with some post-adjustment
- */
- R3 = R1 >> 1; /* Pre-scaled divisor for primitive case */
- R2 = R0 >> 16;
-
- R2 = R3 - R2; /* shifted divisor < upper 16 bits of dividend */
- CC &= CARRY;
- IF CC JUMP .Lshift_and_correct;
-
- /* Fall through to the identities */
-
-/* METHOD 2: identities and manual calculation
- We are not able to use the divide primites, but may still catch some special
- cases.
-*/
-.Lidents:
- /* Test for common identities. Value to be returned is placed in R2. */
- CC = R0 == 0; /* 0/Y => 0 */
- IF CC JUMP .Lreturn_r0;
- CC = R0 == R1; /* X==Y => 1 */
- IF CC JUMP .Lreturn_ident;
- CC = R1 == 1; /* X/1 => X */
- IF CC JUMP .Lreturn_ident;
-
- R2.L = ONES R1;
- R2 = R2.L (Z);
- CC = R2 == 1;
- IF CC JUMP .Lpower_of_two;
-
- [--SP] = (R7:5); /* Push registers R5-R7 */
-
- /* Idents don't match. Go for the full operation. */
-
-
- R6 = 2; /* assume we'll shift two */
- R3 = 1;
-
- P2 = R1;
- /* If either R0 or R1 have sign set, */
- /* divide them by two, and note it's */
- /* been done. */
- CC = R1 < 0;
- R2 = R1 >> 1;
- IF CC R1 = R2; /* Possibly-shifted R1 */
- IF !CC R6 = R3; /* R1 doesn't, so at most 1 shifted */
-
- P0 = 0;
- R3 = -R1;
- [--SP] = R3;
- R2 = R0 >> 1;
- R2 = R0 >> 1;
- CC = R0 < 0;
- IF CC P0 = R6; /* Number of values divided */
- IF !CC R2 = R0; /* Shifted R0 */
-
- /* P0 is 0, 1 (NR/=2) or 2 (NR/=2, DR/=2) */
-
- /* r2 holds Copy dividend */
- R3 = 0; /* Clear partial remainder */
- R7 = 0; /* Initialise quotient bit */
-
- P1 = 32; /* Set loop counter */
- LSETUP(.Lulst, .Lulend) LC0 = P1; /* Set loop counter */
-.Lulst: R6 = R2 >> 31; /* R6 = sign bit of R2, for carry */
- R2 = R2 << 1; /* Shift 64 bit dividend up by 1 bit */
- R3 = R3 << 1 || R5 = [SP];
- R3 = R3 | R6; /* Include any carry */
- CC = R7 < 0; /* Check quotient(AQ) */
- /* If AQ==0, we'll sub divisor */
- IF CC R5 = R1; /* and if AQ==1, we'll add it. */
- R3 = R3 + R5; /* Add/sub divisor to partial remainder */
- R7 = R3 ^ R1; /* Generate next quotient bit */
-
- R5 = R7 >> 31; /* Get AQ */
- BITTGL(R5, 0); /* Invert it, to get what we'll shift */
-.Lulend: R2 = R2 + R5; /* and "shift" it in. */
-
- CC = P0 == 0; /* Check how many inputs we shifted */
- IF CC JUMP .Lno_mult; /* if none... */
- R6 = R2 << 1;
- CC = P0 == 1;
- IF CC R2 = R6; /* if 1, Q = Q*2 */
- IF !CC R1 = P2; /* if 2, restore stored divisor */
-
- R3 = R2; /* Copy of R2 */
- R3 *= R1; /* Q * divisor */
- R5 = R0 - R3; /* Z = (dividend - Q * divisor) */
- CC = R1 <= R5 (IU); /* Check if divisor <= Z? */
- R6 = CC; /* if yes, R6 = 1 */
- R2 = R2 + R6; /* if yes, add one to quotient(Q) */
-.Lno_mult:
- SP += 4;
- (R7:5) = [SP++]; /* Pop registers R5-R7 */
- R0 = R2; /* Store quotient */
- RTS;
-
-.Lreturn_ident:
- CC = R0 < R1 (IU); /* If X < Y, always return 0 */
- R2 = 0;
- IF CC JUMP .Ltrue_return_ident;
- R2 = -1 (X); /* X/0 => 0xFFFFFFFF */
- CC = R1 == 0;
- IF CC JUMP .Ltrue_return_ident;
- R2 = -R2; /* R2 now 1 */
- CC = R0 == R1; /* X==Y => 1 */
- IF CC JUMP .Ltrue_return_ident;
- R2 = R0; /* X/1 => X */
- /*FALLTHRU*/
-
-.Ltrue_return_ident:
- R0 = R2;
-.Lreturn_r0:
- RTS;
-
-.Lpower_of_two:
- /* Y has a single bit set, which means it's a power of two.
- ** That means we can perform the division just by shifting
- ** X to the right the appropriate number of bits
- */
-
- /* signbits returns the number of sign bits, minus one.
- ** 1=>30, 2=>29, ..., 0x40000000=>0. Which means we need
- ** to shift right n-signbits spaces. It also means 0x80000000
- ** is a special case, because that *also* gives a signbits of 0
- */
-
- R2 = R0 >> 31;
- CC = R1 < 0;
- IF CC JUMP .Ltrue_return_ident;
-
- R1.l = SIGNBITS R1;
- R1 = R1.L (Z);
- R1 += -30;
- R0 = LSHIFT R0 by R1.L;
- RTS;
-
-/* METHOD 3: PRESCALE AND USE THE DIVIDE PRIMITIVES WITH SOME POST-CORRECTION
- Two scaling operations are required to use the divide primitives with a
- divisor > 0x7FFFF.
- Firstly (as in method 1) we need to shift the dividend 1 to the left for
- integer division.
- Secondly we need to shift both the divisor and dividend 1 to the right so
- both are in range for the primitives.
- The left/right shift of the dividend does nothing so we can skip it.
-*/
-.Lshift_and_correct:
- R2 = R0;
- // R3 is already R1 >> 1
- CC=!CC;
- AQ = CC; /* Clear AQ, got here with CC = 0 */
- DIVQ(R2, R3); // 1
- DIVQ(R2, R3); // 2
- DIVQ(R2, R3); // 3
- DIVQ(R2, R3); // 4
- DIVQ(R2, R3); // 5
- DIVQ(R2, R3); // 6
- DIVQ(R2, R3); // 7
- DIVQ(R2, R3); // 8
- DIVQ(R2, R3); // 9
- DIVQ(R2, R3); // 10
- DIVQ(R2, R3); // 11
- DIVQ(R2, R3); // 12
- DIVQ(R2, R3); // 13
- DIVQ(R2, R3); // 14
- DIVQ(R2, R3); // 15
- DIVQ(R2, R3); // 16
-
- /* According to the Instruction Set Reference:
- To divide by a divisor > 0x7FFF,
- 1. prescale and perform divide to obtain quotient (Q) (done above),
- 2. multiply quotient by unscaled divisor (result M)
- 3. subtract the product from the divident to get an error (E = X - M)
- 4. if E < divisor (Y) subtract 1, if E > divisor (Y) add 1, else return quotient (Q)
- */
- R3 = R2.L (Z); /* Q = X' / Y' */
- R2 = R3; /* Preserve Q */
- R2 *= R1; /* M = Q * Y */
- R2 = R0 - R2; /* E = X - M */
- R0 = R3; /* Copy Q into result reg */
-
-/* Correction: If result of the multiply is negative, we overflowed
- and need to correct the result by subtracting 1 from the result.*/
- R3 = 0xFFFF (Z);
- R2 = R2 >> 16; /* E >> 16 */
- CC = R2 == R3;
- R3 = 1 ;
- R1 = R0 - R3;
- IF CC R0 = R1;
- RTS;
-
-ENDPROC(___udivsi3)
+++ /dev/null
-/*
- * libgcc1 routines for Blackfin 5xx
- *
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifdef CONFIG_ARITHMETIC_OPS_L1
-.section .l1.text
-#else
-.text
-#endif
-
-.extern ___udivsi3;
-.type ___udivsi3, STT_FUNC;
-.globl ___umodsi3
-.type ___umodsi3, STT_FUNC;
-___umodsi3:
-
- CC=R0==0;
- IF CC JUMP .LRETURN_R0; /* Return 0, if NR == 0 */
- CC= R1==0;
- IF CC JUMP .LRETURN_ZERO_VAL; /* Return 0, if DR == 0 */
- CC=R0==R1;
- IF CC JUMP .LRETURN_ZERO_VAL; /* Return 0, if NR == DR */
- CC = R1 == 1;
- IF CC JUMP .LRETURN_ZERO_VAL; /* Return 0, if DR == 1 */
- CC = R0<R1 (IU);
- IF CC JUMP .LRETURN_R0; /* Return dividend (R0),IF NR<DR */
-
- [--SP] = (R7:6); /* Push registers and */
- [--SP] = RETS; /* Return address */
- R7 = R0; /* Copy of R0 */
- R6 = R1;
- SP += -12; /* Should always provide this space */
- CALL ___udivsi3; /* Compute unsigned quotient using ___udiv32()*/
- SP += 12;
- R0 *= R6; /* Quotient * divisor */
- R0 = R7 - R0; /* Dividend - (quotient * divisor) */
- RETS = [SP++]; /* Pop return address */
- ( R7:6) = [SP++]; /* And registers */
- RTS; /* Return remainder */
-.LRETURN_ZERO_VAL:
- R0 = 0;
-.LRETURN_R0:
- RTS;
-
-.size ___umodsi3, .-___umodsi3
+++ /dev/null
-/*
- * Copyright 2007 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-.align 2
-.global ___umulsi3_highpart;
-.type ___umulsi3_highpart, STT_FUNC;
-
-#ifdef CONFIG_ARITHMETIC_OPS_L1
-.section .l1.text
-#else
-.text
-#endif
-
-___umulsi3_highpart:
- R2 = R1.H * R0.H, R3 = R1.L * R0.H (FU);
- R0 = R1.L * R0.L, R1 = R1.H * R0.L (FU);
- R0 >>= 16;
- /* Unsigned multiplication has the nice property that we can
- ignore carry on this first addition. */
- R0 = R0 + R3;
- R0 = R0 + R1;
- cc = ac0;
- R1 = cc;
- R1 = PACK(R1.l,R0.h);
- R0 = R1 + R2;
- RTS;
-
-.size ___umulsi3_highpart, .-___umulsi3_highpart
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0
-config BF51x
- def_bool y
- depends on (BF512 || BF514 || BF516 || BF518)
-
-if (BF51x)
-
-source "arch/blackfin/mach-bf518/boards/Kconfig"
-
-menu "BF518 Specific Configuration"
-
-comment "Alternative Multiplexing Scheme"
-
-choice
- prompt "PWM Channel Pins"
- default BF518_PWM_ALL_PORTF
- help
- Select pins used for the PWM channels:
- PWM_AH PWM_AL PWM_BH PWM_BL PWM_CH PWM_CL
-
- See the Hardware Reference Manual for more details.
-
-config BF518_PWM_ALL_PORTF
- bool "PF1 - PF6"
- help
- PF{1,2,3,4,5,6} <-> PWM_{AH,AL,BH,BL,CH,CL}
-
-config BF518_PWM_PORTF_PORTG
- bool "PF11 - PF14 / PG1 - PG2"
- help
- PF{11,12,13,14} <-> PWM_{AH,AL,BH,BL}
- PG{1,2} <-> PWM_{CH,CL}
-
-endchoice
-
-choice
- prompt "PWM Sync Pin"
- default BF518_PWM_SYNC_PF7
- help
- Select the pin used for PWM_SYNC.
-
- See the Hardware Reference Manual for more details.
-
-config BF518_PWM_SYNC_PF7
- bool "PF7"
-config BF518_PWM_SYNC_PF15
- bool "PF15"
-endchoice
-
-choice
- prompt "PWM Trip B Pin"
- default BF518_PWM_TRIPB_PG10
- help
- Select the pin used for PWM_TRIPB.
-
- See the Hardware Reference Manual for more details.
-
-config BF518_PWM_TRIPB_PG10
- bool "PG10"
-config BF518_PWM_TRIPB_PG14
- bool "PG14"
-endchoice
-
-choice
- prompt "PPI / Timer Pins"
- default BF518_PPI_TMR_PG5
- help
- Select pins used for PPI/Timer:
- PPICLK PPIFS1 PPIFS2
- TMRCLK TMR0 TMR1
-
- See the Hardware Reference Manual for more details.
-
-config BF518_PPI_TMR_PG5
- bool "PG5 - PG7"
- help
- PG{5,6,7} <-> {PPICLK/TMRCLK,TMR0/PPIFS1,TMR1/PPIFS2}
-
-config BF518_PPI_TMR_PG12
- bool "PG12 - PG14"
- help
- PG{12,13,14} <-> {PPICLK/TMRCLK,TMR0/PPIFS1,TMR1/PPIFS2}
-
-endchoice
-
-comment "Hysteresis/Schmitt Trigger Control"
-config BFIN_HYSTERESIS_CONTROL
- bool "Enable Hysteresis Control"
- help
- The ADSP-BF51x allows to control input hysteresis for Port F,
- Port G and Port H and other processor signal inputs.
- The Schmitt trigger enables can be set only for pin groups.
- Saying Y will overwrite the default reset or boot loader
- initialization.
-
-menu "PORT F"
- depends on BFIN_HYSTERESIS_CONTROL
-config GPIO_HYST_PORTF_0_7
- bool "Enable Hysteresis on PORTF {0...7}"
-config GPIO_HYST_PORTF_8_9
- bool "Enable Hysteresis on PORTF {8, 9}"
-config GPIO_HYST_PORTF_10
- bool "Enable Hysteresis on PORTF 10"
-config GPIO_HYST_PORTF_11
- bool "Enable Hysteresis on PORTF 11"
-config GPIO_HYST_PORTF_12_13
- bool "Enable Hysteresis on PORTF {12, 13}"
-config GPIO_HYST_PORTF_14_15
- bool "Enable Hysteresis on PORTF {14, 15}"
-endmenu
-
-menu "PORT G"
- depends on BFIN_HYSTERESIS_CONTROL
-config GPIO_HYST_PORTG_0
- bool "Enable Hysteresis on PORTG 0"
-config GPIO_HYST_PORTG_1_4
- bool "Enable Hysteresis on PORTG {1...4}"
-config GPIO_HYST_PORTG_5_6
- bool "Enable Hysteresis on PORTG {5, 6}"
-config GPIO_HYST_PORTG_7_8
- bool "Enable Hysteresis on PORTG {7, 8}"
-config GPIO_HYST_PORTG_9
- bool "Enable Hysteresis on PORTG 9"
-config GPIO_HYST_PORTG_10
- bool "Enable Hysteresis on PORTG 10"
-config GPIO_HYST_PORTG_11_13
- bool "Enable Hysteresis on PORTG {11...13}"
-config GPIO_HYST_PORTG_14_15
- bool "Enable Hysteresis on PORTG {14, 15}"
-endmenu
-
-menu "PORT H"
- depends on BFIN_HYSTERESIS_CONTROL
-config GPIO_HYST_PORTH_0_7
- bool "Enable Hysteresis on PORTH {0...7}"
-
-endmenu
-
-menu "None-GPIO"
- depends on BFIN_HYSTERESIS_CONTROL
-config NONEGPIO_HYST_NMI_RST_BMODE
- bool "Enable Hysteresis on {NMI, RESET, BMODE}"
-config NONEGPIO_HYST_JTAG
- bool "Enable Hysteresis on JTAG"
-endmenu
-
-comment "Interrupt Priority Assignment"
-menu "Priority"
-
-config IRQ_PLL_WAKEUP
- int "IRQ_PLL_WAKEUP"
- default 7
-config IRQ_DMA0_ERROR
- int "IRQ_DMA0_ERROR"
- default 7
-config IRQ_DMAR0_BLK
- int "IRQ_DMAR0_BLK"
- default 7
-config IRQ_DMAR1_BLK
- int "IRQ_DMAR1_BLK"
- default 7
-config IRQ_DMAR0_OVR
- int "IRQ_DMAR0_OVR"
- default 7
-config IRQ_DMAR1_OVR
- int "IRQ_DMAR1_OVR"
- default 7
-config IRQ_PPI_ERROR
- int "IRQ_PPI_ERROR"
- default 7
-config IRQ_MAC_ERROR
- int "IRQ_MAC_ERROR"
- default 7
-config IRQ_SPORT0_ERROR
- int "IRQ_SPORT0_ERROR"
- default 7
-config IRQ_SPORT1_ERROR
- int "IRQ_SPORT1_ERROR"
- default 7
-config IRQ_PTP_ERROR
- int "IRQ_PTP_ERROR"
- default 7
-config IRQ_UART0_ERROR
- int "IRQ_UART0_ERROR"
- default 7
-config IRQ_UART1_ERROR
- int "IRQ_UART1_ERROR"
- default 7
-config IRQ_RTC
- int "IRQ_RTC"
- default 8
-config IRQ_PPI
- int "IRQ_PPI"
- default 8
-config IRQ_SPORT0_RX
- int "IRQ_SPORT0_RX"
- default 9
-config IRQ_SPORT0_TX
- int "IRQ_SPORT0_TX"
- default 9
-config IRQ_SPORT1_RX
- int "IRQ_SPORT1_RX"
- default 9
-config IRQ_SPORT1_TX
- int "IRQ_SPORT1_TX"
- default 9
-config IRQ_TWI
- int "IRQ_TWI"
- default 10
-config IRQ_SPI0
- int "IRQ_SPI"
- default 10
-config IRQ_UART0_RX
- int "IRQ_UART0_RX"
- default 10
-config IRQ_UART0_TX
- int "IRQ_UART0_TX"
- default 10
-config IRQ_UART1_RX
- int "IRQ_UART1_RX"
- default 10
-config IRQ_UART1_TX
- int "IRQ_UART1_TX"
- default 10
-config IRQ_OPTSEC
- int "IRQ_OPTSEC"
- default 11
-config IRQ_CNT
- int "IRQ_CNT"
- default 11
-config IRQ_MAC_RX
- int "IRQ_MAC_RX"
- default 11
-config IRQ_PORTH_INTA
- int "IRQ_PORTH_INTA"
- default 11
-config IRQ_MAC_TX
- int "IRQ_MAC_TX/NFC"
- default 11
-config IRQ_PORTH_INTB
- int "IRQ_PORTH_INTB"
- default 11
-config IRQ_TIMER0
- int "IRQ_TIMER0"
- default 7 if TICKSOURCE_GPTMR0
- default 8
-config IRQ_TIMER1
- int "IRQ_TIMER1"
- default 12
-config IRQ_TIMER2
- int "IRQ_TIMER2"
- default 12
-config IRQ_TIMER3
- int "IRQ_TIMER3"
- default 12
-config IRQ_TIMER4
- int "IRQ_TIMER4"
- default 12
-config IRQ_TIMER5
- int "IRQ_TIMER5"
- default 12
-config IRQ_TIMER6
- int "IRQ_TIMER6"
- default 12
-config IRQ_TIMER7
- int "IRQ_TIMER7"
- default 12
-config IRQ_PORTG_INTA
- int "IRQ_PORTG_INTA"
- default 12
-config IRQ_PORTG_INTB
- int "IRQ_PORTG_INTB"
- default 12
-config IRQ_MEM_DMA0
- int "IRQ_MEM_DMA0"
- default 13
-config IRQ_MEM_DMA1
- int "IRQ_MEM_DMA1"
- default 13
-config IRQ_WATCH
- int "IRQ_WATCH"
- default 13
-config IRQ_PORTF_INTA
- int "IRQ_PORTF_INTA"
- default 13
-config IRQ_PORTF_INTB
- int "IRQ_PORTF_INTB"
- default 13
-config IRQ_SPI0_ERROR
- int "IRQ_SPI0_ERROR"
- default 7
-config IRQ_SPI1_ERROR
- int "IRQ_SPI1_ERROR"
- default 7
-config IRQ_RSI_INT0
- int "IRQ_RSI_INT0"
- default 7
-config IRQ_RSI_INT1
- int "IRQ_RSI_INT1"
- default 7
-config IRQ_PWM_TRIP
- int "IRQ_PWM_TRIP"
- default 10
-config IRQ_PWM_SYNC
- int "IRQ_PWM_SYNC"
- default 10
-config IRQ_PTP_STAT
- int "IRQ_PTP_STAT"
- default 10
-
- help
- Enter the priority numbers between 7-13 ONLY. Others are Reserved.
- This applies to all the above. It is not recommended to assign the
- highest priority number 7 to UART or any other device.
-
-endmenu
-
-endmenu
-
-endif
+++ /dev/null
-#
-# arch/blackfin/mach-bf518/Makefile
-#
-
-obj-y := ints-priority.o dma.o
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0
-choice
- prompt "System type"
- default BFIN518F_EZBRD
- help
- Select your board!
-
-config BFIN518F_EZBRD
- bool "BF518F-EZBRD"
- help
- BF518-EZBRD board support.
-
-config BFIN518F_TCM
- bool "Bluetechnix TCM-BF518"
- help
- Bluetechnix TCM-BF518 board support.
-
-endchoice
+++ /dev/null
-#
-# arch/blackfin/mach-bf518/boards/Makefile
-#
-
-obj-$(CONFIG_BFIN518F_EZBRD) += ezbrd.o
-obj-$(CONFIG_BFIN518F_TCM) += tcm-bf518.o
+++ /dev/null
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/export.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-
-#include <linux/i2c.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/reboot.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-#include <asm/bfin_sdh.h>
-#include <linux/spi/ad7877.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "ADI BF518F-EZBRD";
-
-/*
- * Driver needs to know address, irq and flag pin.
- */
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
-static struct mtd_partition ezbrd_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x40000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0x1C0000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct physmap_flash_data ezbrd_flash_data = {
- .width = 2,
- .parts = ezbrd_partitions,
- .nr_parts = ARRAY_SIZE(ezbrd_partitions),
-};
-
-static struct resource ezbrd_flash_resource = {
- .start = 0x20000000,
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- .end = 0x202fffff,
-#else
- .end = 0x203fffff,
-#endif
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device ezbrd_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &ezbrd_flash_data,
- },
- .num_resources = 1,
- .resource = &ezbrd_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
-#include <linux/bfin_mac.h>
-static const unsigned short bfin_mac_peripherals[] = {
- P_MII0_ETxD0,
- P_MII0_ETxD1,
- P_MII0_ETxEN,
- P_MII0_ERxD0,
- P_MII0_ERxD1,
- P_MII0_TxCLK,
- P_MII0_PHYINT,
- P_MII0_CRS,
- P_MII0_MDC,
- P_MII0_MDIO,
- 0
-};
-
-static struct bfin_phydev_platform_data bfin_phydev_data[] = {
- {
- .addr = 1,
- .irq = IRQ_MAC_PHYINT,
- },
-};
-
-static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
- .phydev_number = 1,
- .phydev_data = bfin_phydev_data,
- .phy_mode = PHY_INTERFACE_MODE_MII,
- .mac_peripherals = bfin_mac_peripherals,
- .vlan1_mask = 1,
- .vlan2_mask = 2,
-};
-
-static struct platform_device bfin_mii_bus = {
- .name = "bfin_mii_bus",
- .dev = {
- .platform_data = &bfin_mii_bus_data,
- }
-};
-
-static struct platform_device bfin_mac_device = {
- .name = "bfin_mac",
- .dev = {
- .platform_data = &bfin_mii_bus,
- }
-};
-
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00040000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p16",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
-static const struct ad7877_platform_data bfin_ad7877_ts_info = {
- .model = 7877,
- .vref_delay_usecs = 50, /* internal, no capacitor */
- .x_plate_ohms = 419,
- .y_plate_ohms = 486,
- .pressure_max = 1000,
- .pressure_min = 0,
- .stopacq_polarity = 1,
- .first_conversion_delay = 3,
- .acquisition_time = 1,
- .averaging = 1,
- .pen_down_acc_interval = 1,
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 2, /* On BF518F-EZBRD it's SPI0_SSEL2 */
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
- {
- .modalias = "ad7877",
- .platform_data = &bfin_ad7877_ts_info,
- .irq = IRQ_PF8,
- .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 2,
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_WM8731) \
- && defined(CONFIG_SND_SOC_WM8731_SPI)
- {
- .modalias = "wm8731",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5,
- .mode = SPI_MODE_0,
- },
-#endif
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- },
-#endif
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
- {
- .modalias = "bfin-lq035q1-spi",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- .mode = SPI_CPHA | SPI_CPOL,
- },
-#endif
-};
-
-/* SPI controller data */
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* SPI (0) */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 6,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI0,
- .end = CH_SPI0,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI0,
- .end = IRQ_SPI0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-
-/* SPI (1) */
-static struct bfin5xx_spi_master bfin_spi1_info = {
- .num_chipselect = 6,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
-};
-
-static struct resource bfin_spi1_resource[] = {
- [0] = {
- .start = SPI1_REGBASE,
- .end = SPI1_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI1,
- .end = CH_SPI1,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI1,
- .end = IRQ_SPI1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_spi1_device = {
- .name = "bfin-spi",
- .id = 1, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi1_resource),
- .resource = bfin_spi1_resource,
- .dev = {
- .platform_data = &bfin_spi1_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_THR,
- .end = UART0_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_THR,
- .end = UART1_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX, 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
-static struct platform_device bfin_i2s = {
- .name = "bfin-i2s",
- .id = CONFIG_SND_BF5XX_SPORT_NUM,
- /* TODO: add platform data here */
-};
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_REGBASE,
- .end = TWI0_REGBASE,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI,
- .end = IRQ_TWI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-#endif
-
-static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
-#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
- {
- I2C_BOARD_INFO("pcf8574_lcd", 0x22),
- },
-#endif
-#if IS_ENABLED(CONFIG_INPUT_PCF8574)
- {
- I2C_BOARD_INFO("pcf8574_keypad", 0x27),
- .irq = IRQ_PF8,
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_SSM2602)
- {
- I2C_BOARD_INFO("ssm2602", 0x1b),
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
-#include <linux/input.h>
-#include <linux/gpio_keys.h>
-
-static struct gpio_keys_button bfin_gpio_keys_table[] = {
- {BTN_0, GPIO_PG0, 1, "gpio-keys: BTN0"},
- {BTN_1, GPIO_PG13, 1, "gpio-keys: BTN1"},
-};
-
-static struct gpio_keys_platform_data bfin_gpio_keys_data = {
- .buttons = bfin_gpio_keys_table,
- .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
-};
-
-static struct platform_device bfin_device_gpiokeys = {
- .name = "gpio-keys",
- .dev = {
- .platform_data = &bfin_gpio_keys_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SDH_BFIN)
-
-static struct bfin_sd_host bfin_sdh_data = {
- .dma_chan = CH_RSI,
- .irq_int0 = IRQ_RSI_INT0,
- .pin_req = {P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0},
-};
-
-static struct platform_device bf51x_sdh_device = {
- .name = "bfin-sdh",
- .id = 0,
- .dev = {
- .platform_data = &bfin_sdh_data,
- },
-};
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
- VRPAIR(VLEV_100, 400000000),
- VRPAIR(VLEV_105, 426000000),
- VRPAIR(VLEV_110, 500000000),
- VRPAIR(VLEV_115, 533000000),
- VRPAIR(VLEV_120, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-static struct platform_device *stamp_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
- &bfin_mii_bus,
- &bfin_mac_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
- &bfin_spi1_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
- &bfin_i2s,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
- &bfin_device_gpiokeys,
-#endif
-
-#if IS_ENABLED(CONFIG_SDH_BFIN)
- &bf51x_sdh_device,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
- &ezbrd_flash_device,
-#endif
-};
-
-static int __init ezbrd_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- i2c_register_board_info(0, bfin_i2c_board_info,
- ARRAY_SIZE(bfin_i2c_board_info));
- platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
- /* setup BF518-EZBRD GPIO pin PG11 to AMS2, PG15 to AMS3. */
- peripheral_request(P_AMS2, "ParaFlash");
-#if !IS_ENABLED(CONFIG_SPI_BFIN5XX)
- peripheral_request(P_AMS3, "ParaFlash");
-#endif
- return 0;
-}
-
-arch_initcall(ezbrd_init);
-
-static struct platform_device *ezbrd_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(ezbrd_early_devices,
- ARRAY_SIZE(ezbrd_early_devices));
-}
-
-void native_machine_restart(char *cmd)
-{
- /* workaround reboot hang when booting from SPI */
- if ((bfin_read_SYSCR() & 0x7) == 0x3)
- bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
-}
-
-int bfin_get_ether_addr(char *addr)
-{
- /* the MAC is stored in OTP memory page 0xDF */
- u32 ret;
- u64 otp_mac;
- u32 (*otp_read)(u32 page, u32 flags, u64 *page_content) = (void *)0xEF00001A;
-
- ret = otp_read(0xDF, 0x00, &otp_mac);
- if (!(ret & 0x1)) {
- char *otp_mac_p = (char *)&otp_mac;
- for (ret = 0; ret < 6; ++ret)
- addr[ret] = otp_mac_p[5 - ret];
- }
- return 0;
-}
-EXPORT_SYMBOL(bfin_get_ether_addr);
+++ /dev/null
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/etherdevice.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-
-#include <linux/i2c.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/reboot.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-#include <asm/bfin_sdh.h>
-#include <linux/spi/ad7877.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "Bluetechnix TCM-BF518";
-
-/*
- * Driver needs to know address, irq and flag pin.
- */
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
-static struct mtd_partition tcm_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x40000,
- .offset = 0,
- },
- {
- .name = "linux(nor)",
- .size = 0x1C0000,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct physmap_flash_data tcm_flash_data = {
- .width = 2,
- .parts = tcm_partitions,
- .nr_parts = ARRAY_SIZE(tcm_partitions),
-};
-
-static struct resource tcm_flash_resource = {
- .start = 0x20000000,
- .end = 0x201fffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device tcm_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &tcm_flash_data,
- },
- .num_resources = 1,
- .resource = &tcm_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
-#include <linux/bfin_mac.h>
-static const unsigned short bfin_mac_peripherals[] = P_MII0;
-
-static struct bfin_phydev_platform_data bfin_phydev_data[] = {
- {
- .addr = 1,
- .irq = IRQ_MAC_PHYINT,
- },
-};
-
-static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
- .phydev_number = 1,
- .phydev_data = bfin_phydev_data,
- .phy_mode = PHY_INTERFACE_MODE_MII,
- .mac_peripherals = bfin_mac_peripherals,
-};
-
-static struct platform_device bfin_mii_bus = {
- .name = "bfin_mii_bus",
- .dev = {
- .platform_data = &bfin_mii_bus_data,
- }
-};
-
-static struct platform_device bfin_mac_device = {
- .name = "bfin_mac",
- .dev = {
- .platform_data = &bfin_mii_bus,
- }
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00040000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p16",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
-static const struct ad7877_platform_data bfin_ad7877_ts_info = {
- .model = 7877,
- .vref_delay_usecs = 50, /* internal, no capacitor */
- .x_plate_ohms = 419,
- .y_plate_ohms = 486,
- .pressure_max = 1000,
- .pressure_min = 0,
- .stopacq_polarity = 1,
- .first_conversion_delay = 3,
- .acquisition_time = 1,
- .averaging = 1,
- .pen_down_acc_interval = 1,
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 2, /* SPI0_SSEL2 */
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
- {
- .modalias = "ad7877",
- .platform_data = &bfin_ad7877_ts_info,
- .irq = IRQ_PF8,
- .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 2,
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_WM8731) \
- && defined(CONFIG_SND_SOC_WM8731_SPI)
- {
- .modalias = "wm8731",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5,
- .mode = SPI_MODE_0,
- },
-#endif
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- },
-#endif
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
- {
- .modalias = "bfin-lq035q1-spi",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- .mode = SPI_CPHA | SPI_CPOL,
- },
-#endif
-};
-
-/* SPI controller data */
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* SPI (0) */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 6,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI0,
- .end = CH_SPI0,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI0,
- .end = IRQ_SPI0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-
-/* SPI (1) */
-static struct bfin5xx_spi_master bfin_spi1_info = {
- .num_chipselect = 6,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
-};
-
-static struct resource bfin_spi1_resource[] = {
- [0] = {
- .start = SPI1_REGBASE,
- .end = SPI1_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI1,
- .end = CH_SPI1,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI1,
- .end = IRQ_SPI1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_spi1_device = {
- .name = "bfin-spi",
- .id = 1, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi1_resource),
- .resource = bfin_spi1_resource,
- .dev = {
- .platform_data = &bfin_spi1_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_THR,
- .end = UART0_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_THR,
- .end = UART1_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX, 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_REGBASE,
- .end = TWI0_REGBASE,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI,
- .end = IRQ_TWI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-#endif
-
-static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
-#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
- {
- I2C_BOARD_INFO("pcf8574_lcd", 0x22),
- },
-#endif
-#if IS_ENABLED(CONFIG_INPUT_PCF8574)
- {
- I2C_BOARD_INFO("pcf8574_keypad", 0x27),
- .irq = IRQ_PF8,
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
-#include <linux/input.h>
-#include <linux/gpio_keys.h>
-
-static struct gpio_keys_button bfin_gpio_keys_table[] = {
- {BTN_0, GPIO_PG0, 1, "gpio-keys: BTN0"},
- {BTN_1, GPIO_PG13, 1, "gpio-keys: BTN1"},
-};
-
-static struct gpio_keys_platform_data bfin_gpio_keys_data = {
- .buttons = bfin_gpio_keys_table,
- .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
-};
-
-static struct platform_device bfin_device_gpiokeys = {
- .name = "gpio-keys",
- .dev = {
- .platform_data = &bfin_gpio_keys_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SDH_BFIN)
-
-static struct bfin_sd_host bfin_sdh_data = {
- .dma_chan = CH_RSI,
- .irq_int0 = IRQ_RSI_INT0,
- .pin_req = {P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0},
-};
-
-static struct platform_device bf51x_sdh_device = {
- .name = "bfin-sdh",
- .id = 0,
- .dev = {
- .platform_data = &bfin_sdh_data,
- },
-};
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
- VRPAIR(VLEV_100, 400000000),
- VRPAIR(VLEV_105, 426000000),
- VRPAIR(VLEV_110, 500000000),
- VRPAIR(VLEV_115, 533000000),
- VRPAIR(VLEV_120, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-static struct platform_device *tcm_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
- &bfin_mii_bus,
- &bfin_mac_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
- &bfin_spi1_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
- &bfin_device_gpiokeys,
-#endif
-
-#if IS_ENABLED(CONFIG_SDH_BFIN)
- &bf51x_sdh_device,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
- &tcm_flash_device,
-#endif
-};
-
-static int __init tcm_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- i2c_register_board_info(0, bfin_i2c_board_info,
- ARRAY_SIZE(bfin_i2c_board_info));
- platform_add_devices(tcm_devices, ARRAY_SIZE(tcm_devices));
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
- return 0;
-}
-
-arch_initcall(tcm_init);
-
-static struct platform_device *tcm_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(tcm_early_devices,
- ARRAY_SIZE(tcm_early_devices));
-}
-
-void native_machine_restart(char *cmd)
-{
- /* workaround reboot hang when booting from SPI */
- if ((bfin_read_SYSCR() & 0x7) == 0x3)
- bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
-}
-
-int bfin_get_ether_addr(char *addr)
-{
- return 1;
-}
-EXPORT_SYMBOL(bfin_get_ether_addr);
+++ /dev/null
-/*
- * the simple DMA Implementation for Blackfin
- *
- * Copyright 2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-
-#include <asm/blackfin.h>
-#include <asm/dma.h>
-
-struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
- (struct dma_register *) DMA0_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_NEXT_DESC_PTR,
- (struct dma_register *) DMA3_NEXT_DESC_PTR,
- (struct dma_register *) DMA4_NEXT_DESC_PTR,
- (struct dma_register *) DMA5_NEXT_DESC_PTR,
- (struct dma_register *) DMA6_NEXT_DESC_PTR,
- (struct dma_register *) DMA7_NEXT_DESC_PTR,
- (struct dma_register *) DMA8_NEXT_DESC_PTR,
- (struct dma_register *) DMA9_NEXT_DESC_PTR,
- (struct dma_register *) DMA10_NEXT_DESC_PTR,
- (struct dma_register *) DMA11_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
-};
-EXPORT_SYMBOL(dma_io_base_addr);
-
-int channel2irq(unsigned int channel)
-{
- int ret_irq = -1;
-
- switch (channel) {
- case CH_PPI:
- ret_irq = IRQ_PPI;
- break;
-
- case CH_EMAC_RX:
- ret_irq = IRQ_MAC_RX;
- break;
-
- case CH_EMAC_TX:
- ret_irq = IRQ_MAC_TX;
- break;
-
- case CH_UART1_RX:
- ret_irq = IRQ_UART1_RX;
- break;
-
- case CH_UART1_TX:
- ret_irq = IRQ_UART1_TX;
- break;
-
- case CH_SPORT0_RX:
- ret_irq = IRQ_SPORT0_RX;
- break;
-
- case CH_SPORT0_TX:
- ret_irq = IRQ_SPORT0_TX;
- break;
-
- case CH_SPORT1_RX:
- ret_irq = IRQ_SPORT1_RX;
- break;
-
- case CH_SPORT1_TX:
- ret_irq = IRQ_SPORT1_TX;
- break;
-
- case CH_SPI0:
- ret_irq = IRQ_SPI0;
- break;
-
- case CH_UART0_RX:
- ret_irq = IRQ_UART0_RX;
- break;
-
- case CH_UART0_TX:
- ret_irq = IRQ_UART0_TX;
- break;
-
- case CH_MEM_STREAM0_SRC:
- case CH_MEM_STREAM0_DEST:
- ret_irq = IRQ_MEM_DMA0;
- break;
-
- case CH_MEM_STREAM1_SRC:
- case CH_MEM_STREAM1_DEST:
- ret_irq = IRQ_MEM_DMA1;
- break;
- }
- return ret_irq;
-}
+++ /dev/null
-/*
- * DO NOT EDIT THIS FILE
- * This file is under version control at
- * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
- * and can be replaced with that version at any time
- * DO NOT EDIT THIS FILE
- *
- * Copyright 2004-2011 Analog Devices Inc.
- * Licensed under the Clear BSD license.
- */
-
-/* This file should be up to date with:
- * - Revision F, 05/23/2011; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List
- */
-
-#if __SILICON_REVISION__ < 0
-# error will not work on BF518 silicon version
-#endif
-
-#ifndef _MACH_ANOMALY_H_
-#define _MACH_ANOMALY_H_
-
-/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
-#define ANOMALY_05000074 (1)
-/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
-#define ANOMALY_05000119 (1)
-/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
-#define ANOMALY_05000122 (1)
-/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
-#define ANOMALY_05000245 (1)
-/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
-#define ANOMALY_05000254 (1)
-/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
-#define ANOMALY_05000265 (1)
-/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
-#define ANOMALY_05000310 (1)
-/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
-#define ANOMALY_05000366 (1)
-/* Lockbox SESR Firmware Does Not Save/Restore Full Context */
-#define ANOMALY_05000405 (1)
-/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
-#define ANOMALY_05000408 (1)
-/* Speculative Fetches Can Cause Undesired External FIFO Operations */
-#define ANOMALY_05000416 (1)
-/* TWI Fall Time (Tof) May Violate the Minimum I2C Specification */
-#define ANOMALY_05000421 (1)
-/* TWI Input Capacitance (Ci) May Violate the Maximum I2C Specification */
-#define ANOMALY_05000422 (1)
-/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
-#define ANOMALY_05000426 (1)
-/* Software System Reset Corrupts PLL_LOCKCNT Register */
-#define ANOMALY_05000430 (__SILICON_REVISION__ < 1)
-/* Incorrect Use of Stack in Lockbox Firmware During Authentication */
-#define ANOMALY_05000431 (1)
-/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */
-#define ANOMALY_05000434 (1)
-/* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */
-#define ANOMALY_05000435 (__SILICON_REVISION__ < 1)
-/* PORTx_DRIVE and PORTx_HYSTERESIS Registers Read Back Incorrect Values */
-#define ANOMALY_05000438 (__SILICON_REVISION__ < 1)
-/* Preboot Cannot be Used to Alter the PLL_DIV Register */
-#define ANOMALY_05000439 (__SILICON_REVISION__ < 1)
-/* bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register */
-#define ANOMALY_05000440 (__SILICON_REVISION__ < 1)
-/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
-#define ANOMALY_05000443 (1)
-/* Incorrect L1 Instruction Bank B Memory Map Location */
-#define ANOMALY_05000444 (__SILICON_REVISION__ < 1)
-/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
-#define ANOMALY_05000452 (__SILICON_REVISION__ < 1)
-/* PWM_TRIPB Signal Not Available on PG10 */
-#define ANOMALY_05000453 (__SILICON_REVISION__ < 1)
-/* PPI_FS3 is Driven One Half Cycle Later Than PPI Data */
-#define ANOMALY_05000455 (__SILICON_REVISION__ < 1)
-/* False Hardware Error when RETI Points to Invalid Memory */
-#define ANOMALY_05000461 (1)
-/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
-#define ANOMALY_05000462 (__SILICON_REVISION__ < 2)
-/* Incorrect Default MSEL Value in PLL_CTL */
-#define ANOMALY_05000472 (__SILICON_REVISION__ < 2)
-/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
-#define ANOMALY_05000473 (1)
-/* TESTSET Instruction Cannot Be Interrupted */
-#define ANOMALY_05000477 (1)
-/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
-#define ANOMALY_05000481 (1)
-/* PLL Latches Incorrect Settings During Reset */
-#define ANOMALY_05000482 (__SILICON_REVISION__ < 2)
-/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
-#define ANOMALY_05000485 (__SILICON_REVISION__ < 2)
-/* SPI Master Boot Can Fail Under Certain Conditions */
-#define ANOMALY_05000490 (1)
-/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
-#define ANOMALY_05000491 (1)
-/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
-#define ANOMALY_05000494 (1)
-/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */
-#define ANOMALY_05000498 (1)
-/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
-#define ANOMALY_05000501 (1)
-
-/* Anomalies that don't exist on this proc */
-#define ANOMALY_05000099 (0)
-#define ANOMALY_05000120 (0)
-#define ANOMALY_05000125 (0)
-#define ANOMALY_05000149 (0)
-#define ANOMALY_05000158 (0)
-#define ANOMALY_05000171 (0)
-#define ANOMALY_05000179 (0)
-#define ANOMALY_05000182 (0)
-#define ANOMALY_05000183 (0)
-#define ANOMALY_05000189 (0)
-#define ANOMALY_05000198 (0)
-#define ANOMALY_05000202 (0)
-#define ANOMALY_05000215 (0)
-#define ANOMALY_05000219 (0)
-#define ANOMALY_05000220 (0)
-#define ANOMALY_05000227 (0)
-#define ANOMALY_05000230 (0)
-#define ANOMALY_05000231 (0)
-#define ANOMALY_05000233 (0)
-#define ANOMALY_05000234 (0)
-#define ANOMALY_05000242 (0)
-#define ANOMALY_05000244 (0)
-#define ANOMALY_05000248 (0)
-#define ANOMALY_05000250 (0)
-#define ANOMALY_05000257 (0)
-#define ANOMALY_05000261 (0)
-#define ANOMALY_05000263 (0)
-#define ANOMALY_05000266 (0)
-#define ANOMALY_05000273 (0)
-#define ANOMALY_05000274 (0)
-#define ANOMALY_05000278 (0)
-#define ANOMALY_05000281 (0)
-#define ANOMALY_05000283 (0)
-#define ANOMALY_05000285 (0)
-#define ANOMALY_05000287 (0)
-#define ANOMALY_05000301 (0)
-#define ANOMALY_05000305 (0)
-#define ANOMALY_05000307 (0)
-#define ANOMALY_05000311 (0)
-#define ANOMALY_05000312 (0)
-#define ANOMALY_05000315 (0)
-#define ANOMALY_05000323 (0)
-#define ANOMALY_05000353 (0)
-#define ANOMALY_05000357 (0)
-#define ANOMALY_05000362 (1)
-#define ANOMALY_05000363 (0)
-#define ANOMALY_05000364 (0)
-#define ANOMALY_05000371 (0)
-#define ANOMALY_05000380 (0)
-#define ANOMALY_05000383 (0)
-#define ANOMALY_05000386 (0)
-#define ANOMALY_05000389 (0)
-#define ANOMALY_05000400 (0)
-#define ANOMALY_05000402 (0)
-#define ANOMALY_05000412 (0)
-#define ANOMALY_05000432 (0)
-#define ANOMALY_05000447 (0)
-#define ANOMALY_05000448 (0)
-#define ANOMALY_05000456 (0)
-#define ANOMALY_05000450 (0)
-#define ANOMALY_05000465 (0)
-#define ANOMALY_05000467 (0)
-#define ANOMALY_05000474 (0)
-#define ANOMALY_05000475 (0)
-#define ANOMALY_05000480 (0)
-#define ANOMALY_16000030 (0)
-
-#endif
+++ /dev/null
-/*
- * Copyright 2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __MACH_BF518_H__
-#define __MACH_BF518_H__
-
-#define OFFSET_(x) ((x) & 0x0000FFFF)
-
-/*some misc defines*/
-#define IMASK_IVG15 0x8000
-#define IMASK_IVG14 0x4000
-#define IMASK_IVG13 0x2000
-#define IMASK_IVG12 0x1000
-
-#define IMASK_IVG11 0x0800
-#define IMASK_IVG10 0x0400
-#define IMASK_IVG9 0x0200
-#define IMASK_IVG8 0x0100
-
-#define IMASK_IVG7 0x0080
-#define IMASK_IVGTMR 0x0040
-#define IMASK_IVGHW 0x0020
-
-/***************************/
-
-#define BFIN_DSUBBANKS 4
-#define BFIN_DWAYS 2
-#define BFIN_DLINES 64
-#define BFIN_ISUBBANKS 4
-#define BFIN_IWAYS 4
-#define BFIN_ILINES 32
-
-#define WAY0_L 0x1
-#define WAY1_L 0x2
-#define WAY01_L 0x3
-#define WAY2_L 0x4
-#define WAY02_L 0x5
-#define WAY12_L 0x6
-#define WAY012_L 0x7
-
-#define WAY3_L 0x8
-#define WAY03_L 0x9
-#define WAY13_L 0xA
-#define WAY013_L 0xB
-
-#define WAY32_L 0xC
-#define WAY320_L 0xD
-#define WAY321_L 0xE
-#define WAYALL_L 0xF
-
-#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
-
-/********************************* EBIU Settings ************************************/
-#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
-#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
-
-#ifdef CONFIG_C_AMBEN_ALL
-#define V_AMBEN AMBEN_ALL
-#endif
-#ifdef CONFIG_C_AMBEN
-#define V_AMBEN 0x0
-#endif
-#ifdef CONFIG_C_AMBEN_B0
-#define V_AMBEN AMBEN_B0
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1
-#define V_AMBEN AMBEN_B0_B1
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1_B2
-#define V_AMBEN AMBEN_B0_B1_B2
-#endif
-#ifdef CONFIG_C_AMCKEN
-#define V_AMCKEN AMCKEN
-#else
-#define V_AMCKEN 0x0
-#endif
-#ifdef CONFIG_C_CDPRIO
-#define V_CDPRIO 0x100
-#else
-#define V_CDPRIO 0x0
-#endif
-
-#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO)
-
-/**************************** Hysteresis Settings ****************************/
-
-#ifdef CONFIG_BFIN_HYSTERESIS_CONTROL
-#ifdef CONFIG_GPIO_HYST_PORTF_0_7
-#define HYST_PORTF_0_7 (1 << 0)
-#else
-#define HYST_PORTF_0_7 (0 << 0)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTF_8_9
-#define HYST_PORTF_8_9 (1 << 2)
-#else
-#define HYST_PORTF_8_9 (0 << 2)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTF_10
-#define HYST_PORTF_10 (1 << 4)
-#else
-#define HYST_PORTF_10 (0 << 4)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTF_11
-#define HYST_PORTF_11 (1 << 6)
-#else
-#define HYST_PORTF_11 (0 << 6)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTF_12_13
-#define HYST_PORTF_12_13 (1 << 8)
-#else
-#define HYST_PORTF_12_13 (0 << 8)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTF_14_15
-#define HYST_PORTF_14_15 (1 << 10)
-#else
-#define HYST_PORTF_14_15 (0 << 10)
-#endif
-
-#define HYST_PORTF_0_15 (HYST_PORTF_0_7 | HYST_PORTF_8_9 | HYST_PORTF_10 | \
- HYST_PORTF_11 | HYST_PORTF_12_13 | HYST_PORTF_14_15)
-
-#ifdef CONFIG_GPIO_HYST_PORTG_0
-#define HYST_PORTG_0 (1 << 0)
-#else
-#define HYST_PORTG_0 (0 << 0)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTG_1_4
-#define HYST_PORTG_1_4 (1 << 2)
-#else
-#define HYST_PORTG_1_4 (0 << 2)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTG_5_6
-#define HYST_PORTG_5_6 (1 << 4)
-#else
-#define HYST_PORTG_5_6 (0 << 4)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTG_7_8
-#define HYST_PORTG_7_8 (1 << 6)
-#else
-#define HYST_PORTG_7_8 (0 << 6)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTG_9
-#define HYST_PORTG_9 (1 << 8)
-#else
-#define HYST_PORTG_9 (0 << 8)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTG_10
-#define HYST_PORTG_10 (1 << 10)
-#else
-#define HYST_PORTG_10 (0 << 10)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTG_11_13
-#define HYST_PORTG_11_13 (1 << 12)
-#else
-#define HYST_PORTG_11_13 (0 << 12)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTG_14_15
-#define HYST_PORTG_14_15 (1 << 14)
-#else
-#define HYST_PORTG_14_15 (0 << 14)
-#endif
-
-#define HYST_PORTG_0_15 (HYST_PORTG_0 | HYST_PORTG_1_4 | HYST_PORTG_5_6 | \
- HYST_PORTG_7_8 | HYST_PORTG_9 | HYST_PORTG_10 | \
- HYST_PORTG_11_13 | HYST_PORTG_14_15)
-
-#ifdef CONFIG_GPIO_HYST_PORTH_0_7
-#define HYST_PORTH_0_7 (1 << 0)
-#else
-#define HYST_PORTH_0_7 (0 << 0)
-#endif
-
-#define HYST_PORTH_0_15 (HYST_PORTH_0_7)
-
-#ifdef CONFIG_NONEGPIO_HYST_NMI_RST_BMODE
-#define HYST_NMI_RST_BMODE (1 << 2)
-#else
-#define HYST_NMI_RST_BMODE (0 << 2)
-#endif
-#ifdef CONFIG_NONEGPIO_HYST_JTAG
-#define HYST_JTAG (1 << 4)
-#else
-#define HYST_JTAG (0 << 4)
-#endif
-
-#define HYST_NONEGPIO (HYST_NMI_RST_BMODE | HYST_JTAG)
-#define HYST_NONEGPIO_MASK (0x3C)
-#endif /* CONFIG_BFIN_HYSTERESIS_CONTROL */
-
-#ifdef CONFIG_BF518
-#define CPU "BF518"
-#define CPUID 0x27e8
-#endif
-#ifdef CONFIG_BF516
-#define CPU "BF516"
-#define CPUID 0x27e8
-#endif
-#ifdef CONFIG_BF514
-#define CPU "BF514"
-#define CPUID 0x27e8
-#endif
-#ifdef CONFIG_BF512
-#define CPU "BF512"
-#define CPUID 0x27e8
-#endif
-
-#ifndef CPU
-#error "Unknown CPU type - This kernel doesn't seem to be configured properly"
-#endif
-
-#endif /* __MACH_BF518_H__ */
+++ /dev/null
-/*
- * mach/bfin_serial.h - Blackfin UART/Serial definitions
- *
- * Copyright 2006-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MACH_SERIAL_H__
-#define __BFIN_MACH_SERIAL_H__
-
-#define BFIN_UART_NR_PORTS 2
-
-#endif
+++ /dev/null
-/*
- * Copyright 2008-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_BLACKFIN_H_
-#define _MACH_BLACKFIN_H_
-
-#include "bf518.h"
-#include "anomaly.h"
-
-#include <asm/def_LPBlackfin.h>
-#ifdef CONFIG_BF512
-# include "defBF512.h"
-#endif
-#ifdef CONFIG_BF514
-# include "defBF514.h"
-#endif
-#ifdef CONFIG_BF516
-# include "defBF516.h"
-#endif
-#ifdef CONFIG_BF518
-# include "defBF518.h"
-#endif
-
-#ifndef __ASSEMBLY__
-# include <asm/cdef_LPBlackfin.h>
-# ifdef CONFIG_BF512
-# include "cdefBF512.h"
-# endif
-# ifdef CONFIG_BF514
-# include "cdefBF514.h"
-# endif
-# ifdef CONFIG_BF516
-# include "cdefBF516.h"
-# endif
-# ifdef CONFIG_BF518
-# include "cdefBF518.h"
-# endif
-#endif
-
-#endif
+++ /dev/null
-/*
- * Copyright 2008-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _CDEF_BF512_H
-#define _CDEF_BF512_H
-
-/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
-#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
-#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
-#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
-#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
-#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
-#define bfin_read_CHIPID() bfin_read32(CHIPID)
-#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
-
-
-/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
-#define bfin_read_SWRST() bfin_read16(SWRST)
-#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
-#define bfin_read_SYSCR() bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
-
-#define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT)
-#define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val)
-#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
-#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
-#define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + (x << 6))
-#define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 6)), val)
-
-#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
-#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
-#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
-#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val)
-#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
-#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val)
-#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
-#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val)
-
-#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
-#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
-#define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + (x << 6))
-#define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 6)), val)
-
-#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
-#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
-#define bfin_read_SIC_IWR(x) bfin_read32(SIC_IWR0 + (x << 6))
-#define bfin_write_SIC_IWR(x, val) bfin_write32((SIC_IWR0 + (x << 6)), val)
-
-/* SIC Additions to ADSP-BF51x (0xFFC0014C - 0xFFC00162) */
-
-#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)
-#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val)
-#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4)
-#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val)
-#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5)
-#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val)
-#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6)
-#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val)
-#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7)
-#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val)
-#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
-#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
-#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
-#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val)
-
-/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
-#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
-#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
-#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
-
-
-/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
-#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
-#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val)
-#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
-#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val)
-#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
-#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val)
-#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
-#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val)
-#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
-#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val)
-#define bfin_read_RTC_FAST() bfin_read16(RTC_FAST)
-#define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST, val)
-#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
-#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val)
-
-
-/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
-#define bfin_read_UART0_THR() bfin_read16(UART0_THR)
-#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val)
-#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR)
-#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val)
-#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL)
-#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val)
-#define bfin_read_UART0_IER() bfin_read16(UART0_IER)
-#define bfin_write_UART0_IER(val) bfin_write16(UART0_IER, val)
-#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH)
-#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val)
-#define bfin_read_UART0_IIR() bfin_read16(UART0_IIR)
-#define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR, val)
-#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR)
-#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val)
-#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR)
-#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val)
-#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR)
-#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val)
-#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR)
-#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val)
-#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR)
-#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val)
-#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL)
-#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val)
-
-
-/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
-#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
-#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
-#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
-
-#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
-#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
-#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
-
-#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
-#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
-#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
-
-#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
-#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val)
-#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
-#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
-#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
-#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val)
-#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
-#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val)
-
-#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
-#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val)
-#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
-#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
-#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
-#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val)
-#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
-#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val)
-
-#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
-#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val)
-#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
-#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
-#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
-#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val)
-#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
-#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val)
-
-#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
-#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val)
-#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
-#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
-#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
-#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val)
-#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
-#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val)
-
-#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
-#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val)
-#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
-#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
-#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
-#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val)
-#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
-#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val)
-
-#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE)
-#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val)
-#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE)
-#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val)
-#define bfin_read_TIMER_STATUS() bfin_read32(TIMER_STATUS)
-#define bfin_write_TIMER_STATUS(val) bfin_write32(TIMER_STATUS, val)
-
-
-/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
-#define bfin_read_PORTFIO() bfin_read16(PORTFIO)
-#define bfin_write_PORTFIO(val) bfin_write16(PORTFIO, val)
-#define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR)
-#define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR, val)
-#define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET)
-#define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET, val)
-#define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE)
-#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val)
-#define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA)
-#define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA, val)
-#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR)
-#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val)
-#define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET)
-#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val)
-#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE)
-#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB)
-#define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB, val)
-#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR)
-#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val)
-#define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET)
-#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val)
-#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE)
-#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR)
-#define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR, val)
-#define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR)
-#define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR, val)
-#define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE)
-#define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE, val)
-#define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH)
-#define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH, val)
-#define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN)
-#define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN, val)
-
-
-/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
-#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
-#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
-#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
-#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
-#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
-#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX, val)
-#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX)
-#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX)
-#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX, val)
-#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
-#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
-#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
-#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
-#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
-#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
-#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
-#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
-#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
-#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
-#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
-#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
-#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
-#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
-#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
-#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
-
-
-/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
-#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val)
-#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val)
-#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
-#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
-#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
-#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
-#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX, val)
-#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX, val)
-#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX)
-#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX, val)
-#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX)
-#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX, val)
-#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
-#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val)
-#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
-#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val)
-#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val)
-#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val)
-#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val)
-#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val)
-#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
-#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val)
-#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
-#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val)
-#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
-#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val)
-#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
-#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val)
-#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
-#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val)
-#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
-#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val)
-#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
-#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val)
-#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
-#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val)
-
-
-/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
-#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val)
-#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
-#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
-#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
-#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val)
-#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL)
-#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val)
-#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
-#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val)
-#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
-#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val)
-
-
-/* DMA Traffic Control Registers */
-#define bfin_read_DMAC_TC_PER() bfin_read16(DMAC_TC_PER)
-#define bfin_write_DMAC_TC_PER(val) bfin_write16(DMAC_TC_PER, val)
-#define bfin_read_DMAC_TC_CNT() bfin_read16(DMAC_TC_CNT)
-#define bfin_write_DMAC_TC_CNT(val) bfin_write16(DMAC_TC_CNT, val)
-
-/* DMA Controller */
-#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
-#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val)
-#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val)
-#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val)
-#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
-#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val)
-#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
-#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val)
-#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val)
-#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val)
-#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val)
-#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val)
-#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
-#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
-#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
-#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
-#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
-#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
-#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
-#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
-#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val)
-#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val)
-#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
-#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val)
-#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
-#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val)
-#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val)
-#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val)
-#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val)
-#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
-#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
-#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
-#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
-#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
-#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
-#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val)
-#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val)
-#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
-#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val)
-#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
-#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val)
-#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val)
-#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val)
-#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val)
-#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
-#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
-#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
-#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
-#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
-#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
-#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val)
-#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val)
-#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val)
-#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
-#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val)
-#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
-#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val)
-#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val)
-#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val)
-#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val)
-#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val)
-#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
-#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
-#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
-#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
-#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
-#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
-#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
-#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
-#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val)
-#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val)
-#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val)
-#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
-#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val)
-#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
-#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val)
-#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val)
-#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val)
-#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val)
-#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val)
-#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
-#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
-#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
-#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
-#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
-#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
-#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
-#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
-#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
-#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val)
-#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val)
-#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
-#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val)
-#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
-#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
-#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val)
-#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val)
-#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val)
-#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val)
-#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
-#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
-#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
-#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
-#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
-#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
-#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
-#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
-#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val)
-#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
-#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val)
-#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
-#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val)
-#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
-#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val)
-#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val)
-#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val)
-#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val)
-#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val)
-#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
-#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
-#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
-#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
-#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
-#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
-#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
-#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
-#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val)
-#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val)
-#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val)
-#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
-#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val)
-#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
-#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val)
-#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val)
-#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val)
-#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val)
-#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val)
-#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
-#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
-#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
-#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
-#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
-#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
-#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
-#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG)
-#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val)
-#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR)
-#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR, val)
-#define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR)
-#define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR, val)
-#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT)
-#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val)
-#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT)
-#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val)
-#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY)
-#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val)
-#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY)
-#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val)
-#define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR)
-#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR, val)
-#define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR)
-#define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR, val)
-#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT)
-#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
-#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT)
-#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
-#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
-#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
-#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
-#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG)
-#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val)
-#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR)
-#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR, val)
-#define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR)
-#define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR, val)
-#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT)
-#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val)
-#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT)
-#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val)
-#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY)
-#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val)
-#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY)
-#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val)
-#define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR)
-#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR, val)
-#define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR)
-#define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR, val)
-#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT)
-#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
-#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT)
-#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
-#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS)
-#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
-#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
-#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG)
-#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val)
-#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR)
-#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR, val)
-#define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR)
-#define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR, val)
-#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT)
-#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val)
-#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT)
-#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val)
-#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY)
-#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
-#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY)
-#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
-#define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR)
-#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR, val)
-#define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR)
-#define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR, val)
-#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
-#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
-#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
-#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
-#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS)
-#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
-#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
-#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG)
-#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val)
-#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR)
-#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR, val)
-#define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR)
-#define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR, val)
-#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT)
-#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val)
-#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT)
-#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val)
-#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY)
-#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
-#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY)
-#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
-#define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR)
-#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR, val)
-#define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR)
-#define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR, val)
-#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
-#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
-#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
-#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
-#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS)
-#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
-#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
-#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
-
-#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
-#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
-#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR)
-#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val)
-#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
-#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
-#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
-#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
-#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
-#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
-#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
-#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
-#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR)
-#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR, val)
-#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
-#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
-#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
-#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
-
-#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
-#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
-#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR)
-#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR, val)
-#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
-#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
-#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
-#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
-#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
-#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
-#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
-#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
-#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR)
-#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR, val)
-#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
-#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
-#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
-#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
-
-#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
-#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
-#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR)
-#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR, val)
-#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
-#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
-#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
-#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
-#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
-#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
-#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
-#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
-#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR)
-#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR, val)
-#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
-#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
-#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
-#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
-
-#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
-#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
-#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR)
-#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR, val)
-#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
-#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
-#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
-#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
-#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
-#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
-#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
-#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
-#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR)
-#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR, val)
-#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
-#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
-#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
-#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
-
-
-/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
-#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL)
-#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val)
-#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS)
-#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val)
-#define bfin_clear_PPI_STATUS() bfin_write_PPI_STATUS(0xFFFF)
-#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY)
-#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val)
-#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT)
-#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val)
-#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME)
-#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val)
-
-
-/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
-
-/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
-#define bfin_read_PORTGIO() bfin_read16(PORTGIO)
-#define bfin_write_PORTGIO(val) bfin_write16(PORTGIO, val)
-#define bfin_read_PORTGIO_CLEAR() bfin_read16(PORTGIO_CLEAR)
-#define bfin_write_PORTGIO_CLEAR(val) bfin_write16(PORTGIO_CLEAR, val)
-#define bfin_read_PORTGIO_SET() bfin_read16(PORTGIO_SET)
-#define bfin_write_PORTGIO_SET(val) bfin_write16(PORTGIO_SET, val)
-#define bfin_read_PORTGIO_TOGGLE() bfin_read16(PORTGIO_TOGGLE)
-#define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE, val)
-#define bfin_read_PORTGIO_MASKA() bfin_read16(PORTGIO_MASKA)
-#define bfin_write_PORTGIO_MASKA(val) bfin_write16(PORTGIO_MASKA, val)
-#define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR)
-#define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR, val)
-#define bfin_read_PORTGIO_MASKA_SET() bfin_read16(PORTGIO_MASKA_SET)
-#define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET, val)
-#define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE)
-#define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTGIO_MASKB() bfin_read16(PORTGIO_MASKB)
-#define bfin_write_PORTGIO_MASKB(val) bfin_write16(PORTGIO_MASKB, val)
-#define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR)
-#define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR, val)
-#define bfin_read_PORTGIO_MASKB_SET() bfin_read16(PORTGIO_MASKB_SET)
-#define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET, val)
-#define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE)
-#define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTGIO_DIR() bfin_read16(PORTGIO_DIR)
-#define bfin_write_PORTGIO_DIR(val) bfin_write16(PORTGIO_DIR, val)
-#define bfin_read_PORTGIO_POLAR() bfin_read16(PORTGIO_POLAR)
-#define bfin_write_PORTGIO_POLAR(val) bfin_write16(PORTGIO_POLAR, val)
-#define bfin_read_PORTGIO_EDGE() bfin_read16(PORTGIO_EDGE)
-#define bfin_write_PORTGIO_EDGE(val) bfin_write16(PORTGIO_EDGE, val)
-#define bfin_read_PORTGIO_BOTH() bfin_read16(PORTGIO_BOTH)
-#define bfin_write_PORTGIO_BOTH(val) bfin_write16(PORTGIO_BOTH, val)
-#define bfin_read_PORTGIO_INEN() bfin_read16(PORTGIO_INEN)
-#define bfin_write_PORTGIO_INEN(val) bfin_write16(PORTGIO_INEN, val)
-
-
-/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
-#define bfin_read_PORTHIO() bfin_read16(PORTHIO)
-#define bfin_write_PORTHIO(val) bfin_write16(PORTHIO, val)
-#define bfin_read_PORTHIO_CLEAR() bfin_read16(PORTHIO_CLEAR)
-#define bfin_write_PORTHIO_CLEAR(val) bfin_write16(PORTHIO_CLEAR, val)
-#define bfin_read_PORTHIO_SET() bfin_read16(PORTHIO_SET)
-#define bfin_write_PORTHIO_SET(val) bfin_write16(PORTHIO_SET, val)
-#define bfin_read_PORTHIO_TOGGLE() bfin_read16(PORTHIO_TOGGLE)
-#define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE, val)
-#define bfin_read_PORTHIO_MASKA() bfin_read16(PORTHIO_MASKA)
-#define bfin_write_PORTHIO_MASKA(val) bfin_write16(PORTHIO_MASKA, val)
-#define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR)
-#define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR, val)
-#define bfin_read_PORTHIO_MASKA_SET() bfin_read16(PORTHIO_MASKA_SET)
-#define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET, val)
-#define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE)
-#define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTHIO_MASKB() bfin_read16(PORTHIO_MASKB)
-#define bfin_write_PORTHIO_MASKB(val) bfin_write16(PORTHIO_MASKB, val)
-#define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR)
-#define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR, val)
-#define bfin_read_PORTHIO_MASKB_SET() bfin_read16(PORTHIO_MASKB_SET)
-#define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET, val)
-#define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE)
-#define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTHIO_DIR() bfin_read16(PORTHIO_DIR)
-#define bfin_write_PORTHIO_DIR(val) bfin_write16(PORTHIO_DIR, val)
-#define bfin_read_PORTHIO_POLAR() bfin_read16(PORTHIO_POLAR)
-#define bfin_write_PORTHIO_POLAR(val) bfin_write16(PORTHIO_POLAR, val)
-#define bfin_read_PORTHIO_EDGE() bfin_read16(PORTHIO_EDGE)
-#define bfin_write_PORTHIO_EDGE(val) bfin_write16(PORTHIO_EDGE, val)
-#define bfin_read_PORTHIO_BOTH() bfin_read16(PORTHIO_BOTH)
-#define bfin_write_PORTHIO_BOTH(val) bfin_write16(PORTHIO_BOTH, val)
-#define bfin_read_PORTHIO_INEN() bfin_read16(PORTHIO_INEN)
-#define bfin_write_PORTHIO_INEN(val) bfin_write16(PORTHIO_INEN, val)
-
-
-/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
-#define bfin_read_UART1_THR() bfin_read16(UART1_THR)
-#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val)
-#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR)
-#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val)
-#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL)
-#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val)
-#define bfin_read_UART1_IER() bfin_read16(UART1_IER)
-#define bfin_write_UART1_IER(val) bfin_write16(UART1_IER, val)
-#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH)
-#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val)
-#define bfin_read_UART1_IIR() bfin_read16(UART1_IIR)
-#define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR, val)
-#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR)
-#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val)
-#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR)
-#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val)
-#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR)
-#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val)
-#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR)
-#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val)
-#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR)
-#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val)
-#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL)
-#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val)
-
-/* Omit CAN register sets from the cdefBF534.h (CAN is not in the ADSP-BF51x processor) */
-
-/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
-#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER)
-#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val)
-#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER)
-#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val)
-#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER)
-#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val)
-#define bfin_read_PORT_MUX() bfin_read16(PORT_MUX)
-#define bfin_write_PORT_MUX(val) bfin_write16(PORT_MUX, val)
-
-
-/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
-#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
-#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
-#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
-#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
-#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
-#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
-#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
-#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
-#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
-#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
-#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
-#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
-#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
-#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
-
-#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
-#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
-#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
-#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
-#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
-#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
-#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
-#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
-#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
-#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
-#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
-#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
-#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
-#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
-
-/* ==== end from cdefBF534.h ==== */
-
-/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
-
-#define bfin_read_PORTF_MUX() bfin_read16(PORTF_MUX)
-#define bfin_write_PORTF_MUX(val) bfin_write16(PORTF_MUX, val)
-#define bfin_read_PORTG_MUX() bfin_read16(PORTG_MUX)
-#define bfin_write_PORTG_MUX(val) bfin_write16(PORTG_MUX, val)
-#define bfin_read_PORTH_MUX() bfin_read16(PORTH_MUX)
-#define bfin_write_PORTH_MUX(val) bfin_write16(PORTH_MUX, val)
-
-#define bfin_read_PORTF_DRIVE() bfin_read16(PORTF_DRIVE)
-#define bfin_write_PORTF_DRIVE(val) bfin_write16(PORTF_DRIVE, val)
-#define bfin_read_PORTG_DRIVE() bfin_read16(PORTG_DRIVE)
-#define bfin_write_PORTG_DRIVE(val) bfin_write16(PORTG_DRIVE, val)
-#define bfin_read_PORTH_DRIVE() bfin_read16(PORTH_DRIVE)
-#define bfin_write_PORTH_DRIVE(val) bfin_write16(PORTH_DRIVE, val)
-#define bfin_read_PORTF_SLEW() bfin_read16(PORTF_SLEW)
-#define bfin_write_PORTF_SLEW(val) bfin_write16(PORTF_SLEW, val)
-#define bfin_read_PORTG_SLEW() bfin_read16(PORTG_SLEW)
-#define bfin_write_PORTG_SLEW(val) bfin_write16(PORTG_SLEW, val)
-#define bfin_read_PORTH_SLEW() bfin_read16(PORTH_SLEW)
-#define bfin_write_PORTH_SLEW(val) bfin_write16(PORTH_SLEW, val)
-#define bfin_read_PORTF_HYSTERESIS() bfin_read16(PORTF_HYSTERESIS)
-#define bfin_write_PORTF_HYSTERESIS(val) bfin_write16(PORTF_HYSTERESIS, val)
-#define bfin_read_PORTG_HYSTERESIS() bfin_read16(PORTG_HYSTERESIS)
-#define bfin_write_PORTG_HYSTERESIS(val) bfin_write16(PORTG_HYSTERESIS, val)
-#define bfin_read_PORTH_HYSTERESIS() bfin_read16(PORTH_HYSTERESIS)
-#define bfin_write_PORTH_HYSTERESIS(val) bfin_write16(PORTH_HYSTERESIS, val)
-#define bfin_read_MISCPORT_DRIVE() bfin_read16(MISCPORT_DRIVE)
-#define bfin_write_MISCPORT_DRIVE(val) bfin_write16(MISCPORT_DRIVE, val)
-#define bfin_read_MISCPORT_SLEW() bfin_read16(MISCPORT_SLEW)
-#define bfin_write_MISCPORT_SLEW(val) bfin_write16(MISCPORT_SLEW, val)
-#define bfin_read_MISCPORT_HYSTERESIS() bfin_read16(MISCPORT_HYSTERESIS)
-#define bfin_write_MISCPORT_HYSTERESIS(val) bfin_write16(MISCPORT_HYSTERESIS, val)
-
-/* HOST Port Registers */
-
-#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL)
-#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val)
-#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS)
-#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val)
-#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT)
-#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val)
-
-/* Counter Registers */
-
-#define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG)
-#define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val)
-#define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK)
-#define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val)
-#define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS)
-#define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val)
-#define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND)
-#define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val)
-#define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE)
-#define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val)
-#define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER)
-#define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val)
-#define bfin_read_CNT_MAX() bfin_read32(CNT_MAX)
-#define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val)
-#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN)
-#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val)
-
-/* Security Registers */
-
-#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT)
-#define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val)
-#define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL)
-#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
-#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS)
-#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val)
-
-#endif /* _CDEF_BF512_H */
+++ /dev/null
-/*
- * Copyright 2008-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _CDEF_BF514_H
-#define _CDEF_BF514_H
-
-/* BF514 is BF512 + RSI */
-#include "cdefBF512.h"
-
-/* Removable Storage Interface Registers */
-
-#define bfin_read_RSI_PWR_CTL() bfin_read16(RSI_PWR_CONTROL)
-#define bfin_write_RSI_PWR_CTL(val) bfin_write16(RSI_PWR_CONTROL, val)
-#define bfin_read_RSI_CLK_CTL() bfin_read16(RSI_CLK_CONTROL)
-#define bfin_write_RSI_CLK_CTL(val) bfin_write16(RSI_CLK_CONTROL, val)
-#define bfin_read_RSI_ARGUMENT() bfin_read32(RSI_ARGUMENT)
-#define bfin_write_RSI_ARGUMENT(val) bfin_write32(RSI_ARGUMENT, val)
-#define bfin_read_RSI_COMMAND() bfin_read16(RSI_COMMAND)
-#define bfin_write_RSI_COMMAND(val) bfin_write16(RSI_COMMAND, val)
-#define bfin_read_RSI_RESP_CMD() bfin_read16(RSI_RESP_CMD)
-#define bfin_write_RSI_RESP_CMD(val) bfin_write16(RSI_RESP_CMD, val)
-#define bfin_read_RSI_RESPONSE0() bfin_read32(RSI_RESPONSE0)
-#define bfin_write_RSI_RESPONSE0(val) bfin_write32(RSI_RESPONSE0, val)
-#define bfin_read_RSI_RESPONSE1() bfin_read32(RSI_RESPONSE1)
-#define bfin_write_RSI_RESPONSE1(val) bfin_write32(RSI_RESPONSE1, val)
-#define bfin_read_RSI_RESPONSE2() bfin_read32(RSI_RESPONSE2)
-#define bfin_write_RSI_RESPONSE2(val) bfin_write32(RSI_RESPONSE2, val)
-#define bfin_read_RSI_RESPONSE3() bfin_read32(RSI_RESPONSE3)
-#define bfin_write_RSI_RESPONSE3(val) bfin_write32(RSI_RESPONSE3, val)
-#define bfin_read_RSI_DATA_TIMER() bfin_read32(RSI_DATA_TIMER)
-#define bfin_write_RSI_DATA_TIMER(val) bfin_write32(RSI_DATA_TIMER, val)
-#define bfin_read_RSI_DATA_LGTH() bfin_read16(RSI_DATA_LGTH)
-#define bfin_write_RSI_DATA_LGTH(val) bfin_write16(RSI_DATA_LGTH, val)
-#define bfin_read_RSI_DATA_CTL() bfin_read16(RSI_DATA_CONTROL)
-#define bfin_write_RSI_DATA_CTL(val) bfin_write16(RSI_DATA_CONTROL, val)
-#define bfin_read_RSI_DATA_CNT() bfin_read16(RSI_DATA_CNT)
-#define bfin_write_RSI_DATA_CNT(val) bfin_write16(RSI_DATA_CNT, val)
-#define bfin_read_RSI_STATUS() bfin_read32(RSI_STATUS)
-#define bfin_write_RSI_STATUS(val) bfin_write32(RSI_STATUS, val)
-#define bfin_read_RSI_STATUS_CLR() bfin_read16(RSI_STATUSCL)
-#define bfin_write_RSI_STATUS_CLR(val) bfin_write16(RSI_STATUSCL, val)
-#define bfin_read_RSI_MASK0() bfin_read32(RSI_MASK0)
-#define bfin_write_RSI_MASK0(val) bfin_write32(RSI_MASK0, val)
-#define bfin_read_RSI_MASK1() bfin_read32(RSI_MASK1)
-#define bfin_write_RSI_MASK1(val) bfin_write32(RSI_MASK1, val)
-#define bfin_read_RSI_FIFO_CNT() bfin_read16(RSI_FIFO_CNT)
-#define bfin_write_RSI_FIFO_CNT(val) bfin_write16(RSI_FIFO_CNT, val)
-#define bfin_read_RSI_CEATA_CTL() bfin_read16(RSI_CEATA_CONTROL)
-#define bfin_write_RSI_CEATA_CTL(val) bfin_write16(RSI_CEATA_CONTROL, val)
-#define bfin_read_RSI_FIFO() bfin_read32(RSI_FIFO)
-#define bfin_write_RSI_FIFO(val) bfin_write32(RSI_FIFO, val)
-#define bfin_read_RSI_E_STATUS() bfin_read16(RSI_ESTAT)
-#define bfin_write_RSI_E_STATUS(val) bfin_write16(RSI_ESTAT, val)
-#define bfin_read_RSI_E_MASK() bfin_read16(RSI_EMASK)
-#define bfin_write_RSI_E_MASK(val) bfin_write16(RSI_EMASK, val)
-#define bfin_read_RSI_CFG() bfin_read16(RSI_CONFIG)
-#define bfin_write_RSI_CFG(val) bfin_write16(RSI_CONFIG, val)
-#define bfin_read_RSI_RD_WAIT_EN() bfin_read16(RSI_RD_WAIT_EN)
-#define bfin_write_RSI_RD_WAIT_EN(val) bfin_write16(RSI_RD_WAIT_EN, val)
-#define bfin_read_RSI_PID0() bfin_read16(RSI_PID0)
-#define bfin_write_RSI_PID0(val) bfin_write16(RSI_PID0, val)
-#define bfin_read_RSI_PID1() bfin_read16(RSI_PID1)
-#define bfin_write_RSI_PID1(val) bfin_write16(RSI_PID1, val)
-#define bfin_read_RSI_PID2() bfin_read16(RSI_PID2)
-#define bfin_write_RSI_PID2(val) bfin_write16(RSI_PID2, val)
-#define bfin_read_RSI_PID3() bfin_read16(RSI_PID3)
-#define bfin_write_RSI_PID3(val) bfin_write16(RSI_PID3, val)
-#define bfin_read_RSI_PID4() bfin_read16(RSI_PID4)
-#define bfin_write_RSI_PID4(val) bfin_write16(RSI_PID4, val)
-#define bfin_read_RSI_PID5() bfin_read16(RSI_PID5)
-#define bfin_write_RSI_PID5(val) bfin_write16(RSI_PID5, val)
-#define bfin_read_RSI_PID6() bfin_read16(RSI_PID6)
-#define bfin_write_RSI_PID6(val) bfin_write16(RSI_PID6, val)
-#define bfin_read_RSI_PID7() bfin_read16(RSI_PID7)
-#define bfin_write_RSI_PID7(val) bfin_write16(RSI_PID7, val)
-
-#endif /* _CDEF_BF514_H */
+++ /dev/null
-/*
- * Copyright 2008-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _CDEF_BF516_H
-#define _CDEF_BF516_H
-
-/* BF516 is BF514 + EMAC */
-#include "cdefBF514.h"
-
-/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
-
-#define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE)
-#define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE, val)
-#define bfin_read_EMAC_ADDRLO() bfin_read32(EMAC_ADDRLO)
-#define bfin_write_EMAC_ADDRLO(val) bfin_write32(EMAC_ADDRLO, val)
-#define bfin_read_EMAC_ADDRHI() bfin_read32(EMAC_ADDRHI)
-#define bfin_write_EMAC_ADDRHI(val) bfin_write32(EMAC_ADDRHI, val)
-#define bfin_read_EMAC_HASHLO() bfin_read32(EMAC_HASHLO)
-#define bfin_write_EMAC_HASHLO(val) bfin_write32(EMAC_HASHLO, val)
-#define bfin_read_EMAC_HASHHI() bfin_read32(EMAC_HASHHI)
-#define bfin_write_EMAC_HASHHI(val) bfin_write32(EMAC_HASHHI, val)
-#define bfin_read_EMAC_STAADD() bfin_read32(EMAC_STAADD)
-#define bfin_write_EMAC_STAADD(val) bfin_write32(EMAC_STAADD, val)
-#define bfin_read_EMAC_STADAT() bfin_read32(EMAC_STADAT)
-#define bfin_write_EMAC_STADAT(val) bfin_write32(EMAC_STADAT, val)
-#define bfin_read_EMAC_FLC() bfin_read32(EMAC_FLC)
-#define bfin_write_EMAC_FLC(val) bfin_write32(EMAC_FLC, val)
-#define bfin_read_EMAC_VLAN1() bfin_read32(EMAC_VLAN1)
-#define bfin_write_EMAC_VLAN1(val) bfin_write32(EMAC_VLAN1, val)
-#define bfin_read_EMAC_VLAN2() bfin_read32(EMAC_VLAN2)
-#define bfin_write_EMAC_VLAN2(val) bfin_write32(EMAC_VLAN2, val)
-#define bfin_read_EMAC_WKUP_CTL() bfin_read32(EMAC_WKUP_CTL)
-#define bfin_write_EMAC_WKUP_CTL(val) bfin_write32(EMAC_WKUP_CTL, val)
-#define bfin_read_EMAC_WKUP_FFMSK0() bfin_read32(EMAC_WKUP_FFMSK0)
-#define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0, val)
-#define bfin_read_EMAC_WKUP_FFMSK1() bfin_read32(EMAC_WKUP_FFMSK1)
-#define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1, val)
-#define bfin_read_EMAC_WKUP_FFMSK2() bfin_read32(EMAC_WKUP_FFMSK2)
-#define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2, val)
-#define bfin_read_EMAC_WKUP_FFMSK3() bfin_read32(EMAC_WKUP_FFMSK3)
-#define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3, val)
-#define bfin_read_EMAC_WKUP_FFCMD() bfin_read32(EMAC_WKUP_FFCMD)
-#define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD, val)
-#define bfin_read_EMAC_WKUP_FFOFF() bfin_read32(EMAC_WKUP_FFOFF)
-#define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF, val)
-#define bfin_read_EMAC_WKUP_FFCRC0() bfin_read32(EMAC_WKUP_FFCRC0)
-#define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0, val)
-#define bfin_read_EMAC_WKUP_FFCRC1() bfin_read32(EMAC_WKUP_FFCRC1)
-#define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1, val)
-
-#define bfin_read_EMAC_SYSCTL() bfin_read32(EMAC_SYSCTL)
-#define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL, val)
-#define bfin_read_EMAC_SYSTAT() bfin_read32(EMAC_SYSTAT)
-#define bfin_write_EMAC_SYSTAT(val) bfin_write32(EMAC_SYSTAT, val)
-#define bfin_read_EMAC_RX_STAT() bfin_read32(EMAC_RX_STAT)
-#define bfin_write_EMAC_RX_STAT(val) bfin_write32(EMAC_RX_STAT, val)
-#define bfin_read_EMAC_RX_STKY() bfin_read32(EMAC_RX_STKY)
-#define bfin_write_EMAC_RX_STKY(val) bfin_write32(EMAC_RX_STKY, val)
-#define bfin_read_EMAC_RX_IRQE() bfin_read32(EMAC_RX_IRQE)
-#define bfin_write_EMAC_RX_IRQE(val) bfin_write32(EMAC_RX_IRQE, val)
-#define bfin_read_EMAC_TX_STAT() bfin_read32(EMAC_TX_STAT)
-#define bfin_write_EMAC_TX_STAT(val) bfin_write32(EMAC_TX_STAT, val)
-#define bfin_read_EMAC_TX_STKY() bfin_read32(EMAC_TX_STKY)
-#define bfin_write_EMAC_TX_STKY(val) bfin_write32(EMAC_TX_STKY, val)
-#define bfin_read_EMAC_TX_IRQE() bfin_read32(EMAC_TX_IRQE)
-#define bfin_write_EMAC_TX_IRQE(val) bfin_write32(EMAC_TX_IRQE, val)
-
-#define bfin_read_EMAC_MMC_CTL() bfin_read32(EMAC_MMC_CTL)
-#define bfin_write_EMAC_MMC_CTL(val) bfin_write32(EMAC_MMC_CTL, val)
-#define bfin_read_EMAC_MMC_RIRQS() bfin_read32(EMAC_MMC_RIRQS)
-#define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS, val)
-#define bfin_read_EMAC_MMC_RIRQE() bfin_read32(EMAC_MMC_RIRQE)
-#define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE, val)
-#define bfin_read_EMAC_MMC_TIRQS() bfin_read32(EMAC_MMC_TIRQS)
-#define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS, val)
-#define bfin_read_EMAC_MMC_TIRQE() bfin_read32(EMAC_MMC_TIRQE)
-#define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE, val)
-
-#define bfin_read_EMAC_RXC_OK() bfin_read32(EMAC_RXC_OK)
-#define bfin_write_EMAC_RXC_OK(val) bfin_write32(EMAC_RXC_OK, val)
-#define bfin_read_EMAC_RXC_FCS() bfin_read32(EMAC_RXC_FCS)
-#define bfin_write_EMAC_RXC_FCS(val) bfin_write32(EMAC_RXC_FCS, val)
-#define bfin_read_EMAC_RXC_ALIGN() bfin_read32(EMAC_RXC_ALIGN)
-#define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN, val)
-#define bfin_read_EMAC_RXC_OCTET() bfin_read32(EMAC_RXC_OCTET)
-#define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET, val)
-#define bfin_read_EMAC_RXC_DMAOVF() bfin_read32(EMAC_RXC_DMAOVF)
-#define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF, val)
-#define bfin_read_EMAC_RXC_UNICST() bfin_read32(EMAC_RXC_UNICST)
-#define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST, val)
-#define bfin_read_EMAC_RXC_MULTI() bfin_read32(EMAC_RXC_MULTI)
-#define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI, val)
-#define bfin_read_EMAC_RXC_BROAD() bfin_read32(EMAC_RXC_BROAD)
-#define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD, val)
-#define bfin_read_EMAC_RXC_LNERRI() bfin_read32(EMAC_RXC_LNERRI)
-#define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI, val)
-#define bfin_read_EMAC_RXC_LNERRO() bfin_read32(EMAC_RXC_LNERRO)
-#define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO, val)
-#define bfin_read_EMAC_RXC_LONG() bfin_read32(EMAC_RXC_LONG)
-#define bfin_write_EMAC_RXC_LONG(val) bfin_write32(EMAC_RXC_LONG, val)
-#define bfin_read_EMAC_RXC_MACCTL() bfin_read32(EMAC_RXC_MACCTL)
-#define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL, val)
-#define bfin_read_EMAC_RXC_OPCODE() bfin_read32(EMAC_RXC_OPCODE)
-#define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE, val)
-#define bfin_read_EMAC_RXC_PAUSE() bfin_read32(EMAC_RXC_PAUSE)
-#define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE, val)
-#define bfin_read_EMAC_RXC_ALLFRM() bfin_read32(EMAC_RXC_ALLFRM)
-#define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM, val)
-#define bfin_read_EMAC_RXC_ALLOCT() bfin_read32(EMAC_RXC_ALLOCT)
-#define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT, val)
-#define bfin_read_EMAC_RXC_TYPED() bfin_read32(EMAC_RXC_TYPED)
-#define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED, val)
-#define bfin_read_EMAC_RXC_SHORT() bfin_read32(EMAC_RXC_SHORT)
-#define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT, val)
-#define bfin_read_EMAC_RXC_EQ64() bfin_read32(EMAC_RXC_EQ64)
-#define bfin_write_EMAC_RXC_EQ64(val) bfin_write32(EMAC_RXC_EQ64, val)
-#define bfin_read_EMAC_RXC_LT128() bfin_read32(EMAC_RXC_LT128)
-#define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128, val)
-#define bfin_read_EMAC_RXC_LT256() bfin_read32(EMAC_RXC_LT256)
-#define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256, val)
-#define bfin_read_EMAC_RXC_LT512() bfin_read32(EMAC_RXC_LT512)
-#define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512, val)
-#define bfin_read_EMAC_RXC_LT1024() bfin_read32(EMAC_RXC_LT1024)
-#define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024, val)
-#define bfin_read_EMAC_RXC_GE1024() bfin_read32(EMAC_RXC_GE1024)
-#define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024, val)
-
-#define bfin_read_EMAC_TXC_OK() bfin_read32(EMAC_TXC_OK)
-#define bfin_write_EMAC_TXC_OK(val) bfin_write32(EMAC_TXC_OK, val)
-#define bfin_read_EMAC_TXC_1COL() bfin_read32(EMAC_TXC_1COL)
-#define bfin_write_EMAC_TXC_1COL(val) bfin_write32(EMAC_TXC_1COL, val)
-#define bfin_read_EMAC_TXC_GT1COL() bfin_read32(EMAC_TXC_GT1COL)
-#define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL, val)
-#define bfin_read_EMAC_TXC_OCTET() bfin_read32(EMAC_TXC_OCTET)
-#define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET, val)
-#define bfin_read_EMAC_TXC_DEFER() bfin_read32(EMAC_TXC_DEFER)
-#define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER, val)
-#define bfin_read_EMAC_TXC_LATECL() bfin_read32(EMAC_TXC_LATECL)
-#define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL, val)
-#define bfin_read_EMAC_TXC_XS_COL() bfin_read32(EMAC_TXC_XS_COL)
-#define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL, val)
-#define bfin_read_EMAC_TXC_DMAUND() bfin_read32(EMAC_TXC_DMAUND)
-#define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND, val)
-#define bfin_read_EMAC_TXC_CRSERR() bfin_read32(EMAC_TXC_CRSERR)
-#define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR, val)
-#define bfin_read_EMAC_TXC_UNICST() bfin_read32(EMAC_TXC_UNICST)
-#define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST, val)
-#define bfin_read_EMAC_TXC_MULTI() bfin_read32(EMAC_TXC_MULTI)
-#define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI, val)
-#define bfin_read_EMAC_TXC_BROAD() bfin_read32(EMAC_TXC_BROAD)
-#define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD, val)
-#define bfin_read_EMAC_TXC_XS_DFR() bfin_read32(EMAC_TXC_XS_DFR)
-#define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR, val)
-#define bfin_read_EMAC_TXC_MACCTL() bfin_read32(EMAC_TXC_MACCTL)
-#define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL, val)
-#define bfin_read_EMAC_TXC_ALLFRM() bfin_read32(EMAC_TXC_ALLFRM)
-#define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM, val)
-#define bfin_read_EMAC_TXC_ALLOCT() bfin_read32(EMAC_TXC_ALLOCT)
-#define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT, val)
-#define bfin_read_EMAC_TXC_EQ64() bfin_read32(EMAC_TXC_EQ64)
-#define bfin_write_EMAC_TXC_EQ64(val) bfin_write32(EMAC_TXC_EQ64, val)
-#define bfin_read_EMAC_TXC_LT128() bfin_read32(EMAC_TXC_LT128)
-#define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128, val)
-#define bfin_read_EMAC_TXC_LT256() bfin_read32(EMAC_TXC_LT256)
-#define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256, val)
-#define bfin_read_EMAC_TXC_LT512() bfin_read32(EMAC_TXC_LT512)
-#define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512, val)
-#define bfin_read_EMAC_TXC_LT1024() bfin_read32(EMAC_TXC_LT1024)
-#define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024, val)
-#define bfin_read_EMAC_TXC_GE1024() bfin_read32(EMAC_TXC_GE1024)
-#define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024, val)
-#define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT)
-#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val)
-
-#endif /* _CDEF_BF516_H */
+++ /dev/null
-/*
- * Copyright 2008-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _CDEF_BF518_H
-#define _CDEF_BF518_H
-
-/* BF518 is BF516 + IEEE-1588 */
-#include "cdefBF516.h"
-
-/* PTP TSYNC Registers */
-
-#define bfin_read_EMAC_PTP_CTL() bfin_read16(EMAC_PTP_CTL)
-#define bfin_write_EMAC_PTP_CTL(val) bfin_write16(EMAC_PTP_CTL, val)
-#define bfin_read_EMAC_PTP_IE() bfin_read16(EMAC_PTP_IE)
-#define bfin_write_EMAC_PTP_IE(val) bfin_write16(EMAC_PTP_IE, val)
-#define bfin_read_EMAC_PTP_ISTAT() bfin_read16(EMAC_PTP_ISTAT)
-#define bfin_write_EMAC_PTP_ISTAT(val) bfin_write16(EMAC_PTP_ISTAT, val)
-#define bfin_read_EMAC_PTP_FOFF() bfin_read32(EMAC_PTP_FOFF)
-#define bfin_write_EMAC_PTP_FOFF(val) bfin_write32(EMAC_PTP_FOFF, val)
-#define bfin_read_EMAC_PTP_FV1() bfin_read32(EMAC_PTP_FV1)
-#define bfin_write_EMAC_PTP_FV1(val) bfin_write32(EMAC_PTP_FV1, val)
-#define bfin_read_EMAC_PTP_FV2() bfin_read32(EMAC_PTP_FV2)
-#define bfin_write_EMAC_PTP_FV2(val) bfin_write32(EMAC_PTP_FV2, val)
-#define bfin_read_EMAC_PTP_FV3() bfin_read32(EMAC_PTP_FV3)
-#define bfin_write_EMAC_PTP_FV3(val) bfin_write32(EMAC_PTP_FV3, val)
-#define bfin_read_EMAC_PTP_ADDEND() bfin_read32(EMAC_PTP_ADDEND)
-#define bfin_write_EMAC_PTP_ADDEND(val) bfin_write32(EMAC_PTP_ADDEND, val)
-#define bfin_read_EMAC_PTP_ACCR() bfin_read32(EMAC_PTP_ACCR)
-#define bfin_write_EMAC_PTP_ACCR(val) bfin_write32(EMAC_PTP_ACCR, val)
-#define bfin_read_EMAC_PTP_OFFSET() bfin_read32(EMAC_PTP_OFFSET)
-#define bfin_write_EMAC_PTP_OFFSET(val) bfin_write32(EMAC_PTP_OFFSET, val)
-#define bfin_read_EMAC_PTP_TIMELO() bfin_read32(EMAC_PTP_TIMELO)
-#define bfin_write_EMAC_PTP_TIMELO(val) bfin_write32(EMAC_PTP_TIMELO, val)
-#define bfin_read_EMAC_PTP_TIMEHI() bfin_read32(EMAC_PTP_TIMEHI)
-#define bfin_write_EMAC_PTP_TIMEHI(val) bfin_write32(EMAC_PTP_TIMEHI, val)
-#define bfin_read_EMAC_PTP_RXSNAPLO() bfin_read32(EMAC_PTP_RXSNAPLO)
-#define bfin_read_EMAC_PTP_RXSNAPHI() bfin_read32(EMAC_PTP_RXSNAPHI)
-#define bfin_read_EMAC_PTP_TXSNAPLO() bfin_read32(EMAC_PTP_TXSNAPLO)
-#define bfin_read_EMAC_PTP_TXSNAPHI() bfin_read32(EMAC_PTP_TXSNAPHI)
-#define bfin_read_EMAC_PTP_ALARMLO() bfin_read32(EMAC_PTP_ALARMLO)
-#define bfin_write_EMAC_PTP_ALARMLO(val) bfin_write32(EMAC_PTP_ALARMLO, val)
-#define bfin_read_EMAC_PTP_ALARMHI() bfin_read32(EMAC_PTP_ALARMHI)
-#define bfin_write_EMAC_PTP_ALARMHI(val) bfin_write32(EMAC_PTP_ALARMHI, val)
-#define bfin_read_EMAC_PTP_ID_OFF() bfin_read16(EMAC_PTP_ID_OFF)
-#define bfin_write_EMAC_PTP_ID_OFF(val) bfin_write16(EMAC_PTP_ID_OFF, val)
-#define bfin_read_EMAC_PTP_ID_SNAP() bfin_read32(EMAC_PTP_ID_SNAP)
-#define bfin_write_EMAC_PTP_ID_SNAP(val) bfin_write32(EMAC_PTP_ID_SNAP, val)
-#define bfin_read_EMAC_PTP_PPS_STARTHI() bfin_read32(EMAC_PTP_PPS_STARTHI)
-#define bfin_write_EMAC_PTP_PPS_STARTHI(val) bfin_write32(EMAC_PTP_PPS_STARTHI, val)
-#define bfin_read_EMAC_PTP_PPS_PERIOD() bfin_read32(EMAC_PTP_PPS_PERIOD)
-#define bfin_write_EMAC_PTP_PPS_PERIOD(val) bfin_write32(EMAC_PTP_PPS_PERIOD, val)
-
-#endif /* _CDEF_BF518_H */
+++ /dev/null
-/*
- * Copyright 2008-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF512_H
-#define _DEF_BF512_H
-
-/* ************************************************************** */
-/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF51x */
-/* ************************************************************** */
-
-/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
-#define PLL_CTL 0xFFC00000 /* PLL Control Register */
-#define PLL_DIV 0xFFC00004 /* PLL Divide Register */
-#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */
-#define PLL_STAT 0xFFC0000C /* PLL Status Register */
-#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */
-#define CHIPID 0xFFC00014 /* Device ID Register */
-
-/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
-#define SWRST 0xFFC00100 /* Software Reset Register */
-#define SYSCR 0xFFC00104 /* System Configuration Register */
-#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
-
-#define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */
-#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
-#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
-#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
-#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */
-#define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */
-#define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */
-
-/* SIC Additions to ADSP-BF51x (0xFFC0014C - 0xFFC00162) */
-#define SIC_IMASK1 0xFFC0014C /* Interrupt Mask register of SIC2 */
-#define SIC_IAR4 0xFFC00150 /* Interrupt Assignment register4 */
-#define SIC_IAR5 0xFFC00154 /* Interrupt Assignment register5 */
-#define SIC_IAR6 0xFFC00158 /* Interrupt Assignment register6 */
-#define SIC_IAR7 0xFFC0015C /* Interrupt Assignment register7 */
-#define SIC_ISR1 0xFFC00160 /* Interrupt Statur register */
-#define SIC_IWR1 0xFFC00164 /* Interrupt Wakeup register */
-
-
-/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
-#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
-#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
-#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
-
-
-/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
-#define RTC_STAT 0xFFC00300 /* RTC Status Register */
-#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
-#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
-#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
-#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */
-#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */
-#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Alternate Macro */
-
-
-/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
-#define UART0_THR 0xFFC00400 /* Transmit Holding register */
-#define UART0_RBR 0xFFC00400 /* Receive Buffer register */
-#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
-#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */
-#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
-#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */
-#define UART0_LCR 0xFFC0040C /* Line Control Register */
-#define UART0_MCR 0xFFC00410 /* Modem Control Register */
-#define UART0_LSR 0xFFC00414 /* Line Status Register */
-#define UART0_MSR 0xFFC00418 /* Modem Status Register */
-#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */
-#define UART0_GCTL 0xFFC00424 /* Global Control Register */
-
-/* SPI0 Controller (0xFFC00500 - 0xFFC005FF) */
-#define SPI0_REGBASE 0xFFC00500
-#define SPI0_CTL 0xFFC00500 /* SPI Control Register */
-#define SPI0_FLG 0xFFC00504 /* SPI Flag register */
-#define SPI0_STAT 0xFFC00508 /* SPI Status register */
-#define SPI0_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */
-#define SPI0_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */
-#define SPI0_BAUD 0xFFC00514 /* SPI Baud rate Register */
-#define SPI0_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */
-
-/* SPI1 Controller (0xFFC03400 - 0xFFC034FF) */
-#define SPI1_REGBASE 0xFFC03400
-#define SPI1_CTL 0xFFC03400 /* SPI Control Register */
-#define SPI1_FLG 0xFFC03404 /* SPI Flag register */
-#define SPI1_STAT 0xFFC03408 /* SPI Status register */
-#define SPI1_TDBR 0xFFC0340C /* SPI Transmit Data Buffer Register */
-#define SPI1_RDBR 0xFFC03410 /* SPI Receive Data Buffer Register */
-#define SPI1_BAUD 0xFFC03414 /* SPI Baud rate Register */
-#define SPI1_SHADOW 0xFFC03418 /* SPI_RDBR Shadow Register */
-
-/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
-#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */
-#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */
-#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */
-#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */
-
-#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */
-#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */
-#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */
-#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */
-
-#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */
-#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */
-#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */
-#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */
-
-#define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */
-#define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */
-#define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */
-#define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */
-
-#define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */
-#define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */
-#define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */
-#define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */
-
-#define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */
-#define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */
-#define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */
-#define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */
-
-#define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */
-#define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */
-#define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */
-#define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register */
-
-#define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */
-#define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */
-#define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */
-#define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */
-
-#define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */
-#define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */
-#define TIMER_STATUS 0xFFC00688 /* Timer Status Register */
-
-/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
-#define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */
-#define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */
-#define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */
-#define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */
-#define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */
-#define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */
-#define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */
-#define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */
-#define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */
-#define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */
-#define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */
-#define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */
-#define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */
-#define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */
-#define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */
-#define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */
-#define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */
-
-/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
-#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
-#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
-#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
-#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
-#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
-#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
-#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
-#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
-#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
-#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
-#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
-#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
-#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
-#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
-#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
-#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
-#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
-#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
-
-/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
-#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
-#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
-#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
-#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
-#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
-#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
-#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
-#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
-#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
-#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
-#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
-#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
-#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
-#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
-#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
-#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
-#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
-#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
-
-/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
-#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
-#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
-#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
-#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
-#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
-#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
-#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
-
-/* DMA Traffic Control Registers */
-#define DMAC_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */
-#define DMAC_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */
-
-/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
-#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
-#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
-#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
-#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
-#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
-#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
-#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
-#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
-#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
-#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
-#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
-#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
-#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
-
-#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
-#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
-#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
-#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
-#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
-#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
-#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
-#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
-#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
-#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
-#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
-#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
-#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
-
-#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
-#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
-#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
-#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
-#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
-#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
-#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
-#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
-#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
-#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
-#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
-#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
-#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
-
-#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
-#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
-#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
-#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
-#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
-#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
-#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
-#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
-#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
-#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
-#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
-#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
-#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
-
-#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
-#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
-#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
-#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
-#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
-#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
-#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
-#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
-#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
-#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
-#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
-#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
-#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
-
-#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
-#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
-#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
-#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
-#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
-#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
-#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
-#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
-#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
-#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
-#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
-#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
-#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
-
-#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
-#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
-#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
-#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
-#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
-#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
-#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
-#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
-#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
-#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
-#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
-#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
-#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
-
-#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
-#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
-#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
-#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
-#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
-#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
-#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
-#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
-#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
-#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
-#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
-#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
-#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
-
-#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
-#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */
-#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */
-#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */
-#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */
-#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */
-#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */
-#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
-#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */
-#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
-#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
-#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */
-#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
-
-#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
-#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */
-#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */
-#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */
-#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */
-#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */
-#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */
-#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
-#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */
-#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
-#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
-#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */
-#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
-
-#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
-#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */
-#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */
-#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */
-#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */
-#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */
-#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
-#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
-#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */
-#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
-#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
-#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
-#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
-
-#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
-#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */
-#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */
-#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */
-#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
-#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */
-#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
-#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
-#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */
-#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
-#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
-#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
-#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
-
-#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
-#define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */
-#define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */
-#define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */
-#define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */
-#define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */
-#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */
-#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
-#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */
-#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */
-#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */
-#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */
-#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */
-
-#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
-#define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */
-#define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */
-#define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */
-#define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */
-#define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */
-#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */
-#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
-#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */
-#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */
-#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */
-#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */
-#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */
-
-#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
-#define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */
-#define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */
-#define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */
-#define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */
-#define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */
-#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */
-#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
-#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */
-#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */
-#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */
-#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */
-#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */
-
-#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
-#define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */
-#define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */
-#define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */
-#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */
-#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */
-#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */
-#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
-#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */
-#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */
-#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */
-#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */
-#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */
-
-
-/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
-#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */
-#define PPI_STATUS 0xFFC01004 /* PPI Status Register */
-#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */
-#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */
-#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
-
-
-/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
-#define TWI0_REGBASE 0xFFC01400
-#define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
-#define TWI0_CONTROL 0xFFC01404 /* TWI Control Register */
-#define TWI0_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
-#define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
-#define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
-#define TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */
-#define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
-#define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
-#define TWI0_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */
-#define TWI0_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */
-#define TWI0_FIFO_CTL 0xFFC01428 /* FIFO Control Register */
-#define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
-#define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
-#define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
-#define TWI0_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */
-#define TWI0_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */
-
-
-/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
-#define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */
-#define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */
-#define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */
-#define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */
-#define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */
-#define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */
-#define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */
-#define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */
-#define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */
-#define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */
-#define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */
-#define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */
-#define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */
-#define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */
-#define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */
-#define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */
-#define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */
-
-
-/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
-#define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */
-#define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */
-#define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */
-#define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */
-#define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */
-#define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */
-#define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */
-#define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */
-#define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */
-#define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */
-#define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */
-#define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */
-#define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */
-#define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */
-#define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */
-#define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */
-#define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */
-
-
-/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
-#define UART1_THR 0xFFC02000 /* Transmit Holding register */
-#define UART1_RBR 0xFFC02000 /* Receive Buffer register */
-#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */
-#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */
-#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */
-#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */
-#define UART1_LCR 0xFFC0200C /* Line Control Register */
-#define UART1_MCR 0xFFC02010 /* Modem Control Register */
-#define UART1_LSR 0xFFC02014 /* Line Status Register */
-#define UART1_MSR 0xFFC02018 /* Modem Status Register */
-#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */
-#define UART1_GCTL 0xFFC02024 /* Global Control Register */
-
-
-/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
-#define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */
-#define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */
-#define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */
-#define BFIN_PORT_MUX 0xFFC0320C /* Port Multiplexer Control Register */
-
-
-/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
-#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */
-#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */
-#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */
-#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshold Register */
-#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */
-#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */
-#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */
-
-#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */
-#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */
-#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */
-#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshold Register */
-#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */
-#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */
-#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */
-
-
-/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
-#define PORTF_MUX 0xFFC03210 /* Port F mux control */
-#define PORTG_MUX 0xFFC03214 /* Port G mux control */
-#define PORTH_MUX 0xFFC03218 /* Port H mux control */
-#define PORTF_DRIVE 0xFFC03220 /* Port F drive strength control */
-#define PORTG_DRIVE 0xFFC03224 /* Port G drive strength control */
-#define PORTH_DRIVE 0xFFC03228 /* Port H drive strength control */
-#define PORTF_SLEW 0xFFC03230 /* Port F slew control */
-#define PORTG_SLEW 0xFFC03234 /* Port G slew control */
-#define PORTH_SLEW 0xFFC03238 /* Port H slew control */
-#define PORTF_HYSTERESIS 0xFFC03240 /* Port F Schmitt trigger control */
-#define PORTG_HYSTERESIS 0xFFC03244 /* Port G Schmitt trigger control */
-#define PORTH_HYSTERESIS 0xFFC03248 /* Port H Schmitt trigger control */
-#define MISCPORT_DRIVE 0xFFC03280 /* Misc Port drive strength control */
-#define MISCPORT_SLEW 0xFFC03284 /* Misc Port slew control */
-#define MISCPORT_HYSTERESIS 0xFFC03288 /* Misc Port Schmitt trigger control */
-
-
-/***********************************************************************************
-** System MMR Register Bits And Macros
-**
-** Disclaimer: All macros are intended to make C and Assembly code more readable.
-** Use these macros carefully, as any that do left shifts for field
-** depositing will result in the lower order bits being destroyed. Any
-** macro that shifts left to properly position the bit-field should be
-** used as part of an OR to initialize a register and NOT as a dynamic
-** modifier UNLESS the lower order bits are saved and ORed back in when
-** the macro is used.
-*************************************************************************************/
-
-/* CHIPID Masks */
-#define CHIPID_VERSION 0xF0000000
-#define CHIPID_FAMILY 0x0FFFF000
-#define CHIPID_MANUFACTURE 0x00000FFE
-
-/* SWRST Masks */
-#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
-#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
-#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
-#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
-#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
-
-/* SYSCR Masks */
-#define BMODE 0x0007 /* Boot Mode - Latched During HW Reset From Mode Pins */
-#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
-
-
-/* ************* SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
-/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK */
-
-#if 0
-#define IRQ_PLL_WAKEUP 0x00000001 /* PLL Wakeup Interrupt */
-
-#define IRQ_ERROR1 0x00000002 /* Error Interrupt (DMA, DMARx Block, DMARx Overflow) */
-#define IRQ_ERROR2 0x00000004 /* Error Interrupt (CAN, Ethernet, SPORTx, PPI, SPI, UARTx) */
-#define IRQ_RTC 0x00000008 /* Real Time Clock Interrupt */
-#define IRQ_DMA0 0x00000010 /* DMA Channel 0 (PPI) Interrupt */
-#define IRQ_DMA3 0x00000020 /* DMA Channel 3 (SPORT0 RX) Interrupt */
-#define IRQ_DMA4 0x00000040 /* DMA Channel 4 (SPORT0 TX) Interrupt */
-#define IRQ_DMA5 0x00000080 /* DMA Channel 5 (SPORT1 RX) Interrupt */
-
-#define IRQ_DMA6 0x00000100 /* DMA Channel 6 (SPORT1 TX) Interrupt */
-#define IRQ_TWI 0x00000200 /* TWI Interrupt */
-#define IRQ_DMA7 0x00000400 /* DMA Channel 7 (SPI) Interrupt */
-#define IRQ_DMA8 0x00000800 /* DMA Channel 8 (UART0 RX) Interrupt */
-#define IRQ_DMA9 0x00001000 /* DMA Channel 9 (UART0 TX) Interrupt */
-#define IRQ_DMA10 0x00002000 /* DMA Channel 10 (UART1 RX) Interrupt */
-#define IRQ_DMA11 0x00004000 /* DMA Channel 11 (UART1 TX) Interrupt */
-#define IRQ_CAN_RX 0x00008000 /* CAN Receive Interrupt */
-
-#define IRQ_CAN_TX 0x00010000 /* CAN Transmit Interrupt */
-#define IRQ_DMA1 0x00020000 /* DMA Channel 1 (Ethernet RX) Interrupt */
-#define IRQ_PFA_PORTH 0x00020000 /* PF Port H (PF47:32) Interrupt A */
-#define IRQ_DMA2 0x00040000 /* DMA Channel 2 (Ethernet TX) Interrupt */
-#define IRQ_PFB_PORTH 0x00040000 /* PF Port H (PF47:32) Interrupt B */
-#define IRQ_TIMER0 0x00080000 /* Timer 0 Interrupt */
-#define IRQ_TIMER1 0x00100000 /* Timer 1 Interrupt */
-#define IRQ_TIMER2 0x00200000 /* Timer 2 Interrupt */
-#define IRQ_TIMER3 0x00400000 /* Timer 3 Interrupt */
-#define IRQ_TIMER4 0x00800000 /* Timer 4 Interrupt */
-
-#define IRQ_TIMER5 0x01000000 /* Timer 5 Interrupt */
-#define IRQ_TIMER6 0x02000000 /* Timer 6 Interrupt */
-#define IRQ_TIMER7 0x04000000 /* Timer 7 Interrupt */
-#define IRQ_PFA_PORTFG 0x08000000 /* PF Ports F&G (PF31:0) Interrupt A */
-#define IRQ_PFB_PORTF 0x80000000 /* PF Port F (PF15:0) Interrupt B */
-#define IRQ_DMA12 0x20000000 /* DMA Channels 12 (MDMA1 Source) RX Interrupt */
-#define IRQ_DMA13 0x20000000 /* DMA Channels 13 (MDMA1 Destination) TX Interrupt */
-#define IRQ_DMA14 0x40000000 /* DMA Channels 14 (MDMA0 Source) RX Interrupt */
-#define IRQ_DMA15 0x40000000 /* DMA Channels 15 (MDMA0 Destination) TX Interrupt */
-#define IRQ_WDOG 0x80000000 /* Software Watchdog Timer Interrupt */
-#define IRQ_PFB_PORTG 0x10000000 /* PF Port G (PF31:16) Interrupt B */
-#endif
-
-/* SIC_IAR0 Macros */
-#define P0_IVG(x) (((x)&0xF)-7) /* Peripheral #0 assigned IVG #x */
-#define P1_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #1 assigned IVG #x */
-#define P2_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #2 assigned IVG #x */
-#define P3_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #3 assigned IVG #x */
-#define P4_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #4 assigned IVG #x */
-#define P5_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #5 assigned IVG #x */
-#define P6_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #6 assigned IVG #x */
-#define P7_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #7 assigned IVG #x */
-
-/* SIC_IAR1 Macros */
-#define P8_IVG(x) (((x)&0xF)-7) /* Peripheral #8 assigned IVG #x */
-#define P9_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #9 assigned IVG #x */
-#define P10_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #10 assigned IVG #x */
-#define P11_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #11 assigned IVG #x */
-#define P12_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #12 assigned IVG #x */
-#define P13_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #13 assigned IVG #x */
-#define P14_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #14 assigned IVG #x */
-#define P15_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #15 assigned IVG #x */
-
-/* SIC_IAR2 Macros */
-#define P16_IVG(x) (((x)&0xF)-7) /* Peripheral #16 assigned IVG #x */
-#define P17_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #17 assigned IVG #x */
-#define P18_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #18 assigned IVG #x */
-#define P19_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #19 assigned IVG #x */
-#define P20_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #20 assigned IVG #x */
-#define P21_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #21 assigned IVG #x */
-#define P22_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #22 assigned IVG #x */
-#define P23_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #23 assigned IVG #x */
-
-/* SIC_IAR3 Macros */
-#define P24_IVG(x) (((x)&0xF)-7) /* Peripheral #24 assigned IVG #x */
-#define P25_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #25 assigned IVG #x */
-#define P26_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #26 assigned IVG #x */
-#define P27_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #27 assigned IVG #x */
-#define P28_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #28 assigned IVG #x */
-#define P29_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #29 assigned IVG #x */
-#define P30_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #30 assigned IVG #x */
-#define P31_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #31 assigned IVG #x */
-
-
-/* SIC_IMASK Masks */
-#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
-#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
-#define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
-#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
-
-/* SIC_IWR Masks */
-#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
-#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
-#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
-#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
-
-/* **************** GENERAL PURPOSE TIMER MASKS **********************/
-/* TIMER_ENABLE Masks */
-#define TIMEN0 0x0001 /* Enable Timer 0 */
-#define TIMEN1 0x0002 /* Enable Timer 1 */
-#define TIMEN2 0x0004 /* Enable Timer 2 */
-#define TIMEN3 0x0008 /* Enable Timer 3 */
-#define TIMEN4 0x0010 /* Enable Timer 4 */
-#define TIMEN5 0x0020 /* Enable Timer 5 */
-#define TIMEN6 0x0040 /* Enable Timer 6 */
-#define TIMEN7 0x0080 /* Enable Timer 7 */
-
-/* TIMER_DISABLE Masks */
-#define TIMDIS0 TIMEN0 /* Disable Timer 0 */
-#define TIMDIS1 TIMEN1 /* Disable Timer 1 */
-#define TIMDIS2 TIMEN2 /* Disable Timer 2 */
-#define TIMDIS3 TIMEN3 /* Disable Timer 3 */
-#define TIMDIS4 TIMEN4 /* Disable Timer 4 */
-#define TIMDIS5 TIMEN5 /* Disable Timer 5 */
-#define TIMDIS6 TIMEN6 /* Disable Timer 6 */
-#define TIMDIS7 TIMEN7 /* Disable Timer 7 */
-
-/* TIMER_STATUS Masks */
-#define TIMIL0 0x00000001 /* Timer 0 Interrupt */
-#define TIMIL1 0x00000002 /* Timer 1 Interrupt */
-#define TIMIL2 0x00000004 /* Timer 2 Interrupt */
-#define TIMIL3 0x00000008 /* Timer 3 Interrupt */
-#define TOVF_ERR0 0x00000010 /* Timer 0 Counter Overflow */
-#define TOVF_ERR1 0x00000020 /* Timer 1 Counter Overflow */
-#define TOVF_ERR2 0x00000040 /* Timer 2 Counter Overflow */
-#define TOVF_ERR3 0x00000080 /* Timer 3 Counter Overflow */
-#define TRUN0 0x00001000 /* Timer 0 Slave Enable Status */
-#define TRUN1 0x00002000 /* Timer 1 Slave Enable Status */
-#define TRUN2 0x00004000 /* Timer 2 Slave Enable Status */
-#define TRUN3 0x00008000 /* Timer 3 Slave Enable Status */
-#define TIMIL4 0x00010000 /* Timer 4 Interrupt */
-#define TIMIL5 0x00020000 /* Timer 5 Interrupt */
-#define TIMIL6 0x00040000 /* Timer 6 Interrupt */
-#define TIMIL7 0x00080000 /* Timer 7 Interrupt */
-#define TOVF_ERR4 0x00100000 /* Timer 4 Counter Overflow */
-#define TOVF_ERR5 0x00200000 /* Timer 5 Counter Overflow */
-#define TOVF_ERR6 0x00400000 /* Timer 6 Counter Overflow */
-#define TOVF_ERR7 0x00800000 /* Timer 7 Counter Overflow */
-#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */
-#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */
-#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */
-#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define TOVL_ERR0 TOVF_ERR0
-#define TOVL_ERR1 TOVF_ERR1
-#define TOVL_ERR2 TOVF_ERR2
-#define TOVL_ERR3 TOVF_ERR3
-#define TOVL_ERR4 TOVF_ERR4
-#define TOVL_ERR5 TOVF_ERR5
-#define TOVL_ERR6 TOVF_ERR6
-#define TOVL_ERR7 TOVF_ERR7
-
-/* TIMERx_CONFIG Masks */
-#define PWM_OUT 0x0001 /* Pulse-Width Modulation Output Mode */
-#define WDTH_CAP 0x0002 /* Width Capture Input Mode */
-#define EXT_CLK 0x0003 /* External Clock Mode */
-#define PULSE_HI 0x0004 /* Action Pulse (Positive/Negative*) */
-#define PERIOD_CNT 0x0008 /* Period Count */
-#define IRQ_ENA 0x0010 /* Interrupt Request Enable */
-#define TIN_SEL 0x0020 /* Timer Input Select */
-#define OUT_DIS 0x0040 /* Output Pad Disable */
-#define CLK_SEL 0x0080 /* Timer Clock Select */
-#define TOGGLE_HI 0x0100 /* PWM_OUT PULSE_HI Toggle Mode */
-#define EMU_RUN 0x0200 /* Emulation Behavior Select */
-#define ERR_TYP 0xC000 /* Error Type */
-
-/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/
-/* EBIU_AMGCTL Masks */
-#define AMCKEN 0x0001 /* Enable CLKOUT */
-#define AMBEN_NONE 0x0000 /* All Banks Disabled */
-#define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */
-#define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */
-#define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */
-#define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */
-
-/* EBIU_AMBCTL0 Masks */
-#define B0RDYEN 0x00000001 /* Bank 0 (B0) RDY Enable */
-#define B0RDYPOL 0x00000002 /* B0 RDY Active High */
-#define B0TT_1 0x00000004 /* B0 Transition Time (Read to Write) = 1 cycle */
-#define B0TT_2 0x00000008 /* B0 Transition Time (Read to Write) = 2 cycles */
-#define B0TT_3 0x0000000C /* B0 Transition Time (Read to Write) = 3 cycles */
-#define B0TT_4 0x00000000 /* B0 Transition Time (Read to Write) = 4 cycles */
-#define B0ST_1 0x00000010 /* B0 Setup Time (AOE to Read/Write) = 1 cycle */
-#define B0ST_2 0x00000020 /* B0 Setup Time (AOE to Read/Write) = 2 cycles */
-#define B0ST_3 0x00000030 /* B0 Setup Time (AOE to Read/Write) = 3 cycles */
-#define B0ST_4 0x00000000 /* B0 Setup Time (AOE to Read/Write) = 4 cycles */
-#define B0HT_1 0x00000040 /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle */
-#define B0HT_2 0x00000080 /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles */
-#define B0HT_3 0x000000C0 /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles */
-#define B0HT_0 0x00000000 /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles */
-#define B0RAT_1 0x00000100 /* B0 Read Access Time = 1 cycle */
-#define B0RAT_2 0x00000200 /* B0 Read Access Time = 2 cycles */
-#define B0RAT_3 0x00000300 /* B0 Read Access Time = 3 cycles */
-#define B0RAT_4 0x00000400 /* B0 Read Access Time = 4 cycles */
-#define B0RAT_5 0x00000500 /* B0 Read Access Time = 5 cycles */
-#define B0RAT_6 0x00000600 /* B0 Read Access Time = 6 cycles */
-#define B0RAT_7 0x00000700 /* B0 Read Access Time = 7 cycles */
-#define B0RAT_8 0x00000800 /* B0 Read Access Time = 8 cycles */
-#define B0RAT_9 0x00000900 /* B0 Read Access Time = 9 cycles */
-#define B0RAT_10 0x00000A00 /* B0 Read Access Time = 10 cycles */
-#define B0RAT_11 0x00000B00 /* B0 Read Access Time = 11 cycles */
-#define B0RAT_12 0x00000C00 /* B0 Read Access Time = 12 cycles */
-#define B0RAT_13 0x00000D00 /* B0 Read Access Time = 13 cycles */
-#define B0RAT_14 0x00000E00 /* B0 Read Access Time = 14 cycles */
-#define B0RAT_15 0x00000F00 /* B0 Read Access Time = 15 cycles */
-#define B0WAT_1 0x00001000 /* B0 Write Access Time = 1 cycle */
-#define B0WAT_2 0x00002000 /* B0 Write Access Time = 2 cycles */
-#define B0WAT_3 0x00003000 /* B0 Write Access Time = 3 cycles */
-#define B0WAT_4 0x00004000 /* B0 Write Access Time = 4 cycles */
-#define B0WAT_5 0x00005000 /* B0 Write Access Time = 5 cycles */
-#define B0WAT_6 0x00006000 /* B0 Write Access Time = 6 cycles */
-#define B0WAT_7 0x00007000 /* B0 Write Access Time = 7 cycles */
-#define B0WAT_8 0x00008000 /* B0 Write Access Time = 8 cycles */
-#define B0WAT_9 0x00009000 /* B0 Write Access Time = 9 cycles */
-#define B0WAT_10 0x0000A000 /* B0 Write Access Time = 10 cycles */
-#define B0WAT_11 0x0000B000 /* B0 Write Access Time = 11 cycles */
-#define B0WAT_12 0x0000C000 /* B0 Write Access Time = 12 cycles */
-#define B0WAT_13 0x0000D000 /* B0 Write Access Time = 13 cycles */
-#define B0WAT_14 0x0000E000 /* B0 Write Access Time = 14 cycles */
-#define B0WAT_15 0x0000F000 /* B0 Write Access Time = 15 cycles */
-
-#define B1RDYEN 0x00010000 /* Bank 1 (B1) RDY Enable */
-#define B1RDYPOL 0x00020000 /* B1 RDY Active High */
-#define B1TT_1 0x00040000 /* B1 Transition Time (Read to Write) = 1 cycle */
-#define B1TT_2 0x00080000 /* B1 Transition Time (Read to Write) = 2 cycles */
-#define B1TT_3 0x000C0000 /* B1 Transition Time (Read to Write) = 3 cycles */
-#define B1TT_4 0x00000000 /* B1 Transition Time (Read to Write) = 4 cycles */
-#define B1ST_1 0x00100000 /* B1 Setup Time (AOE to Read/Write) = 1 cycle */
-#define B1ST_2 0x00200000 /* B1 Setup Time (AOE to Read/Write) = 2 cycles */
-#define B1ST_3 0x00300000 /* B1 Setup Time (AOE to Read/Write) = 3 cycles */
-#define B1ST_4 0x00000000 /* B1 Setup Time (AOE to Read/Write) = 4 cycles */
-#define B1HT_1 0x00400000 /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle */
-#define B1HT_2 0x00800000 /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles */
-#define B1HT_3 0x00C00000 /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles */
-#define B1HT_0 0x00000000 /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles */
-#define B1RAT_1 0x01000000 /* B1 Read Access Time = 1 cycle */
-#define B1RAT_2 0x02000000 /* B1 Read Access Time = 2 cycles */
-#define B1RAT_3 0x03000000 /* B1 Read Access Time = 3 cycles */
-#define B1RAT_4 0x04000000 /* B1 Read Access Time = 4 cycles */
-#define B1RAT_5 0x05000000 /* B1 Read Access Time = 5 cycles */
-#define B1RAT_6 0x06000000 /* B1 Read Access Time = 6 cycles */
-#define B1RAT_7 0x07000000 /* B1 Read Access Time = 7 cycles */
-#define B1RAT_8 0x08000000 /* B1 Read Access Time = 8 cycles */
-#define B1RAT_9 0x09000000 /* B1 Read Access Time = 9 cycles */
-#define B1RAT_10 0x0A000000 /* B1 Read Access Time = 10 cycles */
-#define B1RAT_11 0x0B000000 /* B1 Read Access Time = 11 cycles */
-#define B1RAT_12 0x0C000000 /* B1 Read Access Time = 12 cycles */
-#define B1RAT_13 0x0D000000 /* B1 Read Access Time = 13 cycles */
-#define B1RAT_14 0x0E000000 /* B1 Read Access Time = 14 cycles */
-#define B1RAT_15 0x0F000000 /* B1 Read Access Time = 15 cycles */
-#define B1WAT_1 0x10000000 /* B1 Write Access Time = 1 cycle */
-#define B1WAT_2 0x20000000 /* B1 Write Access Time = 2 cycles */
-#define B1WAT_3 0x30000000 /* B1 Write Access Time = 3 cycles */
-#define B1WAT_4 0x40000000 /* B1 Write Access Time = 4 cycles */
-#define B1WAT_5 0x50000000 /* B1 Write Access Time = 5 cycles */
-#define B1WAT_6 0x60000000 /* B1 Write Access Time = 6 cycles */
-#define B1WAT_7 0x70000000 /* B1 Write Access Time = 7 cycles */
-#define B1WAT_8 0x80000000 /* B1 Write Access Time = 8 cycles */
-#define B1WAT_9 0x90000000 /* B1 Write Access Time = 9 cycles */
-#define B1WAT_10 0xA0000000 /* B1 Write Access Time = 10 cycles */
-#define B1WAT_11 0xB0000000 /* B1 Write Access Time = 11 cycles */
-#define B1WAT_12 0xC0000000 /* B1 Write Access Time = 12 cycles */
-#define B1WAT_13 0xD0000000 /* B1 Write Access Time = 13 cycles */
-#define B1WAT_14 0xE0000000 /* B1 Write Access Time = 14 cycles */
-#define B1WAT_15 0xF0000000 /* B1 Write Access Time = 15 cycles */
-
-/* EBIU_AMBCTL1 Masks */
-#define B2RDYEN 0x00000001 /* Bank 2 (B2) RDY Enable */
-#define B2RDYPOL 0x00000002 /* B2 RDY Active High */
-#define B2TT_1 0x00000004 /* B2 Transition Time (Read to Write) = 1 cycle */
-#define B2TT_2 0x00000008 /* B2 Transition Time (Read to Write) = 2 cycles */
-#define B2TT_3 0x0000000C /* B2 Transition Time (Read to Write) = 3 cycles */
-#define B2TT_4 0x00000000 /* B2 Transition Time (Read to Write) = 4 cycles */
-#define B2ST_1 0x00000010 /* B2 Setup Time (AOE to Read/Write) = 1 cycle */
-#define B2ST_2 0x00000020 /* B2 Setup Time (AOE to Read/Write) = 2 cycles */
-#define B2ST_3 0x00000030 /* B2 Setup Time (AOE to Read/Write) = 3 cycles */
-#define B2ST_4 0x00000000 /* B2 Setup Time (AOE to Read/Write) = 4 cycles */
-#define B2HT_1 0x00000040 /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle */
-#define B2HT_2 0x00000080 /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles */
-#define B2HT_3 0x000000C0 /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles */
-#define B2HT_0 0x00000000 /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles */
-#define B2RAT_1 0x00000100 /* B2 Read Access Time = 1 cycle */
-#define B2RAT_2 0x00000200 /* B2 Read Access Time = 2 cycles */
-#define B2RAT_3 0x00000300 /* B2 Read Access Time = 3 cycles */
-#define B2RAT_4 0x00000400 /* B2 Read Access Time = 4 cycles */
-#define B2RAT_5 0x00000500 /* B2 Read Access Time = 5 cycles */
-#define B2RAT_6 0x00000600 /* B2 Read Access Time = 6 cycles */
-#define B2RAT_7 0x00000700 /* B2 Read Access Time = 7 cycles */
-#define B2RAT_8 0x00000800 /* B2 Read Access Time = 8 cycles */
-#define B2RAT_9 0x00000900 /* B2 Read Access Time = 9 cycles */
-#define B2RAT_10 0x00000A00 /* B2 Read Access Time = 10 cycles */
-#define B2RAT_11 0x00000B00 /* B2 Read Access Time = 11 cycles */
-#define B2RAT_12 0x00000C00 /* B2 Read Access Time = 12 cycles */
-#define B2RAT_13 0x00000D00 /* B2 Read Access Time = 13 cycles */
-#define B2RAT_14 0x00000E00 /* B2 Read Access Time = 14 cycles */
-#define B2RAT_15 0x00000F00 /* B2 Read Access Time = 15 cycles */
-#define B2WAT_1 0x00001000 /* B2 Write Access Time = 1 cycle */
-#define B2WAT_2 0x00002000 /* B2 Write Access Time = 2 cycles */
-#define B2WAT_3 0x00003000 /* B2 Write Access Time = 3 cycles */
-#define B2WAT_4 0x00004000 /* B2 Write Access Time = 4 cycles */
-#define B2WAT_5 0x00005000 /* B2 Write Access Time = 5 cycles */
-#define B2WAT_6 0x00006000 /* B2 Write Access Time = 6 cycles */
-#define B2WAT_7 0x00007000 /* B2 Write Access Time = 7 cycles */
-#define B2WAT_8 0x00008000 /* B2 Write Access Time = 8 cycles */
-#define B2WAT_9 0x00009000 /* B2 Write Access Time = 9 cycles */
-#define B2WAT_10 0x0000A000 /* B2 Write Access Time = 10 cycles */
-#define B2WAT_11 0x0000B000 /* B2 Write Access Time = 11 cycles */
-#define B2WAT_12 0x0000C000 /* B2 Write Access Time = 12 cycles */
-#define B2WAT_13 0x0000D000 /* B2 Write Access Time = 13 cycles */
-#define B2WAT_14 0x0000E000 /* B2 Write Access Time = 14 cycles */
-#define B2WAT_15 0x0000F000 /* B2 Write Access Time = 15 cycles */
-
-#define B3RDYEN 0x00010000 /* Bank 3 (B3) RDY Enable */
-#define B3RDYPOL 0x00020000 /* B3 RDY Active High */
-#define B3TT_1 0x00040000 /* B3 Transition Time (Read to Write) = 1 cycle */
-#define B3TT_2 0x00080000 /* B3 Transition Time (Read to Write) = 2 cycles */
-#define B3TT_3 0x000C0000 /* B3 Transition Time (Read to Write) = 3 cycles */
-#define B3TT_4 0x00000000 /* B3 Transition Time (Read to Write) = 4 cycles */
-#define B3ST_1 0x00100000 /* B3 Setup Time (AOE to Read/Write) = 1 cycle */
-#define B3ST_2 0x00200000 /* B3 Setup Time (AOE to Read/Write) = 2 cycles */
-#define B3ST_3 0x00300000 /* B3 Setup Time (AOE to Read/Write) = 3 cycles */
-#define B3ST_4 0x00000000 /* B3 Setup Time (AOE to Read/Write) = 4 cycles */
-#define B3HT_1 0x00400000 /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle */
-#define B3HT_2 0x00800000 /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles */
-#define B3HT_3 0x00C00000 /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles */
-#define B3HT_0 0x00000000 /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles */
-#define B3RAT_1 0x01000000 /* B3 Read Access Time = 1 cycle */
-#define B3RAT_2 0x02000000 /* B3 Read Access Time = 2 cycles */
-#define B3RAT_3 0x03000000 /* B3 Read Access Time = 3 cycles */
-#define B3RAT_4 0x04000000 /* B3 Read Access Time = 4 cycles */
-#define B3RAT_5 0x05000000 /* B3 Read Access Time = 5 cycles */
-#define B3RAT_6 0x06000000 /* B3 Read Access Time = 6 cycles */
-#define B3RAT_7 0x07000000 /* B3 Read Access Time = 7 cycles */
-#define B3RAT_8 0x08000000 /* B3 Read Access Time = 8 cycles */
-#define B3RAT_9 0x09000000 /* B3 Read Access Time = 9 cycles */
-#define B3RAT_10 0x0A000000 /* B3 Read Access Time = 10 cycles */
-#define B3RAT_11 0x0B000000 /* B3 Read Access Time = 11 cycles */
-#define B3RAT_12 0x0C000000 /* B3 Read Access Time = 12 cycles */
-#define B3RAT_13 0x0D000000 /* B3 Read Access Time = 13 cycles */
-#define B3RAT_14 0x0E000000 /* B3 Read Access Time = 14 cycles */
-#define B3RAT_15 0x0F000000 /* B3 Read Access Time = 15 cycles */
-#define B3WAT_1 0x10000000 /* B3 Write Access Time = 1 cycle */
-#define B3WAT_2 0x20000000 /* B3 Write Access Time = 2 cycles */
-#define B3WAT_3 0x30000000 /* B3 Write Access Time = 3 cycles */
-#define B3WAT_4 0x40000000 /* B3 Write Access Time = 4 cycles */
-#define B3WAT_5 0x50000000 /* B3 Write Access Time = 5 cycles */
-#define B3WAT_6 0x60000000 /* B3 Write Access Time = 6 cycles */
-#define B3WAT_7 0x70000000 /* B3 Write Access Time = 7 cycles */
-#define B3WAT_8 0x80000000 /* B3 Write Access Time = 8 cycles */
-#define B3WAT_9 0x90000000 /* B3 Write Access Time = 9 cycles */
-#define B3WAT_10 0xA0000000 /* B3 Write Access Time = 10 cycles */
-#define B3WAT_11 0xB0000000 /* B3 Write Access Time = 11 cycles */
-#define B3WAT_12 0xC0000000 /* B3 Write Access Time = 12 cycles */
-#define B3WAT_13 0xD0000000 /* B3 Write Access Time = 13 cycles */
-#define B3WAT_14 0xE0000000 /* B3 Write Access Time = 14 cycles */
-#define B3WAT_15 0xF0000000 /* B3 Write Access Time = 15 cycles */
-
-
-/* ********************** SDRAM CONTROLLER MASKS **********************************************/
-/* EBIU_SDGCTL Masks */
-#define SCTLE 0x00000001 /* Enable SDRAM Signals */
-#define CL_2 0x00000008 /* SDRAM CAS Latency = 2 cycles */
-#define CL_3 0x0000000C /* SDRAM CAS Latency = 3 cycles */
-#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
-#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
-#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
-#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
-#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
-#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
-#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
-#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
-#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
-#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
-#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
-#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
-#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
-#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
-#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
-#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
-#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
-#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
-#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
-#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
-#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
-#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
-#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
-#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
-#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
-#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
-#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
-#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
-#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
-#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
-#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
-#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
-#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
-#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
-#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
-#define PUPSD 0x00200000 /* Power-Up Start Delay (15 SCLK Cycles Delay) */
-#define PSM 0x00400000 /* Power-Up Sequence (Mode Register Before/After* Refresh) */
-#define PSS 0x00800000 /* Enable Power-Up Sequence on Next SDRAM Access */
-#define SRFS 0x01000000 /* Enable SDRAM Self-Refresh Mode */
-#define EBUFE 0x02000000 /* Enable External Buffering Timing */
-#define FBBRW 0x04000000 /* Enable Fast Back-To-Back Read To Write */
-#define EMREN 0x10000000 /* Extended Mode Register Enable */
-#define TCSR 0x20000000 /* Temp-Compensated Self-Refresh Value (85/45* Deg C) */
-#define CDDBG 0x40000000 /* Tristate SDRAM Controls During Bus Grant */
-
-/* EBIU_SDBCTL Masks */
-#define EBE 0x0001 /* Enable SDRAM External Bank */
-#define EBSZ_16 0x0000 /* SDRAM External Bank Size = 16MB */
-#define EBSZ_32 0x0002 /* SDRAM External Bank Size = 32MB */
-#define EBSZ_64 0x0004 /* SDRAM External Bank Size = 64MB */
-#define EBSZ_128 0x0006 /* SDRAM External Bank Size = 128MB */
-#define EBSZ_256 0x0008 /* SDRAM External Bank Size = 256MB */
-#define EBSZ_512 0x000A /* SDRAM External Bank Size = 512MB */
-#define EBCAW_8 0x0000 /* SDRAM External Bank Column Address Width = 8 Bits */
-#define EBCAW_9 0x0010 /* SDRAM External Bank Column Address Width = 9 Bits */
-#define EBCAW_10 0x0020 /* SDRAM External Bank Column Address Width = 10 Bits */
-#define EBCAW_11 0x0030 /* SDRAM External Bank Column Address Width = 11 Bits */
-
-/* EBIU_SDSTAT Masks */
-#define SDCI 0x0001 /* SDRAM Controller Idle */
-#define SDSRA 0x0002 /* SDRAM Self-Refresh Active */
-#define SDPUA 0x0004 /* SDRAM Power-Up Active */
-#define SDRS 0x0008 /* SDRAM Will Power-Up On Next Access */
-#define SDEASE 0x0010 /* SDRAM EAB Sticky Error Status */
-#define BGSTAT 0x0020 /* Bus Grant Status */
-
-
-/* ************************** DMA CONTROLLER MASKS ********************************/
-
-/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
-#define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */
-#define PMAP 0xF000 /* Peripheral Mapped To This Channel */
-#define PMAP_PPI 0x0000 /* PPI Port DMA */
-#define PMAP_EMACRX 0x1000 /* Ethernet Receive DMA */
-#define PMAP_EMACTX 0x2000 /* Ethernet Transmit DMA */
-#define PMAP_SPORT0RX 0x3000 /* SPORT0 Receive DMA */
-#define PMAP_SPORT0TX 0x4000 /* SPORT0 Transmit DMA */
-#define PMAP_SPORT1RX 0x5000 /* SPORT1 Receive DMA */
-#define PMAP_SPORT1TX 0x6000 /* SPORT1 Transmit DMA */
-#define PMAP_SPI 0x7000 /* SPI Port DMA */
-#define PMAP_UART0RX 0x8000 /* UART0 Port Receive DMA */
-#define PMAP_UART0TX 0x9000 /* UART0 Port Transmit DMA */
-#define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */
-#define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */
-
-/* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
-/* PPI_CONTROL Masks */
-#define PORT_EN 0x0001 /* PPI Port Enable */
-#define PORT_DIR 0x0002 /* PPI Port Direction */
-#define XFR_TYPE 0x000C /* PPI Transfer Type */
-#define PORT_CFG 0x0030 /* PPI Port Configuration */
-#define FLD_SEL 0x0040 /* PPI Active Field Select */
-#define PACK_EN 0x0080 /* PPI Packing Mode */
-#define DMA32 0x0100 /* PPI 32-bit DMA Enable */
-#define SKIP_EN 0x0200 /* PPI Skip Element Enable */
-#define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */
-#define DLEN_8 0x0000 /* Data Length = 8 Bits */
-#define DLEN_10 0x0800 /* Data Length = 10 Bits */
-#define DLEN_11 0x1000 /* Data Length = 11 Bits */
-#define DLEN_12 0x1800 /* Data Length = 12 Bits */
-#define DLEN_13 0x2000 /* Data Length = 13 Bits */
-#define DLEN_14 0x2800 /* Data Length = 14 Bits */
-#define DLEN_15 0x3000 /* Data Length = 15 Bits */
-#define DLEN_16 0x3800 /* Data Length = 16 Bits */
-#define DLENGTH 0x3800 /* PPI Data Length */
-#define POLC 0x4000 /* PPI Clock Polarity */
-#define POLS 0x8000 /* PPI Frame Sync Polarity */
-
-/* PPI_STATUS Masks */
-#define FLD 0x0400 /* Field Indicator */
-#define FT_ERR 0x0800 /* Frame Track Error */
-#define OVR 0x1000 /* FIFO Overflow Error */
-#define UNDR 0x2000 /* FIFO Underrun Error */
-#define ERR_DET 0x4000 /* Error Detected Indicator */
-#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */
-
-
-/* ******************* PIN CONTROL REGISTER MASKS ************************/
-/* PORT_MUX Masks */
-#define PJSE 0x0001 /* Port J SPI/SPORT Enable */
-#define PJSE_SPORT 0x0000 /* Enable TFS0/DT0PRI */
-#define PJSE_SPI 0x0001 /* Enable SPI_SSEL3:2 */
-
-#define PJCE(x) (((x)&0x3)<<1) /* Port J CAN/SPI/SPORT Enable */
-#define PJCE_SPORT 0x0000 /* Enable DR0SEC/DT0SEC */
-#define PJCE_CAN 0x0002 /* Enable CAN RX/TX */
-#define PJCE_SPI 0x0004 /* Enable SPI_SSEL7 */
-
-#define PFDE 0x0008 /* Port F DMA Request Enable */
-#define PFDE_UART 0x0000 /* Enable UART0 RX/TX */
-#define PFDE_DMA 0x0008 /* Enable DMAR1:0 */
-
-#define PFTE 0x0010 /* Port F Timer Enable */
-#define PFTE_UART 0x0000 /* Enable UART1 RX/TX */
-#define PFTE_TIMER 0x0010 /* Enable TMR7:6 */
-
-#define PFS6E 0x0020 /* Port F SPI SSEL 6 Enable */
-#define PFS6E_TIMER 0x0000 /* Enable TMR5 */
-#define PFS6E_SPI 0x0020 /* Enable SPI_SSEL6 */
-
-#define PFS5E 0x0040 /* Port F SPI SSEL 5 Enable */
-#define PFS5E_TIMER 0x0000 /* Enable TMR4 */
-#define PFS5E_SPI 0x0040 /* Enable SPI_SSEL5 */
-
-#define PFS4E 0x0080 /* Port F SPI SSEL 4 Enable */
-#define PFS4E_TIMER 0x0000 /* Enable TMR3 */
-#define PFS4E_SPI 0x0080 /* Enable SPI_SSEL4 */
-
-#define PFFE 0x0100 /* Port F PPI Frame Sync Enable */
-#define PFFE_TIMER 0x0000 /* Enable TMR2 */
-#define PFFE_PPI 0x0100 /* Enable PPI FS3 */
-
-#define PGSE 0x0200 /* Port G SPORT1 Secondary Enable */
-#define PGSE_PPI 0x0000 /* Enable PPI D9:8 */
-#define PGSE_SPORT 0x0200 /* Enable DR1SEC/DT1SEC */
-
-#define PGRE 0x0400 /* Port G SPORT1 Receive Enable */
-#define PGRE_PPI 0x0000 /* Enable PPI D12:10 */
-#define PGRE_SPORT 0x0400 /* Enable DR1PRI/RFS1/RSCLK1 */
-
-#define PGTE 0x0800 /* Port G SPORT1 Transmit Enable */
-#define PGTE_PPI 0x0000 /* Enable PPI D15:13 */
-#define PGTE_SPORT 0x0800 /* Enable DT1PRI/TFS1/TSCLK1 */
-
-/* entry addresses of the user-callable Boot ROM functions */
-
-#define _BOOTROM_RESET 0xEF000000
-#define _BOOTROM_FINAL_INIT 0xEF000002
-#define _BOOTROM_DO_MEMORY_DMA 0xEF000006
-#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008
-#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A
-#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C
-#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010
-#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012
-#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define PGDE_UART PFDE_UART
-#define PGDE_DMA PFDE_DMA
-#define CKELOW SCKELOW
-
-/* HOST Port Registers */
-
-#define HOST_CONTROL 0xffc03400 /* HOST Control Register */
-#define HOST_STATUS 0xffc03404 /* HOST Status Register */
-#define HOST_TIMEOUT 0xffc03408 /* HOST Acknowledge Mode Timeout Register */
-
-/* Counter Registers */
-
-#define CNT_CONFIG 0xffc03500 /* Configuration Register */
-#define CNT_IMASK 0xffc03504 /* Interrupt Mask Register */
-#define CNT_STATUS 0xffc03508 /* Status Register */
-#define CNT_COMMAND 0xffc0350c /* Command Register */
-#define CNT_DEBOUNCE 0xffc03510 /* Debounce Register */
-#define CNT_COUNTER 0xffc03514 /* Counter Register */
-#define CNT_MAX 0xffc03518 /* Maximal Count Register */
-#define CNT_MIN 0xffc0351c /* Minimal Count Register */
-
-/* OTP/FUSE Registers */
-
-#define OTP_CONTROL 0xffc03600 /* OTP/Fuse Control Register */
-#define OTP_BEN 0xffc03604 /* OTP/Fuse Byte Enable */
-#define OTP_STATUS 0xffc03608 /* OTP/Fuse Status */
-#define OTP_TIMING 0xffc0360c /* OTP/Fuse Access Timing */
-
-/* Security Registers */
-
-#define SECURE_SYSSWT 0xffc03620 /* Secure System Switches */
-#define SECURE_CONTROL 0xffc03624 /* Secure Control */
-#define SECURE_STATUS 0xffc03628 /* Secure Status */
-
-/* OTP Read/Write Data Buffer Registers */
-
-#define OTP_DATA0 0xffc03680 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA1 0xffc03684 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA2 0xffc03688 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA3 0xffc0368c /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-
-/* Motor Control PWM Registers */
-
-#define PWM_CTRL 0xffc03700 /* PWM Control Register */
-#define PWM_STAT 0xffc03704 /* PWM Status Register */
-#define PWM_TM 0xffc03708 /* PWM Period Register */
-#define PWM_DT 0xffc0370c /* PWM Dead Time Register */
-#define PWM_GATE 0xffc03710 /* PWM Chopping Control */
-#define PWM_CHA 0xffc03714 /* PWM Channel A Duty Control */
-#define PWM_CHB 0xffc03718 /* PWM Channel B Duty Control */
-#define PWM_CHC 0xffc0371c /* PWM Channel C Duty Control */
-#define PWM_SEG 0xffc03720 /* PWM Crossover and Output Enable */
-#define PWM_SYNCWT 0xffc03724 /* PWM Sync Pluse Width Control */
-#define PWM_CHAL 0xffc03728 /* PWM Channel AL Duty Control (SR mode only) */
-#define PWM_CHBL 0xffc0372c /* PWM Channel BL Duty Control (SR mode only) */
-#define PWM_CHCL 0xffc03730 /* PWM Channel CL Duty Control (SR mode only) */
-#define PWM_LSI 0xffc03734 /* PWM Low Side Invert (SR mode only) */
-#define PWM_STAT2 0xffc03738 /* PWM Status Register 2 */
-
-
-/* ********************************************************** */
-/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
-/* and MULTI BIT READ MACROS */
-/* ********************************************************** */
-
-/* Bit masks for HOST_CONTROL */
-
-#define HOST_CNTR_HOST_EN 0x1 /* Host Enable */
-#define HOST_CNTR_nHOST_EN 0x0
-#define HOST_CNTR_HOST_END 0x2 /* Host Endianess */
-#define HOST_CNTR_nHOST_END 0x0
-#define HOST_CNTR_DATA_SIZE 0x4 /* Data Size */
-#define HOST_CNTR_nDATA_SIZE 0x0
-#define HOST_CNTR_HOST_RST 0x8 /* Host Reset */
-#define HOST_CNTR_nHOST_RST 0x0
-#define HOST_CNTR_HRDY_OVR 0x20 /* Host Ready Override */
-#define HOST_CNTR_nHRDY_OVR 0x0
-#define HOST_CNTR_INT_MODE 0x40 /* Interrupt Mode */
-#define HOST_CNTR_nINT_MODE 0x0
-#define HOST_CNTR_BT_EN 0x80 /* Bus Timeout Enable */
-#define HOST_CNTR_ nBT_EN 0x0
-#define HOST_CNTR_EHW 0x100 /* Enable Host Write */
-#define HOST_CNTR_nEHW 0x0
-#define HOST_CNTR_EHR 0x200 /* Enable Host Read */
-#define HOST_CNTR_nEHR 0x0
-#define HOST_CNTR_BDR 0x400 /* Burst DMA Requests */
-#define HOST_CNTR_nBDR 0x0
-
-/* Bit masks for HOST_STATUS */
-
-#define HOST_STAT_READY 0x1 /* DMA Ready */
-#define HOST_STAT_nREADY 0x0
-#define HOST_STAT_FIFOFULL 0x2 /* FIFO Full */
-#define HOST_STAT_nFIFOFULL 0x0
-#define HOST_STAT_FIFOEMPTY 0x4 /* FIFO Empty */
-#define HOST_STAT_nFIFOEMPTY 0x0
-#define HOST_STAT_COMPLETE 0x8 /* DMA Complete */
-#define HOST_STAT_nCOMPLETE 0x0
-#define HOST_STAT_HSHK 0x10 /* Host Handshake */
-#define HOST_STAT_nHSHK 0x0
-#define HOST_STAT_TIMEOUT 0x20 /* Host Timeout */
-#define HOST_STAT_nTIMEOUT 0x0
-#define HOST_STAT_HIRQ 0x40 /* Host Interrupt Request */
-#define HOST_STAT_nHIRQ 0x0
-#define HOST_STAT_ALLOW_CNFG 0x80 /* Allow New Configuration */
-#define HOST_STAT_nALLOW_CNFG 0x0
-#define HOST_STAT_DMA_DIR 0x100 /* DMA Direction */
-#define HOST_STAT_nDMA_DIR 0x0
-#define HOST_STAT_BTE 0x200 /* Bus Timeout Enabled */
-#define HOST_STAT_nBTE 0x0
-#define HOST_STAT_HOSTRD_DONE 0x8000 /* Host Read Completion Interrupt */
-#define HOST_STAT_nHOSTRD_DONE 0x0
-
-/* Bit masks for HOST_TIMEOUT */
-
-#define HOST_COUNT_TIMEOUT 0x7ff /* Host Timeout count */
-
-/* Bit masks for SECURE_SYSSWT */
-
-#define EMUDABL 0x1 /* Emulation Disable. */
-#define nEMUDABL 0x0
-#define RSTDABL 0x2 /* Reset Disable */
-#define nRSTDABL 0x0
-#define L1IDABL 0x1c /* L1 Instruction Memory Disable. */
-#define L1DADABL 0xe0 /* L1 Data Bank A Memory Disable. */
-#define L1DBDABL 0x700 /* L1 Data Bank B Memory Disable. */
-#define DMA0OVR 0x800 /* DMA0 Memory Access Override */
-#define nDMA0OVR 0x0
-#define DMA1OVR 0x1000 /* DMA1 Memory Access Override */
-#define nDMA1OVR 0x0
-#define EMUOVR 0x4000 /* Emulation Override */
-#define nEMUOVR 0x0
-#define OTPSEN 0x8000 /* OTP Secrets Enable. */
-#define nOTPSEN 0x0
-#define L2DABL 0x70000 /* L2 Memory Disable. */
-
-/* Bit masks for SECURE_CONTROL */
-
-#define SECURE0 0x1 /* SECURE 0 */
-#define nSECURE0 0x0
-#define SECURE1 0x2 /* SECURE 1 */
-#define nSECURE1 0x0
-#define SECURE2 0x4 /* SECURE 2 */
-#define nSECURE2 0x0
-#define SECURE3 0x8 /* SECURE 3 */
-#define nSECURE3 0x0
-
-/* Bit masks for SECURE_STATUS */
-
-#define SECMODE 0x3 /* Secured Mode Control State */
-#define NMI 0x4 /* Non Maskable Interrupt */
-#define nNMI 0x0
-#define AFVALID 0x8 /* Authentication Firmware Valid */
-#define nAFVALID 0x0
-#define AFEXIT 0x10 /* Authentication Firmware Exit */
-#define nAFEXIT 0x0
-#define SECSTAT 0xe0 /* Secure Status */
-
-#endif /* _DEF_BF512_H */
+++ /dev/null
-/*
- * Copyright 2008-2009 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF514_H
-#define _DEF_BF514_H
-
-/* BF514 is BF512 + RSI */
-#include "defBF512.h"
-
-/* Removable Storage Interface Registers */
-
-#define RSI_PWR_CONTROL 0xFFC03800 /* RSI Power Control Register */
-#define RSI_CLK_CONTROL 0xFFC03804 /* RSI Clock Control Register */
-#define RSI_ARGUMENT 0xFFC03808 /* RSI Argument Register */
-#define RSI_COMMAND 0xFFC0380C /* RSI Command Register */
-#define RSI_RESP_CMD 0xFFC03810 /* RSI Response Command Register */
-#define RSI_RESPONSE0 0xFFC03814 /* RSI Response Register */
-#define RSI_RESPONSE1 0xFFC03818 /* RSI Response Register */
-#define RSI_RESPONSE2 0xFFC0381C /* RSI Response Register */
-#define RSI_RESPONSE3 0xFFC03820 /* RSI Response Register */
-#define RSI_DATA_TIMER 0xFFC03824 /* RSI Data Timer Register */
-#define RSI_DATA_LGTH 0xFFC03828 /* RSI Data Length Register */
-#define RSI_DATA_CONTROL 0xFFC0382C /* RSI Data Control Register */
-#define RSI_DATA_CNT 0xFFC03830 /* RSI Data Counter Register */
-#define RSI_STATUS 0xFFC03834 /* RSI Status Register */
-#define RSI_STATUSCL 0xFFC03838 /* RSI Status Clear Register */
-#define RSI_MASK0 0xFFC0383C /* RSI Interrupt 0 Mask Register */
-#define RSI_MASK1 0xFFC03840 /* RSI Interrupt 1 Mask Register */
-#define RSI_FIFO_CNT 0xFFC03848 /* RSI FIFO Counter Register */
-#define RSI_CEATA_CONTROL 0xFFC0384C /* RSI CEATA Register */
-#define RSI_FIFO 0xFFC03880 /* RSI Data FIFO Register */
-#define RSI_ESTAT 0xFFC038C0 /* RSI Exception Status Register */
-#define RSI_EMASK 0xFFC038C4 /* RSI Exception Mask Register */
-#define RSI_CONFIG 0xFFC038C8 /* RSI Configuration Register */
-#define RSI_RD_WAIT_EN 0xFFC038CC /* RSI Read Wait Enable Register */
-#define RSI_PID0 0xFFC038D0 /* RSI Peripheral ID Register 0 */
-#define RSI_PID1 0xFFC038D4 /* RSI Peripheral ID Register 1 */
-#define RSI_PID2 0xFFC038D8 /* RSI Peripheral ID Register 2 */
-#define RSI_PID3 0xFFC038DC /* RSI Peripheral ID Register 3 */
-#define RSI_PID4 0xFFC038E0 /* RSI Peripheral ID Register 0 */
-#define RSI_PID5 0xFFC038E4 /* RSI Peripheral ID Register 1 */
-#define RSI_PID6 0xFFC038E8 /* RSI Peripheral ID Register 2 */
-#define RSI_PID7 0xFFC038EC /* RSI Peripheral ID Register 3 */
-
-#endif /* _DEF_BF514_H */
+++ /dev/null
-/*
- * Copyright 2008-2009 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF516_H
-#define _DEF_BF516_H
-
-/* BF516 is BF514 + EMAC */
-#include "defBF514.h"
-
-/* The following are the #defines needed by ADSP-BF516 that are not in the common header */
-/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
-
-#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */
-#define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */
-#define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */
-#define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */
-#define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */
-#define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */
-#define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */
-#define EMAC_FLC 0xFFC0301C /* Flow Control Register */
-#define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */
-#define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */
-#define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */
-#define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */
-#define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */
-#define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */
-#define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */
-#define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */
-#define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */
-#define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */
-#define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */
-
-#define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */
-#define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */
-#define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */
-#define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */
-#define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */
-#define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */
-#define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */
-#define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */
-
-#define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */
-#define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */
-#define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */
-#define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */
-#define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */
-
-#define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */
-#define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */
-#define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */
-#define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */
-#define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */
-#define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */
-#define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */
-#define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */
-#define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */
-#define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */
-#define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */
-#define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */
-#define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */
-#define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */
-#define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */
-#define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */
-#define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */
-#define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */
-#define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */
-#define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 < x < 128 */
-#define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
-#define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
-#define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
-#define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */
-
-#define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */
-#define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */
-#define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */
-#define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */
-#define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */
-#define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */
-#define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */
-#define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */
-#define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */
-#define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */
-#define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */
-#define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */
-#define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */
-#define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */
-#define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */
-#define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */
-#define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */
-#define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 < x < 128 */
-#define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
-#define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */
-#define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
-#define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */
-#define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */
-
-/* Listing for IEEE-Supported Count Registers */
-
-#define FramesReceivedOK EMAC_RXC_OK /* RX Frame Successful Count */
-#define FrameCheckSequenceErrors EMAC_RXC_FCS /* RX Frame FCS Failure Count */
-#define AlignmentErrors EMAC_RXC_ALIGN /* RX Alignment Error Count */
-#define OctetsReceivedOK EMAC_RXC_OCTET /* RX Octets Successfully Received Count */
-#define FramesLostDueToIntMACRcvError EMAC_RXC_DMAOVF /* Internal MAC Sublayer Error RX Frame Count */
-#define UnicastFramesReceivedOK EMAC_RXC_UNICST /* Unicast RX Frame Count */
-#define MulticastFramesReceivedOK EMAC_RXC_MULTI /* Multicast RX Frame Count */
-#define BroadcastFramesReceivedOK EMAC_RXC_BROAD /* Broadcast RX Frame Count */
-#define InRangeLengthErrors EMAC_RXC_LNERRI /* RX Frame In Range Error Count */
-#define OutOfRangeLengthField EMAC_RXC_LNERRO /* RX Frame Out Of Range Error Count */
-#define FrameTooLongErrors EMAC_RXC_LONG /* RX Frame Too Long Count */
-#define MACControlFramesReceived EMAC_RXC_MACCTL /* MAC Control RX Frame Count */
-#define UnsupportedOpcodesReceived EMAC_RXC_OPCODE /* Unsupported Op-Code RX Frame Count */
-#define PAUSEMACCtrlFramesReceived EMAC_RXC_PAUSE /* MAC Control Pause RX Frame Count */
-#define FramesReceivedAll EMAC_RXC_ALLFRM /* Overall RX Frame Count */
-#define OctetsReceivedAll EMAC_RXC_ALLOCT /* Overall RX Octet Count */
-#define TypedFramesReceived EMAC_RXC_TYPED /* Type/Length Consistent RX Frame Count */
-#define FramesLenLt64Received EMAC_RXC_SHORT /* RX Frame Fragment Count - Byte Count x < 64 */
-#define FramesLenEq64Received EMAC_RXC_EQ64 /* Good RX Frame Count - Byte Count x = 64 */
-#define FramesLen65_127Received EMAC_RXC_LT128 /* Good RX Frame Count - Byte Count 64 < x < 128 */
-#define FramesLen128_255Received EMAC_RXC_LT256 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
-#define FramesLen256_511Received EMAC_RXC_LT512 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
-#define FramesLen512_1023Received EMAC_RXC_LT1024 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
-#define FramesLen1024_MaxReceived EMAC_RXC_GE1024 /* Good RX Frame Count - Byte Count x >= 1024 */
-
-#define FramesTransmittedOK EMAC_TXC_OK /* TX Frame Successful Count */
-#define SingleCollisionFrames EMAC_TXC_1COL /* TX Frames Successful After Single Collision Count */
-#define MultipleCollisionFrames EMAC_TXC_GT1COL /* TX Frames Successful After Multiple Collisions Count */
-#define OctetsTransmittedOK EMAC_TXC_OCTET /* TX Octets Successfully Received Count */
-#define FramesWithDeferredXmissions EMAC_TXC_DEFER /* TX Frame Delayed Due To Busy Count */
-#define LateCollisions EMAC_TXC_LATECL /* Late TX Collisions Count */
-#define FramesAbortedDueToXSColls EMAC_TXC_XS_COL /* TX Frame Failed Due To Excessive Collisions Count */
-#define FramesLostDueToIntMacXmitError EMAC_TXC_DMAUND /* Internal MAC Sublayer Error TX Frame Count */
-#define CarrierSenseErrors EMAC_TXC_CRSERR /* Carrier Sense Deasserted During TX Frame Count */
-#define UnicastFramesXmittedOK EMAC_TXC_UNICST /* Unicast TX Frame Count */
-#define MulticastFramesXmittedOK EMAC_TXC_MULTI /* Multicast TX Frame Count */
-#define BroadcastFramesXmittedOK EMAC_TXC_BROAD /* Broadcast TX Frame Count */
-#define FramesWithExcessiveDeferral EMAC_TXC_XS_DFR /* TX Frames With Excessive Deferral Count */
-#define MACControlFramesTransmitted EMAC_TXC_MACCTL /* MAC Control TX Frame Count */
-#define FramesTransmittedAll EMAC_TXC_ALLFRM /* Overall TX Frame Count */
-#define OctetsTransmittedAll EMAC_TXC_ALLOCT /* Overall TX Octet Count */
-#define FramesLenEq64Transmitted EMAC_TXC_EQ64 /* Good TX Frame Count - Byte Count x = 64 */
-#define FramesLen65_127Transmitted EMAC_TXC_LT128 /* Good TX Frame Count - Byte Count 64 < x < 128 */
-#define FramesLen128_255Transmitted EMAC_TXC_LT256 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
-#define FramesLen256_511Transmitted EMAC_TXC_LT512 /* Good TX Frame Count - Byte Count 256 <= x < 512 */
-#define FramesLen512_1023Transmitted EMAC_TXC_LT1024 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
-#define FramesLen1024_MaxTransmitted EMAC_TXC_GE1024 /* Good TX Frame Count - Byte Count x >= 1024 */
-#define TxAbortedFrames EMAC_TXC_ABORT /* Total TX Frames Aborted Count */
-
-/***********************************************************************************
-** System MMR Register Bits And Macros
-**
-** Disclaimer: All macros are intended to make C and Assembly code more readable.
-** Use these macros carefully, as any that do left shifts for field
-** depositing will result in the lower order bits being destroyed. Any
-** macro that shifts left to properly position the bit-field should be
-** used as part of an OR to initialize a register and NOT as a dynamic
-** modifier UNLESS the lower order bits are saved and ORed back in when
-** the macro is used.
-*************************************************************************************/
-
-/************************ ETHERNET 10/100 CONTROLLER MASKS ************************/
-
-/* EMAC_OPMODE Masks */
-
-#define RE 0x00000001 /* Receiver Enable */
-#define ASTP 0x00000002 /* Enable Automatic Pad Stripping On RX Frames */
-#define HU 0x00000010 /* Hash Filter Unicast Address */
-#define HM 0x00000020 /* Hash Filter Multicast Address */
-#define PAM 0x00000040 /* Pass-All-Multicast Mode Enable */
-#define PR 0x00000080 /* Promiscuous Mode Enable */
-#define IFE 0x00000100 /* Inverse Filtering Enable */
-#define DBF 0x00000200 /* Disable Broadcast Frame Reception */
-#define PBF 0x00000400 /* Pass Bad Frames Enable */
-#define PSF 0x00000800 /* Pass Short Frames Enable */
-#define RAF 0x00001000 /* Receive-All Mode */
-#define TE 0x00010000 /* Transmitter Enable */
-#define DTXPAD 0x00020000 /* Disable Automatic TX Padding */
-#define DTXCRC 0x00040000 /* Disable Automatic TX CRC Generation */
-#define DC 0x00080000 /* Deferral Check */
-#define BOLMT 0x00300000 /* Back-Off Limit */
-#define BOLMT_10 0x00000000 /* 10-bit range */
-#define BOLMT_8 0x00100000 /* 8-bit range */
-#define BOLMT_4 0x00200000 /* 4-bit range */
-#define BOLMT_1 0x00300000 /* 1-bit range */
-#define DRTY 0x00400000 /* Disable TX Retry On Collision */
-#define LCTRE 0x00800000 /* Enable TX Retry On Late Collision */
-#define RMII 0x01000000 /* RMII/MII* Mode */
-#define RMII_10 0x02000000 /* Speed Select for RMII Port (10MBit/100MBit*) */
-#define FDMODE 0x04000000 /* Duplex Mode Enable (Full/Half*) */
-#define LB 0x08000000 /* Internal Loopback Enable */
-#define DRO 0x10000000 /* Disable Receive Own Frames (Half-Duplex Mode) */
-
-/* EMAC_STAADD Masks */
-
-#define STABUSY 0x00000001 /* Initiate Station Mgt Reg Access / STA Busy Stat */
-#define STAOP 0x00000002 /* Station Management Operation Code (Write/Read*) */
-#define STADISPRE 0x00000004 /* Disable Preamble Generation */
-#define STAIE 0x00000008 /* Station Mgt. Transfer Done Interrupt Enable */
-#define REGAD 0x000007C0 /* STA Register Address */
-#define PHYAD 0x0000F800 /* PHY Device Address */
-
-#define SET_REGAD(x) (((x)&0x1F)<< 6 ) /* Set STA Register Address */
-#define SET_PHYAD(x) (((x)&0x1F)<< 11 ) /* Set PHY Device Address */
-
-/* EMAC_STADAT Mask */
-
-#define STADATA 0x0000FFFF /* Station Management Data */
-
-/* EMAC_FLC Masks */
-
-#define FLCBUSY 0x00000001 /* Send Flow Ctrl Frame / Flow Ctrl Busy Status */
-#define FLCE 0x00000002 /* Flow Control Enable */
-#define PCF 0x00000004 /* Pass Control Frames */
-#define BKPRSEN 0x00000008 /* Enable Backpressure */
-#define FLCPAUSE 0xFFFF0000 /* Pause Time */
-
-#define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time */
-
-/* EMAC_WKUP_CTL Masks */
-
-#define CAPWKFRM 0x00000001 /* Capture Wake-Up Frames */
-#define MPKE 0x00000002 /* Magic Packet Enable */
-#define RWKE 0x00000004 /* Remote Wake-Up Frame Enable */
-#define GUWKE 0x00000008 /* Global Unicast Wake Enable */
-#define MPKS 0x00000020 /* Magic Packet Received Status */
-#define RWKS 0x00000F00 /* Wake-Up Frame Received Status, Filters 3:0 */
-
-/* EMAC_WKUP_FFCMD Masks */
-
-#define WF0_E 0x00000001 /* Enable Wake-Up Filter 0 */
-#define WF0_T 0x00000008 /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*) */
-#define WF1_E 0x00000100 /* Enable Wake-Up Filter 1 */
-#define WF1_T 0x00000800 /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*) */
-#define WF2_E 0x00010000 /* Enable Wake-Up Filter 2 */
-#define WF2_T 0x00080000 /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*) */
-#define WF3_E 0x01000000 /* Enable Wake-Up Filter 3 */
-#define WF3_T 0x08000000 /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*) */
-
-/* EMAC_WKUP_FFOFF Masks */
-
-#define WF0_OFF 0x000000FF /* Wake-Up Filter 0 Pattern Offset */
-#define WF1_OFF 0x0000FF00 /* Wake-Up Filter 1 Pattern Offset */
-#define WF2_OFF 0x00FF0000 /* Wake-Up Filter 2 Pattern Offset */
-#define WF3_OFF 0xFF000000 /* Wake-Up Filter 3 Pattern Offset */
-
-#define SET_WF0_OFF(x) (((x)&0xFF)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */
-#define SET_WF1_OFF(x) (((x)&0xFF)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */
-#define SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */
-#define SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */
-/* Set ALL Offsets */
-#define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3)))
-
-/* EMAC_WKUP_FFCRC0 Masks */
-
-#define WF0_CRC 0x0000FFFF /* Wake-Up Filter 0 Pattern CRC */
-#define WF1_CRC 0xFFFF0000 /* Wake-Up Filter 1 Pattern CRC */
-
-#define SET_WF0_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 0 Target CRC */
-#define SET_WF1_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 1 Target CRC */
-
-/* EMAC_WKUP_FFCRC1 Masks */
-
-#define WF2_CRC 0x0000FFFF /* Wake-Up Filter 2 Pattern CRC */
-#define WF3_CRC 0xFFFF0000 /* Wake-Up Filter 3 Pattern CRC */
-
-#define SET_WF2_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 2 Target CRC */
-#define SET_WF3_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 3 Target CRC */
-
-/* EMAC_SYSCTL Masks */
-
-#define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */
-#define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */
-#define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */
-#define TXDWA 0x00000010 /* Transmit Frame DMA Word Alignment (Odd/Even*) */
-#define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */
-
-#define SET_MDCDIV(x) (((x)&0x3F)<< 8) /* Set MDC Clock Divisor */
-
-/* EMAC_SYSTAT Masks */
-
-#define PHYINT 0x00000001 /* PHY_INT Interrupt Status */
-#define MMCINT 0x00000002 /* MMC Counter Interrupt Status */
-#define RXFSINT 0x00000004 /* RX Frame-Status Interrupt Status */
-#define TXFSINT 0x00000008 /* TX Frame-Status Interrupt Status */
-#define WAKEDET 0x00000010 /* Wake-Up Detected Status */
-#define RXDMAERR 0x00000020 /* RX DMA Direction Error Status */
-#define TXDMAERR 0x00000040 /* TX DMA Direction Error Status */
-#define STMDONE 0x00000080 /* Station Mgt. Transfer Done Interrupt Status */
-
-/* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */
-
-#define RX_FRLEN 0x000007FF /* Frame Length In Bytes */
-#define RX_COMP 0x00001000 /* RX Frame Complete */
-#define RX_OK 0x00002000 /* RX Frame Received With No Errors */
-#define RX_LONG 0x00004000 /* RX Frame Too Long Error */
-#define RX_ALIGN 0x00008000 /* RX Frame Alignment Error */
-#define RX_CRC 0x00010000 /* RX Frame CRC Error */
-#define RX_LEN 0x00020000 /* RX Frame Length Error */
-#define RX_FRAG 0x00040000 /* RX Frame Fragment Error */
-#define RX_ADDR 0x00080000 /* RX Frame Address Filter Failed Error */
-#define RX_DMAO 0x00100000 /* RX Frame DMA Overrun Error */
-#define RX_PHY 0x00200000 /* RX Frame PHY Error */
-#define RX_LATE 0x00400000 /* RX Frame Late Collision Error */
-#define RX_RANGE 0x00800000 /* RX Frame Length Field Out of Range Error */
-#define RX_MULTI 0x01000000 /* RX Multicast Frame Indicator */
-#define RX_BROAD 0x02000000 /* RX Broadcast Frame Indicator */
-#define RX_CTL 0x04000000 /* RX Control Frame Indicator */
-#define RX_UCTL 0x08000000 /* Unsupported RX Control Frame Indicator */
-#define RX_TYPE 0x10000000 /* RX Typed Frame Indicator */
-#define RX_VLAN1 0x20000000 /* RX VLAN1 Frame Indicator */
-#define RX_VLAN2 0x40000000 /* RX VLAN2 Frame Indicator */
-#define RX_ACCEPT 0x80000000 /* RX Frame Accepted Indicator */
-
-/* EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks */
-
-#define TX_COMP 0x00000001 /* TX Frame Complete */
-#define TX_OK 0x00000002 /* TX Frame Sent With No Errors */
-#define TX_ECOLL 0x00000004 /* TX Frame Excessive Collision Error */
-#define TX_LATE 0x00000008 /* TX Frame Late Collision Error */
-#define TX_DMAU 0x00000010 /* TX Frame DMA Underrun Error (STAT) */
-#define TX_MACE 0x00000010 /* Internal MAC Error Detected (STKY and IRQE) */
-#define TX_EDEFER 0x00000020 /* TX Frame Excessive Deferral Error */
-#define TX_BROAD 0x00000040 /* TX Broadcast Frame Indicator */
-#define TX_MULTI 0x00000080 /* TX Multicast Frame Indicator */
-#define TX_CCNT 0x00000F00 /* TX Frame Collision Count */
-#define TX_DEFER 0x00001000 /* TX Frame Deferred Indicator */
-#define TX_CRS 0x00002000 /* TX Frame Carrier Sense Not Asserted Error */
-#define TX_LOSS 0x00004000 /* TX Frame Carrier Lost During TX Error */
-#define TX_RETRY 0x00008000 /* TX Frame Successful After Retry */
-#define TX_FRLEN 0x07FF0000 /* TX Frame Length (Bytes) */
-
-/* EMAC_MMC_CTL Masks */
-#define RSTC 0x00000001 /* Reset All Counters */
-#define CROLL 0x00000002 /* Counter Roll-Over Enable */
-#define CCOR 0x00000004 /* Counter Clear-On-Read Mode Enable */
-#define MMCE 0x00000008 /* Enable MMC Counter Operation */
-
-/* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */
-#define RX_OK_CNT 0x00000001 /* RX Frames Received With No Errors */
-#define RX_FCS_CNT 0x00000002 /* RX Frames W/Frame Check Sequence Errors */
-#define RX_ALIGN_CNT 0x00000004 /* RX Frames With Alignment Errors */
-#define RX_OCTET_CNT 0x00000008 /* RX Octets Received OK */
-#define RX_LOST_CNT 0x00000010 /* RX Frames Lost Due To Internal MAC RX Error */
-#define RX_UNI_CNT 0x00000020 /* Unicast RX Frames Received OK */
-#define RX_MULTI_CNT 0x00000040 /* Multicast RX Frames Received OK */
-#define RX_BROAD_CNT 0x00000080 /* Broadcast RX Frames Received OK */
-#define RX_IRL_CNT 0x00000100 /* RX Frames With In-Range Length Errors */
-#define RX_ORL_CNT 0x00000200 /* RX Frames With Out-Of-Range Length Errors */
-#define RX_LONG_CNT 0x00000400 /* RX Frames With Frame Too Long Errors */
-#define RX_MACCTL_CNT 0x00000800 /* MAC Control RX Frames Received */
-#define RX_OPCODE_CTL 0x00001000 /* Unsupported Op-Code RX Frames Received */
-#define RX_PAUSE_CNT 0x00002000 /* PAUSEMAC Control RX Frames Received */
-#define RX_ALLF_CNT 0x00004000 /* All RX Frames Received */
-#define RX_ALLO_CNT 0x00008000 /* All RX Octets Received */
-#define RX_TYPED_CNT 0x00010000 /* Typed RX Frames Received */
-#define RX_SHORT_CNT 0x00020000 /* RX Frame Fragments (< 64 Bytes) Received */
-#define RX_EQ64_CNT 0x00040000 /* 64-Byte RX Frames Received */
-#define RX_LT128_CNT 0x00080000 /* 65-127-Byte RX Frames Received */
-#define RX_LT256_CNT 0x00100000 /* 128-255-Byte RX Frames Received */
-#define RX_LT512_CNT 0x00200000 /* 256-511-Byte RX Frames Received */
-#define RX_LT1024_CNT 0x00400000 /* 512-1023-Byte RX Frames Received */
-#define RX_GE1024_CNT 0x00800000 /* 1024-Max-Byte RX Frames Received */
-
-/* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */
-
-#define TX_OK_CNT 0x00000001 /* TX Frames Sent OK */
-#define TX_SCOLL_CNT 0x00000002 /* TX Frames With Single Collisions */
-#define TX_MCOLL_CNT 0x00000004 /* TX Frames With Multiple Collisions */
-#define TX_OCTET_CNT 0x00000008 /* TX Octets Sent OK */
-#define TX_DEFER_CNT 0x00000010 /* TX Frames With Deferred Transmission */
-#define TX_LATE_CNT 0x00000020 /* TX Frames With Late Collisions */
-#define TX_ABORTC_CNT 0x00000040 /* TX Frames Aborted Due To Excess Collisions */
-#define TX_LOST_CNT 0x00000080 /* TX Frames Lost Due To Internal MAC TX Error */
-#define TX_CRS_CNT 0x00000100 /* TX Frames With Carrier Sense Errors */
-#define TX_UNI_CNT 0x00000200 /* Unicast TX Frames Sent */
-#define TX_MULTI_CNT 0x00000400 /* Multicast TX Frames Sent */
-#define TX_BROAD_CNT 0x00000800 /* Broadcast TX Frames Sent */
-#define TX_EXDEF_CTL 0x00001000 /* TX Frames With Excessive Deferral */
-#define TX_MACCTL_CNT 0x00002000 /* MAC Control TX Frames Sent */
-#define TX_ALLF_CNT 0x00004000 /* All TX Frames Sent */
-#define TX_ALLO_CNT 0x00008000 /* All TX Octets Sent */
-#define TX_EQ64_CNT 0x00010000 /* 64-Byte TX Frames Sent */
-#define TX_LT128_CNT 0x00020000 /* 65-127-Byte TX Frames Sent */
-#define TX_LT256_CNT 0x00040000 /* 128-255-Byte TX Frames Sent */
-#define TX_LT512_CNT 0x00080000 /* 256-511-Byte TX Frames Sent */
-#define TX_LT1024_CNT 0x00100000 /* 512-1023-Byte TX Frames Sent */
-#define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */
-#define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */
-
-#endif /* _DEF_BF516_H */
+++ /dev/null
-/*
- * Copyright 2008-2009 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF518_H
-#define _DEF_BF518_H
-
-/* BF518 is BF516 + IEEE-1588 */
-#include "defBF516.h"
-
-/* PTP TSYNC Registers */
-
-#define EMAC_PTP_CTL 0xFFC030A0 /* PTP Block Control */
-#define EMAC_PTP_IE 0xFFC030A4 /* PTP Block Interrupt Enable */
-#define EMAC_PTP_ISTAT 0xFFC030A8 /* PTP Block Interrupt Status */
-#define EMAC_PTP_FOFF 0xFFC030AC /* PTP Filter offset Register */
-#define EMAC_PTP_FV1 0xFFC030B0 /* PTP Filter Value Register 1 */
-#define EMAC_PTP_FV2 0xFFC030B4 /* PTP Filter Value Register 2 */
-#define EMAC_PTP_FV3 0xFFC030B8 /* PTP Filter Value Register 3 */
-#define EMAC_PTP_ADDEND 0xFFC030BC /* PTP Addend for Frequency Compensation */
-#define EMAC_PTP_ACCR 0xFFC030C0 /* PTP Accumulator for Frequency Compensation */
-#define EMAC_PTP_OFFSET 0xFFC030C4 /* PTP Time Offset Register */
-#define EMAC_PTP_TIMELO 0xFFC030C8 /* PTP Precision Clock Time Low */
-#define EMAC_PTP_TIMEHI 0xFFC030CC /* PTP Precision Clock Time High */
-#define EMAC_PTP_RXSNAPLO 0xFFC030D0 /* PTP Receive Snapshot Register Low */
-#define EMAC_PTP_RXSNAPHI 0xFFC030D4 /* PTP Receive Snapshot Register High */
-#define EMAC_PTP_TXSNAPLO 0xFFC030D8 /* PTP Transmit Snapshot Register Low */
-#define EMAC_PTP_TXSNAPHI 0xFFC030DC /* PTP Transmit Snapshot Register High */
-#define EMAC_PTP_ALARMLO 0xFFC030E0 /* PTP Alarm time Low */
-#define EMAC_PTP_ALARMHI 0xFFC030E4 /* PTP Alarm time High */
-#define EMAC_PTP_ID_OFF 0xFFC030E8 /* PTP Capture ID offset register */
-#define EMAC_PTP_ID_SNAP 0xFFC030EC /* PTP Capture ID register */
-#define EMAC_PTP_PPS_STARTLO 0xFFC030F0 /* PPS Start Time Low */
-#define EMAC_PTP_PPS_STARTHI 0xFFC030F4 /* PPS Start Time High */
-#define EMAC_PTP_PPS_PERIOD 0xFFC030F8 /* PPS Count Register */
-
-/* Bit masks for EMAC_PTP_CTL */
-
-#define PTP_EN 0x1 /* Enable the PTP_TSYNC module */
-#define TL 0x2 /* Timestamp lock control */
-#define ASEN 0x10 /* Auxiliary snapshot control */
-#define PPSEN 0x80 /* Pulse-per-second (PPS) control */
-#define CKOEN 0x2000 /* Clock output control */
-
-/* Bit masks for EMAC_PTP_IE */
-
-#define ALIE 0x1 /* Alarm interrupt enable */
-#define RXEIE 0x2 /* Receive event interrupt enable */
-#define RXGIE 0x4 /* Receive general interrupt enable */
-#define TXIE 0x8 /* Transmit interrupt enable */
-#define RXOVE 0x10 /* Receive overrun error interrupt enable */
-#define TXOVE 0x20 /* Transmit overrun error interrupt enable */
-#define ASIE 0x40 /* Auxiliary snapshot interrupt enable */
-
-/* Bit masks for EMAC_PTP_ISTAT */
-
-#define ALS 0x1 /* Alarm status */
-#define RXEL 0x2 /* Receive event interrupt status */
-#define RXGL 0x4 /* Receive general interrupt status */
-#define TXTL 0x8 /* Transmit snapshot status */
-#define RXOV 0x10 /* Receive snapshot overrun status */
-#define TXOV 0x20 /* Transmit snapshot overrun status */
-#define ASL 0x40 /* Auxiliary snapshot interrupt status */
-
-#endif /* _DEF_BF518_H */
+++ /dev/null
-/* mach/dma.h - arch-specific DMA defines
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_DMA_H_
-#define _MACH_DMA_H_
-
-#define MAX_DMA_CHANNELS 16
-
-#define CH_PPI 0 /* PPI receive/transmit */
-#define CH_EMAC_RX 1 /* Ethernet MAC receive */
-#define CH_EMAC_TX 2 /* Ethernet MAC transmit */
-#define CH_SPORT0_RX 3 /* SPORT0 receive */
-#define CH_SPORT0_TX 4 /* SPORT0 transmit */
-#define CH_RSI 4 /* RSI */
-#define CH_SPORT1_RX 5 /* SPORT1 receive */
-#define CH_SPI1 5 /* SPI1 transmit/receive */
-#define CH_SPORT1_TX 6 /* SPORT1 transmit */
-#define CH_SPI0 7 /* SPI0 transmit/receive */
-#define CH_UART0_RX 8 /* UART0 receive */
-#define CH_UART0_TX 9 /* UART0 transmit */
-#define CH_UART1_RX 10 /* UART1 receive */
-#define CH_UART1_TX 11 /* UART1 transmit */
-
-#define CH_MEM_STREAM0_SRC 12 /* RX */
-#define CH_MEM_STREAM0_DEST 13 /* TX */
-#define CH_MEM_STREAM1_SRC 14 /* RX */
-#define CH_MEM_STREAM1_DEST 15 /* TX */
-
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2008 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-
-#ifndef _MACH_GPIO_H_
-#define _MACH_GPIO_H_
-
-#define MAX_BLACKFIN_GPIOS 41
-
-#define GPIO_PF0 0
-#define GPIO_PF1 1
-#define GPIO_PF2 2
-#define GPIO_PF3 3
-#define GPIO_PF4 4
-#define GPIO_PF5 5
-#define GPIO_PF6 6
-#define GPIO_PF7 7
-#define GPIO_PF8 8
-#define GPIO_PF9 9
-#define GPIO_PF10 10
-#define GPIO_PF11 11
-#define GPIO_PF12 12
-#define GPIO_PF13 13
-#define GPIO_PF14 14
-#define GPIO_PF15 15
-#define GPIO_PG0 16
-#define GPIO_PG1 17
-#define GPIO_PG2 18
-#define GPIO_PG3 19
-#define GPIO_PG4 20
-#define GPIO_PG5 21
-#define GPIO_PG6 22
-#define GPIO_PG7 23
-#define GPIO_PG8 24
-#define GPIO_PG9 25
-#define GPIO_PG10 26
-#define GPIO_PG11 27
-#define GPIO_PG12 28
-#define GPIO_PG13 29
-#define GPIO_PG14 30
-#define GPIO_PG15 31
-#define GPIO_PH0 32
-#define GPIO_PH1 33
-#define GPIO_PH2 34
-#define GPIO_PH3 35
-#define GPIO_PH4 36
-#define GPIO_PH5 37
-#define GPIO_PH6 38
-#define GPIO_PH7 39
-#define GPIO_PH8 40
-
-#define PORT_F GPIO_PF0
-#define PORT_G GPIO_PG0
-#define PORT_H GPIO_PH0
-
-#include <mach-common/ports-f.h>
-#include <mach-common/ports-g.h>
-#include <mach-common/ports-h.h>
-
-#endif /* _MACH_GPIO_H_ */
+++ /dev/null
-/*
- * Copyright 2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _BF518_IRQ_H_
-#define _BF518_IRQ_H_
-
-#include <mach-common/irq.h>
-
-#define NR_PERI_INTS (2 * 32)
-
-#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
-#define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */
-#define IRQ_DMAR0_BLK BFIN_IRQ(2) /* DMAR0 Block Interrupt */
-#define IRQ_DMAR1_BLK BFIN_IRQ(3) /* DMAR1 Block Interrupt */
-#define IRQ_DMAR0_OVR BFIN_IRQ(4) /* DMAR0 Overflow Error */
-#define IRQ_DMAR1_OVR BFIN_IRQ(5) /* DMAR1 Overflow Error */
-#define IRQ_PPI_ERROR BFIN_IRQ(6) /* PPI Error */
-#define IRQ_MAC_ERROR BFIN_IRQ(7) /* MAC Status */
-#define IRQ_SPORT0_ERROR BFIN_IRQ(8) /* SPORT0 Status */
-#define IRQ_SPORT1_ERROR BFIN_IRQ(9) /* SPORT1 Status */
-#define IRQ_PTP_ERROR BFIN_IRQ(10) /* PTP Error Interrupt */
-#define IRQ_UART0_ERROR BFIN_IRQ(12) /* UART0 Status */
-#define IRQ_UART1_ERROR BFIN_IRQ(13) /* UART1 Status */
-#define IRQ_RTC BFIN_IRQ(14) /* RTC */
-#define IRQ_PPI BFIN_IRQ(15) /* DMA Channel 0 (PPI) */
-#define IRQ_SPORT0_RX BFIN_IRQ(16) /* DMA 3 Channel (SPORT0 RX) */
-#define IRQ_SPORT0_TX BFIN_IRQ(17) /* DMA 4 Channel (SPORT0 TX) */
-#define IRQ_RSI BFIN_IRQ(17) /* DMA 4 Channel (RSI) */
-#define IRQ_SPORT1_RX BFIN_IRQ(18) /* DMA 5 Channel (SPORT1 RX/SPI) */
-#define IRQ_SPI1 BFIN_IRQ(18) /* DMA 5 Channel (SPI1) */
-#define IRQ_SPORT1_TX BFIN_IRQ(19) /* DMA 6 Channel (SPORT1 TX) */
-#define IRQ_TWI BFIN_IRQ(20) /* TWI */
-#define IRQ_SPI0 BFIN_IRQ(21) /* DMA 7 Channel (SPI0) */
-#define IRQ_UART0_RX BFIN_IRQ(22) /* DMA8 Channel (UART0 RX) */
-#define IRQ_UART0_TX BFIN_IRQ(23) /* DMA9 Channel (UART0 TX) */
-#define IRQ_UART1_RX BFIN_IRQ(24) /* DMA10 Channel (UART1 RX) */
-#define IRQ_UART1_TX BFIN_IRQ(25) /* DMA11 Channel (UART1 TX) */
-#define IRQ_OPTSEC BFIN_IRQ(26) /* OTPSEC Interrupt */
-#define IRQ_CNT BFIN_IRQ(27) /* GP Counter */
-#define IRQ_MAC_RX BFIN_IRQ(28) /* DMA1 Channel (MAC RX) */
-#define IRQ_PORTH_INTA BFIN_IRQ(29) /* Port H Interrupt A */
-#define IRQ_MAC_TX BFIN_IRQ(30) /* DMA2 Channel (MAC TX) */
-#define IRQ_PORTH_INTB BFIN_IRQ(31) /* Port H Interrupt B */
-#define IRQ_TIMER0 BFIN_IRQ(32) /* Timer 0 */
-#define IRQ_TIMER1 BFIN_IRQ(33) /* Timer 1 */
-#define IRQ_TIMER2 BFIN_IRQ(34) /* Timer 2 */
-#define IRQ_TIMER3 BFIN_IRQ(35) /* Timer 3 */
-#define IRQ_TIMER4 BFIN_IRQ(36) /* Timer 4 */
-#define IRQ_TIMER5 BFIN_IRQ(37) /* Timer 5 */
-#define IRQ_TIMER6 BFIN_IRQ(38) /* Timer 6 */
-#define IRQ_TIMER7 BFIN_IRQ(39) /* Timer 7 */
-#define IRQ_PORTG_INTA BFIN_IRQ(40) /* Port G Interrupt A */
-#define IRQ_PORTG_INTB BFIN_IRQ(41) /* Port G Interrupt B */
-#define IRQ_MEM_DMA0 BFIN_IRQ(42) /* MDMA Stream 0 */
-#define IRQ_MEM_DMA1 BFIN_IRQ(43) /* MDMA Stream 1 */
-#define IRQ_WATCH BFIN_IRQ(44) /* Software Watchdog Timer */
-#define IRQ_PORTF_INTA BFIN_IRQ(45) /* Port F Interrupt A */
-#define IRQ_PORTF_INTB BFIN_IRQ(46) /* Port F Interrupt B */
-#define IRQ_SPI0_ERROR BFIN_IRQ(47) /* SPI0 Status */
-#define IRQ_SPI1_ERROR BFIN_IRQ(48) /* SPI1 Error */
-#define IRQ_RSI_INT0 BFIN_IRQ(51) /* RSI Interrupt0 */
-#define IRQ_RSI_INT1 BFIN_IRQ(52) /* RSI Interrupt1 */
-#define IRQ_PWM_TRIP BFIN_IRQ(53) /* PWM Trip Interrupt */
-#define IRQ_PWM_SYNC BFIN_IRQ(54) /* PWM Sync Interrupt */
-#define IRQ_PTP_STAT BFIN_IRQ(55) /* PTP Stat Interrupt */
-
-#define SYS_IRQS BFIN_IRQ(63) /* 70 */
-
-#define IRQ_PF0 71
-#define IRQ_PF1 72
-#define IRQ_PF2 73
-#define IRQ_PF3 74
-#define IRQ_PF4 75
-#define IRQ_PF5 76
-#define IRQ_PF6 77
-#define IRQ_PF7 78
-#define IRQ_PF8 79
-#define IRQ_PF9 80
-#define IRQ_PF10 81
-#define IRQ_PF11 82
-#define IRQ_PF12 83
-#define IRQ_PF13 84
-#define IRQ_PF14 85
-#define IRQ_PF15 86
-
-#define IRQ_PG0 87
-#define IRQ_PG1 88
-#define IRQ_PG2 89
-#define IRQ_PG3 90
-#define IRQ_PG4 91
-#define IRQ_PG5 92
-#define IRQ_PG6 93
-#define IRQ_PG7 94
-#define IRQ_PG8 95
-#define IRQ_PG9 96
-#define IRQ_PG10 97
-#define IRQ_PG11 98
-#define IRQ_PG12 99
-#define IRQ_PG13 100
-#define IRQ_PG14 101
-#define IRQ_PG15 102
-
-#define IRQ_PH0 103
-#define IRQ_PH1 104
-#define IRQ_PH2 105
-#define IRQ_PH3 106
-#define IRQ_PH4 107
-#define IRQ_PH5 108
-#define IRQ_PH6 109
-#define IRQ_PH7 110
-#define IRQ_PH8 111
-#define IRQ_PH9 112
-#define IRQ_PH10 113
-#define IRQ_PH11 114
-#define IRQ_PH12 115
-#define IRQ_PH13 116
-#define IRQ_PH14 117
-#define IRQ_PH15 118
-
-#define GPIO_IRQ_BASE IRQ_PF0
-
-#define IRQ_MAC_PHYINT 119 /* PHY_INT Interrupt */
-#define IRQ_MAC_MMCINT 120 /* MMC Counter Interrupt */
-#define IRQ_MAC_RXFSINT 121 /* RX Frame-Status Interrupt */
-#define IRQ_MAC_TXFSINT 122 /* TX Frame-Status Interrupt */
-#define IRQ_MAC_WAKEDET 123 /* Wake-Up Interrupt */
-#define IRQ_MAC_RXDMAERR 124 /* RX DMA Direction Error Interrupt */
-#define IRQ_MAC_TXDMAERR 125 /* TX DMA Direction Error Interrupt */
-#define IRQ_MAC_STMDONE 126 /* Station Mgt. Transfer Done Interrupt */
-
-#define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1)
-
-/* IAR0 BIT FIELDS */
-#define IRQ_PLL_WAKEUP_POS 0
-#define IRQ_DMA0_ERROR_POS 4
-#define IRQ_DMAR0_BLK_POS 8
-#define IRQ_DMAR1_BLK_POS 12
-#define IRQ_DMAR0_OVR_POS 16
-#define IRQ_DMAR1_OVR_POS 20
-#define IRQ_PPI_ERROR_POS 24
-#define IRQ_MAC_ERROR_POS 28
-
-/* IAR1 BIT FIELDS */
-#define IRQ_SPORT0_ERROR_POS 0
-#define IRQ_SPORT1_ERROR_POS 4
-#define IRQ_PTP_ERROR_POS 8
-#define IRQ_UART0_ERROR_POS 16
-#define IRQ_UART1_ERROR_POS 20
-#define IRQ_RTC_POS 24
-#define IRQ_PPI_POS 28
-
-/* IAR2 BIT FIELDS */
-#define IRQ_SPORT0_RX_POS 0
-#define IRQ_SPORT0_TX_POS 4
-#define IRQ_RSI_POS 4
-#define IRQ_SPORT1_RX_POS 8
-#define IRQ_SPI1_POS 8
-#define IRQ_SPORT1_TX_POS 12
-#define IRQ_TWI_POS 16
-#define IRQ_SPI0_POS 20
-#define IRQ_UART0_RX_POS 24
-#define IRQ_UART0_TX_POS 28
-
-/* IAR3 BIT FIELDS */
-#define IRQ_UART1_RX_POS 0
-#define IRQ_UART1_TX_POS 4
-#define IRQ_OPTSEC_POS 8
-#define IRQ_CNT_POS 12
-#define IRQ_MAC_RX_POS 16
-#define IRQ_PORTH_INTA_POS 20
-#define IRQ_MAC_TX_POS 24
-#define IRQ_PORTH_INTB_POS 28
-
-/* IAR4 BIT FIELDS */
-#define IRQ_TIMER0_POS 0
-#define IRQ_TIMER1_POS 4
-#define IRQ_TIMER2_POS 8
-#define IRQ_TIMER3_POS 12
-#define IRQ_TIMER4_POS 16
-#define IRQ_TIMER5_POS 20
-#define IRQ_TIMER6_POS 24
-#define IRQ_TIMER7_POS 28
-
-/* IAR5 BIT FIELDS */
-#define IRQ_PORTG_INTA_POS 0
-#define IRQ_PORTG_INTB_POS 4
-#define IRQ_MEM_DMA0_POS 8
-#define IRQ_MEM_DMA1_POS 12
-#define IRQ_WATCH_POS 16
-#define IRQ_PORTF_INTA_POS 20
-#define IRQ_PORTF_INTB_POS 24
-#define IRQ_SPI0_ERROR_POS 28
-
-/* IAR6 BIT FIELDS */
-#define IRQ_SPI1_ERROR_POS 0
-#define IRQ_RSI_INT0_POS 12
-#define IRQ_RSI_INT1_POS 16
-#define IRQ_PWM_TRIP_POS 20
-#define IRQ_PWM_SYNC_POS 24
-#define IRQ_PTP_STAT_POS 28
-
-#endif
+++ /dev/null
-/*
- * BF51x memory map
- *
- * Copyright 2004-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MACH_MEM_MAP_H__
-#define __BFIN_MACH_MEM_MAP_H__
-
-#ifndef __BFIN_MEM_MAP_H__
-# error "do not include mach/mem_map.h directly -- use asm/mem_map.h"
-#endif
-
-/* Async Memory Banks */
-#define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */
-#define ASYNC_BANK3_SIZE 0x00100000 /* 1M */
-#define ASYNC_BANK2_BASE 0x20200000 /* Async Bank 2 */
-#define ASYNC_BANK2_SIZE 0x00100000 /* 1M */
-#define ASYNC_BANK1_BASE 0x20100000 /* Async Bank 1 */
-#define ASYNC_BANK1_SIZE 0x00100000 /* 1M */
-#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
-#define ASYNC_BANK0_SIZE 0x00100000 /* 1M */
-
-/* Boot ROM Memory */
-
-#define BOOT_ROM_START 0xEF000000
-#define BOOT_ROM_LENGTH 0x8000
-
-/* Level 1 Memory */
-
-/* Memory Map for ADSP-BF518/6/4/2 processors */
-
-#ifdef CONFIG_BFIN_ICACHE
-#define BFIN_ICACHESIZE (16 * 1024)
-#else
-#define BFIN_ICACHESIZE (0)
-#endif
-
-#define L1_CODE_START 0xFFA00000
-#define L1_DATA_A_START 0xFF800000
-#define L1_DATA_B_START 0xFF900000
-
-#define L1_CODE_LENGTH 0x8000
-
-#ifdef CONFIG_BFIN_DCACHE
-
-#ifdef CONFIG_BFIN_DCACHE_BANKA
-#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE (16 * 1024)
-#define BFIN_DSUPBANKS 1
-#else
-#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
-#define BFIN_DCACHESIZE (32 * 1024)
-#define BFIN_DSUPBANKS 2
-#endif
-
-#else
-#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH 0x8000
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE 0
-#define BFIN_DSUPBANKS 0
-#endif /*CONFIG_BFIN_DCACHE */
-
-#endif
+++ /dev/null
-#include <mach-common/pll.h>
+++ /dev/null
-/*
- * Copyright 2008-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _MACH_PORTMUX_H_
-#define _MACH_PORTMUX_H_
-
-#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
-
-/* EMAC MII/RMII Port Mux */
-#define P_MII0_ETxD2 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
-#define P_MII0_ERxD2 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
-#define P_MII0_ETxD3 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
-#define P_MII0_ERxD3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
-#define P_MII0_ERxCLK (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
-#define P_MII0_ERxDV (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
-#define P_MII0_COL (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))
-
-#define P_MII0_MDC (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
-#define P_MII0_MDIO (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
-#define P_MII0_ETxD0 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
-#define P_MII0_ERxD0 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
-#define P_MII0_ETxD1 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
-#define P_MII0_ERxD1 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
-#define P_MII0_ETxEN (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
-#define P_MII0_PHYINT (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
-#define P_MII0_CRS (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
-#define P_MII0_ERxER (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
-#define P_MII0_TxCLK (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0))
-
-#define P_MII0 {\
- P_MII0_ETxD0, \
- P_MII0_ETxD1, \
- P_MII0_ETxD2, \
- P_MII0_ETxD3, \
- P_MII0_ETxEN, \
- P_MII0_TxCLK, \
- P_MII0_PHYINT, \
- P_MII0_COL, \
- P_MII0_ERxD0, \
- P_MII0_ERxD1, \
- P_MII0_ERxD2, \
- P_MII0_ERxD3, \
- P_MII0_ERxDV, \
- P_MII0_ERxCLK, \
- P_MII0_ERxER, \
- P_MII0_CRS, \
- P_MII0_MDC, \
- P_MII0_MDIO, 0}
-
-#define P_RMII0 {\
- P_MII0_ETxD0, \
- P_MII0_ETxD1, \
- P_MII0_ETxEN, \
- P_MII0_ERxD0, \
- P_MII0_ERxD1, \
- P_MII0_ERxER, \
- P_MII0_TxCLK, \
- P_MII0_PHYINT, \
- P_MII0_CRS, \
- P_MII0_MDC, \
- P_MII0_MDIO, 0}
-
-/* PPI Port Mux */
-#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
-#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
-#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
-#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
-#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
-#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
-#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
-#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
-#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
-#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
-#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1))
-#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1))
-#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1))
-#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1))
-#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
-#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
-
-#ifndef CONFIG_BF518_PPI_TMR_PG12
-#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1))
-#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
-#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
-#else
-#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
-#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1))
-#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1))
-#endif
-#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
-
-/* SPI Port Mux */
-#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0))
-#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
-#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
-#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
-
-#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
-#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
-#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2))
-#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(2))
-#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(2))
-
-#define P_SPI1_SS (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
-#define P_SPI1_SCK (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(1))
-#define P_SPI1_MISO (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(1))
-#define P_SPI1_MOSI (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(1))
-
-#define P_SPI1_SSEL1 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(2))
-#define P_SPI1_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(2))
-#define P_SPI1_SSEL3 (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(2))
-#define P_SPI1_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(2))
-#define P_SPI1_SSEL5 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(2))
-
-#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PG15
-#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2
-
-/* SPORT Port Mux */
-#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
-#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0))
-#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
-#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
-#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
-#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
-#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
-#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
-
-#define P_SPORT1_DRPRI (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
-#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
-#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
-#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0))
-#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0))
-#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0))
-#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0))
-#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0))
-
-/* UART Port Mux */
-#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1))
-#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1))
-
-#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1))
-#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(1))
-
-/* Timer */
-#ifndef CONFIG_BF518_PPI_TMR_PG12
-#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(2))
-#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2))
-#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2))
-#else
-#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(2))
-#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(2))
-#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(2))
-#endif
-#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(2))
-#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(2))
-#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(2))
-#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(2))
-#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(2))
-#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(2))
-
-/* DMA */
-#define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(1))
-#define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(1))
-
-/* TWI */
-#define P_TWI0_SCL (P_DONTCARE)
-#define P_TWI0_SDA (P_DONTCARE)
-
-/* PWM */
-#ifndef CONFIG_BF518_PWM_PORTF_PORTG
-#define P_PWM_AH (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(2))
-#define P_PWM_AL (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(2))
-#define P_PWM_BH (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(2))
-#define P_PWM_BL (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(2))
-#define P_PWM_CH (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(2))
-#define P_PWM_CL (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(2))
-#else
-#define P_PWM_AH (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(2))
-#define P_PWM_AL (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(2))
-#define P_PWM_BH (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(2))
-#define P_PWM_BL (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(2))
-#define P_PWM_CH (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2))
-#define P_PWM_CL (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(2))
-#endif
-
-#ifndef CONFIG_BF518_PWM_SYNC_PF15
-#define P_PWM_SYNC (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(2))
-#else
-#define P_PWM_SYNC (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(2))
-#endif
-
-#ifndef CONFIG_BF518_PWM_TRIPB_PG14
-#define P_PWM_TRIPB (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(2))
-#else
-#define P_PWM_TRIPB (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(2))
-#endif
-
-/* RSI */
-#define P_RSI_DATA0 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1))
-#define P_RSI_DATA1 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1))
-#define P_RSI_DATA2 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1))
-#define P_RSI_DATA3 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
-#define P_RSI_DATA4 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(2))
-#define P_RSI_DATA5 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(2))
-#define P_RSI_DATA6 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(2))
-#define P_RSI_DATA7 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(2))
-#define P_RSI_CMD (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
-#define P_RSI_CLK (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1))
-
-/* PTP */
-#define P_PTP_PPS (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(2))
-#define P_PTP_CLKOUT (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(2))
-
-/* AMS */
-#define P_AMS2 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
-#define P_AMS3 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(2))
-
-#define P_HWAIT (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(1))
-
-#endif /* _MACH_PORTMUX_H_ */
+++ /dev/null
-/*
- * Set up the interrupt priorities
- *
- * Copyright 2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-#include <linux/irq.h>
-#include <asm/blackfin.h>
-
-void __init program_IAR(void)
-{
- /* Program the IAR0 Register with the configured priority */
- bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) |
- ((CONFIG_IRQ_DMA0_ERROR - 7) << IRQ_DMA0_ERROR_POS) |
- ((CONFIG_IRQ_DMAR0_BLK - 7) << IRQ_DMAR0_BLK_POS) |
- ((CONFIG_IRQ_DMAR1_BLK - 7) << IRQ_DMAR1_BLK_POS) |
- ((CONFIG_IRQ_DMAR0_OVR - 7) << IRQ_DMAR0_OVR_POS) |
- ((CONFIG_IRQ_DMAR1_OVR - 7) << IRQ_DMAR1_OVR_POS) |
- ((CONFIG_IRQ_PPI_ERROR - 7) << IRQ_PPI_ERROR_POS) |
- ((CONFIG_IRQ_MAC_ERROR - 7) << IRQ_MAC_ERROR_POS));
-
-
- bfin_write_SIC_IAR1(((CONFIG_IRQ_SPORT0_ERROR - 7) << IRQ_SPORT0_ERROR_POS) |
- ((CONFIG_IRQ_SPORT1_ERROR - 7) << IRQ_SPORT1_ERROR_POS) |
- ((CONFIG_IRQ_PTP_ERROR - 7) << IRQ_PTP_ERROR_POS) |
- ((CONFIG_IRQ_UART0_ERROR - 7) << IRQ_UART0_ERROR_POS) |
- ((CONFIG_IRQ_UART1_ERROR - 7) << IRQ_UART1_ERROR_POS) |
- ((CONFIG_IRQ_RTC - 7) << IRQ_RTC_POS) |
- ((CONFIG_IRQ_PPI - 7) << IRQ_PPI_POS));
-
- bfin_write_SIC_IAR2(((CONFIG_IRQ_SPORT0_RX - 7) << IRQ_SPORT0_RX_POS) |
- ((CONFIG_IRQ_SPORT0_TX - 7) << IRQ_SPORT0_TX_POS) |
- ((CONFIG_IRQ_SPORT1_RX - 7) << IRQ_SPORT1_RX_POS) |
- ((CONFIG_IRQ_SPORT1_TX - 7) << IRQ_SPORT1_TX_POS) |
- ((CONFIG_IRQ_TWI - 7) << IRQ_TWI_POS) |
- ((CONFIG_IRQ_SPI0 - 7) << IRQ_SPI0_POS) |
- ((CONFIG_IRQ_UART0_RX - 7) << IRQ_UART0_RX_POS) |
- ((CONFIG_IRQ_UART0_TX - 7) << IRQ_UART0_TX_POS));
-
- bfin_write_SIC_IAR3(((CONFIG_IRQ_UART1_RX - 7) << IRQ_UART1_RX_POS) |
- ((CONFIG_IRQ_UART1_TX - 7) << IRQ_UART1_TX_POS) |
- ((CONFIG_IRQ_OPTSEC - 7) << IRQ_OPTSEC_POS) |
- ((CONFIG_IRQ_CNT - 7) << IRQ_CNT_POS) |
- ((CONFIG_IRQ_MAC_RX - 7) << IRQ_MAC_RX_POS) |
- ((CONFIG_IRQ_PORTH_INTA - 7) << IRQ_PORTH_INTA_POS) |
- ((CONFIG_IRQ_MAC_TX - 7) << IRQ_MAC_TX_POS) |
- ((CONFIG_IRQ_PORTH_INTB - 7) << IRQ_PORTH_INTB_POS));
-
- bfin_write_SIC_IAR4(((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) |
- ((CONFIG_IRQ_TIMER1 - 7) << IRQ_TIMER1_POS) |
- ((CONFIG_IRQ_TIMER2 - 7) << IRQ_TIMER2_POS) |
- ((CONFIG_IRQ_TIMER3 - 7) << IRQ_TIMER3_POS) |
- ((CONFIG_IRQ_TIMER4 - 7) << IRQ_TIMER4_POS) |
- ((CONFIG_IRQ_TIMER5 - 7) << IRQ_TIMER5_POS) |
- ((CONFIG_IRQ_TIMER6 - 7) << IRQ_TIMER6_POS) |
- ((CONFIG_IRQ_TIMER7 - 7) << IRQ_TIMER7_POS));
-
- bfin_write_SIC_IAR5(((CONFIG_IRQ_PORTG_INTA - 7) << IRQ_PORTG_INTA_POS) |
- ((CONFIG_IRQ_PORTG_INTB - 7) << IRQ_PORTG_INTB_POS) |
- ((CONFIG_IRQ_MEM_DMA0 - 7) << IRQ_MEM_DMA0_POS) |
- ((CONFIG_IRQ_MEM_DMA1 - 7) << IRQ_MEM_DMA1_POS) |
- ((CONFIG_IRQ_WATCH - 7) << IRQ_WATCH_POS) |
- ((CONFIG_IRQ_PORTF_INTA - 7) << IRQ_PORTF_INTA_POS) |
- ((CONFIG_IRQ_PORTF_INTB - 7) << IRQ_PORTF_INTB_POS) |
- ((CONFIG_IRQ_SPI0_ERROR - 7) << IRQ_SPI0_ERROR_POS));
-
- bfin_write_SIC_IAR6(((CONFIG_IRQ_SPI1_ERROR - 7) << IRQ_SPI1_ERROR_POS) |
- ((CONFIG_IRQ_RSI_INT0 - 7) << IRQ_RSI_INT0_POS) |
- ((CONFIG_IRQ_RSI_INT1 - 7) << IRQ_RSI_INT1_POS) |
- ((CONFIG_IRQ_PWM_TRIP - 7) << IRQ_PWM_TRIP_POS) |
- ((CONFIG_IRQ_PWM_SYNC - 7) << IRQ_PWM_SYNC_POS) |
- ((CONFIG_IRQ_PTP_STAT - 7) << IRQ_PTP_STAT_POS));
-
- SSYNC();
-}
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0
-config BF52x
- def_bool y
- depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
-
-if (BF52x)
-
-source "arch/blackfin/mach-bf527/boards/Kconfig"
-
-menu "BF527 Specific Configuration"
-
-comment "Alternative Multiplexing Scheme"
-
-choice
- prompt "SPORT0"
- default BF527_SPORT0_PORTG
- help
- Select PORT used for SPORT0. See Hardware Reference Manual
-
-config BF527_SPORT0_PORTF
- bool "PORT F"
- help
- PORT F
-
-config BF527_SPORT0_PORTG
- bool "PORT G"
- help
- PORT G
-endchoice
-
-choice
- prompt "SPORT0 TSCLK Location"
- depends on BF527_SPORT0_PORTG
- default BF527_SPORT0_TSCLK_PG10
- help
- Select PIN used for SPORT0_TSCLK. See Hardware Reference Manual
-
-config BF527_SPORT0_TSCLK_PG10
- bool "PORT PG10"
- help
- PORT PG10
-
-config BF527_SPORT0_TSCLK_PG14
- bool "PORT PG14"
- help
- PORT PG14
-endchoice
-
-choice
- prompt "UART1"
- default BF527_UART1_PORTF
- help
- Select PORT used for UART1. See Hardware Reference Manual
-
-config BF527_UART1_PORTF
- bool "PORT F"
- help
- PORT F
-
-config BF527_UART1_PORTG
- bool "PORT G"
- help
- PORT G
-endchoice
-
-choice
- prompt "NAND (NFC) Data"
- default BF527_NAND_D_PORTH
- help
- Select PORT used for NAND Data Bus. See Hardware Reference Manual
-
-config BF527_NAND_D_PORTF
- bool "PORT F"
- help
- PORT F
-
-config BF527_NAND_D_PORTH
- bool "PORT H"
- help
- PORT H
-endchoice
-
-comment "Hysteresis/Schmitt Trigger Control"
-config BFIN_HYSTERESIS_CONTROL
- bool "Enable Hysteresis Control"
- help
- The ADSP-BF52x allows to control input hysteresis for Port F,
- Port G and Port H and other processor signal inputs.
- The Schmitt trigger enables can be set only for pin groups.
- Saying Y will overwrite the default reset or boot loader
- initialization.
-
-menu "PORT F"
- depends on BFIN_HYSTERESIS_CONTROL
-config GPIO_HYST_PORTF_0_7
- bool "Enable Hysteresis on PORTF {0...7}"
-config GPIO_HYST_PORTF_8_9
- bool "Enable Hysteresis on PORTF {8, 9}"
-config GPIO_HYST_PORTF_10
- bool "Enable Hysteresis on PORTF 10"
-config GPIO_HYST_PORTF_11
- bool "Enable Hysteresis on PORTF 11"
-config GPIO_HYST_PORTF_12_13
- bool "Enable Hysteresis on PORTF {12, 13}"
-config GPIO_HYST_PORTF_14_15
- bool "Enable Hysteresis on PORTF {14, 15}"
-endmenu
-
-menu "PORT G"
- depends on BFIN_HYSTERESIS_CONTROL
-config GPIO_HYST_PORTG_0
- bool "Enable Hysteresis on PORTG 0"
-config GPIO_HYST_PORTG_1_4
- bool "Enable Hysteresis on PORTG {1...4}"
-config GPIO_HYST_PORTG_5_6
- bool "Enable Hysteresis on PORTG {5, 6}"
-config GPIO_HYST_PORTG_7_8
- bool "Enable Hysteresis on PORTG {7, 8}"
-config GPIO_HYST_PORTG_9
- bool "Enable Hysteresis on PORTG 9"
-config GPIO_HYST_PORTG_10
- bool "Enable Hysteresis on PORTG 10"
-config GPIO_HYST_PORTG_11_13
- bool "Enable Hysteresis on PORTG {11...13}"
-config GPIO_HYST_PORTG_14_15
- bool "Enable Hysteresis on PORTG {14, 15}"
-endmenu
-
-menu "PORT H"
- depends on BFIN_HYSTERESIS_CONTROL
-config GPIO_HYST_PORTH_0_7
- bool "Enable Hysteresis on PORTH {0...7}"
-config GPIO_HYST_PORTH_8
- bool "Enable Hysteresis on PORTH 8"
-config GPIO_HYST_PORTH_9_15
- bool "Enable Hysteresis on PORTH {9...15}"
-endmenu
-
-menu "None-GPIO"
- depends on BFIN_HYSTERESIS_CONTROL
-config NONEGPIO_HYST_TMR0_FS1_PPICLK
- bool "Enable Hysteresis on {TMR0, PPI_FS1, PPI_CLK}"
-config NONEGPIO_HYST_NMI_RST_BMODE
- bool "Enable Hysteresis on {NMI, RESET, BMODE}"
-config NONEGPIO_HYST_JTAG
- bool "Enable Hysteresis on JTAG"
-endmenu
-
-comment "Interrupt Priority Assignment"
-menu "Priority"
-
-config IRQ_PLL_WAKEUP
- int "IRQ_PLL_WAKEUP"
- default 7
-config IRQ_DMA0_ERROR
- int "IRQ_DMA0_ERROR"
- default 7
-config IRQ_DMAR0_BLK
- int "IRQ_DMAR0_BLK"
- default 7
-config IRQ_DMAR1_BLK
- int "IRQ_DMAR1_BLK"
- default 7
-config IRQ_DMAR0_OVR
- int "IRQ_DMAR0_OVR"
- default 7
-config IRQ_DMAR1_OVR
- int "IRQ_DMAR1_OVR"
- default 7
-config IRQ_PPI_ERROR
- int "IRQ_PPI_ERROR"
- default 7
-config IRQ_MAC_ERROR
- int "IRQ_MAC_ERROR"
- default 7
-config IRQ_SPORT0_ERROR
- int "IRQ_SPORT0_ERROR"
- default 7
-config IRQ_SPORT1_ERROR
- int "IRQ_SPORT1_ERROR"
- default 7
-config IRQ_UART0_ERROR
- int "IRQ_UART0_ERROR"
- default 7
-config IRQ_UART1_ERROR
- int "IRQ_UART1_ERROR"
- default 7
-config IRQ_RTC
- int "IRQ_RTC"
- default 8
-config IRQ_PPI
- int "IRQ_PPI"
- default 8
-config IRQ_SPORT0_RX
- int "IRQ_SPORT0_RX"
- default 9
-config IRQ_SPORT0_TX
- int "IRQ_SPORT0_TX"
- default 9
-config IRQ_SPORT1_RX
- int "IRQ_SPORT1_RX"
- default 9
-config IRQ_SPORT1_TX
- int "IRQ_SPORT1_TX"
- default 9
-config IRQ_TWI
- int "IRQ_TWI"
- default 10
-config IRQ_SPI
- int "IRQ_SPI"
- default 10
-config IRQ_UART0_RX
- int "IRQ_UART0_RX"
- default 10
-config IRQ_UART0_TX
- int "IRQ_UART0_TX"
- default 10
-config IRQ_UART1_RX
- int "IRQ_UART1_RX"
- default 10
-config IRQ_UART1_TX
- int "IRQ_UART1_TX"
- default 10
-config IRQ_OPTSEC
- int "IRQ_OPTSEC"
- default 11
-config IRQ_CNT
- int "IRQ_CNT"
- default 11
-config IRQ_MAC_RX
- int "IRQ_MAC_RX"
- default 11
-config IRQ_PORTH_INTA
- int "IRQ_PORTH_INTA"
- default 11
-config IRQ_MAC_TX
- int "IRQ_MAC_TX/NFC"
- default 11
-config IRQ_PORTH_INTB
- int "IRQ_PORTH_INTB"
- default 11
-config IRQ_TIMER0
- int "IRQ_TIMER0"
- default 7 if TICKSOURCE_GPTMR0
- default 8
-config IRQ_TIMER1
- int "IRQ_TIMER1"
- default 12
-config IRQ_TIMER2
- int "IRQ_TIMER2"
- default 12
-config IRQ_TIMER3
- int "IRQ_TIMER3"
- default 12
-config IRQ_TIMER4
- int "IRQ_TIMER4"
- default 12
-config IRQ_TIMER5
- int "IRQ_TIMER5"
- default 12
-config IRQ_TIMER6
- int "IRQ_TIMER6"
- default 12
-config IRQ_TIMER7
- int "IRQ_TIMER7"
- default 12
-config IRQ_PORTG_INTA
- int "IRQ_PORTG_INTA"
- default 12
-config IRQ_PORTG_INTB
- int "IRQ_PORTG_INTB"
- default 12
-config IRQ_MEM_DMA0
- int "IRQ_MEM_DMA0"
- default 13
-config IRQ_MEM_DMA1
- int "IRQ_MEM_DMA1"
- default 13
-config IRQ_WATCH
- int "IRQ_WATCH"
- default 13
-config IRQ_PORTF_INTA
- int "IRQ_PORTF_INTA"
- default 13
-config IRQ_PORTF_INTB
- int "IRQ_PORTF_INTB"
- default 13
-config IRQ_SPI_ERROR
- int "IRQ_SPI_ERROR"
- default 7
-config IRQ_NFC_ERROR
- int "IRQ_NFC_ERROR"
- default 7
-config IRQ_HDMA_ERROR
- int "IRQ_HDMA_ERROR"
- default 7
-config IRQ_HDMA
- int "IRQ_HDMA"
- default 7
-config IRQ_USB_EINT
- int "IRQ_USB_EINT"
- default 10
-config IRQ_USB_INT0
- int "IRQ_USB_INT0"
- default 10
-config IRQ_USB_INT1
- int "IRQ_USB_INT1"
- default 10
-config IRQ_USB_INT2
- int "IRQ_USB_INT2"
- default 10
-config IRQ_USB_DMA
- int "IRQ_USB_DMA"
- default 10
-
- help
- Enter the priority numbers between 7-13 ONLY. Others are Reserved.
- This applies to all the above. It is not recommended to assign the
- highest priority number 7 to UART or any other device.
-
-endmenu
-
-endmenu
-
-endif
+++ /dev/null
-#
-# arch/blackfin/mach-bf527/Makefile
-#
-
-obj-y := ints-priority.o dma.o
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0
-choice
- prompt "System type"
- default BFIN527_EZKIT
- help
- Select your board!
-
-config BFIN527_EZKIT
- bool "BF527-EZKIT"
- help
- BF527-EZKIT-LITE board support.
-
-config BFIN527_EZKIT_V2
- bool "BF527-EZKIT-V2"
- help
- BF527-EZKIT-LITE V2.1+ board support.
-
-config BFIN527_BLUETECHNIX_CM
- bool "Bluetechnix CM-BF527"
- help
- CM-BF527 support for EVAL- and DEV-Board.
-
-config BFIN526_EZBRD
- bool "BF526-EZBRD"
- help
- BF526-EZBRD/EZKIT Lite board support.
-
-config BFIN527_AD7160EVAL
- bool "BF527-AD7160-EVAL"
- help
- BF527-AD7160-EVAL board support.
-
-config BFIN527_TLL6527M
- bool "The Learning Labs TLL6527M"
- help
- TLL6527M V1.0 platform support
-
-endchoice
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0
-#
-# arch/blackfin/mach-bf527/boards/Makefile
-#
-
-obj-$(CONFIG_BFIN527_EZKIT) += ezkit.o
-obj-$(CONFIG_BFIN527_EZKIT_V2) += ezkit.o
-obj-$(CONFIG_BFIN527_BLUETECHNIX_CM) += cm_bf527.o
-obj-$(CONFIG_BFIN526_EZBRD) += ezbrd.o
-obj-$(CONFIG_BFIN527_AD7160EVAL) += ad7160eval.o
-obj-$(CONFIG_BFIN527_TLL6527M) += tll6527m.o
+++ /dev/null
-/*
- * Copyright 2004-20010 Analog Devices Inc.
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/export.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <linux/i2c.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <linux/usb/musb.h>
-#include <linux/leds.h>
-#include <linux/input.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/reboot.h>
-#include <asm/nand.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "ADI BF527-AD7160EVAL";
-
-/*
- * Driver needs to know address, irq and flag pin.
- */
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
-static struct resource musb_resources[] = {
- [0] = {
- .start = 0xffc03800,
- .end = 0xffc03cff,
- .flags = IORESOURCE_MEM,
- },
- [1] = { /* general IRQ */
- .start = IRQ_USB_INT0,
- .end = IRQ_USB_INT0,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
- [2] = { /* DMA IRQ */
- .start = IRQ_USB_DMA,
- .end = IRQ_USB_DMA,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct musb_hdrc_config musb_config = {
- .multipoint = 0,
- .dyn_fifo = 0,
- .soft_con = 1,
- .dma = 1,
- .num_eps = 8,
- .dma_channels = 8,
- .gpio_vrsel = GPIO_PG13,
- /* Some custom boards need to be active low, just set it to "0"
- * if it is the case.
- */
- .gpio_vrsel_active = 1,
- .clkin = 24, /* musb CLKIN in MHZ */
-};
-
-static struct musb_hdrc_platform_data musb_plat = {
-#if defined(CONFIG_USB_MUSB_OTG)
- .mode = MUSB_OTG,
-#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
- .mode = MUSB_HOST,
-#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
- .mode = MUSB_PERIPHERAL,
-#endif
- .config = &musb_config,
-};
-
-static u64 musb_dmamask = ~(u32)0;
-
-static struct platform_device musb_device = {
- .name = "musb-blackfin",
- .id = 0,
- .dev = {
- .dma_mask = &musb_dmamask,
- .coherent_dma_mask = 0xffffffff,
- .platform_data = &musb_plat,
- },
- .num_resources = ARRAY_SIZE(musb_resources),
- .resource = musb_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BFIN_RA158Z)
-static struct resource bf52x_ra158z_resources[] = {
- {
- .start = IRQ_PPI_ERROR,
- .end = IRQ_PPI_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bf52x_ra158z_device = {
- .name = "bfin-ra158z",
- .id = -1,
- .num_resources = ARRAY_SIZE(bf52x_ra158z_resources),
- .resource = bf52x_ra158z_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
-static struct mtd_partition ad7160eval_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x40000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0x1C0000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct physmap_flash_data ad7160eval_flash_data = {
- .width = 2,
- .parts = ad7160eval_partitions,
- .nr_parts = ARRAY_SIZE(ad7160eval_partitions),
-};
-
-static struct resource ad7160eval_flash_resource = {
- .start = 0x20000000,
- .end = 0x203fffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device ad7160eval_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &ad7160eval_flash_data,
- },
- .num_resources = 1,
- .resource = &ad7160eval_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
-static struct mtd_partition partition_info[] = {
- {
- .name = "linux kernel(nand)",
- .offset = 0,
- .size = 4 * 1024 * 1024,
- },
- {
- .name = "file system(nand)",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- },
-};
-
-static struct bf5xx_nand_platform bf5xx_nand_platform = {
- .data_width = NFC_NWIDTH_8,
- .partitions = partition_info,
- .nr_partitions = ARRAY_SIZE(partition_info),
- .rd_dly = 3,
- .wr_dly = 3,
-};
-
-static struct resource bf5xx_nand_resources[] = {
- {
- .start = NFC_CTL,
- .end = NFC_DATA_RD + 2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = CH_NFC,
- .end = CH_NFC,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bf5xx_nand_device = {
- .name = "bf5xx-nand",
- .id = 0,
- .num_resources = ARRAY_SIZE(bf5xx_nand_resources),
- .resource = bf5xx_nand_resources,
- .dev = {
- .platform_data = &bf5xx_nand_platform,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
-#include <linux/bfin_mac.h>
-static const unsigned short bfin_mac_peripherals[] = P_RMII0;
-
-static struct bfin_phydev_platform_data bfin_phydev_data[] = {
- {
- .addr = 1,
- .irq = IRQ_MAC_PHYINT,
- },
-};
-
-static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
- .phydev_number = 1,
- .phydev_data = bfin_phydev_data,
- .phy_mode = PHY_INTERFACE_MODE_RMII,
- .mac_peripherals = bfin_mac_peripherals,
-};
-
-static struct platform_device bfin_mii_bus = {
- .name = "bfin_mii_bus",
- .dev = {
- .platform_data = &bfin_mii_bus_data,
- }
-};
-
-static struct platform_device bfin_mac_device = {
- .name = "bfin_mac",
- .dev = {
- .platform_data = &bfin_mii_bus,
- }
-};
-#endif
-
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00040000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p16",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
-static struct platform_device bfin_i2s = {
- .name = "bfin-i2s",
- .id = CONFIG_SND_BF5XX_SPORT_NUM,
- /* TODO: add platform data here */
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
- {
- .modalias = "ad183x",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 4,
- },
-#endif
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 30000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = GPIO_PH3 + MAX_CTRL_CS,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_THR,
- .end = UART0_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_THR,
- .end = UART1_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-#ifdef CONFIG_BFIN_UART1_CTSRTS
- { /* CTS pin */
- .start = GPIO_PF9,
- .end = GPIO_PF9,
- .flags = IORESOURCE_IO,
- },
- { /* RTS pin */
- .start = GPIO_PF10,
- .end = GPIO_PF10,
- .flags = IORESOURCE_IO,
- },
-#endif
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX, 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7160)
-#include <linux/input/ad7160.h>
-static const struct ad7160_platform_data bfin_ad7160_ts_info = {
- .sensor_x_res = 854,
- .sensor_y_res = 480,
- .pressure = 100,
- .filter_coef = 3,
- .coord_pref = AD7160_ORIG_TOP_LEFT,
- .first_touch_window = 5,
- .move_window = 3,
- .event_cabs = AD7160_EMIT_ABS_MT_TRACKING_ID |
- AD7160_EMIT_ABS_MT_PRESSURE |
- AD7160_TRACKING_ID_ASCENDING,
- .finger_act_ctrl = 0x64,
- .haptic_effect1_ctrl = AD7160_HAPTIC_SLOT_A(60) |
- AD7160_HAPTIC_SLOT_A_LVL_HIGH |
- AD7160_HAPTIC_SLOT_B(60) |
- AD7160_HAPTIC_SLOT_B_LVL_LOW,
-
- .haptic_effect2_ctrl = AD7160_HAPTIC_SLOT_A(20) |
- AD7160_HAPTIC_SLOT_A_LVL_HIGH |
- AD7160_HAPTIC_SLOT_B(80) |
- AD7160_HAPTIC_SLOT_B_LVL_LOW |
- AD7160_HAPTIC_SLOT_C(120) |
- AD7160_HAPTIC_SLOT_C_LVL_HIGH |
- AD7160_HAPTIC_SLOT_D(30) |
- AD7160_HAPTIC_SLOT_D_LVL_LOW,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_REGBASE,
- .end = TWI0_REGBASE,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI,
- .end = IRQ_TWI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-#endif
-
-static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7160)
- {
- I2C_BOARD_INFO("ad7160", 0x33),
- .irq = IRQ_PH1,
- .platform_data = (void *)&bfin_ad7160_ts_info,
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_BFIN_ROTARY)
-#include <linux/platform_data/bfin_rotary.h>
-
-static const u16 per_cnt[] = {
- P_CNT_CUD,
- P_CNT_CDG,
- P_CNT_CZM,
- 0
-};
-
-static struct bfin_rotary_platform_data bfin_rotary_data = {
- /*.rotary_up_key = KEY_UP,*/
- /*.rotary_down_key = KEY_DOWN,*/
- .rotary_rel_code = REL_WHEEL,
- .rotary_button_key = KEY_ENTER,
- .debounce = 10, /* 0..17 */
- .mode = ROT_QUAD_ENC | ROT_DEBE,
- .pm_wakeup = 1,
- .pin_list = per_cnt,
-};
-
-static struct resource bfin_rotary_resources[] = {
- {
- .start = CNT_CONFIG,
- .end = CNT_CONFIG + 0xff,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_CNT,
- .end = IRQ_CNT,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_rotary_device = {
- .name = "bfin-rotary",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_rotary_resources),
- .resource = bfin_rotary_resources,
- .dev = {
- .platform_data = &bfin_rotary_data,
- },
-};
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] = {
- VRPAIR(VLEV_100, 400000000),
- VRPAIR(VLEV_105, 426000000),
- VRPAIR(VLEV_110, 500000000),
- VRPAIR(VLEV_115, 533000000),
- VRPAIR(VLEV_120, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-static struct platform_device *stamp_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
- &bf5xx_nand_device,
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
- &musb_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
- &bfin_mii_bus,
- &bfin_mac_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BFIN_RA158Z)
- &bf52x_ra158z_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_BFIN_ROTARY)
- &bfin_rotary_device,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
- &ad7160eval_flash_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
- &bfin_i2s,
-#endif
-};
-
-static int __init ad7160eval_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- i2c_register_board_info(0, bfin_i2c_board_info,
- ARRAY_SIZE(bfin_i2c_board_info));
- platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
- return 0;
-}
-
-arch_initcall(ad7160eval_init);
-
-static struct platform_device *ad7160eval_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(ad7160eval_early_devices,
- ARRAY_SIZE(ad7160eval_early_devices));
-}
-
-void native_machine_restart(char *cmd)
-{
- /* workaround reboot hang when booting from SPI */
- if ((bfin_read_SYSCR() & 0x7) == 0x3)
- bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
-}
-
-int bfin_get_ether_addr(char *addr)
-{
- /* the MAC is stored in OTP memory page 0xDF */
- u32 ret;
- u64 otp_mac;
- u32 (*otp_read)(u32 page, u32 flags, u64 *page_content) = (void *)0xEF00001A;
-
- ret = otp_read(0xDF, 0x00, &otp_mac);
- if (!(ret & 0x1)) {
- char *otp_mac_p = (char *)&otp_mac;
- for (ret = 0; ret < 6; ++ret)
- addr[ret] = otp_mac_p[5 - ret];
- }
- return 0;
-}
-EXPORT_SYMBOL(bfin_get_ether_addr);
+++ /dev/null
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2008-2009 Bluetechnix
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/export.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <linux/etherdevice.h>
-#include <linux/i2c.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <linux/usb/musb.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/reboot.h>
-#include <asm/nand.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-#include <linux/spi/ad7877.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "Bluetechnix CM-BF527";
-
-/*
- * Driver needs to know address, irq and flag pin.
- */
-
-#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
-#include <linux/usb/isp1760.h>
-static struct resource bfin_isp1760_resources[] = {
- [0] = {
- .start = 0x203C0000,
- .end = 0x203C0000 + 0x000fffff,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_PF7,
- .end = IRQ_PF7,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct isp1760_platform_data isp1760_priv = {
- .is_isp1761 = 0,
- .bus_width_16 = 1,
- .port1_otg = 0,
- .analog_oc = 0,
- .dack_polarity_high = 0,
- .dreq_polarity_high = 0,
-};
-
-static struct platform_device bfin_isp1760_device = {
- .name = "isp1760",
- .id = 0,
- .dev = {
- .platform_data = &isp1760_priv,
- },
- .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
- .resource = bfin_isp1760_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
-static struct resource musb_resources[] = {
- [0] = {
- .start = 0xffc03800,
- .end = 0xffc03cff,
- .flags = IORESOURCE_MEM,
- },
- [1] = { /* general IRQ */
- .start = IRQ_USB_INT0,
- .end = IRQ_USB_INT0,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- .name = "mc"
- },
- [2] = { /* DMA IRQ */
- .start = IRQ_USB_DMA,
- .end = IRQ_USB_DMA,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- .name = "dma"
- },
-};
-
-static struct musb_hdrc_config musb_config = {
- .multipoint = 0,
- .dyn_fifo = 0,
- .soft_con = 1,
- .dma = 1,
- .num_eps = 8,
- .dma_channels = 8,
- .gpio_vrsel = GPIO_PF11,
- /* Some custom boards need to be active low, just set it to "0"
- * if it is the case.
- */
- .gpio_vrsel_active = 1,
- .clkin = 24, /* musb CLKIN in MHZ */
-};
-
-static struct musb_hdrc_platform_data musb_plat = {
-#if defined(CONFIG_USB_MUSB_OTG)
- .mode = MUSB_OTG,
-#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
- .mode = MUSB_HOST,
-#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
- .mode = MUSB_PERIPHERAL,
-#endif
- .config = &musb_config,
-};
-
-static u64 musb_dmamask = ~(u32)0;
-
-static struct platform_device musb_device = {
- .name = "musb-blackfin",
- .id = 0,
- .dev = {
- .dma_mask = &musb_dmamask,
- .coherent_dma_mask = 0xffffffff,
- .platform_data = &musb_plat,
- },
- .num_resources = ARRAY_SIZE(musb_resources),
- .resource = musb_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
-static struct mtd_partition partition_info[] = {
- {
- .name = "linux kernel(nand)",
- .offset = 0,
- .size = 4 * 1024 * 1024,
- },
- {
- .name = "file system(nand)",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- },
-};
-
-static struct bf5xx_nand_platform bf5xx_nand_platform = {
- .data_width = NFC_NWIDTH_8,
- .partitions = partition_info,
- .nr_partitions = ARRAY_SIZE(partition_info),
- .rd_dly = 3,
- .wr_dly = 3,
-};
-
-static struct resource bf5xx_nand_resources[] = {
- {
- .start = NFC_CTL,
- .end = NFC_DATA_RD + 2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = CH_NFC,
- .end = CH_NFC,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bf5xx_nand_device = {
- .name = "bf5xx-nand",
- .id = 0,
- .num_resources = ARRAY_SIZE(bf5xx_nand_resources),
- .resource = bf5xx_nand_resources,
- .dev = {
- .platform_data = &bf5xx_nand_platform,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA)
-static struct resource bfin_pcmcia_cf_resources[] = {
- {
- .start = 0x20310000, /* IO PORT */
- .end = 0x20312000,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 0x20311000, /* Attribute Memory */
- .end = 0x20311FFF,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF4,
- .end = IRQ_PF4,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
- }, {
- .start = 6, /* Card Detect PF6 */
- .end = 6,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_pcmcia_cf_device = {
- .name = "bfin_cf_pcmcia",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_pcmcia_cf_resources),
- .resource = bfin_pcmcia_cf_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
-#include <linux/smc91x.h>
-
-static struct smc91x_platdata smc91x_info = {
- .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
- .leda = RPC_LED_100_10,
- .ledb = RPC_LED_TX_RX,
-};
-
-static struct resource smc91x_resources[] = {
- {
- .name = "smc91x-regs",
- .start = 0x20300300,
- .end = 0x20300300 + 16,
- .flags = IORESOURCE_MEM,
- }, {
-
- .start = IRQ_PF7,
- .end = IRQ_PF7,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev = {
- .platform_data = &smc91x_info,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_DM9000)
-static struct resource dm9000_resources[] = {
- [0] = {
- .start = 0x203FB800,
- .end = 0x203FB800 + 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = 0x203FB804,
- .end = 0x203FB804 + 1,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .start = IRQ_PF9,
- .end = IRQ_PF9,
- .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE),
- },
-};
-
-static struct platform_device dm9000_device = {
- .name = "dm9000",
- .id = -1,
- .num_resources = ARRAY_SIZE(dm9000_resources),
- .resource = dm9000_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
-#include <linux/bfin_mac.h>
-static const unsigned short bfin_mac_peripherals[] = P_RMII0;
-
-static struct bfin_phydev_platform_data bfin_phydev_data[] = {
- {
- .addr = 1,
- .irq = IRQ_MAC_PHYINT,
- },
-};
-
-static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
- .phydev_number = 1,
- .phydev_data = bfin_phydev_data,
- .phy_mode = PHY_INTERFACE_MODE_RMII,
- .mac_peripherals = bfin_mac_peripherals,
-};
-
-static struct platform_device bfin_mii_bus = {
- .name = "bfin_mii_bus",
- .dev = {
- .platform_data = &bfin_mii_bus_data,
- }
-};
-
-static struct platform_device bfin_mac_device = {
- .name = "bfin_mac",
- .dev = {
- .platform_data = &bfin_mii_bus,
- }
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
-static struct resource net2272_bfin_resources[] = {
- {
- .start = 0x20300000,
- .end = 0x20300000 + 0x100,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF7,
- .end = IRQ_PF7,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device net2272_bfin_device = {
- .name = "net2272",
- .id = -1,
- .num_resources = ARRAY_SIZE(net2272_bfin_resources),
- .resource = net2272_bfin_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00040000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p16",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
-static const struct ad7877_platform_data bfin_ad7877_ts_info = {
- .model = 7877,
- .vref_delay_usecs = 50, /* internal, no capacitor */
- .x_plate_ohms = 419,
- .y_plate_ohms = 486,
- .pressure_max = 1000,
- .pressure_min = 0,
- .stopacq_polarity = 1,
- .first_conversion_delay = 3,
- .acquisition_time = 1,
- .averaging = 1,
- .pen_down_acc_interval = 1,
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
- {
- .modalias = "ad183x",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 4,
- },
-#endif
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
- {
- .modalias = "ad7877",
- .platform_data = &bfin_ad7877_ts_info,
- .irq = IRQ_PF8,
- .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 2,
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_WM8731) \
- && defined(CONFIG_SND_SOC_WM8731_SPI)
- {
- .modalias = "wm8731",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5,
- .mode = SPI_MODE_0,
- },
-#endif
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR)
-static struct mtd_partition cm_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x40000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0x100000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct physmap_flash_data cm_flash_data = {
- .width = 2,
- .parts = cm_partitions,
- .nr_parts = ARRAY_SIZE(cm_partitions),
-};
-
-static unsigned cm_flash_gpios[] = { GPIO_PH9, GPIO_PG11 };
-
-static struct resource cm_flash_resource[] = {
- {
- .name = "cfi_probe",
- .start = 0x20000000,
- .end = 0x201fffff,
- .flags = IORESOURCE_MEM,
- }, {
- .start = (unsigned long)cm_flash_gpios,
- .end = ARRAY_SIZE(cm_flash_gpios),
- .flags = IORESOURCE_IRQ,
- }
-};
-
-static struct platform_device cm_flash_device = {
- .name = "gpio-addr-flash",
- .id = 0,
- .dev = {
- .platform_data = &cm_flash_data,
- },
- .num_resources = ARRAY_SIZE(cm_flash_resource),
- .resource = cm_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_THR,
- .end = UART0_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_THR,
- .end = UART1_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-#ifdef CONFIG_BFIN_UART1_CTSRTS
- { /* CTS pin */
- .start = GPIO_PF9,
- .end = GPIO_PF9,
- .flags = IORESOURCE_IO,
- },
- { /* RTS pin */
- .start = GPIO_PF10,
- .end = GPIO_PF10,
- .flags = IORESOURCE_IO,
- },
-#endif
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX, 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_REGBASE,
- .end = TWI0_REGBASE,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI,
- .end = IRQ_TWI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-#endif
-
-static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
-#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
- {
- I2C_BOARD_INFO("pcf8574_lcd", 0x22),
- },
-#endif
-#if IS_ENABLED(CONFIG_INPUT_PCF8574)
- {
- I2C_BOARD_INFO("pcf8574_keypad", 0x27),
- .irq = IRQ_PF8,
- },
-#endif
-#if IS_ENABLED(CONFIG_FB_BFIN_7393)
- {
- I2C_BOARD_INFO("bfin-adv7393", 0x2B),
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
-#include <linux/input.h>
-#include <linux/gpio_keys.h>
-
-static struct gpio_keys_button bfin_gpio_keys_table[] = {
- {BTN_0, GPIO_PF14, 1, "gpio-keys: BTN0"},
-};
-
-static struct gpio_keys_platform_data bfin_gpio_keys_data = {
- .buttons = bfin_gpio_keys_table,
- .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
-};
-
-static struct platform_device bfin_device_gpiokeys = {
- .name = "gpio-keys",
- .dev = {
- .platform_data = &bfin_gpio_keys_data,
- },
-};
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
- VRPAIR(VLEV_100, 400000000),
- VRPAIR(VLEV_105, 426000000),
- VRPAIR(VLEV_110, 500000000),
- VRPAIR(VLEV_115, 533000000),
- VRPAIR(VLEV_120, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-static struct platform_device *cmbf527_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
- &bf5xx_nand_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA)
- &bfin_pcmcia_cf_device,
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
- &bfin_isp1760_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
- &musb_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
- &smc91x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_DM9000)
- &dm9000_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
- &bfin_mii_bus,
- &bfin_mac_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
- &net2272_bfin_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
- &bfin_device_gpiokeys,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR)
- &cm_flash_device,
-#endif
-};
-
-static int __init cm_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- i2c_register_board_info(0, bfin_i2c_board_info,
- ARRAY_SIZE(bfin_i2c_board_info));
- platform_add_devices(cmbf527_devices, ARRAY_SIZE(cmbf527_devices));
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
- return 0;
-}
-
-arch_initcall(cm_init);
-
-static struct platform_device *cmbf527_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(cmbf527_early_devices,
- ARRAY_SIZE(cmbf527_early_devices));
-}
-
-void native_machine_restart(char *cmd)
-{
- /* workaround reboot hang when booting from SPI */
- if ((bfin_read_SYSCR() & 0x7) == 0x3)
- bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
-}
-
-int bfin_get_ether_addr(char *addr)
-{
- return 1;
-}
-EXPORT_SYMBOL(bfin_get_ether_addr);
+++ /dev/null
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/export.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-
-#include <linux/i2c.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <linux/usb/musb.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/reboot.h>
-#include <asm/nand.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-#include <linux/spi/ad7877.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "ADI BF526-EZBRD";
-
-/*
- * Driver needs to know address, irq and flag pin.
- */
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
-static struct resource musb_resources[] = {
- [0] = {
- .start = 0xffc03800,
- .end = 0xffc03cff,
- .flags = IORESOURCE_MEM,
- },
- [1] = { /* general IRQ */
- .start = IRQ_USB_INT0,
- .end = IRQ_USB_INT0,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- .name = "mc"
- },
- [2] = { /* DMA IRQ */
- .start = IRQ_USB_DMA,
- .end = IRQ_USB_DMA,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- .name = "dma"
- },
-};
-
-static struct musb_hdrc_config musb_config = {
- .multipoint = 0,
- .dyn_fifo = 0,
- .soft_con = 1,
- .dma = 1,
- .num_eps = 8,
- .dma_channels = 8,
- .gpio_vrsel = GPIO_PG13,
- /* Some custom boards need to be active low, just set it to "0"
- * if it is the case.
- */
- .gpio_vrsel_active = 1,
- .clkin = 24, /* musb CLKIN in MHZ */
-};
-
-static struct musb_hdrc_platform_data musb_plat = {
-#if defined(CONFIG_USB_MUSB_OTG)
- .mode = MUSB_OTG,
-#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
- .mode = MUSB_HOST,
-#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
- .mode = MUSB_PERIPHERAL,
-#endif
- .config = &musb_config,
-};
-
-static u64 musb_dmamask = ~(u32)0;
-
-static struct platform_device musb_device = {
- .name = "musb-blackfin",
- .id = 0,
- .dev = {
- .dma_mask = &musb_dmamask,
- .coherent_dma_mask = 0xffffffff,
- .platform_data = &musb_plat,
- },
- .num_resources = ARRAY_SIZE(musb_resources),
- .resource = musb_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
-static struct mtd_partition ezbrd_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x40000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0x1C0000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct physmap_flash_data ezbrd_flash_data = {
- .width = 2,
- .parts = ezbrd_partitions,
- .nr_parts = ARRAY_SIZE(ezbrd_partitions),
-};
-
-static struct resource ezbrd_flash_resource = {
- .start = 0x20000000,
- .end = 0x203fffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device ezbrd_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &ezbrd_flash_data,
- },
- .num_resources = 1,
- .resource = &ezbrd_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
-static struct mtd_partition partition_info[] = {
- {
- .name = "bootloader(nand)",
- .offset = 0,
- .size = 0x40000,
- }, {
- .name = "linux kernel(nand)",
- .offset = MTDPART_OFS_APPEND,
- .size = 4 * 1024 * 1024,
- },
- {
- .name = "file system(nand)",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- },
-};
-
-static struct bf5xx_nand_platform bf5xx_nand_platform = {
- .data_width = NFC_NWIDTH_8,
- .partitions = partition_info,
- .nr_partitions = ARRAY_SIZE(partition_info),
- .rd_dly = 3,
- .wr_dly = 3,
-};
-
-static struct resource bf5xx_nand_resources[] = {
- {
- .start = NFC_CTL,
- .end = NFC_DATA_RD + 2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = CH_NFC,
- .end = CH_NFC,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bf5xx_nand_device = {
- .name = "bf5xx-nand",
- .id = 0,
- .num_resources = ARRAY_SIZE(bf5xx_nand_resources),
- .resource = bf5xx_nand_resources,
- .dev = {
- .platform_data = &bf5xx_nand_platform,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
-#include <linux/bfin_mac.h>
-static const unsigned short bfin_mac_peripherals[] = P_RMII0;
-
-static struct bfin_phydev_platform_data bfin_phydev_data[] = {
- {
- .addr = 1,
- .irq = IRQ_MAC_PHYINT,
- },
-};
-
-static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
- .phydev_number = 1,
- .phydev_data = bfin_phydev_data,
- .phy_mode = PHY_INTERFACE_MODE_RMII,
- .mac_peripherals = bfin_mac_peripherals,
-};
-
-static struct platform_device bfin_mii_bus = {
- .name = "bfin_mii_bus",
- .dev = {
- .platform_data = &bfin_mii_bus_data,
- }
-};
-
-static struct platform_device bfin_mac_device = {
- .name = "bfin_mac",
- .dev = {
- .platform_data = &bfin_mii_bus,
- }
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00040000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "sst25wf040",
-};
-
-/* SPI flash chip (sst25wf040) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
-static const struct ad7877_platform_data bfin_ad7877_ts_info = {
- .model = 7877,
- .vref_delay_usecs = 50, /* internal, no capacitor */
- .x_plate_ohms = 419,
- .y_plate_ohms = 486,
- .pressure_max = 1000,
- .pressure_min = 0,
- .stopacq_polarity = 1,
- .first_conversion_delay = 3,
- .acquisition_time = 1,
- .averaging = 1,
- .pen_down_acc_interval = 1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879)
-#include <linux/platform_data/ad7879.h>
-static const struct ad7879_platform_data bfin_ad7879_ts_info = {
- .model = 7879, /* Model = AD7879 */
- .x_plate_ohms = 620, /* 620 Ohm from the touch datasheet */
- .pressure_max = 10000,
- .pressure_min = 0,
- .first_conversion_delay = 3, /* wait 512us before do a first conversion */
- .acquisition_time = 1, /* 4us acquisition time per sample */
- .median = 2, /* do 8 measurements */
- .averaging = 1, /* take the average of 4 middle samples */
- .pen_down_acc_interval = 255, /* 9.4 ms */
- .gpio_export = 1, /* Export GPIO to gpiolib */
- .gpio_base = -1, /* Dynamic allocation */
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
- {
- .modalias = "ad7877",
- .platform_data = &bfin_ad7877_ts_info,
- .irq = IRQ_PF8,
- .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 2,
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879_SPI)
- {
- .modalias = "ad7879",
- .platform_data = &bfin_ad7879_ts_info,
- .irq = IRQ_PG0,
- .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5,
- .mode = SPI_CPHA | SPI_CPOL,
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_WM8731) \
- && defined(CONFIG_SND_SOC_WM8731_SPI)
- {
- .modalias = "wm8731",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5,
- .mode = SPI_MODE_0,
- },
-#endif
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- },
-#endif
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
- {
- .modalias = "bfin-lq035q1-spi",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- .mode = SPI_CPHA | SPI_CPOL,
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_THR,
- .end = UART0_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_THR,
- .end = UART1_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-#ifdef CONFIG_BFIN_UART1_CTSRTS
- { /* CTS pin */
- .start = GPIO_PG0,
- .end = GPIO_PG0,
- .flags = IORESOURCE_IO,
- },
- { /* RTS pin */
- .start = GPIO_PF10,
- .end = GPIO_PF10,
- .flags = IORESOURCE_IO,
- },
-#endif
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX, 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_REGBASE,
- .end = TWI0_REGBASE,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI,
- .end = IRQ_TWI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-#endif
-
-static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
-#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
- {
- I2C_BOARD_INFO("pcf8574_lcd", 0x22),
- },
-#endif
-#if IS_ENABLED(CONFIG_INPUT_PCF8574)
- {
- I2C_BOARD_INFO("pcf8574_keypad", 0x27),
- .irq = IRQ_PF8,
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
-#include <linux/input.h>
-#include <linux/gpio_keys.h>
-
-static struct gpio_keys_button bfin_gpio_keys_table[] = {
- {BTN_0, GPIO_PG0, 1, "gpio-keys: BTN0"},
- {BTN_1, GPIO_PG13, 1, "gpio-keys: BTN1"},
-};
-
-static struct gpio_keys_platform_data bfin_gpio_keys_data = {
- .buttons = bfin_gpio_keys_table,
- .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
-};
-
-static struct platform_device bfin_device_gpiokeys = {
- .name = "gpio-keys",
- .dev = {
- .platform_data = &bfin_gpio_keys_data,
- },
-};
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
- VRPAIR(VLEV_100, 400000000),
- VRPAIR(VLEV_105, 426000000),
- VRPAIR(VLEV_110, 500000000),
- VRPAIR(VLEV_115, 533000000),
- VRPAIR(VLEV_120, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
-#include <asm/bfin-lq035q1.h>
-
-static struct bfin_lq035q1fb_disp_info bfin_lq035q1_data = {
- .mode = LQ035_NORM | LQ035_RGB | LQ035_RL | LQ035_TB,
- .ppi_mode = USE_RGB565_16_BIT_PPI,
- .use_bl = 1,
- .gpio_bl = GPIO_PG12,
-};
-
-static struct resource bfin_lq035q1_resources[] = {
- {
- .start = IRQ_PPI_ERROR,
- .end = IRQ_PPI_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_lq035q1_device = {
- .name = "bfin-lq035q1",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_lq035q1_resources),
- .resource = bfin_lq035q1_resources,
- .dev = {
- .platform_data = &bfin_lq035q1_data,
- },
-};
-#endif
-
-static struct platform_device *stamp_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
- &bf5xx_nand_device,
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
- &musb_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
- &bfin_mii_bus,
- &bfin_mac_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
- &bfin_lq035q1_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
- &bfin_device_gpiokeys,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
- &ezbrd_flash_device,
-#endif
-};
-
-static int __init ezbrd_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- i2c_register_board_info(0, bfin_i2c_board_info,
- ARRAY_SIZE(bfin_i2c_board_info));
- platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
- return 0;
-}
-
-arch_initcall(ezbrd_init);
-
-static struct platform_device *ezbrd_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(ezbrd_early_devices,
- ARRAY_SIZE(ezbrd_early_devices));
-}
-
-void native_machine_restart(char *cmd)
-{
- /* workaround reboot hang when booting from SPI */
- if ((bfin_read_SYSCR() & 0x7) == 0x3)
- bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
-}
-
-int bfin_get_ether_addr(char *addr)
-{
- /* the MAC is stored in OTP memory page 0xDF */
- u32 ret;
- u64 otp_mac;
- u32 (*otp_read)(u32 page, u32 flags, u64 *page_content) = (void *)0xEF00001A;
-
- ret = otp_read(0xDF, 0x00, &otp_mac);
- if (!(ret & 0x1)) {
- char *otp_mac_p = (char *)&otp_mac;
- for (ret = 0; ret < 6; ++ret)
- addr[ret] = otp_mac_p[5 - ret];
- }
- return 0;
-}
-EXPORT_SYMBOL(bfin_get_ether_addr);
+++ /dev/null
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/export.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <linux/i2c.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <linux/usb/musb.h>
-#include <linux/leds.h>
-#include <linux/input.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/reboot.h>
-#include <asm/nand.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-#include <linux/spi/ad7877.h>
-#include <asm/bfin_sport.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-#ifdef CONFIG_BFIN527_EZKIT_V2
-const char bfin_board_name[] = "ADI BF527-EZKIT V2";
-#else
-const char bfin_board_name[] = "ADI BF527-EZKIT";
-#endif
-
-/*
- * Driver needs to know address, irq and flag pin.
- */
-
-#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
-#include <linux/usb/isp1760.h>
-static struct resource bfin_isp1760_resources[] = {
- [0] = {
- .start = 0x203C0000,
- .end = 0x203C0000 + 0x000fffff,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_PF7,
- .end = IRQ_PF7,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct isp1760_platform_data isp1760_priv = {
- .is_isp1761 = 0,
- .bus_width_16 = 1,
- .port1_otg = 0,
- .analog_oc = 0,
- .dack_polarity_high = 0,
- .dreq_polarity_high = 0,
-};
-
-static struct platform_device bfin_isp1760_device = {
- .name = "isp1760",
- .id = 0,
- .dev = {
- .platform_data = &isp1760_priv,
- },
- .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
- .resource = bfin_isp1760_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
-static struct resource musb_resources[] = {
- [0] = {
- .start = 0xffc03800,
- .end = 0xffc03cff,
- .flags = IORESOURCE_MEM,
- },
- [1] = { /* general IRQ */
- .start = IRQ_USB_INT0,
- .end = IRQ_USB_INT0,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- .name = "mc"
- },
- [2] = { /* DMA IRQ */
- .start = IRQ_USB_DMA,
- .end = IRQ_USB_DMA,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- .name = "dma"
- },
-};
-
-static struct musb_hdrc_config musb_config = {
- .multipoint = 0,
- .dyn_fifo = 0,
- .soft_con = 1,
- .dma = 1,
- .num_eps = 8,
- .dma_channels = 8,
- .gpio_vrsel = GPIO_PG13,
- /* Some custom boards need to be active low, just set it to "0"
- * if it is the case.
- */
- .gpio_vrsel_active = 1,
- .clkin = 24, /* musb CLKIN in MHZ */
-};
-
-static struct musb_hdrc_platform_data musb_plat = {
-#if defined(CONFIG_USB_MUSB_HDRC) && defined(CONFIG_USB_GADGET_MUSB_HDRC)
- .mode = MUSB_OTG,
-#elif defined(CONFIG_USB_MUSB_HDRC)
- .mode = MUSB_HOST,
-#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
- .mode = MUSB_PERIPHERAL,
-#endif
- .config = &musb_config,
-};
-
-static u64 musb_dmamask = ~(u32)0;
-
-static struct platform_device musb_device = {
- .name = "musb-blackfin",
- .id = 0,
- .dev = {
- .dma_mask = &musb_dmamask,
- .coherent_dma_mask = 0xffffffff,
- .platform_data = &musb_plat,
- },
- .num_resources = ARRAY_SIZE(musb_resources),
- .resource = musb_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BFIN_T350MCQB)
-
-static struct resource bf52x_t350mcqb_resources[] = {
- {
- .start = IRQ_PPI_ERROR,
- .end = IRQ_PPI_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bf52x_t350mcqb_device = {
- .name = "bfin-t350mcqb",
- .id = -1,
- .num_resources = ARRAY_SIZE(bf52x_t350mcqb_resources),
- .resource = bf52x_t350mcqb_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
-#include <asm/bfin-lq035q1.h>
-
-static struct bfin_lq035q1fb_disp_info bfin_lq035q1_data = {
- .mode = LQ035_NORM | LQ035_RGB | LQ035_RL | LQ035_TB,
- .ppi_mode = USE_RGB565_8_BIT_PPI,
-};
-
-static struct resource bfin_lq035q1_resources[] = {
- {
- .start = IRQ_PPI_ERROR,
- .end = IRQ_PPI_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_lq035q1_device = {
- .name = "bfin-lq035q1",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_lq035q1_resources),
- .resource = bfin_lq035q1_resources,
- .dev = {
- .platform_data = &bfin_lq035q1_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
-static struct mtd_partition ezkit_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x40000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0x1C0000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct physmap_flash_data ezkit_flash_data = {
- .width = 2,
- .parts = ezkit_partitions,
- .nr_parts = ARRAY_SIZE(ezkit_partitions),
-};
-
-static struct resource ezkit_flash_resource = {
- .start = 0x20000000,
- .end = 0x203fffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device ezkit_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &ezkit_flash_data,
- },
- .num_resources = 1,
- .resource = &ezkit_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
-static struct mtd_partition partition_info[] = {
- {
- .name = "bootloader(nand)",
- .offset = 0,
- .size = 0x40000,
- }, {
- .name = "linux kernel(nand)",
- .offset = MTDPART_OFS_APPEND,
- .size = 4 * 1024 * 1024,
- },
- {
- .name = "file system(nand)",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- },
-};
-
-static struct bf5xx_nand_platform bf5xx_nand_platform = {
- .data_width = NFC_NWIDTH_8,
- .partitions = partition_info,
- .nr_partitions = ARRAY_SIZE(partition_info),
- .rd_dly = 3,
- .wr_dly = 3,
-};
-
-static struct resource bf5xx_nand_resources[] = {
- {
- .start = NFC_CTL,
- .end = NFC_DATA_RD + 2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = CH_NFC,
- .end = CH_NFC,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bf5xx_nand_device = {
- .name = "bf5xx-nand",
- .id = 0,
- .num_resources = ARRAY_SIZE(bf5xx_nand_resources),
- .resource = bf5xx_nand_resources,
- .dev = {
- .platform_data = &bf5xx_nand_platform,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA)
-static struct resource bfin_pcmcia_cf_resources[] = {
- {
- .start = 0x20310000, /* IO PORT */
- .end = 0x20312000,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 0x20311000, /* Attribute Memory */
- .end = 0x20311FFF,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF4,
- .end = IRQ_PF4,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
- }, {
- .start = 6, /* Card Detect PF6 */
- .end = 6,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_pcmcia_cf_device = {
- .name = "bfin_cf_pcmcia",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_pcmcia_cf_resources),
- .resource = bfin_pcmcia_cf_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
-#include <linux/smc91x.h>
-
-static struct smc91x_platdata smc91x_info = {
- .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
- .leda = RPC_LED_100_10,
- .ledb = RPC_LED_TX_RX,
-};
-
-static struct resource smc91x_resources[] = {
- {
- .name = "smc91x-regs",
- .start = 0x20300300,
- .end = 0x20300300 + 16,
- .flags = IORESOURCE_MEM,
- }, {
-
- .start = IRQ_PF7,
- .end = IRQ_PF7,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev = {
- .platform_data = &smc91x_info,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_DM9000)
-static struct resource dm9000_resources[] = {
- [0] = {
- .start = 0x203FB800,
- .end = 0x203FB800 + 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = 0x203FB800 + 4,
- .end = 0x203FB800 + 5,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .start = IRQ_PF9,
- .end = IRQ_PF9,
- .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE),
- },
-};
-
-static struct platform_device dm9000_device = {
- .name = "dm9000",
- .id = -1,
- .num_resources = ARRAY_SIZE(dm9000_resources),
- .resource = dm9000_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
-#include <linux/bfin_mac.h>
-static const unsigned short bfin_mac_peripherals[] = P_RMII0;
-
-static struct bfin_phydev_platform_data bfin_phydev_data[] = {
- {
- .addr = 1,
- .irq = IRQ_MAC_PHYINT,
- },
-};
-
-static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
- .phydev_number = 1,
- .phydev_data = bfin_phydev_data,
- .phy_mode = PHY_INTERFACE_MODE_RMII,
- .mac_peripherals = bfin_mac_peripherals,
-};
-
-static struct platform_device bfin_mii_bus = {
- .name = "bfin_mii_bus",
- .dev = {
- .platform_data = &bfin_mii_bus_data,
- }
-};
-
-static struct platform_device bfin_mac_device = {
- .name = "bfin_mac",
- .dev = {
- .platform_data = &bfin_mii_bus,
- }
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
-static struct resource net2272_bfin_resources[] = {
- {
- .start = 0x20300000,
- .end = 0x20300000 + 0x100,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 1,
- .flags = IORESOURCE_BUS,
- }, {
- .start = IRQ_PF7,
- .end = IRQ_PF7,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device net2272_bfin_device = {
- .name = "net2272",
- .id = -1,
- .num_resources = ARRAY_SIZE(net2272_bfin_resources),
- .resource = net2272_bfin_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00040000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p16",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
-static const struct ad7877_platform_data bfin_ad7877_ts_info = {
- .model = 7877,
- .vref_delay_usecs = 50, /* internal, no capacitor */
- .x_plate_ohms = 419,
- .y_plate_ohms = 486,
- .pressure_max = 1000,
- .pressure_min = 0,
- .stopacq_polarity = 1,
- .first_conversion_delay = 3,
- .acquisition_time = 1,
- .averaging = 1,
- .pen_down_acc_interval = 1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879)
-#include <linux/platform_data/ad7879.h>
-static const struct ad7879_platform_data bfin_ad7879_ts_info = {
- .model = 7879, /* Model = AD7879 */
- .x_plate_ohms = 620, /* 620 Ohm from the touch datasheet */
- .pressure_max = 10000,
- .pressure_min = 0,
- .first_conversion_delay = 3, /* wait 512us before do a first conversion */
- .acquisition_time = 1, /* 4us acquisition time per sample */
- .median = 2, /* do 8 measurements */
- .averaging = 1, /* take the average of 4 middle samples */
- .pen_down_acc_interval = 255, /* 9.4 ms */
- .gpio_export = 0, /* Export GPIO to gpiolib */
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
-
-static const u16 bfin_snd_pin[][7] = {
- {P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0, 0},
- {P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_TFS, 0},
-};
-
-static struct bfin_snd_platform_data bfin_snd_data[] = {
- {
- .pin_req = &bfin_snd_pin[0][0],
- },
- {
- .pin_req = &bfin_snd_pin[1][0],
- },
-};
-
-#define BFIN_SND_RES(x) \
- [x] = { \
- { \
- .start = SPORT##x##_TCR1, \
- .end = SPORT##x##_TCR1, \
- .flags = IORESOURCE_MEM \
- }, \
- { \
- .start = CH_SPORT##x##_RX, \
- .end = CH_SPORT##x##_RX, \
- .flags = IORESOURCE_DMA, \
- }, \
- { \
- .start = CH_SPORT##x##_TX, \
- .end = CH_SPORT##x##_TX, \
- .flags = IORESOURCE_DMA, \
- }, \
- { \
- .start = IRQ_SPORT##x##_ERROR, \
- .end = IRQ_SPORT##x##_ERROR, \
- .flags = IORESOURCE_IRQ, \
- } \
- }
-
-static struct resource bfin_snd_resources[][4] = {
- BFIN_SND_RES(0),
- BFIN_SND_RES(1),
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
-static struct platform_device bfin_i2s_pcm = {
- .name = "bfin-i2s-pcm-audio",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
-static struct platform_device bfin_ac97_pcm = {
- .name = "bfin-ac97-pcm-audio",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
-static struct platform_device bfin_i2s = {
- .name = "bfin-i2s",
- .id = CONFIG_SND_BF5XX_SPORT_NUM,
- .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
- .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
- .dev = {
- .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
-static const char * const ad1836_link[] = {
- "bfin-i2s.0",
- "spi0.4",
-};
-static struct platform_device bfin_ad1836_machine = {
- .name = "bfin-snd-ad1836",
- .id = -1,
- .dev = {
- .platform_data = (void *)ad1836_link,
- },
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
- {
- .modalias = "ad183x",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 4,
- .platform_data = "ad1836",
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 3,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_0,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
- {
- .modalias = "ad7877",
- .platform_data = &bfin_ad7877_ts_info,
- .irq = IRQ_PF8,
- .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 2,
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879_SPI)
- {
- .modalias = "ad7879",
- .platform_data = &bfin_ad7879_ts_info,
- .irq = IRQ_PF8,
- .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 3,
- .mode = SPI_CPHA | SPI_CPOL,
- },
-#endif
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- },
-#endif
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
- {
- .modalias = "bfin-lq035q1-spi",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 7,
- .mode = SPI_CPHA | SPI_CPOL,
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_THR,
- .end = UART0_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_THR,
- .end = UART1_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-#ifdef CONFIG_BFIN_UART1_CTSRTS
- { /* CTS pin */
- .start = GPIO_PF9,
- .end = GPIO_PF9,
- .flags = IORESOURCE_IO,
- },
- { /* RTS pin */
- .start = GPIO_PF10,
- .end = GPIO_PF10,
- .flags = IORESOURCE_IO,
- },
-#endif
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX, 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_REGBASE,
- .end = TWI0_REGBASE,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI,
- .end = IRQ_TWI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_PMIC_ADP5520)
-#include <linux/mfd/adp5520.h>
-
- /*
- * ADP5520/5501 LEDs Data
- */
-
-static struct led_info adp5520_leds[] = {
- {
- .name = "adp5520-led1",
- .default_trigger = "none",
- .flags = FLAG_ID_ADP5520_LED1_ADP5501_LED0 | ADP5520_LED_OFFT_600ms,
- },
-};
-
-static struct adp5520_leds_platform_data adp5520_leds_data = {
- .num_leds = ARRAY_SIZE(adp5520_leds),
- .leds = adp5520_leds,
- .fade_in = ADP5520_FADE_T_600ms,
- .fade_out = ADP5520_FADE_T_600ms,
- .led_on_time = ADP5520_LED_ONT_600ms,
-};
-
- /*
- * ADP5520 Keypad Data
- */
-
-static const unsigned short adp5520_keymap[ADP5520_KEYMAPSIZE] = {
- [ADP5520_KEY(3, 3)] = KEY_1,
- [ADP5520_KEY(2, 3)] = KEY_2,
- [ADP5520_KEY(1, 3)] = KEY_3,
- [ADP5520_KEY(0, 3)] = KEY_UP,
- [ADP5520_KEY(3, 2)] = KEY_4,
- [ADP5520_KEY(2, 2)] = KEY_5,
- [ADP5520_KEY(1, 2)] = KEY_6,
- [ADP5520_KEY(0, 2)] = KEY_DOWN,
- [ADP5520_KEY(3, 1)] = KEY_7,
- [ADP5520_KEY(2, 1)] = KEY_8,
- [ADP5520_KEY(1, 1)] = KEY_9,
- [ADP5520_KEY(0, 1)] = KEY_DOT,
- [ADP5520_KEY(3, 0)] = KEY_BACKSPACE,
- [ADP5520_KEY(2, 0)] = KEY_0,
- [ADP5520_KEY(1, 0)] = KEY_HELP,
- [ADP5520_KEY(0, 0)] = KEY_ENTER,
-};
-
-static struct adp5520_keys_platform_data adp5520_keys_data = {
- .rows_en_mask = ADP5520_ROW_R3 | ADP5520_ROW_R2 | ADP5520_ROW_R1 | ADP5520_ROW_R0,
- .cols_en_mask = ADP5520_COL_C3 | ADP5520_COL_C2 | ADP5520_COL_C1 | ADP5520_COL_C0,
- .keymap = adp5520_keymap,
- .keymapsize = ARRAY_SIZE(adp5520_keymap),
- .repeat = 0,
-};
-
- /*
- * ADP5520/5501 Multifunction Device Init Data
- */
-
-static struct adp5520_platform_data adp5520_pdev_data = {
- .leds = &adp5520_leds_data,
- .keys = &adp5520_keys_data,
-};
-
-#endif
-
-static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
-#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
- {
- I2C_BOARD_INFO("pcf8574_lcd", 0x22),
- },
-#endif
-#if IS_ENABLED(CONFIG_INPUT_PCF8574)
- {
- I2C_BOARD_INFO("pcf8574_keypad", 0x27),
- .irq = IRQ_PF8,
- },
-#endif
-#if IS_ENABLED(CONFIG_FB_BFIN_7393)
- {
- I2C_BOARD_INFO("bfin-adv7393", 0x2B),
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879_I2C)
- {
- I2C_BOARD_INFO("ad7879", 0x2C),
- .irq = IRQ_PF8,
- .platform_data = (void *)&bfin_ad7879_ts_info,
- },
-#endif
-#if IS_ENABLED(CONFIG_PMIC_ADP5520)
- {
- I2C_BOARD_INFO("pmic-adp5520", 0x32),
- .irq = IRQ_PF9,
- .platform_data = (void *)&adp5520_pdev_data,
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_SSM2602)
- {
- I2C_BOARD_INFO("ssm2602", 0x1b),
- },
-#endif
-#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
- {
- I2C_BOARD_INFO("ad5252", 0x2f),
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_ADAU1373)
- {
- I2C_BOARD_INFO("adau1373", 0x1A),
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
-#include <linux/gpio_keys.h>
-
-static struct gpio_keys_button bfin_gpio_keys_table[] = {
- {BTN_0, GPIO_PG0, 1, "gpio-keys: BTN0"},
- {BTN_1, GPIO_PG13, 1, "gpio-keys: BTN1"},
-};
-
-static struct gpio_keys_platform_data bfin_gpio_keys_data = {
- .buttons = bfin_gpio_keys_table,
- .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
-};
-
-static struct platform_device bfin_device_gpiokeys = {
- .name = "gpio-keys",
- .dev = {
- .platform_data = &bfin_gpio_keys_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_BFIN_ROTARY)
-#include <linux/platform_data/bfin_rotary.h>
-
-static const u16 per_cnt[] = {
- P_CNT_CUD,
- P_CNT_CDG,
- P_CNT_CZM,
- 0
-};
-
-static struct bfin_rotary_platform_data bfin_rotary_data = {
- /*.rotary_up_key = KEY_UP,*/
- /*.rotary_down_key = KEY_DOWN,*/
- .rotary_rel_code = REL_WHEEL,
- .rotary_button_key = KEY_ENTER,
- .debounce = 10, /* 0..17 */
- .mode = ROT_QUAD_ENC | ROT_DEBE,
- .pm_wakeup = 1,
- .pin_list = per_cnt,
-};
-
-static struct resource bfin_rotary_resources[] = {
- {
- .start = CNT_CONFIG,
- .end = CNT_CONFIG + 0xff,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_CNT,
- .end = IRQ_CNT,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_rotary_device = {
- .name = "bfin-rotary",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_rotary_resources),
- .resource = bfin_rotary_resources,
- .dev = {
- .platform_data = &bfin_rotary_data,
- },
-};
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
- VRPAIR(VLEV_100, 400000000),
- VRPAIR(VLEV_105, 426000000),
- VRPAIR(VLEV_110, 500000000),
- VRPAIR(VLEV_115, 533000000),
- VRPAIR(VLEV_120, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-static struct platform_device *stamp_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
- &bf5xx_nand_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA)
- &bfin_pcmcia_cf_device,
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
- &bfin_isp1760_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
- &musb_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
- &smc91x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_DM9000)
- &dm9000_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
- &bfin_mii_bus,
- &bfin_mac_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
- &net2272_bfin_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BFIN_T350MCQB)
- &bf52x_t350mcqb_device,
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
- &bfin_lq035q1_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
- &bfin_device_gpiokeys,
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_BFIN_ROTARY)
- &bfin_rotary_device,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
- &ezkit_flash_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
- &bfin_i2s_pcm,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
- &bfin_ac97_pcm,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
- &bfin_i2s,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
- &bfin_ad1836_machine,
-#endif
-};
-
-static int __init ezkit_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- i2c_register_board_info(0, bfin_i2c_board_info,
- ARRAY_SIZE(bfin_i2c_board_info));
- platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
- return 0;
-}
-
-arch_initcall(ezkit_init);
-
-static struct platform_device *ezkit_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(ezkit_early_devices,
- ARRAY_SIZE(ezkit_early_devices));
-}
-
-void native_machine_restart(char *cmd)
-{
- /* workaround reboot hang when booting from SPI */
- if ((bfin_read_SYSCR() & 0x7) == 0x3)
- bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
-}
-
-int bfin_get_ether_addr(char *addr)
-{
- /* the MAC is stored in OTP memory page 0xDF */
- u32 ret;
- u64 otp_mac;
- u32 (*otp_read)(u32 page, u32 flags, u64 *page_content) = (void *)0xEF00001A;
-
- ret = otp_read(0xDF, 0x00, &otp_mac);
- if (!(ret & 0x1)) {
- char *otp_mac_p = (char *)&otp_mac;
- for (ret = 0; ret < 6; ++ret)
- addr[ret] = otp_mac_p[5 - ret];
- }
- return 0;
-}
-EXPORT_SYMBOL(bfin_get_ether_addr);
+++ /dev/null
-/* File: arch/blackfin/mach-bf527/boards/tll6527m.c
- * Based on: arch/blackfin/mach-bf527/boards/ezkit.c
- * Author: Ashish Gupta
- *
- * Copyright: 2010 - The Learning Labs Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/export.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <linux/i2c.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <linux/usb/musb.h>
-#include <linux/leds.h>
-#include <linux/input.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/reboot.h>
-#include <asm/nand.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879)
-#include <linux/platform_data/ad7879.h>
-#define LCD_BACKLIGHT_GPIO 0x40
-/* TLL6527M uses TLL7UIQ35 / ADI LCD EZ Extender. AD7879 AUX GPIO is used for
- * LCD Backlight Enable
- */
-#endif
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "TLL6527M";
-/*
- * Driver needs to know address, irq and flag pin.
- */
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
-static struct resource musb_resources[] = {
- [0] = {
- .start = 0xffc03800,
- .end = 0xffc03cff,
- .flags = IORESOURCE_MEM,
- },
- [1] = { /* general IRQ */
- .start = IRQ_USB_INT0,
- .end = IRQ_USB_INT0,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
- [2] = { /* DMA IRQ */
- .start = IRQ_USB_DMA,
- .end = IRQ_USB_DMA,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct musb_hdrc_config musb_config = {
- .multipoint = 0,
- .dyn_fifo = 0,
- .soft_con = 1,
- .dma = 1,
- .num_eps = 8,
- .dma_channels = 8,
- /*.gpio_vrsel = GPIO_PG13,*/
- /* Some custom boards need to be active low, just set it to "0"
- * if it is the case.
- */
- .gpio_vrsel_active = 1,
-};
-
-static struct musb_hdrc_platform_data musb_plat = {
-#if defined(CONFIG_USB_MUSB_OTG)
- .mode = MUSB_OTG,
-#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
- .mode = MUSB_HOST,
-#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
- .mode = MUSB_PERIPHERAL,
-#endif
- .config = &musb_config,
-};
-
-static u64 musb_dmamask = ~(u32)0;
-
-static struct platform_device musb_device = {
- .name = "musb-blackfin",
- .id = 0,
- .dev = {
- .dma_mask = &musb_dmamask,
- .coherent_dma_mask = 0xffffffff,
- .platform_data = &musb_plat,
- },
- .num_resources = ARRAY_SIZE(musb_resources),
- .resource = musb_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
-#include <asm/bfin-lq035q1.h>
-
-static struct bfin_lq035q1fb_disp_info bfin_lq035q1_data = {
- .mode = LQ035_NORM | LQ035_RGB | LQ035_RL | LQ035_TB,
- .ppi_mode = USE_RGB565_16_BIT_PPI,
- .use_bl = 1,
- .gpio_bl = LCD_BACKLIGHT_GPIO,
-};
-
-static struct resource bfin_lq035q1_resources[] = {
- {
- .start = IRQ_PPI_ERROR,
- .end = IRQ_PPI_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_lq035q1_device = {
- .name = "bfin-lq035q1",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_lq035q1_resources),
- .resource = bfin_lq035q1_resources,
- .dev = {
- .platform_data = &bfin_lq035q1_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR)
-static struct mtd_partition tll6527m_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0xA0000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0xD00000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct physmap_flash_data tll6527m_flash_data = {
- .width = 2,
- .parts = tll6527m_partitions,
- .nr_parts = ARRAY_SIZE(tll6527m_partitions),
-};
-
-static unsigned tll6527m_flash_gpios[] = { GPIO_PG11, GPIO_PH11, GPIO_PH12 };
-
-static struct resource tll6527m_flash_resource[] = {
- {
- .name = "cfi_probe",
- .start = 0x20000000,
- .end = 0x201fffff,
- .flags = IORESOURCE_MEM,
- }, {
- .start = (unsigned long)tll6527m_flash_gpios,
- .end = ARRAY_SIZE(tll6527m_flash_gpios),
- .flags = IORESOURCE_IRQ,
- }
-};
-
-static struct platform_device tll6527m_flash_device = {
- .name = "gpio-addr-flash",
- .id = 0,
- .dev = {
- .platform_data = &tll6527m_flash_data,
- },
- .num_resources = ARRAY_SIZE(tll6527m_flash_resource),
- .resource = tll6527m_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_GPIO_DECODER)
-/* An SN74LVC138A 3:8 decoder chip has been used to generate 7 augmented
- * outputs used as SPI CS lines for all SPI SLAVE devices on TLL6527v1-0.
- * EXP_GPIO_SPISEL_BASE is the base number for the expanded outputs being
- * used as SPI CS lines, this should be > MAX_BLACKFIN_GPIOS
- */
-#include <linux/gpio-decoder.h>
-#define EXP_GPIO_SPISEL_BASE 0x64
-static unsigned gpio_addr_inputs[] = {
- GPIO_PG1, GPIO_PH9, GPIO_PH10
-};
-
-static struct gpio_decoder_platform_data spi_decoded_cs = {
- .base = EXP_GPIO_SPISEL_BASE,
- .input_addrs = gpio_addr_inputs,
- .nr_input_addrs = ARRAY_SIZE(gpio_addr_inputs),
- .default_output = 0,
-/* .default_output = (1 << ARRAY_SIZE(gpio_addr_inputs)) - 1 */
-};
-
-static struct platform_device spi_decoded_gpio = {
- .name = "gpio-decoder",
- .id = 0,
- .dev = {
- .platform_data = &spi_decoded_cs,
- },
-};
-
-#else
-#define EXP_GPIO_SPISEL_BASE 0x0
-
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_ADXL34X)
-#include <linux/input/adxl34x.h>
-static const struct adxl34x_platform_data adxl345_info = {
- .x_axis_offset = 0,
- .y_axis_offset = 0,
- .z_axis_offset = 0,
- .tap_threshold = 0x31,
- .tap_duration = 0x10,
- .tap_latency = 0x60,
- .tap_window = 0xF0,
- .tap_axis_control = ADXL_TAP_X_EN | ADXL_TAP_Y_EN | ADXL_TAP_Z_EN,
- .act_axis_control = 0xFF,
- .activity_threshold = 5,
- .inactivity_threshold = 2,
- .inactivity_time = 2,
- .free_fall_threshold = 0x7,
- .free_fall_time = 0x20,
- .data_rate = 0x8,
- .data_range = ADXL_FULL_RES,
-
- .ev_type = EV_ABS,
- .ev_code_x = ABS_X, /* EV_REL */
- .ev_code_y = ABS_Y, /* EV_REL */
- .ev_code_z = ABS_Z, /* EV_REL */
-
- .ev_code_tap = {BTN_TOUCH, BTN_TOUCH, BTN_TOUCH}, /* EV_KEY x,y,z */
-
-/* .ev_code_ff = KEY_F,*/ /* EV_KEY */
- .ev_code_act_inactivity = KEY_A, /* EV_KEY */
- .use_int2 = 1,
- .power_mode = ADXL_AUTO_SLEEP | ADXL_LINK,
- .fifo_mode = ADXL_FIFO_STREAM,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
-#include <linux/bfin_mac.h>
-static const unsigned short bfin_mac_peripherals[] = P_RMII0;
-
-static struct bfin_phydev_platform_data bfin_phydev_data[] = {
- {
- .addr = 1,
- .irq = IRQ_MAC_PHYINT,
- },
-};
-
-static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
- .phydev_number = 1,
- .phydev_data = bfin_phydev_data,
- .phy_mode = PHY_INTERFACE_MODE_RMII,
- .mac_peripherals = bfin_mac_peripherals,
-};
-
-static struct platform_device bfin_mii_bus = {
- .name = "bfin_mii_bus",
- .dev = {
- .platform_data = &bfin_mii_bus_data,
- }
-};
-
-static struct platform_device bfin_mac_device = {
- .name = "bfin_mac",
- .dev = {
- .platform_data = &bfin_mii_bus,
- }
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00040000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p16",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879)
-static const struct ad7879_platform_data bfin_ad7879_ts_info = {
- .model = 7879, /* Model = AD7879 */
- .x_plate_ohms = 620, /* 620 Ohm from the touch datasheet */
- .pressure_max = 10000,
- .pressure_min = 0,
- .first_conversion_delay = 3,
- /* wait 512us before do a first conversion */
- .acquisition_time = 1, /* 4us acquisition time per sample */
- .median = 2, /* do 8 measurements */
- .averaging = 1,
- /* take the average of 4 middle samples */
- .pen_down_acc_interval = 255, /* 9.4 ms */
- .gpio_export = 1, /* configure AUX as GPIO output*/
- .gpio_base = LCD_BACKLIGHT_GPIO,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
-static struct platform_device bfin_i2s = {
- .name = "bfin-i2s",
- .id = CONFIG_SND_BF5XX_SPORT_NUM,
- /* TODO: add platform data here */
-};
-#endif
-
-#if IS_ENABLED(CONFIG_PINCTRL_MCP23S08)
-#include <linux/spi/mcp23s08.h>
-static const struct mcp23s08_platform_data bfin_mcp23s08_sys_gpio_info = {
- .spi_present_mask = BIT(0),
- .base = 0x30,
-};
-static const struct mcp23s08_platform_data bfin_mcp23s08_usr_gpio_info = {
- .spi_present_mask = BIT(2),
- .base = 0x38,
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000,
- /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = EXP_GPIO_SPISEL_BASE + 0x04 + MAX_CTRL_CS,
- /* Can be connected to TLL6527M GPIO connector */
- /* Either SPI_ADC or M25P80 FLASH can be installed at a time */
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
-/*
- * TLL6527M V1.0 does not support SD Card at SPI Clock > 10 MHz due to
- * SPI buffer limitations
- */
- .max_speed_hz = 10000000,
- /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = EXP_GPIO_SPISEL_BASE + 0x05 + MAX_CTRL_CS,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_0,
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879_SPI)
- {
- .modalias = "ad7879",
- .platform_data = &bfin_ad7879_ts_info,
- .irq = IRQ_PH14,
- .max_speed_hz = 5000000,
- /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = EXP_GPIO_SPISEL_BASE + 0x07 + MAX_CTRL_CS,
- .mode = SPI_CPHA | SPI_CPOL,
- },
-#endif
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 10000000,
- /* TLL6527Mv1-0 supports max spi clock (SCK) speed = 10 MHz */
- .bus_num = 0,
- .chip_select = EXP_GPIO_SPISEL_BASE + 0x03 + MAX_CTRL_CS,
- .mode = SPI_CPHA | SPI_CPOL,
- },
-#endif
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
- {
- .modalias = "bfin-lq035q1-spi",
- .max_speed_hz = 20000000,
- .bus_num = 0,
- .chip_select = EXP_GPIO_SPISEL_BASE + 0x06 + MAX_CTRL_CS,
- .mode = SPI_CPHA | SPI_CPOL,
- },
-#endif
-#if IS_ENABLED(CONFIG_PINCTRL_MCP23S08)
- {
- .modalias = "mcp23s08",
- .platform_data = &bfin_mcp23s08_sys_gpio_info,
- .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = EXP_GPIO_SPISEL_BASE + 0x01 + MAX_CTRL_CS,
- .mode = SPI_CPHA | SPI_CPOL,
- },
- {
- .modalias = "mcp23s08",
- .platform_data = &bfin_mcp23s08_usr_gpio_info,
- .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = EXP_GPIO_SPISEL_BASE + 0x02 + MAX_CTRL_CS,
- .mode = SPI_CPHA | SPI_CPOL,
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = EXP_GPIO_SPISEL_BASE + 8 + MAX_CTRL_CS,
- /* EXP_GPIO_SPISEL_BASE will be > MAX_BLACKFIN_GPIOS */
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_THR,
- .end = UART0_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals,
- /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_THR,
- .end = UART1_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-#ifdef CONFIG_BFIN_UART1_CTSRTS
- { /* CTS pin */
- .start = GPIO_PF9,
- .end = GPIO_PF9,
- .flags = IORESOURCE_IO,
- },
- { /* RTS pin */
- .start = GPIO_PF10,
- .end = GPIO_PF10,
- .flags = IORESOURCE_IO,
- },
-#endif
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX, 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals,
- /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_REGBASE,
- .end = TWI0_REGBASE,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI,
- .end = IRQ_TWI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-#endif
-
-static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
-#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
- {
- I2C_BOARD_INFO("pcf8574_lcd", 0x22),
- },
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BFIN_7393)
- {
- I2C_BOARD_INFO("bfin-adv7393", 0x2B),
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879_I2C)
- {
- I2C_BOARD_INFO("ad7879", 0x2C),
- .irq = IRQ_PH14,
- .platform_data = (void *)&bfin_ad7879_ts_info,
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_SSM2602)
- {
- I2C_BOARD_INFO("ssm2602", 0x1b),
- },
-#endif
- {
- I2C_BOARD_INFO("adm1192", 0x2e),
- },
-
- {
- I2C_BOARD_INFO("ltc3576", 0x09),
- },
-#if IS_ENABLED(CONFIG_INPUT_ADXL34X_I2C)
- {
- I2C_BOARD_INFO("adxl34x", 0x53),
- .irq = IRQ_PH13,
- .platform_data = (void *)&adxl345_info,
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals,
- /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals,
- /* Passed to driver */
- },
-};
-#endif
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] = {
- VRPAIR(VLEV_100, 400000000),
- VRPAIR(VLEV_105, 426000000),
- VRPAIR(VLEV_110, 500000000),
- VRPAIR(VLEV_115, 533000000),
- VRPAIR(VLEV_120, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-static struct platform_device *tll6527m_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
- &musb_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
- &bfin_mii_bus,
- &bfin_mac_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
- &bfin_lq035q1_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR)
- &tll6527m_flash_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
- &bfin_i2s,
-#endif
-
-#if IS_ENABLED(CONFIG_GPIO_DECODER)
- &spi_decoded_gpio,
-#endif
-};
-
-static int __init tll6527m_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- i2c_register_board_info(0, bfin_i2c_board_info,
- ARRAY_SIZE(bfin_i2c_board_info));
- platform_add_devices(tll6527m_devices, ARRAY_SIZE(tll6527m_devices));
- spi_register_board_info(bfin_spi_board_info,
- ARRAY_SIZE(bfin_spi_board_info));
- return 0;
-}
-
-arch_initcall(tll6527m_init);
-
-static struct platform_device *tll6527m_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(tll6527m_early_devices,
- ARRAY_SIZE(tll6527m_early_devices));
-}
-
-void native_machine_restart(char *cmd)
-{
- /* workaround reboot hang when booting from SPI */
- if ((bfin_read_SYSCR() & 0x7) == 0x3)
- bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
-}
-
-int bfin_get_ether_addr(char *addr)
-{
- /* the MAC is stored in OTP memory page 0xDF */
- u32 ret;
- u64 otp_mac;
- u32 (*otp_read)(u32 page, u32 flags,
- u64 *page_content) = (void *)0xEF00001A;
-
- ret = otp_read(0xDF, 0x00, &otp_mac);
- if (!(ret & 0x1)) {
- char *otp_mac_p = (char *)&otp_mac;
- for (ret = 0; ret < 6; ++ret)
- addr[ret] = otp_mac_p[5 - ret];
- }
- return 0;
-}
-EXPORT_SYMBOL(bfin_get_ether_addr);
+++ /dev/null
-/*
- * This file contains the simple DMA Implementation for Blackfin
- *
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-
-#include <asm/blackfin.h>
-#include <asm/dma.h>
-
-struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
- (struct dma_register *) DMA0_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_NEXT_DESC_PTR,
- (struct dma_register *) DMA3_NEXT_DESC_PTR,
- (struct dma_register *) DMA4_NEXT_DESC_PTR,
- (struct dma_register *) DMA5_NEXT_DESC_PTR,
- (struct dma_register *) DMA6_NEXT_DESC_PTR,
- (struct dma_register *) DMA7_NEXT_DESC_PTR,
- (struct dma_register *) DMA8_NEXT_DESC_PTR,
- (struct dma_register *) DMA9_NEXT_DESC_PTR,
- (struct dma_register *) DMA10_NEXT_DESC_PTR,
- (struct dma_register *) DMA11_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
-};
-EXPORT_SYMBOL(dma_io_base_addr);
-
-int channel2irq(unsigned int channel)
-{
- int ret_irq = -1;
-
- switch (channel) {
- case CH_PPI:
- ret_irq = IRQ_PPI;
- break;
-
- case CH_EMAC_RX:
- ret_irq = IRQ_MAC_RX;
- break;
-
- case CH_EMAC_TX:
- ret_irq = IRQ_MAC_TX;
- break;
-
- case CH_UART1_RX:
- ret_irq = IRQ_UART1_RX;
- break;
-
- case CH_UART1_TX:
- ret_irq = IRQ_UART1_TX;
- break;
-
- case CH_SPORT0_RX:
- ret_irq = IRQ_SPORT0_RX;
- break;
-
- case CH_SPORT0_TX:
- ret_irq = IRQ_SPORT0_TX;
- break;
-
- case CH_SPORT1_RX:
- ret_irq = IRQ_SPORT1_RX;
- break;
-
- case CH_SPORT1_TX:
- ret_irq = IRQ_SPORT1_TX;
- break;
-
- case CH_SPI:
- ret_irq = IRQ_SPI;
- break;
-
- case CH_UART0_RX:
- ret_irq = IRQ_UART0_RX;
- break;
-
- case CH_UART0_TX:
- ret_irq = IRQ_UART0_TX;
- break;
-
- case CH_MEM_STREAM0_SRC:
- case CH_MEM_STREAM0_DEST:
- ret_irq = IRQ_MEM_DMA0;
- break;
-
- case CH_MEM_STREAM1_SRC:
- case CH_MEM_STREAM1_DEST:
- ret_irq = IRQ_MEM_DMA1;
- break;
- }
- return ret_irq;
-}
+++ /dev/null
-/*
- * DO NOT EDIT THIS FILE
- * This file is under version control at
- * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
- * and can be replaced with that version at any time
- * DO NOT EDIT THIS FILE
- *
- * Copyright 2004-2011 Analog Devices Inc.
- * Licensed under the Clear BSD license.
- */
-
-/* This file should be up to date with:
- * - Revision F, 05/23/2011; ADSP-BF526 Blackfin Processor Anomaly List
- * - Revision I, 05/23/2011; ADSP-BF527 Blackfin Processor Anomaly List
- */
-
-#ifndef _MACH_ANOMALY_H_
-#define _MACH_ANOMALY_H_
-
-/* We do not support old silicon - sorry */
-#if __SILICON_REVISION__ < 0
-# error will not work on BF526/BF527 silicon version
-#endif
-
-#if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__)
-# define ANOMALY_BF526 1
-#else
-# define ANOMALY_BF526 0
-#endif
-#if defined(__ADSPBF523__) || defined(__ADSPBF525__) || defined(__ADSPBF527__)
-# define ANOMALY_BF527 1
-#else
-# define ANOMALY_BF527 0
-#endif
-
-#define _ANOMALY_BF526(rev526) (ANOMALY_BF526 && __SILICON_REVISION__ rev526)
-#define _ANOMALY_BF527(rev527) (ANOMALY_BF527 && __SILICON_REVISION__ rev527)
-#define _ANOMALY_BF526_BF527(rev526, rev527) (_ANOMALY_BF526(rev526) || _ANOMALY_BF527(rev527))
-
-/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
-#define ANOMALY_05000074 (1)
-/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
-#define ANOMALY_05000119 (1)
-/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
-#define ANOMALY_05000122 (1)
-/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
-#define ANOMALY_05000245 (1)
-/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
-#define ANOMALY_05000254 (1)
-/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
-#define ANOMALY_05000265 (1)
-/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
-#define ANOMALY_05000310 (1)
-/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
-#define ANOMALY_05000313 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Incorrect Access of OTP_STATUS During otp_write() Function */
-#define ANOMALY_05000328 (_ANOMALY_BF527(< 2))
-/* Host DMA Boot Modes Are Not Functional */
-#define ANOMALY_05000330 (_ANOMALY_BF527(< 2))
-/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
-#define ANOMALY_05000337 (_ANOMALY_BF527(< 2))
-/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
-#define ANOMALY_05000341 (_ANOMALY_BF527(< 2))
-/* TWI May Not Operate Correctly Under Certain Signal Termination Conditions */
-#define ANOMALY_05000342 (_ANOMALY_BF527(< 2))
-/* USB Calibration Value Is Not Initialized */
-#define ANOMALY_05000346 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* USB Calibration Value to use */
-#define ANOMALY_05000346_value 0xE510
-/* Preboot Routine Incorrectly Alters Reset Value of USB Register */
-#define ANOMALY_05000347 (_ANOMALY_BF527(< 2))
-/* Security Features Are Not Functional */
-#define ANOMALY_05000348 (_ANOMALY_BF527(< 1))
-/* bfrom_SysControl() Firmware Function Performs Improper System Reset */
-#define ANOMALY_05000353 (_ANOMALY_BF526(< 1))
-/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
-#define ANOMALY_05000355 (_ANOMALY_BF527(< 2))
-/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
-#define ANOMALY_05000357 (_ANOMALY_BF527(< 2))
-/* Incorrect Revision Number in DSPID Register */
-#define ANOMALY_05000364 (_ANOMALY_BF527(== 1))
-/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
-#define ANOMALY_05000366 (1)
-/* Incorrect Default CSEL Value in PLL_DIV */
-#define ANOMALY_05000368 (_ANOMALY_BF527(< 2))
-/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
-#define ANOMALY_05000371 (_ANOMALY_BF527(< 2))
-/* Authentication Fails To Initiate */
-#define ANOMALY_05000376 (_ANOMALY_BF527(< 2))
-/* Data Read From L3 Memory by USB DMA May be Corrupted */
-#define ANOMALY_05000380 (_ANOMALY_BF527(< 2))
-/* 8-Bit NAND Flash Boot Mode Not Functional */
-#define ANOMALY_05000382 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Boot from OTP Memory Not Functional */
-#define ANOMALY_05000385 (_ANOMALY_BF527(< 2))
-/* bfrom_SysControl() Firmware Routine Not Functional */
-#define ANOMALY_05000386 (_ANOMALY_BF527(< 2))
-/* Programmable Preboot Settings Not Functional */
-#define ANOMALY_05000387 (_ANOMALY_BF527(< 2))
-/* CRC32 Checksum Support Not Functional */
-#define ANOMALY_05000388 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Reset Vector Must Not Be in SDRAM Memory Space */
-#define ANOMALY_05000389 (_ANOMALY_BF527(< 2))
-/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */
-#define ANOMALY_05000392 (_ANOMALY_BF527(< 2))
-/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */
-#define ANOMALY_05000393 (_ANOMALY_BF527(< 2))
-/* Log Buffer Not Functional */
-#define ANOMALY_05000394 (_ANOMALY_BF527(< 2))
-/* Hook Routine Not Functional */
-#define ANOMALY_05000395 (_ANOMALY_BF527(< 2))
-/* Header Indirect Bit Not Functional */
-#define ANOMALY_05000396 (_ANOMALY_BF527(< 2))
-/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */
-#define ANOMALY_05000397 (_ANOMALY_BF527(< 2))
-/* SWRESET, DFRESET and WDRESET Bits in the SYSCR Register Not Functional */
-#define ANOMALY_05000398 (_ANOMALY_BF527(< 2))
-/* BCODE_NOBOOT in BCODE Field of SYSCR Register Not Functional */
-#define ANOMALY_05000399 (_ANOMALY_BF527(< 2))
-/* PPI Data Signals D0 and D8 do not Tristate After Disabling PPI */
-#define ANOMALY_05000401 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
-#define ANOMALY_05000403 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Lockbox SESR Disallows Certain User Interrupts */
-#define ANOMALY_05000404 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Lockbox SESR Firmware Does Not Save/Restore Full Context */
-#define ANOMALY_05000405 (1)
-/* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */
-#define ANOMALY_05000407 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
-#define ANOMALY_05000408 (1)
-/* Lockbox firmware leaves MDMA0 channel enabled */
-#define ANOMALY_05000409 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Incorrect Default Internal Voltage Regulator Setting */
-#define ANOMALY_05000410 (_ANOMALY_BF527(< 2))
-/* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */
-#define ANOMALY_05000411 (_ANOMALY_BF526(< 1))
-/* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */
-#define ANOMALY_05000414 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* DEB2_URGENT Bit Not Functional */
-#define ANOMALY_05000415 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Speculative Fetches Can Cause Undesired External FIFO Operations */
-#define ANOMALY_05000416 (1)
-/* SPORT0 Ignores External TSCLK0 on PG14 When TMR6 is an Output */
-#define ANOMALY_05000417 (_ANOMALY_BF527(< 2))
-/* PPI Timing Requirements tSFSPE and tHFSPE Do Not Meet Data Sheet Specifications */
-#define ANOMALY_05000418 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* USB PLL_STABLE Bit May Not Accurately Reflect the USB PLL's Status */
-#define ANOMALY_05000420 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* TWI Fall Time (Tof) May Violate the Minimum I2C Specification */
-#define ANOMALY_05000421 (1)
-/* TWI Input Capacitance (Ci) May Violate the Maximum I2C Specification */
-#define ANOMALY_05000422 (_ANOMALY_BF526_BF527(> 0, > 1))
-/* Certain Ethernet Frames With Errors are Misclassified in RMII Mode */
-#define ANOMALY_05000423 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Internal Voltage Regulator Not Trimmed */
-#define ANOMALY_05000424 (_ANOMALY_BF527(< 2))
-/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
-#define ANOMALY_05000425 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
-#define ANOMALY_05000426 (1)
-/* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Reflects Buffer Status Instead of IRQ Status */
-#define ANOMALY_05000429 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Software System Reset Corrupts PLL_LOCKCNT Register */
-#define ANOMALY_05000430 (_ANOMALY_BF527(> 1))
-/* Incorrect Use of Stack in Lockbox Firmware During Authentication */
-#define ANOMALY_05000431 (1)
-/* bfrom_SysControl() Does Not Clear SIC_IWR1 Before Executing PLL Programming Sequence */
-#define ANOMALY_05000432 (_ANOMALY_BF526(< 1))
-/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */
-#define ANOMALY_05000434 (1)
-/* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */
-#define ANOMALY_05000435 (_ANOMALY_BF526_BF527(< 1, >= 0))
-/* Preboot Cannot be Used to Alter the PLL_DIV Register */
-#define ANOMALY_05000439 (_ANOMALY_BF526_BF527(< 1, >= 0))
-/* bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register */
-#define ANOMALY_05000440 (_ANOMALY_BF526_BF527(< 1, >= 0))
-/* OTP Write Accesses Not Supported */
-#define ANOMALY_05000442 (_ANOMALY_BF527(< 1))
-/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
-#define ANOMALY_05000443 (1)
-/* The WURESET Bit in the SYSCR Register is not Functional */
-#define ANOMALY_05000445 (_ANOMALY_BF527(>= 0))
-/* USB DMA Short Packet Data Corruption */
-#define ANOMALY_05000450 (1)
-/* BCODE_QUICKBOOT, BCODE_ALLBOOT, and BCODE_FULLBOOT Settings in SYSCR Register Not Functional */
-#define ANOMALY_05000451 (_ANOMALY_BF527(>= 0))
-/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
-#define ANOMALY_05000452 (_ANOMALY_BF526_BF527(< 1, >= 0))
-/* USB Receive Interrupt Is Not Generated in DMA Mode 1 */
-#define ANOMALY_05000456 (1)
-/* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */
-#define ANOMALY_05000457 (1)
-/* USB DMA Mode 1 Failure When Multiple USB DMA Channels Are Concurrently Enabled */
-#define ANOMALY_05000460 (1)
-/* False Hardware Error when RETI Points to Invalid Memory */
-#define ANOMALY_05000461 (1)
-/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
-#define ANOMALY_05000462 (1)
-/* USB Rx DMA Hang */
-#define ANOMALY_05000465 (1)
-/* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */
-#define ANOMALY_05000466 (1)
-/* Possible USB RX Data Corruption When Control & Data EP FIFOs are Accessed via the Core */
-#define ANOMALY_05000467 (1)
-/* PLL Latches Incorrect Settings During Reset */
-#define ANOMALY_05000469 (1)
-/* Incorrect Default MSEL Value in PLL_CTL */
-#define ANOMALY_05000472 (_ANOMALY_BF526(>= 0))
-/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
-#define ANOMALY_05000473 (1)
-/* Possible Lockup Condition when Modifying PLL from External Memory */
-#define ANOMALY_05000475 (1)
-/* TESTSET Instruction Cannot Be Interrupted */
-#define ANOMALY_05000477 (1)
-/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
-#define ANOMALY_05000481 (1)
-/* Possible USB Data Corruption When Multiple Endpoints Are Accessed by the Core */
-#define ANOMALY_05000483 (1)
-/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
-#define ANOMALY_05000485 (_ANOMALY_BF526_BF527(< 2, >= 0))
-/* The CODEC Zero-Cross Detect Feature is not Functional */
-#define ANOMALY_05000487 (1)
-/* SPI Master Boot Can Fail Under Certain Conditions */
-#define ANOMALY_05000490 (1)
-/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
-#define ANOMALY_05000491 (1)
-/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
-#define ANOMALY_05000494 (1)
-/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */
-#define ANOMALY_05000498 (1)
-/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
-#define ANOMALY_05000501 (1)
-
-/* Anomalies that don't exist on this proc */
-#define ANOMALY_05000099 (0)
-#define ANOMALY_05000120 (0)
-#define ANOMALY_05000125 (0)
-#define ANOMALY_05000149 (0)
-#define ANOMALY_05000158 (0)
-#define ANOMALY_05000171 (0)
-#define ANOMALY_05000179 (0)
-#define ANOMALY_05000182 (0)
-#define ANOMALY_05000183 (0)
-#define ANOMALY_05000189 (0)
-#define ANOMALY_05000198 (0)
-#define ANOMALY_05000202 (0)
-#define ANOMALY_05000215 (0)
-#define ANOMALY_05000219 (0)
-#define ANOMALY_05000220 (0)
-#define ANOMALY_05000227 (0)
-#define ANOMALY_05000230 (0)
-#define ANOMALY_05000231 (0)
-#define ANOMALY_05000233 (0)
-#define ANOMALY_05000234 (0)
-#define ANOMALY_05000242 (0)
-#define ANOMALY_05000244 (0)
-#define ANOMALY_05000248 (0)
-#define ANOMALY_05000250 (0)
-#define ANOMALY_05000257 (0)
-#define ANOMALY_05000261 (0)
-#define ANOMALY_05000263 (0)
-#define ANOMALY_05000266 (0)
-#define ANOMALY_05000273 (0)
-#define ANOMALY_05000274 (0)
-#define ANOMALY_05000278 (0)
-#define ANOMALY_05000281 (0)
-#define ANOMALY_05000283 (0)
-#define ANOMALY_05000285 (0)
-#define ANOMALY_05000287 (0)
-#define ANOMALY_05000301 (0)
-#define ANOMALY_05000305 (0)
-#define ANOMALY_05000307 (0)
-#define ANOMALY_05000311 (0)
-#define ANOMALY_05000312 (0)
-#define ANOMALY_05000315 (0)
-#define ANOMALY_05000323 (0)
-#define ANOMALY_05000362 (1)
-#define ANOMALY_05000363 (0)
-#define ANOMALY_05000383 (0)
-#define ANOMALY_05000400 (0)
-#define ANOMALY_05000402 (0)
-#define ANOMALY_05000412 (0)
-#define ANOMALY_05000447 (0)
-#define ANOMALY_05000448 (0)
-#define ANOMALY_05000474 (0)
-#define ANOMALY_05000480 (0)
-#define ANOMALY_16000030 (0)
-
-#endif
+++ /dev/null
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __MACH_BF527_H__
-#define __MACH_BF527_H__
-
-#define OFFSET_(x) ((x) & 0x0000FFFF)
-
-/*some misc defines*/
-#define IMASK_IVG15 0x8000
-#define IMASK_IVG14 0x4000
-#define IMASK_IVG13 0x2000
-#define IMASK_IVG12 0x1000
-
-#define IMASK_IVG11 0x0800
-#define IMASK_IVG10 0x0400
-#define IMASK_IVG9 0x0200
-#define IMASK_IVG8 0x0100
-
-#define IMASK_IVG7 0x0080
-#define IMASK_IVGTMR 0x0040
-#define IMASK_IVGHW 0x0020
-
-/***************************/
-
-#define BFIN_DSUBBANKS 4
-#define BFIN_DWAYS 2
-#define BFIN_DLINES 64
-#define BFIN_ISUBBANKS 4
-#define BFIN_IWAYS 4
-#define BFIN_ILINES 32
-
-#define WAY0_L 0x1
-#define WAY1_L 0x2
-#define WAY01_L 0x3
-#define WAY2_L 0x4
-#define WAY02_L 0x5
-#define WAY12_L 0x6
-#define WAY012_L 0x7
-
-#define WAY3_L 0x8
-#define WAY03_L 0x9
-#define WAY13_L 0xA
-#define WAY013_L 0xB
-
-#define WAY32_L 0xC
-#define WAY320_L 0xD
-#define WAY321_L 0xE
-#define WAYALL_L 0xF
-
-#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
-
-/********************************* EBIU Settings ************************************/
-#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
-#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
-
-#ifdef CONFIG_C_AMBEN_ALL
-#define V_AMBEN AMBEN_ALL
-#endif
-#ifdef CONFIG_C_AMBEN
-#define V_AMBEN 0x0
-#endif
-#ifdef CONFIG_C_AMBEN_B0
-#define V_AMBEN AMBEN_B0
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1
-#define V_AMBEN AMBEN_B0_B1
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1_B2
-#define V_AMBEN AMBEN_B0_B1_B2
-#endif
-#ifdef CONFIG_C_AMCKEN
-#define V_AMCKEN AMCKEN
-#else
-#define V_AMCKEN 0x0
-#endif
-#ifdef CONFIG_C_CDPRIO
-#define V_CDPRIO 0x100
-#else
-#define V_CDPRIO 0x0
-#endif
-
-#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO)
-
-/**************************** Hysteresis Settings ****************************/
-
-#ifdef CONFIG_BFIN_HYSTERESIS_CONTROL
-#ifdef CONFIG_GPIO_HYST_PORTF_0_7
-#define HYST_PORTF_0_7 (1 << 0)
-#else
-#define HYST_PORTF_0_7 (0 << 0)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTF_8_9
-#define HYST_PORTF_8_9 (1 << 2)
-#else
-#define HYST_PORTF_8_9 (0 << 2)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTF_10
-#define HYST_PORTF_10 (1 << 4)
-#else
-#define HYST_PORTF_10 (0 << 4)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTF_11
-#define HYST_PORTF_11 (1 << 6)
-#else
-#define HYST_PORTF_11 (0 << 6)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTF_12_13
-#define HYST_PORTF_12_13 (1 << 8)
-#else
-#define HYST_PORTF_12_13 (0 << 8)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTF_14_15
-#define HYST_PORTF_14_15 (1 << 10)
-#else
-#define HYST_PORTF_14_15 (0 << 10)
-#endif
-
-#define HYST_PORTF_0_15 (HYST_PORTF_0_7 | HYST_PORTF_8_9 | HYST_PORTF_10 | \
- HYST_PORTF_11 | HYST_PORTF_12_13 | HYST_PORTF_14_15)
-
-#ifdef CONFIG_GPIO_HYST_PORTG_0
-#define HYST_PORTG_0 (1 << 0)
-#else
-#define HYST_PORTG_0 (0 << 0)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTG_1_4
-#define HYST_PORTG_1_4 (1 << 2)
-#else
-#define HYST_PORTG_1_4 (0 << 2)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTG_5_6
-#define HYST_PORTG_5_6 (1 << 4)
-#else
-#define HYST_PORTG_5_6 (0 << 4)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTG_7_8
-#define HYST_PORTG_7_8 (1 << 6)
-#else
-#define HYST_PORTG_7_8 (0 << 6)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTG_9
-#define HYST_PORTG_9 (1 << 8)
-#else
-#define HYST_PORTG_9 (0 << 8)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTG_10
-#define HYST_PORTG_10 (1 << 10)
-#else
-#define HYST_PORTG_10 (0 << 10)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTG_11_13
-#define HYST_PORTG_11_13 (1 << 12)
-#else
-#define HYST_PORTG_11_13 (0 << 12)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTG_14_15
-#define HYST_PORTG_14_15 (1 << 14)
-#else
-#define HYST_PORTG_14_15 (0 << 14)
-#endif
-
-#define HYST_PORTG_0_15 (HYST_PORTG_0 | HYST_PORTG_1_4 | HYST_PORTG_5_6 | \
- HYST_PORTG_7_8 | HYST_PORTG_9 | HYST_PORTG_10 | \
- HYST_PORTG_11_13 | HYST_PORTG_14_15)
-
-#ifdef CONFIG_GPIO_HYST_PORTH_0_7
-#define HYST_PORTH_0_7 (1 << 0)
-#else
-#define HYST_PORTH_0_7 (0 << 0)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTH_8
-#define HYST_PORTH_8 (1 << 2)
-#else
-#define HYST_PORTH_8 (0 << 2)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTH_9_15
-#define HYST_PORTH_9_15 (1 << 4)
-#else
-#define HYST_PORTH_9_15 (0 << 4)
-#endif
-
-#define HYST_PORTH_0_15 (HYST_PORTH_0_7 | HYST_PORTH_8 | HYST_PORTH_9_15)
-
-#ifdef CONFIG_NONEGPIO_HYST_TMR0_FS1_PPICLK
-#define HYST_TMR0_FS1_PPICLK (1 << 0)
-#else
-#define HYST_TMR0_FS1_PPICLK (0 << 0)
-#endif
-#ifdef CONFIG_NONEGPIO_HYST_NMI_RST_BMODE
-#define HYST_NMI_RST_BMODE (1 << 2)
-#else
-#define HYST_NMI_RST_BMODE (0 << 2)
-#endif
-#ifdef CONFIG_NONEGPIO_HYST_JTAG
-#define HYST_JTAG (1 << 4)
-#else
-#define HYST_JTAG (0 << 4)
-#endif
-
-#define HYST_NONEGPIO (HYST_TMR0_FS1_PPICLK | HYST_NMI_RST_BMODE | HYST_JTAG)
-#define HYST_NONEGPIO_MASK (0x3F)
-#endif /* CONFIG_BFIN_HYSTERESIS_CONTROL */
-
-#ifdef CONFIG_BF527
-#define CPU "BF527"
-#define CPUID 0x27e0
-#endif
-#ifdef CONFIG_BF526
-#define CPU "BF526"
-#define CPUID 0x27e4
-#endif
-#ifdef CONFIG_BF525
-#define CPU "BF525"
-#define CPUID 0x27e0
-#endif
-#ifdef CONFIG_BF524
-#define CPU "BF524"
-#define CPUID 0x27e4
-#endif
-#ifdef CONFIG_BF523
-#define CPU "BF523"
-#define CPUID 0x27e0
-#endif
-#ifdef CONFIG_BF522
-#define CPU "BF522"
-#define CPUID 0x27e4
-#endif
-
-#ifndef CPU
-#error "Unknown CPU type - This kernel doesn't seem to be configured properly"
-#endif
-
-#endif /* __MACH_BF527_H__ */
+++ /dev/null
-/*
- * mach/bfin_serial.h - Blackfin UART/Serial definitions
- *
- * Copyright 2006-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MACH_SERIAL_H__
-#define __BFIN_MACH_SERIAL_H__
-
-#define BFIN_UART_NR_PORTS 2
-
-#endif
+++ /dev/null
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_BLACKFIN_H_
-#define _MACH_BLACKFIN_H_
-
-#include "bf527.h"
-#include "anomaly.h"
-
-#include <asm/def_LPBlackfin.h>
-#if defined(CONFIG_BF523) || defined(CONFIG_BF522)
-# include "defBF522.h"
-#endif
-#if defined(CONFIG_BF525) || defined(CONFIG_BF524)
-# include "defBF525.h"
-#endif
-#if defined(CONFIG_BF527) || defined(CONFIG_BF526)
-# include "defBF527.h"
-#endif
-
-#if !defined(__ASSEMBLY__)
-# include <asm/cdef_LPBlackfin.h>
-# if defined(CONFIG_BF523) || defined(CONFIG_BF522)
-# include "cdefBF522.h"
-# endif
-# if defined(CONFIG_BF525) || defined(CONFIG_BF524)
-# include "cdefBF525.h"
-# endif
-# if defined(CONFIG_BF527) || defined(CONFIG_BF526)
-# include "cdefBF527.h"
-# endif
-#endif
-
-#endif
+++ /dev/null
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CDEF_BF522_H
-#define _CDEF_BF522_H
-
-/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
-#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
-#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
-#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
-#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
-#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
-#define bfin_read_CHIPID() bfin_read32(CHIPID)
-#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
-
-
-/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
-#define bfin_read_SWRST() bfin_read16(SWRST)
-#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
-#define bfin_read_SYSCR() bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
-
-#define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT)
-#define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val)
-#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
-#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
-#define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + (x << 6))
-#define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 6)), val)
-
-#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
-#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
-#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
-#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val)
-#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
-#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val)
-#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
-#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val)
-
-#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
-#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
-#define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + (x << 6))
-#define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 6)), val)
-
-#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
-#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
-#define bfin_read_SIC_IWR(x) bfin_read32(SIC_IWR0 + (x << 6))
-#define bfin_write_SIC_IWR(x, val) bfin_write32((SIC_IWR0 + (x << 6)), val)
-
-/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */
-
-#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)
-#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val)
-#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4)
-#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val)
-#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5)
-#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val)
-#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6)
-#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val)
-#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7)
-#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val)
-#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
-#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
-#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
-#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val)
-
-/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
-#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
-#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
-#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
-
-
-/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
-#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
-#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val)
-#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
-#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val)
-#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
-#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val)
-#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
-#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val)
-#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
-#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val)
-#define bfin_read_RTC_FAST() bfin_read16(RTC_FAST)
-#define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST, val)
-#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
-#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val)
-
-
-/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
-#define bfin_read_UART0_THR() bfin_read16(UART0_THR)
-#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val)
-#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR)
-#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val)
-#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL)
-#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val)
-#define bfin_read_UART0_IER() bfin_read16(UART0_IER)
-#define bfin_write_UART0_IER(val) bfin_write16(UART0_IER, val)
-#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH)
-#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val)
-#define bfin_read_UART0_IIR() bfin_read16(UART0_IIR)
-#define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR, val)
-#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR)
-#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val)
-#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR)
-#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val)
-#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR)
-#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val)
-#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR)
-#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val)
-#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR)
-#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val)
-#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL)
-#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val)
-
-
-/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
-#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL)
-#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL, val)
-#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG)
-#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG, val)
-#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT)
-#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT, val)
-#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR)
-#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR, val)
-#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR)
-#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR, val)
-#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD)
-#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD, val)
-#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW)
-#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW, val)
-
-
-/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
-#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
-#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
-#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
-
-#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
-#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
-#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
-
-#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
-#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
-#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
-
-#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
-#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val)
-#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
-#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
-#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
-#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val)
-#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
-#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val)
-
-#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
-#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val)
-#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
-#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
-#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
-#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val)
-#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
-#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val)
-
-#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
-#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val)
-#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
-#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
-#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
-#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val)
-#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
-#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val)
-
-#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
-#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val)
-#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
-#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
-#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
-#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val)
-#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
-#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val)
-
-#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
-#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val)
-#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
-#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
-#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
-#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val)
-#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
-#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val)
-
-#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE)
-#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val)
-#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE)
-#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val)
-#define bfin_read_TIMER_STATUS() bfin_read32(TIMER_STATUS)
-#define bfin_write_TIMER_STATUS(val) bfin_write32(TIMER_STATUS, val)
-
-
-/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
-#define bfin_read_PORTFIO() bfin_read16(PORTFIO)
-#define bfin_write_PORTFIO(val) bfin_write16(PORTFIO, val)
-#define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR)
-#define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR, val)
-#define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET)
-#define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET, val)
-#define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE)
-#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val)
-#define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA)
-#define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA, val)
-#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR)
-#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val)
-#define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET)
-#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val)
-#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE)
-#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB)
-#define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB, val)
-#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR)
-#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val)
-#define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET)
-#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val)
-#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE)
-#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR)
-#define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR, val)
-#define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR)
-#define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR, val)
-#define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE)
-#define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE, val)
-#define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH)
-#define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH, val)
-#define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN)
-#define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN, val)
-
-
-/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
-#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
-#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
-#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
-#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
-#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
-#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX, val)
-#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX)
-#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX)
-#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX, val)
-#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
-#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
-#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
-#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
-#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
-#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
-#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
-#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
-#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
-#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
-#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
-#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
-#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
-#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
-#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
-#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
-
-
-/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
-#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val)
-#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val)
-#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
-#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
-#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
-#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
-#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX, val)
-#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX, val)
-#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX)
-#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX, val)
-#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX)
-#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX, val)
-#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
-#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val)
-#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
-#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val)
-#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val)
-#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val)
-#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val)
-#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val)
-#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
-#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val)
-#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
-#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val)
-#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
-#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val)
-#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
-#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val)
-#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
-#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val)
-#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
-#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val)
-#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
-#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val)
-#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
-#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val)
-
-
-/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
-#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val)
-#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
-#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
-#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
-#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val)
-#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL)
-#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val)
-#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
-#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val)
-#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
-#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val)
-
-
-/* DMA Traffic Control Registers */
-#define bfin_read_DMAC_TC_PER() bfin_read16(DMAC_TC_PER)
-#define bfin_write_DMAC_TC_PER(val) bfin_write16(DMAC_TC_PER, val)
-#define bfin_read_DMAC_TC_CNT() bfin_read16(DMAC_TC_CNT)
-#define bfin_write_DMAC_TC_CNT(val) bfin_write16(DMAC_TC_CNT, val)
-
-/* DMA Controller */
-#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
-#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val)
-#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val)
-#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val)
-#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
-#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val)
-#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
-#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val)
-#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val)
-#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val)
-#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val)
-#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val)
-#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
-#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
-#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
-#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
-#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
-#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
-#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
-#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
-#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val)
-#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val)
-#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
-#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val)
-#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
-#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val)
-#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val)
-#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val)
-#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val)
-#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
-#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
-#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
-#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
-#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
-#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
-#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val)
-#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val)
-#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
-#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val)
-#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
-#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val)
-#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val)
-#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val)
-#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val)
-#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
-#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
-#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
-#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
-#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
-#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
-#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val)
-#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val)
-#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val)
-#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
-#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val)
-#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
-#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val)
-#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val)
-#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val)
-#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val)
-#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val)
-#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
-#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
-#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
-#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
-#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
-#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
-#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
-#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
-#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val)
-#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val)
-#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val)
-#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
-#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val)
-#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
-#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val)
-#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val)
-#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val)
-#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val)
-#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val)
-#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
-#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
-#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
-#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
-#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
-#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
-#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
-#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
-#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
-#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val)
-#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val)
-#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
-#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val)
-#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
-#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
-#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val)
-#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val)
-#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val)
-#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val)
-#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
-#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
-#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
-#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
-#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
-#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
-#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
-#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
-#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val)
-#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
-#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val)
-#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
-#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val)
-#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
-#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val)
-#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val)
-#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val)
-#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val)
-#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val)
-#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
-#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
-#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
-#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
-#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
-#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
-#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
-#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
-#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val)
-#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val)
-#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val)
-#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
-#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val)
-#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
-#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val)
-#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val)
-#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val)
-#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val)
-#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val)
-#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
-#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
-#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
-#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
-#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
-#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
-#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
-#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG)
-#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val)
-#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR)
-#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR, val)
-#define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR)
-#define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR, val)
-#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT)
-#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val)
-#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT)
-#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val)
-#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY)
-#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val)
-#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY)
-#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val)
-#define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR)
-#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR, val)
-#define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR)
-#define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR, val)
-#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT)
-#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
-#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT)
-#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
-#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
-#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
-#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
-#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG)
-#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val)
-#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR)
-#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR, val)
-#define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR)
-#define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR, val)
-#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT)
-#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val)
-#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT)
-#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val)
-#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY)
-#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val)
-#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY)
-#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val)
-#define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR)
-#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR, val)
-#define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR)
-#define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR, val)
-#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT)
-#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
-#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT)
-#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
-#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS)
-#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
-#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
-#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG)
-#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val)
-#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR)
-#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR, val)
-#define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR)
-#define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR, val)
-#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT)
-#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val)
-#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT)
-#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val)
-#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY)
-#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
-#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY)
-#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
-#define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR)
-#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR, val)
-#define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR)
-#define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR, val)
-#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
-#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
-#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
-#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
-#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS)
-#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
-#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
-#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG)
-#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val)
-#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR)
-#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR, val)
-#define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR)
-#define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR, val)
-#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT)
-#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val)
-#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT)
-#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val)
-#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY)
-#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
-#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY)
-#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
-#define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR)
-#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR, val)
-#define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR)
-#define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR, val)
-#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
-#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
-#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
-#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
-#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS)
-#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
-#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
-#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
-
-#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
-#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
-#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR)
-#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val)
-#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
-#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
-#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
-#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
-#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
-#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
-#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
-#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
-#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR)
-#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR, val)
-#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
-#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
-#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
-#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
-
-#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
-#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
-#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR)
-#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR, val)
-#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
-#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
-#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
-#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
-#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
-#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
-#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
-#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
-#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR)
-#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR, val)
-#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
-#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
-#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
-#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
-
-#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
-#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
-#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR)
-#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR, val)
-#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
-#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
-#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
-#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
-#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
-#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
-#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
-#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
-#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR)
-#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR, val)
-#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
-#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
-#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
-#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
-
-#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
-#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
-#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR)
-#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR, val)
-#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
-#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
-#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
-#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
-#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
-#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
-#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
-#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
-#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR)
-#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR, val)
-#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
-#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
-#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
-#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
-
-
-/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
-#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL)
-#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val)
-#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS)
-#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val)
-#define bfin_clear_PPI_STATUS() bfin_write_PPI_STATUS(0xFFFF)
-#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY)
-#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val)
-#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT)
-#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val)
-#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME)
-#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val)
-
-
-/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
-
-/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
-#define bfin_read_PORTGIO() bfin_read16(PORTGIO)
-#define bfin_write_PORTGIO(val) bfin_write16(PORTGIO, val)
-#define bfin_read_PORTGIO_CLEAR() bfin_read16(PORTGIO_CLEAR)
-#define bfin_write_PORTGIO_CLEAR(val) bfin_write16(PORTGIO_CLEAR, val)
-#define bfin_read_PORTGIO_SET() bfin_read16(PORTGIO_SET)
-#define bfin_write_PORTGIO_SET(val) bfin_write16(PORTGIO_SET, val)
-#define bfin_read_PORTGIO_TOGGLE() bfin_read16(PORTGIO_TOGGLE)
-#define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE, val)
-#define bfin_read_PORTGIO_MASKA() bfin_read16(PORTGIO_MASKA)
-#define bfin_write_PORTGIO_MASKA(val) bfin_write16(PORTGIO_MASKA, val)
-#define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR)
-#define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR, val)
-#define bfin_read_PORTGIO_MASKA_SET() bfin_read16(PORTGIO_MASKA_SET)
-#define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET, val)
-#define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE)
-#define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTGIO_MASKB() bfin_read16(PORTGIO_MASKB)
-#define bfin_write_PORTGIO_MASKB(val) bfin_write16(PORTGIO_MASKB, val)
-#define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR)
-#define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR, val)
-#define bfin_read_PORTGIO_MASKB_SET() bfin_read16(PORTGIO_MASKB_SET)
-#define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET, val)
-#define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE)
-#define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTGIO_DIR() bfin_read16(PORTGIO_DIR)
-#define bfin_write_PORTGIO_DIR(val) bfin_write16(PORTGIO_DIR, val)
-#define bfin_read_PORTGIO_POLAR() bfin_read16(PORTGIO_POLAR)
-#define bfin_write_PORTGIO_POLAR(val) bfin_write16(PORTGIO_POLAR, val)
-#define bfin_read_PORTGIO_EDGE() bfin_read16(PORTGIO_EDGE)
-#define bfin_write_PORTGIO_EDGE(val) bfin_write16(PORTGIO_EDGE, val)
-#define bfin_read_PORTGIO_BOTH() bfin_read16(PORTGIO_BOTH)
-#define bfin_write_PORTGIO_BOTH(val) bfin_write16(PORTGIO_BOTH, val)
-#define bfin_read_PORTGIO_INEN() bfin_read16(PORTGIO_INEN)
-#define bfin_write_PORTGIO_INEN(val) bfin_write16(PORTGIO_INEN, val)
-
-
-/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
-#define bfin_read_PORTHIO() bfin_read16(PORTHIO)
-#define bfin_write_PORTHIO(val) bfin_write16(PORTHIO, val)
-#define bfin_read_PORTHIO_CLEAR() bfin_read16(PORTHIO_CLEAR)
-#define bfin_write_PORTHIO_CLEAR(val) bfin_write16(PORTHIO_CLEAR, val)
-#define bfin_read_PORTHIO_SET() bfin_read16(PORTHIO_SET)
-#define bfin_write_PORTHIO_SET(val) bfin_write16(PORTHIO_SET, val)
-#define bfin_read_PORTHIO_TOGGLE() bfin_read16(PORTHIO_TOGGLE)
-#define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE, val)
-#define bfin_read_PORTHIO_MASKA() bfin_read16(PORTHIO_MASKA)
-#define bfin_write_PORTHIO_MASKA(val) bfin_write16(PORTHIO_MASKA, val)
-#define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR)
-#define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR, val)
-#define bfin_read_PORTHIO_MASKA_SET() bfin_read16(PORTHIO_MASKA_SET)
-#define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET, val)
-#define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE)
-#define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTHIO_MASKB() bfin_read16(PORTHIO_MASKB)
-#define bfin_write_PORTHIO_MASKB(val) bfin_write16(PORTHIO_MASKB, val)
-#define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR)
-#define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR, val)
-#define bfin_read_PORTHIO_MASKB_SET() bfin_read16(PORTHIO_MASKB_SET)
-#define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET, val)
-#define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE)
-#define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTHIO_DIR() bfin_read16(PORTHIO_DIR)
-#define bfin_write_PORTHIO_DIR(val) bfin_write16(PORTHIO_DIR, val)
-#define bfin_read_PORTHIO_POLAR() bfin_read16(PORTHIO_POLAR)
-#define bfin_write_PORTHIO_POLAR(val) bfin_write16(PORTHIO_POLAR, val)
-#define bfin_read_PORTHIO_EDGE() bfin_read16(PORTHIO_EDGE)
-#define bfin_write_PORTHIO_EDGE(val) bfin_write16(PORTHIO_EDGE, val)
-#define bfin_read_PORTHIO_BOTH() bfin_read16(PORTHIO_BOTH)
-#define bfin_write_PORTHIO_BOTH(val) bfin_write16(PORTHIO_BOTH, val)
-#define bfin_read_PORTHIO_INEN() bfin_read16(PORTHIO_INEN)
-#define bfin_write_PORTHIO_INEN(val) bfin_write16(PORTHIO_INEN, val)
-
-
-/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
-#define bfin_read_UART1_THR() bfin_read16(UART1_THR)
-#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val)
-#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR)
-#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val)
-#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL)
-#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val)
-#define bfin_read_UART1_IER() bfin_read16(UART1_IER)
-#define bfin_write_UART1_IER(val) bfin_write16(UART1_IER, val)
-#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH)
-#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val)
-#define bfin_read_UART1_IIR() bfin_read16(UART1_IIR)
-#define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR, val)
-#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR)
-#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val)
-#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR)
-#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val)
-#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR)
-#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val)
-#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR)
-#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val)
-#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR)
-#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val)
-#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL)
-#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val)
-
-/* Omit CAN register sets from the cdefBF534.h (CAN is not in the ADSP-BF52x processor) */
-
-/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
-#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER)
-#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val)
-#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER)
-#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val)
-#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER)
-#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val)
-#define bfin_read_PORT_MUX() bfin_read16(PORT_MUX)
-#define bfin_write_PORT_MUX(val) bfin_write16(PORT_MUX, val)
-
-
-/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
-#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
-#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
-#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
-#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
-#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
-#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
-#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
-#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
-#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
-#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
-#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
-#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
-#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
-#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
-
-#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
-#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
-#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
-#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
-#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
-#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
-#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
-#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
-#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
-#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
-#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
-#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
-#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
-#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
-
-/* ==== end from cdefBF534.h ==== */
-
-/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
-
-#define bfin_read_PORTF_MUX() bfin_read16(PORTF_MUX)
-#define bfin_write_PORTF_MUX(val) bfin_write16(PORTF_MUX, val)
-#define bfin_read_PORTG_MUX() bfin_read16(PORTG_MUX)
-#define bfin_write_PORTG_MUX(val) bfin_write16(PORTG_MUX, val)
-#define bfin_read_PORTH_MUX() bfin_read16(PORTH_MUX)
-#define bfin_write_PORTH_MUX(val) bfin_write16(PORTH_MUX, val)
-
-#define bfin_read_PORTF_DRIVE() bfin_read16(PORTF_DRIVE)
-#define bfin_write_PORTF_DRIVE(val) bfin_write16(PORTF_DRIVE, val)
-#define bfin_read_PORTG_DRIVE() bfin_read16(PORTG_DRIVE)
-#define bfin_write_PORTG_DRIVE(val) bfin_write16(PORTG_DRIVE, val)
-#define bfin_read_PORTH_DRIVE() bfin_read16(PORTH_DRIVE)
-#define bfin_write_PORTH_DRIVE(val) bfin_write16(PORTH_DRIVE, val)
-#define bfin_read_PORTF_SLEW() bfin_read16(PORTF_SLEW)
-#define bfin_write_PORTF_SLEW(val) bfin_write16(PORTF_SLEW, val)
-#define bfin_read_PORTG_SLEW() bfin_read16(PORTG_SLEW)
-#define bfin_write_PORTG_SLEW(val) bfin_write16(PORTG_SLEW, val)
-#define bfin_read_PORTH_SLEW() bfin_read16(PORTH_SLEW)
-#define bfin_write_PORTH_SLEW(val) bfin_write16(PORTH_SLEW, val)
-#define bfin_read_PORTF_HYSTERESIS() bfin_read16(PORTF_HYSTERESIS)
-#define bfin_write_PORTF_HYSTERESIS(val) bfin_write16(PORTF_HYSTERESIS, val)
-#define bfin_read_PORTG_HYSTERESIS() bfin_read16(PORTG_HYSTERESIS)
-#define bfin_write_PORTG_HYSTERESIS(val) bfin_write16(PORTG_HYSTERESIS, val)
-#define bfin_read_PORTH_HYSTERESIS() bfin_read16(PORTH_HYSTERESIS)
-#define bfin_write_PORTH_HYSTERESIS(val) bfin_write16(PORTH_HYSTERESIS, val)
-#define bfin_read_MISCPORT_DRIVE() bfin_read16(MISCPORT_DRIVE)
-#define bfin_write_MISCPORT_DRIVE(val) bfin_write16(MISCPORT_DRIVE, val)
-#define bfin_read_MISCPORT_SLEW() bfin_read16(MISCPORT_SLEW)
-#define bfin_write_MISCPORT_SLEW(val) bfin_write16(MISCPORT_SLEW, val)
-#define bfin_read_MISCPORT_HYSTERESIS() bfin_read16(MISCPORT_HYSTERESIS)
-#define bfin_write_MISCPORT_HYSTERESIS(val) bfin_write16(MISCPORT_HYSTERESIS, val)
-
-/* HOST Port Registers */
-
-#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL)
-#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val)
-#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS)
-#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val)
-#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT)
-#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val)
-
-/* Counter Registers */
-
-#define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG)
-#define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val)
-#define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK)
-#define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val)
-#define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS)
-#define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val)
-#define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND)
-#define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val)
-#define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE)
-#define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val)
-#define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER)
-#define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val)
-#define bfin_read_CNT_MAX() bfin_read32(CNT_MAX)
-#define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val)
-#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN)
-#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val)
-
-/* Security Registers */
-
-#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT)
-#define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val)
-#define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL)
-#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
-#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS)
-#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val)
-
-/* NFC Registers */
-
-#define bfin_read_NFC_CTL() bfin_read16(NFC_CTL)
-#define bfin_write_NFC_CTL(val) bfin_write16(NFC_CTL, val)
-#define bfin_read_NFC_STAT() bfin_read16(NFC_STAT)
-#define bfin_write_NFC_STAT(val) bfin_write16(NFC_STAT, val)
-#define bfin_read_NFC_IRQSTAT() bfin_read16(NFC_IRQSTAT)
-#define bfin_write_NFC_IRQSTAT(val) bfin_write16(NFC_IRQSTAT, val)
-#define bfin_read_NFC_IRQMASK() bfin_read16(NFC_IRQMASK)
-#define bfin_write_NFC_IRQMASK(val) bfin_write16(NFC_IRQMASK, val)
-#define bfin_read_NFC_ECC0() bfin_read16(NFC_ECC0)
-#define bfin_write_NFC_ECC0(val) bfin_write16(NFC_ECC0, val)
-#define bfin_read_NFC_ECC1() bfin_read16(NFC_ECC1)
-#define bfin_write_NFC_ECC1(val) bfin_write16(NFC_ECC1, val)
-#define bfin_read_NFC_ECC2() bfin_read16(NFC_ECC2)
-#define bfin_write_NFC_ECC2(val) bfin_write16(NFC_ECC2, val)
-#define bfin_read_NFC_ECC3() bfin_read16(NFC_ECC3)
-#define bfin_write_NFC_ECC3(val) bfin_write16(NFC_ECC3, val)
-#define bfin_read_NFC_COUNT() bfin_read16(NFC_COUNT)
-#define bfin_write_NFC_COUNT(val) bfin_write16(NFC_COUNT, val)
-#define bfin_read_NFC_RST() bfin_read16(NFC_RST)
-#define bfin_write_NFC_RST(val) bfin_write16(NFC_RST, val)
-#define bfin_read_NFC_PGCTL() bfin_read16(NFC_PGCTL)
-#define bfin_write_NFC_PGCTL(val) bfin_write16(NFC_PGCTL, val)
-#define bfin_read_NFC_READ() bfin_read16(NFC_READ)
-#define bfin_write_NFC_READ(val) bfin_write16(NFC_READ, val)
-#define bfin_read_NFC_ADDR() bfin_read16(NFC_ADDR)
-#define bfin_write_NFC_ADDR(val) bfin_write16(NFC_ADDR, val)
-#define bfin_read_NFC_CMD() bfin_read16(NFC_CMD)
-#define bfin_write_NFC_CMD(val) bfin_write16(NFC_CMD, val)
-#define bfin_read_NFC_DATA_WR() bfin_read16(NFC_DATA_WR)
-#define bfin_write_NFC_DATA_WR(val) bfin_write16(NFC_DATA_WR, val)
-#define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD)
-#define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val)
-
-#endif /* _CDEF_BF522_H */
+++ /dev/null
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CDEF_BF525_H
-#define _CDEF_BF525_H
-
-/* BF525 is BF522 + USB */
-#include "cdefBF522.h"
-
-/* USB Control Registers */
-
-#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
-#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
-#define bfin_read_USB_POWER() bfin_read16(USB_POWER)
-#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val)
-#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX)
-#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val)
-#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX)
-#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val)
-#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE)
-#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val)
-#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE)
-#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val)
-#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB)
-#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val)
-#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE)
-#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val)
-#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME)
-#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val)
-#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX)
-#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val)
-#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE)
-#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val)
-#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR)
-#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val)
-#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL)
-#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
-
-/* USB Packet Control Registers */
-
-#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET)
-#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
-#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0)
-#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val)
-#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR)
-#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val)
-#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET)
-#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
-#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR)
-#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val)
-#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0)
-#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val)
-#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT)
-#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val)
-#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE)
-#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val)
-#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0)
-#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val)
-#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL)
-#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
-#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE)
-#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val)
-#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL)
-#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
-#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT)
-#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val)
-
-/* USB Endpoint FIFO Registers */
-
-#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO)
-#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val)
-#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO)
-#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val)
-#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO)
-#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val)
-#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO)
-#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val)
-#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO)
-#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val)
-#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO)
-#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val)
-#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO)
-#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val)
-#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO)
-#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val)
-
-/* USB OTG Control Registers */
-
-#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL)
-#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
-#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ)
-#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
-#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK)
-#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
-
-/* USB Phy Control Registers */
-
-#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO)
-#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val)
-#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN)
-#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val)
-#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1)
-#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val)
-#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1)
-#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val)
-#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1)
-#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val)
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL)
-#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB)
-#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
-
-#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2)
-#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
-
-#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL)
-#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
-#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV)
-#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
-
-/* USB Endpoint 0 Control Registers */
-
-#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP)
-#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
-#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR)
-#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
-#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP)
-#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
-#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR)
-#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
-#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
-#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
-#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE)
-#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
-#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
-#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE)
-#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
-#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
-#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
-#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
-
-/* USB Endpoint 1 Control Registers */
-
-#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP)
-#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
-#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR)
-#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
-#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP)
-#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
-#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR)
-#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
-#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
-#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
-#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE)
-#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
-#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
-#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE)
-#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
-#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
-#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
-#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
-
-/* USB Endpoint 2 Control Registers */
-
-#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP)
-#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
-#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR)
-#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
-#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP)
-#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
-#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR)
-#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
-#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
-#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
-#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE)
-#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
-#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
-#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE)
-#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
-#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
-#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
-#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
-
-/* USB Endpoint 3 Control Registers */
-
-#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP)
-#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
-#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR)
-#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
-#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP)
-#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
-#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR)
-#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
-#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
-#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
-#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE)
-#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
-#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
-#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE)
-#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
-#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
-#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
-#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
-
-/* USB Endpoint 4 Control Registers */
-
-#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP)
-#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
-#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR)
-#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
-#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP)
-#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
-#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR)
-#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
-#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
-#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
-#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE)
-#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
-#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
-#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE)
-#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
-#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
-#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
-#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
-
-/* USB Endpoint 5 Control Registers */
-
-#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP)
-#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
-#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR)
-#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
-#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP)
-#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
-#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR)
-#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
-#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
-#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
-#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE)
-#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
-#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
-#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE)
-#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
-#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
-#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
-#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
-
-/* USB Endpoint 6 Control Registers */
-
-#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP)
-#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
-#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR)
-#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
-#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP)
-#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
-#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR)
-#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
-#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
-#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
-#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE)
-#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
-#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
-#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE)
-#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
-#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
-#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
-#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
-
-/* USB Endpoint 7 Control Registers */
-
-#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP)
-#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
-#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR)
-#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
-#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP)
-#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
-#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR)
-#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
-#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
-#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
-#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE)
-#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
-#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
-#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE)
-#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
-#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
-#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
-#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
-
-#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT)
-#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
-
-/* USB Channel 0 Config Registers */
-
-#define bfin_read_USB_DMA0CONTROL() bfin_read16(USB_DMA0CONTROL)
-#define bfin_write_USB_DMA0CONTROL(val) bfin_write16(USB_DMA0CONTROL, val)
-#define bfin_read_USB_DMA0ADDRLOW() bfin_read16(USB_DMA0ADDRLOW)
-#define bfin_write_USB_DMA0ADDRLOW(val) bfin_write16(USB_DMA0ADDRLOW, val)
-#define bfin_read_USB_DMA0ADDRHIGH() bfin_read16(USB_DMA0ADDRHIGH)
-#define bfin_write_USB_DMA0ADDRHIGH(val) bfin_write16(USB_DMA0ADDRHIGH, val)
-#define bfin_read_USB_DMA0COUNTLOW() bfin_read16(USB_DMA0COUNTLOW)
-#define bfin_write_USB_DMA0COUNTLOW(val) bfin_write16(USB_DMA0COUNTLOW, val)
-#define bfin_read_USB_DMA0COUNTHIGH() bfin_read16(USB_DMA0COUNTHIGH)
-#define bfin_write_USB_DMA0COUNTHIGH(val) bfin_write16(USB_DMA0COUNTHIGH, val)
-
-/* USB Channel 1 Config Registers */
-
-#define bfin_read_USB_DMA1CONTROL() bfin_read16(USB_DMA1CONTROL)
-#define bfin_write_USB_DMA1CONTROL(val) bfin_write16(USB_DMA1CONTROL, val)
-#define bfin_read_USB_DMA1ADDRLOW() bfin_read16(USB_DMA1ADDRLOW)
-#define bfin_write_USB_DMA1ADDRLOW(val) bfin_write16(USB_DMA1ADDRLOW, val)
-#define bfin_read_USB_DMA1ADDRHIGH() bfin_read16(USB_DMA1ADDRHIGH)
-#define bfin_write_USB_DMA1ADDRHIGH(val) bfin_write16(USB_DMA1ADDRHIGH, val)
-#define bfin_read_USB_DMA1COUNTLOW() bfin_read16(USB_DMA1COUNTLOW)
-#define bfin_write_USB_DMA1COUNTLOW(val) bfin_write16(USB_DMA1COUNTLOW, val)
-#define bfin_read_USB_DMA1COUNTHIGH() bfin_read16(USB_DMA1COUNTHIGH)
-#define bfin_write_USB_DMA1COUNTHIGH(val) bfin_write16(USB_DMA1COUNTHIGH, val)
-
-/* USB Channel 2 Config Registers */
-
-#define bfin_read_USB_DMA2CONTROL() bfin_read16(USB_DMA2CONTROL)
-#define bfin_write_USB_DMA2CONTROL(val) bfin_write16(USB_DMA2CONTROL, val)
-#define bfin_read_USB_DMA2ADDRLOW() bfin_read16(USB_DMA2ADDRLOW)
-#define bfin_write_USB_DMA2ADDRLOW(val) bfin_write16(USB_DMA2ADDRLOW, val)
-#define bfin_read_USB_DMA2ADDRHIGH() bfin_read16(USB_DMA2ADDRHIGH)
-#define bfin_write_USB_DMA2ADDRHIGH(val) bfin_write16(USB_DMA2ADDRHIGH, val)
-#define bfin_read_USB_DMA2COUNTLOW() bfin_read16(USB_DMA2COUNTLOW)
-#define bfin_write_USB_DMA2COUNTLOW(val) bfin_write16(USB_DMA2COUNTLOW, val)
-#define bfin_read_USB_DMA2COUNTHIGH() bfin_read16(USB_DMA2COUNTHIGH)
-#define bfin_write_USB_DMA2COUNTHIGH(val) bfin_write16(USB_DMA2COUNTHIGH, val)
-
-/* USB Channel 3 Config Registers */
-
-#define bfin_read_USB_DMA3CONTROL() bfin_read16(USB_DMA3CONTROL)
-#define bfin_write_USB_DMA3CONTROL(val) bfin_write16(USB_DMA3CONTROL, val)
-#define bfin_read_USB_DMA3ADDRLOW() bfin_read16(USB_DMA3ADDRLOW)
-#define bfin_write_USB_DMA3ADDRLOW(val) bfin_write16(USB_DMA3ADDRLOW, val)
-#define bfin_read_USB_DMA3ADDRHIGH() bfin_read16(USB_DMA3ADDRHIGH)
-#define bfin_write_USB_DMA3ADDRHIGH(val) bfin_write16(USB_DMA3ADDRHIGH, val)
-#define bfin_read_USB_DMA3COUNTLOW() bfin_read16(USB_DMA3COUNTLOW)
-#define bfin_write_USB_DMA3COUNTLOW(val) bfin_write16(USB_DMA3COUNTLOW, val)
-#define bfin_read_USB_DMA3COUNTHIGH() bfin_read16(USB_DMA3COUNTHIGH)
-#define bfin_write_USB_DMA3COUNTHIGH(val) bfin_write16(USB_DMA3COUNTHIGH, val)
-
-/* USB Channel 4 Config Registers */
-
-#define bfin_read_USB_DMA4CONTROL() bfin_read16(USB_DMA4CONTROL)
-#define bfin_write_USB_DMA4CONTROL(val) bfin_write16(USB_DMA4CONTROL, val)
-#define bfin_read_USB_DMA4ADDRLOW() bfin_read16(USB_DMA4ADDRLOW)
-#define bfin_write_USB_DMA4ADDRLOW(val) bfin_write16(USB_DMA4ADDRLOW, val)
-#define bfin_read_USB_DMA4ADDRHIGH() bfin_read16(USB_DMA4ADDRHIGH)
-#define bfin_write_USB_DMA4ADDRHIGH(val) bfin_write16(USB_DMA4ADDRHIGH, val)
-#define bfin_read_USB_DMA4COUNTLOW() bfin_read16(USB_DMA4COUNTLOW)
-#define bfin_write_USB_DMA4COUNTLOW(val) bfin_write16(USB_DMA4COUNTLOW, val)
-#define bfin_read_USB_DMA4COUNTHIGH() bfin_read16(USB_DMA4COUNTHIGH)
-#define bfin_write_USB_DMA4COUNTHIGH(val) bfin_write16(USB_DMA4COUNTHIGH, val)
-
-/* USB Channel 5 Config Registers */
-
-#define bfin_read_USB_DMA5CONTROL() bfin_read16(USB_DMA5CONTROL)
-#define bfin_write_USB_DMA5CONTROL(val) bfin_write16(USB_DMA5CONTROL, val)
-#define bfin_read_USB_DMA5ADDRLOW() bfin_read16(USB_DMA5ADDRLOW)
-#define bfin_write_USB_DMA5ADDRLOW(val) bfin_write16(USB_DMA5ADDRLOW, val)
-#define bfin_read_USB_DMA5ADDRHIGH() bfin_read16(USB_DMA5ADDRHIGH)
-#define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val)
-#define bfin_read_USB_DMA5COUNTLOW() bfin_read16(USB_DMA5COUNTLOW)
-#define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val)
-#define bfin_read_USB_DMA5COUNTHIGH() bfin_read16(USB_DMA5COUNTHIGH)
-#define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val)
-
-/* USB Channel 6 Config Registers */
-
-#define bfin_read_USB_DMA6CONTROL() bfin_read16(USB_DMA6CONTROL)
-#define bfin_write_USB_DMA6CONTROL(val) bfin_write16(USB_DMA6CONTROL, val)
-#define bfin_read_USB_DMA6ADDRLOW() bfin_read16(USB_DMA6ADDRLOW)
-#define bfin_write_USB_DMA6ADDRLOW(val) bfin_write16(USB_DMA6ADDRLOW, val)
-#define bfin_read_USB_DMA6ADDRHIGH() bfin_read16(USB_DMA6ADDRHIGH)
-#define bfin_write_USB_DMA6ADDRHIGH(val) bfin_write16(USB_DMA6ADDRHIGH, val)
-#define bfin_read_USB_DMA6COUNTLOW() bfin_read16(USB_DMA6COUNTLOW)
-#define bfin_write_USB_DMA6COUNTLOW(val) bfin_write16(USB_DMA6COUNTLOW, val)
-#define bfin_read_USB_DMA6COUNTHIGH() bfin_read16(USB_DMA6COUNTHIGH)
-#define bfin_write_USB_DMA6COUNTHIGH(val) bfin_write16(USB_DMA6COUNTHIGH, val)
-
-/* USB Channel 7 Config Registers */
-
-#define bfin_read_USB_DMA7CONTROL() bfin_read16(USB_DMA7CONTROL)
-#define bfin_write_USB_DMA7CONTROL(val) bfin_write16(USB_DMA7CONTROL, val)
-#define bfin_read_USB_DMA7ADDRLOW() bfin_read16(USB_DMA7ADDRLOW)
-#define bfin_write_USB_DMA7ADDRLOW(val) bfin_write16(USB_DMA7ADDRLOW, val)
-#define bfin_read_USB_DMA7ADDRHIGH() bfin_read16(USB_DMA7ADDRHIGH)
-#define bfin_write_USB_DMA7ADDRHIGH(val) bfin_write16(USB_DMA7ADDRHIGH, val)
-#define bfin_read_USB_DMA7COUNTLOW() bfin_read16(USB_DMA7COUNTLOW)
-#define bfin_write_USB_DMA7COUNTLOW(val) bfin_write16(USB_DMA7COUNTLOW, val)
-#define bfin_read_USB_DMA7COUNTHIGH() bfin_read16(USB_DMA7COUNTHIGH)
-#define bfin_write_USB_DMA7COUNTHIGH(val) bfin_write16(USB_DMA7COUNTHIGH, val)
-
-#endif /* _CDEF_BF525_H */
+++ /dev/null
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CDEF_BF527_H
-#define _CDEF_BF527_H
-
-/* BF527 is BF525 + EMAC */
-#include "cdefBF525.h"
-
-/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
-
-#define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE)
-#define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE, val)
-#define bfin_read_EMAC_ADDRLO() bfin_read32(EMAC_ADDRLO)
-#define bfin_write_EMAC_ADDRLO(val) bfin_write32(EMAC_ADDRLO, val)
-#define bfin_read_EMAC_ADDRHI() bfin_read32(EMAC_ADDRHI)
-#define bfin_write_EMAC_ADDRHI(val) bfin_write32(EMAC_ADDRHI, val)
-#define bfin_read_EMAC_HASHLO() bfin_read32(EMAC_HASHLO)
-#define bfin_write_EMAC_HASHLO(val) bfin_write32(EMAC_HASHLO, val)
-#define bfin_read_EMAC_HASHHI() bfin_read32(EMAC_HASHHI)
-#define bfin_write_EMAC_HASHHI(val) bfin_write32(EMAC_HASHHI, val)
-#define bfin_read_EMAC_STAADD() bfin_read32(EMAC_STAADD)
-#define bfin_write_EMAC_STAADD(val) bfin_write32(EMAC_STAADD, val)
-#define bfin_read_EMAC_STADAT() bfin_read32(EMAC_STADAT)
-#define bfin_write_EMAC_STADAT(val) bfin_write32(EMAC_STADAT, val)
-#define bfin_read_EMAC_FLC() bfin_read32(EMAC_FLC)
-#define bfin_write_EMAC_FLC(val) bfin_write32(EMAC_FLC, val)
-#define bfin_read_EMAC_VLAN1() bfin_read32(EMAC_VLAN1)
-#define bfin_write_EMAC_VLAN1(val) bfin_write32(EMAC_VLAN1, val)
-#define bfin_read_EMAC_VLAN2() bfin_read32(EMAC_VLAN2)
-#define bfin_write_EMAC_VLAN2(val) bfin_write32(EMAC_VLAN2, val)
-#define bfin_read_EMAC_WKUP_CTL() bfin_read32(EMAC_WKUP_CTL)
-#define bfin_write_EMAC_WKUP_CTL(val) bfin_write32(EMAC_WKUP_CTL, val)
-#define bfin_read_EMAC_WKUP_FFMSK0() bfin_read32(EMAC_WKUP_FFMSK0)
-#define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0, val)
-#define bfin_read_EMAC_WKUP_FFMSK1() bfin_read32(EMAC_WKUP_FFMSK1)
-#define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1, val)
-#define bfin_read_EMAC_WKUP_FFMSK2() bfin_read32(EMAC_WKUP_FFMSK2)
-#define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2, val)
-#define bfin_read_EMAC_WKUP_FFMSK3() bfin_read32(EMAC_WKUP_FFMSK3)
-#define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3, val)
-#define bfin_read_EMAC_WKUP_FFCMD() bfin_read32(EMAC_WKUP_FFCMD)
-#define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD, val)
-#define bfin_read_EMAC_WKUP_FFOFF() bfin_read32(EMAC_WKUP_FFOFF)
-#define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF, val)
-#define bfin_read_EMAC_WKUP_FFCRC0() bfin_read32(EMAC_WKUP_FFCRC0)
-#define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0, val)
-#define bfin_read_EMAC_WKUP_FFCRC1() bfin_read32(EMAC_WKUP_FFCRC1)
-#define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1, val)
-
-#define bfin_read_EMAC_SYSCTL() bfin_read32(EMAC_SYSCTL)
-#define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL, val)
-#define bfin_read_EMAC_SYSTAT() bfin_read32(EMAC_SYSTAT)
-#define bfin_write_EMAC_SYSTAT(val) bfin_write32(EMAC_SYSTAT, val)
-#define bfin_read_EMAC_RX_STAT() bfin_read32(EMAC_RX_STAT)
-#define bfin_write_EMAC_RX_STAT(val) bfin_write32(EMAC_RX_STAT, val)
-#define bfin_read_EMAC_RX_STKY() bfin_read32(EMAC_RX_STKY)
-#define bfin_write_EMAC_RX_STKY(val) bfin_write32(EMAC_RX_STKY, val)
-#define bfin_read_EMAC_RX_IRQE() bfin_read32(EMAC_RX_IRQE)
-#define bfin_write_EMAC_RX_IRQE(val) bfin_write32(EMAC_RX_IRQE, val)
-#define bfin_read_EMAC_TX_STAT() bfin_read32(EMAC_TX_STAT)
-#define bfin_write_EMAC_TX_STAT(val) bfin_write32(EMAC_TX_STAT, val)
-#define bfin_read_EMAC_TX_STKY() bfin_read32(EMAC_TX_STKY)
-#define bfin_write_EMAC_TX_STKY(val) bfin_write32(EMAC_TX_STKY, val)
-#define bfin_read_EMAC_TX_IRQE() bfin_read32(EMAC_TX_IRQE)
-#define bfin_write_EMAC_TX_IRQE(val) bfin_write32(EMAC_TX_IRQE, val)
-
-#define bfin_read_EMAC_MMC_CTL() bfin_read32(EMAC_MMC_CTL)
-#define bfin_write_EMAC_MMC_CTL(val) bfin_write32(EMAC_MMC_CTL, val)
-#define bfin_read_EMAC_MMC_RIRQS() bfin_read32(EMAC_MMC_RIRQS)
-#define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS, val)
-#define bfin_read_EMAC_MMC_RIRQE() bfin_read32(EMAC_MMC_RIRQE)
-#define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE, val)
-#define bfin_read_EMAC_MMC_TIRQS() bfin_read32(EMAC_MMC_TIRQS)
-#define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS, val)
-#define bfin_read_EMAC_MMC_TIRQE() bfin_read32(EMAC_MMC_TIRQE)
-#define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE, val)
-
-#define bfin_read_EMAC_RXC_OK() bfin_read32(EMAC_RXC_OK)
-#define bfin_write_EMAC_RXC_OK(val) bfin_write32(EMAC_RXC_OK, val)
-#define bfin_read_EMAC_RXC_FCS() bfin_read32(EMAC_RXC_FCS)
-#define bfin_write_EMAC_RXC_FCS(val) bfin_write32(EMAC_RXC_FCS, val)
-#define bfin_read_EMAC_RXC_ALIGN() bfin_read32(EMAC_RXC_ALIGN)
-#define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN, val)
-#define bfin_read_EMAC_RXC_OCTET() bfin_read32(EMAC_RXC_OCTET)
-#define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET, val)
-#define bfin_read_EMAC_RXC_DMAOVF() bfin_read32(EMAC_RXC_DMAOVF)
-#define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF, val)
-#define bfin_read_EMAC_RXC_UNICST() bfin_read32(EMAC_RXC_UNICST)
-#define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST, val)
-#define bfin_read_EMAC_RXC_MULTI() bfin_read32(EMAC_RXC_MULTI)
-#define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI, val)
-#define bfin_read_EMAC_RXC_BROAD() bfin_read32(EMAC_RXC_BROAD)
-#define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD, val)
-#define bfin_read_EMAC_RXC_LNERRI() bfin_read32(EMAC_RXC_LNERRI)
-#define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI, val)
-#define bfin_read_EMAC_RXC_LNERRO() bfin_read32(EMAC_RXC_LNERRO)
-#define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO, val)
-#define bfin_read_EMAC_RXC_LONG() bfin_read32(EMAC_RXC_LONG)
-#define bfin_write_EMAC_RXC_LONG(val) bfin_write32(EMAC_RXC_LONG, val)
-#define bfin_read_EMAC_RXC_MACCTL() bfin_read32(EMAC_RXC_MACCTL)
-#define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL, val)
-#define bfin_read_EMAC_RXC_OPCODE() bfin_read32(EMAC_RXC_OPCODE)
-#define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE, val)
-#define bfin_read_EMAC_RXC_PAUSE() bfin_read32(EMAC_RXC_PAUSE)
-#define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE, val)
-#define bfin_read_EMAC_RXC_ALLFRM() bfin_read32(EMAC_RXC_ALLFRM)
-#define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM, val)
-#define bfin_read_EMAC_RXC_ALLOCT() bfin_read32(EMAC_RXC_ALLOCT)
-#define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT, val)
-#define bfin_read_EMAC_RXC_TYPED() bfin_read32(EMAC_RXC_TYPED)
-#define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED, val)
-#define bfin_read_EMAC_RXC_SHORT() bfin_read32(EMAC_RXC_SHORT)
-#define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT, val)
-#define bfin_read_EMAC_RXC_EQ64() bfin_read32(EMAC_RXC_EQ64)
-#define bfin_write_EMAC_RXC_EQ64(val) bfin_write32(EMAC_RXC_EQ64, val)
-#define bfin_read_EMAC_RXC_LT128() bfin_read32(EMAC_RXC_LT128)
-#define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128, val)
-#define bfin_read_EMAC_RXC_LT256() bfin_read32(EMAC_RXC_LT256)
-#define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256, val)
-#define bfin_read_EMAC_RXC_LT512() bfin_read32(EMAC_RXC_LT512)
-#define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512, val)
-#define bfin_read_EMAC_RXC_LT1024() bfin_read32(EMAC_RXC_LT1024)
-#define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024, val)
-#define bfin_read_EMAC_RXC_GE1024() bfin_read32(EMAC_RXC_GE1024)
-#define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024, val)
-
-#define bfin_read_EMAC_TXC_OK() bfin_read32(EMAC_TXC_OK)
-#define bfin_write_EMAC_TXC_OK(val) bfin_write32(EMAC_TXC_OK, val)
-#define bfin_read_EMAC_TXC_1COL() bfin_read32(EMAC_TXC_1COL)
-#define bfin_write_EMAC_TXC_1COL(val) bfin_write32(EMAC_TXC_1COL, val)
-#define bfin_read_EMAC_TXC_GT1COL() bfin_read32(EMAC_TXC_GT1COL)
-#define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL, val)
-#define bfin_read_EMAC_TXC_OCTET() bfin_read32(EMAC_TXC_OCTET)
-#define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET, val)
-#define bfin_read_EMAC_TXC_DEFER() bfin_read32(EMAC_TXC_DEFER)
-#define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER, val)
-#define bfin_read_EMAC_TXC_LATECL() bfin_read32(EMAC_TXC_LATECL)
-#define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL, val)
-#define bfin_read_EMAC_TXC_XS_COL() bfin_read32(EMAC_TXC_XS_COL)
-#define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL, val)
-#define bfin_read_EMAC_TXC_DMAUND() bfin_read32(EMAC_TXC_DMAUND)
-#define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND, val)
-#define bfin_read_EMAC_TXC_CRSERR() bfin_read32(EMAC_TXC_CRSERR)
-#define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR, val)
-#define bfin_read_EMAC_TXC_UNICST() bfin_read32(EMAC_TXC_UNICST)
-#define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST, val)
-#define bfin_read_EMAC_TXC_MULTI() bfin_read32(EMAC_TXC_MULTI)
-#define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI, val)
-#define bfin_read_EMAC_TXC_BROAD() bfin_read32(EMAC_TXC_BROAD)
-#define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD, val)
-#define bfin_read_EMAC_TXC_XS_DFR() bfin_read32(EMAC_TXC_XS_DFR)
-#define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR, val)
-#define bfin_read_EMAC_TXC_MACCTL() bfin_read32(EMAC_TXC_MACCTL)
-#define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL, val)
-#define bfin_read_EMAC_TXC_ALLFRM() bfin_read32(EMAC_TXC_ALLFRM)
-#define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM, val)
-#define bfin_read_EMAC_TXC_ALLOCT() bfin_read32(EMAC_TXC_ALLOCT)
-#define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT, val)
-#define bfin_read_EMAC_TXC_EQ64() bfin_read32(EMAC_TXC_EQ64)
-#define bfin_write_EMAC_TXC_EQ64(val) bfin_write32(EMAC_TXC_EQ64, val)
-#define bfin_read_EMAC_TXC_LT128() bfin_read32(EMAC_TXC_LT128)
-#define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128, val)
-#define bfin_read_EMAC_TXC_LT256() bfin_read32(EMAC_TXC_LT256)
-#define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256, val)
-#define bfin_read_EMAC_TXC_LT512() bfin_read32(EMAC_TXC_LT512)
-#define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512, val)
-#define bfin_read_EMAC_TXC_LT1024() bfin_read32(EMAC_TXC_LT1024)
-#define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024, val)
-#define bfin_read_EMAC_TXC_GE1024() bfin_read32(EMAC_TXC_GE1024)
-#define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024, val)
-#define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT)
-#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val)
-
-#endif /* _CDEF_BF527_H */
+++ /dev/null
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF522_H
-#define _DEF_BF522_H
-
-/* ************************************************************** */
-/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF52x */
-/* ************************************************************** */
-
-/* ==== begin from defBF534.h ==== */
-
-/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
-#define PLL_CTL 0xFFC00000 /* PLL Control Register */
-#define PLL_DIV 0xFFC00004 /* PLL Divide Register */
-#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */
-#define PLL_STAT 0xFFC0000C /* PLL Status Register */
-#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */
-#define CHIPID 0xFFC00014 /* Device ID Register */
-
-
-/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
-#define SWRST 0xFFC00100 /* Software Reset Register */
-#define SYSCR 0xFFC00104 /* System Configuration Register */
-#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
-
-#define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */
-#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
-#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
-#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
-#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */
-#define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */
-#define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */
-
-/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */
-#define SIC_IMASK1 0xFFC0014C /* Interrupt Mask register of SIC2 */
-#define SIC_IAR4 0xFFC00150 /* Interrupt Assignment register4 */
-#define SIC_IAR5 0xFFC00154 /* Interrupt Assignment register5 */
-#define SIC_IAR6 0xFFC00158 /* Interrupt Assignment register6 */
-#define SIC_IAR7 0xFFC0015C /* Interrupt Assignment register7 */
-#define SIC_ISR1 0xFFC00160 /* Interrupt Statur register */
-#define SIC_IWR1 0xFFC00164 /* Interrupt Wakeup register */
-
-
-/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
-#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
-#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
-#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
-
-
-/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
-#define RTC_STAT 0xFFC00300 /* RTC Status Register */
-#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
-#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
-#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
-#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */
-#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */
-#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Alternate Macro */
-
-
-/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
-#define UART0_THR 0xFFC00400 /* Transmit Holding register */
-#define UART0_RBR 0xFFC00400 /* Receive Buffer register */
-#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
-#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */
-#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
-#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */
-#define UART0_LCR 0xFFC0040C /* Line Control Register */
-#define UART0_MCR 0xFFC00410 /* Modem Control Register */
-#define UART0_LSR 0xFFC00414 /* Line Status Register */
-#define UART0_MSR 0xFFC00418 /* Modem Status Register */
-#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */
-#define UART0_GCTL 0xFFC00424 /* Global Control Register */
-
-
-/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
-#define SPI0_REGBASE 0xFFC00500
-#define SPI_CTL 0xFFC00500 /* SPI Control Register */
-#define SPI_FLG 0xFFC00504 /* SPI Flag register */
-#define SPI_STAT 0xFFC00508 /* SPI Status register */
-#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */
-#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */
-#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */
-#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */
-
-
-/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
-#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */
-#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */
-#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */
-#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */
-
-#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */
-#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */
-#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */
-#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */
-
-#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */
-#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */
-#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */
-#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */
-
-#define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */
-#define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */
-#define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */
-#define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */
-
-#define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */
-#define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */
-#define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */
-#define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */
-
-#define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */
-#define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */
-#define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */
-#define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */
-
-#define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */
-#define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */
-#define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */
-#define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register */
-
-#define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */
-#define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */
-#define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */
-#define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */
-
-#define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */
-#define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */
-#define TIMER_STATUS 0xFFC00688 /* Timer Status Register */
-
-
-/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
-#define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */
-#define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */
-#define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */
-#define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */
-#define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */
-#define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */
-#define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */
-#define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */
-#define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */
-#define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */
-#define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */
-#define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */
-#define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */
-#define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */
-#define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */
-#define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */
-#define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */
-
-
-/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
-#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
-#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
-#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
-#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
-#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
-#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
-#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
-#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
-#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
-#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
-#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
-#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
-#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
-#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
-#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
-#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
-#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
-#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
-
-
-/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
-#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
-#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
-#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
-#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
-#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
-#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
-#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
-#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
-#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
-#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
-#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
-#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
-#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
-#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
-#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
-#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
-#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
-#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
-
-
-/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
-#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
-#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
-#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
-#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
-#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
-#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
-#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
-
-
-/* DMA Traffic Control Registers */
-#define DMAC_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */
-#define DMAC_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */
-
-/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
-#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
-#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
-#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
-#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
-#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
-#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
-#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
-#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
-#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
-#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
-#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
-#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
-#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
-
-#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
-#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
-#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
-#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
-#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
-#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
-#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
-#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
-#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
-#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
-#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
-#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
-#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
-
-#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
-#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
-#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
-#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
-#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
-#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
-#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
-#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
-#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
-#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
-#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
-#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
-#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
-
-#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
-#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
-#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
-#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
-#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
-#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
-#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
-#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
-#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
-#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
-#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
-#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
-#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
-
-#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
-#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
-#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
-#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
-#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
-#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
-#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
-#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
-#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
-#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
-#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
-#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
-#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
-
-#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
-#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
-#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
-#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
-#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
-#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
-#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
-#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
-#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
-#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
-#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
-#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
-#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
-
-#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
-#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
-#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
-#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
-#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
-#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
-#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
-#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
-#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
-#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
-#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
-#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
-#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
-
-#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
-#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
-#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
-#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
-#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
-#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
-#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
-#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
-#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
-#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
-#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
-#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
-#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
-
-#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
-#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */
-#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */
-#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */
-#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */
-#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */
-#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */
-#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
-#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */
-#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
-#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
-#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */
-#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
-
-#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
-#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */
-#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */
-#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */
-#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */
-#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */
-#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */
-#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
-#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */
-#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
-#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
-#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */
-#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
-
-#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
-#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */
-#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */
-#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */
-#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */
-#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */
-#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
-#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
-#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */
-#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
-#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
-#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
-#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
-
-#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
-#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */
-#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */
-#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */
-#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
-#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */
-#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
-#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
-#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */
-#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
-#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
-#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
-#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
-
-#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
-#define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */
-#define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */
-#define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */
-#define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */
-#define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */
-#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */
-#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
-#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */
-#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */
-#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */
-#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */
-#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */
-
-#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
-#define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */
-#define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */
-#define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */
-#define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */
-#define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */
-#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */
-#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
-#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */
-#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */
-#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */
-#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */
-#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */
-
-#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
-#define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */
-#define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */
-#define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */
-#define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */
-#define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */
-#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */
-#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
-#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */
-#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */
-#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */
-#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */
-#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */
-
-#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
-#define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */
-#define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */
-#define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */
-#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */
-#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */
-#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */
-#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
-#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */
-#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */
-#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */
-#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */
-#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */
-
-
-/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
-#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */
-#define PPI_STATUS 0xFFC01004 /* PPI Status Register */
-#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */
-#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */
-#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
-
-
-/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
-#define TWI0_REGBASE 0xFFC01400
-#define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
-#define TWI0_CONTROL 0xFFC01404 /* TWI Control Register */
-#define TWI0_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
-#define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
-#define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
-#define TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */
-#define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
-#define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
-#define TWI0_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */
-#define TWI0_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */
-#define TWI0_FIFO_CTL 0xFFC01428 /* FIFO Control Register */
-#define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
-#define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
-#define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
-#define TWI0_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */
-#define TWI0_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */
-
-
-/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
-#define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */
-#define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */
-#define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */
-#define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */
-#define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */
-#define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */
-#define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */
-#define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */
-#define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */
-#define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */
-#define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */
-#define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */
-#define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */
-#define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */
-#define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */
-#define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */
-#define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */
-
-
-/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
-#define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */
-#define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */
-#define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */
-#define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */
-#define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */
-#define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */
-#define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */
-#define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */
-#define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */
-#define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */
-#define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */
-#define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */
-#define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */
-#define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */
-#define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */
-#define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */
-#define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */
-
-
-/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
-#define UART1_THR 0xFFC02000 /* Transmit Holding register */
-#define UART1_RBR 0xFFC02000 /* Receive Buffer register */
-#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */
-#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */
-#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */
-#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */
-#define UART1_LCR 0xFFC0200C /* Line Control Register */
-#define UART1_MCR 0xFFC02010 /* Modem Control Register */
-#define UART1_LSR 0xFFC02014 /* Line Status Register */
-#define UART1_MSR 0xFFC02018 /* Modem Status Register */
-#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */
-#define UART1_GCTL 0xFFC02024 /* Global Control Register */
-
-
-/* Omit CAN register sets from the defBF534.h (CAN is not in the ADSP-BF52x processor) */
-
-/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
-#define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */
-#define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */
-#define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */
-#define BFIN_PORT_MUX 0xFFC0320C /* Port Multiplexer Control Register */
-
-
-/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
-#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */
-#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */
-#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */
-#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshold Register */
-#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */
-#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */
-#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */
-
-#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */
-#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */
-#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */
-#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshold Register */
-#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */
-#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */
-#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */
-
-/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
-#define PORTF_MUX 0xFFC03210 /* Port F mux control */
-#define PORTG_MUX 0xFFC03214 /* Port G mux control */
-#define PORTH_MUX 0xFFC03218 /* Port H mux control */
-#define PORTF_DRIVE 0xFFC03220 /* Port F drive strength control */
-#define PORTG_DRIVE 0xFFC03224 /* Port G drive strength control */
-#define PORTH_DRIVE 0xFFC03228 /* Port H drive strength control */
-#define PORTF_SLEW 0xFFC03230 /* Port F slew control */
-#define PORTG_SLEW 0xFFC03234 /* Port G slew control */
-#define PORTH_SLEW 0xFFC03238 /* Port H slew control */
-#define PORTF_HYSTERESIS 0xFFC03240 /* Port F Schmitt trigger control */
-#define PORTG_HYSTERESIS 0xFFC03244 /* Port G Schmitt trigger control */
-#define PORTH_HYSTERESIS 0xFFC03248 /* Port H Schmitt trigger control */
-#define MISCPORT_DRIVE 0xFFC03280 /* Misc Port drive strength control */
-#define MISCPORT_SLEW 0xFFC03284 /* Misc Port slew control */
-#define MISCPORT_HYSTERESIS 0xFFC03288 /* Misc Port Schmitt trigger control */
-
-
-/***********************************************************************************
-** System MMR Register Bits And Macros
-**
-** Disclaimer: All macros are intended to make C and Assembly code more readable.
-** Use these macros carefully, as any that do left shifts for field
-** depositing will result in the lower order bits being destroyed. Any
-** macro that shifts left to properly position the bit-field should be
-** used as part of an OR to initialize a register and NOT as a dynamic
-** modifier UNLESS the lower order bits are saved and ORed back in when
-** the macro is used.
-*************************************************************************************/
-
-/* CHIPID Masks */
-#define CHIPID_VERSION 0xF0000000
-#define CHIPID_FAMILY 0x0FFFF000
-#define CHIPID_MANUFACTURE 0x00000FFE
-
-/* SWRST Masks */
-#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
-#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
-#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
-#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
-#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
-
-/* SYSCR Masks */
-#define BMODE 0x0007 /* Boot Mode - Latched During HW Reset From Mode Pins */
-#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
-
-
-/* ************* SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
-/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK */
-
-#if 0
-#define IRQ_PLL_WAKEUP 0x00000001 /* PLL Wakeup Interrupt */
-
-#define IRQ_ERROR1 0x00000002 /* Error Interrupt (DMA, DMARx Block, DMARx Overflow) */
-#define IRQ_ERROR2 0x00000004 /* Error Interrupt (CAN, Ethernet, SPORTx, PPI, SPI, UARTx) */
-#define IRQ_RTC 0x00000008 /* Real Time Clock Interrupt */
-#define IRQ_DMA0 0x00000010 /* DMA Channel 0 (PPI) Interrupt */
-#define IRQ_DMA3 0x00000020 /* DMA Channel 3 (SPORT0 RX) Interrupt */
-#define IRQ_DMA4 0x00000040 /* DMA Channel 4 (SPORT0 TX) Interrupt */
-#define IRQ_DMA5 0x00000080 /* DMA Channel 5 (SPORT1 RX) Interrupt */
-
-#define IRQ_DMA6 0x00000100 /* DMA Channel 6 (SPORT1 TX) Interrupt */
-#define IRQ_TWI 0x00000200 /* TWI Interrupt */
-#define IRQ_DMA7 0x00000400 /* DMA Channel 7 (SPI) Interrupt */
-#define IRQ_DMA8 0x00000800 /* DMA Channel 8 (UART0 RX) Interrupt */
-#define IRQ_DMA9 0x00001000 /* DMA Channel 9 (UART0 TX) Interrupt */
-#define IRQ_DMA10 0x00002000 /* DMA Channel 10 (UART1 RX) Interrupt */
-#define IRQ_DMA11 0x00004000 /* DMA Channel 11 (UART1 TX) Interrupt */
-#define IRQ_CAN_RX 0x00008000 /* CAN Receive Interrupt */
-
-#define IRQ_CAN_TX 0x00010000 /* CAN Transmit Interrupt */
-#define IRQ_DMA1 0x00020000 /* DMA Channel 1 (Ethernet RX) Interrupt */
-#define IRQ_PFA_PORTH 0x00020000 /* PF Port H (PF47:32) Interrupt A */
-#define IRQ_DMA2 0x00040000 /* DMA Channel 2 (Ethernet TX) Interrupt */
-#define IRQ_PFB_PORTH 0x00040000 /* PF Port H (PF47:32) Interrupt B */
-#define IRQ_TIMER0 0x00080000 /* Timer 0 Interrupt */
-#define IRQ_TIMER1 0x00100000 /* Timer 1 Interrupt */
-#define IRQ_TIMER2 0x00200000 /* Timer 2 Interrupt */
-#define IRQ_TIMER3 0x00400000 /* Timer 3 Interrupt */
-#define IRQ_TIMER4 0x00800000 /* Timer 4 Interrupt */
-
-#define IRQ_TIMER5 0x01000000 /* Timer 5 Interrupt */
-#define IRQ_TIMER6 0x02000000 /* Timer 6 Interrupt */
-#define IRQ_TIMER7 0x04000000 /* Timer 7 Interrupt */
-#define IRQ_PFA_PORTFG 0x08000000 /* PF Ports F&G (PF31:0) Interrupt A */
-#define IRQ_PFB_PORTF 0x80000000 /* PF Port F (PF15:0) Interrupt B */
-#define IRQ_DMA12 0x20000000 /* DMA Channels 12 (MDMA1 Source) RX Interrupt */
-#define IRQ_DMA13 0x20000000 /* DMA Channels 13 (MDMA1 Destination) TX Interrupt */
-#define IRQ_DMA14 0x40000000 /* DMA Channels 14 (MDMA0 Source) RX Interrupt */
-#define IRQ_DMA15 0x40000000 /* DMA Channels 15 (MDMA0 Destination) TX Interrupt */
-#define IRQ_WDOG 0x80000000 /* Software Watchdog Timer Interrupt */
-#define IRQ_PFB_PORTG 0x10000000 /* PF Port G (PF31:16) Interrupt B */
-#endif
-
-/* SIC_IAR0 Macros */
-#define P0_IVG(x) (((x)&0xF)-7) /* Peripheral #0 assigned IVG #x */
-#define P1_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #1 assigned IVG #x */
-#define P2_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #2 assigned IVG #x */
-#define P3_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #3 assigned IVG #x */
-#define P4_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #4 assigned IVG #x */
-#define P5_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #5 assigned IVG #x */
-#define P6_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #6 assigned IVG #x */
-#define P7_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #7 assigned IVG #x */
-
-/* SIC_IAR1 Macros */
-#define P8_IVG(x) (((x)&0xF)-7) /* Peripheral #8 assigned IVG #x */
-#define P9_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #9 assigned IVG #x */
-#define P10_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #10 assigned IVG #x */
-#define P11_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #11 assigned IVG #x */
-#define P12_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #12 assigned IVG #x */
-#define P13_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #13 assigned IVG #x */
-#define P14_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #14 assigned IVG #x */
-#define P15_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #15 assigned IVG #x */
-
-/* SIC_IAR2 Macros */
-#define P16_IVG(x) (((x)&0xF)-7) /* Peripheral #16 assigned IVG #x */
-#define P17_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #17 assigned IVG #x */
-#define P18_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #18 assigned IVG #x */
-#define P19_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #19 assigned IVG #x */
-#define P20_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #20 assigned IVG #x */
-#define P21_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #21 assigned IVG #x */
-#define P22_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #22 assigned IVG #x */
-#define P23_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #23 assigned IVG #x */
-
-/* SIC_IAR3 Macros */
-#define P24_IVG(x) (((x)&0xF)-7) /* Peripheral #24 assigned IVG #x */
-#define P25_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #25 assigned IVG #x */
-#define P26_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #26 assigned IVG #x */
-#define P27_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #27 assigned IVG #x */
-#define P28_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #28 assigned IVG #x */
-#define P29_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #29 assigned IVG #x */
-#define P30_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #30 assigned IVG #x */
-#define P31_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #31 assigned IVG #x */
-
-
-/* SIC_IMASK Masks */
-#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
-#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
-#define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
-#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
-
-/* SIC_IWR Masks */
-#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
-#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
-#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
-#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
-
-/* **************** GENERAL PURPOSE TIMER MASKS **********************/
-/* TIMER_ENABLE Masks */
-#define TIMEN0 0x0001 /* Enable Timer 0 */
-#define TIMEN1 0x0002 /* Enable Timer 1 */
-#define TIMEN2 0x0004 /* Enable Timer 2 */
-#define TIMEN3 0x0008 /* Enable Timer 3 */
-#define TIMEN4 0x0010 /* Enable Timer 4 */
-#define TIMEN5 0x0020 /* Enable Timer 5 */
-#define TIMEN6 0x0040 /* Enable Timer 6 */
-#define TIMEN7 0x0080 /* Enable Timer 7 */
-
-/* TIMER_DISABLE Masks */
-#define TIMDIS0 TIMEN0 /* Disable Timer 0 */
-#define TIMDIS1 TIMEN1 /* Disable Timer 1 */
-#define TIMDIS2 TIMEN2 /* Disable Timer 2 */
-#define TIMDIS3 TIMEN3 /* Disable Timer 3 */
-#define TIMDIS4 TIMEN4 /* Disable Timer 4 */
-#define TIMDIS5 TIMEN5 /* Disable Timer 5 */
-#define TIMDIS6 TIMEN6 /* Disable Timer 6 */
-#define TIMDIS7 TIMEN7 /* Disable Timer 7 */
-
-/* TIMER_STATUS Masks */
-#define TIMIL0 0x00000001 /* Timer 0 Interrupt */
-#define TIMIL1 0x00000002 /* Timer 1 Interrupt */
-#define TIMIL2 0x00000004 /* Timer 2 Interrupt */
-#define TIMIL3 0x00000008 /* Timer 3 Interrupt */
-#define TOVF_ERR0 0x00000010 /* Timer 0 Counter Overflow */
-#define TOVF_ERR1 0x00000020 /* Timer 1 Counter Overflow */
-#define TOVF_ERR2 0x00000040 /* Timer 2 Counter Overflow */
-#define TOVF_ERR3 0x00000080 /* Timer 3 Counter Overflow */
-#define TRUN0 0x00001000 /* Timer 0 Slave Enable Status */
-#define TRUN1 0x00002000 /* Timer 1 Slave Enable Status */
-#define TRUN2 0x00004000 /* Timer 2 Slave Enable Status */
-#define TRUN3 0x00008000 /* Timer 3 Slave Enable Status */
-#define TIMIL4 0x00010000 /* Timer 4 Interrupt */
-#define TIMIL5 0x00020000 /* Timer 5 Interrupt */
-#define TIMIL6 0x00040000 /* Timer 6 Interrupt */
-#define TIMIL7 0x00080000 /* Timer 7 Interrupt */
-#define TOVF_ERR4 0x00100000 /* Timer 4 Counter Overflow */
-#define TOVF_ERR5 0x00200000 /* Timer 5 Counter Overflow */
-#define TOVF_ERR6 0x00400000 /* Timer 6 Counter Overflow */
-#define TOVF_ERR7 0x00800000 /* Timer 7 Counter Overflow */
-#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */
-#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */
-#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */
-#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define TOVL_ERR0 TOVF_ERR0
-#define TOVL_ERR1 TOVF_ERR1
-#define TOVL_ERR2 TOVF_ERR2
-#define TOVL_ERR3 TOVF_ERR3
-#define TOVL_ERR4 TOVF_ERR4
-#define TOVL_ERR5 TOVF_ERR5
-#define TOVL_ERR6 TOVF_ERR6
-#define TOVL_ERR7 TOVF_ERR7
-
-/* TIMERx_CONFIG Masks */
-#define PWM_OUT 0x0001 /* Pulse-Width Modulation Output Mode */
-#define WDTH_CAP 0x0002 /* Width Capture Input Mode */
-#define EXT_CLK 0x0003 /* External Clock Mode */
-#define PULSE_HI 0x0004 /* Action Pulse (Positive/Negative*) */
-#define PERIOD_CNT 0x0008 /* Period Count */
-#define IRQ_ENA 0x0010 /* Interrupt Request Enable */
-#define TIN_SEL 0x0020 /* Timer Input Select */
-#define OUT_DIS 0x0040 /* Output Pad Disable */
-#define CLK_SEL 0x0080 /* Timer Clock Select */
-#define TOGGLE_HI 0x0100 /* PWM_OUT PULSE_HI Toggle Mode */
-#define EMU_RUN 0x0200 /* Emulation Behavior Select */
-#define ERR_TYP 0xC000 /* Error Type */
-
-/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/
-/* EBIU_AMGCTL Masks */
-#define AMCKEN 0x0001 /* Enable CLKOUT */
-#define AMBEN_NONE 0x0000 /* All Banks Disabled */
-#define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */
-#define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */
-#define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */
-#define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */
-
-/* EBIU_AMBCTL0 Masks */
-#define B0RDYEN 0x00000001 /* Bank 0 (B0) RDY Enable */
-#define B0RDYPOL 0x00000002 /* B0 RDY Active High */
-#define B0TT_1 0x00000004 /* B0 Transition Time (Read to Write) = 1 cycle */
-#define B0TT_2 0x00000008 /* B0 Transition Time (Read to Write) = 2 cycles */
-#define B0TT_3 0x0000000C /* B0 Transition Time (Read to Write) = 3 cycles */
-#define B0TT_4 0x00000000 /* B0 Transition Time (Read to Write) = 4 cycles */
-#define B0ST_1 0x00000010 /* B0 Setup Time (AOE to Read/Write) = 1 cycle */
-#define B0ST_2 0x00000020 /* B0 Setup Time (AOE to Read/Write) = 2 cycles */
-#define B0ST_3 0x00000030 /* B0 Setup Time (AOE to Read/Write) = 3 cycles */
-#define B0ST_4 0x00000000 /* B0 Setup Time (AOE to Read/Write) = 4 cycles */
-#define B0HT_1 0x00000040 /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle */
-#define B0HT_2 0x00000080 /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles */
-#define B0HT_3 0x000000C0 /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles */
-#define B0HT_0 0x00000000 /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles */
-#define B0RAT_1 0x00000100 /* B0 Read Access Time = 1 cycle */
-#define B0RAT_2 0x00000200 /* B0 Read Access Time = 2 cycles */
-#define B0RAT_3 0x00000300 /* B0 Read Access Time = 3 cycles */
-#define B0RAT_4 0x00000400 /* B0 Read Access Time = 4 cycles */
-#define B0RAT_5 0x00000500 /* B0 Read Access Time = 5 cycles */
-#define B0RAT_6 0x00000600 /* B0 Read Access Time = 6 cycles */
-#define B0RAT_7 0x00000700 /* B0 Read Access Time = 7 cycles */
-#define B0RAT_8 0x00000800 /* B0 Read Access Time = 8 cycles */
-#define B0RAT_9 0x00000900 /* B0 Read Access Time = 9 cycles */
-#define B0RAT_10 0x00000A00 /* B0 Read Access Time = 10 cycles */
-#define B0RAT_11 0x00000B00 /* B0 Read Access Time = 11 cycles */
-#define B0RAT_12 0x00000C00 /* B0 Read Access Time = 12 cycles */
-#define B0RAT_13 0x00000D00 /* B0 Read Access Time = 13 cycles */
-#define B0RAT_14 0x00000E00 /* B0 Read Access Time = 14 cycles */
-#define B0RAT_15 0x00000F00 /* B0 Read Access Time = 15 cycles */
-#define B0WAT_1 0x00001000 /* B0 Write Access Time = 1 cycle */
-#define B0WAT_2 0x00002000 /* B0 Write Access Time = 2 cycles */
-#define B0WAT_3 0x00003000 /* B0 Write Access Time = 3 cycles */
-#define B0WAT_4 0x00004000 /* B0 Write Access Time = 4 cycles */
-#define B0WAT_5 0x00005000 /* B0 Write Access Time = 5 cycles */
-#define B0WAT_6 0x00006000 /* B0 Write Access Time = 6 cycles */
-#define B0WAT_7 0x00007000 /* B0 Write Access Time = 7 cycles */
-#define B0WAT_8 0x00008000 /* B0 Write Access Time = 8 cycles */
-#define B0WAT_9 0x00009000 /* B0 Write Access Time = 9 cycles */
-#define B0WAT_10 0x0000A000 /* B0 Write Access Time = 10 cycles */
-#define B0WAT_11 0x0000B000 /* B0 Write Access Time = 11 cycles */
-#define B0WAT_12 0x0000C000 /* B0 Write Access Time = 12 cycles */
-#define B0WAT_13 0x0000D000 /* B0 Write Access Time = 13 cycles */
-#define B0WAT_14 0x0000E000 /* B0 Write Access Time = 14 cycles */
-#define B0WAT_15 0x0000F000 /* B0 Write Access Time = 15 cycles */
-
-#define B1RDYEN 0x00010000 /* Bank 1 (B1) RDY Enable */
-#define B1RDYPOL 0x00020000 /* B1 RDY Active High */
-#define B1TT_1 0x00040000 /* B1 Transition Time (Read to Write) = 1 cycle */
-#define B1TT_2 0x00080000 /* B1 Transition Time (Read to Write) = 2 cycles */
-#define B1TT_3 0x000C0000 /* B1 Transition Time (Read to Write) = 3 cycles */
-#define B1TT_4 0x00000000 /* B1 Transition Time (Read to Write) = 4 cycles */
-#define B1ST_1 0x00100000 /* B1 Setup Time (AOE to Read/Write) = 1 cycle */
-#define B1ST_2 0x00200000 /* B1 Setup Time (AOE to Read/Write) = 2 cycles */
-#define B1ST_3 0x00300000 /* B1 Setup Time (AOE to Read/Write) = 3 cycles */
-#define B1ST_4 0x00000000 /* B1 Setup Time (AOE to Read/Write) = 4 cycles */
-#define B1HT_1 0x00400000 /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle */
-#define B1HT_2 0x00800000 /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles */
-#define B1HT_3 0x00C00000 /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles */
-#define B1HT_0 0x00000000 /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles */
-#define B1RAT_1 0x01000000 /* B1 Read Access Time = 1 cycle */
-#define B1RAT_2 0x02000000 /* B1 Read Access Time = 2 cycles */
-#define B1RAT_3 0x03000000 /* B1 Read Access Time = 3 cycles */
-#define B1RAT_4 0x04000000 /* B1 Read Access Time = 4 cycles */
-#define B1RAT_5 0x05000000 /* B1 Read Access Time = 5 cycles */
-#define B1RAT_6 0x06000000 /* B1 Read Access Time = 6 cycles */
-#define B1RAT_7 0x07000000 /* B1 Read Access Time = 7 cycles */
-#define B1RAT_8 0x08000000 /* B1 Read Access Time = 8 cycles */
-#define B1RAT_9 0x09000000 /* B1 Read Access Time = 9 cycles */
-#define B1RAT_10 0x0A000000 /* B1 Read Access Time = 10 cycles */
-#define B1RAT_11 0x0B000000 /* B1 Read Access Time = 11 cycles */
-#define B1RAT_12 0x0C000000 /* B1 Read Access Time = 12 cycles */
-#define B1RAT_13 0x0D000000 /* B1 Read Access Time = 13 cycles */
-#define B1RAT_14 0x0E000000 /* B1 Read Access Time = 14 cycles */
-#define B1RAT_15 0x0F000000 /* B1 Read Access Time = 15 cycles */
-#define B1WAT_1 0x10000000 /* B1 Write Access Time = 1 cycle */
-#define B1WAT_2 0x20000000 /* B1 Write Access Time = 2 cycles */
-#define B1WAT_3 0x30000000 /* B1 Write Access Time = 3 cycles */
-#define B1WAT_4 0x40000000 /* B1 Write Access Time = 4 cycles */
-#define B1WAT_5 0x50000000 /* B1 Write Access Time = 5 cycles */
-#define B1WAT_6 0x60000000 /* B1 Write Access Time = 6 cycles */
-#define B1WAT_7 0x70000000 /* B1 Write Access Time = 7 cycles */
-#define B1WAT_8 0x80000000 /* B1 Write Access Time = 8 cycles */
-#define B1WAT_9 0x90000000 /* B1 Write Access Time = 9 cycles */
-#define B1WAT_10 0xA0000000 /* B1 Write Access Time = 10 cycles */
-#define B1WAT_11 0xB0000000 /* B1 Write Access Time = 11 cycles */
-#define B1WAT_12 0xC0000000 /* B1 Write Access Time = 12 cycles */
-#define B1WAT_13 0xD0000000 /* B1 Write Access Time = 13 cycles */
-#define B1WAT_14 0xE0000000 /* B1 Write Access Time = 14 cycles */
-#define B1WAT_15 0xF0000000 /* B1 Write Access Time = 15 cycles */
-
-/* EBIU_AMBCTL1 Masks */
-#define B2RDYEN 0x00000001 /* Bank 2 (B2) RDY Enable */
-#define B2RDYPOL 0x00000002 /* B2 RDY Active High */
-#define B2TT_1 0x00000004 /* B2 Transition Time (Read to Write) = 1 cycle */
-#define B2TT_2 0x00000008 /* B2 Transition Time (Read to Write) = 2 cycles */
-#define B2TT_3 0x0000000C /* B2 Transition Time (Read to Write) = 3 cycles */
-#define B2TT_4 0x00000000 /* B2 Transition Time (Read to Write) = 4 cycles */
-#define B2ST_1 0x00000010 /* B2 Setup Time (AOE to Read/Write) = 1 cycle */
-#define B2ST_2 0x00000020 /* B2 Setup Time (AOE to Read/Write) = 2 cycles */
-#define B2ST_3 0x00000030 /* B2 Setup Time (AOE to Read/Write) = 3 cycles */
-#define B2ST_4 0x00000000 /* B2 Setup Time (AOE to Read/Write) = 4 cycles */
-#define B2HT_1 0x00000040 /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle */
-#define B2HT_2 0x00000080 /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles */
-#define B2HT_3 0x000000C0 /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles */
-#define B2HT_0 0x00000000 /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles */
-#define B2RAT_1 0x00000100 /* B2 Read Access Time = 1 cycle */
-#define B2RAT_2 0x00000200 /* B2 Read Access Time = 2 cycles */
-#define B2RAT_3 0x00000300 /* B2 Read Access Time = 3 cycles */
-#define B2RAT_4 0x00000400 /* B2 Read Access Time = 4 cycles */
-#define B2RAT_5 0x00000500 /* B2 Read Access Time = 5 cycles */
-#define B2RAT_6 0x00000600 /* B2 Read Access Time = 6 cycles */
-#define B2RAT_7 0x00000700 /* B2 Read Access Time = 7 cycles */
-#define B2RAT_8 0x00000800 /* B2 Read Access Time = 8 cycles */
-#define B2RAT_9 0x00000900 /* B2 Read Access Time = 9 cycles */
-#define B2RAT_10 0x00000A00 /* B2 Read Access Time = 10 cycles */
-#define B2RAT_11 0x00000B00 /* B2 Read Access Time = 11 cycles */
-#define B2RAT_12 0x00000C00 /* B2 Read Access Time = 12 cycles */
-#define B2RAT_13 0x00000D00 /* B2 Read Access Time = 13 cycles */
-#define B2RAT_14 0x00000E00 /* B2 Read Access Time = 14 cycles */
-#define B2RAT_15 0x00000F00 /* B2 Read Access Time = 15 cycles */
-#define B2WAT_1 0x00001000 /* B2 Write Access Time = 1 cycle */
-#define B2WAT_2 0x00002000 /* B2 Write Access Time = 2 cycles */
-#define B2WAT_3 0x00003000 /* B2 Write Access Time = 3 cycles */
-#define B2WAT_4 0x00004000 /* B2 Write Access Time = 4 cycles */
-#define B2WAT_5 0x00005000 /* B2 Write Access Time = 5 cycles */
-#define B2WAT_6 0x00006000 /* B2 Write Access Time = 6 cycles */
-#define B2WAT_7 0x00007000 /* B2 Write Access Time = 7 cycles */
-#define B2WAT_8 0x00008000 /* B2 Write Access Time = 8 cycles */
-#define B2WAT_9 0x00009000 /* B2 Write Access Time = 9 cycles */
-#define B2WAT_10 0x0000A000 /* B2 Write Access Time = 10 cycles */
-#define B2WAT_11 0x0000B000 /* B2 Write Access Time = 11 cycles */
-#define B2WAT_12 0x0000C000 /* B2 Write Access Time = 12 cycles */
-#define B2WAT_13 0x0000D000 /* B2 Write Access Time = 13 cycles */
-#define B2WAT_14 0x0000E000 /* B2 Write Access Time = 14 cycles */
-#define B2WAT_15 0x0000F000 /* B2 Write Access Time = 15 cycles */
-
-#define B3RDYEN 0x00010000 /* Bank 3 (B3) RDY Enable */
-#define B3RDYPOL 0x00020000 /* B3 RDY Active High */
-#define B3TT_1 0x00040000 /* B3 Transition Time (Read to Write) = 1 cycle */
-#define B3TT_2 0x00080000 /* B3 Transition Time (Read to Write) = 2 cycles */
-#define B3TT_3 0x000C0000 /* B3 Transition Time (Read to Write) = 3 cycles */
-#define B3TT_4 0x00000000 /* B3 Transition Time (Read to Write) = 4 cycles */
-#define B3ST_1 0x00100000 /* B3 Setup Time (AOE to Read/Write) = 1 cycle */
-#define B3ST_2 0x00200000 /* B3 Setup Time (AOE to Read/Write) = 2 cycles */
-#define B3ST_3 0x00300000 /* B3 Setup Time (AOE to Read/Write) = 3 cycles */
-#define B3ST_4 0x00000000 /* B3 Setup Time (AOE to Read/Write) = 4 cycles */
-#define B3HT_1 0x00400000 /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle */
-#define B3HT_2 0x00800000 /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles */
-#define B3HT_3 0x00C00000 /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles */
-#define B3HT_0 0x00000000 /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles */
-#define B3RAT_1 0x01000000 /* B3 Read Access Time = 1 cycle */
-#define B3RAT_2 0x02000000 /* B3 Read Access Time = 2 cycles */
-#define B3RAT_3 0x03000000 /* B3 Read Access Time = 3 cycles */
-#define B3RAT_4 0x04000000 /* B3 Read Access Time = 4 cycles */
-#define B3RAT_5 0x05000000 /* B3 Read Access Time = 5 cycles */
-#define B3RAT_6 0x06000000 /* B3 Read Access Time = 6 cycles */
-#define B3RAT_7 0x07000000 /* B3 Read Access Time = 7 cycles */
-#define B3RAT_8 0x08000000 /* B3 Read Access Time = 8 cycles */
-#define B3RAT_9 0x09000000 /* B3 Read Access Time = 9 cycles */
-#define B3RAT_10 0x0A000000 /* B3 Read Access Time = 10 cycles */
-#define B3RAT_11 0x0B000000 /* B3 Read Access Time = 11 cycles */
-#define B3RAT_12 0x0C000000 /* B3 Read Access Time = 12 cycles */
-#define B3RAT_13 0x0D000000 /* B3 Read Access Time = 13 cycles */
-#define B3RAT_14 0x0E000000 /* B3 Read Access Time = 14 cycles */
-#define B3RAT_15 0x0F000000 /* B3 Read Access Time = 15 cycles */
-#define B3WAT_1 0x10000000 /* B3 Write Access Time = 1 cycle */
-#define B3WAT_2 0x20000000 /* B3 Write Access Time = 2 cycles */
-#define B3WAT_3 0x30000000 /* B3 Write Access Time = 3 cycles */
-#define B3WAT_4 0x40000000 /* B3 Write Access Time = 4 cycles */
-#define B3WAT_5 0x50000000 /* B3 Write Access Time = 5 cycles */
-#define B3WAT_6 0x60000000 /* B3 Write Access Time = 6 cycles */
-#define B3WAT_7 0x70000000 /* B3 Write Access Time = 7 cycles */
-#define B3WAT_8 0x80000000 /* B3 Write Access Time = 8 cycles */
-#define B3WAT_9 0x90000000 /* B3 Write Access Time = 9 cycles */
-#define B3WAT_10 0xA0000000 /* B3 Write Access Time = 10 cycles */
-#define B3WAT_11 0xB0000000 /* B3 Write Access Time = 11 cycles */
-#define B3WAT_12 0xC0000000 /* B3 Write Access Time = 12 cycles */
-#define B3WAT_13 0xD0000000 /* B3 Write Access Time = 13 cycles */
-#define B3WAT_14 0xE0000000 /* B3 Write Access Time = 14 cycles */
-#define B3WAT_15 0xF0000000 /* B3 Write Access Time = 15 cycles */
-
-
-/* ********************** SDRAM CONTROLLER MASKS **********************************************/
-/* EBIU_SDGCTL Masks */
-#define SCTLE 0x00000001 /* Enable SDRAM Signals */
-#define CL_2 0x00000008 /* SDRAM CAS Latency = 2 cycles */
-#define CL_3 0x0000000C /* SDRAM CAS Latency = 3 cycles */
-#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
-#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
-#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
-#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
-#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
-#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
-#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
-#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
-#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
-#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
-#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
-#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
-#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
-#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
-#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
-#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
-#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
-#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
-#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
-#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
-#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
-#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
-#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
-#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
-#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
-#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
-#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
-#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
-#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
-#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
-#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
-#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
-#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
-#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
-#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
-#define PUPSD 0x00200000 /* Power-Up Start Delay (15 SCLK Cycles Delay) */
-#define PSM 0x00400000 /* Power-Up Sequence (Mode Register Before/After* Refresh) */
-#define PSS 0x00800000 /* Enable Power-Up Sequence on Next SDRAM Access */
-#define SRFS 0x01000000 /* Enable SDRAM Self-Refresh Mode */
-#define EBUFE 0x02000000 /* Enable External Buffering Timing */
-#define FBBRW 0x04000000 /* Enable Fast Back-To-Back Read To Write */
-#define EMREN 0x10000000 /* Extended Mode Register Enable */
-#define TCSR 0x20000000 /* Temp-Compensated Self-Refresh Value (85/45* Deg C) */
-#define CDDBG 0x40000000 /* Tristate SDRAM Controls During Bus Grant */
-
-/* EBIU_SDBCTL Masks */
-#define EBE 0x0001 /* Enable SDRAM External Bank */
-#define EBSZ_16 0x0000 /* SDRAM External Bank Size = 16MB */
-#define EBSZ_32 0x0002 /* SDRAM External Bank Size = 32MB */
-#define EBSZ_64 0x0004 /* SDRAM External Bank Size = 64MB */
-#define EBSZ_128 0x0006 /* SDRAM External Bank Size = 128MB */
-#define EBSZ_256 0x0008 /* SDRAM External Bank Size = 256MB */
-#define EBSZ_512 0x000A /* SDRAM External Bank Size = 512MB */
-#define EBCAW_8 0x0000 /* SDRAM External Bank Column Address Width = 8 Bits */
-#define EBCAW_9 0x0010 /* SDRAM External Bank Column Address Width = 9 Bits */
-#define EBCAW_10 0x0020 /* SDRAM External Bank Column Address Width = 10 Bits */
-#define EBCAW_11 0x0030 /* SDRAM External Bank Column Address Width = 11 Bits */
-
-/* EBIU_SDSTAT Masks */
-#define SDCI 0x0001 /* SDRAM Controller Idle */
-#define SDSRA 0x0002 /* SDRAM Self-Refresh Active */
-#define SDPUA 0x0004 /* SDRAM Power-Up Active */
-#define SDRS 0x0008 /* SDRAM Will Power-Up On Next Access */
-#define SDEASE 0x0010 /* SDRAM EAB Sticky Error Status */
-#define BGSTAT 0x0020 /* Bus Grant Status */
-
-
-/* ************************** DMA CONTROLLER MASKS ********************************/
-
-/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
-#define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */
-#define PMAP 0xF000 /* Peripheral Mapped To This Channel */
-#define PMAP_PPI 0x0000 /* PPI Port DMA */
-#define PMAP_EMACRX 0x1000 /* Ethernet Receive DMA */
-#define PMAP_EMACTX 0x2000 /* Ethernet Transmit DMA */
-#define PMAP_SPORT0RX 0x3000 /* SPORT0 Receive DMA */
-#define PMAP_SPORT0TX 0x4000 /* SPORT0 Transmit DMA */
-#define PMAP_SPORT1RX 0x5000 /* SPORT1 Receive DMA */
-#define PMAP_SPORT1TX 0x6000 /* SPORT1 Transmit DMA */
-#define PMAP_SPI 0x7000 /* SPI Port DMA */
-#define PMAP_UART0RX 0x8000 /* UART0 Port Receive DMA */
-#define PMAP_UART0TX 0x9000 /* UART0 Port Transmit DMA */
-#define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */
-#define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */
-
-/* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
-/* PPI_CONTROL Masks */
-#define PORT_EN 0x0001 /* PPI Port Enable */
-#define PORT_DIR 0x0002 /* PPI Port Direction */
-#define XFR_TYPE 0x000C /* PPI Transfer Type */
-#define PORT_CFG 0x0030 /* PPI Port Configuration */
-#define FLD_SEL 0x0040 /* PPI Active Field Select */
-#define PACK_EN 0x0080 /* PPI Packing Mode */
-#define DMA32 0x0100 /* PPI 32-bit DMA Enable */
-#define SKIP_EN 0x0200 /* PPI Skip Element Enable */
-#define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */
-#define DLEN_8 0x0000 /* Data Length = 8 Bits */
-#define DLEN_10 0x0800 /* Data Length = 10 Bits */
-#define DLEN_11 0x1000 /* Data Length = 11 Bits */
-#define DLEN_12 0x1800 /* Data Length = 12 Bits */
-#define DLEN_13 0x2000 /* Data Length = 13 Bits */
-#define DLEN_14 0x2800 /* Data Length = 14 Bits */
-#define DLEN_15 0x3000 /* Data Length = 15 Bits */
-#define DLEN_16 0x3800 /* Data Length = 16 Bits */
-#define DLENGTH 0x3800 /* PPI Data Length */
-#define POLC 0x4000 /* PPI Clock Polarity */
-#define POLS 0x8000 /* PPI Frame Sync Polarity */
-
-/* PPI_STATUS Masks */
-#define FLD 0x0400 /* Field Indicator */
-#define FT_ERR 0x0800 /* Frame Track Error */
-#define OVR 0x1000 /* FIFO Overflow Error */
-#define UNDR 0x2000 /* FIFO Underrun Error */
-#define ERR_DET 0x4000 /* Error Detected Indicator */
-#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */
-
-
-/* Omit CAN masks from defBF534.h */
-
-/* ******************* PIN CONTROL REGISTER MASKS ************************/
-/* PORT_MUX Masks */
-#define PJSE 0x0001 /* Port J SPI/SPORT Enable */
-#define PJSE_SPORT 0x0000 /* Enable TFS0/DT0PRI */
-#define PJSE_SPI 0x0001 /* Enable SPI_SSEL3:2 */
-
-#define PJCE(x) (((x)&0x3)<<1) /* Port J CAN/SPI/SPORT Enable */
-#define PJCE_SPORT 0x0000 /* Enable DR0SEC/DT0SEC */
-#define PJCE_CAN 0x0002 /* Enable CAN RX/TX */
-#define PJCE_SPI 0x0004 /* Enable SPI_SSEL7 */
-
-#define PFDE 0x0008 /* Port F DMA Request Enable */
-#define PFDE_UART 0x0000 /* Enable UART0 RX/TX */
-#define PFDE_DMA 0x0008 /* Enable DMAR1:0 */
-
-#define PFTE 0x0010 /* Port F Timer Enable */
-#define PFTE_UART 0x0000 /* Enable UART1 RX/TX */
-#define PFTE_TIMER 0x0010 /* Enable TMR7:6 */
-
-#define PFS6E 0x0020 /* Port F SPI SSEL 6 Enable */
-#define PFS6E_TIMER 0x0000 /* Enable TMR5 */
-#define PFS6E_SPI 0x0020 /* Enable SPI_SSEL6 */
-
-#define PFS5E 0x0040 /* Port F SPI SSEL 5 Enable */
-#define PFS5E_TIMER 0x0000 /* Enable TMR4 */
-#define PFS5E_SPI 0x0040 /* Enable SPI_SSEL5 */
-
-#define PFS4E 0x0080 /* Port F SPI SSEL 4 Enable */
-#define PFS4E_TIMER 0x0000 /* Enable TMR3 */
-#define PFS4E_SPI 0x0080 /* Enable SPI_SSEL4 */
-
-#define PFFE 0x0100 /* Port F PPI Frame Sync Enable */
-#define PFFE_TIMER 0x0000 /* Enable TMR2 */
-#define PFFE_PPI 0x0100 /* Enable PPI FS3 */
-
-#define PGSE 0x0200 /* Port G SPORT1 Secondary Enable */
-#define PGSE_PPI 0x0000 /* Enable PPI D9:8 */
-#define PGSE_SPORT 0x0200 /* Enable DR1SEC/DT1SEC */
-
-#define PGRE 0x0400 /* Port G SPORT1 Receive Enable */
-#define PGRE_PPI 0x0000 /* Enable PPI D12:10 */
-#define PGRE_SPORT 0x0400 /* Enable DR1PRI/RFS1/RSCLK1 */
-
-#define PGTE 0x0800 /* Port G SPORT1 Transmit Enable */
-#define PGTE_PPI 0x0000 /* Enable PPI D15:13 */
-#define PGTE_SPORT 0x0800 /* Enable DT1PRI/TFS1/TSCLK1 */
-
-/* entry addresses of the user-callable Boot ROM functions */
-
-#define _BOOTROM_RESET 0xEF000000
-#define _BOOTROM_FINAL_INIT 0xEF000002
-#define _BOOTROM_DO_MEMORY_DMA 0xEF000006
-#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008
-#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A
-#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C
-#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010
-#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012
-#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define PGDE_UART PFDE_UART
-#define PGDE_DMA PFDE_DMA
-#define CKELOW SCKELOW
-
-/* ==== end from defBF534.h ==== */
-
-/* HOST Port Registers */
-
-#define HOST_CONTROL 0xffc03400 /* HOST Control Register */
-#define HOST_STATUS 0xffc03404 /* HOST Status Register */
-#define HOST_TIMEOUT 0xffc03408 /* HOST Acknowledge Mode Timeout Register */
-
-/* Counter Registers */
-
-#define CNT_CONFIG 0xffc03500 /* Configuration Register */
-#define CNT_IMASK 0xffc03504 /* Interrupt Mask Register */
-#define CNT_STATUS 0xffc03508 /* Status Register */
-#define CNT_COMMAND 0xffc0350c /* Command Register */
-#define CNT_DEBOUNCE 0xffc03510 /* Debounce Register */
-#define CNT_COUNTER 0xffc03514 /* Counter Register */
-#define CNT_MAX 0xffc03518 /* Maximal Count Register */
-#define CNT_MIN 0xffc0351c /* Minimal Count Register */
-
-/* OTP/FUSE Registers */
-
-#define OTP_CONTROL 0xffc03600 /* OTP/Fuse Control Register */
-#define OTP_BEN 0xffc03604 /* OTP/Fuse Byte Enable */
-#define OTP_STATUS 0xffc03608 /* OTP/Fuse Status */
-#define OTP_TIMING 0xffc0360c /* OTP/Fuse Access Timing */
-
-/* Security Registers */
-
-#define SECURE_SYSSWT 0xffc03620 /* Secure System Switches */
-#define SECURE_CONTROL 0xffc03624 /* Secure Control */
-#define SECURE_STATUS 0xffc03628 /* Secure Status */
-
-/* OTP Read/Write Data Buffer Registers */
-
-#define OTP_DATA0 0xffc03680 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA1 0xffc03684 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA2 0xffc03688 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA3 0xffc0368c /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-
-/* NFC Registers */
-
-#define NFC_CTL 0xffc03700 /* NAND Control Register */
-#define NFC_STAT 0xffc03704 /* NAND Status Register */
-#define NFC_IRQSTAT 0xffc03708 /* NAND Interrupt Status Register */
-#define NFC_IRQMASK 0xffc0370c /* NAND Interrupt Mask Register */
-#define NFC_ECC0 0xffc03710 /* NAND ECC Register 0 */
-#define NFC_ECC1 0xffc03714 /* NAND ECC Register 1 */
-#define NFC_ECC2 0xffc03718 /* NAND ECC Register 2 */
-#define NFC_ECC3 0xffc0371c /* NAND ECC Register 3 */
-#define NFC_COUNT 0xffc03720 /* NAND ECC Count Register */
-#define NFC_RST 0xffc03724 /* NAND ECC Reset Register */
-#define NFC_PGCTL 0xffc03728 /* NAND Page Control Register */
-#define NFC_READ 0xffc0372c /* NAND Read Data Register */
-#define NFC_ADDR 0xffc03740 /* NAND Address Register */
-#define NFC_CMD 0xffc03744 /* NAND Command Register */
-#define NFC_DATA_WR 0xffc03748 /* NAND Data Write Register */
-#define NFC_DATA_RD 0xffc0374c /* NAND Data Read Register */
-
-/* ********************************************************** */
-/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
-/* and MULTI BIT READ MACROS */
-/* ********************************************************** */
-
-/* Bit masks for HOST_CONTROL */
-
-#define HOST_CNTR_HOST_EN 0x1 /* Host Enable */
-#define HOST_CNTR_nHOST_EN 0x0
-#define HOST_CNTR_HOST_END 0x2 /* Host Endianess */
-#define HOST_CNTR_nHOST_END 0x0
-#define HOST_CNTR_DATA_SIZE 0x4 /* Data Size */
-#define HOST_CNTR_nDATA_SIZE 0x0
-#define HOST_CNTR_HOST_RST 0x8 /* Host Reset */
-#define HOST_CNTR_nHOST_RST 0x0
-#define HOST_CNTR_HRDY_OVR 0x20 /* Host Ready Override */
-#define HOST_CNTR_nHRDY_OVR 0x0
-#define HOST_CNTR_INT_MODE 0x40 /* Interrupt Mode */
-#define HOST_CNTR_nINT_MODE 0x0
-#define HOST_CNTR_BT_EN 0x80 /* Bus Timeout Enable */
-#define HOST_CNTR_ nBT_EN 0x0
-#define HOST_CNTR_EHW 0x100 /* Enable Host Write */
-#define HOST_CNTR_nEHW 0x0
-#define HOST_CNTR_EHR 0x200 /* Enable Host Read */
-#define HOST_CNTR_nEHR 0x0
-#define HOST_CNTR_BDR 0x400 /* Burst DMA Requests */
-#define HOST_CNTR_nBDR 0x0
-
-/* Bit masks for HOST_STATUS */
-
-#define HOST_STAT_READY 0x1 /* DMA Ready */
-#define HOST_STAT_nREADY 0x0
-#define HOST_STAT_FIFOFULL 0x2 /* FIFO Full */
-#define HOST_STAT_nFIFOFULL 0x0
-#define HOST_STAT_FIFOEMPTY 0x4 /* FIFO Empty */
-#define HOST_STAT_nFIFOEMPTY 0x0
-#define HOST_STAT_COMPLETE 0x8 /* DMA Complete */
-#define HOST_STAT_nCOMPLETE 0x0
-#define HOST_STAT_HSHK 0x10 /* Host Handshake */
-#define HOST_STAT_nHSHK 0x0
-#define HOST_STAT_TIMEOUT 0x20 /* Host Timeout */
-#define HOST_STAT_nTIMEOUT 0x0
-#define HOST_STAT_HIRQ 0x40 /* Host Interrupt Request */
-#define HOST_STAT_nHIRQ 0x0
-#define HOST_STAT_ALLOW_CNFG 0x80 /* Allow New Configuration */
-#define HOST_STAT_nALLOW_CNFG 0x0
-#define HOST_STAT_DMA_DIR 0x100 /* DMA Direction */
-#define HOST_STAT_nDMA_DIR 0x0
-#define HOST_STAT_BTE 0x200 /* Bus Timeout Enabled */
-#define HOST_STAT_nBTE 0x0
-#define HOST_STAT_HOSTRD_DONE 0x8000 /* Host Read Completion Interrupt */
-#define HOST_STAT_nHOSTRD_DONE 0x0
-
-/* Bit masks for HOST_TIMEOUT */
-
-#define HOST_COUNT_TIMEOUT 0x7ff /* Host Timeout count */
-
-/* Bit masks for SECURE_SYSSWT */
-
-#define EMUDABL 0x1 /* Emulation Disable. */
-#define nEMUDABL 0x0
-#define RSTDABL 0x2 /* Reset Disable */
-#define nRSTDABL 0x0
-#define L1IDABL 0x1c /* L1 Instruction Memory Disable. */
-#define L1DADABL 0xe0 /* L1 Data Bank A Memory Disable. */
-#define L1DBDABL 0x700 /* L1 Data Bank B Memory Disable. */
-#define DMA0OVR 0x800 /* DMA0 Memory Access Override */
-#define nDMA0OVR 0x0
-#define DMA1OVR 0x1000 /* DMA1 Memory Access Override */
-#define nDMA1OVR 0x0
-#define EMUOVR 0x4000 /* Emulation Override */
-#define nEMUOVR 0x0
-#define OTPSEN 0x8000 /* OTP Secrets Enable. */
-#define nOTPSEN 0x0
-#define L2DABL 0x70000 /* L2 Memory Disable. */
-
-/* Bit masks for SECURE_CONTROL */
-
-#define SECURE0 0x1 /* SECURE 0 */
-#define nSECURE0 0x0
-#define SECURE1 0x2 /* SECURE 1 */
-#define nSECURE1 0x0
-#define SECURE2 0x4 /* SECURE 2 */
-#define nSECURE2 0x0
-#define SECURE3 0x8 /* SECURE 3 */
-#define nSECURE3 0x0
-
-/* Bit masks for SECURE_STATUS */
-
-#define SECMODE 0x3 /* Secured Mode Control State */
-#define NMI 0x4 /* Non Maskable Interrupt */
-#define nNMI 0x0
-#define AFVALID 0x8 /* Authentication Firmware Valid */
-#define nAFVALID 0x0
-#define AFEXIT 0x10 /* Authentication Firmware Exit */
-#define nAFEXIT 0x0
-#define SECSTAT 0xe0 /* Secure Status */
-
-#endif /* _DEF_BF522_H */
+++ /dev/null
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF525_H
-#define _DEF_BF525_H
-
-/* BF525 is BF522 + USB */
-#include "defBF522.h"
-
-/* USB Control Registers */
-
-#define USB_FADDR 0xffc03800 /* Function address register */
-#define USB_POWER 0xffc03804 /* Power management register */
-#define USB_INTRTX 0xffc03808 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
-#define USB_INTRRX 0xffc0380c /* Interrupt register for Rx endpoints 1 to 7 */
-#define USB_INTRTXE 0xffc03810 /* Interrupt enable register for IntrTx */
-#define USB_INTRRXE 0xffc03814 /* Interrupt enable register for IntrRx */
-#define USB_INTRUSB 0xffc03818 /* Interrupt register for common USB interrupts */
-#define USB_INTRUSBE 0xffc0381c /* Interrupt enable register for IntrUSB */
-#define USB_FRAME 0xffc03820 /* USB frame number */
-#define USB_INDEX 0xffc03824 /* Index register for selecting the indexed endpoint registers */
-#define USB_TESTMODE 0xffc03828 /* Enabled USB 20 test modes */
-#define USB_GLOBINTR 0xffc0382c /* Global Interrupt Mask register and Wakeup Exception Interrupt */
-#define USB_GLOBAL_CTL 0xffc03830 /* Global Clock Control for the core */
-
-/* USB Packet Control Registers */
-
-#define USB_TX_MAX_PACKET 0xffc03840 /* Maximum packet size for Host Tx endpoint */
-#define USB_CSR0 0xffc03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define USB_TXCSR 0xffc03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define USB_RX_MAX_PACKET 0xffc03848 /* Maximum packet size for Host Rx endpoint */
-#define USB_RXCSR 0xffc0384c /* Control Status register for Host Rx endpoint */
-#define USB_COUNT0 0xffc03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define USB_RXCOUNT 0xffc03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define USB_TXTYPE 0xffc03854 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
-#define USB_NAKLIMIT0 0xffc03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define USB_TXINTERVAL 0xffc03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define USB_RXTYPE 0xffc0385c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
-#define USB_RXINTERVAL 0xffc03860 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
-#define USB_TXCOUNT 0xffc03868 /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* USB Endpoint FIFO Registers */
-
-#define USB_EP0_FIFO 0xffc03880 /* Endpoint 0 FIFO */
-#define USB_EP1_FIFO 0xffc03888 /* Endpoint 1 FIFO */
-#define USB_EP2_FIFO 0xffc03890 /* Endpoint 2 FIFO */
-#define USB_EP3_FIFO 0xffc03898 /* Endpoint 3 FIFO */
-#define USB_EP4_FIFO 0xffc038a0 /* Endpoint 4 FIFO */
-#define USB_EP5_FIFO 0xffc038a8 /* Endpoint 5 FIFO */
-#define USB_EP6_FIFO 0xffc038b0 /* Endpoint 6 FIFO */
-#define USB_EP7_FIFO 0xffc038b8 /* Endpoint 7 FIFO */
-
-/* USB OTG Control Registers */
-
-#define USB_OTG_DEV_CTL 0xffc03900 /* OTG Device Control Register */
-#define USB_OTG_VBUS_IRQ 0xffc03904 /* OTG VBUS Control Interrupts */
-#define USB_OTG_VBUS_MASK 0xffc03908 /* VBUS Control Interrupt Enable */
-
-/* USB Phy Control Registers */
-
-#define USB_LINKINFO 0xffc03948 /* Enables programming of some PHY-side delays */
-#define USB_VPLEN 0xffc0394c /* Determines duration of VBUS pulse for VBUS charging */
-#define USB_HS_EOF1 0xffc03950 /* Time buffer for High-Speed transactions */
-#define USB_FS_EOF1 0xffc03954 /* Time buffer for Full-Speed transactions */
-#define USB_LS_EOF1 0xffc03958 /* Time buffer for Low-Speed transactions */
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define USB_APHY_CNTRL 0xffc039e0 /* Register that increases visibility of Analog PHY */
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define USB_APHY_CALIB 0xffc039e4 /* Register used to set some calibration values */
-
-#define USB_APHY_CNTRL2 0xffc039e8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
-
-#define USB_PLLOSC_CTRL 0xffc039f0 /* Used to program different parameters for USB PLL and Oscillator */
-#define USB_SRP_CLKDIV 0xffc039f4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
-
-/* USB Endpoint 0 Control Registers */
-
-#define USB_EP_NI0_TXMAXP 0xffc03a00 /* Maximum packet size for Host Tx endpoint0 */
-#define USB_EP_NI0_TXCSR 0xffc03a04 /* Control Status register for endpoint 0 */
-#define USB_EP_NI0_RXMAXP 0xffc03a08 /* Maximum packet size for Host Rx endpoint0 */
-#define USB_EP_NI0_RXCSR 0xffc03a0c /* Control Status register for Host Rx endpoint0 */
-#define USB_EP_NI0_RXCOUNT 0xffc03a10 /* Number of bytes received in endpoint 0 FIFO */
-#define USB_EP_NI0_TXTYPE 0xffc03a14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
-#define USB_EP_NI0_TXINTERVAL 0xffc03a18 /* Sets the NAK response timeout on Endpoint 0 */
-#define USB_EP_NI0_RXTYPE 0xffc03a1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
-#define USB_EP_NI0_RXINTERVAL 0xffc03a20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
-#define USB_EP_NI0_TXCOUNT 0xffc03a28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
-
-/* USB Endpoint 1 Control Registers */
-
-#define USB_EP_NI1_TXMAXP 0xffc03a40 /* Maximum packet size for Host Tx endpoint1 */
-#define USB_EP_NI1_TXCSR 0xffc03a44 /* Control Status register for endpoint1 */
-#define USB_EP_NI1_RXMAXP 0xffc03a48 /* Maximum packet size for Host Rx endpoint1 */
-#define USB_EP_NI1_RXCSR 0xffc03a4c /* Control Status register for Host Rx endpoint1 */
-#define USB_EP_NI1_RXCOUNT 0xffc03a50 /* Number of bytes received in endpoint1 FIFO */
-#define USB_EP_NI1_TXTYPE 0xffc03a54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
-#define USB_EP_NI1_TXINTERVAL 0xffc03a58 /* Sets the NAK response timeout on Endpoint1 */
-#define USB_EP_NI1_RXTYPE 0xffc03a5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
-#define USB_EP_NI1_RXINTERVAL 0xffc03a60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
-#define USB_EP_NI1_TXCOUNT 0xffc03a68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
-
-/* USB Endpoint 2 Control Registers */
-
-#define USB_EP_NI2_TXMAXP 0xffc03a80 /* Maximum packet size for Host Tx endpoint2 */
-#define USB_EP_NI2_TXCSR 0xffc03a84 /* Control Status register for endpoint2 */
-#define USB_EP_NI2_RXMAXP 0xffc03a88 /* Maximum packet size for Host Rx endpoint2 */
-#define USB_EP_NI2_RXCSR 0xffc03a8c /* Control Status register for Host Rx endpoint2 */
-#define USB_EP_NI2_RXCOUNT 0xffc03a90 /* Number of bytes received in endpoint2 FIFO */
-#define USB_EP_NI2_TXTYPE 0xffc03a94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
-#define USB_EP_NI2_TXINTERVAL 0xffc03a98 /* Sets the NAK response timeout on Endpoint2 */
-#define USB_EP_NI2_RXTYPE 0xffc03a9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
-#define USB_EP_NI2_RXINTERVAL 0xffc03aa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
-#define USB_EP_NI2_TXCOUNT 0xffc03aa8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
-
-/* USB Endpoint 3 Control Registers */
-
-#define USB_EP_NI3_TXMAXP 0xffc03ac0 /* Maximum packet size for Host Tx endpoint3 */
-#define USB_EP_NI3_TXCSR 0xffc03ac4 /* Control Status register for endpoint3 */
-#define USB_EP_NI3_RXMAXP 0xffc03ac8 /* Maximum packet size for Host Rx endpoint3 */
-#define USB_EP_NI3_RXCSR 0xffc03acc /* Control Status register for Host Rx endpoint3 */
-#define USB_EP_NI3_RXCOUNT 0xffc03ad0 /* Number of bytes received in endpoint3 FIFO */
-#define USB_EP_NI3_TXTYPE 0xffc03ad4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
-#define USB_EP_NI3_TXINTERVAL 0xffc03ad8 /* Sets the NAK response timeout on Endpoint3 */
-#define USB_EP_NI3_RXTYPE 0xffc03adc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
-#define USB_EP_NI3_RXINTERVAL 0xffc03ae0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
-#define USB_EP_NI3_TXCOUNT 0xffc03ae8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
-
-/* USB Endpoint 4 Control Registers */
-
-#define USB_EP_NI4_TXMAXP 0xffc03b00 /* Maximum packet size for Host Tx endpoint4 */
-#define USB_EP_NI4_TXCSR 0xffc03b04 /* Control Status register for endpoint4 */
-#define USB_EP_NI4_RXMAXP 0xffc03b08 /* Maximum packet size for Host Rx endpoint4 */
-#define USB_EP_NI4_RXCSR 0xffc03b0c /* Control Status register for Host Rx endpoint4 */
-#define USB_EP_NI4_RXCOUNT 0xffc03b10 /* Number of bytes received in endpoint4 FIFO */
-#define USB_EP_NI4_TXTYPE 0xffc03b14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
-#define USB_EP_NI4_TXINTERVAL 0xffc03b18 /* Sets the NAK response timeout on Endpoint4 */
-#define USB_EP_NI4_RXTYPE 0xffc03b1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
-#define USB_EP_NI4_RXINTERVAL 0xffc03b20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
-#define USB_EP_NI4_TXCOUNT 0xffc03b28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
-
-/* USB Endpoint 5 Control Registers */
-
-#define USB_EP_NI5_TXMAXP 0xffc03b40 /* Maximum packet size for Host Tx endpoint5 */
-#define USB_EP_NI5_TXCSR 0xffc03b44 /* Control Status register for endpoint5 */
-#define USB_EP_NI5_RXMAXP 0xffc03b48 /* Maximum packet size for Host Rx endpoint5 */
-#define USB_EP_NI5_RXCSR 0xffc03b4c /* Control Status register for Host Rx endpoint5 */
-#define USB_EP_NI5_RXCOUNT 0xffc03b50 /* Number of bytes received in endpoint5 FIFO */
-#define USB_EP_NI5_TXTYPE 0xffc03b54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
-#define USB_EP_NI5_TXINTERVAL 0xffc03b58 /* Sets the NAK response timeout on Endpoint5 */
-#define USB_EP_NI5_RXTYPE 0xffc03b5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
-#define USB_EP_NI5_RXINTERVAL 0xffc03b60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
-#define USB_EP_NI5_TXCOUNT 0xffc03b68 /* Number of bytes to be written to the endpoint5 Tx FIFO */
-
-/* USB Endpoint 6 Control Registers */
-
-#define USB_EP_NI6_TXMAXP 0xffc03b80 /* Maximum packet size for Host Tx endpoint6 */
-#define USB_EP_NI6_TXCSR 0xffc03b84 /* Control Status register for endpoint6 */
-#define USB_EP_NI6_RXMAXP 0xffc03b88 /* Maximum packet size for Host Rx endpoint6 */
-#define USB_EP_NI6_RXCSR 0xffc03b8c /* Control Status register for Host Rx endpoint6 */
-#define USB_EP_NI6_RXCOUNT 0xffc03b90 /* Number of bytes received in endpoint6 FIFO */
-#define USB_EP_NI6_TXTYPE 0xffc03b94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
-#define USB_EP_NI6_TXINTERVAL 0xffc03b98 /* Sets the NAK response timeout on Endpoint6 */
-#define USB_EP_NI6_RXTYPE 0xffc03b9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
-#define USB_EP_NI6_RXINTERVAL 0xffc03ba0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
-#define USB_EP_NI6_TXCOUNT 0xffc03ba8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
-
-/* USB Endpoint 7 Control Registers */
-
-#define USB_EP_NI7_TXMAXP 0xffc03bc0 /* Maximum packet size for Host Tx endpoint7 */
-#define USB_EP_NI7_TXCSR 0xffc03bc4 /* Control Status register for endpoint7 */
-#define USB_EP_NI7_RXMAXP 0xffc03bc8 /* Maximum packet size for Host Rx endpoint7 */
-#define USB_EP_NI7_RXCSR 0xffc03bcc /* Control Status register for Host Rx endpoint7 */
-#define USB_EP_NI7_RXCOUNT 0xffc03bd0 /* Number of bytes received in endpoint7 FIFO */
-#define USB_EP_NI7_TXTYPE 0xffc03bd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
-#define USB_EP_NI7_TXINTERVAL 0xffc03bd8 /* Sets the NAK response timeout on Endpoint7 */
-#define USB_EP_NI7_RXTYPE 0xffc03bdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
-#define USB_EP_NI7_RXINTERVAL 0xffc03be0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
-#define USB_EP_NI7_TXCOUNT 0xffc03be8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
-
-#define USB_DMA_INTERRUPT 0xffc03c00 /* Indicates pending interrupts for the DMA channels */
-
-/* USB Channel 0 Config Registers */
-
-#define USB_DMA0CONTROL 0xffc03c04 /* DMA master channel 0 configuration */
-#define USB_DMA0ADDRLOW 0xffc03c08 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
-#define USB_DMA0ADDRHIGH 0xffc03c0c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
-#define USB_DMA0COUNTLOW 0xffc03c10 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define USB_DMA0COUNTHIGH 0xffc03c14 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
-
-/* USB Channel 1 Config Registers */
-
-#define USB_DMA1CONTROL 0xffc03c24 /* DMA master channel 1 configuration */
-#define USB_DMA1ADDRLOW 0xffc03c28 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
-#define USB_DMA1ADDRHIGH 0xffc03c2c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
-#define USB_DMA1COUNTLOW 0xffc03c30 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define USB_DMA1COUNTHIGH 0xffc03c34 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
-
-/* USB Channel 2 Config Registers */
-
-#define USB_DMA2CONTROL 0xffc03c44 /* DMA master channel 2 configuration */
-#define USB_DMA2ADDRLOW 0xffc03c48 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
-#define USB_DMA2ADDRHIGH 0xffc03c4c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
-#define USB_DMA2COUNTLOW 0xffc03c50 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define USB_DMA2COUNTHIGH 0xffc03c54 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
-
-/* USB Channel 3 Config Registers */
-
-#define USB_DMA3CONTROL 0xffc03c64 /* DMA master channel 3 configuration */
-#define USB_DMA3ADDRLOW 0xffc03c68 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
-#define USB_DMA3ADDRHIGH 0xffc03c6c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
-#define USB_DMA3COUNTLOW 0xffc03c70 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define USB_DMA3COUNTHIGH 0xffc03c74 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
-
-/* USB Channel 4 Config Registers */
-
-#define USB_DMA4CONTROL 0xffc03c84 /* DMA master channel 4 configuration */
-#define USB_DMA4ADDRLOW 0xffc03c88 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
-#define USB_DMA4ADDRHIGH 0xffc03c8c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
-#define USB_DMA4COUNTLOW 0xffc03c90 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define USB_DMA4COUNTHIGH 0xffc03c94 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
-
-/* USB Channel 5 Config Registers */
-
-#define USB_DMA5CONTROL 0xffc03ca4 /* DMA master channel 5 configuration */
-#define USB_DMA5ADDRLOW 0xffc03ca8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
-#define USB_DMA5ADDRHIGH 0xffc03cac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
-#define USB_DMA5COUNTLOW 0xffc03cb0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define USB_DMA5COUNTHIGH 0xffc03cb4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
-
-/* USB Channel 6 Config Registers */
-
-#define USB_DMA6CONTROL 0xffc03cc4 /* DMA master channel 6 configuration */
-#define USB_DMA6ADDRLOW 0xffc03cc8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
-#define USB_DMA6ADDRHIGH 0xffc03ccc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
-#define USB_DMA6COUNTLOW 0xffc03cd0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define USB_DMA6COUNTHIGH 0xffc03cd4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
-
-/* USB Channel 7 Config Registers */
-
-#define USB_DMA7CONTROL 0xffc03ce4 /* DMA master channel 7 configuration */
-#define USB_DMA7ADDRLOW 0xffc03ce8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
-#define USB_DMA7ADDRHIGH 0xffc03cec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
-#define USB_DMA7COUNTLOW 0xffc03cf0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
-#define USB_DMA7COUNTHIGH 0xffc03cf4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
-
-/* Bit masks for USB_FADDR */
-
-#define FUNCTION_ADDRESS 0x7f /* Function address */
-
-/* Bit masks for USB_POWER */
-
-#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
-#define nENABLE_SUSPENDM 0x0
-#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
-#define nSUSPEND_MODE 0x0
-#define RESUME_MODE 0x4 /* DMA Mode */
-#define nRESUME_MODE 0x0
-#define RESET 0x8 /* Reset indicator */
-#define nRESET 0x0
-#define HS_MODE 0x10 /* High Speed mode indicator */
-#define nHS_MODE 0x0
-#define HS_ENABLE 0x20 /* high Speed Enable */
-#define nHS_ENABLE 0x0
-#define SOFT_CONN 0x40 /* Soft connect */
-#define nSOFT_CONN 0x0
-#define ISO_UPDATE 0x80 /* Isochronous update */
-#define nISO_UPDATE 0x0
-
-/* Bit masks for USB_INTRTX */
-
-#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
-#define nEP0_TX 0x0
-#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
-#define nEP1_TX 0x0
-#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
-#define nEP2_TX 0x0
-#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
-#define nEP3_TX 0x0
-#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
-#define nEP4_TX 0x0
-#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
-#define nEP5_TX 0x0
-#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
-#define nEP6_TX 0x0
-#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
-#define nEP7_TX 0x0
-
-/* Bit masks for USB_INTRRX */
-
-#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
-#define nEP1_RX 0x0
-#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
-#define nEP2_RX 0x0
-#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
-#define nEP3_RX 0x0
-#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
-#define nEP4_RX 0x0
-#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
-#define nEP5_RX 0x0
-#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
-#define nEP6_RX 0x0
-#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
-#define nEP7_RX 0x0
-
-/* Bit masks for USB_INTRTXE */
-
-#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
-#define nEP0_TX_E 0x0
-#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
-#define nEP1_TX_E 0x0
-#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
-#define nEP2_TX_E 0x0
-#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
-#define nEP3_TX_E 0x0
-#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
-#define nEP4_TX_E 0x0
-#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
-#define nEP5_TX_E 0x0
-#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
-#define nEP6_TX_E 0x0
-#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
-#define nEP7_TX_E 0x0
-
-/* Bit masks for USB_INTRRXE */
-
-#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
-#define nEP1_RX_E 0x0
-#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
-#define nEP2_RX_E 0x0
-#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
-#define nEP3_RX_E 0x0
-#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
-#define nEP4_RX_E 0x0
-#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
-#define nEP5_RX_E 0x0
-#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
-#define nEP6_RX_E 0x0
-#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
-#define nEP7_RX_E 0x0
-
-/* Bit masks for USB_INTRUSB */
-
-#define SUSPEND_B 0x1 /* Suspend indicator */
-#define nSUSPEND_B 0x0
-#define RESUME_B 0x2 /* Resume indicator */
-#define nRESUME_B 0x0
-#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
-#define nRESET_OR_BABLE_B 0x0
-#define SOF_B 0x8 /* Start of frame */
-#define nSOF_B 0x0
-#define CONN_B 0x10 /* Connection indicator */
-#define nCONN_B 0x0
-#define DISCON_B 0x20 /* Disconnect indicator */
-#define nDISCON_B 0x0
-#define SESSION_REQ_B 0x40 /* Session Request */
-#define nSESSION_REQ_B 0x0
-#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
-#define nVBUS_ERROR_B 0x0
-
-/* Bit masks for USB_INTRUSBE */
-
-#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
-#define nSUSPEND_BE 0x0
-#define RESUME_BE 0x2 /* Resume indicator int enable */
-#define nRESUME_BE 0x0
-#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
-#define nRESET_OR_BABLE_BE 0x0
-#define SOF_BE 0x8 /* Start of frame int enable */
-#define nSOF_BE 0x0
-#define CONN_BE 0x10 /* Connection indicator int enable */
-#define nCONN_BE 0x0
-#define DISCON_BE 0x20 /* Disconnect indicator int enable */
-#define nDISCON_BE 0x0
-#define SESSION_REQ_BE 0x40 /* Session Request int enable */
-#define nSESSION_REQ_BE 0x0
-#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
-#define nVBUS_ERROR_BE 0x0
-
-/* Bit masks for USB_FRAME */
-
-#define FRAME_NUMBER 0x7ff /* Frame number */
-
-/* Bit masks for USB_INDEX */
-
-#define SELECTED_ENDPOINT 0xf /* selected endpoint */
-
-/* Bit masks for USB_GLOBAL_CTL */
-
-#define GLOBAL_ENA 0x1 /* enables USB module */
-#define nGLOBAL_ENA 0x0
-#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
-#define nEP1_TX_ENA 0x0
-#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
-#define nEP2_TX_ENA 0x0
-#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
-#define nEP3_TX_ENA 0x0
-#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
-#define nEP4_TX_ENA 0x0
-#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
-#define nEP5_TX_ENA 0x0
-#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
-#define nEP6_TX_ENA 0x0
-#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
-#define nEP7_TX_ENA 0x0
-#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
-#define nEP1_RX_ENA 0x0
-#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
-#define nEP2_RX_ENA 0x0
-#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
-#define nEP3_RX_ENA 0x0
-#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
-#define nEP4_RX_ENA 0x0
-#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
-#define nEP5_RX_ENA 0x0
-#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
-#define nEP6_RX_ENA 0x0
-#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
-#define nEP7_RX_ENA 0x0
-
-/* Bit masks for USB_OTG_DEV_CTL */
-
-#define SESSION 0x1 /* session indicator */
-#define nSESSION 0x0
-#define HOST_REQ 0x2 /* Host negotiation request */
-#define nHOST_REQ 0x0
-#define HOST_MODE 0x4 /* indicates USBDRC is a host */
-#define nHOST_MODE 0x0
-#define VBUS0 0x8 /* Vbus level indicator[0] */
-#define nVBUS0 0x0
-#define VBUS1 0x10 /* Vbus level indicator[1] */
-#define nVBUS1 0x0
-#define LSDEV 0x20 /* Low-speed indicator */
-#define nLSDEV 0x0
-#define FSDEV 0x40 /* Full or High-speed indicator */
-#define nFSDEV 0x0
-#define B_DEVICE 0x80 /* A' or 'B' device indicator */
-#define nB_DEVICE 0x0
-
-/* Bit masks for USB_OTG_VBUS_IRQ */
-
-#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
-#define nDRIVE_VBUS_ON 0x0
-#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
-#define nDRIVE_VBUS_OFF 0x0
-#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
-#define nCHRG_VBUS_START 0x0
-#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
-#define nCHRG_VBUS_END 0x0
-#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
-#define nDISCHRG_VBUS_START 0x0
-#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
-#define nDISCHRG_VBUS_END 0x0
-
-/* Bit masks for USB_OTG_VBUS_MASK */
-
-#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
-#define nDRIVE_VBUS_ON_ENA 0x0
-#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
-#define nDRIVE_VBUS_OFF_ENA 0x0
-#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
-#define nCHRG_VBUS_START_ENA 0x0
-#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
-#define nCHRG_VBUS_END_ENA 0x0
-#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
-#define nDISCHRG_VBUS_START_ENA 0x0
-#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
-#define nDISCHRG_VBUS_END_ENA 0x0
-
-/* Bit masks for USB_CSR0 */
-
-#define RXPKTRDY 0x1 /* data packet receive indicator */
-#define nRXPKTRDY 0x0
-#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
-#define nTXPKTRDY 0x0
-#define STALL_SENT 0x4 /* STALL handshake sent */
-#define nSTALL_SENT 0x0
-#define DATAEND 0x8 /* Data end indicator */
-#define nDATAEND 0x0
-#define SETUPEND 0x10 /* Setup end */
-#define nSETUPEND 0x0
-#define SENDSTALL 0x20 /* Send STALL handshake */
-#define nSENDSTALL 0x0
-#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
-#define nSERVICED_RXPKTRDY 0x0
-#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
-#define nSERVICED_SETUPEND 0x0
-#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
-#define nFLUSHFIFO 0x0
-#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
-#define nSTALL_RECEIVED_H 0x0
-#define SETUPPKT_H 0x8 /* send Setup token host mode */
-#define nSETUPPKT_H 0x0
-#define ERROR_H 0x10 /* timeout error indicator host mode */
-#define nERROR_H 0x0
-#define REQPKT_H 0x20 /* Request an IN transaction host mode */
-#define nREQPKT_H 0x0
-#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
-#define nSTATUSPKT_H 0x0
-#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
-#define nNAK_TIMEOUT_H 0x0
-
-/* Bit masks for USB_COUNT0 */
-
-#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */
-
-/* Bit masks for USB_NAKLIMIT0 */
-
-#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */
-
-/* Bit masks for USB_TX_MAX_PACKET */
-
-#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */
-
-/* Bit masks for USB_RX_MAX_PACKET */
-
-#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */
-
-/* Bit masks for USB_TXCSR */
-
-#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
-#define nTXPKTRDY_T 0x0
-#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
-#define nFIFO_NOT_EMPTY_T 0x0
-#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
-#define nUNDERRUN_T 0x0
-#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
-#define nFLUSHFIFO_T 0x0
-#define STALL_SEND_T 0x10 /* issue a Stall handshake */
-#define nSTALL_SEND_T 0x0
-#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
-#define nSTALL_SENT_T 0x0
-#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
-#define nCLEAR_DATATOGGLE_T 0x0
-#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
-#define nINCOMPTX_T 0x0
-#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
-#define nDMAREQMODE_T 0x0
-#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
-#define nFORCE_DATATOGGLE_T 0x0
-#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
-#define nDMAREQ_ENA_T 0x0
-#define ISO_T 0x4000 /* enable Isochronous transfers */
-#define nISO_T 0x0
-#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
-#define nAUTOSET_T 0x0
-#define ERROR_TH 0x4 /* error condition host mode */
-#define nERROR_TH 0x0
-#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
-#define nSTALL_RECEIVED_TH 0x0
-#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
-#define nNAK_TIMEOUT_TH 0x0
-
-/* Bit masks for USB_TXCOUNT */
-
-#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* Bit masks for USB_RXCSR */
-
-#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
-#define nRXPKTRDY_R 0x0
-#define FIFO_FULL_R 0x2 /* FIFO not empty */
-#define nFIFO_FULL_R 0x0
-#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
-#define nOVERRUN_R 0x0
-#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
-#define nDATAERROR_R 0x0
-#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
-#define nFLUSHFIFO_R 0x0
-#define STALL_SEND_R 0x20 /* issue a Stall handshake */
-#define nSTALL_SEND_R 0x0
-#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
-#define nSTALL_SENT_R 0x0
-#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
-#define nCLEAR_DATATOGGLE_R 0x0
-#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
-#define nINCOMPRX_R 0x0
-#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
-#define nDMAREQMODE_R 0x0
-#define DISNYET_R 0x1000 /* disable Nyet handshakes */
-#define nDISNYET_R 0x0
-#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
-#define nDMAREQ_ENA_R 0x0
-#define ISO_R 0x4000 /* enable Isochronous transfers */
-#define nISO_R 0x0
-#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
-#define nAUTOCLEAR_R 0x0
-#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
-#define nERROR_RH 0x0
-#define REQPKT_RH 0x20 /* request an IN transaction host mode */
-#define nREQPKT_RH 0x0
-#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
-#define nSTALL_RECEIVED_RH 0x0
-#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
-#define nINCOMPRX_RH 0x0
-#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
-#define nDMAREQMODE_RH 0x0
-#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
-#define nAUTOREQ_RH 0x0
-
-/* Bit masks for USB_RXCOUNT */
-
-#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */
-
-/* Bit masks for USB_TXTYPE */
-
-#define TARGET_EP_NO_T 0xf /* EP number */
-#define PROTOCOL_T 0xc /* transfer type */
-
-/* Bit masks for USB_TXINTERVAL */
-
-#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
-
-/* Bit masks for USB_RXTYPE */
-
-#define TARGET_EP_NO_R 0xf /* EP number */
-#define PROTOCOL_R 0xc /* transfer type */
-
-/* Bit masks for USB_RXINTERVAL */
-
-#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
-
-/* Bit masks for USB_DMA_INTERRUPT */
-
-#define DMA0_INT 0x1 /* DMA0 pending interrupt */
-#define nDMA0_INT 0x0
-#define DMA1_INT 0x2 /* DMA1 pending interrupt */
-#define nDMA1_INT 0x0
-#define DMA2_INT 0x4 /* DMA2 pending interrupt */
-#define nDMA2_INT 0x0
-#define DMA3_INT 0x8 /* DMA3 pending interrupt */
-#define nDMA3_INT 0x0
-#define DMA4_INT 0x10 /* DMA4 pending interrupt */
-#define nDMA4_INT 0x0
-#define DMA5_INT 0x20 /* DMA5 pending interrupt */
-#define nDMA5_INT 0x0
-#define DMA6_INT 0x40 /* DMA6 pending interrupt */
-#define nDMA6_INT 0x0
-#define DMA7_INT 0x80 /* DMA7 pending interrupt */
-#define nDMA7_INT 0x0
-
-/* Bit masks for USB_DMAxCONTROL */
-
-#define DMA_ENA 0x1 /* DMA enable */
-#define nDMA_ENA 0x0
-#define DIRECTION 0x2 /* direction of DMA transfer */
-#define nDIRECTION 0x0
-#define MODE 0x4 /* DMA Bus error */
-#define nMODE 0x0
-#define INT_ENA 0x8 /* Interrupt enable */
-#define nINT_ENA 0x0
-#define EPNUM 0xf0 /* EP number */
-#define BUSERROR 0x100 /* DMA Bus error */
-#define nBUSERROR 0x0
-
-/* Bit masks for USB_DMAxADDRHIGH */
-
-#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxADDRLOW */
-
-#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTHIGH */
-
-#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTLOW */
-
-#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
-
-#endif /* _DEF_BF525_H */
+++ /dev/null
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF527_H
-#define _DEF_BF527_H
-
-/* BF527 is BF525 + EMAC */
-#include "defBF525.h"
-
-/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
-
-#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */
-#define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */
-#define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */
-#define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */
-#define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */
-#define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */
-#define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */
-#define EMAC_FLC 0xFFC0301C /* Flow Control Register */
-#define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */
-#define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */
-#define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */
-#define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */
-#define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */
-#define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */
-#define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */
-#define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */
-#define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */
-#define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */
-#define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */
-
-#define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */
-#define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */
-#define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */
-#define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */
-#define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */
-#define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */
-#define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */
-#define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */
-
-#define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */
-#define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */
-#define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */
-#define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */
-#define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */
-
-#define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */
-#define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */
-#define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */
-#define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */
-#define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */
-#define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */
-#define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */
-#define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */
-#define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */
-#define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */
-#define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */
-#define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */
-#define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */
-#define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */
-#define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */
-#define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */
-#define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */
-#define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */
-#define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */
-#define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 < x < 128 */
-#define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
-#define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
-#define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
-#define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */
-
-#define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */
-#define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */
-#define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */
-#define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */
-#define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */
-#define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */
-#define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */
-#define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */
-#define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */
-#define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */
-#define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */
-#define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */
-#define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */
-#define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */
-#define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */
-#define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */
-#define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */
-#define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 < x < 128 */
-#define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
-#define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */
-#define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
-#define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */
-#define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */
-
-/* Listing for IEEE-Supported Count Registers */
-
-#define FramesReceivedOK EMAC_RXC_OK /* RX Frame Successful Count */
-#define FrameCheckSequenceErrors EMAC_RXC_FCS /* RX Frame FCS Failure Count */
-#define AlignmentErrors EMAC_RXC_ALIGN /* RX Alignment Error Count */
-#define OctetsReceivedOK EMAC_RXC_OCTET /* RX Octets Successfully Received Count */
-#define FramesLostDueToIntMACRcvError EMAC_RXC_DMAOVF /* Internal MAC Sublayer Error RX Frame Count */
-#define UnicastFramesReceivedOK EMAC_RXC_UNICST /* Unicast RX Frame Count */
-#define MulticastFramesReceivedOK EMAC_RXC_MULTI /* Multicast RX Frame Count */
-#define BroadcastFramesReceivedOK EMAC_RXC_BROAD /* Broadcast RX Frame Count */
-#define InRangeLengthErrors EMAC_RXC_LNERRI /* RX Frame In Range Error Count */
-#define OutOfRangeLengthField EMAC_RXC_LNERRO /* RX Frame Out Of Range Error Count */
-#define FrameTooLongErrors EMAC_RXC_LONG /* RX Frame Too Long Count */
-#define MACControlFramesReceived EMAC_RXC_MACCTL /* MAC Control RX Frame Count */
-#define UnsupportedOpcodesReceived EMAC_RXC_OPCODE /* Unsupported Op-Code RX Frame Count */
-#define PAUSEMACCtrlFramesReceived EMAC_RXC_PAUSE /* MAC Control Pause RX Frame Count */
-#define FramesReceivedAll EMAC_RXC_ALLFRM /* Overall RX Frame Count */
-#define OctetsReceivedAll EMAC_RXC_ALLOCT /* Overall RX Octet Count */
-#define TypedFramesReceived EMAC_RXC_TYPED /* Type/Length Consistent RX Frame Count */
-#define FramesLenLt64Received EMAC_RXC_SHORT /* RX Frame Fragment Count - Byte Count x < 64 */
-#define FramesLenEq64Received EMAC_RXC_EQ64 /* Good RX Frame Count - Byte Count x = 64 */
-#define FramesLen65_127Received EMAC_RXC_LT128 /* Good RX Frame Count - Byte Count 64 < x < 128 */
-#define FramesLen128_255Received EMAC_RXC_LT256 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
-#define FramesLen256_511Received EMAC_RXC_LT512 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
-#define FramesLen512_1023Received EMAC_RXC_LT1024 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
-#define FramesLen1024_MaxReceived EMAC_RXC_GE1024 /* Good RX Frame Count - Byte Count x >= 1024 */
-
-#define FramesTransmittedOK EMAC_TXC_OK /* TX Frame Successful Count */
-#define SingleCollisionFrames EMAC_TXC_1COL /* TX Frames Successful After Single Collision Count */
-#define MultipleCollisionFrames EMAC_TXC_GT1COL /* TX Frames Successful After Multiple Collisions Count */
-#define OctetsTransmittedOK EMAC_TXC_OCTET /* TX Octets Successfully Received Count */
-#define FramesWithDeferredXmissions EMAC_TXC_DEFER /* TX Frame Delayed Due To Busy Count */
-#define LateCollisions EMAC_TXC_LATECL /* Late TX Collisions Count */
-#define FramesAbortedDueToXSColls EMAC_TXC_XS_COL /* TX Frame Failed Due To Excessive Collisions Count */
-#define FramesLostDueToIntMacXmitError EMAC_TXC_DMAUND /* Internal MAC Sublayer Error TX Frame Count */
-#define CarrierSenseErrors EMAC_TXC_CRSERR /* Carrier Sense Deasserted During TX Frame Count */
-#define UnicastFramesXmittedOK EMAC_TXC_UNICST /* Unicast TX Frame Count */
-#define MulticastFramesXmittedOK EMAC_TXC_MULTI /* Multicast TX Frame Count */
-#define BroadcastFramesXmittedOK EMAC_TXC_BROAD /* Broadcast TX Frame Count */
-#define FramesWithExcessiveDeferral EMAC_TXC_XS_DFR /* TX Frames With Excessive Deferral Count */
-#define MACControlFramesTransmitted EMAC_TXC_MACCTL /* MAC Control TX Frame Count */
-#define FramesTransmittedAll EMAC_TXC_ALLFRM /* Overall TX Frame Count */
-#define OctetsTransmittedAll EMAC_TXC_ALLOCT /* Overall TX Octet Count */
-#define FramesLenEq64Transmitted EMAC_TXC_EQ64 /* Good TX Frame Count - Byte Count x = 64 */
-#define FramesLen65_127Transmitted EMAC_TXC_LT128 /* Good TX Frame Count - Byte Count 64 < x < 128 */
-#define FramesLen128_255Transmitted EMAC_TXC_LT256 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
-#define FramesLen256_511Transmitted EMAC_TXC_LT512 /* Good TX Frame Count - Byte Count 256 <= x < 512 */
-#define FramesLen512_1023Transmitted EMAC_TXC_LT1024 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
-#define FramesLen1024_MaxTransmitted EMAC_TXC_GE1024 /* Good TX Frame Count - Byte Count x >= 1024 */
-#define TxAbortedFrames EMAC_TXC_ABORT /* Total TX Frames Aborted Count */
-
-/***********************************************************************************
-** System MMR Register Bits And Macros
-**
-** Disclaimer: All macros are intended to make C and Assembly code more readable.
-** Use these macros carefully, as any that do left shifts for field
-** depositing will result in the lower order bits being destroyed. Any
-** macro that shifts left to properly position the bit-field should be
-** used as part of an OR to initialize a register and NOT as a dynamic
-** modifier UNLESS the lower order bits are saved and ORed back in when
-** the macro is used.
-*************************************************************************************/
-
-/************************ ETHERNET 10/100 CONTROLLER MASKS ************************/
-
-/* EMAC_OPMODE Masks */
-
-#define RE 0x00000001 /* Receiver Enable */
-#define ASTP 0x00000002 /* Enable Automatic Pad Stripping On RX Frames */
-#define HU 0x00000010 /* Hash Filter Unicast Address */
-#define HM 0x00000020 /* Hash Filter Multicast Address */
-#define PAM 0x00000040 /* Pass-All-Multicast Mode Enable */
-#define PR 0x00000080 /* Promiscuous Mode Enable */
-#define IFE 0x00000100 /* Inverse Filtering Enable */
-#define DBF 0x00000200 /* Disable Broadcast Frame Reception */
-#define PBF 0x00000400 /* Pass Bad Frames Enable */
-#define PSF 0x00000800 /* Pass Short Frames Enable */
-#define RAF 0x00001000 /* Receive-All Mode */
-#define TE 0x00010000 /* Transmitter Enable */
-#define DTXPAD 0x00020000 /* Disable Automatic TX Padding */
-#define DTXCRC 0x00040000 /* Disable Automatic TX CRC Generation */
-#define DC 0x00080000 /* Deferral Check */
-#define BOLMT 0x00300000 /* Back-Off Limit */
-#define BOLMT_10 0x00000000 /* 10-bit range */
-#define BOLMT_8 0x00100000 /* 8-bit range */
-#define BOLMT_4 0x00200000 /* 4-bit range */
-#define BOLMT_1 0x00300000 /* 1-bit range */
-#define DRTY 0x00400000 /* Disable TX Retry On Collision */
-#define LCTRE 0x00800000 /* Enable TX Retry On Late Collision */
-#define RMII 0x01000000 /* RMII/MII* Mode */
-#define RMII_10 0x02000000 /* Speed Select for RMII Port (10MBit/100MBit*) */
-#define FDMODE 0x04000000 /* Duplex Mode Enable (Full/Half*) */
-#define LB 0x08000000 /* Internal Loopback Enable */
-#define DRO 0x10000000 /* Disable Receive Own Frames (Half-Duplex Mode) */
-
-/* EMAC_STAADD Masks */
-
-#define STABUSY 0x00000001 /* Initiate Station Mgt Reg Access / STA Busy Stat */
-#define STAOP 0x00000002 /* Station Management Operation Code (Write/Read*) */
-#define STADISPRE 0x00000004 /* Disable Preamble Generation */
-#define STAIE 0x00000008 /* Station Mgt. Transfer Done Interrupt Enable */
-#define REGAD 0x000007C0 /* STA Register Address */
-#define PHYAD 0x0000F800 /* PHY Device Address */
-
-#define SET_REGAD(x) (((x)&0x1F)<< 6 ) /* Set STA Register Address */
-#define SET_PHYAD(x) (((x)&0x1F)<< 11 ) /* Set PHY Device Address */
-
-/* EMAC_STADAT Mask */
-
-#define STADATA 0x0000FFFF /* Station Management Data */
-
-/* EMAC_FLC Masks */
-
-#define FLCBUSY 0x00000001 /* Send Flow Ctrl Frame / Flow Ctrl Busy Status */
-#define FLCE 0x00000002 /* Flow Control Enable */
-#define PCF 0x00000004 /* Pass Control Frames */
-#define BKPRSEN 0x00000008 /* Enable Backpressure */
-#define FLCPAUSE 0xFFFF0000 /* Pause Time */
-
-#define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time */
-
-/* EMAC_WKUP_CTL Masks */
-
-#define CAPWKFRM 0x00000001 /* Capture Wake-Up Frames */
-#define MPKE 0x00000002 /* Magic Packet Enable */
-#define RWKE 0x00000004 /* Remote Wake-Up Frame Enable */
-#define GUWKE 0x00000008 /* Global Unicast Wake Enable */
-#define MPKS 0x00000020 /* Magic Packet Received Status */
-#define RWKS 0x00000F00 /* Wake-Up Frame Received Status, Filters 3:0 */
-
-/* EMAC_WKUP_FFCMD Masks */
-
-#define WF0_E 0x00000001 /* Enable Wake-Up Filter 0 */
-#define WF0_T 0x00000008 /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*) */
-#define WF1_E 0x00000100 /* Enable Wake-Up Filter 1 */
-#define WF1_T 0x00000800 /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*) */
-#define WF2_E 0x00010000 /* Enable Wake-Up Filter 2 */
-#define WF2_T 0x00080000 /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*) */
-#define WF3_E 0x01000000 /* Enable Wake-Up Filter 3 */
-#define WF3_T 0x08000000 /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*) */
-
-/* EMAC_WKUP_FFOFF Masks */
-
-#define WF0_OFF 0x000000FF /* Wake-Up Filter 0 Pattern Offset */
-#define WF1_OFF 0x0000FF00 /* Wake-Up Filter 1 Pattern Offset */
-#define WF2_OFF 0x00FF0000 /* Wake-Up Filter 2 Pattern Offset */
-#define WF3_OFF 0xFF000000 /* Wake-Up Filter 3 Pattern Offset */
-
-#define SET_WF0_OFF(x) (((x)&0xFF)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */
-#define SET_WF1_OFF(x) (((x)&0xFF)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */
-#define SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */
-#define SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */
-/* Set ALL Offsets */
-#define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3)))
-
-/* EMAC_WKUP_FFCRC0 Masks */
-
-#define WF0_CRC 0x0000FFFF /* Wake-Up Filter 0 Pattern CRC */
-#define WF1_CRC 0xFFFF0000 /* Wake-Up Filter 1 Pattern CRC */
-
-#define SET_WF0_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 0 Target CRC */
-#define SET_WF1_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 1 Target CRC */
-
-/* EMAC_WKUP_FFCRC1 Masks */
-
-#define WF2_CRC 0x0000FFFF /* Wake-Up Filter 2 Pattern CRC */
-#define WF3_CRC 0xFFFF0000 /* Wake-Up Filter 3 Pattern CRC */
-
-#define SET_WF2_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 2 Target CRC */
-#define SET_WF3_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 3 Target CRC */
-
-/* EMAC_SYSCTL Masks */
-
-#define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */
-#define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */
-#define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */
-#define TXDWA 0x00000010 /* Transmit Frame DMA Word Alignment (Odd/Even*) */
-#define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */
-
-#define SET_MDCDIV(x) (((x)&0x3F)<< 8) /* Set MDC Clock Divisor */
-
-/* EMAC_SYSTAT Masks */
-
-#define PHYINT 0x00000001 /* PHY_INT Interrupt Status */
-#define MMCINT 0x00000002 /* MMC Counter Interrupt Status */
-#define RXFSINT 0x00000004 /* RX Frame-Status Interrupt Status */
-#define TXFSINT 0x00000008 /* TX Frame-Status Interrupt Status */
-#define WAKEDET 0x00000010 /* Wake-Up Detected Status */
-#define RXDMAERR 0x00000020 /* RX DMA Direction Error Status */
-#define TXDMAERR 0x00000040 /* TX DMA Direction Error Status */
-#define STMDONE 0x00000080 /* Station Mgt. Transfer Done Interrupt Status */
-
-/* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */
-
-#define RX_FRLEN 0x000007FF /* Frame Length In Bytes */
-#define RX_COMP 0x00001000 /* RX Frame Complete */
-#define RX_OK 0x00002000 /* RX Frame Received With No Errors */
-#define RX_LONG 0x00004000 /* RX Frame Too Long Error */
-#define RX_ALIGN 0x00008000 /* RX Frame Alignment Error */
-#define RX_CRC 0x00010000 /* RX Frame CRC Error */
-#define RX_LEN 0x00020000 /* RX Frame Length Error */
-#define RX_FRAG 0x00040000 /* RX Frame Fragment Error */
-#define RX_ADDR 0x00080000 /* RX Frame Address Filter Failed Error */
-#define RX_DMAO 0x00100000 /* RX Frame DMA Overrun Error */
-#define RX_PHY 0x00200000 /* RX Frame PHY Error */
-#define RX_LATE 0x00400000 /* RX Frame Late Collision Error */
-#define RX_RANGE 0x00800000 /* RX Frame Length Field Out of Range Error */
-#define RX_MULTI 0x01000000 /* RX Multicast Frame Indicator */
-#define RX_BROAD 0x02000000 /* RX Broadcast Frame Indicator */
-#define RX_CTL 0x04000000 /* RX Control Frame Indicator */
-#define RX_UCTL 0x08000000 /* Unsupported RX Control Frame Indicator */
-#define RX_TYPE 0x10000000 /* RX Typed Frame Indicator */
-#define RX_VLAN1 0x20000000 /* RX VLAN1 Frame Indicator */
-#define RX_VLAN2 0x40000000 /* RX VLAN2 Frame Indicator */
-#define RX_ACCEPT 0x80000000 /* RX Frame Accepted Indicator */
-
-/* EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks */
-
-#define TX_COMP 0x00000001 /* TX Frame Complete */
-#define TX_OK 0x00000002 /* TX Frame Sent With No Errors */
-#define TX_ECOLL 0x00000004 /* TX Frame Excessive Collision Error */
-#define TX_LATE 0x00000008 /* TX Frame Late Collision Error */
-#define TX_DMAU 0x00000010 /* TX Frame DMA Underrun Error (STAT) */
-#define TX_MACE 0x00000010 /* Internal MAC Error Detected (STKY and IRQE) */
-#define TX_EDEFER 0x00000020 /* TX Frame Excessive Deferral Error */
-#define TX_BROAD 0x00000040 /* TX Broadcast Frame Indicator */
-#define TX_MULTI 0x00000080 /* TX Multicast Frame Indicator */
-#define TX_CCNT 0x00000F00 /* TX Frame Collision Count */
-#define TX_DEFER 0x00001000 /* TX Frame Deferred Indicator */
-#define TX_CRS 0x00002000 /* TX Frame Carrier Sense Not Asserted Error */
-#define TX_LOSS 0x00004000 /* TX Frame Carrier Lost During TX Error */
-#define TX_RETRY 0x00008000 /* TX Frame Successful After Retry */
-#define TX_FRLEN 0x07FF0000 /* TX Frame Length (Bytes) */
-
-/* EMAC_MMC_CTL Masks */
-#define RSTC 0x00000001 /* Reset All Counters */
-#define CROLL 0x00000002 /* Counter Roll-Over Enable */
-#define CCOR 0x00000004 /* Counter Clear-On-Read Mode Enable */
-#define MMCE 0x00000008 /* Enable MMC Counter Operation */
-
-/* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */
-#define RX_OK_CNT 0x00000001 /* RX Frames Received With No Errors */
-#define RX_FCS_CNT 0x00000002 /* RX Frames W/Frame Check Sequence Errors */
-#define RX_ALIGN_CNT 0x00000004 /* RX Frames With Alignment Errors */
-#define RX_OCTET_CNT 0x00000008 /* RX Octets Received OK */
-#define RX_LOST_CNT 0x00000010 /* RX Frames Lost Due To Internal MAC RX Error */
-#define RX_UNI_CNT 0x00000020 /* Unicast RX Frames Received OK */
-#define RX_MULTI_CNT 0x00000040 /* Multicast RX Frames Received OK */
-#define RX_BROAD_CNT 0x00000080 /* Broadcast RX Frames Received OK */
-#define RX_IRL_CNT 0x00000100 /* RX Frames With In-Range Length Errors */
-#define RX_ORL_CNT 0x00000200 /* RX Frames With Out-Of-Range Length Errors */
-#define RX_LONG_CNT 0x00000400 /* RX Frames With Frame Too Long Errors */
-#define RX_MACCTL_CNT 0x00000800 /* MAC Control RX Frames Received */
-#define RX_OPCODE_CTL 0x00001000 /* Unsupported Op-Code RX Frames Received */
-#define RX_PAUSE_CNT 0x00002000 /* PAUSEMAC Control RX Frames Received */
-#define RX_ALLF_CNT 0x00004000 /* All RX Frames Received */
-#define RX_ALLO_CNT 0x00008000 /* All RX Octets Received */
-#define RX_TYPED_CNT 0x00010000 /* Typed RX Frames Received */
-#define RX_SHORT_CNT 0x00020000 /* RX Frame Fragments (< 64 Bytes) Received */
-#define RX_EQ64_CNT 0x00040000 /* 64-Byte RX Frames Received */
-#define RX_LT128_CNT 0x00080000 /* 65-127-Byte RX Frames Received */
-#define RX_LT256_CNT 0x00100000 /* 128-255-Byte RX Frames Received */
-#define RX_LT512_CNT 0x00200000 /* 256-511-Byte RX Frames Received */
-#define RX_LT1024_CNT 0x00400000 /* 512-1023-Byte RX Frames Received */
-#define RX_GE1024_CNT 0x00800000 /* 1024-Max-Byte RX Frames Received */
-
-/* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */
-
-#define TX_OK_CNT 0x00000001 /* TX Frames Sent OK */
-#define TX_SCOLL_CNT 0x00000002 /* TX Frames With Single Collisions */
-#define TX_MCOLL_CNT 0x00000004 /* TX Frames With Multiple Collisions */
-#define TX_OCTET_CNT 0x00000008 /* TX Octets Sent OK */
-#define TX_DEFER_CNT 0x00000010 /* TX Frames With Deferred Transmission */
-#define TX_LATE_CNT 0x00000020 /* TX Frames With Late Collisions */
-#define TX_ABORTC_CNT 0x00000040 /* TX Frames Aborted Due To Excess Collisions */
-#define TX_LOST_CNT 0x00000080 /* TX Frames Lost Due To Internal MAC TX Error */
-#define TX_CRS_CNT 0x00000100 /* TX Frames With Carrier Sense Errors */
-#define TX_UNI_CNT 0x00000200 /* Unicast TX Frames Sent */
-#define TX_MULTI_CNT 0x00000400 /* Multicast TX Frames Sent */
-#define TX_BROAD_CNT 0x00000800 /* Broadcast TX Frames Sent */
-#define TX_EXDEF_CTL 0x00001000 /* TX Frames With Excessive Deferral */
-#define TX_MACCTL_CNT 0x00002000 /* MAC Control TX Frames Sent */
-#define TX_ALLF_CNT 0x00004000 /* All TX Frames Sent */
-#define TX_ALLO_CNT 0x00008000 /* All TX Octets Sent */
-#define TX_EQ64_CNT 0x00010000 /* 64-Byte TX Frames Sent */
-#define TX_LT128_CNT 0x00020000 /* 65-127-Byte TX Frames Sent */
-#define TX_LT256_CNT 0x00040000 /* 128-255-Byte TX Frames Sent */
-#define TX_LT512_CNT 0x00080000 /* 256-511-Byte TX Frames Sent */
-#define TX_LT1024_CNT 0x00100000 /* 512-1023-Byte TX Frames Sent */
-#define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */
-#define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */
-
-#endif /* _DEF_BF527_H */
+++ /dev/null
-/* mach/dma.h - arch-specific DMA defines
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_DMA_H_
-#define _MACH_DMA_H_
-
-#define MAX_DMA_CHANNELS 16
-
-#define CH_PPI 0 /* PPI receive/transmit or NFC */
-#define CH_EMAC_RX 1 /* Ethernet MAC receive or HOSTDP */
-#define CH_EMAC_HOSTDP 1 /* Ethernet MAC receive or HOSTDP */
-#define CH_EMAC_TX 2 /* Ethernet MAC transmit or NFC */
-#define CH_SPORT0_RX 3 /* SPORT0 receive */
-#define CH_SPORT0_TX 4 /* SPORT0 transmit */
-#define CH_SPORT1_RX 5 /* SPORT1 receive */
-#define CH_SPORT1_TX 6 /* SPORT1 transmit */
-#define CH_SPI 7 /* SPI transmit/receive */
-#define CH_UART0_RX 8 /* UART0 receive */
-#define CH_UART0_TX 9 /* UART0 transmit */
-#define CH_UART1_RX 10 /* UART1 receive */
-#define CH_UART1_TX 11 /* UART1 transmit */
-
-#define CH_MEM_STREAM0_DEST 12 /* TX */
-#define CH_MEM_STREAM0_SRC 13 /* RX */
-#define CH_MEM_STREAM1_DEST 14 /* TX */
-#define CH_MEM_STREAM1_SRC 15 /* RX */
-
-#if defined(CONFIG_BF527_NAND_D_PORTF)
-#define CH_NFC CH_PPI /* PPI receive/transmit or NFC */
-#elif defined(CONFIG_BF527_NAND_D_PORTH)
-#define CH_NFC CH_EMAC_TX /* PPI receive/transmit or NFC */
-#endif
-
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2008 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-
-#ifndef _MACH_GPIO_H_
-#define _MACH_GPIO_H_
-
-#define MAX_BLACKFIN_GPIOS 48
-
-#define GPIO_PF0 0
-#define GPIO_PF1 1
-#define GPIO_PF2 2
-#define GPIO_PF3 3
-#define GPIO_PF4 4
-#define GPIO_PF5 5
-#define GPIO_PF6 6
-#define GPIO_PF7 7
-#define GPIO_PF8 8
-#define GPIO_PF9 9
-#define GPIO_PF10 10
-#define GPIO_PF11 11
-#define GPIO_PF12 12
-#define GPIO_PF13 13
-#define GPIO_PF14 14
-#define GPIO_PF15 15
-#define GPIO_PG0 16
-#define GPIO_PG1 17
-#define GPIO_PG2 18
-#define GPIO_PG3 19
-#define GPIO_PG4 20
-#define GPIO_PG5 21
-#define GPIO_PG6 22
-#define GPIO_PG7 23
-#define GPIO_PG8 24
-#define GPIO_PG9 25
-#define GPIO_PG10 26
-#define GPIO_PG11 27
-#define GPIO_PG12 28
-#define GPIO_PG13 29
-#define GPIO_PG14 30
-#define GPIO_PG15 31
-#define GPIO_PH0 32
-#define GPIO_PH1 33
-#define GPIO_PH2 34
-#define GPIO_PH3 35
-#define GPIO_PH4 36
-#define GPIO_PH5 37
-#define GPIO_PH6 38
-#define GPIO_PH7 39
-#define GPIO_PH8 40
-#define GPIO_PH9 41
-#define GPIO_PH10 42
-#define GPIO_PH11 43
-#define GPIO_PH12 44
-#define GPIO_PH13 45
-#define GPIO_PH14 46
-#define GPIO_PH15 47
-
-#define PORT_F GPIO_PF0
-#define PORT_G GPIO_PG0
-#define PORT_H GPIO_PH0
-
-#include <mach-common/ports-f.h>
-#include <mach-common/ports-g.h>
-#include <mach-common/ports-h.h>
-
-#endif /* _MACH_GPIO_H_ */
+++ /dev/null
-/*
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _BF527_IRQ_H_
-#define _BF527_IRQ_H_
-
-#include <mach-common/irq.h>
-
-#define NR_PERI_INTS (2 * 32)
-
-#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
-#define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */
-#define IRQ_DMAR0_BLK BFIN_IRQ(2) /* DMAR0 Block Interrupt */
-#define IRQ_DMAR1_BLK BFIN_IRQ(3) /* DMAR1 Block Interrupt */
-#define IRQ_DMAR0_OVR BFIN_IRQ(4) /* DMAR0 Overflow Error */
-#define IRQ_DMAR1_OVR BFIN_IRQ(5) /* DMAR1 Overflow Error */
-#define IRQ_PPI_ERROR BFIN_IRQ(6) /* PPI Error */
-#define IRQ_MAC_ERROR BFIN_IRQ(7) /* MAC Status */
-#define IRQ_SPORT0_ERROR BFIN_IRQ(8) /* SPORT0 Status */
-#define IRQ_SPORT1_ERROR BFIN_IRQ(9) /* SPORT1 Status */
-#define IRQ_UART0_ERROR BFIN_IRQ(12) /* UART0 Status */
-#define IRQ_UART1_ERROR BFIN_IRQ(13) /* UART1 Status */
-#define IRQ_RTC BFIN_IRQ(14) /* RTC */
-#define IRQ_PPI BFIN_IRQ(15) /* DMA Channel 0 (PPI/NAND) */
-#define IRQ_SPORT0_RX BFIN_IRQ(16) /* DMA 3 Channel (SPORT0 RX) */
-#define IRQ_SPORT0_TX BFIN_IRQ(17) /* DMA 4 Channel (SPORT0 TX) */
-#define IRQ_SPORT1_RX BFIN_IRQ(18) /* DMA 5 Channel (SPORT1 RX) */
-#define IRQ_SPORT1_TX BFIN_IRQ(19) /* DMA 6 Channel (SPORT1 TX) */
-#define IRQ_TWI BFIN_IRQ(20) /* TWI */
-#define IRQ_SPI BFIN_IRQ(21) /* DMA 7 Channel (SPI) */
-#define IRQ_UART0_RX BFIN_IRQ(22) /* DMA8 Channel (UART0 RX) */
-#define IRQ_UART0_TX BFIN_IRQ(23) /* DMA9 Channel (UART0 TX) */
-#define IRQ_UART1_RX BFIN_IRQ(24) /* DMA10 Channel (UART1 RX) */
-#define IRQ_UART1_TX BFIN_IRQ(25) /* DMA11 Channel (UART1 TX) */
-#define IRQ_OPTSEC BFIN_IRQ(26) /* OTPSEC Interrupt */
-#define IRQ_CNT BFIN_IRQ(27) /* GP Counter */
-#define IRQ_MAC_RX BFIN_IRQ(28) /* DMA1 Channel (MAC RX/HDMA) */
-#define IRQ_PORTH_INTA BFIN_IRQ(29) /* Port H Interrupt A */
-#define IRQ_MAC_TX BFIN_IRQ(30) /* DMA2 Channel (MAC TX/NAND) */
-#define IRQ_NFC BFIN_IRQ(30) /* DMA2 Channel (MAC TX/NAND) */
-#define IRQ_PORTH_INTB BFIN_IRQ(31) /* Port H Interrupt B */
-#define IRQ_TIMER0 BFIN_IRQ(32) /* Timer 0 */
-#define IRQ_TIMER1 BFIN_IRQ(33) /* Timer 1 */
-#define IRQ_TIMER2 BFIN_IRQ(34) /* Timer 2 */
-#define IRQ_TIMER3 BFIN_IRQ(35) /* Timer 3 */
-#define IRQ_TIMER4 BFIN_IRQ(36) /* Timer 4 */
-#define IRQ_TIMER5 BFIN_IRQ(37) /* Timer 5 */
-#define IRQ_TIMER6 BFIN_IRQ(38) /* Timer 6 */
-#define IRQ_TIMER7 BFIN_IRQ(39) /* Timer 7 */
-#define IRQ_PORTG_INTA BFIN_IRQ(40) /* Port G Interrupt A */
-#define IRQ_PORTG_INTB BFIN_IRQ(41) /* Port G Interrupt B */
-#define IRQ_MEM_DMA0 BFIN_IRQ(42) /* MDMA Stream 0 */
-#define IRQ_MEM_DMA1 BFIN_IRQ(43) /* MDMA Stream 1 */
-#define IRQ_WATCH BFIN_IRQ(44) /* Software Watchdog Timer */
-#define IRQ_PORTF_INTA BFIN_IRQ(45) /* Port F Interrupt A */
-#define IRQ_PORTF_INTB BFIN_IRQ(46) /* Port F Interrupt B */
-#define IRQ_SPI_ERROR BFIN_IRQ(47) /* SPI Status */
-#define IRQ_NFC_ERROR BFIN_IRQ(48) /* NAND Error */
-#define IRQ_HDMA_ERROR BFIN_IRQ(49) /* HDMA Error */
-#define IRQ_HDMA BFIN_IRQ(50) /* HDMA (TFI) */
-#define IRQ_USB_EINT BFIN_IRQ(51) /* USB_EINT Interrupt */
-#define IRQ_USB_INT0 BFIN_IRQ(52) /* USB_INT0 Interrupt */
-#define IRQ_USB_INT1 BFIN_IRQ(53) /* USB_INT1 Interrupt */
-#define IRQ_USB_INT2 BFIN_IRQ(54) /* USB_INT2 Interrupt */
-#define IRQ_USB_DMA BFIN_IRQ(55) /* USB_DMAINT Interrupt */
-
-#define SYS_IRQS BFIN_IRQ(63) /* 70 */
-
-#define IRQ_PF0 71
-#define IRQ_PF1 72
-#define IRQ_PF2 73
-#define IRQ_PF3 74
-#define IRQ_PF4 75
-#define IRQ_PF5 76
-#define IRQ_PF6 77
-#define IRQ_PF7 78
-#define IRQ_PF8 79
-#define IRQ_PF9 80
-#define IRQ_PF10 81
-#define IRQ_PF11 82
-#define IRQ_PF12 83
-#define IRQ_PF13 84
-#define IRQ_PF14 85
-#define IRQ_PF15 86
-
-#define IRQ_PG0 87
-#define IRQ_PG1 88
-#define IRQ_PG2 89
-#define IRQ_PG3 90
-#define IRQ_PG4 91
-#define IRQ_PG5 92
-#define IRQ_PG6 93
-#define IRQ_PG7 94
-#define IRQ_PG8 95
-#define IRQ_PG9 96
-#define IRQ_PG10 97
-#define IRQ_PG11 98
-#define IRQ_PG12 99
-#define IRQ_PG13 100
-#define IRQ_PG14 101
-#define IRQ_PG15 102
-
-#define IRQ_PH0 103
-#define IRQ_PH1 104
-#define IRQ_PH2 105
-#define IRQ_PH3 106
-#define IRQ_PH4 107
-#define IRQ_PH5 108
-#define IRQ_PH6 109
-#define IRQ_PH7 110
-#define IRQ_PH8 111
-#define IRQ_PH9 112
-#define IRQ_PH10 113
-#define IRQ_PH11 114
-#define IRQ_PH12 115
-#define IRQ_PH13 116
-#define IRQ_PH14 117
-#define IRQ_PH15 118
-
-#define GPIO_IRQ_BASE IRQ_PF0
-
-#define IRQ_MAC_PHYINT 119 /* PHY_INT Interrupt */
-#define IRQ_MAC_MMCINT 120 /* MMC Counter Interrupt */
-#define IRQ_MAC_RXFSINT 121 /* RX Frame-Status Interrupt */
-#define IRQ_MAC_TXFSINT 122 /* TX Frame-Status Interrupt */
-#define IRQ_MAC_WAKEDET 123 /* Wake-Up Interrupt */
-#define IRQ_MAC_RXDMAERR 124 /* RX DMA Direction Error Interrupt */
-#define IRQ_MAC_TXDMAERR 125 /* TX DMA Direction Error Interrupt */
-#define IRQ_MAC_STMDONE 126 /* Station Mgt. Transfer Done Interrupt */
-
-#define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1)
-
-/* IAR0 BIT FIELDS */
-#define IRQ_PLL_WAKEUP_POS 0
-#define IRQ_DMA0_ERROR_POS 4
-#define IRQ_DMAR0_BLK_POS 8
-#define IRQ_DMAR1_BLK_POS 12
-#define IRQ_DMAR0_OVR_POS 16
-#define IRQ_DMAR1_OVR_POS 20
-#define IRQ_PPI_ERROR_POS 24
-#define IRQ_MAC_ERROR_POS 28
-
-/* IAR1 BIT FIELDS */
-#define IRQ_SPORT0_ERROR_POS 0
-#define IRQ_SPORT1_ERROR_POS 4
-#define IRQ_UART0_ERROR_POS 16
-#define IRQ_UART1_ERROR_POS 20
-#define IRQ_RTC_POS 24
-#define IRQ_PPI_POS 28
-
-/* IAR2 BIT FIELDS */
-#define IRQ_SPORT0_RX_POS 0
-#define IRQ_SPORT0_TX_POS 4
-#define IRQ_SPORT1_RX_POS 8
-#define IRQ_SPORT1_TX_POS 12
-#define IRQ_TWI_POS 16
-#define IRQ_SPI_POS 20
-#define IRQ_UART0_RX_POS 24
-#define IRQ_UART0_TX_POS 28
-
-/* IAR3 BIT FIELDS */
-#define IRQ_UART1_RX_POS 0
-#define IRQ_UART1_TX_POS 4
-#define IRQ_OPTSEC_POS 8
-#define IRQ_CNT_POS 12
-#define IRQ_MAC_RX_POS 16
-#define IRQ_PORTH_INTA_POS 20
-#define IRQ_MAC_TX_POS 24
-#define IRQ_PORTH_INTB_POS 28
-
-/* IAR4 BIT FIELDS */
-#define IRQ_TIMER0_POS 0
-#define IRQ_TIMER1_POS 4
-#define IRQ_TIMER2_POS 8
-#define IRQ_TIMER3_POS 12
-#define IRQ_TIMER4_POS 16
-#define IRQ_TIMER5_POS 20
-#define IRQ_TIMER6_POS 24
-#define IRQ_TIMER7_POS 28
-
-/* IAR5 BIT FIELDS */
-#define IRQ_PORTG_INTA_POS 0
-#define IRQ_PORTG_INTB_POS 4
-#define IRQ_MEM_DMA0_POS 8
-#define IRQ_MEM_DMA1_POS 12
-#define IRQ_WATCH_POS 16
-#define IRQ_PORTF_INTA_POS 20
-#define IRQ_PORTF_INTB_POS 24
-#define IRQ_SPI_ERROR_POS 28
-
-/* IAR6 BIT FIELDS */
-#define IRQ_NFC_ERROR_POS 0
-#define IRQ_HDMA_ERROR_POS 4
-#define IRQ_HDMA_POS 8
-#define IRQ_USB_EINT_POS 12
-#define IRQ_USB_INT0_POS 16
-#define IRQ_USB_INT1_POS 20
-#define IRQ_USB_INT2_POS 24
-#define IRQ_USB_DMA_POS 28
-
-#endif
+++ /dev/null
-/*
- * BF52x memory map
- *
- * Copyright 2004-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MACH_MEM_MAP_H__
-#define __BFIN_MACH_MEM_MAP_H__
-
-#ifndef __BFIN_MEM_MAP_H__
-# error "do not include mach/mem_map.h directly -- use asm/mem_map.h"
-#endif
-
-/* Async Memory Banks */
-#define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */
-#define ASYNC_BANK3_SIZE 0x00100000 /* 1M */
-#define ASYNC_BANK2_BASE 0x20200000 /* Async Bank 2 */
-#define ASYNC_BANK2_SIZE 0x00100000 /* 1M */
-#define ASYNC_BANK1_BASE 0x20100000 /* Async Bank 1 */
-#define ASYNC_BANK1_SIZE 0x00100000 /* 1M */
-#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
-#define ASYNC_BANK0_SIZE 0x00100000 /* 1M */
-
-/* Boot ROM Memory */
-
-#define BOOT_ROM_START 0xEF000000
-#define BOOT_ROM_LENGTH 0x8000
-
-/* Level 1 Memory */
-
-/* Memory Map for ADSP-BF527 ADSP-BF525 ADSP-BF522 processors */
-
-#ifdef CONFIG_BFIN_ICACHE
-#define BFIN_ICACHESIZE (16*1024)
-#else
-#define BFIN_ICACHESIZE (0*1024)
-#endif
-
-#define L1_CODE_START 0xFFA00000
-#define L1_DATA_A_START 0xFF800000
-#define L1_DATA_B_START 0xFF900000
-
-#define L1_CODE_LENGTH 0xC000
-
-#ifdef CONFIG_BFIN_DCACHE
-
-#ifdef CONFIG_BFIN_DCACHE_BANKA
-#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE (16*1024)
-#define BFIN_DSUPBANKS 1
-#else
-#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
-#define BFIN_DCACHESIZE (32*1024)
-#define BFIN_DSUPBANKS 2
-#endif
-
-#else
-#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH 0x8000
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE (0*1024)
-#define BFIN_DSUPBANKS 0
-#endif /*CONFIG_BFIN_DCACHE */
-
-#endif
+++ /dev/null
-#include <mach-common/pll.h>
+++ /dev/null
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _MACH_PORTMUX_H_
-#define _MACH_PORTMUX_H_
-
-#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
-
-#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
-#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
-#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
-#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
-#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
-#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
-#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))
-#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
-#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
-#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
-#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
-#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
-#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
-#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
-#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
-#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
-
-#if defined(CONFIG_BF527_SPORT0_PORTF)
-#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
-#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
-#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
-#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
-#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
-#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
-#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
-#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
-#elif defined(CONFIG_BF527_SPORT0_PORTG)
-#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
-#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1))
-#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1))
-#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
-#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1))
-#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1))
-#if defined(CONFIG_BF527_SPORT0_TSCLK_PG10)
-#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1))
-#elif defined(CONFIG_BF527_SPORT0_TSCLK_PG14)
-#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
-#endif
-#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
-#endif
-
-#define P_SPORT1_DRPRI (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
-#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
-#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1))
-#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1))
-#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1))
-#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1))
-#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
-#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
-
-#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(2))
-#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(2))
-
-#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(2))
-#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(2))
-
-#if defined(CONFIG_BF527_UART1_PORTF)
-#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(2))
-#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(2))
-#elif defined(CONFIG_BF527_UART1_PORTG)
-#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
-#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1))
-#endif
-
-#define P_CNT_CZM (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(3))
-#define P_CNT_CDG (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(3))
-#define P_CNT_CUD (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(3))
-
-#define P_HWAIT (P_DONTCARE)
-
-#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PG1
-#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL1
-
-#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
-#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2))
-#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(2))
-#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(2))
-#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(2))
-#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
-#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
-#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
-#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
-#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
-#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
-/* #define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0)) */
-#define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
-#define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
-#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
-#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
-#define P_MDC (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1))
-#define P_RMII0_MDINT (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
-#define P_MII0_PHYINT (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
-
-#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2))
-#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2))
-#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(2))
-
-#define P_HOST_WR (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(2))
-#define P_HOST_ACK (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(2))
-#define P_HOST_ADDR (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(2))
-#define P_HOST_RD (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(2))
-#define P_HOST_CE (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(2))
-
-#if defined(CONFIG_BF527_NAND_D_PORTF)
-#define P_NAND_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(2))
-#define P_NAND_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(2))
-#define P_NAND_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(2))
-#define P_NAND_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(2))
-#define P_NAND_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(2))
-#define P_NAND_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(2))
-#define P_NAND_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(2))
-#define P_NAND_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(2))
-#elif defined(CONFIG_BF527_NAND_D_PORTH)
-#define P_NAND_D0 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
-#define P_NAND_D1 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
-#define P_NAND_D2 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
-#define P_NAND_D3 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0))
-#define P_NAND_D4 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0))
-#define P_NAND_D5 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0))
-#define P_NAND_D6 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0))
-#define P_NAND_D7 (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0))
-#endif
-
-#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(0))
-#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(0))
-#define P_NAND_CE (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(0))
-#define P_NAND_WE (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(0))
-#define P_NAND_RE (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(0))
-#define P_NAND_RB (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(0))
-#define P_NAND_CLE (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(0))
-#define P_NAND_ALE (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(0))
-
-#define P_HOST_D0 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(2))
-#define P_HOST_D1 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(2))
-#define P_HOST_D2 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(2))
-#define P_HOST_D3 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(2))
-#define P_HOST_D4 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2))
-#define P_HOST_D5 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(2))
-#define P_HOST_D6 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(2))
-#define P_HOST_D7 (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(2))
-#define P_HOST_D8 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(2))
-#define P_HOST_D9 (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(2))
-#define P_HOST_D10 (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(2))
-#define P_HOST_D11 (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(2))
-#define P_HOST_D12 (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(2))
-#define P_HOST_D13 (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(2))
-#define P_HOST_D14 (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(2))
-#define P_HOST_D15 (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(2))
-
-#define P_MII0_ETxD0 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(1))
-#define P_MII0_ETxD1 (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(1))
-#define P_MII0_ETxD2 (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(1))
-#define P_MII0_ETxD3 (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(1))
-#define P_MII0_ETxEN (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(1))
-#define P_MII0_TxCLK (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(1))
-#define P_MII0_COL (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(1))
-#define P_MII0_ERxD0 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1))
-#define P_MII0_ERxD1 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(1))
-#define P_MII0_ERxD2 (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(1))
-#define P_MII0_ERxD3 (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(1))
-#define P_MII0_ERxDV (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(1))
-#define P_MII0_ERxCLK (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(1))
-#define P_MII0_ERxER (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(1))
-#define P_MII0_CRS (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
-#define P_RMII0_REF_CLK (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(1))
-#define P_RMII0_CRS_DV (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
-#define P_MDIO (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(1))
-
-#define P_TWI0_SCL (P_DONTCARE)
-#define P_TWI0_SDA (P_DONTCARE)
-#define P_PPI0_FS1 (P_DONTCARE)
-#define P_TMR0 (P_DONTCARE)
-#define P_TMRCLK (P_DONTCARE)
-#define P_PPI0_CLK (P_DONTCARE)
-
-#define P_MII0 {\
- P_MII0_ETxD0, \
- P_MII0_ETxD1, \
- P_MII0_ETxD2, \
- P_MII0_ETxD3, \
- P_MII0_ETxEN, \
- P_MII0_TxCLK, \
- P_MII0_PHYINT, \
- P_MII0_COL, \
- P_MII0_ERxD0, \
- P_MII0_ERxD1, \
- P_MII0_ERxD2, \
- P_MII0_ERxD3, \
- P_MII0_ERxDV, \
- P_MII0_ERxCLK, \
- P_MII0_ERxER, \
- P_MII0_CRS, \
- P_MDC, \
- P_MDIO, 0}
-
-#define P_RMII0 {\
- P_MII0_ETxD0, \
- P_MII0_ETxD1, \
- P_MII0_ETxEN, \
- P_MII0_ERxD0, \
- P_MII0_ERxD1, \
- P_MII0_ERxER, \
- P_RMII0_REF_CLK, \
- P_RMII0_MDINT, \
- P_RMII0_CRS_DV, \
- P_MDC, \
- P_MDIO, 0}
-
-#endif /* _MACH_PORTMUX_H_ */
+++ /dev/null
-/*
- * Set up the interrupt priorities
- *
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-#include <linux/irq.h>
-#include <asm/blackfin.h>
-
-void __init program_IAR(void)
-{
- /* Program the IAR0 Register with the configured priority */
- bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) |
- ((CONFIG_IRQ_DMA0_ERROR - 7) << IRQ_DMA0_ERROR_POS) |
- ((CONFIG_IRQ_DMAR0_BLK - 7) << IRQ_DMAR0_BLK_POS) |
- ((CONFIG_IRQ_DMAR1_BLK - 7) << IRQ_DMAR1_BLK_POS) |
- ((CONFIG_IRQ_DMAR0_OVR - 7) << IRQ_DMAR0_OVR_POS) |
- ((CONFIG_IRQ_DMAR1_OVR - 7) << IRQ_DMAR1_OVR_POS) |
- ((CONFIG_IRQ_PPI_ERROR - 7) << IRQ_PPI_ERROR_POS) |
- ((CONFIG_IRQ_MAC_ERROR - 7) << IRQ_MAC_ERROR_POS));
-
-
- bfin_write_SIC_IAR1(((CONFIG_IRQ_SPORT0_ERROR - 7) << IRQ_SPORT0_ERROR_POS) |
- ((CONFIG_IRQ_SPORT1_ERROR - 7) << IRQ_SPORT1_ERROR_POS) |
- ((CONFIG_IRQ_UART0_ERROR - 7) << IRQ_UART0_ERROR_POS) |
- ((CONFIG_IRQ_UART1_ERROR - 7) << IRQ_UART1_ERROR_POS) |
- ((CONFIG_IRQ_RTC - 7) << IRQ_RTC_POS) |
- ((CONFIG_IRQ_PPI - 7) << IRQ_PPI_POS));
-
- bfin_write_SIC_IAR2(((CONFIG_IRQ_SPORT0_RX - 7) << IRQ_SPORT0_RX_POS) |
- ((CONFIG_IRQ_SPORT0_TX - 7) << IRQ_SPORT0_TX_POS) |
- ((CONFIG_IRQ_SPORT1_RX - 7) << IRQ_SPORT1_RX_POS) |
- ((CONFIG_IRQ_SPORT1_TX - 7) << IRQ_SPORT1_TX_POS) |
- ((CONFIG_IRQ_TWI - 7) << IRQ_TWI_POS) |
- ((CONFIG_IRQ_SPI - 7) << IRQ_SPI_POS) |
- ((CONFIG_IRQ_UART0_RX - 7) << IRQ_UART0_RX_POS) |
- ((CONFIG_IRQ_UART0_TX - 7) << IRQ_UART0_TX_POS));
-
- bfin_write_SIC_IAR3(((CONFIG_IRQ_UART1_RX - 7) << IRQ_UART1_RX_POS) |
- ((CONFIG_IRQ_UART1_TX - 7) << IRQ_UART1_TX_POS) |
- ((CONFIG_IRQ_OPTSEC - 7) << IRQ_OPTSEC_POS) |
- ((CONFIG_IRQ_CNT - 7) << IRQ_CNT_POS) |
- ((CONFIG_IRQ_MAC_RX - 7) << IRQ_MAC_RX_POS) |
- ((CONFIG_IRQ_PORTH_INTA - 7) << IRQ_PORTH_INTA_POS) |
- ((CONFIG_IRQ_MAC_TX - 7) << IRQ_MAC_TX_POS) |
- ((CONFIG_IRQ_PORTH_INTB - 7) << IRQ_PORTH_INTB_POS));
-
- bfin_write_SIC_IAR4(((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) |
- ((CONFIG_IRQ_TIMER1 - 7) << IRQ_TIMER1_POS) |
- ((CONFIG_IRQ_TIMER2 - 7) << IRQ_TIMER2_POS) |
- ((CONFIG_IRQ_TIMER3 - 7) << IRQ_TIMER3_POS) |
- ((CONFIG_IRQ_TIMER4 - 7) << IRQ_TIMER4_POS) |
- ((CONFIG_IRQ_TIMER5 - 7) << IRQ_TIMER5_POS) |
- ((CONFIG_IRQ_TIMER6 - 7) << IRQ_TIMER6_POS) |
- ((CONFIG_IRQ_TIMER7 - 7) << IRQ_TIMER7_POS));
-
- bfin_write_SIC_IAR5(((CONFIG_IRQ_PORTG_INTA - 7) << IRQ_PORTG_INTA_POS) |
- ((CONFIG_IRQ_PORTG_INTB - 7) << IRQ_PORTG_INTB_POS) |
- ((CONFIG_IRQ_MEM_DMA0 - 7) << IRQ_MEM_DMA0_POS) |
- ((CONFIG_IRQ_MEM_DMA1 - 7) << IRQ_MEM_DMA1_POS) |
- ((CONFIG_IRQ_WATCH - 7) << IRQ_WATCH_POS) |
- ((CONFIG_IRQ_PORTF_INTA - 7) << IRQ_PORTF_INTA_POS) |
- ((CONFIG_IRQ_PORTF_INTB - 7) << IRQ_PORTF_INTB_POS) |
- ((CONFIG_IRQ_SPI_ERROR - 7) << IRQ_SPI_ERROR_POS));
-
- bfin_write_SIC_IAR6(((CONFIG_IRQ_NFC_ERROR - 7) << IRQ_NFC_ERROR_POS) |
- ((CONFIG_IRQ_HDMA_ERROR - 7) << IRQ_HDMA_ERROR_POS) |
- ((CONFIG_IRQ_HDMA - 7) << IRQ_HDMA_POS) |
- ((CONFIG_IRQ_USB_EINT - 7) << IRQ_USB_EINT_POS) |
- ((CONFIG_IRQ_USB_INT0 - 7) << IRQ_USB_INT0_POS) |
- ((CONFIG_IRQ_USB_INT1 - 7) << IRQ_USB_INT1_POS) |
- ((CONFIG_IRQ_USB_INT2 - 7) << IRQ_USB_INT2_POS) |
- ((CONFIG_IRQ_USB_DMA - 7) << IRQ_USB_DMA_POS));
-
- SSYNC();
-}
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0
-if (BF533 || BF532 || BF531)
-
-source "arch/blackfin/mach-bf533/boards/Kconfig"
-
-menu "BF533/2/1 Specific Configuration"
-
-comment "Interrupt Priority Assignment"
-menu "Priority"
-
-config UART_ERROR
- int "UART ERROR"
- default 7
-config SPORT0_ERROR
- int "SPORT0 ERROR"
- default 7
-config SPI_ERROR
- int "SPI ERROR"
- default 7
-config SPORT1_ERROR
- int "SPORT1 ERROR"
- default 7
-config PPI_ERROR
- int "PPI ERROR"
- default 7
-config DMA_ERROR
- int "DMA ERROR"
- default 7
-config PLLWAKE_ERROR
- int "PLL WAKEUP ERROR"
- default 7
-
-config RTC_ERROR
- int "RTC ERROR"
- default 8
-config DMA0_PPI
- int "DMA0 PPI"
- default 8
-
-config DMA1_SPORT0RX
- int "DMA1 (SPORT0 RX)"
- default 9
-config DMA2_SPORT0TX
- int "DMA2 (SPORT0 TX)"
- default 9
-config DMA3_SPORT1RX
- int "DMA3 (SPORT1 RX)"
- default 9
-config DMA4_SPORT1TX
- int "DMA4 (SPORT1 TX)"
- default 9
-config DMA5_SPI
- int "DMA5 (SPI)"
- default 10
-config DMA6_UARTRX
- int "DMA6 (UART0 RX)"
- default 10
-config DMA7_UARTTX
- int "DMA7 (UART0 TX)"
- default 10
-config TIMER0
- int "TIMER0"
- default 7 if TICKSOURCE_GPTMR0
- default 8
-config TIMER1
- int "TIMER1"
- default 11
-config TIMER2
- int "TIMER2"
- default 11
-config PFA
- int "PF Interrupt A"
- default 12
-config PFB
- int "PF Interrupt B"
- default 12
-config MEMDMA0
- int "MEMORY DMA0"
- default 13
-config MEMDMA1
- int "MEMORY DMA1"
- default 13
-config WDTIMER
- int "WATCH DOG TIMER"
- default 13
-
- help
- Enter the priority numbers between 7-13 ONLY. Others are Reserved.
- This applies to all the above. It is not recommended to assign the
- highest priority number 7 to UART or any other device.
-
-endmenu
-
-endmenu
-
-endif
+++ /dev/null
-#
-# arch/blackfin/mach-bf533/Makefile
-#
-
-obj-y := ints-priority.o dma.o
+++ /dev/null
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2007-2008 HV Sistemas S.L.
- * Javier Herrero <jherrero@hvsistemas.es>
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-#include <linux/usb/isp1362.h>
-#endif
-#include <linux/irq.h>
-
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/reboot.h>
-#include <asm/portmux.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "HV Sistemas H8606";
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-/*
-* Driver needs to know address, irq and flag pin.
- */
-#if IS_ENABLED(CONFIG_DM9000)
-static struct resource dm9000_resources[] = {
- [0] = {
- .start = 0x20300000,
- .end = 0x20300002,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = 0x20300004,
- .end = 0x20300006,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .start = IRQ_PF10,
- .end = IRQ_PF10,
- .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE |
- IORESOURCE_IRQ_SHAREABLE),
- },
-};
-
-static struct platform_device dm9000_device = {
- .id = 0,
- .name = "dm9000",
- .resource = dm9000_resources,
- .num_resources = ARRAY_SIZE(dm9000_resources),
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
-#include <linux/smc91x.h>
-
-static struct smc91x_platdata smc91x_info = {
- .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
- .leda = RPC_LED_100_10,
- .ledb = RPC_LED_TX_RX,
-};
-
-static struct resource smc91x_resources[] = {
- {
- .name = "smc91x-regs",
- .start = 0x20300300,
- .end = 0x20300300 + 16,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PROG_INTB,
- .end = IRQ_PROG_INTB,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- }, {
- .start = IRQ_PF7,
- .end = IRQ_PF7,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev = {
- .platform_data = &smc91x_info,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
-static struct resource net2272_bfin_resources[] = {
- {
- .start = 0x20300000,
- .end = 0x20300000 + 0x100,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF10,
- .end = IRQ_PF10,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device net2272_bfin_device = {
- .name = "net2272",
- .id = -1,
- .num_resources = ARRAY_SIZE(net2272_bfin_resources),
- .resource = net2272_bfin_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* all SPI peripherals info goes here */
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader (spi)",
- .size = 0x40000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "fpga (spi)",
- .size = 0x30000,
- .offset = 0x40000
- }, {
- .name = "linux kernel (spi)",
- .size = 0x150000,
- .offset = 0x70000
- }, {
- .name = "jffs2 root file system (spi)",
- .size = 0x640000,
- .offset = 0x1c0000,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p64",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-/* Notice: for blackfin, the speed_hz is the value of register
- * SPI_BAUD, not the real baudrate */
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- /* this value is the baudrate divisor */
- .max_speed_hz = 50000000, /* actual baudrate is SCLK/(2xspeed_hz) */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 2, /* Framework chip select. On STAMP537 it is SPISSEL2*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
- {
- .modalias = "ad183x",
- .max_speed_hz = 16,
- .bus_num = 1,
- .chip_select = 4,
- },
-#endif
-
-};
-
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = BFIN_UART_THR,
- .end = BFIN_UART_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_8250)
-
-#include <linux/serial_8250.h>
-#include <linux/serial.h>
-
-/*
- * Configuration for two 16550 UARTS in FPGA at addresses 0x20200000 and 0x202000010.
- * running at half system clock, both with interrupt output or-ed to PF8. Change to
- * suit different FPGA configuration, or to suit real 16550 UARTS connected to the bus
- */
-
-static struct plat_serial8250_port serial8250_platform_data [] = {
- {
- .membase = (void *)0x20200000,
- .mapbase = 0x20200000,
- .irq = IRQ_PF8,
- .irqflags = IRQF_TRIGGER_HIGH,
- .flags = UPF_BOOT_AUTOCONF | UART_CONFIG_TYPE,
- .iotype = UPIO_MEM,
- .regshift = 1,
- .uartclk = 66666667,
- }, {
- .membase = (void *)0x20200010,
- .mapbase = 0x20200010,
- .irq = IRQ_PF8,
- .irqflags = IRQF_TRIGGER_HIGH,
- .flags = UPF_BOOT_AUTOCONF | UART_CONFIG_TYPE,
- .iotype = UPIO_MEM,
- .regshift = 1,
- .uartclk = 66666667,
- }, {
- }
-};
-
-static struct platform_device serial8250_device = {
- .id = PLAT8250_DEV_PLATFORM,
- .name = "serial8250",
- .dev = {
- .platform_data = serial8250_platform_data,
- },
-};
-
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_OPENCORES)
-
-/*
- * Configuration for one OpenCores keyboard controller in FPGA at address 0x20200030,
- * interrupt output wired to PF9. Change to suit different FPGA configuration
- */
-
-static struct resource opencores_kbd_resources[] = {
- [0] = {
- .start = 0x20200030,
- .end = 0x20300030 + 2,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_PF9,
- .end = IRQ_PF9,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
- },
-};
-
-static struct platform_device opencores_kbd_device = {
- .id = -1,
- .name = "opencores-kbd",
- .resource = opencores_kbd_resources,
- .num_resources = ARRAY_SIZE(opencores_kbd_resources),
-};
-#endif
-
-static struct platform_device *h8606_devices[] __initdata = {
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_DM9000)
- &dm9000_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
- &smc91x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
- &net2272_bfin_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_8250)
- &serial8250_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_OPENCORES)
- &opencores_kbd_device,
-#endif
-};
-
-static int __init H8606_init(void)
-{
- printk(KERN_INFO "HV Sistemas H8606 board support by http://www.hvsistemas.com\n");
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- platform_add_devices(h8606_devices, ARRAY_SIZE(h8606_devices));
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
-#endif
- return 0;
-}
-
-arch_initcall(H8606_init);
-
-static struct platform_device *H8606_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(H8606_early_devices,
- ARRAY_SIZE(H8606_early_devices));
-}
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0
-choice
- prompt "System type"
- default BFIN533_STAMP
- help
- Select your board!
-
-config BFIN533_EZKIT
- bool "BF533-EZKIT"
- help
- BF533-EZKIT-LITE board support.
-
-config BFIN533_STAMP
- bool "BF533-STAMP"
- help
- BF533-STAMP board support.
-
-config BLACKSTAMP
- bool "BlackStamp"
- help
- Support for the BlackStamp board. Hardware info available at
- http://blackfin.uclinux.org/gf/project/blackstamp/
-
-config BFIN533_BLUETECHNIX_CM
- bool "Bluetechnix CM-BF533"
- depends on (BF533)
- help
- CM-BF533 support for EVAL- and DEV-Board.
-
-config H8606_HVSISTEMAS
- bool "HV Sistemas H8606"
- depends on (BF532)
- help
- HV Sistemas H8606 board support.
-
-config BFIN532_IP0X
- bool "IP04/IP08 IP-PBX"
- depends on (BF532)
- help
- Core support for IP04/IP04 open hardware IP-PBX.
-
-endchoice
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0
-#
-# arch/blackfin/mach-bf533/boards/Makefile
-#
-
-obj-$(CONFIG_BFIN533_STAMP) += stamp.o
-obj-$(CONFIG_BFIN532_IP0X) += ip0x.o
-obj-$(CONFIG_BFIN533_EZKIT) += ezkit.o
-obj-$(CONFIG_BFIN533_BLUETECHNIX_CM) += cm_bf533.o
-obj-$(CONFIG_BLACKSTAMP) += blackstamp.o
-obj-$(CONFIG_H8606_HVSISTEMAS) += H8606.o
+++ /dev/null
-/*
- * Board Info File for the BlackStamp
- *
- * Copyright 2004-2008 Analog Devices Inc.
- * 2008 Benjamin Matthews <bmat@lle.rochester.edu>
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * More info about the BlackStamp at:
- * http://blackfin.uclinux.org/gf/project/blackstamp/
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <linux/irq.h>
-#include <linux/gpio.h>
-#include <linux/i2c.h>
-#include <linux/gpio/machine.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "BlackStamp";
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-/*
- * Driver needs to know address, irq and flag pin.
- */
-#if IS_ENABLED(CONFIG_SMC91X)
-#include <linux/smc91x.h>
-
-static struct smc91x_platdata smc91x_info = {
- .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
- .leda = RPC_LED_100_10,
- .ledb = RPC_LED_TX_RX,
-};
-
-static struct resource smc91x_resources[] = {
- {
- .name = "smc91x-regs",
- .start = 0x20300300,
- .end = 0x20300300 + 16,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF3,
- .end = IRQ_PF3,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev = {
- .platform_data = &smc91x_info,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00040000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = 0x180000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(spi)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p64",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 2, /* Framework chip select. */
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 7,
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = BFIN_UART_THR,
- .end = BFIN_UART_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
-#include <linux/input.h>
-#include <linux/gpio_keys.h>
-
-static struct gpio_keys_button bfin_gpio_keys_table[] = {
- {BTN_0, GPIO_PF4, 0, "gpio-keys: BTN0"},
- {BTN_1, GPIO_PF5, 0, "gpio-keys: BTN1"},
- {BTN_2, GPIO_PF6, 0, "gpio-keys: BTN2"},
-}; /* Mapped to the first three PF Test Points */
-
-static struct gpio_keys_platform_data bfin_gpio_keys_data = {
- .buttons = bfin_gpio_keys_table,
- .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
-};
-
-static struct platform_device bfin_device_gpiokeys = {
- .name = "gpio-keys",
- .dev = {
- .platform_data = &bfin_gpio_keys_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_GPIO)
-#include <linux/i2c-gpio.h>
-
-static struct gpiod_lookup_table bfin_i2c_gpiod_table = {
- .dev_id = "i2c-gpio",
- .table = {
- GPIO_LOOKUP_IDX("BFIN-GPIO", GPIO_PF8, NULL, 0,
- GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
- GPIO_LOOKUP_IDX("BFIN-GPIO", GPIO_PF9, NULL, 1,
- GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
- },
-};
-
-static struct i2c_gpio_platform_data i2c_gpio_data = {
- .udelay = 40,
-}; /* This hasn't actually been used these pins
- * are (currently) free pins on the expansion connector */
-
-static struct platform_device i2c_gpio_device = {
- .name = "i2c-gpio",
- .id = 0,
- .dev = {
- .platform_data = &i2c_gpio_data,
- },
-};
-#endif
-
-static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
-};
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
- VRPAIR(VLEV_085, 250000000),
- VRPAIR(VLEV_090, 376000000),
- VRPAIR(VLEV_095, 426000000),
- VRPAIR(VLEV_100, 426000000),
- VRPAIR(VLEV_105, 476000000),
- VRPAIR(VLEV_110, 476000000),
- VRPAIR(VLEV_115, 476000000),
- VRPAIR(VLEV_120, 600000000),
- VRPAIR(VLEV_125, 600000000),
- VRPAIR(VLEV_130, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-static struct platform_device *stamp_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
- &smc91x_device,
-#endif
-
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
- &bfin_device_gpiokeys,
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_GPIO)
- &i2c_gpio_device,
-#endif
-};
-
-static int __init blackstamp_init(void)
-{
- int ret;
-
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
-#if IS_ENABLED(CONFIG_I2C_GPIO)
- gpiod_add_lookup_table(&bfin_i2c_gpiod_table);
-#endif
- i2c_register_board_info(0, bfin_i2c_board_info,
- ARRAY_SIZE(bfin_i2c_board_info));
-
- ret = platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
- if (ret < 0)
- return ret;
-
-#if IS_ENABLED(CONFIG_SMC91X)
- /*
- * setup BF533_STAMP CPLD to route AMS3 to Ethernet MAC.
- * the bfin-async-map driver takes care of flipping between
- * flash and ethernet when necessary.
- */
- ret = gpio_request(GPIO_PF0, "enet_cpld");
- if (!ret) {
- gpio_direction_output(GPIO_PF0, 1);
- gpio_free(GPIO_PF0);
- }
-#endif
-
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
- return 0;
-}
-
-arch_initcall(blackstamp_init);
-
-static struct platform_device *stamp_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(stamp_early_devices,
- ARRAY_SIZE(stamp_early_devices));
-}
+++ /dev/null
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2008-2009 Bluetechnix
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <linux/spi/mmc_spi.h>
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-#include <linux/usb/isp1362.h>
-#endif
-#include <linux/irq.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "Bluetechnix CM BF533";
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* all SPI peripherals info goes here */
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00020000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = 0xe0000,
- .offset = 0x20000
- }, {
- .name = "file system(spi)",
- .size = 0x700000,
- .offset = 0x00100000,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p64",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
- {
- .modalias = "ad183x",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 4,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-};
-
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
-#include <linux/smc91x.h>
-
-static struct smc91x_platdata smc91x_info = {
- .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
- .leda = RPC_LED_100_10,
- .ledb = RPC_LED_TX_RX,
-};
-
-static struct resource smc91x_resources[] = {
- {
- .start = 0x20200300,
- .end = 0x20200300 + 16,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF0,
- .end = IRQ_PF0,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev = {
- .platform_data = &smc91x_info,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SMSC911X)
-#include <linux/smsc911x.h>
-
-static struct resource smsc911x_resources[] = {
- {
- .name = "smsc911x-memory",
- .start = 0x20308000,
- .end = 0x20308000 + 0xFF,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF8,
- .end = IRQ_PF8,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
- },
-};
-
-static struct smsc911x_platform_config smsc911x_config = {
- .flags = SMSC911X_USE_16BIT,
- .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
- .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
- .phy_interface = PHY_INTERFACE_MODE_MII,
-};
-
-static struct platform_device smsc911x_device = {
- .name = "smsc911x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smsc911x_resources),
- .resource = smsc911x_resources,
- .dev = {
- .platform_data = &smsc911x_config,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = BFIN_UART_THR,
- .end = BFIN_UART_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-static struct resource isp1362_hcd_resources[] = {
- {
- .start = 0x20308000,
- .end = 0x20308000,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 0x20308004,
- .end = 0x20308004,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF4,
- .end = IRQ_PF4,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
- },
-};
-
-static struct isp1362_platform_data isp1362_priv = {
- .sel15Kres = 1,
- .clknotstop = 0,
- .oc_enable = 0,
- .int_act_high = 0,
- .int_edge_triggered = 0,
- .remote_wakeup_connected = 0,
- .no_power_switching = 1,
- .power_switching_mode = 0,
-};
-
-static struct platform_device isp1362_hcd_device = {
- .name = "isp1362-hcd",
- .id = 0,
- .dev = {
- .platform_data = &isp1362_priv,
- },
- .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
- .resource = isp1362_hcd_resources,
-};
-#endif
-
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
-static struct resource net2272_bfin_resources[] = {
- {
- .start = 0x20300000,
- .end = 0x20300000 + 0x100,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF6,
- .end = IRQ_PF6,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device net2272_bfin_device = {
- .name = "net2272",
- .id = -1,
- .num_resources = ARRAY_SIZE(net2272_bfin_resources),
- .resource = net2272_bfin_resources,
-};
-#endif
-
-
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
-static struct mtd_partition para_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x40000,
- .offset = 0,
- }, {
- .name = "linux+rootfs(nor)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- },
-};
-
-static struct physmap_flash_data para_flash_data = {
- .width = 2,
- .parts = para_partitions,
- .nr_parts = ARRAY_SIZE(para_partitions),
-};
-
-static struct resource para_flash_resource = {
- .start = 0x20000000,
- .end = 0x201fffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device para_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = ¶_flash_data,
- },
- .num_resources = 1,
- .resource = ¶_flash_resource,
-};
-#endif
-
-
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
- VRPAIR(VLEV_085, 250000000),
- VRPAIR(VLEV_090, 376000000),
- VRPAIR(VLEV_095, 426000000),
- VRPAIR(VLEV_100, 426000000),
- VRPAIR(VLEV_105, 476000000),
- VRPAIR(VLEV_110, 476000000),
- VRPAIR(VLEV_115, 476000000),
- VRPAIR(VLEV_120, 600000000),
- VRPAIR(VLEV_125, 600000000),
- VRPAIR(VLEV_130, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-static struct platform_device *cm_bf533_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
- &isp1362_hcd_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
- &smc91x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SMSC911X)
- &smsc911x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
- &net2272_bfin_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
- ¶_flash_device,
-#endif
-};
-
-static int __init cm_bf533_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- platform_add_devices(cm_bf533_devices, ARRAY_SIZE(cm_bf533_devices));
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
-#endif
- return 0;
-}
-
-arch_initcall(cm_bf533_init);
-
-static struct platform_device *cm_bf533_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(cm_bf533_early_devices,
- ARRAY_SIZE(cm_bf533_early_devices));
-}
+++ /dev/null
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/plat-ram.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-#include <linux/usb/isp1362.h>
-#endif
-#include <linux/irq.h>
-#include <linux/i2c.h>
-#include <linux/gpio/machine.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "ADI BF533-EZKIT";
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-/*
- * USB-LAN EzExtender board
- * Driver needs to know address, irq and flag pin.
- */
-#if IS_ENABLED(CONFIG_SMC91X)
-#include <linux/smc91x.h>
-
-static struct smc91x_platdata smc91x_info = {
- .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
- .leda = RPC_LED_100_10,
- .ledb = RPC_LED_TX_RX,
-};
-
-static struct resource smc91x_resources[] = {
- {
- .name = "smc91x-regs",
- .start = 0x20310300,
- .end = 0x20310300 + 16,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF9,
- .end = IRQ_PF9,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev = {
- .platform_data = &smc91x_info,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
-static struct mtd_partition ezkit_partitions_a[] = {
- {
- .name = "bootloader(nor a)",
- .size = 0x40000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor a)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- },
-};
-
-static struct physmap_flash_data ezkit_flash_data_a = {
- .width = 2,
- .parts = ezkit_partitions_a,
- .nr_parts = ARRAY_SIZE(ezkit_partitions_a),
-};
-
-static struct resource ezkit_flash_resource_a = {
- .start = 0x20000000,
- .end = 0x200fffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device ezkit_flash_device_a = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &ezkit_flash_data_a,
- },
- .num_resources = 1,
- .resource = &ezkit_flash_resource_a,
-};
-
-static struct mtd_partition ezkit_partitions_b[] = {
- {
- .name = "file system(nor b)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- },
-};
-
-static struct physmap_flash_data ezkit_flash_data_b = {
- .width = 2,
- .parts = ezkit_partitions_b,
- .nr_parts = ARRAY_SIZE(ezkit_partitions_b),
-};
-
-static struct resource ezkit_flash_resource_b = {
- .start = 0x20100000,
- .end = 0x201fffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device ezkit_flash_device_b = {
- .name = "physmap-flash",
- .id = 4,
- .dev = {
- .platform_data = &ezkit_flash_data_b,
- },
- .num_resources = 1,
- .resource = &ezkit_flash_resource_b,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PLATRAM)
-static struct platdata_mtd_ram sram_data_a = {
- .mapname = "Flash A SRAM",
- .bankwidth = 2,
-};
-
-static struct resource sram_resource_a = {
- .start = 0x20240000,
- .end = 0x2024ffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device sram_device_a = {
- .name = "mtd-ram",
- .id = 8,
- .dev = {
- .platform_data = &sram_data_a,
- },
- .num_resources = 1,
- .resource = &sram_resource_a,
-};
-
-static struct platdata_mtd_ram sram_data_b = {
- .mapname = "Flash B SRAM",
- .bankwidth = 2,
-};
-
-static struct resource sram_resource_b = {
- .start = 0x202c0000,
- .end = 0x202cffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device sram_device_b = {
- .name = "mtd-ram",
- .id = 9,
- .dev = {
- .platform_data = &sram_data_b,
- },
- .num_resources = 1,
- .resource = &sram_resource_b,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00020000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = 0xe0000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(spi)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p64",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 2, /* Framework chip select. On STAMP537 it is SPISSEL2*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
- {
- .modalias = "ad183x",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 4,
- },
-#endif
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = BFIN_UART_THR,
- .end = BFIN_UART_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
-#include <linux/input.h>
-#include <linux/gpio_keys.h>
-
-static struct gpio_keys_button bfin_gpio_keys_table[] = {
- {BTN_0, GPIO_PF7, 1, "gpio-keys: BTN0"},
- {BTN_1, GPIO_PF8, 1, "gpio-keys: BTN1"},
- {BTN_2, GPIO_PF9, 1, "gpio-keys: BTN2"},
- {BTN_3, GPIO_PF10, 1, "gpio-keys: BTN3"},
-};
-
-static struct gpio_keys_platform_data bfin_gpio_keys_data = {
- .buttons = bfin_gpio_keys_table,
- .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
-};
-
-static struct platform_device bfin_device_gpiokeys = {
- .name = "gpio-keys",
- .dev = {
- .platform_data = &bfin_gpio_keys_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_GPIO)
-#include <linux/i2c-gpio.h>
-
-static struct gpiod_lookup_table bfin_i2c_gpiod_table = {
- .dev_id = "i2c-gpio",
- .table = {
- GPIO_LOOKUP_IDX("BFIN-GPIO", GPIO_PF1, NULL, 0,
- GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
- GPIO_LOOKUP_IDX("BFIN-GPIO", GPIO_PF0, NULL, 1,
- GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
- },
-};
-
-static struct i2c_gpio_platform_data i2c_gpio_data = {
- .udelay = 40,
-};
-
-static struct platform_device i2c_gpio_device = {
- .name = "i2c-gpio",
- .id = 0,
- .dev = {
- .platform_data = &i2c_gpio_data,
- },
-};
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
- VRPAIR(VLEV_085, 250000000),
- VRPAIR(VLEV_090, 376000000),
- VRPAIR(VLEV_095, 426000000),
- VRPAIR(VLEV_100, 426000000),
- VRPAIR(VLEV_105, 476000000),
- VRPAIR(VLEV_110, 476000000),
- VRPAIR(VLEV_115, 476000000),
- VRPAIR(VLEV_120, 600000000),
- VRPAIR(VLEV_125, 600000000),
- VRPAIR(VLEV_130, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
-#if IS_ENABLED(CONFIG_FB_BFIN_7393)
- {
- I2C_BOARD_INFO("bfin-adv7393", 0x2B),
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
-static struct platform_device bfin_i2s = {
- .name = "bfin-i2s",
- .id = CONFIG_SND_BF5XX_SPORT_NUM,
- /* TODO: add platform data here */
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
-static struct platform_device bfin_ac97 = {
- .name = "bfin-ac97",
- .id = CONFIG_SND_BF5XX_SPORT_NUM,
- /* TODO: add platform data here */
-};
-#endif
-
-static struct platform_device *ezkit_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
- &ezkit_flash_device_a,
- &ezkit_flash_device_b,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PLATRAM)
- &sram_device_a,
- &sram_device_b,
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
- &smc91x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
- &bfin_device_gpiokeys,
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_GPIO)
- &i2c_gpio_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
- &bfin_i2s,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
- &bfin_ac97,
-#endif
-};
-
-static int __init ezkit_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
-#if IS_ENABLED(CONFIG_I2C_GPIO)
- gpiod_add_lookup_table(&bfin_i2c_gpiod_table);
-#endif
- platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices));
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
- i2c_register_board_info(0, bfin_i2c_board_info,
- ARRAY_SIZE(bfin_i2c_board_info));
- return 0;
-}
-
-arch_initcall(ezkit_init);
-
-static struct platform_device *ezkit_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(ezkit_early_devices,
- ARRAY_SIZE(ezkit_early_devices));
-}
+++ /dev/null
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2007 David Rowe
- * 2006 Intratrade Ltd.
- * Ivan Danov <idanov@gmail.com>
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-#include <linux/usb/isp1362.h>
-#endif
-#include <asm/irq.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/portmux.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "IP04/IP08";
-
-/*
- * Driver needs to know address, irq and flag pin.
- */
-#if defined(CONFIG_BFIN532_IP0X)
-#if IS_ENABLED(CONFIG_DM9000)
-
-#include <linux/dm9000.h>
-
-static struct resource dm9000_resource1[] = {
- {
- .start = 0x20100000,
- .end = 0x20100000 + 1,
- .flags = IORESOURCE_MEM
- },{
- .start = 0x20100000 + 2,
- .end = 0x20100000 + 3,
- .flags = IORESOURCE_MEM
- },{
- .start = IRQ_PF15,
- .end = IRQ_PF15,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE
- }
-};
-
-static struct resource dm9000_resource2[] = {
- {
- .start = 0x20200000,
- .end = 0x20200000 + 1,
- .flags = IORESOURCE_MEM
- },{
- .start = 0x20200000 + 2,
- .end = 0x20200000 + 3,
- .flags = IORESOURCE_MEM
- },{
- .start = IRQ_PF14,
- .end = IRQ_PF14,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE
- }
-};
-
-/*
-* for the moment we limit ourselves to 16bit IO until some
-* better IO routines can be written and tested
-*/
-static struct dm9000_plat_data dm9000_platdata1 = {
- .flags = DM9000_PLATF_16BITONLY,
-};
-
-static struct platform_device dm9000_device1 = {
- .name = "dm9000",
- .id = 0,
- .num_resources = ARRAY_SIZE(dm9000_resource1),
- .resource = dm9000_resource1,
- .dev = {
- .platform_data = &dm9000_platdata1,
- }
-};
-
-static struct dm9000_plat_data dm9000_platdata2 = {
- .flags = DM9000_PLATF_16BITONLY,
-};
-
-static struct platform_device dm9000_device2 = {
- .name = "dm9000",
- .id = 1,
- .num_resources = ARRAY_SIZE(dm9000_resource2),
- .resource = dm9000_resource2,
- .dev = {
- .platform_data = &dm9000_platdata2,
- }
-};
-
-#endif
-#endif
-
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* all SPI peripherals info goes here */
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0, /* if 1 - block!!! */
-};
-#endif
-
-/* Notice: for blackfin, the speed_hz is the value of register
- * SPI_BAUD, not the real baudrate */
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 2,
- .bus_num = 1,
- .chip_select = 5,
- .controller_data = &mmc_spi_chip_info,
- },
-#endif
-};
-
-/* SPI controller data */
-static struct bfin5xx_spi_master spi_bfin_master_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
-};
-
-static struct platform_device spi_bfin_master_device = {
- .name = "bfin-spi-master",
- .id = 1, /* Bus number */
- .dev = {
- .platform_data = &spi_bfin_master_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = BFIN_UART_THR,
- .end = BFIN_UART_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-static struct resource isp1362_hcd_resources[] = {
- {
- .start = 0x20300000,
- .end = 0x20300000 + 1,
- .flags = IORESOURCE_MEM,
- },{
- .start = 0x20300000 + 2,
- .end = 0x20300000 + 3,
- .flags = IORESOURCE_MEM,
- },{
- .start = IRQ_PF11,
- .end = IRQ_PF11,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
- },
-};
-
-static struct isp1362_platform_data isp1362_priv = {
- .sel15Kres = 1,
- .clknotstop = 0,
- .oc_enable = 0, /* external OC */
- .int_act_high = 0,
- .int_edge_triggered = 0,
- .remote_wakeup_connected = 0,
- .no_power_switching = 1,
- .power_switching_mode = 0,
-};
-
-static struct platform_device isp1362_hcd_device = {
- .name = "isp1362-hcd",
- .id = 0,
- .dev = {
- .platform_data = &isp1362_priv,
- },
- .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
- .resource = isp1362_hcd_resources,
-};
-#endif
-
-
-static struct platform_device *ip0x_devices[] __initdata = {
-#if defined(CONFIG_BFIN532_IP0X)
-#if IS_ENABLED(CONFIG_DM9000)
- &dm9000_device1,
- &dm9000_device2,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &spi_bfin_master_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
- &isp1362_hcd_device,
-#endif
-};
-
-static int __init ip0x_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- platform_add_devices(ip0x_devices, ARRAY_SIZE(ip0x_devices));
-
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
-
- return 0;
-}
-
-arch_initcall(ip0x_init);
-
-static struct platform_device *ip0x_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(ip0x_early_devices,
- ARRAY_SIZE(ip0x_early_devices));
-}
+++ /dev/null
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/delay.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <linux/spi/mmc_spi.h>
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-#include <linux/usb/isp1362.h>
-#endif
-#include <linux/gpio.h>
-#include <linux/irq.h>
-#include <linux/i2c.h>
-#include <linux/gpio/machine.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/reboot.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "ADI BF533-STAMP";
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-/*
- * Driver needs to know address, irq and flag pin.
- */
-#if IS_ENABLED(CONFIG_SMC91X)
-#include <linux/smc91x.h>
-
-static struct smc91x_platdata smc91x_info = {
- .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
- .leda = RPC_LED_100_10,
- .ledb = RPC_LED_TX_RX,
-};
-
-static struct resource smc91x_resources[] = {
- {
- .name = "smc91x-regs",
- .start = 0x20300300,
- .end = 0x20300300 + 16,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF7,
- .end = IRQ_PF7,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev = {
- .platform_data = &smc91x_info,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
-static struct resource net2272_bfin_resources[] = {
- {
- .start = 0x20300000,
- .end = 0x20300000 + 0x100,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 1,
- .flags = IORESOURCE_BUS,
- }, {
- .start = IRQ_PF10,
- .end = IRQ_PF10,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device net2272_bfin_device = {
- .name = "net2272",
- .id = -1,
- .num_resources = ARRAY_SIZE(net2272_bfin_resources),
- .resource = net2272_bfin_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_BFIN_ASYNC)
-static struct mtd_partition stamp_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x40000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0x180000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct physmap_flash_data stamp_flash_data = {
- .width = 2,
- .parts = stamp_partitions,
- .nr_parts = ARRAY_SIZE(stamp_partitions),
-};
-
-static struct resource stamp_flash_resource[] = {
- {
- .name = "cfi_probe",
- .start = 0x20000000,
- .end = 0x203fffff,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 0x7BB07BB0, /* AMBCTL0 setting when accessing flash */
- .end = 0x7BB07BB0, /* AMBCTL1 setting when accessing flash */
- .flags = IORESOURCE_MEM,
- }, {
- .start = GPIO_PF0,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-static struct platform_device stamp_flash_device = {
- .name = "bfin-async-flash",
- .id = 0,
- .dev = {
- .platform_data = &stamp_flash_data,
- },
- .num_resources = ARRAY_SIZE(stamp_flash_resource),
- .resource = stamp_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00040000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = 0x180000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(spi)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p64",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-#define MMC_SPI_CARD_DETECT_INT IRQ_PF5
-static int bfin_mmc_spi_init(struct device *dev,
- irqreturn_t (*detect_int)(int, void *), void *data)
-{
- return request_irq(MMC_SPI_CARD_DETECT_INT, detect_int,
- IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
- "mmc-spi-detect", data);
-}
-
-static void bfin_mmc_spi_exit(struct device *dev, void *data)
-{
- free_irq(MMC_SPI_CARD_DETECT_INT, data);
-}
-
-static struct mmc_spi_platform_data bfin_mmc_spi_pdata = {
- .init = bfin_mmc_spi_init,
- .exit = bfin_mmc_spi_exit,
- .detect_delay = 100, /* msecs */
-};
-
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0,
- .pio_interrupt = 0,
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 2, /* Framework chip select. On STAMP537 it is SPISSEL2*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
- {
- .modalias = "ad1836",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 4,
- .platform_data = "ad1836", /* only includes chip name for the moment */
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- },
-#endif
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 4,
- .platform_data = &bfin_mmc_spi_pdata,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = BFIN_UART_THR,
- .end = BFIN_UART_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SPORT)
-static struct resource bfin_sport0_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_TX,
- .end = IRQ_SPORT0_TX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_SPORT0_TX,
- .end = CH_SPORT0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_SPORT0_RX,
- .end = CH_SPORT0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sport0_device = {
- .name = "bfin_sport_raw",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_resources),
- .resource = bfin_sport0_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
-#include <linux/input.h>
-#include <linux/gpio_keys.h>
-
-static struct gpio_keys_button bfin_gpio_keys_table[] = {
- {BTN_0, GPIO_PF5, 0, "gpio-keys: BTN0"},
- {BTN_1, GPIO_PF6, 0, "gpio-keys: BTN1"},
- {BTN_2, GPIO_PF8, 0, "gpio-keys: BTN2"},
-};
-
-static struct gpio_keys_platform_data bfin_gpio_keys_data = {
- .buttons = bfin_gpio_keys_table,
- .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
-};
-
-static struct platform_device bfin_device_gpiokeys = {
- .name = "gpio-keys",
- .dev = {
- .platform_data = &bfin_gpio_keys_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_GPIO)
-#include <linux/i2c-gpio.h>
-
-static struct gpiod_lookup_table bfin_i2c_gpiod_table = {
- .dev_id = "i2c-gpio",
- .table = {
- GPIO_LOOKUP_IDX("BFIN-GPIO", GPIO_PF2, NULL, 0,
- GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
- GPIO_LOOKUP_IDX("BFIN-GPIO", GPIO_PF3, NULL, 1,
- GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
- },
-};
-
-static struct i2c_gpio_platform_data i2c_gpio_data = {
- .udelay = 10,
-};
-
-static struct platform_device i2c_gpio_device = {
- .name = "i2c-gpio",
- .id = 0,
- .dev = {
- .platform_data = &i2c_gpio_data,
- },
-};
-#endif
-
-static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
-#if IS_ENABLED(CONFIG_JOYSTICK_AD7142)
- {
- I2C_BOARD_INFO("ad7142_joystick", 0x2C),
- .irq = 39,
- },
-#endif
-#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
- {
- I2C_BOARD_INFO("pcf8574_lcd", 0x22),
- },
-#endif
-#if IS_ENABLED(CONFIG_INPUT_PCF8574)
- {
- I2C_BOARD_INFO("pcf8574_keypad", 0x27),
- .irq = 39,
- },
-#endif
-#if IS_ENABLED(CONFIG_FB_BFIN_7393)
- {
- I2C_BOARD_INFO("bfin-adv7393", 0x2B),
- },
-#endif
-#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
- {
- I2C_BOARD_INFO("ad5252", 0x2f),
- },
-#endif
-};
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
- VRPAIR(VLEV_085, 250000000),
- VRPAIR(VLEV_090, 376000000),
- VRPAIR(VLEV_095, 426000000),
- VRPAIR(VLEV_100, 426000000),
- VRPAIR(VLEV_105, 476000000),
- VRPAIR(VLEV_110, 476000000),
- VRPAIR(VLEV_115, 476000000),
- VRPAIR(VLEV_120, 600000000),
- VRPAIR(VLEV_125, 600000000),
- VRPAIR(VLEV_130, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S) || \
- IS_ENABLED(CONFIG_SND_BF5XX_AC97)
-
-#include <asm/bfin_sport.h>
-
-#define SPORT_REQ(x) \
- [x] = {P_SPORT##x##_TFS, P_SPORT##x##_DTPRI, P_SPORT##x##_TSCLK, \
- P_SPORT##x##_RFS, P_SPORT##x##_DRPRI, P_SPORT##x##_RSCLK, 0}
-
-static const u16 bfin_snd_pin[][7] = {
- SPORT_REQ(0),
- SPORT_REQ(1),
-};
-
-static struct bfin_snd_platform_data bfin_snd_data[] = {
- {
- .pin_req = &bfin_snd_pin[0][0],
- },
- {
- .pin_req = &bfin_snd_pin[1][0],
- },
-};
-
-#define BFIN_SND_RES(x) \
- [x] = { \
- { \
- .start = SPORT##x##_TCR1, \
- .end = SPORT##x##_TCR1, \
- .flags = IORESOURCE_MEM \
- }, \
- { \
- .start = CH_SPORT##x##_RX, \
- .end = CH_SPORT##x##_RX, \
- .flags = IORESOURCE_DMA, \
- }, \
- { \
- .start = CH_SPORT##x##_TX, \
- .end = CH_SPORT##x##_TX, \
- .flags = IORESOURCE_DMA, \
- }, \
- { \
- .start = IRQ_SPORT##x##_ERROR, \
- .end = IRQ_SPORT##x##_ERROR, \
- .flags = IORESOURCE_IRQ, \
- } \
- }
-
-static struct resource bfin_snd_resources[][4] = {
- BFIN_SND_RES(0),
- BFIN_SND_RES(1),
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
-static struct platform_device bfin_i2s_pcm = {
- .name = "bfin-i2s-pcm-audio",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
-static struct platform_device bfin_ac97_pcm = {
- .name = "bfin-ac97-pcm-audio",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
-static const char * const ad1836_link[] = {
- "bfin-i2s.0",
- "spi0.4",
-};
-static struct platform_device bfin_ad1836_machine = {
- .name = "bfin-snd-ad1836",
- .id = -1,
- .dev = {
- .platform_data = (void *)ad1836_link,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD73311)
-static const unsigned ad73311_gpio[] = {
- GPIO_PF4,
-};
-
-static struct platform_device bfin_ad73311_machine = {
- .name = "bfin-snd-ad73311",
- .id = 1,
- .dev = {
- .platform_data = (void *)ad73311_gpio,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_SOC_AD73311)
-static struct platform_device bfin_ad73311_codec_device = {
- .name = "ad73311",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_SOC_AD74111)
-static struct platform_device bfin_ad74111_codec_device = {
- .name = "ad74111",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_I2S)
-static struct platform_device bfin_i2s = {
- .name = "bfin-i2s",
- .id = CONFIG_SND_BF5XX_SPORT_NUM,
- .num_resources =
- ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
- .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
- .dev = {
- .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AC97)
-static struct platform_device bfin_ac97 = {
- .name = "bfin-ac97",
- .id = CONFIG_SND_BF5XX_SPORT_NUM,
- .num_resources =
- ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
- .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
- .dev = {
- .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
- },
-};
-#endif
-
-static struct platform_device *stamp_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
- &smc91x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
- &net2272_bfin_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
- &bfin_device_gpiokeys,
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_GPIO)
- &i2c_gpio_device,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_BFIN_ASYNC)
- &stamp_flash_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
- &bfin_i2s_pcm,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
- &bfin_ac97_pcm,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
- &bfin_ad1836_machine,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD73311)
- &bfin_ad73311_machine,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_SOC_AD73311)
- &bfin_ad73311_codec_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_SOC_AD74111)
- &bfin_ad74111_codec_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_I2S)
- &bfin_i2s,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AC97)
- &bfin_ac97,
-#endif
-};
-
-static int __init net2272_init(void)
-{
-#if IS_ENABLED(CONFIG_USB_NET2272)
- int ret;
-
- /* Set PF0 to 0, PF1 to 1 make /AMS3 work properly */
- ret = gpio_request(GPIO_PF0, "net2272");
- if (ret)
- return ret;
-
- ret = gpio_request(GPIO_PF1, "net2272");
- if (ret) {
- gpio_free(GPIO_PF0);
- return ret;
- }
-
- ret = gpio_request(GPIO_PF11, "net2272");
- if (ret) {
- gpio_free(GPIO_PF0);
- gpio_free(GPIO_PF1);
- return ret;
- }
-
- gpio_direction_output(GPIO_PF0, 0);
- gpio_direction_output(GPIO_PF1, 1);
-
- /* Reset the USB chip */
- gpio_direction_output(GPIO_PF11, 0);
- mdelay(2);
- gpio_set_value(GPIO_PF11, 1);
-#endif
-
- return 0;
-}
-
-static int __init stamp_init(void)
-{
- int ret;
-
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
-
-#if IS_ENABLED(CONFIG_I2C_GPIO)
- gpiod_add_lookup_table(&bfin_i2c_gpiod_table);
-#endif
- i2c_register_board_info(0, bfin_i2c_board_info,
- ARRAY_SIZE(bfin_i2c_board_info));
-
- ret = platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
- if (ret < 0)
- return ret;
-
-#if IS_ENABLED(CONFIG_SMC91X)
- /*
- * setup BF533_STAMP CPLD to route AMS3 to Ethernet MAC.
- * the bfin-async-map driver takes care of flipping between
- * flash and ethernet when necessary.
- */
- ret = gpio_request(GPIO_PF0, "enet_cpld");
- if (!ret) {
- gpio_direction_output(GPIO_PF0, 1);
- gpio_free(GPIO_PF0);
- }
-#endif
-
- if (net2272_init())
- pr_warning("unable to configure net2272; it probably won't work\n");
-
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
- return 0;
-}
-
-arch_initcall(stamp_init);
-
-static struct platform_device *stamp_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(stamp_early_devices,
- ARRAY_SIZE(stamp_early_devices));
-}
-
-void native_machine_restart(char *cmd)
-{
- /* workaround pull up on cpld / flash pin not being strong enough */
- gpio_request(GPIO_PF0, "flash_cpld");
- gpio_direction_output(GPIO_PF0, 0);
-}
+++ /dev/null
-/*
- * simple DMA Implementation for Blackfin
- *
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-
-#include <asm/blackfin.h>
-#include <asm/dma.h>
-
-struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
- (struct dma_register *) DMA0_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_NEXT_DESC_PTR,
- (struct dma_register *) DMA3_NEXT_DESC_PTR,
- (struct dma_register *) DMA4_NEXT_DESC_PTR,
- (struct dma_register *) DMA5_NEXT_DESC_PTR,
- (struct dma_register *) DMA6_NEXT_DESC_PTR,
- (struct dma_register *) DMA7_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
-};
-EXPORT_SYMBOL(dma_io_base_addr);
-
-int channel2irq(unsigned int channel)
-{
- int ret_irq = -1;
-
- switch (channel) {
- case CH_PPI:
- ret_irq = IRQ_PPI;
- break;
-
- case CH_SPORT0_RX:
- ret_irq = IRQ_SPORT0_RX;
- break;
-
- case CH_SPORT0_TX:
- ret_irq = IRQ_SPORT0_TX;
- break;
-
- case CH_SPORT1_RX:
- ret_irq = IRQ_SPORT1_RX;
- break;
-
- case CH_SPORT1_TX:
- ret_irq = IRQ_SPORT1_TX;
- break;
-
- case CH_SPI:
- ret_irq = IRQ_SPI;
- break;
-
- case CH_UART0_RX:
- ret_irq = IRQ_UART0_RX;
- break;
-
- case CH_UART0_TX:
- ret_irq = IRQ_UART0_TX;
- break;
-
- case CH_MEM_STREAM0_SRC:
- case CH_MEM_STREAM0_DEST:
- ret_irq = IRQ_MEM_DMA0;
- break;
-
- case CH_MEM_STREAM1_SRC:
- case CH_MEM_STREAM1_DEST:
- ret_irq = IRQ_MEM_DMA1;
- break;
- }
- return ret_irq;
-}
+++ /dev/null
-/*
- * DO NOT EDIT THIS FILE
- * This file is under version control at
- * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
- * and can be replaced with that version at any time
- * DO NOT EDIT THIS FILE
- *
- * Copyright 2004-2011 Analog Devices Inc.
- * Licensed under the Clear BSD license.
- */
-
-/* This file should be up to date with:
- * - Revision G, 05/23/2011; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
- */
-
-#ifndef _MACH_ANOMALY_H_
-#define _MACH_ANOMALY_H_
-
-/* We do not support 0.1 or 0.2 silicon - sorry */
-#if __SILICON_REVISION__ < 3
-# error will not work on BF533 silicon version 0.0, 0.1, or 0.2
-#endif
-
-#if defined(__ADSPBF531__)
-# define ANOMALY_BF531 1
-#else
-# define ANOMALY_BF531 0
-#endif
-#if defined(__ADSPBF532__)
-# define ANOMALY_BF532 1
-#else
-# define ANOMALY_BF532 0
-#endif
-#if defined(__ADSPBF533__)
-# define ANOMALY_BF533 1
-#else
-# define ANOMALY_BF533 0
-#endif
-
-/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
-#define ANOMALY_05000074 (1)
-/* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */
-#define ANOMALY_05000099 (__SILICON_REVISION__ < 5)
-/* Watchpoint Status Register (WPSTAT) Bits Are Set on Every Corresponding Match */
-#define ANOMALY_05000105 (__SILICON_REVISION__ > 2)
-/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
-#define ANOMALY_05000119 (1)
-/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
-#define ANOMALY_05000122 (1)
-/* Instruction DMA Can Cause Data Cache Fills to Fail (Boot Implications) */
-#define ANOMALY_05000158 (__SILICON_REVISION__ < 5)
-/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */
-#define ANOMALY_05000166 (1)
-/* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */
-#define ANOMALY_05000167 (1)
-/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */
-#define ANOMALY_05000179 (__SILICON_REVISION__ < 5)
-/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
-#define ANOMALY_05000180 (1)
-/* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */
-#define ANOMALY_05000183 (__SILICON_REVISION__ < 4)
-/* False Protection Exceptions when Speculative Fetch Is Cancelled */
-#define ANOMALY_05000189 (__SILICON_REVISION__ < 4)
-/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */
-#define ANOMALY_05000193 (__SILICON_REVISION__ < 4)
-/* Restarting SPORT in Specific Modes May Cause Data Corruption */
-#define ANOMALY_05000194 (__SILICON_REVISION__ < 4)
-/* Failing MMR Accesses when Preceding Memory Read Stalls */
-#define ANOMALY_05000198 (__SILICON_REVISION__ < 5)
-/* Current DMA Address Shows Wrong Value During Carry Fix */
-#define ANOMALY_05000199 (__SILICON_REVISION__ < 4)
-/* SPORT TFS and DT Are Incorrectly Driven During Inactive Channels in Certain Conditions */
-#define ANOMALY_05000200 (__SILICON_REVISION__ == 3 || __SILICON_REVISION__ == 4)
-/* Receive Frame Sync Not Ignored During Active Frames in SPORT Multi-Channel Mode */
-#define ANOMALY_05000201 (__SILICON_REVISION__ == 3)
-/* Possible Infinite Stall with Specific Dual-DAG Situation */
-#define ANOMALY_05000202 (__SILICON_REVISION__ < 5)
-/* Specific Sequence That Can Cause DMA Error or DMA Stopping */
-#define ANOMALY_05000203 (__SILICON_REVISION__ < 4)
-/* Incorrect Data Read with Writethrough "Allocate Cache Lines on Reads Only" Cache Mode */
-#define ANOMALY_05000204 (__SILICON_REVISION__ < 4 && ANOMALY_BF533)
-/* Recovery from "Brown-Out" Condition */
-#define ANOMALY_05000207 (__SILICON_REVISION__ < 4)
-/* VSTAT Status Bit in PLL_STAT Register Is Not Functional */
-#define ANOMALY_05000208 (1)
-/* Speed Path in Computational Unit Affects Certain Instructions */
-#define ANOMALY_05000209 (__SILICON_REVISION__ < 4)
-/* UART TX Interrupt Masked Erroneously */
-#define ANOMALY_05000215 (__SILICON_REVISION__ < 5)
-/* NMI Event at Boot Time Results in Unpredictable State */
-#define ANOMALY_05000219 (1)
-/* Incorrect Pulse-Width of UART Start Bit */
-#define ANOMALY_05000225 (__SILICON_REVISION__ < 5)
-/* Scratchpad Memory Bank Reads May Return Incorrect Data */
-#define ANOMALY_05000227 (__SILICON_REVISION__ < 5)
-/* SPI Slave Boot Mode Modifies Registers from Reset Value */
-#define ANOMALY_05000229 (1)
-/* UART Receiver is Less Robust Against Baudrate Differences in Certain Conditions */
-#define ANOMALY_05000230 (__SILICON_REVISION__ < 5)
-/* UART STB Bit Incorrectly Affects Receiver Setting */
-#define ANOMALY_05000231 (__SILICON_REVISION__ < 5)
-/* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */
-#define ANOMALY_05000233 (__SILICON_REVISION__ < 6)
-/* Incorrect Revision Number in DSPID Register */
-#define ANOMALY_05000234 (__SILICON_REVISION__ == 4)
-/* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */
-#define ANOMALY_05000242 (__SILICON_REVISION__ < 5)
-/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
-#define ANOMALY_05000244 (__SILICON_REVISION__ < 5)
-/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
-#define ANOMALY_05000245 (1)
-/* Data CPLBs Should Prevent False Hardware Errors */
-#define ANOMALY_05000246 (__SILICON_REVISION__ < 5)
-/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
-#define ANOMALY_05000250 (__SILICON_REVISION__ == 4)
-/* Maximum External Clock Speed for Timers */
-#define ANOMALY_05000253 (__SILICON_REVISION__ < 5)
-/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
-#define ANOMALY_05000254 (__SILICON_REVISION__ > 4)
-/* Entering Hibernate State with RTC Seconds Interrupt Not Functional */
-#define ANOMALY_05000255 (__SILICON_REVISION__ < 5)
-/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */
-#define ANOMALY_05000257 (__SILICON_REVISION__ < 5)
-/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */
-#define ANOMALY_05000258 (__SILICON_REVISION__ < 5)
-/* ICPLB_STATUS MMR Register May Be Corrupted */
-#define ANOMALY_05000260 (__SILICON_REVISION__ < 5)
-/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
-#define ANOMALY_05000261 (__SILICON_REVISION__ < 5)
-/* Stores To Data Cache May Be Lost */
-#define ANOMALY_05000262 (__SILICON_REVISION__ < 5)
-/* Hardware Loop Corrupted When Taking an ICPLB Exception */
-#define ANOMALY_05000263 (__SILICON_REVISION__ < 5)
-/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */
-#define ANOMALY_05000264 (__SILICON_REVISION__ < 5)
-/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
-#define ANOMALY_05000265 (1)
-/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */
-#define ANOMALY_05000269 (__SILICON_REVISION__ < 5)
-/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
-#define ANOMALY_05000270 (__SILICON_REVISION__ < 5)
-/* Spontaneous Reset of Internal Voltage Regulator */
-#define ANOMALY_05000271 (__SILICON_REVISION__ == 3)
-/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
-#define ANOMALY_05000272 (1)
-/* Writes to Synchronous SDRAM Memory May Be Lost */
-#define ANOMALY_05000273 (__SILICON_REVISION__ < 6)
-/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */
-#define ANOMALY_05000276 (1)
-/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
-#define ANOMALY_05000277 (__SILICON_REVISION__ < 6)
-/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
-#define ANOMALY_05000278 (__SILICON_REVISION__ < 6)
-/* False Hardware Error when ISR Context Is Not Restored */
-#define ANOMALY_05000281 (__SILICON_REVISION__ < 6)
-/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
-#define ANOMALY_05000282 (__SILICON_REVISION__ < 6)
-/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */
-#define ANOMALY_05000283 (__SILICON_REVISION__ < 6)
-/* SPORTs May Receive Bad Data If FIFOs Fill Up */
-#define ANOMALY_05000288 (__SILICON_REVISION__ < 6)
-/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
-#define ANOMALY_05000301 (__SILICON_REVISION__ < 6)
-/* SSYNCs after Writes to DMA MMR Registers May Not Be Handled Correctly */
-#define ANOMALY_05000302 (__SILICON_REVISION__ < 5)
-/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */
-#define ANOMALY_05000305 (__SILICON_REVISION__ < 5)
-/* ALT_TIMING Bit in PPI_CONTROL Register Is Not Functional */
-#define ANOMALY_05000306 (__SILICON_REVISION__ < 5)
-/* SCKELOW Bit Does Not Maintain State Through Hibernate */
-#define ANOMALY_05000307 (1) /* note: brokenness is noted in documentation, not anomaly sheet */
-/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
-#define ANOMALY_05000310 (1)
-/* Erroneous Flag (GPIO) Pin Operations under Specific Sequences */
-#define ANOMALY_05000311 (__SILICON_REVISION__ < 6)
-/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
-#define ANOMALY_05000312 (__SILICON_REVISION__ < 6)
-/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
-#define ANOMALY_05000313 (__SILICON_REVISION__ < 6)
-/* Killed System MMR Write Completes Erroneously on Next System MMR Access */
-#define ANOMALY_05000315 (__SILICON_REVISION__ < 6)
-/* Internal Voltage Regulator Values of 1.05V, 1.10V and 1.15V Not Allowed for LQFP Packages */
-#define ANOMALY_05000319 ((ANOMALY_BF531 || ANOMALY_BF532) && __SILICON_REVISION__ < 6)
-/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
-#define ANOMALY_05000357 (__SILICON_REVISION__ < 6)
-/* UART Break Signal Issues */
-#define ANOMALY_05000363 (__SILICON_REVISION__ < 5)
-/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
-#define ANOMALY_05000366 (1)
-/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
-#define ANOMALY_05000371 (__SILICON_REVISION__ < 6)
-/* PPI Does Not Start Properly In Specific Mode */
-#define ANOMALY_05000400 (__SILICON_REVISION__ == 5)
-/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
-#define ANOMALY_05000402 (__SILICON_REVISION__ == 5)
-/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
-#define ANOMALY_05000403 (1)
-/* Speculative Fetches Can Cause Undesired External FIFO Operations */
-#define ANOMALY_05000416 (1)
-/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
-#define ANOMALY_05000425 (1)
-/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
-#define ANOMALY_05000426 (1)
-/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
-#define ANOMALY_05000443 (1)
-/* False Hardware Error when RETI Points to Invalid Memory */
-#define ANOMALY_05000461 (1)
-/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
-#define ANOMALY_05000462 (1)
-/* Boot Failure When SDRAM Control Signals Toggle Coming Out Of Reset */
-#define ANOMALY_05000471 (1)
-/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
-#define ANOMALY_05000473 (1)
-/* Possible Lockup Condition when Modifying PLL from External Memory */
-#define ANOMALY_05000475 (1)
-/* TESTSET Instruction Cannot Be Interrupted */
-#define ANOMALY_05000477 (1)
-/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
-#define ANOMALY_05000481 (1)
-/* PLL May Latch Incorrect Values Coming Out of Reset */
-#define ANOMALY_05000489 (1)
-/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
-#define ANOMALY_05000491 (1)
-/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
-#define ANOMALY_05000494 (1)
-/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
-#define ANOMALY_05000501 (1)
-
-/*
- * These anomalies have been "phased" out of analog.com anomaly sheets and are
- * here to show running on older silicon just isn't feasible.
- */
-
-/* Internal voltage regulator can't be modified via register writes */
-#define ANOMALY_05000066 (__SILICON_REVISION__ < 2)
-/* Watchpoints (Hardware Breakpoints) are not supported */
-#define ANOMALY_05000067 (__SILICON_REVISION__ < 3)
-/* SDRAM PSSE bit cannot be set again after SDRAM Powerup */
-#define ANOMALY_05000070 (__SILICON_REVISION__ < 2)
-/* Writing FIO_DIR can corrupt a programmable flag's data */
-#define ANOMALY_05000079 (__SILICON_REVISION__ < 2)
-/* Timer Auto-Baud Mode requires the UART clock to be enabled. */
-#define ANOMALY_05000086 (__SILICON_REVISION__ < 2)
-/* Internal Clocking Modes on SPORT0 not supported */
-#define ANOMALY_05000088 (__SILICON_REVISION__ < 2)
-/* Internal voltage regulator does not wake up from an RTC wakeup */
-#define ANOMALY_05000092 (__SILICON_REVISION__ < 2)
-/* The IFLUSH Instruction Must Be Preceded by a CSYNC Instruction */
-#define ANOMALY_05000093 (__SILICON_REVISION__ < 2)
-/* Vectoring to instruction that is being filled into the i-cache may cause erroneous behavior */
-#define ANOMALY_05000095 (__SILICON_REVISION__ < 2)
-/* PREFETCH, FLUSH, and FLUSHINV Instructions Must Be Followed by a CSYNC Instruction */
-#define ANOMALY_05000096 (__SILICON_REVISION__ < 2)
-/* Performance Monitor 0 and 1 are swapped when monitoring memory events */
-#define ANOMALY_05000097 (__SILICON_REVISION__ < 2)
-/* 32-bit SPORT DMA will be word reversed */
-#define ANOMALY_05000098 (__SILICON_REVISION__ < 2)
-/* Incorrect status in the UART_IIR register */
-#define ANOMALY_05000100 (__SILICON_REVISION__ < 2)
-/* Reading X_MODIFY or Y_MODIFY while DMA channel is active */
-#define ANOMALY_05000101 (__SILICON_REVISION__ < 2)
-/* Descriptor MemDMA may lock up with 32-bit transfers or if transfers span 64KB buffers */
-#define ANOMALY_05000102 (__SILICON_REVISION__ < 2)
-/* Incorrect Value Written to the Cycle Counters */
-#define ANOMALY_05000103 (__SILICON_REVISION__ < 2)
-/* Stores to L1 Data Memory Incorrect when a Specific Sequence Is Followed */
-#define ANOMALY_05000104 (__SILICON_REVISION__ < 2)
-/* Programmable Flag (PF3) functionality not supported in all PPI modes */
-#define ANOMALY_05000106 (__SILICON_REVISION__ < 2)
-/* Data store can be lost when targeting a cache line fill */
-#define ANOMALY_05000107 (__SILICON_REVISION__ < 2)
-/* Reserved Bits in SYSCFG Register Not Set at Power-On */
-#define ANOMALY_05000109 (__SILICON_REVISION__ < 3)
-/* Infinite Core Stall */
-#define ANOMALY_05000114 (__SILICON_REVISION__ < 2)
-/* PPI_FSx may glitch when generated by the on chip Timers. */
-#define ANOMALY_05000115 (__SILICON_REVISION__ < 2)
-/* Trace Buffers May Contain Errors in Emulation Mode and/or Exception, NMI, Reset Handlers */
-#define ANOMALY_05000116 (__SILICON_REVISION__ < 3)
-/* DTEST registers allow access to Data Cache when DTEST_COMMAND< 14 >= 0 */
-#define ANOMALY_05000117 (__SILICON_REVISION__ < 2)
-/* Booting from an 8-bit or 24-bit Addressable SPI device is not supported */
-#define ANOMALY_05000118 (__SILICON_REVISION__ < 2)
-/* DTEST_COMMAND Initiated Memory Access May Be Incorrect If Data Cache or DMA Is Active */
-#define ANOMALY_05000123 (__SILICON_REVISION__ < 3)
-/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */
-#define ANOMALY_05000124 (__SILICON_REVISION__ < 3)
-/* Erroneous Exception when Enabling Cache */
-#define ANOMALY_05000125 (__SILICON_REVISION__ < 3)
-/* SPI clock polarity and phase bits incorrect during booting */
-#define ANOMALY_05000126 (__SILICON_REVISION__ < 3)
-/* DMEM_CONTROL<12> Is Not Set on Reset */
-#define ANOMALY_05000137 (__SILICON_REVISION__ < 3)
-/* SPI boot will not complete if there is a zero fill block in the loader file */
-#define ANOMALY_05000138 (__SILICON_REVISION__ == 2)
-/* TIMERx_CONFIG[5] must be set for PPI in GP output mode with internal Frame Syncs */
-#define ANOMALY_05000139 (__SILICON_REVISION__ < 2)
-/* Allowing the SPORT RX FIFO to fill will cause an overflow */
-#define ANOMALY_05000140 (__SILICON_REVISION__ < 3)
-/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */
-#define ANOMALY_05000141 (__SILICON_REVISION__ < 3)
-/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */
-#define ANOMALY_05000142 (__SILICON_REVISION__ < 3)
-/* A read from external memory may return a wrong value with data cache enabled */
-#define ANOMALY_05000143 (__SILICON_REVISION__ < 3)
-/* DMA and TESTSET conflict when both are accessing external memory */
-#define ANOMALY_05000144 (__SILICON_REVISION__ < 3)
-/* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */
-#define ANOMALY_05000145 (__SILICON_REVISION__ < 3)
-/* MDMA may lose the first few words of a descriptor chain */
-#define ANOMALY_05000146 (__SILICON_REVISION__ < 3)
-/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */
-#define ANOMALY_05000147 (__SILICON_REVISION__ < 3)
-/* When booting from 16-bit asynchronous memory, the upper 8 bits of each word must be 0x00 */
-#define ANOMALY_05000148 (__SILICON_REVISION__ < 3)
-/* Frame Delay in SPORT Multichannel Mode */
-#define ANOMALY_05000153 (__SILICON_REVISION__ < 3)
-/* SPORT TFS signal stays active in multichannel mode outside of valid channels */
-#define ANOMALY_05000154 (__SILICON_REVISION__ < 3)
-/* Timer1 can not be used for PWMOUT mode when a certain PPI mode is in use */
-#define ANOMALY_05000155 (__SILICON_REVISION__ < 3)
-/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
-#define ANOMALY_05000157 (__SILICON_REVISION__ < 3)
-/* SPORT Transmit Data Is Not Gated by External Frame Sync in Certain Conditions */
-#define ANOMALY_05000163 (__SILICON_REVISION__ < 3)
-/* Undefined Behavior when Power-Up Sequence Is Issued to SDRAM during Auto-Refresh */
-#define ANOMALY_05000168 (__SILICON_REVISION__ < 3)
-/* DATA CPLB Page Miss Can Result in Lost Write-Through Data Cache Writes */
-#define ANOMALY_05000169 (__SILICON_REVISION__ < 3)
-/* DMA vs Core accesses to external memory */
-#define ANOMALY_05000173 (__SILICON_REVISION__ < 3)
-/* Cache Fill Buffer Data lost */
-#define ANOMALY_05000174 (__SILICON_REVISION__ < 3)
-/* Overlapping Sequencer and Memory Stalls */
-#define ANOMALY_05000175 (__SILICON_REVISION__ < 3)
-/* Overflow Bit Asserted when Multiplication of -1 by -1 Followed by Accumulator Saturation */
-#define ANOMALY_05000176 (__SILICON_REVISION__ < 3)
-/* Disabling the PPI Resets the PPI Configuration Registers */
-#define ANOMALY_05000181 (__SILICON_REVISION__ < 3)
-/* Early PPI Transmit when FS1 Asserts before FS2 in TX Mode with 2 External Frame Syncs */
-#define ANOMALY_05000185 (__SILICON_REVISION__ < 3)
-/* PPI does not invert the Driving PPICLK edge in Transmit Modes */
-#define ANOMALY_05000191 (__SILICON_REVISION__ < 3)
-/* In PPI Transmit Modes with External Frame Syncs POLC bit must be set to 1 */
-#define ANOMALY_05000192 (__SILICON_REVISION__ < 3)
-/* Internal Voltage Regulator may not start up */
-#define ANOMALY_05000206 (__SILICON_REVISION__ < 3)
-
-/* Anomalies that don't exist on this proc */
-#define ANOMALY_05000120 (0)
-#define ANOMALY_05000149 (0)
-#define ANOMALY_05000171 (0)
-#define ANOMALY_05000182 (0)
-#define ANOMALY_05000220 (0)
-#define ANOMALY_05000248 (0)
-#define ANOMALY_05000266 (0)
-#define ANOMALY_05000274 (0)
-#define ANOMALY_05000287 (0)
-#define ANOMALY_05000323 (0)
-#define ANOMALY_05000353 (1)
-#define ANOMALY_05000362 (1)
-#define ANOMALY_05000364 (0)
-#define ANOMALY_05000380 (0)
-#define ANOMALY_05000383 (0)
-#define ANOMALY_05000386 (1)
-#define ANOMALY_05000389 (0)
-#define ANOMALY_05000412 (0)
-#define ANOMALY_05000430 (0)
-#define ANOMALY_05000432 (0)
-#define ANOMALY_05000435 (0)
-#define ANOMALY_05000440 (0)
-#define ANOMALY_05000447 (0)
-#define ANOMALY_05000448 (0)
-#define ANOMALY_05000456 (0)
-#define ANOMALY_05000450 (0)
-#define ANOMALY_05000465 (0)
-#define ANOMALY_05000467 (0)
-#define ANOMALY_05000474 (0)
-#define ANOMALY_05000480 (0)
-#define ANOMALY_05000485 (0)
-#define ANOMALY_16000030 (0)
-
-#endif
+++ /dev/null
-/*
- * SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561
- *
- * Copyright 2005-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __MACH_BF533_H__
-#define __MACH_BF533_H__
-
-#define OFFSET_(x) ((x) & 0x0000FFFF)
-
-/*some misc defines*/
-#define IMASK_IVG15 0x8000
-#define IMASK_IVG14 0x4000
-#define IMASK_IVG13 0x2000
-#define IMASK_IVG12 0x1000
-
-#define IMASK_IVG11 0x0800
-#define IMASK_IVG10 0x0400
-#define IMASK_IVG9 0x0200
-#define IMASK_IVG8 0x0100
-
-#define IMASK_IVG7 0x0080
-#define IMASK_IVGTMR 0x0040
-#define IMASK_IVGHW 0x0020
-
-/***************************/
-
-
-#define BFIN_DSUBBANKS 4
-#define BFIN_DWAYS 2
-#define BFIN_DLINES 64
-#define BFIN_ISUBBANKS 4
-#define BFIN_IWAYS 4
-#define BFIN_ILINES 32
-
-#define WAY0_L 0x1
-#define WAY1_L 0x2
-#define WAY01_L 0x3
-#define WAY2_L 0x4
-#define WAY02_L 0x5
-#define WAY12_L 0x6
-#define WAY012_L 0x7
-
-#define WAY3_L 0x8
-#define WAY03_L 0x9
-#define WAY13_L 0xA
-#define WAY013_L 0xB
-
-#define WAY32_L 0xC
-#define WAY320_L 0xD
-#define WAY321_L 0xE
-#define WAYALL_L 0xF
-
-#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
-
-/* IAR0 BIT FIELDS*/
-#define RTC_ERROR_BIT 0x0FFFFFFF
-#define UART_ERROR_BIT 0xF0FFFFFF
-#define SPORT1_ERROR_BIT 0xFF0FFFFF
-#define SPI_ERROR_BIT 0xFFF0FFFF
-#define SPORT0_ERROR_BIT 0xFFFF0FFF
-#define PPI_ERROR_BIT 0xFFFFF0FF
-#define DMA_ERROR_BIT 0xFFFFFF0F
-#define PLLWAKE_ERROR_BIT 0xFFFFFFFF
-
-/* IAR1 BIT FIELDS*/
-#define DMA7_UARTTX_BIT 0x0FFFFFFF
-#define DMA6_UARTRX_BIT 0xF0FFFFFF
-#define DMA5_SPI_BIT 0xFF0FFFFF
-#define DMA4_SPORT1TX_BIT 0xFFF0FFFF
-#define DMA3_SPORT1RX_BIT 0xFFFF0FFF
-#define DMA2_SPORT0TX_BIT 0xFFFFF0FF
-#define DMA1_SPORT0RX_BIT 0xFFFFFF0F
-#define DMA0_PPI_BIT 0xFFFFFFFF
-
-/* IAR2 BIT FIELDS*/
-#define WDTIMER_BIT 0x0FFFFFFF
-#define MEMDMA1_BIT 0xF0FFFFFF
-#define MEMDMA0_BIT 0xFF0FFFFF
-#define PFB_BIT 0xFFF0FFFF
-#define PFA_BIT 0xFFFF0FFF
-#define TIMER2_BIT 0xFFFFF0FF
-#define TIMER1_BIT 0xFFFFFF0F
-#define TIMER0_BIT 0xFFFFFFFF
-
-/********************************* EBIU Settings ************************************/
-#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
-#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
-
-#ifdef CONFIG_C_AMBEN_ALL
-#define V_AMBEN AMBEN_ALL
-#endif
-#ifdef CONFIG_C_AMBEN
-#define V_AMBEN 0x0
-#endif
-#ifdef CONFIG_C_AMBEN_B0
-#define V_AMBEN AMBEN_B0
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1
-#define V_AMBEN AMBEN_B0_B1
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1_B2
-#define V_AMBEN AMBEN_B0_B1_B2
-#endif
-#ifdef CONFIG_C_AMCKEN
-#define V_AMCKEN AMCKEN
-#else
-#define V_AMCKEN 0x0
-#endif
-#ifdef CONFIG_C_CDPRIO
-#define V_CDPRIO 0x100
-#else
-#define V_CDPRIO 0x0
-#endif
-
-#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO)
-
-#ifdef CONFIG_BF533
-#define CPU "BF533"
-#define CPUID 0x27a5
-#endif
-#ifdef CONFIG_BF532
-#define CPU "BF532"
-#define CPUID 0x27a5
-#endif
-#ifdef CONFIG_BF531
-#define CPU "BF531"
-#define CPUID 0x27a5
-#endif
-
-#ifndef CPU
-#error "Unknown CPU type - This kernel doesn't seem to be configured properly"
-#endif
-
-#endif /* __MACH_BF533_H__ */
+++ /dev/null
-/*
- * mach/bfin_serial.h - Blackfin UART/Serial definitions
- *
- * Copyright 2006-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MACH_SERIAL_H__
-#define __BFIN_MACH_SERIAL_H__
-
-#define BFIN_UART_NR_PORTS 1
-
-#endif
+++ /dev/null
-/*
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_BLACKFIN_H_
-#define _MACH_BLACKFIN_H_
-
-#define BF533_FAMILY
-
-#include "bf533.h"
-#include "anomaly.h"
-
-#include <asm/def_LPBlackfin.h>
-#include "defBF532.h"
-
-#ifndef __ASSEMBLY__
-# include <asm/cdef_LPBlackfin.h>
-# include "cdefBF532.h"
-#endif
-
-#endif
+++ /dev/null
-/*
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _CDEF_BF532_H
-#define _CDEF_BF532_H
-
-/* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */
-#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
-#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val)
-#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val)
-#define bfin_read_CHIPID() bfin_read32(CHIPID)
-#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val)
-#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
-
-/* System Interrupt Controller (0xFFC0 0C00-0xFFC0 0FFF) */
-#define bfin_read_SWRST() bfin_read16(SWRST)
-#define bfin_write_SWRST(val) bfin_write16(SWRST,val)
-#define bfin_read_SYSCR() bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val) bfin_write16(SYSCR,val)
-#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
-#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0,val)
-#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
-#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1,val)
-#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
-#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2,val)
-#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
-#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3,val)
-#define bfin_read_SIC_IMASK() bfin_read32(SIC_IMASK)
-#define bfin_write_SIC_IMASK(val) bfin_write32(SIC_IMASK,val)
-#define bfin_read_SIC_ISR() bfin_read32(SIC_ISR)
-#define bfin_write_SIC_ISR(val) bfin_write32(SIC_ISR,val)
-#define bfin_read_SIC_IWR() bfin_read32(SIC_IWR)
-#define bfin_write_SIC_IWR(val) bfin_write32(SIC_IWR,val)
-
-/* Watchdog Timer (0xFFC0 1000-0xFFC0 13FF) */
-#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL,val)
-#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT,val)
-#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT,val)
-
-/* Real Time Clock (0xFFC0 1400-0xFFC0 17FF) */
-#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
-#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT,val)
-#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
-#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL,val)
-#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
-#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT,val)
-#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
-#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT,val)
-#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
-#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM,val)
-#define bfin_read_RTC_FAST() bfin_read16(RTC_FAST)
-#define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST,val)
-#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
-#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN,val)
-
-/* DMA Traffic controls */
-#define bfin_read_DMAC_TC_PER() bfin_read16(DMAC_TC_PER)
-#define bfin_write_DMAC_TC_PER(val) bfin_write16(DMAC_TC_PER,val)
-#define bfin_read_DMAC_TC_CNT() bfin_read16(DMAC_TC_CNT)
-#define bfin_write_DMAC_TC_CNT(val) bfin_write16(DMAC_TC_CNT,val)
-
-/* General Purpose IO (0xFFC0 2400-0xFFC0 27FF) */
-#define bfin_read_FIO_DIR() bfin_read16(FIO_DIR)
-#define bfin_write_FIO_DIR(val) bfin_write16(FIO_DIR,val)
-#define bfin_read_FIO_MASKA_C() bfin_read16(FIO_MASKA_C)
-#define bfin_write_FIO_MASKA_C(val) bfin_write16(FIO_MASKA_C,val)
-#define bfin_read_FIO_MASKA_S() bfin_read16(FIO_MASKA_S)
-#define bfin_write_FIO_MASKA_S(val) bfin_write16(FIO_MASKA_S,val)
-#define bfin_read_FIO_MASKB_C() bfin_read16(FIO_MASKB_C)
-#define bfin_write_FIO_MASKB_C(val) bfin_write16(FIO_MASKB_C,val)
-#define bfin_read_FIO_MASKB_S() bfin_read16(FIO_MASKB_S)
-#define bfin_write_FIO_MASKB_S(val) bfin_write16(FIO_MASKB_S,val)
-#define bfin_read_FIO_POLAR() bfin_read16(FIO_POLAR)
-#define bfin_write_FIO_POLAR(val) bfin_write16(FIO_POLAR,val)
-#define bfin_read_FIO_EDGE() bfin_read16(FIO_EDGE)
-#define bfin_write_FIO_EDGE(val) bfin_write16(FIO_EDGE,val)
-#define bfin_read_FIO_BOTH() bfin_read16(FIO_BOTH)
-#define bfin_write_FIO_BOTH(val) bfin_write16(FIO_BOTH,val)
-#define bfin_read_FIO_INEN() bfin_read16(FIO_INEN)
-#define bfin_write_FIO_INEN(val) bfin_write16(FIO_INEN,val)
-#define bfin_read_FIO_MASKA_D() bfin_read16(FIO_MASKA_D)
-#define bfin_write_FIO_MASKA_D(val) bfin_write16(FIO_MASKA_D,val)
-#define bfin_read_FIO_MASKA_T() bfin_read16(FIO_MASKA_T)
-#define bfin_write_FIO_MASKA_T(val) bfin_write16(FIO_MASKA_T,val)
-#define bfin_read_FIO_MASKB_D() bfin_read16(FIO_MASKB_D)
-#define bfin_write_FIO_MASKB_D(val) bfin_write16(FIO_MASKB_D,val)
-#define bfin_read_FIO_MASKB_T() bfin_read16(FIO_MASKB_T)
-#define bfin_write_FIO_MASKB_T(val) bfin_write16(FIO_MASKB_T,val)
-
-#if ANOMALY_05000311
-/* Keep at the CPP expansion to avoid circular header dependency loops */
-#define BFIN_WRITE_FIO_FLAG(name, val) \
- do { \
- unsigned long __flags; \
- __flags = hard_local_irq_save(); \
- bfin_write16(FIO_FLAG_##name, val); \
- bfin_read_CHIPID(); \
- hard_local_irq_restore(__flags); \
- } while (0)
-#define bfin_write_FIO_FLAG_D(val) BFIN_WRITE_FIO_FLAG(D, val)
-#define bfin_write_FIO_FLAG_C(val) BFIN_WRITE_FIO_FLAG(C, val)
-#define bfin_write_FIO_FLAG_S(val) BFIN_WRITE_FIO_FLAG(S, val)
-#define bfin_write_FIO_FLAG_T(val) BFIN_WRITE_FIO_FLAG(T, val)
-
-#define BFIN_READ_FIO_FLAG(name) \
- ({ \
- unsigned long __flags; \
- u16 __ret; \
- __flags = hard_local_irq_save(); \
- __ret = bfin_read16(FIO_FLAG_##name); \
- bfin_read_CHIPID(); \
- hard_local_irq_restore(__flags); \
- __ret; \
- })
-#define bfin_read_FIO_FLAG_D() BFIN_READ_FIO_FLAG(D)
-#define bfin_read_FIO_FLAG_C() BFIN_READ_FIO_FLAG(C)
-#define bfin_read_FIO_FLAG_S() BFIN_READ_FIO_FLAG(S)
-#define bfin_read_FIO_FLAG_T() BFIN_READ_FIO_FLAG(T)
-
-#else
-#define bfin_write_FIO_FLAG_D(val) bfin_write16(FIO_FLAG_D, val)
-#define bfin_write_FIO_FLAG_C(val) bfin_write16(FIO_FLAG_C, val)
-#define bfin_write_FIO_FLAG_S(val) bfin_write16(FIO_FLAG_S, val)
-#define bfin_write_FIO_FLAG_T(val) bfin_write16(FIO_FLAG_T, val)
-#define bfin_read_FIO_FLAG_D() bfin_read16(FIO_FLAG_D)
-#define bfin_read_FIO_FLAG_C() bfin_read16(FIO_FLAG_C)
-#define bfin_read_FIO_FLAG_S() bfin_read16(FIO_FLAG_S)
-#define bfin_read_FIO_FLAG_T() bfin_read16(FIO_FLAG_T)
-#endif
-
-/* DMA Controller */
-#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
-#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG,val)
-#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR,val)
-#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR,val)
-#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
-#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT,val)
-#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
-#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT,val)
-#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY,val)
-#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY,val)
-#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR,val)
-#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR,val)
-#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
-#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT,val)
-#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
-#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT,val)
-#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
-#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS,val)
-#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
-#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
-#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG,val)
-#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR,val)
-#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
-#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT,val)
-#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
-#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT,val)
-#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY,val)
-#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY,val)
-#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR,val)
-#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
-#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT,val)
-#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
-#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
-#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS,val)
-#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
-#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG,val)
-#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR,val)
-#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
-#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT,val)
-#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
-#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT,val)
-#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY,val)
-#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY,val)
-#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR,val)
-#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
-#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT,val)
-#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
-#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
-#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS,val)
-#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
-#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG,val)
-#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR,val)
-#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR,val)
-#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
-#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT,val)
-#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
-#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT,val)
-#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY,val)
-#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY,val)
-#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR,val)
-#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR,val)
-#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
-#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT,val)
-#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
-#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT,val)
-#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
-#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS,val)
-#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
-#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
-#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG,val)
-#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR,val)
-#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR,val)
-#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
-#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT,val)
-#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
-#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT,val)
-#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY,val)
-#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY,val)
-#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR,val)
-#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR,val)
-#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
-#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT,val)
-#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
-#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT,val)
-#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
-#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS,val)
-#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
-#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
-#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG,val)
-#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR,val)
-#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR,val)
-#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
-#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT,val)
-#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
-#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT,val)
-#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY,val)
-#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY,val)
-#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR,val)
-#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR,val)
-#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
-#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT,val)
-#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
-#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT,val)
-#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
-#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS,val)
-#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
-#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
-#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG,val)
-#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR,val)
-#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR,val)
-#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
-#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT,val)
-#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
-#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT,val)
-#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY,val)
-#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY,val)
-#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR,val)
-#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR,val)
-#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
-#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT,val)
-#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
-#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT,val)
-#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
-#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS,val)
-#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
-#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
-#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG,val)
-#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR,val)
-#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR,val)
-#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
-#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT,val)
-#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
-#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT,val)
-#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY,val)
-#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY,val)
-#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR,val)
-#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR,val)
-#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
-#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT,val)
-#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
-#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT,val)
-#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
-#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS,val)
-#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
-#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP,val)
-
-#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
-#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG,val)
-#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR)
-#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR,val)
-#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
-#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT,val)
-#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
-#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT,val)
-#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
-#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY,val)
-#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
-#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY,val)
-#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR)
-#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR,val)
-#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
-#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT,val)
-#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
-#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS,val)
-#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP,val)
-
-#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
-#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG,val)
-#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR)
-#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR,val)
-#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
-#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT,val)
-#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
-#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT,val)
-#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
-#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY,val)
-#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
-#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY,val)
-#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR)
-#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR,val)
-#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
-#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT,val)
-#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
-#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS,val)
-#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP,val)
-
-#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
-#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG,val)
-#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR)
-#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR,val)
-#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
-#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT,val)
-#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
-#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT,val)
-#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
-#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY,val)
-#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
-#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY,val)
-#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR)
-#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR,val)
-#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
-#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT,val)
-#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
-#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS,val)
-#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP,val)
-
-#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
-#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG,val)
-#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR)
-#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR,val)
-#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
-#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT,val)
-#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
-#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT,val)
-#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
-#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY,val)
-#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
-#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY,val)
-#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR)
-#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR,val)
-#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
-#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT,val)
-#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
-#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS,val)
-#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP,val)
-
-/* Aysnchronous Memory Controller - External Bus Interface Unit (0xFFC0 3C00-0xFFC0 3FFF) */
-#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL,val)
-#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0,val)
-#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1,val)
-
-/* SDRAM Controller External Bus Interface Unit (0xFFC0 4C00-0xFFC0 4FFF) */
-#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
-#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL,val)
-#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
-#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC,val)
-#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
-#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT,val)
-#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL)
-#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL,val)
-
-/* UART Controller */
-#define bfin_read_UART_THR() bfin_read16(UART_THR)
-#define bfin_write_UART_THR(val) bfin_write16(UART_THR,val)
-#define bfin_read_UART_RBR() bfin_read16(UART_RBR)
-#define bfin_write_UART_RBR(val) bfin_write16(UART_RBR,val)
-#define bfin_read_UART_DLL() bfin_read16(UART_DLL)
-#define bfin_write_UART_DLL(val) bfin_write16(UART_DLL,val)
-#define bfin_read_UART_IER() bfin_read16(UART_IER)
-#define bfin_write_UART_IER(val) bfin_write16(UART_IER,val)
-#define bfin_read_UART_DLH() bfin_read16(UART_DLH)
-#define bfin_write_UART_DLH(val) bfin_write16(UART_DLH,val)
-#define bfin_read_UART_IIR() bfin_read16(UART_IIR)
-#define bfin_write_UART_IIR(val) bfin_write16(UART_IIR,val)
-#define bfin_read_UART_LCR() bfin_read16(UART_LCR)
-#define bfin_write_UART_LCR(val) bfin_write16(UART_LCR,val)
-#define bfin_read_UART_MCR() bfin_read16(UART_MCR)
-#define bfin_write_UART_MCR(val) bfin_write16(UART_MCR,val)
-#define bfin_read_UART_LSR() bfin_read16(UART_LSR)
-#define bfin_write_UART_LSR(val) bfin_write16(UART_LSR,val)
-/*
-#define UART_MSR
-*/
-#define bfin_read_UART_SCR() bfin_read16(UART_SCR)
-#define bfin_write_UART_SCR(val) bfin_write16(UART_SCR,val)
-#define bfin_read_UART_GCTL() bfin_read16(UART_GCTL)
-#define bfin_write_UART_GCTL(val) bfin_write16(UART_GCTL,val)
-
-/* SPI Controller */
-#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL)
-#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL,val)
-#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG)
-#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG,val)
-#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT)
-#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT,val)
-#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR)
-#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR,val)
-#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR)
-#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR,val)
-#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD)
-#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD,val)
-#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW)
-#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW,val)
-
-/* TIMER 0, 1, 2 Registers */
-#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG,val)
-#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER,val)
-#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD,val)
-#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH,val)
-
-#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG,val)
-#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER,val)
-#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD,val)
-#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH,val)
-
-#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG,val)
-#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER,val)
-#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD,val)
-#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH,val)
-
-#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE)
-#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE,val)
-#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE)
-#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE,val)
-#define bfin_read_TIMER_STATUS() bfin_read16(TIMER_STATUS)
-#define bfin_write_TIMER_STATUS(val) bfin_write16(TIMER_STATUS,val)
-
-/* SPORT0 Controller */
-#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1,val)
-#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2,val)
-#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV,val)
-#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV,val)
-#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX,val)
-#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX,val)
-#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX,val)
-#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX,val)
-#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX)
-#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX,val)
-#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX)
-#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX,val)
-#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1,val)
-#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2,val)
-#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV,val)
-#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV,val)
-#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT,val)
-#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL,val)
-#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1,val)
-#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2,val)
-#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0,val)
-#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1,val)
-#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2,val)
-#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3,val)
-#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0,val)
-#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1,val)
-#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2,val)
-#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3,val)
-
-/* SPORT1 Controller */
-#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1,val)
-#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2,val)
-#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV,val)
-#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV,val)
-#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX,val)
-#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX,val)
-#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX,val)
-#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX,val)
-#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX)
-#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX,val)
-#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX)
-#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX,val)
-#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1,val)
-#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2,val)
-#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV,val)
-#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV,val)
-#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT,val)
-#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL,val)
-#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1,val)
-#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2,val)
-#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
-#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0,val)
-#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
-#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1,val)
-#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
-#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2,val)
-#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
-#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3,val)
-#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
-#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0,val)
-#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
-#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1,val)
-#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
-#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2,val)
-#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
-#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3,val)
-
-/* Parallel Peripheral Interface (PPI) */
-#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL)
-#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL,val)
-#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS)
-#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS,val)
-#define bfin_clear_PPI_STATUS() bfin_read_PPI_STATUS()
-#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY)
-#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY,val)
-#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT)
-#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT,val)
-#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME)
-#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME,val)
-
-#endif /* _CDEF_BF532_H */
+++ /dev/null
-/*
- * System & MMR bit and Address definitions for ADSP-BF532
- *
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF532_H
-#define _DEF_BF532_H
-
-/*********************************************************************************** */
-/* System MMR Register Map */
-/*********************************************************************************** */
-/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
-
-#define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */
-#define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */
-#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */
-#define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */
-#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */
-#define CHIPID 0xFFC00014 /* Chip ID Register */
-
-/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
-#define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */
-#define SYSCR 0xFFC00104 /* System Configuration registe */
-#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
-#define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */
-#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
-#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
-#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
-#define SIC_ISR 0xFFC00120 /* Interrupt Status Register */
-#define SIC_IWR 0xFFC00124 /* Interrupt Wakeup Register */
-
-/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
-#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
-#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
-#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
-
-/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
-#define RTC_STAT 0xFFC00300 /* RTC Status Register */
-#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
-#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
-#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
-#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */
-#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */
-#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register (alternate macro) */
-
-/* UART Controller (0xFFC00400 - 0xFFC004FF) */
-
-/*
- * Because include/linux/serial_reg.h have defined UART_*,
- * So we define blackfin uart regs to BFIN_UART_*.
- */
-#define BFIN_UART_THR 0xFFC00400 /* Transmit Holding register */
-#define BFIN_UART_RBR 0xFFC00400 /* Receive Buffer register */
-#define BFIN_UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
-#define BFIN_UART_IER 0xFFC00404 /* Interrupt Enable Register */
-#define BFIN_UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
-#define BFIN_UART_IIR 0xFFC00408 /* Interrupt Identification Register */
-#define BFIN_UART_LCR 0xFFC0040C /* Line Control Register */
-#define BFIN_UART_MCR 0xFFC00410 /* Modem Control Register */
-#define BFIN_UART_LSR 0xFFC00414 /* Line Status Register */
-#if 0
-#define BFIN_UART_MSR 0xFFC00418 /* Modem Status Register (UNUSED in ADSP-BF532) */
-#endif
-#define BFIN_UART_SCR 0xFFC0041C /* SCR Scratch Register */
-#define BFIN_UART_GCTL 0xFFC00424 /* Global Control Register */
-
-/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
-#define SPI0_REGBASE 0xFFC00500
-#define SPI_CTL 0xFFC00500 /* SPI Control Register */
-#define SPI_FLG 0xFFC00504 /* SPI Flag register */
-#define SPI_STAT 0xFFC00508 /* SPI Status register */
-#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */
-#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */
-#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */
-#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */
-
-/* TIMER 0, 1, 2 Registers (0xFFC00600 - 0xFFC006FF) */
-
-#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */
-#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */
-#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */
-#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */
-
-#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */
-#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */
-#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */
-#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */
-
-#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */
-#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */
-#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */
-#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */
-
-#define TIMER_ENABLE 0xFFC00640 /* Timer Enable Register */
-#define TIMER_DISABLE 0xFFC00644 /* Timer Disable Register */
-#define TIMER_STATUS 0xFFC00648 /* Timer Status Register */
-
-/* General Purpose IO (0xFFC00700 - 0xFFC007FF) */
-
-#define FIO_FLAG_D 0xFFC00700 /* Flag Mask to directly specify state of pins */
-#define FIO_FLAG_C 0xFFC00704 /* Peripheral Interrupt Flag Register (clear) */
-#define FIO_FLAG_S 0xFFC00708 /* Peripheral Interrupt Flag Register (set) */
-#define FIO_FLAG_T 0xFFC0070C /* Flag Mask to directly toggle state of pins */
-#define FIO_MASKA_D 0xFFC00710 /* Flag Mask Interrupt A Register (set directly) */
-#define FIO_MASKA_C 0xFFC00714 /* Flag Mask Interrupt A Register (clear) */
-#define FIO_MASKA_S 0xFFC00718 /* Flag Mask Interrupt A Register (set) */
-#define FIO_MASKA_T 0xFFC0071C /* Flag Mask Interrupt A Register (toggle) */
-#define FIO_MASKB_D 0xFFC00720 /* Flag Mask Interrupt B Register (set directly) */
-#define FIO_MASKB_C 0xFFC00724 /* Flag Mask Interrupt B Register (clear) */
-#define FIO_MASKB_S 0xFFC00728 /* Flag Mask Interrupt B Register (set) */
-#define FIO_MASKB_T 0xFFC0072C /* Flag Mask Interrupt B Register (toggle) */
-#define FIO_DIR 0xFFC00730 /* Peripheral Flag Direction Register */
-#define FIO_POLAR 0xFFC00734 /* Flag Source Polarity Register */
-#define FIO_EDGE 0xFFC00738 /* Flag Source Sensitivity Register */
-#define FIO_BOTH 0xFFC0073C /* Flag Set on BOTH Edges Register */
-#define FIO_INEN 0xFFC00740 /* Flag Input Enable Register */
-
-/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
-#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
-#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
-#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
-#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
-#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
-#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
-#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
-#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
-#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
-#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
-#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
-#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
-#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
-#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
-#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
-#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
-#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
-#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
-
-/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
-#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
-#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
-#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
-#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
-#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
-#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
-#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
-#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
-#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
-#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
-#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
-#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
-#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
-#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
-#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
-#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
-#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
-#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
-
-/* Asynchronous Memory Controller - External Bus Interface Unit */
-#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
-#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
-#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
-
-/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
-
-#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
-#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
-#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
-#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
-
-/* DMA Traffic controls */
-#define DMAC_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */
-#define DMAC_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */
-
-/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
-#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
-#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
-#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
-#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
-#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
-#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
-#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
-#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
-#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
-#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
-#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
-#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
-#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
-
-#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
-#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
-#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
-#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
-#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
-#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
-#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
-#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
-#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
-#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
-#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
-#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
-#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
-
-#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
-#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
-#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
-#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
-#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
-#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
-#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
-#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
-#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
-#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
-#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
-#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
-#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
-
-#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
-#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
-#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
-#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
-#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
-#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
-#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
-#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
-#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
-#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
-#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
-#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
-#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
-
-#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
-#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
-#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
-#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
-#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
-#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
-#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
-#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
-#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
-#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
-#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
-#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
-#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
-
-#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
-#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
-#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
-#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
-#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
-#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
-#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
-#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
-#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
-#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
-#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
-#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
-#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
-
-#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
-#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
-#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
-#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
-#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
-#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
-#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
-#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
-#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
-#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
-#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
-#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
-#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
-
-#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
-#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
-#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
-#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
-#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
-#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
-#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
-#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
-#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
-#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
-#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
-#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
-#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
-
-#define MDMA_D1_CONFIG 0xFFC00E88 /* MemDMA Stream 1 Destination Configuration Register */
-#define MDMA_D1_NEXT_DESC_PTR 0xFFC00E80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
-#define MDMA_D1_START_ADDR 0xFFC00E84 /* MemDMA Stream 1 Destination Start Address Register */
-#define MDMA_D1_X_COUNT 0xFFC00E90 /* MemDMA Stream 1 Destination X Count Register */
-#define MDMA_D1_Y_COUNT 0xFFC00E98 /* MemDMA Stream 1 Destination Y Count Register */
-#define MDMA_D1_X_MODIFY 0xFFC00E94 /* MemDMA Stream 1 Destination X Modify Register */
-#define MDMA_D1_Y_MODIFY 0xFFC00E9C /* MemDMA Stream 1 Destination Y Modify Register */
-#define MDMA_D1_CURR_DESC_PTR 0xFFC00EA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
-#define MDMA_D1_CURR_ADDR 0xFFC00EA4 /* MemDMA Stream 1 Destination Current Address Register */
-#define MDMA_D1_CURR_X_COUNT 0xFFC00EB0 /* MemDMA Stream 1 Destination Current X Count Register */
-#define MDMA_D1_CURR_Y_COUNT 0xFFC00EB8 /* MemDMA Stream 1 Destination Current Y Count Register */
-#define MDMA_D1_IRQ_STATUS 0xFFC00EA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */
-#define MDMA_D1_PERIPHERAL_MAP 0xFFC00EAC /* MemDMA Stream 1 Destination Peripheral Map Register */
-
-#define MDMA_S1_CONFIG 0xFFC00EC8 /* MemDMA Stream 1 Source Configuration Register */
-#define MDMA_S1_NEXT_DESC_PTR 0xFFC00EC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
-#define MDMA_S1_START_ADDR 0xFFC00EC4 /* MemDMA Stream 1 Source Start Address Register */
-#define MDMA_S1_X_COUNT 0xFFC00ED0 /* MemDMA Stream 1 Source X Count Register */
-#define MDMA_S1_Y_COUNT 0xFFC00ED8 /* MemDMA Stream 1 Source Y Count Register */
-#define MDMA_S1_X_MODIFY 0xFFC00ED4 /* MemDMA Stream 1 Source X Modify Register */
-#define MDMA_S1_Y_MODIFY 0xFFC00EDC /* MemDMA Stream 1 Source Y Modify Register */
-#define MDMA_S1_CURR_DESC_PTR 0xFFC00EE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
-#define MDMA_S1_CURR_ADDR 0xFFC00EE4 /* MemDMA Stream 1 Source Current Address Register */
-#define MDMA_S1_CURR_X_COUNT 0xFFC00EF0 /* MemDMA Stream 1 Source Current X Count Register */
-#define MDMA_S1_CURR_Y_COUNT 0xFFC00EF8 /* MemDMA Stream 1 Source Current Y Count Register */
-#define MDMA_S1_IRQ_STATUS 0xFFC00EE8 /* MemDMA Stream 1 Source Interrupt/Status Register */
-#define MDMA_S1_PERIPHERAL_MAP 0xFFC00EEC /* MemDMA Stream 1 Source Peripheral Map Register */
-
-#define MDMA_D0_CONFIG 0xFFC00E08 /* MemDMA Stream 0 Destination Configuration Register */
-#define MDMA_D0_NEXT_DESC_PTR 0xFFC00E00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
-#define MDMA_D0_START_ADDR 0xFFC00E04 /* MemDMA Stream 0 Destination Start Address Register */
-#define MDMA_D0_X_COUNT 0xFFC00E10 /* MemDMA Stream 0 Destination X Count Register */
-#define MDMA_D0_Y_COUNT 0xFFC00E18 /* MemDMA Stream 0 Destination Y Count Register */
-#define MDMA_D0_X_MODIFY 0xFFC00E14 /* MemDMA Stream 0 Destination X Modify Register */
-#define MDMA_D0_Y_MODIFY 0xFFC00E1C /* MemDMA Stream 0 Destination Y Modify Register */
-#define MDMA_D0_CURR_DESC_PTR 0xFFC00E20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
-#define MDMA_D0_CURR_ADDR 0xFFC00E24 /* MemDMA Stream 0 Destination Current Address Register */
-#define MDMA_D0_CURR_X_COUNT 0xFFC00E30 /* MemDMA Stream 0 Destination Current X Count Register */
-#define MDMA_D0_CURR_Y_COUNT 0xFFC00E38 /* MemDMA Stream 0 Destination Current Y Count Register */
-#define MDMA_D0_IRQ_STATUS 0xFFC00E28 /* MemDMA Stream 0 Destination Interrupt/Status Register */
-#define MDMA_D0_PERIPHERAL_MAP 0xFFC00E2C /* MemDMA Stream 0 Destination Peripheral Map Register */
-
-#define MDMA_S0_CONFIG 0xFFC00E48 /* MemDMA Stream 0 Source Configuration Register */
-#define MDMA_S0_NEXT_DESC_PTR 0xFFC00E40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
-#define MDMA_S0_START_ADDR 0xFFC00E44 /* MemDMA Stream 0 Source Start Address Register */
-#define MDMA_S0_X_COUNT 0xFFC00E50 /* MemDMA Stream 0 Source X Count Register */
-#define MDMA_S0_Y_COUNT 0xFFC00E58 /* MemDMA Stream 0 Source Y Count Register */
-#define MDMA_S0_X_MODIFY 0xFFC00E54 /* MemDMA Stream 0 Source X Modify Register */
-#define MDMA_S0_Y_MODIFY 0xFFC00E5C /* MemDMA Stream 0 Source Y Modify Register */
-#define MDMA_S0_CURR_DESC_PTR 0xFFC00E60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
-#define MDMA_S0_CURR_ADDR 0xFFC00E64 /* MemDMA Stream 0 Source Current Address Register */
-#define MDMA_S0_CURR_X_COUNT 0xFFC00E70 /* MemDMA Stream 0 Source Current X Count Register */
-#define MDMA_S0_CURR_Y_COUNT 0xFFC00E78 /* MemDMA Stream 0 Source Current Y Count Register */
-#define MDMA_S0_IRQ_STATUS 0xFFC00E68 /* MemDMA Stream 0 Source Interrupt/Status Register */
-#define MDMA_S0_PERIPHERAL_MAP 0xFFC00E6C /* MemDMA Stream 0 Source Peripheral Map Register */
-
-/* Parallel Peripheral Interface (PPI) (0xFFC01000 - 0xFFC010FF) */
-
-#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */
-#define PPI_STATUS 0xFFC01004 /* PPI Status Register */
-#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */
-#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */
-#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
-
-/*********************************************************************************** */
-/* System MMR Register Bits */
-/******************************************************************************* */
-
-/* CHIPID Masks */
-#define CHIPID_VERSION 0xF0000000
-#define CHIPID_FAMILY 0x0FFFF000
-#define CHIPID_MANUFACTURE 0x00000FFE
-
-/* SWRST Mask */
-#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
-#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
-#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
-#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
-#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
-
-/* SYSCR Masks */
-#define BMODE 0x0006 /* Boot Mode - Latched During HW Reset From Mode Pins */
-#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
-
-/* ************* SYSTEM INTERRUPT CONTROLLER MASKS ***************** */
-
- /* SIC_IAR0 Masks */
-
-#define P0_IVG(x) ((x)-7) /* Peripheral #0 assigned IVG #x */
-#define P1_IVG(x) ((x)-7) << 0x4 /* Peripheral #1 assigned IVG #x */
-#define P2_IVG(x) ((x)-7) << 0x8 /* Peripheral #2 assigned IVG #x */
-#define P3_IVG(x) ((x)-7) << 0xC /* Peripheral #3 assigned IVG #x */
-#define P4_IVG(x) ((x)-7) << 0x10 /* Peripheral #4 assigned IVG #x */
-#define P5_IVG(x) ((x)-7) << 0x14 /* Peripheral #5 assigned IVG #x */
-#define P6_IVG(x) ((x)-7) << 0x18 /* Peripheral #6 assigned IVG #x */
-#define P7_IVG(x) ((x)-7) << 0x1C /* Peripheral #7 assigned IVG #x */
-
-/* SIC_IAR1 Masks */
-
-#define P8_IVG(x) ((x)-7) /* Peripheral #8 assigned IVG #x */
-#define P9_IVG(x) ((x)-7) << 0x4 /* Peripheral #9 assigned IVG #x */
-#define P10_IVG(x) ((x)-7) << 0x8 /* Peripheral #10 assigned IVG #x */
-#define P11_IVG(x) ((x)-7) << 0xC /* Peripheral #11 assigned IVG #x */
-#define P12_IVG(x) ((x)-7) << 0x10 /* Peripheral #12 assigned IVG #x */
-#define P13_IVG(x) ((x)-7) << 0x14 /* Peripheral #13 assigned IVG #x */
-#define P14_IVG(x) ((x)-7) << 0x18 /* Peripheral #14 assigned IVG #x */
-#define P15_IVG(x) ((x)-7) << 0x1C /* Peripheral #15 assigned IVG #x */
-
-/* SIC_IAR2 Masks */
-#define P16_IVG(x) ((x)-7) /* Peripheral #16 assigned IVG #x */
-#define P17_IVG(x) ((x)-7) << 0x4 /* Peripheral #17 assigned IVG #x */
-#define P18_IVG(x) ((x)-7) << 0x8 /* Peripheral #18 assigned IVG #x */
-#define P19_IVG(x) ((x)-7) << 0xC /* Peripheral #19 assigned IVG #x */
-#define P20_IVG(x) ((x)-7) << 0x10 /* Peripheral #20 assigned IVG #x */
-#define P21_IVG(x) ((x)-7) << 0x14 /* Peripheral #21 assigned IVG #x */
-#define P22_IVG(x) ((x)-7) << 0x18 /* Peripheral #22 assigned IVG #x */
-#define P23_IVG(x) ((x)-7) << 0x1C /* Peripheral #23 assigned IVG #x */
-
-/* SIC_IMASK Masks */
-#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
-#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
-#define SIC_MASK(x) (1 << (x)) /* Mask Peripheral #x interrupt */
-#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */
-
-/* SIC_IWR Masks */
-#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
-#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
-#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */
-#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */
-
-/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */
-
-/* PPI_CONTROL Masks */
-#define PORT_EN 0x00000001 /* PPI Port Enable */
-#define PORT_DIR 0x00000002 /* PPI Port Direction */
-#define XFR_TYPE 0x0000000C /* PPI Transfer Type */
-#define PORT_CFG 0x00000030 /* PPI Port Configuration */
-#define FLD_SEL 0x00000040 /* PPI Active Field Select */
-#define PACK_EN 0x00000080 /* PPI Packing Mode */
-#define DMA32 0x00000100 /* PPI 32-bit DMA Enable */
-#define SKIP_EN 0x00000200 /* PPI Skip Element Enable */
-#define SKIP_EO 0x00000400 /* PPI Skip Even/Odd Elements */
-#define DLENGTH 0x00003800 /* PPI Data Length */
-#define DLEN_8 0x0000 /* Data Length = 8 Bits */
-#define DLEN_10 0x0800 /* Data Length = 10 Bits */
-#define DLEN_11 0x1000 /* Data Length = 11 Bits */
-#define DLEN_12 0x1800 /* Data Length = 12 Bits */
-#define DLEN_13 0x2000 /* Data Length = 13 Bits */
-#define DLEN_14 0x2800 /* Data Length = 14 Bits */
-#define DLEN_15 0x3000 /* Data Length = 15 Bits */
-#define DLEN_16 0x3800 /* Data Length = 16 Bits */
-#define DLEN(x) (((x-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */
-#define POL 0x0000C000 /* PPI Signal Polarities */
-#define POLC 0x4000 /* PPI Clock Polarity */
-#define POLS 0x8000 /* PPI Frame Sync Polarity */
-
-/* PPI_STATUS Masks */
-#define FLD 0x00000400 /* Field Indicator */
-#define FT_ERR 0x00000800 /* Frame Track Error */
-#define OVR 0x00001000 /* FIFO Overflow Error */
-#define UNDR 0x00002000 /* FIFO Underrun Error */
-#define ERR_DET 0x00004000 /* Error Detected Indicator */
-#define ERR_NCOR 0x00008000 /* Error Not Corrected Indicator */
-
-/* ********** DMA CONTROLLER MASKS *********************8 */
-
-/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
-
-#define CTYPE 0x00000040 /* DMA Channel Type Indicator */
-#define CTYPE_P 6 /* DMA Channel Type Indicator BIT POSITION */
-#define PCAP8 0x00000080 /* DMA 8-bit Operation Indicator */
-#define PCAP16 0x00000100 /* DMA 16-bit Operation Indicator */
-#define PCAP32 0x00000200 /* DMA 32-bit Operation Indicator */
-#define PCAPWR 0x00000400 /* DMA Write Operation Indicator */
-#define PCAPRD 0x00000800 /* DMA Read Operation Indicator */
-#define PMAP 0x00007000 /* DMA Peripheral Map Field */
-
-#define PMAP_PPI 0x0000 /* PMAP PPI Port DMA */
-#define PMAP_SPORT0RX 0x1000 /* PMAP SPORT0 Receive DMA */
-#define PMAP_SPORT0TX 0x2000 /* PMAP SPORT0 Transmit DMA */
-#define PMAP_SPORT1RX 0x3000 /* PMAP SPORT1 Receive DMA */
-#define PMAP_SPORT1TX 0x4000 /* PMAP SPORT1 Transmit DMA */
-#define PMAP_SPI 0x5000 /* PMAP SPI DMA */
-#define PMAP_UARTRX 0x6000 /* PMAP UART Receive DMA */
-#define PMAP_UARTTX 0x7000 /* PMAP UART Transmit DMA */
-
-/* ************* GENERAL PURPOSE TIMER MASKS ******************** */
-
-/* PWM Timer bit definitions */
-
-/* TIMER_ENABLE Register */
-#define TIMEN0 0x0001
-#define TIMEN1 0x0002
-#define TIMEN2 0x0004
-
-#define TIMEN0_P 0x00
-#define TIMEN1_P 0x01
-#define TIMEN2_P 0x02
-
-/* TIMER_DISABLE Register */
-#define TIMDIS0 0x0001
-#define TIMDIS1 0x0002
-#define TIMDIS2 0x0004
-
-#define TIMDIS0_P 0x00
-#define TIMDIS1_P 0x01
-#define TIMDIS2_P 0x02
-
-/* TIMER_STATUS Register */
-#define TIMIL0 0x0001
-#define TIMIL1 0x0002
-#define TIMIL2 0x0004
-#define TOVF_ERR0 0x0010 /* Timer 0 Counter Overflow */
-#define TOVF_ERR1 0x0020 /* Timer 1 Counter Overflow */
-#define TOVF_ERR2 0x0040 /* Timer 2 Counter Overflow */
-#define TRUN0 0x1000
-#define TRUN1 0x2000
-#define TRUN2 0x4000
-
-#define TIMIL0_P 0x00
-#define TIMIL1_P 0x01
-#define TIMIL2_P 0x02
-#define TOVF_ERR0_P 0x04
-#define TOVF_ERR1_P 0x05
-#define TOVF_ERR2_P 0x06
-#define TRUN0_P 0x0C
-#define TRUN1_P 0x0D
-#define TRUN2_P 0x0E
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define TOVL_ERR0 TOVF_ERR0
-#define TOVL_ERR1 TOVF_ERR1
-#define TOVL_ERR2 TOVF_ERR2
-#define TOVL_ERR0_P TOVF_ERR0_P
-#define TOVL_ERR1_P TOVF_ERR1_P
-#define TOVL_ERR2_P TOVF_ERR2_P
-
-/* TIMERx_CONFIG Registers */
-#define PWM_OUT 0x0001
-#define WDTH_CAP 0x0002
-#define EXT_CLK 0x0003
-#define PULSE_HI 0x0004
-#define PERIOD_CNT 0x0008
-#define IRQ_ENA 0x0010
-#define TIN_SEL 0x0020
-#define OUT_DIS 0x0040
-#define CLK_SEL 0x0080
-#define TOGGLE_HI 0x0100
-#define EMU_RUN 0x0200
-#define ERR_TYP(x) ((x & 0x03) << 14)
-
-#define TMODE_P0 0x00
-#define TMODE_P1 0x01
-#define PULSE_HI_P 0x02
-#define PERIOD_CNT_P 0x03
-#define IRQ_ENA_P 0x04
-#define TIN_SEL_P 0x05
-#define OUT_DIS_P 0x06
-#define CLK_SEL_P 0x07
-#define TOGGLE_HI_P 0x08
-#define EMU_RUN_P 0x09
-#define ERR_TYP_P0 0x0E
-#define ERR_TYP_P1 0x0F
-
-/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */
-
-/* AMGCTL Masks */
-#define AMCKEN 0x00000001 /* Enable CLKOUT */
-#define AMBEN_NONE 0x00000000 /* All Banks Disabled */
-#define AMBEN_B0 0x00000002 /* Enable Asynchronous Memory Bank 0 only */
-#define AMBEN_B0_B1 0x00000004 /* Enable Asynchronous Memory Banks 0 & 1 only */
-#define AMBEN_B0_B1_B2 0x00000006 /* Enable Asynchronous Memory Banks 0, 1, and 2 */
-#define AMBEN_ALL 0x00000008 /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */
-
-/* AMGCTL Bit Positions */
-#define AMCKEN_P 0x00000000 /* Enable CLKOUT */
-#define AMBEN_P0 0x00000001 /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */
-#define AMBEN_P1 0x00000002 /* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 enabled */
-#define AMBEN_P2 0x00000003 /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */
-
-/* AMBCTL0 Masks */
-#define B0RDYEN 0x00000001 /* Bank 0 RDY Enable, 0=disable, 1=enable */
-#define B0RDYPOL 0x00000002 /* Bank 0 RDY Active high, 0=active low, 1=active high */
-#define B0TT_1 0x00000004 /* Bank 0 Transition Time from Read to Write = 1 cycle */
-#define B0TT_2 0x00000008 /* Bank 0 Transition Time from Read to Write = 2 cycles */
-#define B0TT_3 0x0000000C /* Bank 0 Transition Time from Read to Write = 3 cycles */
-#define B0TT_4 0x00000000 /* Bank 0 Transition Time from Read to Write = 4 cycles */
-#define B0ST_1 0x00000010 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */
-#define B0ST_2 0x00000020 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */
-#define B0ST_3 0x00000030 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */
-#define B0ST_4 0x00000000 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */
-#define B0HT_1 0x00000040 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */
-#define B0HT_2 0x00000080 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */
-#define B0HT_3 0x000000C0 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */
-#define B0HT_0 0x00000000 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */
-#define B0RAT_1 0x00000100 /* Bank 0 Read Access Time = 1 cycle */
-#define B0RAT_2 0x00000200 /* Bank 0 Read Access Time = 2 cycles */
-#define B0RAT_3 0x00000300 /* Bank 0 Read Access Time = 3 cycles */
-#define B0RAT_4 0x00000400 /* Bank 0 Read Access Time = 4 cycles */
-#define B0RAT_5 0x00000500 /* Bank 0 Read Access Time = 5 cycles */
-#define B0RAT_6 0x00000600 /* Bank 0 Read Access Time = 6 cycles */
-#define B0RAT_7 0x00000700 /* Bank 0 Read Access Time = 7 cycles */
-#define B0RAT_8 0x00000800 /* Bank 0 Read Access Time = 8 cycles */
-#define B0RAT_9 0x00000900 /* Bank 0 Read Access Time = 9 cycles */
-#define B0RAT_10 0x00000A00 /* Bank 0 Read Access Time = 10 cycles */
-#define B0RAT_11 0x00000B00 /* Bank 0 Read Access Time = 11 cycles */
-#define B0RAT_12 0x00000C00 /* Bank 0 Read Access Time = 12 cycles */
-#define B0RAT_13 0x00000D00 /* Bank 0 Read Access Time = 13 cycles */
-#define B0RAT_14 0x00000E00 /* Bank 0 Read Access Time = 14 cycles */
-#define B0RAT_15 0x00000F00 /* Bank 0 Read Access Time = 15 cycles */
-#define B0WAT_1 0x00001000 /* Bank 0 Write Access Time = 1 cycle */
-#define B0WAT_2 0x00002000 /* Bank 0 Write Access Time = 2 cycles */
-#define B0WAT_3 0x00003000 /* Bank 0 Write Access Time = 3 cycles */
-#define B0WAT_4 0x00004000 /* Bank 0 Write Access Time = 4 cycles */
-#define B0WAT_5 0x00005000 /* Bank 0 Write Access Time = 5 cycles */
-#define B0WAT_6 0x00006000 /* Bank 0 Write Access Time = 6 cycles */
-#define B0WAT_7 0x00007000 /* Bank 0 Write Access Time = 7 cycles */
-#define B0WAT_8 0x00008000 /* Bank 0 Write Access Time = 8 cycles */
-#define B0WAT_9 0x00009000 /* Bank 0 Write Access Time = 9 cycles */
-#define B0WAT_10 0x0000A000 /* Bank 0 Write Access Time = 10 cycles */
-#define B0WAT_11 0x0000B000 /* Bank 0 Write Access Time = 11 cycles */
-#define B0WAT_12 0x0000C000 /* Bank 0 Write Access Time = 12 cycles */
-#define B0WAT_13 0x0000D000 /* Bank 0 Write Access Time = 13 cycles */
-#define B0WAT_14 0x0000E000 /* Bank 0 Write Access Time = 14 cycles */
-#define B0WAT_15 0x0000F000 /* Bank 0 Write Access Time = 15 cycles */
-#define B1RDYEN 0x00010000 /* Bank 1 RDY enable, 0=disable, 1=enable */
-#define B1RDYPOL 0x00020000 /* Bank 1 RDY Active high, 0=active low, 1=active high */
-#define B1TT_1 0x00040000 /* Bank 1 Transition Time from Read to Write = 1 cycle */
-#define B1TT_2 0x00080000 /* Bank 1 Transition Time from Read to Write = 2 cycles */
-#define B1TT_3 0x000C0000 /* Bank 1 Transition Time from Read to Write = 3 cycles */
-#define B1TT_4 0x00000000 /* Bank 1 Transition Time from Read to Write = 4 cycles */
-#define B1ST_1 0x00100000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B1ST_2 0x00200000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B1ST_3 0x00300000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B1ST_4 0x00000000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B1HT_1 0x00400000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B1HT_2 0x00800000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B1HT_3 0x00C00000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B1HT_0 0x00000000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B1RAT_1 0x01000000 /* Bank 1 Read Access Time = 1 cycle */
-#define B1RAT_2 0x02000000 /* Bank 1 Read Access Time = 2 cycles */
-#define B1RAT_3 0x03000000 /* Bank 1 Read Access Time = 3 cycles */
-#define B1RAT_4 0x04000000 /* Bank 1 Read Access Time = 4 cycles */
-#define B1RAT_5 0x05000000 /* Bank 1 Read Access Time = 5 cycles */
-#define B1RAT_6 0x06000000 /* Bank 1 Read Access Time = 6 cycles */
-#define B1RAT_7 0x07000000 /* Bank 1 Read Access Time = 7 cycles */
-#define B1RAT_8 0x08000000 /* Bank 1 Read Access Time = 8 cycles */
-#define B1RAT_9 0x09000000 /* Bank 1 Read Access Time = 9 cycles */
-#define B1RAT_10 0x0A000000 /* Bank 1 Read Access Time = 10 cycles */
-#define B1RAT_11 0x0B000000 /* Bank 1 Read Access Time = 11 cycles */
-#define B1RAT_12 0x0C000000 /* Bank 1 Read Access Time = 12 cycles */
-#define B1RAT_13 0x0D000000 /* Bank 1 Read Access Time = 13 cycles */
-#define B1RAT_14 0x0E000000 /* Bank 1 Read Access Time = 14 cycles */
-#define B1RAT_15 0x0F000000 /* Bank 1 Read Access Time = 15 cycles */
-#define B1WAT_1 0x10000000 /* Bank 1 Write Access Time = 1 cycle */
-#define B1WAT_2 0x20000000 /* Bank 1 Write Access Time = 2 cycles */
-#define B1WAT_3 0x30000000 /* Bank 1 Write Access Time = 3 cycles */
-#define B1WAT_4 0x40000000 /* Bank 1 Write Access Time = 4 cycles */
-#define B1WAT_5 0x50000000 /* Bank 1 Write Access Time = 5 cycles */
-#define B1WAT_6 0x60000000 /* Bank 1 Write Access Time = 6 cycles */
-#define B1WAT_7 0x70000000 /* Bank 1 Write Access Time = 7 cycles */
-#define B1WAT_8 0x80000000 /* Bank 1 Write Access Time = 8 cycles */
-#define B1WAT_9 0x90000000 /* Bank 1 Write Access Time = 9 cycles */
-#define B1WAT_10 0xA0000000 /* Bank 1 Write Access Time = 10 cycles */
-#define B1WAT_11 0xB0000000 /* Bank 1 Write Access Time = 11 cycles */
-#define B1WAT_12 0xC0000000 /* Bank 1 Write Access Time = 12 cycles */
-#define B1WAT_13 0xD0000000 /* Bank 1 Write Access Time = 13 cycles */
-#define B1WAT_14 0xE0000000 /* Bank 1 Write Access Time = 14 cycles */
-#define B1WAT_15 0xF0000000 /* Bank 1 Write Access Time = 15 cycles */
-
-/* AMBCTL1 Masks */
-#define B2RDYEN 0x00000001 /* Bank 2 RDY Enable, 0=disable, 1=enable */
-#define B2RDYPOL 0x00000002 /* Bank 2 RDY Active high, 0=active low, 1=active high */
-#define B2TT_1 0x00000004 /* Bank 2 Transition Time from Read to Write = 1 cycle */
-#define B2TT_2 0x00000008 /* Bank 2 Transition Time from Read to Write = 2 cycles */
-#define B2TT_3 0x0000000C /* Bank 2 Transition Time from Read to Write = 3 cycles */
-#define B2TT_4 0x00000000 /* Bank 2 Transition Time from Read to Write = 4 cycles */
-#define B2ST_1 0x00000010 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B2ST_2 0x00000020 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B2ST_3 0x00000030 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B2ST_4 0x00000000 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B2HT_1 0x00000040 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B2HT_2 0x00000080 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B2HT_3 0x000000C0 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B2HT_0 0x00000000 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B2RAT_1 0x00000100 /* Bank 2 Read Access Time = 1 cycle */
-#define B2RAT_2 0x00000200 /* Bank 2 Read Access Time = 2 cycles */
-#define B2RAT_3 0x00000300 /* Bank 2 Read Access Time = 3 cycles */
-#define B2RAT_4 0x00000400 /* Bank 2 Read Access Time = 4 cycles */
-#define B2RAT_5 0x00000500 /* Bank 2 Read Access Time = 5 cycles */
-#define B2RAT_6 0x00000600 /* Bank 2 Read Access Time = 6 cycles */
-#define B2RAT_7 0x00000700 /* Bank 2 Read Access Time = 7 cycles */
-#define B2RAT_8 0x00000800 /* Bank 2 Read Access Time = 8 cycles */
-#define B2RAT_9 0x00000900 /* Bank 2 Read Access Time = 9 cycles */
-#define B2RAT_10 0x00000A00 /* Bank 2 Read Access Time = 10 cycles */
-#define B2RAT_11 0x00000B00 /* Bank 2 Read Access Time = 11 cycles */
-#define B2RAT_12 0x00000C00 /* Bank 2 Read Access Time = 12 cycles */
-#define B2RAT_13 0x00000D00 /* Bank 2 Read Access Time = 13 cycles */
-#define B2RAT_14 0x00000E00 /* Bank 2 Read Access Time = 14 cycles */
-#define B2RAT_15 0x00000F00 /* Bank 2 Read Access Time = 15 cycles */
-#define B2WAT_1 0x00001000 /* Bank 2 Write Access Time = 1 cycle */
-#define B2WAT_2 0x00002000 /* Bank 2 Write Access Time = 2 cycles */
-#define B2WAT_3 0x00003000 /* Bank 2 Write Access Time = 3 cycles */
-#define B2WAT_4 0x00004000 /* Bank 2 Write Access Time = 4 cycles */
-#define B2WAT_5 0x00005000 /* Bank 2 Write Access Time = 5 cycles */
-#define B2WAT_6 0x00006000 /* Bank 2 Write Access Time = 6 cycles */
-#define B2WAT_7 0x00007000 /* Bank 2 Write Access Time = 7 cycles */
-#define B2WAT_8 0x00008000 /* Bank 2 Write Access Time = 8 cycles */
-#define B2WAT_9 0x00009000 /* Bank 2 Write Access Time = 9 cycles */
-#define B2WAT_10 0x0000A000 /* Bank 2 Write Access Time = 10 cycles */
-#define B2WAT_11 0x0000B000 /* Bank 2 Write Access Time = 11 cycles */
-#define B2WAT_12 0x0000C000 /* Bank 2 Write Access Time = 12 cycles */
-#define B2WAT_13 0x0000D000 /* Bank 2 Write Access Time = 13 cycles */
-#define B2WAT_14 0x0000E000 /* Bank 2 Write Access Time = 14 cycles */
-#define B2WAT_15 0x0000F000 /* Bank 2 Write Access Time = 15 cycles */
-#define B3RDYEN 0x00010000 /* Bank 3 RDY enable, 0=disable, 1=enable */
-#define B3RDYPOL 0x00020000 /* Bank 3 RDY Active high, 0=active low, 1=active high */
-#define B3TT_1 0x00040000 /* Bank 3 Transition Time from Read to Write = 1 cycle */
-#define B3TT_2 0x00080000 /* Bank 3 Transition Time from Read to Write = 2 cycles */
-#define B3TT_3 0x000C0000 /* Bank 3 Transition Time from Read to Write = 3 cycles */
-#define B3TT_4 0x00000000 /* Bank 3 Transition Time from Read to Write = 4 cycles */
-#define B3ST_1 0x00100000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B3ST_2 0x00200000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B3ST_3 0x00300000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B3ST_4 0x00000000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B3HT_1 0x00400000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B3HT_2 0x00800000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B3HT_3 0x00C00000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B3HT_0 0x00000000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B3RAT_1 0x01000000 /* Bank 3 Read Access Time = 1 cycle */
-#define B3RAT_2 0x02000000 /* Bank 3 Read Access Time = 2 cycles */
-#define B3RAT_3 0x03000000 /* Bank 3 Read Access Time = 3 cycles */
-#define B3RAT_4 0x04000000 /* Bank 3 Read Access Time = 4 cycles */
-#define B3RAT_5 0x05000000 /* Bank 3 Read Access Time = 5 cycles */
-#define B3RAT_6 0x06000000 /* Bank 3 Read Access Time = 6 cycles */
-#define B3RAT_7 0x07000000 /* Bank 3 Read Access Time = 7 cycles */
-#define B3RAT_8 0x08000000 /* Bank 3 Read Access Time = 8 cycles */
-#define B3RAT_9 0x09000000 /* Bank 3 Read Access Time = 9 cycles */
-#define B3RAT_10 0x0A000000 /* Bank 3 Read Access Time = 10 cycles */
-#define B3RAT_11 0x0B000000 /* Bank 3 Read Access Time = 11 cycles */
-#define B3RAT_12 0x0C000000 /* Bank 3 Read Access Time = 12 cycles */
-#define B3RAT_13 0x0D000000 /* Bank 3 Read Access Time = 13 cycles */
-#define B3RAT_14 0x0E000000 /* Bank 3 Read Access Time = 14 cycles */
-#define B3RAT_15 0x0F000000 /* Bank 3 Read Access Time = 15 cycles */
-#define B3WAT_1 0x10000000 /* Bank 3 Write Access Time = 1 cycle */
-#define B3WAT_2 0x20000000 /* Bank 3 Write Access Time = 2 cycles */
-#define B3WAT_3 0x30000000 /* Bank 3 Write Access Time = 3 cycles */
-#define B3WAT_4 0x40000000 /* Bank 3 Write Access Time = 4 cycles */
-#define B3WAT_5 0x50000000 /* Bank 3 Write Access Time = 5 cycles */
-#define B3WAT_6 0x60000000 /* Bank 3 Write Access Time = 6 cycles */
-#define B3WAT_7 0x70000000 /* Bank 3 Write Access Time = 7 cycles */
-#define B3WAT_8 0x80000000 /* Bank 3 Write Access Time = 8 cycles */
-#define B3WAT_9 0x90000000 /* Bank 3 Write Access Time = 9 cycles */
-#define B3WAT_10 0xA0000000 /* Bank 3 Write Access Time = 10 cycles */
-#define B3WAT_11 0xB0000000 /* Bank 3 Write Access Time = 11 cycles */
-#define B3WAT_12 0xC0000000 /* Bank 3 Write Access Time = 12 cycles */
-#define B3WAT_13 0xD0000000 /* Bank 3 Write Access Time = 13 cycles */
-#define B3WAT_14 0xE0000000 /* Bank 3 Write Access Time = 14 cycles */
-#define B3WAT_15 0xF0000000 /* Bank 3 Write Access Time = 15 cycles */
-
-/* ********************** SDRAM CONTROLLER MASKS *************************** */
-
-/* SDGCTL Masks */
-#define SCTLE 0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */
-#define CL_2 0x00000008 /* SDRAM CAS latency = 2 cycles */
-#define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */
-#define PFE 0x00000010 /* Enable SDRAM prefetch */
-#define PFP 0x00000020 /* Prefetch has priority over AMC requests */
-#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
-#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
-#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
-#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
-#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
-#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
-#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
-#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
-#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
-#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
-#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
-#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
-#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
-#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
-#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
-#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
-#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
-#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
-#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
-#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
-#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
-#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
-#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
-#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
-#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
-#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
-#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
-#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
-#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
-#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
-#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
-#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
-#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
-#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
-#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
-#define PUPSD 0x00200000 /*Power-up start delay */
-#define PSM 0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */
-#define PSS 0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */
-#define SRFS 0x01000000 /* Start SDRAM self-refresh mode */
-#define EBUFE 0x02000000 /* Enable external buffering timing */
-#define FBBRW 0x04000000 /* Fast back-to-back read write enable */
-#define EMREN 0x10000000 /* Extended mode register enable */
-#define TCSR 0x20000000 /* Temp compensated self refresh value 85 deg C */
-#define CDDBG 0x40000000 /* Tristate SDRAM controls during bus grant */
-
-/* EBIU_SDBCTL Masks */
-#define EBE 0x00000001 /* Enable SDRAM external bank */
-#define EBSZ_16 0x00000000 /* SDRAM external bank size = 16MB */
-#define EBSZ_32 0x00000002 /* SDRAM external bank size = 32MB */
-#define EBSZ_64 0x00000004 /* SDRAM external bank size = 64MB */
-#define EBSZ_128 0x00000006 /* SDRAM external bank size = 128MB */
-#define EBCAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */
-#define EBCAW_9 0x00000010 /* SDRAM external bank column address width = 9 bits */
-#define EBCAW_10 0x00000020 /* SDRAM external bank column address width = 9 bits */
-#define EBCAW_11 0x00000030 /* SDRAM external bank column address width = 9 bits */
-
-/* EBIU_SDSTAT Masks */
-#define SDCI 0x00000001 /* SDRAM controller is idle */
-#define SDSRA 0x00000002 /* SDRAM SDRAM self refresh is active */
-#define SDPUA 0x00000004 /* SDRAM power up active */
-#define SDRS 0x00000008 /* SDRAM is in reset state */
-#define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */
-#define BGSTAT 0x00000020 /* Bus granted */
-
-
-#endif /* _DEF_BF532_H */
+++ /dev/null
-/* mach/dma.h - arch-specific DMA defines
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_DMA_H_
-#define _MACH_DMA_H_
-
-#define MAX_DMA_CHANNELS 12
-
-#define CH_PPI 0
-#define CH_SPORT0_RX 1
-#define CH_SPORT0_TX 2
-#define CH_SPORT1_RX 3
-#define CH_SPORT1_TX 4
-#define CH_SPI 5
-#define CH_UART0_RX 6
-#define CH_UART0_TX 7
-#define CH_MEM_STREAM0_DEST 8 /* TX */
-#define CH_MEM_STREAM0_SRC 9 /* RX */
-#define CH_MEM_STREAM1_DEST 10 /* TX */
-#define CH_MEM_STREAM1_SRC 11 /* RX */
-
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2008 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-
-#ifndef _MACH_GPIO_H_
-#define _MACH_GPIO_H_
-
-#define MAX_BLACKFIN_GPIOS 16
-
-#define GPIO_PF0 0
-#define GPIO_PF1 1
-#define GPIO_PF2 2
-#define GPIO_PF3 3
-#define GPIO_PF4 4
-#define GPIO_PF5 5
-#define GPIO_PF6 6
-#define GPIO_PF7 7
-#define GPIO_PF8 8
-#define GPIO_PF9 9
-#define GPIO_PF10 10
-#define GPIO_PF11 11
-#define GPIO_PF12 12
-#define GPIO_PF13 13
-#define GPIO_PF14 14
-#define GPIO_PF15 15
-
-#define PORT_F GPIO_PF0
-
-#include <mach-common/ports-f.h>
-
-#endif /* _MACH_GPIO_H_ */
+++ /dev/null
-/*
- * Copyright 2005-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _BF533_IRQ_H_
-#define _BF533_IRQ_H_
-
-#include <mach-common/irq.h>
-
-#define NR_PERI_INTS 24
-
-#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
-#define IRQ_DMA_ERROR BFIN_IRQ(1) /* DMA Error (general) */
-#define IRQ_PPI_ERROR BFIN_IRQ(2) /* PPI Error Interrupt */
-#define IRQ_SPORT0_ERROR BFIN_IRQ(3) /* SPORT0 Error Interrupt */
-#define IRQ_SPORT1_ERROR BFIN_IRQ(4) /* SPORT1 Error Interrupt */
-#define IRQ_SPI_ERROR BFIN_IRQ(5) /* SPI Error Interrupt */
-#define IRQ_UART0_ERROR BFIN_IRQ(6) /* UART Error Interrupt */
-#define IRQ_RTC BFIN_IRQ(7) /* RTC Interrupt */
-#define IRQ_PPI BFIN_IRQ(8) /* DMA0 Interrupt (PPI) */
-#define IRQ_SPORT0_RX BFIN_IRQ(9) /* DMA1 Interrupt (SPORT0 RX) */
-#define IRQ_SPORT0_TX BFIN_IRQ(10) /* DMA2 Interrupt (SPORT0 TX) */
-#define IRQ_SPORT1_RX BFIN_IRQ(11) /* DMA3 Interrupt (SPORT1 RX) */
-#define IRQ_SPORT1_TX BFIN_IRQ(12) /* DMA4 Interrupt (SPORT1 TX) */
-#define IRQ_SPI BFIN_IRQ(13) /* DMA5 Interrupt (SPI) */
-#define IRQ_UART0_RX BFIN_IRQ(14) /* DMA6 Interrupt (UART RX) */
-#define IRQ_UART0_TX BFIN_IRQ(15) /* DMA7 Interrupt (UART TX) */
-#define IRQ_TIMER0 BFIN_IRQ(16) /* Timer 0 */
-#define IRQ_TIMER1 BFIN_IRQ(17) /* Timer 1 */
-#define IRQ_TIMER2 BFIN_IRQ(18) /* Timer 2 */
-#define IRQ_PROG_INTA BFIN_IRQ(19) /* Programmable Flags A (8) */
-#define IRQ_PROG_INTB BFIN_IRQ(20) /* Programmable Flags B (8) */
-#define IRQ_MEM_DMA0 BFIN_IRQ(21) /* DMA8/9 Interrupt (Memory DMA Stream 0) */
-#define IRQ_MEM_DMA1 BFIN_IRQ(22) /* DMA10/11 Interrupt (Memory DMA Stream 1) */
-#define IRQ_WATCH BFIN_IRQ(23) /* Watch Dog Timer */
-
-#define SYS_IRQS 31
-
-#define IRQ_PF0 33
-#define IRQ_PF1 34
-#define IRQ_PF2 35
-#define IRQ_PF3 36
-#define IRQ_PF4 37
-#define IRQ_PF5 38
-#define IRQ_PF6 39
-#define IRQ_PF7 40
-#define IRQ_PF8 41
-#define IRQ_PF9 42
-#define IRQ_PF10 43
-#define IRQ_PF11 44
-#define IRQ_PF12 45
-#define IRQ_PF13 46
-#define IRQ_PF14 47
-#define IRQ_PF15 48
-
-#define GPIO_IRQ_BASE IRQ_PF0
-
-#define NR_MACH_IRQS (IRQ_PF15 + 1)
-
-/* IAR0 BIT FIELDS */
-#define RTC_ERROR_POS 28
-#define UART_ERROR_POS 24
-#define SPORT1_ERROR_POS 20
-#define SPI_ERROR_POS 16
-#define SPORT0_ERROR_POS 12
-#define PPI_ERROR_POS 8
-#define DMA_ERROR_POS 4
-#define PLLWAKE_ERROR_POS 0
-
-/* IAR1 BIT FIELDS */
-#define DMA7_UARTTX_POS 28
-#define DMA6_UARTRX_POS 24
-#define DMA5_SPI_POS 20
-#define DMA4_SPORT1TX_POS 16
-#define DMA3_SPORT1RX_POS 12
-#define DMA2_SPORT0TX_POS 8
-#define DMA1_SPORT0RX_POS 4
-#define DMA0_PPI_POS 0
-
-/* IAR2 BIT FIELDS */
-#define WDTIMER_POS 28
-#define MEMDMA1_POS 24
-#define MEMDMA0_POS 20
-#define PFB_POS 16
-#define PFA_POS 12
-#define TIMER2_POS 8
-#define TIMER1_POS 4
-#define TIMER0_POS 0
-
-#endif
+++ /dev/null
-/*
- * BF533 memory map
- *
- * Copyright 2004-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MACH_MEM_MAP_H__
-#define __BFIN_MACH_MEM_MAP_H__
-
-#ifndef __BFIN_MEM_MAP_H__
-# error "do not include mach/mem_map.h directly -- use asm/mem_map.h"
-#endif
-
-/* Async Memory Banks */
-#define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */
-#define ASYNC_BANK3_SIZE 0x00100000 /* 1M */
-#define ASYNC_BANK2_BASE 0x20200000 /* Async Bank 2 */
-#define ASYNC_BANK2_SIZE 0x00100000 /* 1M */
-#define ASYNC_BANK1_BASE 0x20100000 /* Async Bank 1 */
-#define ASYNC_BANK1_SIZE 0x00100000 /* 1M */
-#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
-#define ASYNC_BANK0_SIZE 0x00100000 /* 1M */
-
-/* Boot ROM Memory */
-
-#define BOOT_ROM_START 0xEF000000
-#define BOOT_ROM_LENGTH 0x400
-
-/* Level 1 Memory */
-
-#ifdef CONFIG_BFIN_ICACHE
-#define BFIN_ICACHESIZE (16*1024)
-#else
-#define BFIN_ICACHESIZE (0*1024)
-#endif
-
-/* Memory Map for ADSP-BF533 processors */
-
-#ifdef CONFIG_BF533
-#define L1_CODE_START 0xFFA00000
-#define L1_DATA_A_START 0xFF800000
-#define L1_DATA_B_START 0xFF900000
-
-#ifdef CONFIG_BFIN_ICACHE
-#define L1_CODE_LENGTH (0x14000 - 0x4000)
-#else
-#define L1_CODE_LENGTH 0x14000
-#endif
-
-#ifdef CONFIG_BFIN_DCACHE
-
-#ifdef CONFIG_BFIN_DCACHE_BANKA
-#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE (16*1024)
-#define BFIN_DSUPBANKS 1
-#else
-#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
-#define BFIN_DCACHESIZE (32*1024)
-#define BFIN_DSUPBANKS 2
-#endif
-
-#else
-#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH 0x8000
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE (0*1024)
-#define BFIN_DSUPBANKS 0
-#endif /*CONFIG_BFIN_DCACHE*/
-#endif
-
-/* Memory Map for ADSP-BF532 processors */
-
-#ifdef CONFIG_BF532
-#define L1_CODE_START 0xFFA08000
-#define L1_DATA_A_START 0xFF804000
-#define L1_DATA_B_START 0xFF904000
-
-#ifdef CONFIG_BFIN_ICACHE
-#define L1_CODE_LENGTH (0xC000 - 0x4000)
-#else
-#define L1_CODE_LENGTH 0xC000
-#endif
-
-#ifdef CONFIG_BFIN_DCACHE
-
-#ifdef CONFIG_BFIN_DCACHE_BANKA
-#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
-#define L1_DATA_B_LENGTH 0x4000
-#define BFIN_DCACHESIZE (16*1024)
-#define BFIN_DSUPBANKS 1
-
-#else
-#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
-#define L1_DATA_B_LENGTH (0x4000 - 0x4000)
-#define BFIN_DCACHESIZE (32*1024)
-#define BFIN_DSUPBANKS 2
-#endif
-
-#else
-#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH 0x4000
-#define L1_DATA_B_LENGTH 0x4000
-#define BFIN_DCACHESIZE (0*1024)
-#define BFIN_DSUPBANKS 0
-#endif /*CONFIG_BFIN_DCACHE*/
-#endif
-
-/* Memory Map for ADSP-BF531 processors */
-
-#ifdef CONFIG_BF531
-#define L1_CODE_START 0xFFA08000
-#define L1_DATA_A_START 0xFF804000
-#define L1_DATA_B_START 0xFF904000
-#define L1_CODE_LENGTH 0x4000
-#define L1_DATA_B_LENGTH 0x0000
-
-
-#ifdef CONFIG_BFIN_DCACHE
-#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
-#define BFIN_DCACHESIZE (16*1024)
-#define BFIN_DSUPBANKS 1
-#else
-#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH 0x4000
-#define BFIN_DCACHESIZE (0*1024)
-#define BFIN_DSUPBANKS 0
-#endif
-
-#endif
-
-#endif
+++ /dev/null
-#include <mach-common/pll.h>
+++ /dev/null
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _MACH_PORTMUX_H_
-#define _MACH_PORTMUX_H_
-
-#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
-
-#define P_PPI0_CLK (P_DONTCARE)
-#define P_PPI0_FS1 (P_DONTCARE)
-#define P_PPI0_FS2 (P_DONTCARE)
-#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PF3))
-#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF4))
-#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF5))
-#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF6))
-#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF7))
-#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF8))
-#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF9))
-#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF10))
-#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF11))
-#define P_PPI0_D0 (P_DONTCARE)
-#define P_PPI0_D1 (P_DONTCARE)
-#define P_PPI0_D2 (P_DONTCARE)
-#define P_PPI0_D3 (P_DONTCARE)
-#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF15))
-#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF14))
-#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF13))
-#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF12))
-
-#define P_SPORT1_TSCLK (P_DONTCARE)
-#define P_SPORT1_RSCLK (P_DONTCARE)
-#define P_SPORT0_TSCLK (P_DONTCARE)
-#define P_SPORT0_RSCLK (P_DONTCARE)
-#define P_UART0_RX (P_DONTCARE)
-#define P_UART0_TX (P_DONTCARE)
-#define P_SPORT1_DRSEC (P_DONTCARE)
-#define P_SPORT1_RFS (P_DONTCARE)
-#define P_SPORT1_DTPRI (P_DONTCARE)
-#define P_SPORT1_DTSEC (P_DONTCARE)
-#define P_SPORT1_TFS (P_DONTCARE)
-#define P_SPORT1_DRPRI (P_DONTCARE)
-#define P_SPORT0_DRSEC (P_DONTCARE)
-#define P_SPORT0_RFS (P_DONTCARE)
-#define P_SPORT0_DTPRI (P_DONTCARE)
-#define P_SPORT0_DTSEC (P_DONTCARE)
-#define P_SPORT0_TFS (P_DONTCARE)
-#define P_SPORT0_DRPRI (P_DONTCARE)
-
-#define P_SPI0_MOSI (P_DONTCARE)
-#define P_SPI0_MISO (P_DONTCARE)
-#define P_SPI0_SCK (P_DONTCARE)
-#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF7))
-#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF6))
-#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5))
-#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF4))
-#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF3))
-#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2))
-#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1))
-#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0))
-#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF2
-#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2
-
-#define P_TMR2 (P_DONTCARE)
-#define P_TMR1 (P_DONTCARE)
-#define P_TMR0 (P_DONTCARE)
-#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF1))
-
-#endif /* _MACH_PORTMUX_H_ */
+++ /dev/null
-/*
- * Set up the interrupt priorities
- *
- * Copyright 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-#include <linux/irq.h>
-#include <asm/blackfin.h>
-
-void __init program_IAR(void)
-{
- /* Program the IAR0 Register with the configured priority */
- bfin_write_SIC_IAR0(((CONFIG_PLLWAKE_ERROR - 7) << PLLWAKE_ERROR_POS) |
- ((CONFIG_DMA_ERROR - 7) << DMA_ERROR_POS) |
- ((CONFIG_PPI_ERROR - 7) << PPI_ERROR_POS) |
- ((CONFIG_SPORT0_ERROR - 7) << SPORT0_ERROR_POS) |
- ((CONFIG_SPI_ERROR - 7) << SPI_ERROR_POS) |
- ((CONFIG_SPORT1_ERROR - 7) << SPORT1_ERROR_POS) |
- ((CONFIG_UART_ERROR - 7) << UART_ERROR_POS) |
- ((CONFIG_RTC_ERROR - 7) << RTC_ERROR_POS));
-
- bfin_write_SIC_IAR1(((CONFIG_DMA0_PPI - 7) << DMA0_PPI_POS) |
- ((CONFIG_DMA1_SPORT0RX - 7) << DMA1_SPORT0RX_POS) |
- ((CONFIG_DMA2_SPORT0TX - 7) << DMA2_SPORT0TX_POS) |
- ((CONFIG_DMA3_SPORT1RX - 7) << DMA3_SPORT1RX_POS) |
- ((CONFIG_DMA4_SPORT1TX - 7) << DMA4_SPORT1TX_POS) |
- ((CONFIG_DMA5_SPI - 7) << DMA5_SPI_POS) |
- ((CONFIG_DMA6_UARTRX - 7) << DMA6_UARTRX_POS) |
- ((CONFIG_DMA7_UARTTX - 7) << DMA7_UARTTX_POS));
-
- bfin_write_SIC_IAR2(((CONFIG_TIMER0 - 7) << TIMER0_POS) |
- ((CONFIG_TIMER1 - 7) << TIMER1_POS) |
- ((CONFIG_TIMER2 - 7) << TIMER2_POS) |
- ((CONFIG_PFA - 7) << PFA_POS) |
- ((CONFIG_PFB - 7) << PFB_POS) |
- ((CONFIG_MEMDMA0 - 7) << MEMDMA0_POS) |
- ((CONFIG_MEMDMA1 - 7) << MEMDMA1_POS) |
- ((CONFIG_WDTIMER - 7) << WDTIMER_POS));
-
- SSYNC();
-}
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0
-if (BF537 || BF534 || BF536)
-
-source "arch/blackfin/mach-bf537/boards/Kconfig"
-
-menu "BF537 Specific Configuration"
-
-comment "Interrupt Priority Assignment"
-menu "Priority"
-
-config IRQ_PLL_WAKEUP
- int "IRQ_PLL_WAKEUP"
- default 7
-config IRQ_DMA_ERROR
- int "IRQ_DMA_ERROR Generic"
- default 7
-config IRQ_ERROR
- int "IRQ_ERROR: PPI CAN MAC SPORT0 SPORT1 SPI UART0 UART1"
- default 11
-config IRQ_RTC
- int "IRQ_RTC"
- default 8
-config IRQ_PPI
- int "IRQ_PPI"
- default 8
-config IRQ_SPORT0_RX
- int "IRQ_SPORT0_RX"
- default 9
-config IRQ_SPORT0_TX
- int "IRQ_SPORT0_TX"
- default 9
-config IRQ_SPORT1_RX
- int "IRQ_SPORT1_RX"
- default 9
-config IRQ_SPORT1_TX
- int "IRQ_SPORT1_TX"
- default 9
-config IRQ_TWI
- int "IRQ_TWI"
- default 10
-config IRQ_SPI
- int "IRQ_SPI"
- default 10
-config IRQ_UART0_RX
- int "IRQ_UART0_RX"
- default 10
-config IRQ_UART0_TX
- int "IRQ_UART0_TX"
- default 10
-config IRQ_UART1_RX
- int "IRQ_UART1_RX"
- default 10
-config IRQ_UART1_TX
- int "IRQ_UART1_TX"
- default 10
-config IRQ_CAN_RX
- int "IRQ_CAN_RX"
- default 11
-config IRQ_CAN_TX
- int "IRQ_CAN_TX"
- default 11
-config IRQ_MAC_RX
- int "IRQ_MAC_RX"
- default 11
-config IRQ_MAC_TX
- int "IRQ_MAC_TX"
- default 11
-config IRQ_TIMER0
- int "IRQ_TIMER0"
- default 7 if TICKSOURCE_GPTMR0
- default 8
-config IRQ_TIMER1
- int "IRQ_TIMER1"
- default 12
-config IRQ_TIMER2
- int "IRQ_TIMER2"
- default 12
-config IRQ_TIMER3
- int "IRQ_TIMER3"
- default 12
-config IRQ_TIMER4
- int "IRQ_TIMER4"
- default 12
-config IRQ_TIMER5
- int "IRQ_TIMER5"
- default 12
-config IRQ_TIMER6
- int "IRQ_TIMER6"
- default 12
-config IRQ_TIMER7
- int "IRQ_TIMER7"
- default 12
-config IRQ_PROG_INTA
- int "IRQ_PROG_INTA"
- default 12
-config IRQ_PORTG_INTB
- int "IRQ_PORTG_INTB"
- default 12
-config IRQ_MEM_DMA0
- int "IRQ_MEM_DMA0"
- default 13
-config IRQ_MEM_DMA1
- int "IRQ_MEM_DMA1"
- default 13
-config IRQ_WATCH
- int "IRQ_WATCH"
- default 13
-
- help
- Enter the priority numbers between 7-13 ONLY. Others are Reserved.
- This applies to all the above. It is not recommended to assign the
- highest priority number 7 to UART or any other device.
-
-endmenu
-
-endmenu
-
-endif
+++ /dev/null
-#
-# arch/blackfin/mach-bf537/Makefile
-#
-
-obj-y := ints-priority.o dma.o
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0
-choice
- prompt "System type"
- default BFIN537_STAMP
- help
- Select your board!
-
-config BFIN537_STAMP
- bool "BF537-STAMP"
- help
- BF537-STAMP board support.
-
-config BFIN537_BLUETECHNIX_CM_E
- bool "Bluetechnix CM-BF537E"
- depends on (BF537)
- help
- CM-BF537E support for EVAL- and DEV-Board.
-
-config BFIN537_BLUETECHNIX_CM_U
- bool "Bluetechnix CM-BF537U"
- depends on (BF537)
- help
- CM-BF537U support for EVAL- and DEV-Board.
-
-config BFIN537_BLUETECHNIX_TCM
- bool "Bluetechnix TCM-BF537"
- depends on (BF537)
- help
- TCM-BF537 support for EVAL- and DEV-Board.
-
-config PNAV10
- bool "PNAV board"
- depends on (BF537)
- help
- PNAV board support.
-
-config CAMSIG_MINOTAUR
- bool "Cambridge Signal Processing LTD Minotaur"
- depends on (BF537)
- help
- Board supply package for CSP Minotaur
-
-config DNP5370
- bool "SSV Dil/NetPC DNP/5370"
- depends on (BF537)
- help
- Board supply package for DNP/5370 DIL64 module
-
-endchoice
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0
-#
-# arch/blackfin/mach-bf537/boards/Makefile
-#
-
-obj-$(CONFIG_BFIN537_STAMP) += stamp.o
-obj-$(CONFIG_BFIN537_BLUETECHNIX_CM_E) += cm_bf537e.o
-obj-$(CONFIG_BFIN537_BLUETECHNIX_CM_U) += cm_bf537u.o
-obj-$(CONFIG_BFIN537_BLUETECHNIX_TCM) += tcm_bf537.o
-obj-$(CONFIG_PNAV10) += pnav10.o
-obj-$(CONFIG_CAMSIG_MINOTAUR) += minotaur.o
-obj-$(CONFIG_DNP5370) += dnp5370.o
+++ /dev/null
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2008-2009 Bluetechnix
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/export.h>
-#include <linux/etherdevice.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-#include <linux/usb/isp1362.h>
-#endif
-#include <linux/ata_platform.h>
-#include <linux/irq.h>
-#include <linux/gpio.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-#include <asm/bfin_sport.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "Bluetechnix CM BF537E";
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* all SPI peripherals info goes here */
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00020000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = 0xe0000,
- .offset = 0x20000
- }, {
- .name = "file system(spi)",
- .size = 0x700000,
- .offset = 0x00100000,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p64",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
- {
- .modalias = "ad183x",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 4,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-};
-
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_SPI_BFIN_SPORT)
-
-/* SPORT SPI controller data */
-static struct bfin5xx_spi_master bfin_sport_spi0_info = {
- .num_chipselect = MAX_BLACKFIN_GPIOS,
- .enable_dma = 0, /* master don't support DMA */
- .pin_req = {P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_DRPRI,
- P_SPORT0_RSCLK, P_SPORT0_TFS, P_SPORT0_RFS, 0},
-};
-
-static struct resource bfin_sport_spi0_resource[] = {
- [0] = {
- .start = SPORT0_TCR1,
- .end = SPORT0_TCR1 + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_sport_spi0_device = {
- .name = "bfin-sport-spi",
- .id = 1, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_sport_spi0_resource),
- .resource = bfin_sport_spi0_resource,
- .dev = {
- .platform_data = &bfin_sport_spi0_info, /* Passed to driver */
- },
-};
-
-static struct bfin5xx_spi_master bfin_sport_spi1_info = {
- .num_chipselect = MAX_BLACKFIN_GPIOS,
- .enable_dma = 0, /* master don't support DMA */
- .pin_req = {P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_DRPRI,
- P_SPORT1_RSCLK, P_SPORT1_TFS, P_SPORT1_RFS, 0},
-};
-
-static struct resource bfin_sport_spi1_resource[] = {
- [0] = {
- .start = SPORT1_TCR1,
- .end = SPORT1_TCR1 + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_sport_spi1_device = {
- .name = "bfin-sport-spi",
- .id = 2, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_sport_spi1_resource),
- .resource = bfin_sport_spi1_resource,
- .dev = {
- .platform_data = &bfin_sport_spi1_info, /* Passed to driver */
- },
-};
-
-#endif /* sport spi master and devices */
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_FB_HITACHI_TX09)
-static struct platform_device hitachi_fb_device = {
- .name = "hitachi-tx09",
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
-#include <linux/smc91x.h>
-
-static struct smc91x_platdata smc91x_info = {
- .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
- .leda = RPC_LED_100_10,
- .ledb = RPC_LED_TX_RX,
-};
-
-static struct resource smc91x_resources[] = {
- {
- .start = 0x20200300,
- .end = 0x20200300 + 16,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF14,
- .end = IRQ_PF14,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev = {
- .platform_data = &smc91x_info,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-static struct resource isp1362_hcd_resources[] = {
- {
- .start = 0x20308000,
- .end = 0x20308000,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 0x20308004,
- .end = 0x20308004,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PG15,
- .end = IRQ_PG15,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
- },
-};
-
-static struct isp1362_platform_data isp1362_priv = {
- .sel15Kres = 1,
- .clknotstop = 0,
- .oc_enable = 0,
- .int_act_high = 0,
- .int_edge_triggered = 0,
- .remote_wakeup_connected = 0,
- .no_power_switching = 1,
- .power_switching_mode = 0,
-};
-
-static struct platform_device isp1362_hcd_device = {
- .name = "isp1362-hcd",
- .id = 0,
- .dev = {
- .platform_data = &isp1362_priv,
- },
- .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
- .resource = isp1362_hcd_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
-static struct resource net2272_bfin_resources[] = {
- {
- .start = 0x20300000,
- .end = 0x20300000 + 0x100,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PG13,
- .end = IRQ_PG13,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device net2272_bfin_device = {
- .name = "net2272",
- .id = -1,
- .num_resources = ARRAY_SIZE(net2272_bfin_resources),
- .resource = net2272_bfin_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR)
-static struct mtd_partition cm_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x40000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0x100000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct physmap_flash_data cm_flash_data = {
- .width = 2,
- .parts = cm_partitions,
- .nr_parts = ARRAY_SIZE(cm_partitions),
-};
-
-static unsigned cm_flash_gpios[] = { GPIO_PF4 };
-
-static struct resource cm_flash_resource[] = {
- {
- .name = "cfi_probe",
- .start = 0x20000000,
- .end = 0x201fffff,
- .flags = IORESOURCE_MEM,
- }, {
- .start = (unsigned long)cm_flash_gpios,
- .end = ARRAY_SIZE(cm_flash_gpios),
- .flags = IORESOURCE_IRQ,
- }
-};
-
-static struct platform_device cm_flash_device = {
- .name = "gpio-addr-flash",
- .id = 0,
- .dev = {
- .platform_data = &cm_flash_data,
- },
- .num_resources = ARRAY_SIZE(cm_flash_resource),
- .resource = cm_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_THR,
- .end = UART0_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-#ifdef CONFIG_BFIN_UART0_CTSRTS
- {
- /*
- * Refer to arch/blackfin/mach-xxx/include/mach/gpio.h for the GPIO map.
- */
- .start = -1,
- .end = -1,
- .flags = IORESOURCE_IO,
- },
- {
- /*
- * Refer to arch/blackfin/mach-xxx/include/mach/gpio.h for the GPIO map.
- */
- .start = -1,
- .end = -1,
- .flags = IORESOURCE_IO,
- },
-#endif
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_THR,
- .end = UART1_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-#ifdef CONFIG_BFIN_UART1_CTSRTS
- {
- /*
- * Refer to arch/blackfin/mach-xxx/include/mach/gpio.h for the GPIO map.
- */
- .start = -1,
- .end = -1,
- .flags = IORESOURCE_IO,
- },
- {
- /*
- * Refer to arch/blackfin/mach-xxx/include/mach/gpio.h for the GPIO map.
- */
- .start = -1,
- .end = -1,
- .flags = IORESOURCE_IO,
- },
-#endif
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX, 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_REGBASE,
- .end = TWI0_REGBASE,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI,
- .end = IRQ_TWI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) \
-|| IS_ENABLED(CONFIG_BFIN_SPORT)
-unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
-};
-#endif
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-#if IS_ENABLED(CONFIG_BFIN_SPORT)
-static struct resource bfin_sport0_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_TX,
- .end = IRQ_SPORT0_TX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_SPORT0_TX,
- .end = CH_SPORT0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_SPORT0_RX,
- .end = CH_SPORT0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sport0_device = {
- .name = "bfin_sport_raw",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_resources),
- .resource = bfin_sport0_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
-#include <linux/bfin_mac.h>
-static const unsigned short bfin_mac_peripherals[] = P_MII0;
-
-static struct bfin_phydev_platform_data bfin_phydev_data[] = {
- {
- .addr = 1,
- .irq = IRQ_MAC_PHYINT,
- },
-};
-
-static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
- .phydev_number = 1,
- .phydev_data = bfin_phydev_data,
- .phy_mode = PHY_INTERFACE_MODE_MII,
- .mac_peripherals = bfin_mac_peripherals,
-};
-
-static struct platform_device bfin_mii_bus = {
- .name = "bfin_mii_bus",
- .dev = {
- .platform_data = &bfin_mii_bus_data,
- }
-};
-
-static struct platform_device bfin_mac_device = {
- .name = "bfin_mac",
- .dev = {
- .platform_data = &bfin_mii_bus,
- }
-};
-#endif
-
-#if IS_ENABLED(CONFIG_PATA_PLATFORM)
-#define PATA_INT IRQ_PF14
-
-static struct pata_platform_info bfin_pata_platform_data = {
- .ioport_shift = 2,
-};
-
-static struct resource bfin_pata_resources[] = {
- {
- .start = 0x2030C000,
- .end = 0x2030C01F,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = 0x2030D018,
- .end = 0x2030D01B,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = PATA_INT,
- .end = PATA_INT,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device bfin_pata_device = {
- .name = "pata_platform",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_pata_resources),
- .resource = bfin_pata_resources,
- .dev = {
- .platform_data = &bfin_pata_platform_data,
- }
-};
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
- VRPAIR(VLEV_085, 250000000),
- VRPAIR(VLEV_090, 376000000),
- VRPAIR(VLEV_095, 426000000),
- VRPAIR(VLEV_100, 426000000),
- VRPAIR(VLEV_105, 476000000),
- VRPAIR(VLEV_110, 476000000),
- VRPAIR(VLEV_115, 476000000),
- VRPAIR(VLEV_120, 500000000),
- VRPAIR(VLEV_125, 533000000),
- VRPAIR(VLEV_130, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-static struct platform_device *cm_bf537e_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_BFIN_SPORT)
- &bfin_sport0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_FB_HITACHI_TX09)
- &hitachi_fb_device,
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
- &isp1362_hcd_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
- &smc91x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
- &bfin_mii_bus,
- &bfin_mac_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
- &net2272_bfin_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN_SPORT)
- &bfin_sport_spi0_device,
- &bfin_sport_spi1_device,
-#endif
-
-#if IS_ENABLED(CONFIG_PATA_PLATFORM)
- &bfin_pata_device,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR)
- &cm_flash_device,
-#endif
-};
-
-static int __init net2272_init(void)
-{
-#if IS_ENABLED(CONFIG_USB_NET2272)
- int ret;
-
- ret = gpio_request(GPIO_PG14, "net2272");
- if (ret)
- return ret;
-
- /* Reset USB Chip, PG14 */
- gpio_direction_output(GPIO_PG14, 0);
- mdelay(2);
- gpio_set_value(GPIO_PG14, 1);
-#endif
-
- return 0;
-}
-
-static int __init cm_bf537e_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- platform_add_devices(cm_bf537e_devices, ARRAY_SIZE(cm_bf537e_devices));
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
-#endif
-
-#if IS_ENABLED(CONFIG_PATA_PLATFORM)
- irq_set_status_flags(PATA_INT, IRQ_NOAUTOEN);
-#endif
-
- if (net2272_init())
- pr_warning("unable to configure net2272; it probably won't work\n");
-
- return 0;
-}
-
-arch_initcall(cm_bf537e_init);
-
-static struct platform_device *cm_bf537e_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(cm_bf537e_early_devices,
- ARRAY_SIZE(cm_bf537e_early_devices));
-}
-
-int bfin_get_ether_addr(char *addr)
-{
- return 1;
-}
-EXPORT_SYMBOL(bfin_get_ether_addr);
+++ /dev/null
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2008-2009 Bluetechnix
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/etherdevice.h>
-#include <linux/export.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-#include <linux/usb/isp1362.h>
-#endif
-#include <linux/ata_platform.h>
-#include <linux/irq.h>
-#include <linux/gpio.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-#include <linux/spi/mmc_spi.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "Bluetechnix CM BF537U";
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* all SPI peripherals info goes here */
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00020000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = 0xe0000,
- .offset = 0x20000
- }, {
- .name = "file system(spi)",
- .size = 0x700000,
- .offset = 0x00100000,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p64",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
- {
- .modalias = "ad183x",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 4,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-};
-
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_FB_HITACHI_TX09)
-static struct platform_device hitachi_fb_device = {
- .name = "hitachi-tx09",
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
-#include <linux/smc91x.h>
-
-static struct smc91x_platdata smc91x_info = {
- .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
- .leda = RPC_LED_100_10,
- .ledb = RPC_LED_TX_RX,
-};
-
-static struct resource smc91x_resources[] = {
- {
- .start = 0x20200300,
- .end = 0x20200300 + 16,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF14,
- .end = IRQ_PF14,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev = {
- .platform_data = &smc91x_info,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-static struct resource isp1362_hcd_resources[] = {
- {
- .start = 0x20308000,
- .end = 0x20308000,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 0x20308004,
- .end = 0x20308004,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PG15,
- .end = IRQ_PG15,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
- },
-};
-
-static struct isp1362_platform_data isp1362_priv = {
- .sel15Kres = 1,
- .clknotstop = 0,
- .oc_enable = 0,
- .int_act_high = 0,
- .int_edge_triggered = 0,
- .remote_wakeup_connected = 0,
- .no_power_switching = 1,
- .power_switching_mode = 0,
-};
-
-static struct platform_device isp1362_hcd_device = {
- .name = "isp1362-hcd",
- .id = 0,
- .dev = {
- .platform_data = &isp1362_priv,
- },
- .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
- .resource = isp1362_hcd_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
-static struct resource net2272_bfin_resources[] = {
- {
- .start = 0x20200000,
- .end = 0x20200000 + 0x100,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PH14,
- .end = IRQ_PH14,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device net2272_bfin_device = {
- .name = "net2272",
- .id = -1,
- .num_resources = ARRAY_SIZE(net2272_bfin_resources),
- .resource = net2272_bfin_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR)
-static struct mtd_partition cm_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x40000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0x100000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct physmap_flash_data cm_flash_data = {
- .width = 2,
- .parts = cm_partitions,
- .nr_parts = ARRAY_SIZE(cm_partitions),
-};
-
-static unsigned cm_flash_gpios[] = { GPIO_PH0 };
-
-static struct resource cm_flash_resource[] = {
- {
- .name = "cfi_probe",
- .start = 0x20000000,
- .end = 0x201fffff,
- .flags = IORESOURCE_MEM,
- }, {
- .start = (unsigned long)cm_flash_gpios,
- .end = ARRAY_SIZE(cm_flash_gpios),
- .flags = IORESOURCE_IRQ,
- }
-};
-
-static struct platform_device cm_flash_device = {
- .name = "gpio-addr-flash",
- .id = 0,
- .dev = {
- .platform_data = &cm_flash_data,
- },
- .num_resources = ARRAY_SIZE(cm_flash_resource),
- .resource = cm_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_THR,
- .end = UART0_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_THR,
- .end = UART1_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX, 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_REGBASE,
- .end = TWI0_REGBASE,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI,
- .end = IRQ_TWI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
-#include <linux/bfin_mac.h>
-static const unsigned short bfin_mac_peripherals[] = P_MII0;
-
-static struct bfin_phydev_platform_data bfin_phydev_data[] = {
- {
- .addr = 1,
- .irq = IRQ_MAC_PHYINT,
- },
-};
-
-static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
- .phydev_number = 1,
- .phydev_data = bfin_phydev_data,
- .phy_mode = PHY_INTERFACE_MODE_MII,
- .mac_peripherals = bfin_mac_peripherals,
-};
-
-static struct platform_device bfin_mii_bus = {
- .name = "bfin_mii_bus",
- .dev = {
- .platform_data = &bfin_mii_bus_data,
- }
-};
-
-static struct platform_device bfin_mac_device = {
- .name = "bfin_mac",
- .dev = {
- .platform_data = &bfin_mii_bus,
- }
-};
-#endif
-
-#if IS_ENABLED(CONFIG_PATA_PLATFORM)
-#define PATA_INT IRQ_PF14
-
-static struct pata_platform_info bfin_pata_platform_data = {
- .ioport_shift = 2,
-};
-
-static struct resource bfin_pata_resources[] = {
- {
- .start = 0x2030C000,
- .end = 0x2030C01F,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = 0x2030D018,
- .end = 0x2030D01B,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = PATA_INT,
- .end = PATA_INT,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device bfin_pata_device = {
- .name = "pata_platform",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_pata_resources),
- .resource = bfin_pata_resources,
- .dev = {
- .platform_data = &bfin_pata_platform_data,
- }
-};
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
- VRPAIR(VLEV_085, 250000000),
- VRPAIR(VLEV_090, 376000000),
- VRPAIR(VLEV_095, 426000000),
- VRPAIR(VLEV_100, 426000000),
- VRPAIR(VLEV_105, 476000000),
- VRPAIR(VLEV_110, 476000000),
- VRPAIR(VLEV_115, 476000000),
- VRPAIR(VLEV_120, 500000000),
- VRPAIR(VLEV_125, 533000000),
- VRPAIR(VLEV_130, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-static struct platform_device *cm_bf537u_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_FB_HITACHI_TX09)
- &hitachi_fb_device,
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
- &isp1362_hcd_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
- &smc91x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
- &bfin_mii_bus,
- &bfin_mac_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
- &net2272_bfin_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_PATA_PLATFORM)
- &bfin_pata_device,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR)
- &cm_flash_device,
-#endif
-};
-
-static int __init net2272_init(void)
-{
-#if IS_ENABLED(CONFIG_USB_NET2272)
- int ret;
-
- ret = gpio_request(GPIO_PH15, driver_name);
- if (ret)
- return ret;
-
- ret = gpio_request(GPIO_PH13, "net2272");
- if (ret) {
- gpio_free(GPIO_PH15);
- return ret;
- }
-
- /* Set PH15 Low make /AMS2 work properly */
- gpio_direction_output(GPIO_PH15, 0);
-
- /* enable CLKBUF output */
- bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE);
-
- /* Reset the USB chip */
- gpio_direction_output(GPIO_PH13, 0);
- mdelay(2);
- gpio_set_value(GPIO_PH13, 1);
-#endif
-
- return 0;
-}
-
-static int __init cm_bf537u_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- platform_add_devices(cm_bf537u_devices, ARRAY_SIZE(cm_bf537u_devices));
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
-#endif
-
-#if IS_ENABLED(CONFIG_PATA_PLATFORM)
- irq_set_status_flags(PATA_INT, IRQ_NOAUTOEN);
-#endif
-
- if (net2272_init())
- pr_warning("unable to configure net2272; it probably won't work\n");
-
- return 0;
-}
-
-arch_initcall(cm_bf537u_init);
-
-static struct platform_device *cm_bf537u_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(cm_bf537u_early_devices,
- ARRAY_SIZE(cm_bf537u_early_devices));
-}
-
-int bfin_get_ether_addr(char *addr)
-{
- return 1;
-}
-EXPORT_SYMBOL(bfin_get_ether_addr);
+++ /dev/null
-/*
- * This is the configuration for SSV Dil/NetPC DNP/5370 board.
- *
- * DIL module: http://www.dilnetpc.com/dnp0086.htm
- * SK28 (starter kit): http://www.dilnetpc.com/dnp0088.htm
- *
- * Copyright 2010 3ality Digital Systems
- * Copyright 2005 National ICT Australia (NICTA)
- * Copyright 2004-2006 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/export.h>
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/rawnand.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/plat-ram.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <linux/i2c.h>
-#include <linux/spi/mmc_spi.h>
-#include <linux/phy.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/reboot.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "DNP/5370";
-#define FLASH_MAC 0x202f0000
-#define CONFIG_MTD_PHYSMAP_LEN 0x300000
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
-#include <linux/bfin_mac.h>
-static const unsigned short bfin_mac_peripherals[] = P_RMII0;
-
-static struct bfin_phydev_platform_data bfin_phydev_data[] = {
- {
- .addr = 1,
- .irq = PHY_POLL, /* IRQ_MAC_PHYINT */
- },
-};
-
-static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
- .phydev_number = 1,
- .phydev_data = bfin_phydev_data,
- .phy_mode = PHY_INTERFACE_MODE_RMII,
- .mac_peripherals = bfin_mac_peripherals,
-};
-
-static struct platform_device bfin_mii_bus = {
- .name = "bfin_mii_bus",
- .dev = {
- .platform_data = &bfin_mii_bus_data,
- }
-};
-
-static struct platform_device bfin_mac_device = {
- .name = "bfin_mac",
- .dev = {
- .platform_data = &bfin_mii_bus,
- }
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
-static struct mtd_partition asmb_flash_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x30000,
- .offset = 0,
- }, {
- .name = "linux kernel and rootfs(nor)",
- .size = 0x300000 - 0x30000 - 0x10000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "MAC address(nor)",
- .size = 0x10000,
- .offset = MTDPART_OFS_APPEND,
- .mask_flags = MTD_WRITEABLE,
- }
-};
-
-static struct physmap_flash_data asmb_flash_data = {
- .width = 1,
- .parts = asmb_flash_partitions,
- .nr_parts = ARRAY_SIZE(asmb_flash_partitions),
-};
-
-static struct resource asmb_flash_resource = {
- .start = 0x20000000,
- .end = 0x202fffff,
- .flags = IORESOURCE_MEM,
-};
-
-/* 4 MB NOR flash attached to async memory banks 0-2,
- * therefore only 3 MB visible.
- */
-static struct platform_device asmb_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &asmb_flash_data,
- },
- .num_resources = 1,
- .resource = &asmb_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0, /* use no dma transfer with this chip*/
-};
-
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_DATAFLASH)
-/* This mapping is for at45db642 it has 1056 page size,
- * partition size and offset should be page aligned
- */
-static struct mtd_partition bfin_spi_dataflash_partitions[] = {
- {
- .name = "JFFS2 dataflash(nor)",
-#ifdef CONFIG_MTD_PAGESIZE_1024
- .offset = 0x40000,
- .size = 0x7C0000,
-#else
- .offset = 0x0,
- .size = 0x840000,
-#endif
- }
-};
-
-static struct flash_platform_data bfin_spi_dataflash_data = {
- .name = "mtd_dataflash",
- .parts = bfin_spi_dataflash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_dataflash_partitions),
- .type = "mtd_dataflash",
-};
-
-static struct bfin5xx_spi_chip spi_dataflash_chip_info = {
- .enable_dma = 0, /* use no dma transfer with this chip*/
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-/* SD/MMC card reader at SPI bus */
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 20000000,
- .bus_num = 0,
- .chip_select = 1,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-/* 8 Megabyte Atmel NOR flash chip at SPI bus */
-#if IS_ENABLED(CONFIG_MTD_DATAFLASH)
- {
- .modalias = "mtd_dataflash",
- .max_speed_hz = 16700000,
- .bus_num = 0,
- .chip_select = 2,
- .platform_data = &bfin_spi_dataflash_data,
- .controller_data = &spi_dataflash_chip_info,
- .mode = SPI_MODE_3, /* SPI_CPHA and SPI_CPOL */
- },
-#endif
-};
-
-/* SPI controller data */
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct bfin5xx_spi_master spi_bfin_master_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct platform_device spi_bfin_master_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &spi_bfin_master_info, /* Passed to driver */
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_THR,
- .end = UART0_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_THR,
- .end = UART1_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX, 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_REGBASE,
- .end = TWI0_REGBASE + 0xff,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI,
- .end = IRQ_TWI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-#endif
-
-static struct platform_device *dnp5370_devices[] __initdata = {
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
- &asmb_flash_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
- &bfin_mii_bus,
- &bfin_mac_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &spi_bfin_master_device,
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi_device,
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-};
-
-static int __init dnp5370_init(void)
-{
- printk(KERN_INFO "DNP/5370: registering device resources\n");
- platform_add_devices(dnp5370_devices, ARRAY_SIZE(dnp5370_devices));
- printk(KERN_INFO "DNP/5370: registering %zu SPI slave devices\n",
- ARRAY_SIZE(bfin_spi_board_info));
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
- printk(KERN_INFO "DNP/5370: MAC %pM\n", (void *)FLASH_MAC);
- return 0;
-}
-arch_initcall(dnp5370_init);
-
-/*
- * Currently the MAC address is saved in Flash by U-Boot
- */
-int bfin_get_ether_addr(char *addr)
-{
- *(u32 *)(&(addr[0])) = bfin_read32(FLASH_MAC);
- *(u16 *)(&(addr[4])) = bfin_read16(FLASH_MAC + 4);
- return 0;
-}
-EXPORT_SYMBOL(bfin_get_ether_addr);
+++ /dev/null
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2008-2009 Cambridge Signal Processing
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-#include <linux/usb/isp1362.h>
-#endif
-#include <linux/ata_platform.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <linux/usb/sl811.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/reboot.h>
-#include <asm/portmux.h>
-#include <linux/spi/ad7877.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "CamSig Minotaur BF537";
-
-#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA)
-static struct resource bfin_pcmcia_cf_resources[] = {
- {
- .start = 0x20310000, /* IO PORT */
- .end = 0x20312000,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 0x20311000, /* Attribute Memory */
- .end = 0x20311FFF,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF4,
- .end = IRQ_PF4,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
- }, {
- .start = IRQ_PF6, /* Card Detect PF6 */
- .end = IRQ_PF6,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_pcmcia_cf_device = {
- .name = "bfin_cf_pcmcia",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_pcmcia_cf_resources),
- .resource = bfin_pcmcia_cf_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
-#include <linux/bfin_mac.h>
-static const unsigned short bfin_mac_peripherals[] = P_MII0;
-
-static struct bfin_phydev_platform_data bfin_phydev_data[] = {
- {
- .addr = 1,
- .irq = IRQ_MAC_PHYINT,
- },
-};
-
-static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
- .phydev_number = 1,
- .phydev_data = bfin_phydev_data,
- .phy_mode = PHY_INTERFACE_MODE_MII,
- .mac_peripherals = bfin_mac_peripherals,
-};
-
-static struct platform_device bfin_mii_bus = {
- .name = "bfin_mii_bus",
- .dev = {
- .platform_data = &bfin_mii_bus_data,
- }
-};
-
-static struct platform_device bfin_mac_device = {
- .name = "bfin_mac",
- .dev = {
- .platform_data = &bfin_mii_bus,
- }
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
-static struct resource net2272_bfin_resources[] = {
- {
- .start = 0x20300000,
- .end = 0x20300000 + 0x100,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF7,
- .end = IRQ_PF7,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device net2272_bfin_device = {
- .name = "net2272",
- .id = -1,
- .num_resources = ARRAY_SIZE(net2272_bfin_resources),
- .resource = net2272_bfin_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* all SPI peripherals info goes here */
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-
-/* Partition sizes */
-#define FLASH_SIZE 0x00400000
-#define PSIZE_UBOOT 0x00030000
-#define PSIZE_INITRAMFS 0x00240000
-
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = PSIZE_UBOOT,
- .offset = 0x000000,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "initramfs(spi)",
- .size = PSIZE_INITRAMFS,
- .offset = PSIZE_UBOOT
- }, {
- .name = "opt(spi)",
- .size = FLASH_SIZE - (PSIZE_UBOOT + PSIZE_INITRAMFS),
- .offset = PSIZE_UBOOT + PSIZE_INITRAMFS,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p64",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-};
-
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
-};
-
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_THR,
- .end = UART0_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_THR,
- .end = UART1_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX, 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_REGBASE,
- .end = TWI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI,
- .end = IRQ_TWI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-static struct platform_device *minotaur_devices[] __initdata = {
-#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA)
- &bfin_pcmcia_cf_device,
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
- &bfin_mii_bus,
- &bfin_mac_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
- &net2272_bfin_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-
-};
-
-static int __init minotaur_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- platform_add_devices(minotaur_devices, ARRAY_SIZE(minotaur_devices));
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- spi_register_board_info(bfin_spi_board_info,
- ARRAY_SIZE(bfin_spi_board_info));
-#endif
-
- return 0;
-}
-
-arch_initcall(minotaur_init);
-
-static struct platform_device *minotaur_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(minotaur_early_devices,
- ARRAY_SIZE(minotaur_early_devices));
-}
-
-void native_machine_restart(char *cmd)
-{
- /* workaround reboot hang when booting from SPI */
- if ((bfin_read_SYSCR() & 0x7) == 0x3)
- bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
-}
+++ /dev/null
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/etherdevice.h>
-#include <linux/export.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <linux/irq.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/portmux.h>
-
-#include <linux/spi/ad7877.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "ADI PNAV-1.0";
-
-/*
- * Driver needs to know address, irq and flag pin.
- */
-
-#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA)
-static struct resource bfin_pcmcia_cf_resources[] = {
- {
- .start = 0x20310000, /* IO PORT */
- .end = 0x20312000,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 0x20311000, /* Attribute Memory */
- .end = 0x20311FFF,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF4,
- .end = IRQ_PF4,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
- }, {
- .start = 6, /* Card Detect PF6 */
- .end = 6,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_pcmcia_cf_device = {
- .name = "bfin_cf_pcmcia",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_pcmcia_cf_resources),
- .resource = bfin_pcmcia_cf_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
-#include <linux/smc91x.h>
-
-static struct smc91x_platdata smc91x_info = {
- .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
- .leda = RPC_LED_100_10,
- .ledb = RPC_LED_TX_RX,
-};
-
-static struct resource smc91x_resources[] = {
- {
- .name = "smc91x-regs",
- .start = 0x20300300,
- .end = 0x20300300 + 16,
- .flags = IORESOURCE_MEM,
- }, {
-
- .start = IRQ_PF7,
- .end = IRQ_PF7,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev = {
- .platform_data = &smc91x_info,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
-#include <linux/bfin_mac.h>
-static const unsigned short bfin_mac_peripherals[] = P_RMII0;
-
-static struct bfin_phydev_platform_data bfin_phydev_data[] = {
- {
- .addr = 1,
- .irq = IRQ_MAC_PHYINT,
- },
-};
-
-static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
- .phydev_number = 1,
- .phydev_data = bfin_phydev_data,
- .phy_mode = PHY_INTERFACE_MODE_RMII,
- .mac_peripherals = bfin_mac_peripherals,
-};
-
-static struct platform_device bfin_mii_bus = {
- .name = "bfin_mii_bus",
- .dev = {
- .platform_data = &bfin_mii_bus_data,
- }
-};
-
-static struct platform_device bfin_mac_device = {
- .name = "bfin_mac",
- .dev = {
- .platform_data = &bfin_mii_bus,
- }
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
-static struct resource net2272_bfin_resources[] = {
- {
- .start = 0x20300000,
- .end = 0x20300000 + 0x100,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF7,
- .end = IRQ_PF7,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device net2272_bfin_device = {
- .name = "net2272",
- .id = -1,
- .num_resources = ARRAY_SIZE(net2272_bfin_resources),
- .resource = net2272_bfin_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* all SPI peripherals info goes here */
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00020000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = 0xe0000,
- .offset = 0x20000
- }, {
- .name = "file system(spi)",
- .size = 0x700000,
- .offset = 0x00100000,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p64",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
-static const struct ad7877_platform_data bfin_ad7877_ts_info = {
- .model = 7877,
- .vref_delay_usecs = 50, /* internal, no capacitor */
- .x_plate_ohms = 419,
- .y_plate_ohms = 486,
- .pressure_max = 1000,
- .pressure_min = 0,
- .stopacq_polarity = 1,
- .first_conversion_delay = 3,
- .acquisition_time = 1,
- .averaging = 1,
- .pen_down_acc_interval = 1,
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
- {
- .modalias = "ad183x",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 4,
- },
-#endif
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
-{
- .modalias = "ad7877",
- .platform_data = &bfin_ad7877_ts_info,
- .irq = IRQ_PF2,
- .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5,
-},
-#endif
-
-};
-
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_FB_BF537_LQ035)
-static struct platform_device bfin_fb_device = {
- .name = "bf537-lq035",
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_THR,
- .end = UART0_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_THR,
- .end = UART1_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX, 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif
-#endif
-
-static struct platform_device *stamp_devices[] __initdata = {
-#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA)
- &bfin_pcmcia_cf_device,
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
- &smc91x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
- &bfin_mii_bus,
- &bfin_mac_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
- &net2272_bfin_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BF537_LQ035)
- &bfin_fb_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#endif
-};
-
-static int __init pnav_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- spi_register_board_info(bfin_spi_board_info,
- ARRAY_SIZE(bfin_spi_board_info));
-#endif
- return 0;
-}
-
-arch_initcall(pnav_init);
-
-static struct platform_device *stamp_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(stamp_early_devices,
- ARRAY_SIZE(stamp_early_devices));
-}
-
-int bfin_get_ether_addr(char *addr)
-{
- return 1;
-}
-EXPORT_SYMBOL(bfin_get_ether_addr);
+++ /dev/null
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/export.h>
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/rawnand.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/plat-ram.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-#include <linux/usb/isp1362.h>
-#endif
-#include <linux/i2c.h>
-#include <linux/platform_data/adp5588.h>
-#include <linux/etherdevice.h>
-#include <linux/ata_platform.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <linux/usb/sl811.h>
-#include <linux/spi/mmc_spi.h>
-#include <linux/leds.h>
-#include <linux/input.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/reboot.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-#include <asm/bfin_sport.h>
-#ifdef CONFIG_REGULATOR_FIXED_VOLTAGE
-#include <linux/regulator/fixed.h>
-#endif
-#include <linux/regulator/machine.h>
-#include <linux/regulator/consumer.h>
-#include <linux/regulator/userspace-consumer.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "ADI BF537-STAMP";
-
-/*
- * Driver needs to know address, irq and flag pin.
- */
-
-#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
-#include <linux/usb/isp1760.h>
-static struct resource bfin_isp1760_resources[] = {
- [0] = {
- .start = 0x203C0000,
- .end = 0x203C0000 + 0x000fffff,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_PF7,
- .end = IRQ_PF7,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
- },
-};
-
-static struct isp1760_platform_data isp1760_priv = {
- .is_isp1761 = 0,
- .bus_width_16 = 1,
- .port1_otg = 0,
- .analog_oc = 0,
- .dack_polarity_high = 0,
- .dreq_polarity_high = 0,
-};
-
-static struct platform_device bfin_isp1760_device = {
- .name = "isp1760",
- .id = 0,
- .dev = {
- .platform_data = &isp1760_priv,
- },
- .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
- .resource = bfin_isp1760_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
-#include <linux/gpio_keys.h>
-
-static struct gpio_keys_button bfin_gpio_keys_table[] = {
- {BTN_0, GPIO_PF2, 1, "gpio-keys: BTN0"},
- {BTN_1, GPIO_PF3, 1, "gpio-keys: BTN1"},
- {BTN_2, GPIO_PF4, 1, "gpio-keys: BTN2"},
- {BTN_3, GPIO_PF5, 1, "gpio-keys: BTN3"},
-};
-
-static struct gpio_keys_platform_data bfin_gpio_keys_data = {
- .buttons = bfin_gpio_keys_table,
- .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
-};
-
-static struct platform_device bfin_device_gpiokeys = {
- .name = "gpio-keys",
- .dev = {
- .platform_data = &bfin_gpio_keys_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA)
-static struct resource bfin_pcmcia_cf_resources[] = {
- {
- .start = 0x20310000, /* IO PORT */
- .end = 0x20312000,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 0x20311000, /* Attribute Memory */
- .end = 0x20311FFF,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF4,
- .end = IRQ_PF4,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
- }, {
- .start = 6, /* Card Detect PF6 */
- .end = 6,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_pcmcia_cf_device = {
- .name = "bfin_cf_pcmcia",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_pcmcia_cf_resources),
- .resource = bfin_pcmcia_cf_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
-#include <linux/smc91x.h>
-
-static struct smc91x_platdata smc91x_info = {
- .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
- .leda = RPC_LED_100_10,
- .ledb = RPC_LED_TX_RX,
-};
-
-static struct resource smc91x_resources[] = {
- {
- .name = "smc91x-regs",
- .start = 0x20300300,
- .end = 0x20300300 + 16,
- .flags = IORESOURCE_MEM,
- }, {
-
- .start = IRQ_PF7,
- .end = IRQ_PF7,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev = {
- .platform_data = &smc91x_info,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_DM9000)
-static struct resource dm9000_resources[] = {
- [0] = {
- .start = 0x203FB800,
- .end = 0x203FB800 + 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = 0x203FB804,
- .end = 0x203FB804 + 1,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .start = IRQ_PF9,
- .end = IRQ_PF9,
- .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE),
- },
-};
-
-static struct platform_device dm9000_device = {
- .name = "dm9000",
- .id = -1,
- .num_resources = ARRAY_SIZE(dm9000_resources),
- .resource = dm9000_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_SL811_HCD)
-static struct resource sl811_hcd_resources[] = {
- {
- .start = 0x20340000,
- .end = 0x20340000,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 0x20340004,
- .end = 0x20340004,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF4,
- .end = IRQ_PF4,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-#if defined(CONFIG_USB_SL811_BFIN_USE_VBUS)
-void sl811_port_power(struct device *dev, int is_on)
-{
- gpio_request(CONFIG_USB_SL811_BFIN_GPIO_VBUS, "usb:SL811_VBUS");
- gpio_direction_output(CONFIG_USB_SL811_BFIN_GPIO_VBUS, is_on);
-}
-#endif
-
-static struct sl811_platform_data sl811_priv = {
- .potpg = 10,
- .power = 250, /* == 500mA */
-#if defined(CONFIG_USB_SL811_BFIN_USE_VBUS)
- .port_power = &sl811_port_power,
-#endif
-};
-
-static struct platform_device sl811_hcd_device = {
- .name = "sl811-hcd",
- .id = 0,
- .dev = {
- .platform_data = &sl811_priv,
- },
- .num_resources = ARRAY_SIZE(sl811_hcd_resources),
- .resource = sl811_hcd_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-static struct resource isp1362_hcd_resources[] = {
- {
- .start = 0x20360000,
- .end = 0x20360000,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 0x20360004,
- .end = 0x20360004,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF3,
- .end = IRQ_PF3,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
- },
-};
-
-static struct isp1362_platform_data isp1362_priv = {
- .sel15Kres = 1,
- .clknotstop = 0,
- .oc_enable = 0,
- .int_act_high = 0,
- .int_edge_triggered = 0,
- .remote_wakeup_connected = 0,
- .no_power_switching = 1,
- .power_switching_mode = 0,
-};
-
-static struct platform_device isp1362_hcd_device = {
- .name = "isp1362-hcd",
- .id = 0,
- .dev = {
- .platform_data = &isp1362_priv,
- },
- .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
- .resource = isp1362_hcd_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_CAN_BFIN)
-static unsigned short bfin_can_peripherals[] = {
- P_CAN0_RX, P_CAN0_TX, 0
-};
-
-static struct resource bfin_can_resources[] = {
- {
- .start = 0xFFC02A00,
- .end = 0xFFC02FFF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_CAN_RX,
- .end = IRQ_CAN_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_CAN_TX,
- .end = IRQ_CAN_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_CAN_ERROR,
- .end = IRQ_CAN_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_can_device = {
- .name = "bfin_can",
- .num_resources = ARRAY_SIZE(bfin_can_resources),
- .resource = bfin_can_resources,
- .dev = {
- .platform_data = &bfin_can_peripherals, /* Passed to driver */
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
-#include <linux/bfin_mac.h>
-static const unsigned short bfin_mac_peripherals[] = P_MII0;
-
-static struct bfin_phydev_platform_data bfin_phydev_data[] = {
- {
- .addr = 1,
- .irq = PHY_POLL, /* IRQ_MAC_PHYINT */
- },
-};
-
-static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
- .phydev_number = 1,
- .phydev_data = bfin_phydev_data,
- .phy_mode = PHY_INTERFACE_MODE_MII,
- .mac_peripherals = bfin_mac_peripherals,
-};
-
-static struct platform_device bfin_mii_bus = {
- .name = "bfin_mii_bus",
- .dev = {
- .platform_data = &bfin_mii_bus_data,
- }
-};
-
-static struct platform_device bfin_mac_device = {
- .name = "bfin_mac",
- .dev = {
- .platform_data = &bfin_mii_bus,
- }
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
-static struct resource net2272_bfin_resources[] = {
- {
- .start = 0x20300000,
- .end = 0x20300000 + 0x100,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 1,
- .flags = IORESOURCE_BUS,
- }, {
- .start = IRQ_PF7,
- .end = IRQ_PF7,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device net2272_bfin_device = {
- .name = "net2272",
- .id = -1,
- .num_resources = ARRAY_SIZE(net2272_bfin_resources),
- .resource = net2272_bfin_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_NAND_PLATFORM)
-const char *part_probes[] = { "cmdlinepart", "RedBoot", NULL };
-
-static struct mtd_partition bfin_plat_nand_partitions[] = {
- {
- .name = "linux kernel(nand)",
- .size = 0x400000,
- .offset = 0,
- }, {
- .name = "file system(nand)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- },
-};
-
-#define BFIN_NAND_PLAT_CLE 2
-#define BFIN_NAND_PLAT_ALE 1
-static void bfin_plat_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
-{
- struct nand_chip *this = mtd_to_nand(mtd);
-
- if (cmd == NAND_CMD_NONE)
- return;
-
- if (ctrl & NAND_CLE)
- writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_CLE));
- else
- writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_ALE));
-}
-
-#define BFIN_NAND_PLAT_READY GPIO_PF3
-static int bfin_plat_nand_dev_ready(struct mtd_info *mtd)
-{
- return gpio_get_value(BFIN_NAND_PLAT_READY);
-}
-
-static struct platform_nand_data bfin_plat_nand_data = {
- .chip = {
- .nr_chips = 1,
- .chip_delay = 30,
- .part_probe_types = part_probes,
- .partitions = bfin_plat_nand_partitions,
- .nr_partitions = ARRAY_SIZE(bfin_plat_nand_partitions),
- },
- .ctrl = {
- .cmd_ctrl = bfin_plat_nand_cmd_ctrl,
- .dev_ready = bfin_plat_nand_dev_ready,
- },
-};
-
-#define MAX(x, y) (x > y ? x : y)
-static struct resource bfin_plat_nand_resources = {
- .start = 0x20212000,
- .end = 0x20212000 + (1 << MAX(BFIN_NAND_PLAT_CLE, BFIN_NAND_PLAT_ALE)),
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device bfin_async_nand_device = {
- .name = "gen_nand",
- .id = -1,
- .num_resources = 1,
- .resource = &bfin_plat_nand_resources,
- .dev = {
- .platform_data = &bfin_plat_nand_data,
- },
-};
-
-static void bfin_plat_nand_init(void)
-{
- gpio_request(BFIN_NAND_PLAT_READY, "bfin_nand_plat");
- gpio_direction_input(BFIN_NAND_PLAT_READY);
-}
-#else
-static void bfin_plat_nand_init(void) {}
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
-static struct mtd_partition stamp_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x40000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0x180000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = 0x400000 - 0x40000 - 0x180000 - 0x10000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "MAC Address(nor)",
- .size = MTDPART_SIZ_FULL,
- .offset = 0x3F0000,
- .mask_flags = MTD_WRITEABLE,
- }
-};
-
-static struct physmap_flash_data stamp_flash_data = {
- .width = 2,
- .parts = stamp_partitions,
- .nr_parts = ARRAY_SIZE(stamp_partitions),
-#ifdef CONFIG_ROMKERNEL
- .probe_type = "map_rom",
-#endif
-};
-
-static struct resource stamp_flash_resource = {
- .start = 0x20000000,
- .end = 0x203fffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device stamp_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &stamp_flash_data,
- },
- .num_resources = 1,
- .resource = &stamp_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00040000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = 0x180000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(spi)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- /* .type = "m25p64", */
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_AD714X_SPI)
-#include <linux/input/ad714x.h>
-
-static struct ad714x_slider_plat ad7147_spi_slider_plat[] = {
- {
- .start_stage = 0,
- .end_stage = 7,
- .max_coord = 128,
- },
-};
-
-static struct ad714x_button_plat ad7147_spi_button_plat[] = {
- {
- .keycode = BTN_FORWARD,
- .l_mask = 0,
- .h_mask = 0x600,
- },
- {
- .keycode = BTN_LEFT,
- .l_mask = 0,
- .h_mask = 0x500,
- },
- {
- .keycode = BTN_MIDDLE,
- .l_mask = 0,
- .h_mask = 0x800,
- },
- {
- .keycode = BTN_RIGHT,
- .l_mask = 0x100,
- .h_mask = 0x400,
- },
- {
- .keycode = BTN_BACK,
- .l_mask = 0x200,
- .h_mask = 0x400,
- },
-};
-static struct ad714x_platform_data ad7147_spi_platform_data = {
- .slider_num = 1,
- .button_num = 5,
- .slider = ad7147_spi_slider_plat,
- .button = ad7147_spi_button_plat,
- .stage_cfg_reg = {
- {0xFBFF, 0x1FFF, 0, 0x2626, 1600, 1600, 1600, 1600},
- {0xEFFF, 0x1FFF, 0, 0x2626, 1650, 1650, 1650, 1650},
- {0xFFFF, 0x1FFE, 0, 0x2626, 1650, 1650, 1650, 1650},
- {0xFFFF, 0x1FFB, 0, 0x2626, 1650, 1650, 1650, 1650},
- {0xFFFF, 0x1FEF, 0, 0x2626, 1650, 1650, 1650, 1650},
- {0xFFFF, 0x1FBF, 0, 0x2626, 1650, 1650, 1650, 1650},
- {0xFFFF, 0x1EFF, 0, 0x2626, 1650, 1650, 1650, 1650},
- {0xFFFF, 0x1BFF, 0, 0x2626, 1600, 1600, 1600, 1600},
- {0xFF7B, 0x3FFF, 0x506, 0x2626, 1100, 1100, 1150, 1150},
- {0xFDFE, 0x3FFF, 0x606, 0x2626, 1100, 1100, 1150, 1150},
- {0xFEBA, 0x1FFF, 0x1400, 0x2626, 1200, 1200, 1300, 1300},
- {0xFFEF, 0x1FFF, 0x0, 0x2626, 1100, 1100, 1150, 1150},
- },
- .sys_cfg_reg = {0x2B2, 0x0, 0x3233, 0x819, 0x832, 0xCFF, 0xCFF, 0x0},
-};
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_AD714X_I2C)
-#include <linux/input/ad714x.h>
-static struct ad714x_button_plat ad7142_i2c_button_plat[] = {
- {
- .keycode = BTN_1,
- .l_mask = 0,
- .h_mask = 0x1,
- },
- {
- .keycode = BTN_2,
- .l_mask = 0,
- .h_mask = 0x2,
- },
- {
- .keycode = BTN_3,
- .l_mask = 0,
- .h_mask = 0x4,
- },
- {
- .keycode = BTN_4,
- .l_mask = 0x0,
- .h_mask = 0x8,
- },
-};
-static struct ad714x_platform_data ad7142_i2c_platform_data = {
- .button_num = 4,
- .button = ad7142_i2c_button_plat,
- .stage_cfg_reg = {
- /* fixme: figure out right setting for all comoponent according
- * to hardware feature of EVAL-AD7142EB board */
- {0xE7FF, 0x3FFF, 0x0005, 0x2626, 0x01F4, 0x01F4, 0x028A, 0x028A},
- {0xFDBF, 0x3FFF, 0x0001, 0x2626, 0x01F4, 0x01F4, 0x028A, 0x028A},
- {0xFFFF, 0x2DFF, 0x0001, 0x2626, 0x01F4, 0x01F4, 0x028A, 0x028A},
- {0xFFFF, 0x37BF, 0x0001, 0x2626, 0x01F4, 0x01F4, 0x028A, 0x028A},
- {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320},
- {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320},
- {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320},
- {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320},
- {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320},
- {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320},
- {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320},
- {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320},
- },
- .sys_cfg_reg = {0x0B2, 0x0, 0x690, 0x664, 0x290F, 0xF, 0xF, 0x0},
-};
-#endif
-
-#if IS_ENABLED(CONFIG_AD2S90)
-static struct bfin5xx_spi_chip ad2s90_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_AD2S1200)
-static unsigned short ad2s1200_platform_data[] = {
- /* used as SAMPLE and RDVEL */
- GPIO_PF5, GPIO_PF6, 0
-};
-
-static struct bfin5xx_spi_chip ad2s1200_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_AD2S1210)
-static unsigned short ad2s1210_platform_data[] = {
- /* use as SAMPLE, A0, A1 */
- GPIO_PF7, GPIO_PF8, GPIO_PF9,
-# if defined(CONFIG_AD2S1210_GPIO_INPUT) || defined(CONFIG_AD2S1210_GPIO_OUTPUT)
- /* the RES0 and RES1 pins */
- GPIO_PF4, GPIO_PF5,
-# endif
- 0,
-};
-
-static struct bfin5xx_spi_chip ad2s1210_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SENSORS_AD7314)
-static struct bfin5xx_spi_chip ad7314_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_AD7816)
-static unsigned short ad7816_platform_data[] = {
- GPIO_PF4, /* rdwr_pin */
- GPIO_PF5, /* convert_pin */
- GPIO_PF7, /* busy_pin */
- 0,
-};
-
-static struct bfin5xx_spi_chip ad7816_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_ADT7310)
-static unsigned long adt7310_platform_data[3] = {
-/* INT bound temperature alarm event. line 1 */
- IRQ_PG4, IRQF_TRIGGER_LOW,
-/* CT bound temperature alarm event irq_flags. line 0 */
- IRQF_TRIGGER_LOW,
-};
-
-static struct bfin5xx_spi_chip adt7310_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_AD7298)
-static unsigned short ad7298_platform_data[] = {
- GPIO_PF7, /* busy_pin */
- 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_ADT7316_SPI)
-static unsigned long adt7316_spi_data[2] = {
- IRQF_TRIGGER_LOW, /* interrupt flags */
- GPIO_PF7, /* ldac_pin, 0 means DAC/LDAC registers control DAC update */
-};
-
-static struct bfin5xx_spi_chip adt7316_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-#define MMC_SPI_CARD_DETECT_INT IRQ_PF5
-
-static int bfin_mmc_spi_init(struct device *dev,
- irqreturn_t (*detect_int)(int, void *), void *data)
-{
- return request_irq(MMC_SPI_CARD_DETECT_INT, detect_int,
- IRQF_TRIGGER_FALLING, "mmc-spi-detect", data);
-}
-
-static void bfin_mmc_spi_exit(struct device *dev, void *data)
-{
- free_irq(MMC_SPI_CARD_DETECT_INT, data);
-}
-
-static struct mmc_spi_platform_data bfin_mmc_spi_pdata = {
- .init = bfin_mmc_spi_init,
- .exit = bfin_mmc_spi_exit,
- .detect_delay = 100, /* msecs */
-};
-
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0,
- .pio_interrupt = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
-#include <linux/spi/ad7877.h>
-static const struct ad7877_platform_data bfin_ad7877_ts_info = {
- .model = 7877,
- .vref_delay_usecs = 50, /* internal, no capacitor */
- .x_plate_ohms = 419,
- .y_plate_ohms = 486,
- .pressure_max = 1000,
- .pressure_min = 0,
- .stopacq_polarity = 1,
- .first_conversion_delay = 3,
- .acquisition_time = 1,
- .averaging = 1,
- .pen_down_acc_interval = 1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879)
-#include <linux/platform_data/ad7879.h>
-static const struct ad7879_platform_data bfin_ad7879_ts_info = {
- .model = 7879, /* Model = AD7879 */
- .x_plate_ohms = 620, /* 620 Ohm from the touch datasheet */
- .pressure_max = 10000,
- .pressure_min = 0,
- .first_conversion_delay = 3, /* wait 512us before do a first conversion */
- .acquisition_time = 1, /* 4us acquisition time per sample */
- .median = 2, /* do 8 measurements */
- .averaging = 1, /* take the average of 4 middle samples */
- .pen_down_acc_interval = 255, /* 9.4 ms */
- .gpio_export = 1, /* Export GPIO to gpiolib */
- .gpio_base = -1, /* Dynamic allocation */
-};
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_ADXL34X)
-#include <linux/input/adxl34x.h>
-static const struct adxl34x_platform_data adxl34x_info = {
- .x_axis_offset = 0,
- .y_axis_offset = 0,
- .z_axis_offset = 0,
- .tap_threshold = 0x31,
- .tap_duration = 0x10,
- .tap_latency = 0x60,
- .tap_window = 0xF0,
- .tap_axis_control = ADXL_TAP_X_EN | ADXL_TAP_Y_EN | ADXL_TAP_Z_EN,
- .act_axis_control = 0xFF,
- .activity_threshold = 5,
- .inactivity_threshold = 3,
- .inactivity_time = 4,
- .free_fall_threshold = 0x7,
- .free_fall_time = 0x20,
- .data_rate = 0x8,
- .data_range = ADXL_FULL_RES,
-
- .ev_type = EV_ABS,
- .ev_code_x = ABS_X, /* EV_REL */
- .ev_code_y = ABS_Y, /* EV_REL */
- .ev_code_z = ABS_Z, /* EV_REL */
-
- .ev_code_tap = {BTN_TOUCH, BTN_TOUCH, BTN_TOUCH}, /* EV_KEY x,y,z */
-
-/* .ev_code_ff = KEY_F,*/ /* EV_KEY */
-/* .ev_code_act_inactivity = KEY_A,*/ /* EV_KEY */
- .power_mode = ADXL_AUTO_SLEEP | ADXL_LINK,
- .fifo_mode = ADXL_FIFO_STREAM,
- .orientation_enable = ADXL_EN_ORIENTATION_3D,
- .deadzone_angle = ADXL_DEADZONE_ANGLE_10p8,
- .divisor_length = ADXL_LP_FILTER_DIVISOR_16,
- /* EV_KEY {+Z, +Y, +X, -X, -Y, -Z} */
- .ev_codes_orient_3d = {BTN_Z, BTN_Y, BTN_X, BTN_A, BTN_B, BTN_C},
-};
-#endif
-
-#if IS_ENABLED(CONFIG_ENC28J60)
-static struct bfin5xx_spi_chip enc28j60_spi_chip_info = {
- .enable_dma = 1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_ADF702X)
-#include <linux/spi/adf702x.h>
-#define TXREG 0x0160A470
-static const u32 adf7021_regs[] = {
- 0x09608FA0,
- 0x00575011,
- 0x00A7F092,
- 0x2B141563,
- 0x81F29E94,
- 0x00003155,
- 0x050A4F66,
- 0x00000007,
- 0x00000008,
- 0x000231E9,
- 0x3296354A,
- 0x891A2B3B,
- 0x00000D9C,
- 0x0000000D,
- 0x0000000E,
- 0x0000000F,
-};
-
-static struct adf702x_platform_data adf7021_platform_data = {
- .regs_base = (void *)SPORT1_TCR1,
- .dma_ch_rx = CH_SPORT1_RX,
- .dma_ch_tx = CH_SPORT1_TX,
- .irq_sport_err = IRQ_SPORT1_ERROR,
- .gpio_int_rfs = GPIO_PF8,
- .pin_req = {P_SPORT1_DTPRI, P_SPORT1_RFS, P_SPORT1_DRPRI,
- P_SPORT1_RSCLK, P_SPORT1_TSCLK, 0},
- .adf702x_model = MODEL_ADF7021,
- .adf702x_regs = adf7021_regs,
- .tx_reg = TXREG,
-};
-static inline void adf702x_mac_init(void)
-{
- eth_random_addr(adf7021_platform_data.mac_addr);
-}
-#else
-static inline void adf702x_mac_init(void) {}
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_ADS7846)
-#include <linux/spi/ads7846.h>
-static int ads7873_get_pendown_state(void)
-{
- return gpio_get_value(GPIO_PF6);
-}
-
-static struct ads7846_platform_data __initdata ad7873_pdata = {
- .model = 7873, /* AD7873 */
- .x_max = 0xfff,
- .y_max = 0xfff,
- .x_plate_ohms = 620,
- .debounce_max = 1,
- .debounce_rep = 0,
- .debounce_tol = (~0),
- .get_pendown_state = ads7873_get_pendown_state,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_DATAFLASH)
-
-static struct mtd_partition bfin_spi_dataflash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00040000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = 0x180000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(spi)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct flash_platform_data bfin_spi_dataflash_data = {
- .name = "SPI Dataflash",
- .parts = bfin_spi_dataflash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_dataflash_partitions),
-};
-
-/* DataFlash chip */
-static struct bfin5xx_spi_chip data_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_AD7476)
-static struct bfin5xx_spi_chip spi_ad7476_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_MTD_DATAFLASH)
- { /* DataFlash chip */
- .modalias = "mtd_dataflash",
- .max_speed_hz = 33250000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
- .platform_data = &bfin_spi_dataflash_data,
- .controller_data = &data_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
- {
- .modalias = "ad1836",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 4,
- .platform_data = "ad1836", /* only includes chip name for the moment */
- .mode = SPI_MODE_3,
- },
-#endif
-
-#ifdef CONFIG_SND_SOC_AD193X_SPI
- {
- .modalias = "ad193x",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SND_SOC_ADAV80X)
- {
- .modalias = "adav801",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_AD714X_SPI)
- {
- .modalias = "ad714x_captouch",
- .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
- .irq = IRQ_PF4,
- .bus_num = 0,
- .chip_select = 5,
- .mode = SPI_MODE_3,
- .platform_data = &ad7147_spi_platform_data,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_AD2S90)
- {
- .modalias = "ad2s90",
- .bus_num = 0,
- .chip_select = 3, /* change it for your board */
- .mode = SPI_MODE_3,
- .platform_data = NULL,
- .controller_data = &ad2s90_spi_chip_info,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_AD2S1200)
- {
- .modalias = "ad2s1200",
- .bus_num = 0,
- .chip_select = 4, /* CS, change it for your board */
- .platform_data = ad2s1200_platform_data,
- .controller_data = &ad2s1200_spi_chip_info,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_AD2S1210)
- {
- .modalias = "ad2s1210",
- .max_speed_hz = 8192000,
- .bus_num = 0,
- .chip_select = 4, /* CS, change it for your board */
- .platform_data = ad2s1210_platform_data,
- .controller_data = &ad2s1210_spi_chip_info,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SENSORS_AD7314)
- {
- .modalias = "ad7314",
- .max_speed_hz = 1000000,
- .bus_num = 0,
- .chip_select = 4, /* CS, change it for your board */
- .controller_data = &ad7314_spi_chip_info,
- .mode = SPI_MODE_1,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_AD7816)
- {
- .modalias = "ad7818",
- .max_speed_hz = 1000000,
- .bus_num = 0,
- .chip_select = 4, /* CS, change it for your board */
- .platform_data = ad7816_platform_data,
- .controller_data = &ad7816_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_ADT7310)
- {
- .modalias = "adt7310",
- .max_speed_hz = 1000000,
- .irq = IRQ_PG5, /* CT alarm event. Line 0 */
- .bus_num = 0,
- .chip_select = 4, /* CS, change it for your board */
- .platform_data = adt7310_platform_data,
- .controller_data = &adt7310_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_AD7298)
- {
- .modalias = "ad7298",
- .max_speed_hz = 1000000,
- .bus_num = 0,
- .chip_select = 4, /* CS, change it for your board */
- .platform_data = ad7298_platform_data,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_ADT7316_SPI)
- {
- .modalias = "adt7316",
- .max_speed_hz = 1000000,
- .irq = IRQ_PG5, /* interrupt line */
- .bus_num = 0,
- .chip_select = 4, /* CS, change it for your board */
- .platform_data = adt7316_spi_data,
- .controller_data = &adt7316_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 4,
- .platform_data = &bfin_mmc_spi_pdata,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
- {
- .modalias = "ad7877",
- .platform_data = &bfin_ad7877_ts_info,
- .irq = IRQ_PF6,
- .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879_SPI)
- {
- .modalias = "ad7879",
- .platform_data = &bfin_ad7879_ts_info,
- .irq = IRQ_PF7,
- .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- .mode = SPI_CPHA | SPI_CPOL,
- },
-#endif
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- },
-#endif
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
- {
- .modalias = "bfin-lq035q1-spi",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 2,
- .mode = SPI_CPHA | SPI_CPOL,
- },
-#endif
-#if IS_ENABLED(CONFIG_ENC28J60)
- {
- .modalias = "enc28j60",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .irq = IRQ_PF6,
- .bus_num = 0,
- .chip_select = GPIO_PF10 + MAX_CTRL_CS, /* GPIO controlled SSEL */
- .controller_data = &enc28j60_spi_chip_info,
- .mode = SPI_MODE_0,
- },
-#endif
-#if IS_ENABLED(CONFIG_INPUT_ADXL34X_SPI)
- {
- .modalias = "adxl34x",
- .platform_data = &adxl34x_info,
- .irq = IRQ_PF6,
- .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 2,
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADF702X)
- {
- .modalias = "adf702x",
- .max_speed_hz = 16000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = GPIO_PF10 + MAX_CTRL_CS, /* GPIO controlled SSEL */
- .platform_data = &adf7021_platform_data,
- .mode = SPI_MODE_0,
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_ADS7846)
- {
- .modalias = "ads7846",
- .max_speed_hz = 2000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .irq = IRQ_PF6,
- .chip_select = GPIO_PF10 + MAX_CTRL_CS, /* GPIO controlled SSEL */
- .platform_data = &ad7873_pdata,
- .mode = SPI_MODE_0,
- },
-#endif
-#if IS_ENABLED(CONFIG_AD7476)
- {
- .modalias = "ad7476", /* Name of spi_driver for this device */
- .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 1, /* Framework chip select. */
- .platform_data = NULL, /* No spi_driver specific config */
- .controller_data = &spi_ad7476_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADE7753)
- {
- .modalias = "ade7753",
- .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1, /* CS, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_1,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADE7754)
- {
- .modalias = "ade7754",
- .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1, /* CS, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_1,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADE7758)
- {
- .modalias = "ade7758",
- .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1, /* CS, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_1,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADE7759)
- {
- .modalias = "ade7759",
- .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1, /* CS, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_1,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADE7854_SPI)
- {
- .modalias = "ade7854",
- .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1, /* CS, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADIS16060)
- {
- .modalias = "adis16060_r",
- .max_speed_hz = 2900000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = MAX_CTRL_CS + 1, /* CS for read, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_0,
- },
- {
- .modalias = "adis16060_w",
- .max_speed_hz = 2900000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 2, /* CS for write, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_1,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADIS16130)
- {
- .modalias = "adis16130",
- .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1, /* CS for read, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADIS16201)
- {
- .modalias = "adis16201",
- .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5, /* CS, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_3,
- .irq = IRQ_PF4,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADIS16203)
- {
- .modalias = "adis16203",
- .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5, /* CS, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_3,
- .irq = IRQ_PF4,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADIS16204)
- {
- .modalias = "adis16204",
- .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5, /* CS, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_3,
- .irq = IRQ_PF4,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADIS16209)
- {
- .modalias = "adis16209",
- .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5, /* CS, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_3,
- .irq = IRQ_PF4,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADIS16220)
- {
- .modalias = "adis16220",
- .max_speed_hz = 2000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5, /* CS, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_3,
- .irq = IRQ_PF4,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADIS16240)
- {
- .modalias = "adis16240",
- .max_speed_hz = 1500000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5, /* CS, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_3,
- .irq = IRQ_PF4,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADIS16260)
- {
- .modalias = "adis16260",
- .max_speed_hz = 1500000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5, /* CS, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_3,
- .irq = IRQ_PF4,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADIS16261)
- {
- .modalias = "adis16261",
- .max_speed_hz = 2500000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1, /* CS, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADIS16300)
- {
- .modalias = "adis16300",
- .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5, /* CS, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_3,
- .irq = IRQ_PF4,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADIS16350)
- {
- .modalias = "adis16364",
- .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5, /* CS, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_3,
- .irq = IRQ_PF4,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADIS16400)
- {
- .modalias = "adis16400",
- .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1, /* CS, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_3,
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_SPI_BFIN_SPORT)
-
-/* SPORT SPI controller data */
-static struct bfin5xx_spi_master bfin_sport_spi0_info = {
- .num_chipselect = MAX_BLACKFIN_GPIOS,
- .enable_dma = 0, /* master don't support DMA */
- .pin_req = {P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_DRPRI,
- P_SPORT0_RSCLK, P_SPORT0_TFS, P_SPORT0_RFS, 0},
-};
-
-static struct resource bfin_sport_spi0_resource[] = {
- [0] = {
- .start = SPORT0_TCR1,
- .end = SPORT0_TCR1 + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_sport_spi0_device = {
- .name = "bfin-sport-spi",
- .id = 1, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_sport_spi0_resource),
- .resource = bfin_sport_spi0_resource,
- .dev = {
- .platform_data = &bfin_sport_spi0_info, /* Passed to driver */
- },
-};
-
-static struct bfin5xx_spi_master bfin_sport_spi1_info = {
- .num_chipselect = MAX_BLACKFIN_GPIOS,
- .enable_dma = 0, /* master don't support DMA */
- .pin_req = {P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_DRPRI,
- P_SPORT1_RSCLK, P_SPORT1_TFS, P_SPORT1_RFS, 0},
-};
-
-static struct resource bfin_sport_spi1_resource[] = {
- [0] = {
- .start = SPORT1_TCR1,
- .end = SPORT1_TCR1 + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_sport_spi1_device = {
- .name = "bfin-sport-spi",
- .id = 2, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_sport_spi1_resource),
- .resource = bfin_sport_spi1_resource,
- .dev = {
- .platform_data = &bfin_sport_spi1_info, /* Passed to driver */
- },
-};
-
-#endif /* sport spi master and devices */
-
-#if IS_ENABLED(CONFIG_FB_BF537_LQ035)
-static struct platform_device bfin_fb_device = {
- .name = "bf537_lq035",
-};
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
-#include <asm/bfin-lq035q1.h>
-
-static struct bfin_lq035q1fb_disp_info bfin_lq035q1_data = {
- .mode = LQ035_NORM | LQ035_RGB | LQ035_RL | LQ035_TB,
- .ppi_mode = USE_RGB565_16_BIT_PPI,
- .use_bl = 0, /* let something else control the LCD Blacklight */
- .gpio_bl = GPIO_PF7,
-};
-
-static struct resource bfin_lq035q1_resources[] = {
- {
- .start = IRQ_PPI_ERROR,
- .end = IRQ_PPI_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_lq035q1_device = {
- .name = "bfin-lq035q1",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_lq035q1_resources),
- .resource = bfin_lq035q1_resources,
- .dev = {
- .platform_data = &bfin_lq035q1_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_CAPTURE)
-#include <linux/videodev2.h>
-#include <media/blackfin/bfin_capture.h>
-#include <media/blackfin/ppi.h>
-
-static const unsigned short ppi_req[] = {
- P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
- P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
- P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
- 0,
-};
-
-static const struct ppi_info ppi_info = {
- .type = PPI_TYPE_PPI,
- .dma_ch = CH_PPI,
- .irq_err = IRQ_PPI_ERROR,
- .base = (void __iomem *)PPI_CONTROL,
- .pin_req = ppi_req,
-};
-
-#if IS_ENABLED(CONFIG_VIDEO_VS6624)
-static struct v4l2_input vs6624_inputs[] = {
- {
- .index = 0,
- .name = "Camera",
- .type = V4L2_INPUT_TYPE_CAMERA,
- .std = V4L2_STD_UNKNOWN,
- },
-};
-
-static struct bcap_route vs6624_routes[] = {
- {
- .input = 0,
- .output = 0,
- },
-};
-
-static const unsigned vs6624_ce_pin = GPIO_PF10;
-
-static struct bfin_capture_config bfin_capture_data = {
- .card_name = "BF537",
- .inputs = vs6624_inputs,
- .num_inputs = ARRAY_SIZE(vs6624_inputs),
- .routes = vs6624_routes,
- .i2c_adapter_id = 0,
- .board_info = {
- .type = "vs6624",
- .addr = 0x10,
- .platform_data = (void *)&vs6624_ce_pin,
- },
- .ppi_info = &ppi_info,
- .ppi_control = (PACK_EN | DLEN_8 | XFR_TYPE | 0x0020),
-};
-#endif
-
-static struct platform_device bfin_capture_device = {
- .name = "bfin_capture",
- .dev = {
- .platform_data = &bfin_capture_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_THR,
- .end = UART0_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-#ifdef CONFIG_BFIN_UART0_CTSRTS
- { /* CTS pin */
- .start = GPIO_PG7,
- .end = GPIO_PG7,
- .flags = IORESOURCE_IO,
- },
- { /* RTS pin */
- .start = GPIO_PG6,
- .end = GPIO_PG6,
- .flags = IORESOURCE_IO,
- },
-#endif
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_THR,
- .end = UART1_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX, 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_REGBASE,
- .end = TWI0_REGBASE,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI,
- .end = IRQ_TWI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_ADP5588)
-static const unsigned short adp5588_keymap[ADP5588_KEYMAPSIZE] = {
- [0] = KEY_GRAVE,
- [1] = KEY_1,
- [2] = KEY_2,
- [3] = KEY_3,
- [4] = KEY_4,
- [5] = KEY_5,
- [6] = KEY_6,
- [7] = KEY_7,
- [8] = KEY_8,
- [9] = KEY_9,
- [10] = KEY_0,
- [11] = KEY_MINUS,
- [12] = KEY_EQUAL,
- [13] = KEY_BACKSLASH,
- [15] = KEY_KP0,
- [16] = KEY_Q,
- [17] = KEY_W,
- [18] = KEY_E,
- [19] = KEY_R,
- [20] = KEY_T,
- [21] = KEY_Y,
- [22] = KEY_U,
- [23] = KEY_I,
- [24] = KEY_O,
- [25] = KEY_P,
- [26] = KEY_LEFTBRACE,
- [27] = KEY_RIGHTBRACE,
- [29] = KEY_KP1,
- [30] = KEY_KP2,
- [31] = KEY_KP3,
- [32] = KEY_A,
- [33] = KEY_S,
- [34] = KEY_D,
- [35] = KEY_F,
- [36] = KEY_G,
- [37] = KEY_H,
- [38] = KEY_J,
- [39] = KEY_K,
- [40] = KEY_L,
- [41] = KEY_SEMICOLON,
- [42] = KEY_APOSTROPHE,
- [43] = KEY_BACKSLASH,
- [45] = KEY_KP4,
- [46] = KEY_KP5,
- [47] = KEY_KP6,
- [48] = KEY_102ND,
- [49] = KEY_Z,
- [50] = KEY_X,
- [51] = KEY_C,
- [52] = KEY_V,
- [53] = KEY_B,
- [54] = KEY_N,
- [55] = KEY_M,
- [56] = KEY_COMMA,
- [57] = KEY_DOT,
- [58] = KEY_SLASH,
- [60] = KEY_KPDOT,
- [61] = KEY_KP7,
- [62] = KEY_KP8,
- [63] = KEY_KP9,
- [64] = KEY_SPACE,
- [65] = KEY_BACKSPACE,
- [66] = KEY_TAB,
- [67] = KEY_KPENTER,
- [68] = KEY_ENTER,
- [69] = KEY_ESC,
- [70] = KEY_DELETE,
- [74] = KEY_KPMINUS,
- [76] = KEY_UP,
- [77] = KEY_DOWN,
- [78] = KEY_RIGHT,
- [79] = KEY_LEFT,
-};
-
-static struct adp5588_kpad_platform_data adp5588_kpad_data = {
- .rows = 8,
- .cols = 10,
- .keymap = adp5588_keymap,
- .keymapsize = ARRAY_SIZE(adp5588_keymap),
- .repeat = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_PMIC_ADP5520)
-#include <linux/mfd/adp5520.h>
-
- /*
- * ADP5520/5501 Backlight Data
- */
-
-static struct adp5520_backlight_platform_data adp5520_backlight_data = {
- .fade_in = ADP5520_FADE_T_1200ms,
- .fade_out = ADP5520_FADE_T_1200ms,
- .fade_led_law = ADP5520_BL_LAW_LINEAR,
- .en_ambl_sens = 1,
- .abml_filt = ADP5520_BL_AMBL_FILT_640ms,
- .l1_daylight_max = ADP5520_BL_CUR_mA(15),
- .l1_daylight_dim = ADP5520_BL_CUR_mA(0),
- .l2_office_max = ADP5520_BL_CUR_mA(7),
- .l2_office_dim = ADP5520_BL_CUR_mA(0),
- .l3_dark_max = ADP5520_BL_CUR_mA(3),
- .l3_dark_dim = ADP5520_BL_CUR_mA(0),
- .l2_trip = ADP5520_L2_COMP_CURR_uA(700),
- .l2_hyst = ADP5520_L2_COMP_CURR_uA(50),
- .l3_trip = ADP5520_L3_COMP_CURR_uA(80),
- .l3_hyst = ADP5520_L3_COMP_CURR_uA(20),
-};
-
- /*
- * ADP5520/5501 LEDs Data
- */
-
-static struct led_info adp5520_leds[] = {
- {
- .name = "adp5520-led1",
- .default_trigger = "none",
- .flags = FLAG_ID_ADP5520_LED1_ADP5501_LED0 | ADP5520_LED_OFFT_600ms,
- },
-#ifdef ADP5520_EN_ALL_LEDS
- {
- .name = "adp5520-led2",
- .default_trigger = "none",
- .flags = FLAG_ID_ADP5520_LED2_ADP5501_LED1,
- },
- {
- .name = "adp5520-led3",
- .default_trigger = "none",
- .flags = FLAG_ID_ADP5520_LED3_ADP5501_LED2,
- },
-#endif
-};
-
-static struct adp5520_leds_platform_data adp5520_leds_data = {
- .num_leds = ARRAY_SIZE(adp5520_leds),
- .leds = adp5520_leds,
- .fade_in = ADP5520_FADE_T_600ms,
- .fade_out = ADP5520_FADE_T_600ms,
- .led_on_time = ADP5520_LED_ONT_600ms,
-};
-
- /*
- * ADP5520 GPIO Data
- */
-
-static struct adp5520_gpio_platform_data adp5520_gpio_data = {
- .gpio_start = 50,
- .gpio_en_mask = ADP5520_GPIO_C1 | ADP5520_GPIO_C2 | ADP5520_GPIO_R2,
- .gpio_pullup_mask = ADP5520_GPIO_C1 | ADP5520_GPIO_C2 | ADP5520_GPIO_R2,
-};
-
- /*
- * ADP5520 Keypad Data
- */
-
-static const unsigned short adp5520_keymap[ADP5520_KEYMAPSIZE] = {
- [ADP5520_KEY(0, 0)] = KEY_GRAVE,
- [ADP5520_KEY(0, 1)] = KEY_1,
- [ADP5520_KEY(0, 2)] = KEY_2,
- [ADP5520_KEY(0, 3)] = KEY_3,
- [ADP5520_KEY(1, 0)] = KEY_4,
- [ADP5520_KEY(1, 1)] = KEY_5,
- [ADP5520_KEY(1, 2)] = KEY_6,
- [ADP5520_KEY(1, 3)] = KEY_7,
- [ADP5520_KEY(2, 0)] = KEY_8,
- [ADP5520_KEY(2, 1)] = KEY_9,
- [ADP5520_KEY(2, 2)] = KEY_0,
- [ADP5520_KEY(2, 3)] = KEY_MINUS,
- [ADP5520_KEY(3, 0)] = KEY_EQUAL,
- [ADP5520_KEY(3, 1)] = KEY_BACKSLASH,
- [ADP5520_KEY(3, 2)] = KEY_BACKSPACE,
- [ADP5520_KEY(3, 3)] = KEY_ENTER,
-};
-
-static struct adp5520_keys_platform_data adp5520_keys_data = {
- .rows_en_mask = ADP5520_ROW_R3 | ADP5520_ROW_R2 | ADP5520_ROW_R1 | ADP5520_ROW_R0,
- .cols_en_mask = ADP5520_COL_C3 | ADP5520_COL_C2 | ADP5520_COL_C1 | ADP5520_COL_C0,
- .keymap = adp5520_keymap,
- .keymapsize = ARRAY_SIZE(adp5520_keymap),
- .repeat = 0,
-};
-
- /*
- * ADP5520/5501 Multifunction Device Init Data
- */
-
-static struct adp5520_platform_data adp5520_pdev_data = {
- .backlight = &adp5520_backlight_data,
- .leds = &adp5520_leds_data,
- .gpio = &adp5520_gpio_data,
- .keys = &adp5520_keys_data,
-};
-
-#endif
-
-#if IS_ENABLED(CONFIG_GPIO_ADP5588)
-static struct adp5588_gpio_platform_data adp5588_gpio_data = {
- .gpio_start = 50,
- .pullup_dis_mask = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_BACKLIGHT_ADP8870)
-#include <linux/platform_data/adp8870.h>
-static struct led_info adp8870_leds[] = {
- {
- .name = "adp8870-led7",
- .default_trigger = "none",
- .flags = ADP8870_LED_D7 | ADP8870_LED_OFFT_600ms,
- },
-};
-
-
-static struct adp8870_backlight_platform_data adp8870_pdata = {
- .bl_led_assign = ADP8870_BL_D1 | ADP8870_BL_D2 | ADP8870_BL_D3 |
- ADP8870_BL_D4 | ADP8870_BL_D5 | ADP8870_BL_D6, /* 1 = Backlight 0 = Individual LED */
- .pwm_assign = 0, /* 1 = Enables PWM mode */
-
- .bl_fade_in = ADP8870_FADE_T_1200ms, /* Backlight Fade-In Timer */
- .bl_fade_out = ADP8870_FADE_T_1200ms, /* Backlight Fade-Out Timer */
- .bl_fade_law = ADP8870_FADE_LAW_CUBIC1, /* fade-on/fade-off transfer characteristic */
-
- .en_ambl_sens = 1, /* 1 = enable ambient light sensor */
- .abml_filt = ADP8870_BL_AMBL_FILT_320ms, /* Light sensor filter time */
-
- .l1_daylight_max = ADP8870_BL_CUR_mA(20), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
- .l1_daylight_dim = ADP8870_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
- .l2_bright_max = ADP8870_BL_CUR_mA(14), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
- .l2_bright_dim = ADP8870_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
- .l3_office_max = ADP8870_BL_CUR_mA(6), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
- .l3_office_dim = ADP8870_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
- .l4_indoor_max = ADP8870_BL_CUR_mA(3), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
- .l4_indor_dim = ADP8870_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
- .l5_dark_max = ADP8870_BL_CUR_mA(2), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
- .l5_dark_dim = ADP8870_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
-
- .l2_trip = ADP8870_L2_COMP_CURR_uA(710), /* use L2_COMP_CURR_uA(I) 0 <= I <= 1106 uA */
- .l2_hyst = ADP8870_L2_COMP_CURR_uA(73), /* use L2_COMP_CURR_uA(I) 0 <= I <= 1106 uA */
- .l3_trip = ADP8870_L3_COMP_CURR_uA(389), /* use L3_COMP_CURR_uA(I) 0 <= I <= 551 uA */
- .l3_hyst = ADP8870_L3_COMP_CURR_uA(54), /* use L3_COMP_CURR_uA(I) 0 <= I <= 551 uA */
- .l4_trip = ADP8870_L4_COMP_CURR_uA(167), /* use L4_COMP_CURR_uA(I) 0 <= I <= 275 uA */
- .l4_hyst = ADP8870_L4_COMP_CURR_uA(16), /* use L4_COMP_CURR_uA(I) 0 <= I <= 275 uA */
- .l5_trip = ADP8870_L5_COMP_CURR_uA(43), /* use L5_COMP_CURR_uA(I) 0 <= I <= 138 uA */
- .l5_hyst = ADP8870_L5_COMP_CURR_uA(11), /* use L6_COMP_CURR_uA(I) 0 <= I <= 138 uA */
-
- .leds = adp8870_leds,
- .num_leds = ARRAY_SIZE(adp8870_leds),
- .led_fade_law = ADP8870_FADE_LAW_SQUARE, /* fade-on/fade-off transfer characteristic */
- .led_fade_in = ADP8870_FADE_T_600ms,
- .led_fade_out = ADP8870_FADE_T_600ms,
- .led_on_time = ADP8870_LED_ONT_200ms,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_BACKLIGHT_ADP8860)
-#include <linux/platform_data/adp8860.h>
-static struct led_info adp8860_leds[] = {
- {
- .name = "adp8860-led7",
- .default_trigger = "none",
- .flags = ADP8860_LED_D7 | ADP8860_LED_OFFT_600ms,
- },
-};
-
-static struct adp8860_backlight_platform_data adp8860_pdata = {
- .bl_led_assign = ADP8860_BL_D1 | ADP8860_BL_D2 | ADP8860_BL_D3 |
- ADP8860_BL_D4 | ADP8860_BL_D5 | ADP8860_BL_D6, /* 1 = Backlight 0 = Individual LED */
-
- .bl_fade_in = ADP8860_FADE_T_1200ms, /* Backlight Fade-In Timer */
- .bl_fade_out = ADP8860_FADE_T_1200ms, /* Backlight Fade-Out Timer */
- .bl_fade_law = ADP8860_FADE_LAW_CUBIC1, /* fade-on/fade-off transfer characteristic */
-
- .en_ambl_sens = 1, /* 1 = enable ambient light sensor */
- .abml_filt = ADP8860_BL_AMBL_FILT_320ms, /* Light sensor filter time */
-
- .l1_daylight_max = ADP8860_BL_CUR_mA(20), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
- .l1_daylight_dim = ADP8860_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
- .l2_office_max = ADP8860_BL_CUR_mA(6), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
- .l2_office_dim = ADP8860_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
- .l3_dark_max = ADP8860_BL_CUR_mA(2), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
- .l3_dark_dim = ADP8860_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
-
- .l2_trip = ADP8860_L2_COMP_CURR_uA(710), /* use L2_COMP_CURR_uA(I) 0 <= I <= 1106 uA */
- .l2_hyst = ADP8860_L2_COMP_CURR_uA(73), /* use L2_COMP_CURR_uA(I) 0 <= I <= 1106 uA */
- .l3_trip = ADP8860_L3_COMP_CURR_uA(43), /* use L3_COMP_CURR_uA(I) 0 <= I <= 138 uA */
- .l3_hyst = ADP8860_L3_COMP_CURR_uA(11), /* use L3_COMP_CURR_uA(I) 0 <= I <= 138 uA */
-
- .leds = adp8860_leds,
- .num_leds = ARRAY_SIZE(adp8860_leds),
- .led_fade_law = ADP8860_FADE_LAW_SQUARE, /* fade-on/fade-off transfer characteristic */
- .led_fade_in = ADP8860_FADE_T_600ms,
- .led_fade_out = ADP8860_FADE_T_600ms,
- .led_on_time = ADP8860_LED_ONT_200ms,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_REGULATOR_AD5398)
-static struct regulator_consumer_supply ad5398_consumer = {
- .supply = "current",
-};
-
-static struct regulator_init_data ad5398_regulator_data = {
- .constraints = {
- .name = "current range",
- .max_uA = 120000,
- .valid_ops_mask = REGULATOR_CHANGE_CURRENT | REGULATOR_CHANGE_STATUS,
- },
- .num_consumer_supplies = 1,
- .consumer_supplies = &ad5398_consumer,
-};
-
-#if IS_ENABLED(CONFIG_REGULATOR_VIRTUAL_CONSUMER)
-static struct platform_device ad5398_virt_consumer_device = {
- .name = "reg-virt-consumer",
- .id = 0,
- .dev = {
- .platform_data = "current", /* Passed to driver */
- },
-};
-#endif
-#if IS_ENABLED(CONFIG_REGULATOR_USERSPACE_CONSUMER)
-static struct regulator_bulk_data ad5398_bulk_data = {
- .supply = "current",
-};
-
-static struct regulator_userspace_consumer_data ad5398_userspace_comsumer_data = {
- .name = "ad5398",
- .num_supplies = 1,
- .supplies = &ad5398_bulk_data,
-};
-
-static struct platform_device ad5398_userspace_consumer_device = {
- .name = "reg-userspace-consumer",
- .id = 0,
- .dev = {
- .platform_data = &ad5398_userspace_comsumer_data,
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_ADT7410)
-/* INT bound temperature alarm event. line 1 */
-static unsigned long adt7410_platform_data[2] = {
- IRQ_PG4, IRQF_TRIGGER_LOW,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_ADT7316_I2C)
-/* INT bound temperature alarm event. line 1 */
-static unsigned long adt7316_i2c_data[2] = {
- IRQF_TRIGGER_LOW, /* interrupt flags */
- GPIO_PF4, /* ldac_pin, 0 means DAC/LDAC registers control DAC update */
-};
-#endif
-
-static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
-#ifdef CONFIG_SND_SOC_AD193X_I2C
- {
- I2C_BOARD_INFO("ad1937", 0x04),
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SND_SOC_ADAV80X)
- {
- I2C_BOARD_INFO("adav803", 0x10),
- },
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_AD714X_I2C)
- {
- I2C_BOARD_INFO("ad7142_captouch", 0x2C),
- .irq = IRQ_PG5,
- .platform_data = (void *)&ad7142_i2c_platform_data,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_AD7150)
- {
- I2C_BOARD_INFO("ad7150", 0x48),
- .irq = IRQ_PG5, /* fixme: use real interrupt number */
- },
-#endif
-
-#if IS_ENABLED(CONFIG_AD7152)
- {
- I2C_BOARD_INFO("ad7152", 0x48),
- },
-#endif
-
-#if IS_ENABLED(CONFIG_AD774X)
- {
- I2C_BOARD_INFO("ad774x", 0x48),
- },
-#endif
-
-#if IS_ENABLED(CONFIG_ADE7854_I2C)
- {
- I2C_BOARD_INFO("ade7854", 0x38),
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SENSORS_LM75)
- {
- I2C_BOARD_INFO("adt75", 0x9),
- .irq = IRQ_PG5,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_ADT7410)
- {
- I2C_BOARD_INFO("adt7410", 0x48),
- /* CT critical temperature event. line 0 */
- .irq = IRQ_PG5,
- .platform_data = (void *)&adt7410_platform_data,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_AD7291)
- {
- I2C_BOARD_INFO("ad7291", 0x20),
- .irq = IRQ_PG5,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_ADT7316_I2C)
- {
- I2C_BOARD_INFO("adt7316", 0x48),
- .irq = IRQ_PG6,
- .platform_data = (void *)&adt7316_i2c_data,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
- {
- I2C_BOARD_INFO("pcf8574_lcd", 0x22),
- },
-#endif
-#if IS_ENABLED(CONFIG_INPUT_PCF8574)
- {
- I2C_BOARD_INFO("pcf8574_keypad", 0x27),
- .irq = IRQ_PG6,
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879_I2C)
- {
- I2C_BOARD_INFO("ad7879", 0x2F),
- .irq = IRQ_PG5,
- .platform_data = (void *)&bfin_ad7879_ts_info,
- },
-#endif
-#if IS_ENABLED(CONFIG_KEYBOARD_ADP5588)
- {
- I2C_BOARD_INFO("adp5588-keys", 0x34),
- .irq = IRQ_PG0,
- .platform_data = (void *)&adp5588_kpad_data,
- },
-#endif
-#if IS_ENABLED(CONFIG_PMIC_ADP5520)
- {
- I2C_BOARD_INFO("pmic-adp5520", 0x32),
- .irq = IRQ_PG0,
- .platform_data = (void *)&adp5520_pdev_data,
- },
-#endif
-#if IS_ENABLED(CONFIG_INPUT_ADXL34X_I2C)
- {
- I2C_BOARD_INFO("adxl34x", 0x53),
- .irq = IRQ_PG3,
- .platform_data = (void *)&adxl34x_info,
- },
-#endif
-#if IS_ENABLED(CONFIG_GPIO_ADP5588)
- {
- I2C_BOARD_INFO("adp5588-gpio", 0x34),
- .platform_data = (void *)&adp5588_gpio_data,
- },
-#endif
-#if IS_ENABLED(CONFIG_FB_BFIN_7393)
- {
- I2C_BOARD_INFO("bfin-adv7393", 0x2B),
- },
-#endif
-#if IS_ENABLED(CONFIG_FB_BF537_LQ035)
- {
- I2C_BOARD_INFO("bf537-lq035-ad5280", 0x2F),
- },
-#endif
-#if IS_ENABLED(CONFIG_BACKLIGHT_ADP8870)
- {
- I2C_BOARD_INFO("adp8870", 0x2B),
- .platform_data = (void *)&adp8870_pdata,
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_ADAU1371)
- {
- I2C_BOARD_INFO("adau1371", 0x1A),
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_ADAU1761)
- {
- I2C_BOARD_INFO("adau1761", 0x38),
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_ADAU1361)
- {
- I2C_BOARD_INFO("adau1361", 0x38),
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_ADAU1701)
- {
- I2C_BOARD_INFO("adau1701", 0x34),
- },
-#endif
-#if IS_ENABLED(CONFIG_AD525X_DPOT)
- {
- I2C_BOARD_INFO("ad5258", 0x18),
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_SSM2602)
- {
- I2C_BOARD_INFO("ssm2602", 0x1b),
- },
-#endif
-#if IS_ENABLED(CONFIG_REGULATOR_AD5398)
- {
- I2C_BOARD_INFO("ad5398", 0xC),
- .platform_data = (void *)&ad5398_regulator_data,
- },
-#endif
-#if IS_ENABLED(CONFIG_BACKLIGHT_ADP8860)
- {
- I2C_BOARD_INFO("adp8860", 0x2A),
- .platform_data = (void *)&adp8860_pdata,
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_ADAU1373)
- {
- I2C_BOARD_INFO("adau1373", 0x1A),
- },
-#endif
-#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
- {
- I2C_BOARD_INFO("ad5252", 0x2e),
- },
-#endif
-};
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) \
-|| IS_ENABLED(CONFIG_BFIN_SPORT)
-unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
-};
-#endif
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-#if IS_ENABLED(CONFIG_BFIN_SPORT)
-static struct resource bfin_sport0_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_TX,
- .end = IRQ_SPORT0_TX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_SPORT0_TX,
- .end = CH_SPORT0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_SPORT0_RX,
- .end = CH_SPORT0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sport0_device = {
- .name = "bfin_sport_raw",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_resources),
- .resource = bfin_sport0_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#if IS_ENABLED(CONFIG_PATA_PLATFORM)
-#define CF_IDE_NAND_CARD_USE_HDD_INTERFACE
-/* #define CF_IDE_NAND_CARD_USE_CF_IN_COMMON_MEMORY_MODE */
-
-#ifdef CF_IDE_NAND_CARD_USE_HDD_INTERFACE
-#define PATA_INT IRQ_PF5
-static struct pata_platform_info bfin_pata_platform_data = {
- .ioport_shift = 1,
-};
-
-static struct resource bfin_pata_resources[] = {
- {
- .start = 0x20314020,
- .end = 0x2031403F,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = 0x2031401C,
- .end = 0x2031401F,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = PATA_INT,
- .end = PATA_INT,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-#elif defined(CF_IDE_NAND_CARD_USE_CF_IN_COMMON_MEMORY_MODE)
-static struct pata_platform_info bfin_pata_platform_data = {
- .ioport_shift = 0,
-};
-/* CompactFlash Storage Card Memory Mapped Addressing
- * /REG = A11 = 1
- */
-static struct resource bfin_pata_resources[] = {
- {
- .start = 0x20211800,
- .end = 0x20211807,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = 0x2021180E, /* Device Ctl */
- .end = 0x2021180E,
- .flags = IORESOURCE_MEM,
- },
-};
-#endif
-
-static struct platform_device bfin_pata_device = {
- .name = "pata_platform",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_pata_resources),
- .resource = bfin_pata_resources,
- .dev = {
- .platform_data = &bfin_pata_platform_data,
- }
-};
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
- VRPAIR(VLEV_085, 250000000),
- VRPAIR(VLEV_090, 376000000),
- VRPAIR(VLEV_095, 426000000),
- VRPAIR(VLEV_100, 426000000),
- VRPAIR(VLEV_105, 476000000),
- VRPAIR(VLEV_110, 476000000),
- VRPAIR(VLEV_115, 476000000),
- VRPAIR(VLEV_120, 500000000),
- VRPAIR(VLEV_125, 533000000),
- VRPAIR(VLEV_130, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S) || \
- IS_ENABLED(CONFIG_SND_BF5XX_AC97)
-
-#define SPORT_REQ(x) \
- [x] = {P_SPORT##x##_TFS, P_SPORT##x##_DTPRI, P_SPORT##x##_TSCLK, \
- P_SPORT##x##_RFS, P_SPORT##x##_DRPRI, P_SPORT##x##_RSCLK, 0}
-
-static const u16 bfin_snd_pin[][7] = {
- SPORT_REQ(0),
- SPORT_REQ(1),
-};
-
-static struct bfin_snd_platform_data bfin_snd_data[] = {
- {
- .pin_req = &bfin_snd_pin[0][0],
- },
- {
- .pin_req = &bfin_snd_pin[1][0],
- },
-};
-
-#define BFIN_SND_RES(x) \
- [x] = { \
- { \
- .start = SPORT##x##_TCR1, \
- .end = SPORT##x##_TCR1, \
- .flags = IORESOURCE_MEM \
- }, \
- { \
- .start = CH_SPORT##x##_RX, \
- .end = CH_SPORT##x##_RX, \
- .flags = IORESOURCE_DMA, \
- }, \
- { \
- .start = CH_SPORT##x##_TX, \
- .end = CH_SPORT##x##_TX, \
- .flags = IORESOURCE_DMA, \
- }, \
- { \
- .start = IRQ_SPORT##x##_ERROR, \
- .end = IRQ_SPORT##x##_ERROR, \
- .flags = IORESOURCE_IRQ, \
- } \
- }
-
-static struct resource bfin_snd_resources[][4] = {
- BFIN_SND_RES(0),
- BFIN_SND_RES(1),
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
-static struct platform_device bfin_i2s_pcm = {
- .name = "bfin-i2s-pcm-audio",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
-static struct platform_device bfin_ac97_pcm = {
- .name = "bfin-ac97-pcm-audio",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
-static const char * const ad1836_link[] = {
- "bfin-i2s.0",
- "spi0.4",
-};
-static struct platform_device bfin_ad1836_machine = {
- .name = "bfin-snd-ad1836",
- .id = -1,
- .dev = {
- .platform_data = (void *)ad1836_link,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD73311)
-static const unsigned ad73311_gpio[] = {
- GPIO_PF4,
-};
-
-static struct platform_device bfin_ad73311_machine = {
- .name = "bfin-snd-ad73311",
- .id = 1,
- .dev = {
- .platform_data = (void *)ad73311_gpio,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_SOC_AD73311)
-static struct platform_device bfin_ad73311_codec_device = {
- .name = "ad73311",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAV80X)
-static struct platform_device bfin_eval_adav801_device = {
- .name = "bfin-eval-adav801",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_I2S)
-static struct platform_device bfin_i2s = {
- .name = "bfin-i2s",
- .id = CONFIG_SND_BF5XX_SPORT_NUM,
- .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
- .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
- .dev = {
- .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AC97)
-static struct platform_device bfin_ac97 = {
- .name = "bfin-ac97",
- .id = CONFIG_SND_BF5XX_SPORT_NUM,
- .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
- .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
- .dev = {
- .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_REGULATOR_FIXED_VOLTAGE)
-#define REGULATOR_ADP122 "adp122"
-#define REGULATOR_ADP122_UV 2500000
-
-static struct regulator_consumer_supply adp122_consumers = {
- .supply = REGULATOR_ADP122,
-};
-
-static struct regulator_init_data adp_switch_regulator_data = {
- .constraints = {
- .name = REGULATOR_ADP122,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS,
- .min_uV = REGULATOR_ADP122_UV,
- .max_uV = REGULATOR_ADP122_UV,
- .min_uA = 0,
- .max_uA = 300000,
- },
- .num_consumer_supplies = 1, /* only 1 */
- .consumer_supplies = &adp122_consumers,
-};
-
-static struct fixed_voltage_config adp_switch_pdata = {
- .supply_name = REGULATOR_ADP122,
- .microvolts = REGULATOR_ADP122_UV,
- .gpio = GPIO_PF2,
- .enable_high = 1,
- .enabled_at_boot = 0,
- .init_data = &adp_switch_regulator_data,
-};
-
-static struct platform_device adp_switch_device = {
- .name = "reg-fixed-voltage",
- .id = 0,
- .dev = {
- .platform_data = &adp_switch_pdata,
- },
-};
-
-#if IS_ENABLED(CONFIG_REGULATOR_USERSPACE_CONSUMER)
-static struct regulator_bulk_data adp122_bulk_data = {
- .supply = REGULATOR_ADP122,
-};
-
-static struct regulator_userspace_consumer_data adp122_userspace_comsumer_data = {
- .name = REGULATOR_ADP122,
- .num_supplies = 1,
- .supplies = &adp122_bulk_data,
-};
-
-static struct platform_device adp122_userspace_consumer_device = {
- .name = "reg-userspace-consumer",
- .id = 0,
- .dev = {
- .platform_data = &adp122_userspace_comsumer_data,
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_IIO_GPIO_TRIGGER)
-
-static struct resource iio_gpio_trigger_resources[] = {
- [0] = {
- .start = IRQ_PF5,
- .end = IRQ_PF5,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
- },
-};
-
-static struct platform_device iio_gpio_trigger = {
- .name = "iio_gpio_trigger",
- .num_resources = ARRAY_SIZE(iio_gpio_trigger_resources),
- .resource = iio_gpio_trigger_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAU1373)
-static struct platform_device bf5xx_adau1373_device = {
- .name = "bfin-eval-adau1373",
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAU1701)
-static struct platform_device bf5xx_adau1701_device = {
- .name = "bfin-eval-adau1701",
-};
-#endif
-
-static struct platform_device *stamp_devices[] __initdata = {
-
- &bfin_dpmc,
-#if IS_ENABLED(CONFIG_BFIN_SPORT)
- &bfin_sport0_device,
-#endif
-#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA)
- &bfin_pcmcia_cf_device,
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_SL811_HCD)
- &sl811_hcd_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
- &isp1362_hcd_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
- &bfin_isp1760_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
- &smc91x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_DM9000)
- &dm9000_device,
-#endif
-
-#if IS_ENABLED(CONFIG_CAN_BFIN)
- &bfin_can_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
- &bfin_mii_bus,
- &bfin_mac_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
- &net2272_bfin_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN_SPORT)
- &bfin_sport_spi0_device,
- &bfin_sport_spi1_device,
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BF537_LQ035)
- &bfin_fb_device,
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
- &bfin_lq035q1_device,
-#endif
-
-#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_CAPTURE)
- &bfin_capture_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_PATA_PLATFORM)
- &bfin_pata_device,
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
- &bfin_device_gpiokeys,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_NAND_PLATFORM)
- &bfin_async_nand_device,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
- &stamp_flash_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
- &bfin_i2s_pcm,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
- &bfin_ac97_pcm,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
- &bfin_ad1836_machine,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD73311)
- &bfin_ad73311_machine,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_SOC_AD73311)
- &bfin_ad73311_codec_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_I2S)
- &bfin_i2s,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AC97)
- &bfin_ac97,
-#endif
-
-#if IS_ENABLED(CONFIG_REGULATOR_AD5398)
-#if IS_ENABLED(CONFIG_REGULATOR_VIRTUAL_CONSUMER)
- &ad5398_virt_consumer_device,
-#endif
-#if IS_ENABLED(CONFIG_REGULATOR_USERSPACE_CONSUMER)
- &ad5398_userspace_consumer_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_REGULATOR_FIXED_VOLTAGE)
- &adp_switch_device,
-#if IS_ENABLED(CONFIG_REGULATOR_USERSPACE_CONSUMER)
- &adp122_userspace_consumer_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_IIO_GPIO_TRIGGER)
- &iio_gpio_trigger,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAU1373)
- &bf5xx_adau1373_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAU1701)
- &bf5xx_adau1701_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAV80X)
- &bfin_eval_adav801_device,
-#endif
-};
-
-static int __init net2272_init(void)
-{
-#if IS_ENABLED(CONFIG_USB_NET2272)
- int ret;
-
- ret = gpio_request(GPIO_PF6, "net2272");
- if (ret)
- return ret;
-
- /* Reset the USB chip */
- gpio_direction_output(GPIO_PF6, 0);
- mdelay(2);
- gpio_set_value(GPIO_PF6, 1);
-#endif
-
- return 0;
-}
-
-static int __init stamp_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- bfin_plat_nand_init();
- adf702x_mac_init();
- platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
- i2c_register_board_info(0, bfin_i2c_board_info,
- ARRAY_SIZE(bfin_i2c_board_info));
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
-
- if (net2272_init())
- pr_warning("unable to configure net2272; it probably won't work\n");
-
- return 0;
-}
-
-arch_initcall(stamp_init);
-
-
-static struct platform_device *stamp_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(stamp_early_devices,
- ARRAY_SIZE(stamp_early_devices));
-}
-
-void native_machine_restart(char *cmd)
-{
- /* workaround reboot hang when booting from SPI */
- if ((bfin_read_SYSCR() & 0x7) == 0x3)
- bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
-}
-
-/*
- * Currently the MAC address is saved in Flash by U-Boot
- */
-#define FLASH_MAC 0x203f0000
-int bfin_get_ether_addr(char *addr)
-{
- *(u32 *)(&(addr[0])) = bfin_read32(FLASH_MAC);
- *(u16 *)(&(addr[4])) = bfin_read16(FLASH_MAC + 4);
- return 0;
-}
-EXPORT_SYMBOL(bfin_get_ether_addr);
+++ /dev/null
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2008-2009 Bluetechnix
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/etherdevice.h>
-#include <linux/export.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-#include <linux/usb/isp1362.h>
-#endif
-#include <linux/ata_platform.h>
-#include <linux/irq.h>
-#include <linux/gpio.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-#include <linux/spi/mmc_spi.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "Bluetechnix TCM BF537";
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* all SPI peripherals info goes here */
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00020000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = 0xe0000,
- .offset = 0x20000
- }, {
- .name = "file system(spi)",
- .size = 0x700000,
- .offset = 0x00100000,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p64",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
- {
- .modalias = "ad183x",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 4,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-};
-
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_FB_HITACHI_TX09)
-static struct platform_device hitachi_fb_device = {
- .name = "hitachi-tx09",
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
-#include <linux/smc91x.h>
-
-static struct smc91x_platdata smc91x_info = {
- .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
- .leda = RPC_LED_100_10,
- .ledb = RPC_LED_TX_RX,
-};
-
-static struct resource smc91x_resources[] = {
- {
- .start = 0x20200300,
- .end = 0x20200300 + 16,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF14,
- .end = IRQ_PF14,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev = {
- .platform_data = &smc91x_info,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-static struct resource isp1362_hcd_resources[] = {
- {
- .start = 0x20308000,
- .end = 0x20308000,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 0x20308004,
- .end = 0x20308004,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PG15,
- .end = IRQ_PG15,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
- },
-};
-
-static struct isp1362_platform_data isp1362_priv = {
- .sel15Kres = 1,
- .clknotstop = 0,
- .oc_enable = 0,
- .int_act_high = 0,
- .int_edge_triggered = 0,
- .remote_wakeup_connected = 0,
- .no_power_switching = 1,
- .power_switching_mode = 0,
-};
-
-static struct platform_device isp1362_hcd_device = {
- .name = "isp1362-hcd",
- .id = 0,
- .dev = {
- .platform_data = &isp1362_priv,
- },
- .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
- .resource = isp1362_hcd_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
-static struct resource net2272_bfin_resources[] = {
- {
- .start = 0x20300000,
- .end = 0x20300000 + 0x100,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PG13,
- .end = IRQ_PG13,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device net2272_bfin_device = {
- .name = "net2272",
- .id = -1,
- .num_resources = ARRAY_SIZE(net2272_bfin_resources),
- .resource = net2272_bfin_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR)
-static struct mtd_partition cm_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x40000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0x100000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct physmap_flash_data cm_flash_data = {
- .width = 2,
- .parts = cm_partitions,
- .nr_parts = ARRAY_SIZE(cm_partitions),
-};
-
-static unsigned cm_flash_gpios[] = { GPIO_PF4, GPIO_PF5 };
-
-static struct resource cm_flash_resource[] = {
- {
- .name = "cfi_probe",
- .start = 0x20000000,
- .end = 0x201fffff,
- .flags = IORESOURCE_MEM,
- }, {
- .start = (unsigned long)cm_flash_gpios,
- .end = ARRAY_SIZE(cm_flash_gpios),
- .flags = IORESOURCE_IRQ,
- }
-};
-
-static struct platform_device cm_flash_device = {
- .name = "gpio-addr-flash",
- .id = 0,
- .dev = {
- .platform_data = &cm_flash_data,
- },
- .num_resources = ARRAY_SIZE(cm_flash_resource),
- .resource = cm_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_THR,
- .end = UART0_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_THR,
- .end = UART1_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX, 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_REGBASE,
- .end = TWI0_REGBASE,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI,
- .end = IRQ_TWI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
-#include <linux/bfin_mac.h>
-static const unsigned short bfin_mac_peripherals[] = P_MII0;
-
-static struct bfin_phydev_platform_data bfin_phydev_data[] = {
- {
- .addr = 1,
- .irq = IRQ_MAC_PHYINT,
- },
-};
-
-static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
- .phydev_number = 1,
- .phydev_data = bfin_phydev_data,
- .phy_mode = PHY_INTERFACE_MODE_MII,
- .mac_peripherals = bfin_mac_peripherals,
-};
-
-static struct platform_device bfin_mii_bus = {
- .name = "bfin_mii_bus",
- .dev = {
- .platform_data = &bfin_mii_bus_data,
- }
-};
-
-static struct platform_device bfin_mac_device = {
- .name = "bfin_mac",
- .dev = {
- .platform_data = &bfin_mii_bus,
- }
-};
-#endif
-
-#if IS_ENABLED(CONFIG_PATA_PLATFORM)
-#define PATA_INT IRQ_PF14
-
-static struct pata_platform_info bfin_pata_platform_data = {
- .ioport_shift = 2,
-};
-
-static struct resource bfin_pata_resources[] = {
- {
- .start = 0x2030C000,
- .end = 0x2030C01F,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = 0x2030D018,
- .end = 0x2030D01B,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = PATA_INT,
- .end = PATA_INT,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device bfin_pata_device = {
- .name = "pata_platform",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_pata_resources),
- .resource = bfin_pata_resources,
- .dev = {
- .platform_data = &bfin_pata_platform_data,
- }
-};
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
- VRPAIR(VLEV_085, 250000000),
- VRPAIR(VLEV_090, 376000000),
- VRPAIR(VLEV_095, 426000000),
- VRPAIR(VLEV_100, 426000000),
- VRPAIR(VLEV_105, 476000000),
- VRPAIR(VLEV_110, 476000000),
- VRPAIR(VLEV_115, 476000000),
- VRPAIR(VLEV_120, 500000000),
- VRPAIR(VLEV_125, 533000000),
- VRPAIR(VLEV_130, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-static struct platform_device *cm_bf537_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_FB_HITACHI_TX09)
- &hitachi_fb_device,
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
- &isp1362_hcd_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
- &smc91x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
- &bfin_mii_bus,
- &bfin_mac_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
- &net2272_bfin_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_PATA_PLATFORM)
- &bfin_pata_device,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR)
- &cm_flash_device,
-#endif
-};
-
-static int __init net2272_init(void)
-{
-#if IS_ENABLED(CONFIG_USB_NET2272)
- int ret;
-
- ret = gpio_request(GPIO_PG14, "net2272");
- if (ret)
- return ret;
-
- /* Reset USB Chip, PG14 */
- gpio_direction_output(GPIO_PG14, 0);
- mdelay(2);
- gpio_set_value(GPIO_PG14, 1);
-#endif
-
- return 0;
-}
-
-static int __init tcm_bf537_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- platform_add_devices(cm_bf537_devices, ARRAY_SIZE(cm_bf537_devices));
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
-#endif
-
-#if IS_ENABLED(CONFIG_PATA_PLATFORM)
- irq_set_status_flags(PATA_INT, IRQ_NOAUTOEN);
-#endif
-
- if (net2272_init())
- pr_warning("unable to configure net2272; it probably won't work\n");
-
- return 0;
-}
-
-arch_initcall(tcm_bf537_init);
-
-static struct platform_device *cm_bf537_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(cm_bf537_early_devices,
- ARRAY_SIZE(cm_bf537_early_devices));
-}
-
-int bfin_get_ether_addr(char *addr)
-{
- return 1;
-}
-EXPORT_SYMBOL(bfin_get_ether_addr);
+++ /dev/null
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- *
- * This file contains the simple DMA Implementation for Blackfin
- */
-
-#include <linux/module.h>
-
-#include <asm/blackfin.h>
-#include <asm/dma.h>
-
-struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
- (struct dma_register *) DMA0_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_NEXT_DESC_PTR,
- (struct dma_register *) DMA3_NEXT_DESC_PTR,
- (struct dma_register *) DMA4_NEXT_DESC_PTR,
- (struct dma_register *) DMA5_NEXT_DESC_PTR,
- (struct dma_register *) DMA6_NEXT_DESC_PTR,
- (struct dma_register *) DMA7_NEXT_DESC_PTR,
- (struct dma_register *) DMA8_NEXT_DESC_PTR,
- (struct dma_register *) DMA9_NEXT_DESC_PTR,
- (struct dma_register *) DMA10_NEXT_DESC_PTR,
- (struct dma_register *) DMA11_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
-};
-EXPORT_SYMBOL(dma_io_base_addr);
-
-int channel2irq(unsigned int channel)
-{
- int ret_irq = -1;
-
- switch (channel) {
- case CH_PPI:
- ret_irq = IRQ_PPI;
- break;
-
- case CH_EMAC_RX:
- ret_irq = IRQ_MAC_RX;
- break;
-
- case CH_EMAC_TX:
- ret_irq = IRQ_MAC_TX;
- break;
-
- case CH_UART1_RX:
- ret_irq = IRQ_UART1_RX;
- break;
-
- case CH_UART1_TX:
- ret_irq = IRQ_UART1_TX;
- break;
-
- case CH_SPORT0_RX:
- ret_irq = IRQ_SPORT0_RX;
- break;
-
- case CH_SPORT0_TX:
- ret_irq = IRQ_SPORT0_TX;
- break;
-
- case CH_SPORT1_RX:
- ret_irq = IRQ_SPORT1_RX;
- break;
-
- case CH_SPORT1_TX:
- ret_irq = IRQ_SPORT1_TX;
- break;
-
- case CH_SPI:
- ret_irq = IRQ_SPI;
- break;
-
- case CH_UART0_RX:
- ret_irq = IRQ_UART0_RX;
- break;
-
- case CH_UART0_TX:
- ret_irq = IRQ_UART0_TX;
- break;
-
- case CH_MEM_STREAM0_SRC:
- case CH_MEM_STREAM0_DEST:
- ret_irq = IRQ_MEM_DMA0;
- break;
-
- case CH_MEM_STREAM1_SRC:
- case CH_MEM_STREAM1_DEST:
- ret_irq = IRQ_MEM_DMA1;
- break;
- }
- return ret_irq;
-}
+++ /dev/null
-/*
- * DO NOT EDIT THIS FILE
- * This file is under version control at
- * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
- * and can be replaced with that version at any time
- * DO NOT EDIT THIS FILE
- *
- * Copyright 2004-2011 Analog Devices Inc.
- * Licensed under the Clear BSD license.
- */
-
-/* This file should be up to date with:
- * - Revision F, 05/23/2011; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
- */
-
-#ifndef _MACH_ANOMALY_H_
-#define _MACH_ANOMALY_H_
-
-/* We do not support 0.1 silicon - sorry */
-#if __SILICON_REVISION__ < 2
-# error will not work on BF537 silicon version 0.0 or 0.1
-#endif
-
-#if defined(__ADSPBF534__)
-# define ANOMALY_BF534 1
-#else
-# define ANOMALY_BF534 0
-#endif
-#if defined(__ADSPBF536__)
-# define ANOMALY_BF536 1
-#else
-# define ANOMALY_BF536 0
-#endif
-#if defined(__ADSPBF537__)
-# define ANOMALY_BF537 1
-#else
-# define ANOMALY_BF537 0
-#endif
-
-/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
-#define ANOMALY_05000074 (1)
-/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
-#define ANOMALY_05000119 (1)
-/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
-#define ANOMALY_05000122 (1)
-/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
-#define ANOMALY_05000180 (1)
-/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
-#define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
-/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
-#define ANOMALY_05000245 (1)
-/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
-#define ANOMALY_05000250 (__SILICON_REVISION__ < 3)
-/* EMAC TX DMA Error After an Early Frame Abort */
-#define ANOMALY_05000252 (__SILICON_REVISION__ < 3)
-/* Maximum External Clock Speed for Timers */
-#define ANOMALY_05000253 (__SILICON_REVISION__ < 3)
-/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
-#define ANOMALY_05000254 (__SILICON_REVISION__ > 2)
-/* Entering Hibernate State with RTC Seconds Interrupt Not Functional */
-#define ANOMALY_05000255 (__SILICON_REVISION__ < 3)
-/* EMAC MDIO Input Latched on Wrong MDC Edge */
-#define ANOMALY_05000256 (__SILICON_REVISION__ < 3)
-/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */
-#define ANOMALY_05000257 (__SILICON_REVISION__ < 3)
-/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */
-#define ANOMALY_05000258 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ == 1) || __SILICON_REVISION__ == 2)
-/* ICPLB_STATUS MMR Register May Be Corrupted */
-#define ANOMALY_05000260 (__SILICON_REVISION__ == 2)
-/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
-#define ANOMALY_05000261 (__SILICON_REVISION__ < 3)
-/* Stores To Data Cache May Be Lost */
-#define ANOMALY_05000262 (__SILICON_REVISION__ < 3)
-/* Hardware Loop Corrupted When Taking an ICPLB Exception */
-#define ANOMALY_05000263 (__SILICON_REVISION__ == 2)
-/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */
-#define ANOMALY_05000264 (__SILICON_REVISION__ < 3)
-/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
-#define ANOMALY_05000265 (1)
-/* Memory DMA Error when Peripheral DMA Is Running with Non-Zero DEB_TRAFFIC_PERIOD */
-#define ANOMALY_05000268 (__SILICON_REVISION__ < 3)
-/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
-#define ANOMALY_05000270 (__SILICON_REVISION__ < 3)
-/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
-#define ANOMALY_05000272 (1)
-/* Writes to Synchronous SDRAM Memory May Be Lost */
-#define ANOMALY_05000273 (__SILICON_REVISION__ < 3)
-/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
-#define ANOMALY_05000277 (__SILICON_REVISION__ < 3)
-/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
-#define ANOMALY_05000278 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ < 3) || (ANOMALY_BF534 && __SILICON_REVISION__ < 2))
-/* SPI Master Boot Mode Does Not Work Well with Atmel Data Flash Devices */
-#define ANOMALY_05000280 (1)
-/* False Hardware Error when ISR Context Is Not Restored */
-#define ANOMALY_05000281 (__SILICON_REVISION__ < 3)
-/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
-#define ANOMALY_05000282 (__SILICON_REVISION__ < 3)
-/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */
-#define ANOMALY_05000283 (__SILICON_REVISION__ < 3)
-/* TXDWA Bit in EMAC_SYSCTL Register Is Not Functional */
-#define ANOMALY_05000285 (__SILICON_REVISION__ < 3)
-/* SPORTs May Receive Bad Data If FIFOs Fill Up */
-#define ANOMALY_05000288 (__SILICON_REVISION__ < 3)
-/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
-#define ANOMALY_05000301 (1)
-/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
-#define ANOMALY_05000304 (__SILICON_REVISION__ < 3)
-/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */
-#define ANOMALY_05000305 (__SILICON_REVISION__ < 3)
-/* SCKELOW Bit Does Not Maintain State Through Hibernate */
-#define ANOMALY_05000307 (__SILICON_REVISION__ < 3)
-/* Writing UART_THR While UART Clock Is Disabled Sends Erroneous Start Bit */
-#define ANOMALY_05000309 (__SILICON_REVISION__ < 3)
-/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
-#define ANOMALY_05000310 (1)
-/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
-#define ANOMALY_05000312 (1)
-/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
-#define ANOMALY_05000313 (1)
-/* Killed System MMR Write Completes Erroneously on Next System MMR Access */
-#define ANOMALY_05000315 (__SILICON_REVISION__ < 3)
-/* EMAC RMII Mode: Collisions Occur in Full Duplex Mode */
-#define ANOMALY_05000316 (__SILICON_REVISION__ < 3)
-/* EMAC RMII Mode: TX Frames in Half Duplex Fail with Status "No Carrier" */
-#define ANOMALY_05000321 (__SILICON_REVISION__ < 3)
-/* EMAC RMII Mode at 10-Base-T Speed: RX Frames Not Received Properly */
-#define ANOMALY_05000322 (1)
-/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
-#define ANOMALY_05000341 (__SILICON_REVISION__ >= 3)
-/* UART Gets Disabled after UART Boot */
-#define ANOMALY_05000350 (__SILICON_REVISION__ >= 3)
-/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
-#define ANOMALY_05000355 (1)
-/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
-#define ANOMALY_05000357 (1)
-/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
-#define ANOMALY_05000359 (1)
-/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
-#define ANOMALY_05000366 (1)
-/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
-#define ANOMALY_05000371 (1)
-/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
-#define ANOMALY_05000402 (__SILICON_REVISION__ == 2)
-/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
-#define ANOMALY_05000403 (1)
-/* Speculative Fetches Can Cause Undesired External FIFO Operations */
-#define ANOMALY_05000416 (1)
-/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
-#define ANOMALY_05000425 (1)
-/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
-#define ANOMALY_05000426 (1)
-/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
-#define ANOMALY_05000443 (1)
-/* False Hardware Error when RETI Points to Invalid Memory */
-#define ANOMALY_05000461 (1)
-/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
-#define ANOMALY_05000462 (1)
-/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
-#define ANOMALY_05000473 (1)
-/* Possible Lockup Condition when Modifying PLL from External Memory */
-#define ANOMALY_05000475 (1)
-/* TESTSET Instruction Cannot Be Interrupted */
-#define ANOMALY_05000477 (1)
-/* Multiple Simultaneous Urgent DMA Requests May Cause DMA System Instability */
-#define ANOMALY_05000480 (__SILICON_REVISION__ < 3)
-/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
-#define ANOMALY_05000481 (1)
-/* PLL May Latch Incorrect Values Coming Out of Reset */
-#define ANOMALY_05000489 (1)
-/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
-#define ANOMALY_05000491 (1)
-/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
-#define ANOMALY_05000494 (1)
-/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
-#define ANOMALY_05000501 (1)
-
-/*
- * These anomalies have been "phased" out of analog.com anomaly sheets and are
- * here to show running on older silicon just isn't feasible.
- */
-
-/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
-#define ANOMALY_05000157 (__SILICON_REVISION__ < 2)
-/* Instruction Cache Is Not Functional */
-#define ANOMALY_05000237 (__SILICON_REVISION__ < 2)
-/* Buffered CLKIN Output Is Disabled by Default */
-#define ANOMALY_05000247 (__SILICON_REVISION__ < 2)
-
-/* Anomalies that don't exist on this proc */
-#define ANOMALY_05000099 (0)
-#define ANOMALY_05000120 (0)
-#define ANOMALY_05000125 (0)
-#define ANOMALY_05000149 (0)
-#define ANOMALY_05000158 (0)
-#define ANOMALY_05000171 (0)
-#define ANOMALY_05000179 (0)
-#define ANOMALY_05000182 (0)
-#define ANOMALY_05000183 (0)
-#define ANOMALY_05000189 (0)
-#define ANOMALY_05000198 (0)
-#define ANOMALY_05000202 (0)
-#define ANOMALY_05000215 (0)
-#define ANOMALY_05000219 (0)
-#define ANOMALY_05000220 (0)
-#define ANOMALY_05000227 (0)
-#define ANOMALY_05000230 (0)
-#define ANOMALY_05000231 (0)
-#define ANOMALY_05000233 (0)
-#define ANOMALY_05000234 (0)
-#define ANOMALY_05000242 (0)
-#define ANOMALY_05000248 (0)
-#define ANOMALY_05000266 (0)
-#define ANOMALY_05000274 (0)
-#define ANOMALY_05000287 (0)
-#define ANOMALY_05000311 (0)
-#define ANOMALY_05000323 (0)
-#define ANOMALY_05000353 (1)
-#define ANOMALY_05000362 (1)
-#define ANOMALY_05000363 (0)
-#define ANOMALY_05000364 (0)
-#define ANOMALY_05000380 (0)
-#define ANOMALY_05000383 (0)
-#define ANOMALY_05000386 (1)
-#define ANOMALY_05000389 (0)
-#define ANOMALY_05000400 (0)
-#define ANOMALY_05000412 (0)
-#define ANOMALY_05000430 (0)
-#define ANOMALY_05000432 (0)
-#define ANOMALY_05000435 (0)
-#define ANOMALY_05000440 (0)
-#define ANOMALY_05000447 (0)
-#define ANOMALY_05000448 (0)
-#define ANOMALY_05000456 (0)
-#define ANOMALY_05000450 (0)
-#define ANOMALY_05000465 (0)
-#define ANOMALY_05000467 (0)
-#define ANOMALY_05000474 (0)
-#define ANOMALY_05000485 (0)
-#define ANOMALY_16000030 (0)
-
-#endif
+++ /dev/null
-/*
- * System MMR Register and memory map for ADSP-BF537
- *
- * Copyright 2005-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __MACH_BF537_H__
-#define __MACH_BF537_H__
-
-#define OFFSET_(x) ((x) & 0x0000FFFF)
-
-/*some misc defines*/
-#define IMASK_IVG15 0x8000
-#define IMASK_IVG14 0x4000
-#define IMASK_IVG13 0x2000
-#define IMASK_IVG12 0x1000
-
-#define IMASK_IVG11 0x0800
-#define IMASK_IVG10 0x0400
-#define IMASK_IVG9 0x0200
-#define IMASK_IVG8 0x0100
-
-#define IMASK_IVG7 0x0080
-#define IMASK_IVGTMR 0x0040
-#define IMASK_IVGHW 0x0020
-
-/***************************/
-
-
-#define BFIN_DSUBBANKS 4
-#define BFIN_DWAYS 2
-#define BFIN_DLINES 64
-#define BFIN_ISUBBANKS 4
-#define BFIN_IWAYS 4
-#define BFIN_ILINES 32
-
-#define WAY0_L 0x1
-#define WAY1_L 0x2
-#define WAY01_L 0x3
-#define WAY2_L 0x4
-#define WAY02_L 0x5
-#define WAY12_L 0x6
-#define WAY012_L 0x7
-
-#define WAY3_L 0x8
-#define WAY03_L 0x9
-#define WAY13_L 0xA
-#define WAY013_L 0xB
-
-#define WAY32_L 0xC
-#define WAY320_L 0xD
-#define WAY321_L 0xE
-#define WAYALL_L 0xF
-
-#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
-
-/********************************* EBIU Settings ************************************/
-#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
-#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
-
-#ifdef CONFIG_C_AMBEN_ALL
-#define V_AMBEN AMBEN_ALL
-#endif
-#ifdef CONFIG_C_AMBEN
-#define V_AMBEN 0x0
-#endif
-#ifdef CONFIG_C_AMBEN_B0
-#define V_AMBEN AMBEN_B0
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1
-#define V_AMBEN AMBEN_B0_B1
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1_B2
-#define V_AMBEN AMBEN_B0_B1_B2
-#endif
-#ifdef CONFIG_C_AMCKEN
-#define V_AMCKEN AMCKEN
-#else
-#define V_AMCKEN 0x0
-#endif
-#ifdef CONFIG_C_CDPRIO
-#define V_CDPRIO 0x100
-#else
-#define V_CDPRIO 0x0
-#endif
-
-#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO)
-
-#ifdef CONFIG_BF537
-#define CPU "BF537"
-#define CPUID 0x27c8
-#endif
-#ifdef CONFIG_BF536
-#define CPU "BF536"
-#define CPUID 0x27c8
-#endif
-#ifdef CONFIG_BF534
-#define CPU "BF534"
-#define CPUID 0x27c6
-#endif
-
-#ifndef CPU
-#error "Unknown CPU type - This kernel doesn't seem to be configured properly"
-#endif
-
-#endif /* __MACH_BF537_H__ */
+++ /dev/null
-/*
- * mach/bfin_serial.h - Blackfin UART/Serial definitions
- *
- * Copyright 2006-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MACH_SERIAL_H__
-#define __BFIN_MACH_SERIAL_H__
-
-#define BFIN_UART_NR_PORTS 2
-
-#endif
+++ /dev/null
-/*
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_BLACKFIN_H_
-#define _MACH_BLACKFIN_H_
-
-#define BF537_FAMILY
-
-#include "bf537.h"
-#include "anomaly.h"
-
-#include <asm/def_LPBlackfin.h>
-#ifdef CONFIG_BF534
-# include "defBF534.h"
-#endif
-#if defined(CONFIG_BF537) || defined(CONFIG_BF536)
-# include "defBF537.h"
-#endif
-
-#if !defined(__ASSEMBLY__)
-# include <asm/cdef_LPBlackfin.h>
-# ifdef CONFIG_BF534
-# include "cdefBF534.h"
-# endif
-# if defined(CONFIG_BF537) || defined(CONFIG_BF536)
-# include "cdefBF537.h"
-# endif
-#endif
-
-#endif
+++ /dev/null
-/*
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _CDEF_BF534_H
-#define _CDEF_BF534_H
-
-/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
-#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
-#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val)
-#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
-#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val)
-#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val)
-#define bfin_read_CHIPID() bfin_read32(CHIPID)
-
-/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
-#define bfin_read_SWRST() bfin_read16(SWRST)
-#define bfin_write_SWRST(val) bfin_write16(SWRST,val)
-#define bfin_read_SYSCR() bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val) bfin_write16(SYSCR,val)
-#define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT)
-#define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT,val)
-#define bfin_read_SIC_IMASK() bfin_read32(SIC_IMASK)
-#define bfin_write_SIC_IMASK(val) bfin_write32(SIC_IMASK,val)
-#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
-#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0,val)
-#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
-#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1,val)
-#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
-#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2,val)
-#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
-#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3,val)
-#define bfin_read_SIC_ISR() bfin_read32(SIC_ISR)
-#define bfin_write_SIC_ISR(val) bfin_write32(SIC_ISR,val)
-#define bfin_read_SIC_IWR() bfin_read32(SIC_IWR)
-#define bfin_write_SIC_IWR(val) bfin_write32(SIC_IWR,val)
-
-/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
-#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL,val)
-#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT,val)
-#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT,val)
-
-/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
-#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
-#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT,val)
-#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
-#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL,val)
-#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
-#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT,val)
-#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
-#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT,val)
-#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
-#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM,val)
-#define bfin_read_RTC_FAST() bfin_read16(RTC_FAST)
-#define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST,val)
-#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
-#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN,val)
-
-/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
-#define bfin_read_UART0_THR() bfin_read16(UART0_THR)
-#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR,val)
-#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR)
-#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR,val)
-#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL)
-#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL,val)
-#define bfin_read_UART0_IER() bfin_read16(UART0_IER)
-#define bfin_write_UART0_IER(val) bfin_write16(UART0_IER,val)
-#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH)
-#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH,val)
-#define bfin_read_UART0_IIR() bfin_read16(UART0_IIR)
-#define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR,val)
-#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR)
-#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR,val)
-#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR)
-#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR,val)
-#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR)
-#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR,val)
-#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR)
-#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR,val)
-#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR)
-#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR,val)
-#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL)
-#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL,val)
-
-/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
-#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL)
-#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL,val)
-#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG)
-#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG,val)
-#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT)
-#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT,val)
-#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR)
-#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR,val)
-#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR)
-#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR,val)
-#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD)
-#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD,val)
-#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW)
-#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW,val)
-
-/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
-#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG,val)
-#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER,val)
-#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD,val)
-#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH,val)
-
-#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG,val)
-#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER,val)
-#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD,val)
-#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH,val)
-
-#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG,val)
-#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER,val)
-#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD,val)
-#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH,val)
-
-#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
-#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG,val)
-#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
-#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER,val)
-#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
-#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD,val)
-#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
-#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH,val)
-
-#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
-#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG,val)
-#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
-#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER,val)
-#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
-#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD,val)
-#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
-#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH,val)
-
-#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
-#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG,val)
-#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
-#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER,val)
-#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
-#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD,val)
-#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
-#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH,val)
-
-#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
-#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG,val)
-#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
-#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER,val)
-#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
-#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD,val)
-#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
-#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH,val)
-
-#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
-#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG,val)
-#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
-#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER,val)
-#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
-#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD,val)
-#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
-#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH,val)
-
-#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE)
-#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE,val)
-#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE)
-#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE,val)
-#define bfin_read_TIMER_STATUS() bfin_read32(TIMER_STATUS)
-#define bfin_write_TIMER_STATUS(val) bfin_write32(TIMER_STATUS,val)
-
-/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
-#define bfin_read_PORTFIO() bfin_read16(PORTFIO)
-#define bfin_write_PORTFIO(val) bfin_write16(PORTFIO,val)
-#define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR)
-#define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR,val)
-#define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET)
-#define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET,val)
-#define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE)
-#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE,val)
-#define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA)
-#define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA,val)
-#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR)
-#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR,val)
-#define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET)
-#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET,val)
-#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE)
-#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE,val)
-#define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB)
-#define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB,val)
-#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR)
-#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR,val)
-#define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET)
-#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET,val)
-#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE)
-#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE,val)
-#define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR)
-#define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR,val)
-#define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR)
-#define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR,val)
-#define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE)
-#define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE,val)
-#define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH)
-#define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH,val)
-#define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN)
-#define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN,val)
-
-/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
-#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1,val)
-#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2,val)
-#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV,val)
-#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV,val)
-#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX,val)
-#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX,val)
-#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX,val)
-#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX,val)
-#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX)
-#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX,val)
-#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX)
-#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX,val)
-#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1,val)
-#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2,val)
-#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV,val)
-#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV,val)
-#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT,val)
-#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL,val)
-#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1,val)
-#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2,val)
-#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0,val)
-#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1,val)
-#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2,val)
-#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3,val)
-#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0,val)
-#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1,val)
-#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2,val)
-#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3,val)
-
-/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
-#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1,val)
-#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2,val)
-#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV,val)
-#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV,val)
-#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX,val)
-#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX,val)
-#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX,val)
-#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX,val)
-#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX)
-#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX,val)
-#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX)
-#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX,val)
-#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1,val)
-#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2,val)
-#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV,val)
-#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV,val)
-#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT,val)
-#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL,val)
-#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1,val)
-#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2,val)
-#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
-#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0,val)
-#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
-#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1,val)
-#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
-#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2,val)
-#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
-#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3,val)
-#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
-#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0,val)
-#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
-#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1,val)
-#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
-#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2,val)
-#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
-#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3,val)
-
-/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
-#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL,val)
-#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0,val)
-#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1,val)
-#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
-#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL,val)
-#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL)
-#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL,val)
-#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
-#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC,val)
-#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
-#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT,val)
-
-/* DMA Traffic Control Registers */
-#define bfin_read_DMAC_TC_PER() bfin_read16(DMAC_TC_PER)
-#define bfin_write_DMAC_TC_PER(val) bfin_write16(DMAC_TC_PER,val)
-#define bfin_read_DMAC_TC_CNT() bfin_read16(DMAC_TC_CNT)
-#define bfin_write_DMAC_TC_CNT(val) bfin_write16(DMAC_TC_CNT,val)
-
-/* DMA Controller */
-#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
-#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG,val)
-#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR,val)
-#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR,val)
-#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
-#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT,val)
-#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
-#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT,val)
-#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY,val)
-#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY,val)
-#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR,val)
-#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR,val)
-#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
-#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT,val)
-#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
-#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT,val)
-#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
-#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS,val)
-#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
-#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
-#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG,val)
-#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR,val)
-#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
-#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT,val)
-#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
-#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT,val)
-#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY,val)
-#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY,val)
-#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR,val)
-#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
-#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT,val)
-#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
-#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
-#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS,val)
-#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
-#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG,val)
-#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR,val)
-#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
-#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT,val)
-#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
-#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT,val)
-#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY,val)
-#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY,val)
-#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR,val)
-#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
-#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT,val)
-#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
-#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
-#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS,val)
-#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
-#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG,val)
-#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR,val)
-#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR,val)
-#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
-#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT,val)
-#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
-#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT,val)
-#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY,val)
-#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY,val)
-#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR,val)
-#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR,val)
-#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
-#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT,val)
-#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
-#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT,val)
-#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
-#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS,val)
-#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
-#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
-#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG,val)
-#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR,val)
-#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR,val)
-#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
-#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT,val)
-#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
-#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT,val)
-#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY,val)
-#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY,val)
-#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR,val)
-#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR,val)
-#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
-#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT,val)
-#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
-#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT,val)
-#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
-#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS,val)
-#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
-#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
-#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG,val)
-#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR,val)
-#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR,val)
-#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
-#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT,val)
-#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
-#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT,val)
-#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY,val)
-#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY,val)
-#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR,val)
-#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR,val)
-#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
-#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT,val)
-#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
-#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT,val)
-#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
-#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS,val)
-#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
-#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
-#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG,val)
-#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR,val)
-#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR,val)
-#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
-#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT,val)
-#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
-#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT,val)
-#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY,val)
-#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY,val)
-#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR,val)
-#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR,val)
-#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
-#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT,val)
-#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
-#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT,val)
-#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
-#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS,val)
-#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
-#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
-#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG,val)
-#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR,val)
-#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR,val)
-#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
-#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT,val)
-#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
-#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT,val)
-#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY,val)
-#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY,val)
-#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR,val)
-#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR,val)
-#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
-#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT,val)
-#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
-#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT,val)
-#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
-#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS,val)
-#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
-#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG)
-#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG,val)
-#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR)
-#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR,val)
-#define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR)
-#define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR,val)
-#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT)
-#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT,val)
-#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT)
-#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT,val)
-#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY)
-#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY,val)
-#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY)
-#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY,val)
-#define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR)
-#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR,val)
-#define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR)
-#define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR,val)
-#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT)
-#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT,val)
-#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT)
-#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT,val)
-#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
-#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS,val)
-#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
-#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG)
-#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG,val)
-#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR)
-#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR,val)
-#define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR)
-#define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR,val)
-#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT)
-#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT,val)
-#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT)
-#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT,val)
-#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY)
-#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY,val)
-#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY)
-#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY,val)
-#define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR)
-#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR,val)
-#define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR)
-#define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR,val)
-#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT)
-#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT,val)
-#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT)
-#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT,val)
-#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS)
-#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS,val)
-#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
-#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG)
-#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG,val)
-#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR)
-#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR,val)
-#define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR)
-#define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR,val)
-#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT)
-#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT,val)
-#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT)
-#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT,val)
-#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY)
-#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY,val)
-#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY)
-#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY,val)
-#define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR)
-#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR,val)
-#define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR)
-#define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR,val)
-#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
-#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT,val)
-#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
-#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT,val)
-#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS)
-#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS,val)
-#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
-#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG)
-#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG,val)
-#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR)
-#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR,val)
-#define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR)
-#define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR,val)
-#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT)
-#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT,val)
-#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT)
-#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT,val)
-#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY)
-#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY,val)
-#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY)
-#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY,val)
-#define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR)
-#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR,val)
-#define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR)
-#define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR,val)
-#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
-#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT,val)
-#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
-#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT,val)
-#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS)
-#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS,val)
-#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
-#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP,val)
-
-#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
-#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG,val)
-#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR)
-#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR,val)
-#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
-#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT,val)
-#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
-#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT,val)
-#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
-#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY,val)
-#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
-#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY,val)
-#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR)
-#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR,val)
-#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
-#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT,val)
-#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
-#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS,val)
-#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP,val)
-
-#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
-#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG,val)
-#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR)
-#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR,val)
-#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
-#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT,val)
-#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
-#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT,val)
-#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
-#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY,val)
-#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
-#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY,val)
-#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR)
-#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR,val)
-#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
-#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT,val)
-#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
-#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS,val)
-#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP,val)
-
-#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
-#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG,val)
-#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR)
-#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR,val)
-#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
-#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT,val)
-#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
-#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT,val)
-#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
-#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY,val)
-#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
-#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY,val)
-#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR)
-#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR,val)
-#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
-#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT,val)
-#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
-#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS,val)
-#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP,val)
-
-#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
-#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG,val)
-#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR)
-#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR,val)
-#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
-#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT,val)
-#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
-#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT,val)
-#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
-#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY,val)
-#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
-#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY,val)
-#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR)
-#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR,val)
-#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
-#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT,val)
-#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
-#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS,val)
-#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP,val)
-
-/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
-#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL)
-#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL,val)
-#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS)
-#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS,val)
-#define bfin_clear_PPI_STATUS() bfin_write_PPI_STATUS(0xFFFF)
-#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY)
-#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY,val)
-#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT)
-#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT,val)
-#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME)
-#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME,val)
-
-/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
-
-/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
-#define bfin_read_PORTGIO() bfin_read16(PORTGIO)
-#define bfin_write_PORTGIO(val) bfin_write16(PORTGIO,val)
-#define bfin_read_PORTGIO_CLEAR() bfin_read16(PORTGIO_CLEAR)
-#define bfin_write_PORTGIO_CLEAR(val) bfin_write16(PORTGIO_CLEAR,val)
-#define bfin_read_PORTGIO_SET() bfin_read16(PORTGIO_SET)
-#define bfin_write_PORTGIO_SET(val) bfin_write16(PORTGIO_SET,val)
-#define bfin_read_PORTGIO_TOGGLE() bfin_read16(PORTGIO_TOGGLE)
-#define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE,val)
-#define bfin_read_PORTGIO_MASKA() bfin_read16(PORTGIO_MASKA)
-#define bfin_write_PORTGIO_MASKA(val) bfin_write16(PORTGIO_MASKA,val)
-#define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR)
-#define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR,val)
-#define bfin_read_PORTGIO_MASKA_SET() bfin_read16(PORTGIO_MASKA_SET)
-#define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET,val)
-#define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE)
-#define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE,val)
-#define bfin_read_PORTGIO_MASKB() bfin_read16(PORTGIO_MASKB)
-#define bfin_write_PORTGIO_MASKB(val) bfin_write16(PORTGIO_MASKB,val)
-#define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR)
-#define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR,val)
-#define bfin_read_PORTGIO_MASKB_SET() bfin_read16(PORTGIO_MASKB_SET)
-#define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET,val)
-#define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE)
-#define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE,val)
-#define bfin_read_PORTGIO_DIR() bfin_read16(PORTGIO_DIR)
-#define bfin_write_PORTGIO_DIR(val) bfin_write16(PORTGIO_DIR,val)
-#define bfin_read_PORTGIO_POLAR() bfin_read16(PORTGIO_POLAR)
-#define bfin_write_PORTGIO_POLAR(val) bfin_write16(PORTGIO_POLAR,val)
-#define bfin_read_PORTGIO_EDGE() bfin_read16(PORTGIO_EDGE)
-#define bfin_write_PORTGIO_EDGE(val) bfin_write16(PORTGIO_EDGE,val)
-#define bfin_read_PORTGIO_BOTH() bfin_read16(PORTGIO_BOTH)
-#define bfin_write_PORTGIO_BOTH(val) bfin_write16(PORTGIO_BOTH,val)
-#define bfin_read_PORTGIO_INEN() bfin_read16(PORTGIO_INEN)
-#define bfin_write_PORTGIO_INEN(val) bfin_write16(PORTGIO_INEN,val)
-
-/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
-#define bfin_read_PORTHIO() bfin_read16(PORTHIO)
-#define bfin_write_PORTHIO(val) bfin_write16(PORTHIO,val)
-#define bfin_read_PORTHIO_CLEAR() bfin_read16(PORTHIO_CLEAR)
-#define bfin_write_PORTHIO_CLEAR(val) bfin_write16(PORTHIO_CLEAR,val)
-#define bfin_read_PORTHIO_SET() bfin_read16(PORTHIO_SET)
-#define bfin_write_PORTHIO_SET(val) bfin_write16(PORTHIO_SET,val)
-#define bfin_read_PORTHIO_TOGGLE() bfin_read16(PORTHIO_TOGGLE)
-#define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE,val)
-#define bfin_read_PORTHIO_MASKA() bfin_read16(PORTHIO_MASKA)
-#define bfin_write_PORTHIO_MASKA(val) bfin_write16(PORTHIO_MASKA,val)
-#define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR)
-#define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR,val)
-#define bfin_read_PORTHIO_MASKA_SET() bfin_read16(PORTHIO_MASKA_SET)
-#define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET,val)
-#define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE)
-#define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE,val)
-#define bfin_read_PORTHIO_MASKB() bfin_read16(PORTHIO_MASKB)
-#define bfin_write_PORTHIO_MASKB(val) bfin_write16(PORTHIO_MASKB,val)
-#define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR)
-#define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR,val)
-#define bfin_read_PORTHIO_MASKB_SET() bfin_read16(PORTHIO_MASKB_SET)
-#define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET,val)
-#define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE)
-#define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE,val)
-#define bfin_read_PORTHIO_DIR() bfin_read16(PORTHIO_DIR)
-#define bfin_write_PORTHIO_DIR(val) bfin_write16(PORTHIO_DIR,val)
-#define bfin_read_PORTHIO_POLAR() bfin_read16(PORTHIO_POLAR)
-#define bfin_write_PORTHIO_POLAR(val) bfin_write16(PORTHIO_POLAR,val)
-#define bfin_read_PORTHIO_EDGE() bfin_read16(PORTHIO_EDGE)
-#define bfin_write_PORTHIO_EDGE(val) bfin_write16(PORTHIO_EDGE,val)
-#define bfin_read_PORTHIO_BOTH() bfin_read16(PORTHIO_BOTH)
-#define bfin_write_PORTHIO_BOTH(val) bfin_write16(PORTHIO_BOTH,val)
-#define bfin_read_PORTHIO_INEN() bfin_read16(PORTHIO_INEN)
-#define bfin_write_PORTHIO_INEN(val) bfin_write16(PORTHIO_INEN,val)
-
-/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
-#define bfin_read_UART1_THR() bfin_read16(UART1_THR)
-#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR,val)
-#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR)
-#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR,val)
-#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL)
-#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL,val)
-#define bfin_read_UART1_IER() bfin_read16(UART1_IER)
-#define bfin_write_UART1_IER(val) bfin_write16(UART1_IER,val)
-#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH)
-#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH,val)
-#define bfin_read_UART1_IIR() bfin_read16(UART1_IIR)
-#define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR,val)
-#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR)
-#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR,val)
-#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR)
-#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR,val)
-#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR)
-#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR,val)
-#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR)
-#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR,val)
-#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR)
-#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR,val)
-#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL)
-#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL,val)
-
-/* CAN Controller (0xFFC02A00 - 0xFFC02FFF) */
-/* For Mailboxes 0-15 */
-#define bfin_read_CAN_MC1() bfin_read16(CAN_MC1)
-#define bfin_write_CAN_MC1(val) bfin_write16(CAN_MC1,val)
-#define bfin_read_CAN_MD1() bfin_read16(CAN_MD1)
-#define bfin_write_CAN_MD1(val) bfin_write16(CAN_MD1,val)
-#define bfin_read_CAN_TRS1() bfin_read16(CAN_TRS1)
-#define bfin_write_CAN_TRS1(val) bfin_write16(CAN_TRS1,val)
-#define bfin_read_CAN_TRR1() bfin_read16(CAN_TRR1)
-#define bfin_write_CAN_TRR1(val) bfin_write16(CAN_TRR1,val)
-#define bfin_read_CAN_TA1() bfin_read16(CAN_TA1)
-#define bfin_write_CAN_TA1(val) bfin_write16(CAN_TA1,val)
-#define bfin_read_CAN_AA1() bfin_read16(CAN_AA1)
-#define bfin_write_CAN_AA1(val) bfin_write16(CAN_AA1,val)
-#define bfin_read_CAN_RMP1() bfin_read16(CAN_RMP1)
-#define bfin_write_CAN_RMP1(val) bfin_write16(CAN_RMP1,val)
-#define bfin_read_CAN_RML1() bfin_read16(CAN_RML1)
-#define bfin_write_CAN_RML1(val) bfin_write16(CAN_RML1,val)
-#define bfin_read_CAN_MBTIF1() bfin_read16(CAN_MBTIF1)
-#define bfin_write_CAN_MBTIF1(val) bfin_write16(CAN_MBTIF1,val)
-#define bfin_read_CAN_MBRIF1() bfin_read16(CAN_MBRIF1)
-#define bfin_write_CAN_MBRIF1(val) bfin_write16(CAN_MBRIF1,val)
-#define bfin_read_CAN_MBIM1() bfin_read16(CAN_MBIM1)
-#define bfin_write_CAN_MBIM1(val) bfin_write16(CAN_MBIM1,val)
-#define bfin_read_CAN_RFH1() bfin_read16(CAN_RFH1)
-#define bfin_write_CAN_RFH1(val) bfin_write16(CAN_RFH1,val)
-#define bfin_read_CAN_OPSS1() bfin_read16(CAN_OPSS1)
-#define bfin_write_CAN_OPSS1(val) bfin_write16(CAN_OPSS1,val)
-
-/* For Mailboxes 16-31 */
-#define bfin_read_CAN_MC2() bfin_read16(CAN_MC2)
-#define bfin_write_CAN_MC2(val) bfin_write16(CAN_MC2,val)
-#define bfin_read_CAN_MD2() bfin_read16(CAN_MD2)
-#define bfin_write_CAN_MD2(val) bfin_write16(CAN_MD2,val)
-#define bfin_read_CAN_TRS2() bfin_read16(CAN_TRS2)
-#define bfin_write_CAN_TRS2(val) bfin_write16(CAN_TRS2,val)
-#define bfin_read_CAN_TRR2() bfin_read16(CAN_TRR2)
-#define bfin_write_CAN_TRR2(val) bfin_write16(CAN_TRR2,val)
-#define bfin_read_CAN_TA2() bfin_read16(CAN_TA2)
-#define bfin_write_CAN_TA2(val) bfin_write16(CAN_TA2,val)
-#define bfin_read_CAN_AA2() bfin_read16(CAN_AA2)
-#define bfin_write_CAN_AA2(val) bfin_write16(CAN_AA2,val)
-#define bfin_read_CAN_RMP2() bfin_read16(CAN_RMP2)
-#define bfin_write_CAN_RMP2(val) bfin_write16(CAN_RMP2,val)
-#define bfin_read_CAN_RML2() bfin_read16(CAN_RML2)
-#define bfin_write_CAN_RML2(val) bfin_write16(CAN_RML2,val)
-#define bfin_read_CAN_MBTIF2() bfin_read16(CAN_MBTIF2)
-#define bfin_write_CAN_MBTIF2(val) bfin_write16(CAN_MBTIF2,val)
-#define bfin_read_CAN_MBRIF2() bfin_read16(CAN_MBRIF2)
-#define bfin_write_CAN_MBRIF2(val) bfin_write16(CAN_MBRIF2,val)
-#define bfin_read_CAN_MBIM2() bfin_read16(CAN_MBIM2)
-#define bfin_write_CAN_MBIM2(val) bfin_write16(CAN_MBIM2,val)
-#define bfin_read_CAN_RFH2() bfin_read16(CAN_RFH2)
-#define bfin_write_CAN_RFH2(val) bfin_write16(CAN_RFH2,val)
-#define bfin_read_CAN_OPSS2() bfin_read16(CAN_OPSS2)
-#define bfin_write_CAN_OPSS2(val) bfin_write16(CAN_OPSS2,val)
-
-#define bfin_read_CAN_CLOCK() bfin_read16(CAN_CLOCK)
-#define bfin_write_CAN_CLOCK(val) bfin_write16(CAN_CLOCK,val)
-#define bfin_read_CAN_TIMING() bfin_read16(CAN_TIMING)
-#define bfin_write_CAN_TIMING(val) bfin_write16(CAN_TIMING,val)
-#define bfin_read_CAN_DEBUG() bfin_read16(CAN_DEBUG)
-#define bfin_write_CAN_DEBUG(val) bfin_write16(CAN_DEBUG,val)
-#define bfin_read_CAN_STATUS() bfin_read16(CAN_STATUS)
-#define bfin_write_CAN_STATUS(val) bfin_write16(CAN_STATUS,val)
-#define bfin_read_CAN_CEC() bfin_read16(CAN_CEC)
-#define bfin_write_CAN_CEC(val) bfin_write16(CAN_CEC,val)
-#define bfin_read_CAN_GIS() bfin_read16(CAN_GIS)
-#define bfin_write_CAN_GIS(val) bfin_write16(CAN_GIS,val)
-#define bfin_read_CAN_GIM() bfin_read16(CAN_GIM)
-#define bfin_write_CAN_GIM(val) bfin_write16(CAN_GIM,val)
-#define bfin_read_CAN_GIF() bfin_read16(CAN_GIF)
-#define bfin_write_CAN_GIF(val) bfin_write16(CAN_GIF,val)
-#define bfin_read_CAN_CONTROL() bfin_read16(CAN_CONTROL)
-#define bfin_write_CAN_CONTROL(val) bfin_write16(CAN_CONTROL,val)
-#define bfin_read_CAN_INTR() bfin_read16(CAN_INTR)
-#define bfin_write_CAN_INTR(val) bfin_write16(CAN_INTR,val)
-#define bfin_read_CAN_SFCMVER() bfin_read16(CAN_SFCMVER)
-#define bfin_write_CAN_SFCMVER(val) bfin_write16(CAN_SFCMVER,val)
-#define bfin_read_CAN_MBTD() bfin_read16(CAN_MBTD)
-#define bfin_write_CAN_MBTD(val) bfin_write16(CAN_MBTD,val)
-#define bfin_read_CAN_EWR() bfin_read16(CAN_EWR)
-#define bfin_write_CAN_EWR(val) bfin_write16(CAN_EWR,val)
-#define bfin_read_CAN_ESR() bfin_read16(CAN_ESR)
-#define bfin_write_CAN_ESR(val) bfin_write16(CAN_ESR,val)
-#define bfin_read_CAN_UCREG() bfin_read16(CAN_UCREG)
-#define bfin_write_CAN_UCREG(val) bfin_write16(CAN_UCREG,val)
-#define bfin_read_CAN_UCCNT() bfin_read16(CAN_UCCNT)
-#define bfin_write_CAN_UCCNT(val) bfin_write16(CAN_UCCNT,val)
-#define bfin_read_CAN_UCRC() bfin_read16(CAN_UCRC)
-#define bfin_write_CAN_UCRC(val) bfin_write16(CAN_UCRC,val)
-#define bfin_read_CAN_UCCNF() bfin_read16(CAN_UCCNF)
-#define bfin_write_CAN_UCCNF(val) bfin_write16(CAN_UCCNF,val)
-
-/* Mailbox Acceptance Masks */
-#define bfin_read_CAN_AM00L() bfin_read16(CAN_AM00L)
-#define bfin_write_CAN_AM00L(val) bfin_write16(CAN_AM00L,val)
-#define bfin_read_CAN_AM00H() bfin_read16(CAN_AM00H)
-#define bfin_write_CAN_AM00H(val) bfin_write16(CAN_AM00H,val)
-#define bfin_read_CAN_AM01L() bfin_read16(CAN_AM01L)
-#define bfin_write_CAN_AM01L(val) bfin_write16(CAN_AM01L,val)
-#define bfin_read_CAN_AM01H() bfin_read16(CAN_AM01H)
-#define bfin_write_CAN_AM01H(val) bfin_write16(CAN_AM01H,val)
-#define bfin_read_CAN_AM02L() bfin_read16(CAN_AM02L)
-#define bfin_write_CAN_AM02L(val) bfin_write16(CAN_AM02L,val)
-#define bfin_read_CAN_AM02H() bfin_read16(CAN_AM02H)
-#define bfin_write_CAN_AM02H(val) bfin_write16(CAN_AM02H,val)
-#define bfin_read_CAN_AM03L() bfin_read16(CAN_AM03L)
-#define bfin_write_CAN_AM03L(val) bfin_write16(CAN_AM03L,val)
-#define bfin_read_CAN_AM03H() bfin_read16(CAN_AM03H)
-#define bfin_write_CAN_AM03H(val) bfin_write16(CAN_AM03H,val)
-#define bfin_read_CAN_AM04L() bfin_read16(CAN_AM04L)
-#define bfin_write_CAN_AM04L(val) bfin_write16(CAN_AM04L,val)
-#define bfin_read_CAN_AM04H() bfin_read16(CAN_AM04H)
-#define bfin_write_CAN_AM04H(val) bfin_write16(CAN_AM04H,val)
-#define bfin_read_CAN_AM05L() bfin_read16(CAN_AM05L)
-#define bfin_write_CAN_AM05L(val) bfin_write16(CAN_AM05L,val)
-#define bfin_read_CAN_AM05H() bfin_read16(CAN_AM05H)
-#define bfin_write_CAN_AM05H(val) bfin_write16(CAN_AM05H,val)
-#define bfin_read_CAN_AM06L() bfin_read16(CAN_AM06L)
-#define bfin_write_CAN_AM06L(val) bfin_write16(CAN_AM06L,val)
-#define bfin_read_CAN_AM06H() bfin_read16(CAN_AM06H)
-#define bfin_write_CAN_AM06H(val) bfin_write16(CAN_AM06H,val)
-#define bfin_read_CAN_AM07L() bfin_read16(CAN_AM07L)
-#define bfin_write_CAN_AM07L(val) bfin_write16(CAN_AM07L,val)
-#define bfin_read_CAN_AM07H() bfin_read16(CAN_AM07H)
-#define bfin_write_CAN_AM07H(val) bfin_write16(CAN_AM07H,val)
-#define bfin_read_CAN_AM08L() bfin_read16(CAN_AM08L)
-#define bfin_write_CAN_AM08L(val) bfin_write16(CAN_AM08L,val)
-#define bfin_read_CAN_AM08H() bfin_read16(CAN_AM08H)
-#define bfin_write_CAN_AM08H(val) bfin_write16(CAN_AM08H,val)
-#define bfin_read_CAN_AM09L() bfin_read16(CAN_AM09L)
-#define bfin_write_CAN_AM09L(val) bfin_write16(CAN_AM09L,val)
-#define bfin_read_CAN_AM09H() bfin_read16(CAN_AM09H)
-#define bfin_write_CAN_AM09H(val) bfin_write16(CAN_AM09H,val)
-#define bfin_read_CAN_AM10L() bfin_read16(CAN_AM10L)
-#define bfin_write_CAN_AM10L(val) bfin_write16(CAN_AM10L,val)
-#define bfin_read_CAN_AM10H() bfin_read16(CAN_AM10H)
-#define bfin_write_CAN_AM10H(val) bfin_write16(CAN_AM10H,val)
-#define bfin_read_CAN_AM11L() bfin_read16(CAN_AM11L)
-#define bfin_write_CAN_AM11L(val) bfin_write16(CAN_AM11L,val)
-#define bfin_read_CAN_AM11H() bfin_read16(CAN_AM11H)
-#define bfin_write_CAN_AM11H(val) bfin_write16(CAN_AM11H,val)
-#define bfin_read_CAN_AM12L() bfin_read16(CAN_AM12L)
-#define bfin_write_CAN_AM12L(val) bfin_write16(CAN_AM12L,val)
-#define bfin_read_CAN_AM12H() bfin_read16(CAN_AM12H)
-#define bfin_write_CAN_AM12H(val) bfin_write16(CAN_AM12H,val)
-#define bfin_read_CAN_AM13L() bfin_read16(CAN_AM13L)
-#define bfin_write_CAN_AM13L(val) bfin_write16(CAN_AM13L,val)
-#define bfin_read_CAN_AM13H() bfin_read16(CAN_AM13H)
-#define bfin_write_CAN_AM13H(val) bfin_write16(CAN_AM13H,val)
-#define bfin_read_CAN_AM14L() bfin_read16(CAN_AM14L)
-#define bfin_write_CAN_AM14L(val) bfin_write16(CAN_AM14L,val)
-#define bfin_read_CAN_AM14H() bfin_read16(CAN_AM14H)
-#define bfin_write_CAN_AM14H(val) bfin_write16(CAN_AM14H,val)
-#define bfin_read_CAN_AM15L() bfin_read16(CAN_AM15L)
-#define bfin_write_CAN_AM15L(val) bfin_write16(CAN_AM15L,val)
-#define bfin_read_CAN_AM15H() bfin_read16(CAN_AM15H)
-#define bfin_write_CAN_AM15H(val) bfin_write16(CAN_AM15H,val)
-
-#define bfin_read_CAN_AM16L() bfin_read16(CAN_AM16L)
-#define bfin_write_CAN_AM16L(val) bfin_write16(CAN_AM16L,val)
-#define bfin_read_CAN_AM16H() bfin_read16(CAN_AM16H)
-#define bfin_write_CAN_AM16H(val) bfin_write16(CAN_AM16H,val)
-#define bfin_read_CAN_AM17L() bfin_read16(CAN_AM17L)
-#define bfin_write_CAN_AM17L(val) bfin_write16(CAN_AM17L,val)
-#define bfin_read_CAN_AM17H() bfin_read16(CAN_AM17H)
-#define bfin_write_CAN_AM17H(val) bfin_write16(CAN_AM17H,val)
-#define bfin_read_CAN_AM18L() bfin_read16(CAN_AM18L)
-#define bfin_write_CAN_AM18L(val) bfin_write16(CAN_AM18L,val)
-#define bfin_read_CAN_AM18H() bfin_read16(CAN_AM18H)
-#define bfin_write_CAN_AM18H(val) bfin_write16(CAN_AM18H,val)
-#define bfin_read_CAN_AM19L() bfin_read16(CAN_AM19L)
-#define bfin_write_CAN_AM19L(val) bfin_write16(CAN_AM19L,val)
-#define bfin_read_CAN_AM19H() bfin_read16(CAN_AM19H)
-#define bfin_write_CAN_AM19H(val) bfin_write16(CAN_AM19H,val)
-#define bfin_read_CAN_AM20L() bfin_read16(CAN_AM20L)
-#define bfin_write_CAN_AM20L(val) bfin_write16(CAN_AM20L,val)
-#define bfin_read_CAN_AM20H() bfin_read16(CAN_AM20H)
-#define bfin_write_CAN_AM20H(val) bfin_write16(CAN_AM20H,val)
-#define bfin_read_CAN_AM21L() bfin_read16(CAN_AM21L)
-#define bfin_write_CAN_AM21L(val) bfin_write16(CAN_AM21L,val)
-#define bfin_read_CAN_AM21H() bfin_read16(CAN_AM21H)
-#define bfin_write_CAN_AM21H(val) bfin_write16(CAN_AM21H,val)
-#define bfin_read_CAN_AM22L() bfin_read16(CAN_AM22L)
-#define bfin_write_CAN_AM22L(val) bfin_write16(CAN_AM22L,val)
-#define bfin_read_CAN_AM22H() bfin_read16(CAN_AM22H)
-#define bfin_write_CAN_AM22H(val) bfin_write16(CAN_AM22H,val)
-#define bfin_read_CAN_AM23L() bfin_read16(CAN_AM23L)
-#define bfin_write_CAN_AM23L(val) bfin_write16(CAN_AM23L,val)
-#define bfin_read_CAN_AM23H() bfin_read16(CAN_AM23H)
-#define bfin_write_CAN_AM23H(val) bfin_write16(CAN_AM23H,val)
-#define bfin_read_CAN_AM24L() bfin_read16(CAN_AM24L)
-#define bfin_write_CAN_AM24L(val) bfin_write16(CAN_AM24L,val)
-#define bfin_read_CAN_AM24H() bfin_read16(CAN_AM24H)
-#define bfin_write_CAN_AM24H(val) bfin_write16(CAN_AM24H,val)
-#define bfin_read_CAN_AM25L() bfin_read16(CAN_AM25L)
-#define bfin_write_CAN_AM25L(val) bfin_write16(CAN_AM25L,val)
-#define bfin_read_CAN_AM25H() bfin_read16(CAN_AM25H)
-#define bfin_write_CAN_AM25H(val) bfin_write16(CAN_AM25H,val)
-#define bfin_read_CAN_AM26L() bfin_read16(CAN_AM26L)
-#define bfin_write_CAN_AM26L(val) bfin_write16(CAN_AM26L,val)
-#define bfin_read_CAN_AM26H() bfin_read16(CAN_AM26H)
-#define bfin_write_CAN_AM26H(val) bfin_write16(CAN_AM26H,val)
-#define bfin_read_CAN_AM27L() bfin_read16(CAN_AM27L)
-#define bfin_write_CAN_AM27L(val) bfin_write16(CAN_AM27L,val)
-#define bfin_read_CAN_AM27H() bfin_read16(CAN_AM27H)
-#define bfin_write_CAN_AM27H(val) bfin_write16(CAN_AM27H,val)
-#define bfin_read_CAN_AM28L() bfin_read16(CAN_AM28L)
-#define bfin_write_CAN_AM28L(val) bfin_write16(CAN_AM28L,val)
-#define bfin_read_CAN_AM28H() bfin_read16(CAN_AM28H)
-#define bfin_write_CAN_AM28H(val) bfin_write16(CAN_AM28H,val)
-#define bfin_read_CAN_AM29L() bfin_read16(CAN_AM29L)
-#define bfin_write_CAN_AM29L(val) bfin_write16(CAN_AM29L,val)
-#define bfin_read_CAN_AM29H() bfin_read16(CAN_AM29H)
-#define bfin_write_CAN_AM29H(val) bfin_write16(CAN_AM29H,val)
-#define bfin_read_CAN_AM30L() bfin_read16(CAN_AM30L)
-#define bfin_write_CAN_AM30L(val) bfin_write16(CAN_AM30L,val)
-#define bfin_read_CAN_AM30H() bfin_read16(CAN_AM30H)
-#define bfin_write_CAN_AM30H(val) bfin_write16(CAN_AM30H,val)
-#define bfin_read_CAN_AM31L() bfin_read16(CAN_AM31L)
-#define bfin_write_CAN_AM31L(val) bfin_write16(CAN_AM31L,val)
-#define bfin_read_CAN_AM31H() bfin_read16(CAN_AM31H)
-#define bfin_write_CAN_AM31H(val) bfin_write16(CAN_AM31H,val)
-
-/* CAN Acceptance Mask Area Macros */
-#define bfin_read_CAN_AM_L(x)() bfin_read16(CAN_AM_L(x))
-#define bfin_write_CAN_AM_L(x)(val) bfin_write16(CAN_AM_L(x),val)
-#define bfin_read_CAN_AM_H(x)() bfin_read16(CAN_AM_H(x))
-#define bfin_write_CAN_AM_H(x)(val) bfin_write16(CAN_AM_H(x),val)
-
-/* Mailbox Registers */
-#define bfin_read_CAN_MB00_ID1() bfin_read16(CAN_MB00_ID1)
-#define bfin_write_CAN_MB00_ID1(val) bfin_write16(CAN_MB00_ID1,val)
-#define bfin_read_CAN_MB00_ID0() bfin_read16(CAN_MB00_ID0)
-#define bfin_write_CAN_MB00_ID0(val) bfin_write16(CAN_MB00_ID0,val)
-#define bfin_read_CAN_MB00_TIMESTAMP() bfin_read16(CAN_MB00_TIMESTAMP)
-#define bfin_write_CAN_MB00_TIMESTAMP(val) bfin_write16(CAN_MB00_TIMESTAMP,val)
-#define bfin_read_CAN_MB00_LENGTH() bfin_read16(CAN_MB00_LENGTH)
-#define bfin_write_CAN_MB00_LENGTH(val) bfin_write16(CAN_MB00_LENGTH,val)
-#define bfin_read_CAN_MB00_DATA3() bfin_read16(CAN_MB00_DATA3)
-#define bfin_write_CAN_MB00_DATA3(val) bfin_write16(CAN_MB00_DATA3,val)
-#define bfin_read_CAN_MB00_DATA2() bfin_read16(CAN_MB00_DATA2)
-#define bfin_write_CAN_MB00_DATA2(val) bfin_write16(CAN_MB00_DATA2,val)
-#define bfin_read_CAN_MB00_DATA1() bfin_read16(CAN_MB00_DATA1)
-#define bfin_write_CAN_MB00_DATA1(val) bfin_write16(CAN_MB00_DATA1,val)
-#define bfin_read_CAN_MB00_DATA0() bfin_read16(CAN_MB00_DATA0)
-#define bfin_write_CAN_MB00_DATA0(val) bfin_write16(CAN_MB00_DATA0,val)
-
-#define bfin_read_CAN_MB01_ID1() bfin_read16(CAN_MB01_ID1)
-#define bfin_write_CAN_MB01_ID1(val) bfin_write16(CAN_MB01_ID1,val)
-#define bfin_read_CAN_MB01_ID0() bfin_read16(CAN_MB01_ID0)
-#define bfin_write_CAN_MB01_ID0(val) bfin_write16(CAN_MB01_ID0,val)
-#define bfin_read_CAN_MB01_TIMESTAMP() bfin_read16(CAN_MB01_TIMESTAMP)
-#define bfin_write_CAN_MB01_TIMESTAMP(val) bfin_write16(CAN_MB01_TIMESTAMP,val)
-#define bfin_read_CAN_MB01_LENGTH() bfin_read16(CAN_MB01_LENGTH)
-#define bfin_write_CAN_MB01_LENGTH(val) bfin_write16(CAN_MB01_LENGTH,val)
-#define bfin_read_CAN_MB01_DATA3() bfin_read16(CAN_MB01_DATA3)
-#define bfin_write_CAN_MB01_DATA3(val) bfin_write16(CAN_MB01_DATA3,val)
-#define bfin_read_CAN_MB01_DATA2() bfin_read16(CAN_MB01_DATA2)
-#define bfin_write_CAN_MB01_DATA2(val) bfin_write16(CAN_MB01_DATA2,val)
-#define bfin_read_CAN_MB01_DATA1() bfin_read16(CAN_MB01_DATA1)
-#define bfin_write_CAN_MB01_DATA1(val) bfin_write16(CAN_MB01_DATA1,val)
-#define bfin_read_CAN_MB01_DATA0() bfin_read16(CAN_MB01_DATA0)
-#define bfin_write_CAN_MB01_DATA0(val) bfin_write16(CAN_MB01_DATA0,val)
-
-#define bfin_read_CAN_MB02_ID1() bfin_read16(CAN_MB02_ID1)
-#define bfin_write_CAN_MB02_ID1(val) bfin_write16(CAN_MB02_ID1,val)
-#define bfin_read_CAN_MB02_ID0() bfin_read16(CAN_MB02_ID0)
-#define bfin_write_CAN_MB02_ID0(val) bfin_write16(CAN_MB02_ID0,val)
-#define bfin_read_CAN_MB02_TIMESTAMP() bfin_read16(CAN_MB02_TIMESTAMP)
-#define bfin_write_CAN_MB02_TIMESTAMP(val) bfin_write16(CAN_MB02_TIMESTAMP,val)
-#define bfin_read_CAN_MB02_LENGTH() bfin_read16(CAN_MB02_LENGTH)
-#define bfin_write_CAN_MB02_LENGTH(val) bfin_write16(CAN_MB02_LENGTH,val)
-#define bfin_read_CAN_MB02_DATA3() bfin_read16(CAN_MB02_DATA3)
-#define bfin_write_CAN_MB02_DATA3(val) bfin_write16(CAN_MB02_DATA3,val)
-#define bfin_read_CAN_MB02_DATA2() bfin_read16(CAN_MB02_DATA2)
-#define bfin_write_CAN_MB02_DATA2(val) bfin_write16(CAN_MB02_DATA2,val)
-#define bfin_read_CAN_MB02_DATA1() bfin_read16(CAN_MB02_DATA1)
-#define bfin_write_CAN_MB02_DATA1(val) bfin_write16(CAN_MB02_DATA1,val)
-#define bfin_read_CAN_MB02_DATA0() bfin_read16(CAN_MB02_DATA0)
-#define bfin_write_CAN_MB02_DATA0(val) bfin_write16(CAN_MB02_DATA0,val)
-
-#define bfin_read_CAN_MB03_ID1() bfin_read16(CAN_MB03_ID1)
-#define bfin_write_CAN_MB03_ID1(val) bfin_write16(CAN_MB03_ID1,val)
-#define bfin_read_CAN_MB03_ID0() bfin_read16(CAN_MB03_ID0)
-#define bfin_write_CAN_MB03_ID0(val) bfin_write16(CAN_MB03_ID0,val)
-#define bfin_read_CAN_MB03_TIMESTAMP() bfin_read16(CAN_MB03_TIMESTAMP)
-#define bfin_write_CAN_MB03_TIMESTAMP(val) bfin_write16(CAN_MB03_TIMESTAMP,val)
-#define bfin_read_CAN_MB03_LENGTH() bfin_read16(CAN_MB03_LENGTH)
-#define bfin_write_CAN_MB03_LENGTH(val) bfin_write16(CAN_MB03_LENGTH,val)
-#define bfin_read_CAN_MB03_DATA3() bfin_read16(CAN_MB03_DATA3)
-#define bfin_write_CAN_MB03_DATA3(val) bfin_write16(CAN_MB03_DATA3,val)
-#define bfin_read_CAN_MB03_DATA2() bfin_read16(CAN_MB03_DATA2)
-#define bfin_write_CAN_MB03_DATA2(val) bfin_write16(CAN_MB03_DATA2,val)
-#define bfin_read_CAN_MB03_DATA1() bfin_read16(CAN_MB03_DATA1)
-#define bfin_write_CAN_MB03_DATA1(val) bfin_write16(CAN_MB03_DATA1,val)
-#define bfin_read_CAN_MB03_DATA0() bfin_read16(CAN_MB03_DATA0)
-#define bfin_write_CAN_MB03_DATA0(val) bfin_write16(CAN_MB03_DATA0,val)
-
-#define bfin_read_CAN_MB04_ID1() bfin_read16(CAN_MB04_ID1)
-#define bfin_write_CAN_MB04_ID1(val) bfin_write16(CAN_MB04_ID1,val)
-#define bfin_read_CAN_MB04_ID0() bfin_read16(CAN_MB04_ID0)
-#define bfin_write_CAN_MB04_ID0(val) bfin_write16(CAN_MB04_ID0,val)
-#define bfin_read_CAN_MB04_TIMESTAMP() bfin_read16(CAN_MB04_TIMESTAMP)
-#define bfin_write_CAN_MB04_TIMESTAMP(val) bfin_write16(CAN_MB04_TIMESTAMP,val)
-#define bfin_read_CAN_MB04_LENGTH() bfin_read16(CAN_MB04_LENGTH)
-#define bfin_write_CAN_MB04_LENGTH(val) bfin_write16(CAN_MB04_LENGTH,val)
-#define bfin_read_CAN_MB04_DATA3() bfin_read16(CAN_MB04_DATA3)
-#define bfin_write_CAN_MB04_DATA3(val) bfin_write16(CAN_MB04_DATA3,val)
-#define bfin_read_CAN_MB04_DATA2() bfin_read16(CAN_MB04_DATA2)
-#define bfin_write_CAN_MB04_DATA2(val) bfin_write16(CAN_MB04_DATA2,val)
-#define bfin_read_CAN_MB04_DATA1() bfin_read16(CAN_MB04_DATA1)
-#define bfin_write_CAN_MB04_DATA1(val) bfin_write16(CAN_MB04_DATA1,val)
-#define bfin_read_CAN_MB04_DATA0() bfin_read16(CAN_MB04_DATA0)
-#define bfin_write_CAN_MB04_DATA0(val) bfin_write16(CAN_MB04_DATA0,val)
-
-#define bfin_read_CAN_MB05_ID1() bfin_read16(CAN_MB05_ID1)
-#define bfin_write_CAN_MB05_ID1(val) bfin_write16(CAN_MB05_ID1,val)
-#define bfin_read_CAN_MB05_ID0() bfin_read16(CAN_MB05_ID0)
-#define bfin_write_CAN_MB05_ID0(val) bfin_write16(CAN_MB05_ID0,val)
-#define bfin_read_CAN_MB05_TIMESTAMP() bfin_read16(CAN_MB05_TIMESTAMP)
-#define bfin_write_CAN_MB05_TIMESTAMP(val) bfin_write16(CAN_MB05_TIMESTAMP,val)
-#define bfin_read_CAN_MB05_LENGTH() bfin_read16(CAN_MB05_LENGTH)
-#define bfin_write_CAN_MB05_LENGTH(val) bfin_write16(CAN_MB05_LENGTH,val)
-#define bfin_read_CAN_MB05_DATA3() bfin_read16(CAN_MB05_DATA3)
-#define bfin_write_CAN_MB05_DATA3(val) bfin_write16(CAN_MB05_DATA3,val)
-#define bfin_read_CAN_MB05_DATA2() bfin_read16(CAN_MB05_DATA2)
-#define bfin_write_CAN_MB05_DATA2(val) bfin_write16(CAN_MB05_DATA2,val)
-#define bfin_read_CAN_MB05_DATA1() bfin_read16(CAN_MB05_DATA1)
-#define bfin_write_CAN_MB05_DATA1(val) bfin_write16(CAN_MB05_DATA1,val)
-#define bfin_read_CAN_MB05_DATA0() bfin_read16(CAN_MB05_DATA0)
-#define bfin_write_CAN_MB05_DATA0(val) bfin_write16(CAN_MB05_DATA0,val)
-
-#define bfin_read_CAN_MB06_ID1() bfin_read16(CAN_MB06_ID1)
-#define bfin_write_CAN_MB06_ID1(val) bfin_write16(CAN_MB06_ID1,val)
-#define bfin_read_CAN_MB06_ID0() bfin_read16(CAN_MB06_ID0)
-#define bfin_write_CAN_MB06_ID0(val) bfin_write16(CAN_MB06_ID0,val)
-#define bfin_read_CAN_MB06_TIMESTAMP() bfin_read16(CAN_MB06_TIMESTAMP)
-#define bfin_write_CAN_MB06_TIMESTAMP(val) bfin_write16(CAN_MB06_TIMESTAMP,val)
-#define bfin_read_CAN_MB06_LENGTH() bfin_read16(CAN_MB06_LENGTH)
-#define bfin_write_CAN_MB06_LENGTH(val) bfin_write16(CAN_MB06_LENGTH,val)
-#define bfin_read_CAN_MB06_DATA3() bfin_read16(CAN_MB06_DATA3)
-#define bfin_write_CAN_MB06_DATA3(val) bfin_write16(CAN_MB06_DATA3,val)
-#define bfin_read_CAN_MB06_DATA2() bfin_read16(CAN_MB06_DATA2)
-#define bfin_write_CAN_MB06_DATA2(val) bfin_write16(CAN_MB06_DATA2,val)
-#define bfin_read_CAN_MB06_DATA1() bfin_read16(CAN_MB06_DATA1)
-#define bfin_write_CAN_MB06_DATA1(val) bfin_write16(CAN_MB06_DATA1,val)
-#define bfin_read_CAN_MB06_DATA0() bfin_read16(CAN_MB06_DATA0)
-#define bfin_write_CAN_MB06_DATA0(val) bfin_write16(CAN_MB06_DATA0,val)
-
-#define bfin_read_CAN_MB07_ID1() bfin_read16(CAN_MB07_ID1)
-#define bfin_write_CAN_MB07_ID1(val) bfin_write16(CAN_MB07_ID1,val)
-#define bfin_read_CAN_MB07_ID0() bfin_read16(CAN_MB07_ID0)
-#define bfin_write_CAN_MB07_ID0(val) bfin_write16(CAN_MB07_ID0,val)
-#define bfin_read_CAN_MB07_TIMESTAMP() bfin_read16(CAN_MB07_TIMESTAMP)
-#define bfin_write_CAN_MB07_TIMESTAMP(val) bfin_write16(CAN_MB07_TIMESTAMP,val)
-#define bfin_read_CAN_MB07_LENGTH() bfin_read16(CAN_MB07_LENGTH)
-#define bfin_write_CAN_MB07_LENGTH(val) bfin_write16(CAN_MB07_LENGTH,val)
-#define bfin_read_CAN_MB07_DATA3() bfin_read16(CAN_MB07_DATA3)
-#define bfin_write_CAN_MB07_DATA3(val) bfin_write16(CAN_MB07_DATA3,val)
-#define bfin_read_CAN_MB07_DATA2() bfin_read16(CAN_MB07_DATA2)
-#define bfin_write_CAN_MB07_DATA2(val) bfin_write16(CAN_MB07_DATA2,val)
-#define bfin_read_CAN_MB07_DATA1() bfin_read16(CAN_MB07_DATA1)
-#define bfin_write_CAN_MB07_DATA1(val) bfin_write16(CAN_MB07_DATA1,val)
-#define bfin_read_CAN_MB07_DATA0() bfin_read16(CAN_MB07_DATA0)
-#define bfin_write_CAN_MB07_DATA0(val) bfin_write16(CAN_MB07_DATA0,val)
-
-#define bfin_read_CAN_MB08_ID1() bfin_read16(CAN_MB08_ID1)
-#define bfin_write_CAN_MB08_ID1(val) bfin_write16(CAN_MB08_ID1,val)
-#define bfin_read_CAN_MB08_ID0() bfin_read16(CAN_MB08_ID0)
-#define bfin_write_CAN_MB08_ID0(val) bfin_write16(CAN_MB08_ID0,val)
-#define bfin_read_CAN_MB08_TIMESTAMP() bfin_read16(CAN_MB08_TIMESTAMP)
-#define bfin_write_CAN_MB08_TIMESTAMP(val) bfin_write16(CAN_MB08_TIMESTAMP,val)
-#define bfin_read_CAN_MB08_LENGTH() bfin_read16(CAN_MB08_LENGTH)
-#define bfin_write_CAN_MB08_LENGTH(val) bfin_write16(CAN_MB08_LENGTH,val)
-#define bfin_read_CAN_MB08_DATA3() bfin_read16(CAN_MB08_DATA3)
-#define bfin_write_CAN_MB08_DATA3(val) bfin_write16(CAN_MB08_DATA3,val)
-#define bfin_read_CAN_MB08_DATA2() bfin_read16(CAN_MB08_DATA2)
-#define bfin_write_CAN_MB08_DATA2(val) bfin_write16(CAN_MB08_DATA2,val)
-#define bfin_read_CAN_MB08_DATA1() bfin_read16(CAN_MB08_DATA1)
-#define bfin_write_CAN_MB08_DATA1(val) bfin_write16(CAN_MB08_DATA1,val)
-#define bfin_read_CAN_MB08_DATA0() bfin_read16(CAN_MB08_DATA0)
-#define bfin_write_CAN_MB08_DATA0(val) bfin_write16(CAN_MB08_DATA0,val)
-
-#define bfin_read_CAN_MB09_ID1() bfin_read16(CAN_MB09_ID1)
-#define bfin_write_CAN_MB09_ID1(val) bfin_write16(CAN_MB09_ID1,val)
-#define bfin_read_CAN_MB09_ID0() bfin_read16(CAN_MB09_ID0)
-#define bfin_write_CAN_MB09_ID0(val) bfin_write16(CAN_MB09_ID0,val)
-#define bfin_read_CAN_MB09_TIMESTAMP() bfin_read16(CAN_MB09_TIMESTAMP)
-#define bfin_write_CAN_MB09_TIMESTAMP(val) bfin_write16(CAN_MB09_TIMESTAMP,val)
-#define bfin_read_CAN_MB09_LENGTH() bfin_read16(CAN_MB09_LENGTH)
-#define bfin_write_CAN_MB09_LENGTH(val) bfin_write16(CAN_MB09_LENGTH,val)
-#define bfin_read_CAN_MB09_DATA3() bfin_read16(CAN_MB09_DATA3)
-#define bfin_write_CAN_MB09_DATA3(val) bfin_write16(CAN_MB09_DATA3,val)
-#define bfin_read_CAN_MB09_DATA2() bfin_read16(CAN_MB09_DATA2)
-#define bfin_write_CAN_MB09_DATA2(val) bfin_write16(CAN_MB09_DATA2,val)
-#define bfin_read_CAN_MB09_DATA1() bfin_read16(CAN_MB09_DATA1)
-#define bfin_write_CAN_MB09_DATA1(val) bfin_write16(CAN_MB09_DATA1,val)
-#define bfin_read_CAN_MB09_DATA0() bfin_read16(CAN_MB09_DATA0)
-#define bfin_write_CAN_MB09_DATA0(val) bfin_write16(CAN_MB09_DATA0,val)
-
-#define bfin_read_CAN_MB10_ID1() bfin_read16(CAN_MB10_ID1)
-#define bfin_write_CAN_MB10_ID1(val) bfin_write16(CAN_MB10_ID1,val)
-#define bfin_read_CAN_MB10_ID0() bfin_read16(CAN_MB10_ID0)
-#define bfin_write_CAN_MB10_ID0(val) bfin_write16(CAN_MB10_ID0,val)
-#define bfin_read_CAN_MB10_TIMESTAMP() bfin_read16(CAN_MB10_TIMESTAMP)
-#define bfin_write_CAN_MB10_TIMESTAMP(val) bfin_write16(CAN_MB10_TIMESTAMP,val)
-#define bfin_read_CAN_MB10_LENGTH() bfin_read16(CAN_MB10_LENGTH)
-#define bfin_write_CAN_MB10_LENGTH(val) bfin_write16(CAN_MB10_LENGTH,val)
-#define bfin_read_CAN_MB10_DATA3() bfin_read16(CAN_MB10_DATA3)
-#define bfin_write_CAN_MB10_DATA3(val) bfin_write16(CAN_MB10_DATA3,val)
-#define bfin_read_CAN_MB10_DATA2() bfin_read16(CAN_MB10_DATA2)
-#define bfin_write_CAN_MB10_DATA2(val) bfin_write16(CAN_MB10_DATA2,val)
-#define bfin_read_CAN_MB10_DATA1() bfin_read16(CAN_MB10_DATA1)
-#define bfin_write_CAN_MB10_DATA1(val) bfin_write16(CAN_MB10_DATA1,val)
-#define bfin_read_CAN_MB10_DATA0() bfin_read16(CAN_MB10_DATA0)
-#define bfin_write_CAN_MB10_DATA0(val) bfin_write16(CAN_MB10_DATA0,val)
-
-#define bfin_read_CAN_MB11_ID1() bfin_read16(CAN_MB11_ID1)
-#define bfin_write_CAN_MB11_ID1(val) bfin_write16(CAN_MB11_ID1,val)
-#define bfin_read_CAN_MB11_ID0() bfin_read16(CAN_MB11_ID0)
-#define bfin_write_CAN_MB11_ID0(val) bfin_write16(CAN_MB11_ID0,val)
-#define bfin_read_CAN_MB11_TIMESTAMP() bfin_read16(CAN_MB11_TIMESTAMP)
-#define bfin_write_CAN_MB11_TIMESTAMP(val) bfin_write16(CAN_MB11_TIMESTAMP,val)
-#define bfin_read_CAN_MB11_LENGTH() bfin_read16(CAN_MB11_LENGTH)
-#define bfin_write_CAN_MB11_LENGTH(val) bfin_write16(CAN_MB11_LENGTH,val)
-#define bfin_read_CAN_MB11_DATA3() bfin_read16(CAN_MB11_DATA3)
-#define bfin_write_CAN_MB11_DATA3(val) bfin_write16(CAN_MB11_DATA3,val)
-#define bfin_read_CAN_MB11_DATA2() bfin_read16(CAN_MB11_DATA2)
-#define bfin_write_CAN_MB11_DATA2(val) bfin_write16(CAN_MB11_DATA2,val)
-#define bfin_read_CAN_MB11_DATA1() bfin_read16(CAN_MB11_DATA1)
-#define bfin_write_CAN_MB11_DATA1(val) bfin_write16(CAN_MB11_DATA1,val)
-#define bfin_read_CAN_MB11_DATA0() bfin_read16(CAN_MB11_DATA0)
-#define bfin_write_CAN_MB11_DATA0(val) bfin_write16(CAN_MB11_DATA0,val)
-
-#define bfin_read_CAN_MB12_ID1() bfin_read16(CAN_MB12_ID1)
-#define bfin_write_CAN_MB12_ID1(val) bfin_write16(CAN_MB12_ID1,val)
-#define bfin_read_CAN_MB12_ID0() bfin_read16(CAN_MB12_ID0)
-#define bfin_write_CAN_MB12_ID0(val) bfin_write16(CAN_MB12_ID0,val)
-#define bfin_read_CAN_MB12_TIMESTAMP() bfin_read16(CAN_MB12_TIMESTAMP)
-#define bfin_write_CAN_MB12_TIMESTAMP(val) bfin_write16(CAN_MB12_TIMESTAMP,val)
-#define bfin_read_CAN_MB12_LENGTH() bfin_read16(CAN_MB12_LENGTH)
-#define bfin_write_CAN_MB12_LENGTH(val) bfin_write16(CAN_MB12_LENGTH,val)
-#define bfin_read_CAN_MB12_DATA3() bfin_read16(CAN_MB12_DATA3)
-#define bfin_write_CAN_MB12_DATA3(val) bfin_write16(CAN_MB12_DATA3,val)
-#define bfin_read_CAN_MB12_DATA2() bfin_read16(CAN_MB12_DATA2)
-#define bfin_write_CAN_MB12_DATA2(val) bfin_write16(CAN_MB12_DATA2,val)
-#define bfin_read_CAN_MB12_DATA1() bfin_read16(CAN_MB12_DATA1)
-#define bfin_write_CAN_MB12_DATA1(val) bfin_write16(CAN_MB12_DATA1,val)
-#define bfin_read_CAN_MB12_DATA0() bfin_read16(CAN_MB12_DATA0)
-#define bfin_write_CAN_MB12_DATA0(val) bfin_write16(CAN_MB12_DATA0,val)
-
-#define bfin_read_CAN_MB13_ID1() bfin_read16(CAN_MB13_ID1)
-#define bfin_write_CAN_MB13_ID1(val) bfin_write16(CAN_MB13_ID1,val)
-#define bfin_read_CAN_MB13_ID0() bfin_read16(CAN_MB13_ID0)
-#define bfin_write_CAN_MB13_ID0(val) bfin_write16(CAN_MB13_ID0,val)
-#define bfin_read_CAN_MB13_TIMESTAMP() bfin_read16(CAN_MB13_TIMESTAMP)
-#define bfin_write_CAN_MB13_TIMESTAMP(val) bfin_write16(CAN_MB13_TIMESTAMP,val)
-#define bfin_read_CAN_MB13_LENGTH() bfin_read16(CAN_MB13_LENGTH)
-#define bfin_write_CAN_MB13_LENGTH(val) bfin_write16(CAN_MB13_LENGTH,val)
-#define bfin_read_CAN_MB13_DATA3() bfin_read16(CAN_MB13_DATA3)
-#define bfin_write_CAN_MB13_DATA3(val) bfin_write16(CAN_MB13_DATA3,val)
-#define bfin_read_CAN_MB13_DATA2() bfin_read16(CAN_MB13_DATA2)
-#define bfin_write_CAN_MB13_DATA2(val) bfin_write16(CAN_MB13_DATA2,val)
-#define bfin_read_CAN_MB13_DATA1() bfin_read16(CAN_MB13_DATA1)
-#define bfin_write_CAN_MB13_DATA1(val) bfin_write16(CAN_MB13_DATA1,val)
-#define bfin_read_CAN_MB13_DATA0() bfin_read16(CAN_MB13_DATA0)
-#define bfin_write_CAN_MB13_DATA0(val) bfin_write16(CAN_MB13_DATA0,val)
-
-#define bfin_read_CAN_MB14_ID1() bfin_read16(CAN_MB14_ID1)
-#define bfin_write_CAN_MB14_ID1(val) bfin_write16(CAN_MB14_ID1,val)
-#define bfin_read_CAN_MB14_ID0() bfin_read16(CAN_MB14_ID0)
-#define bfin_write_CAN_MB14_ID0(val) bfin_write16(CAN_MB14_ID0,val)
-#define bfin_read_CAN_MB14_TIMESTAMP() bfin_read16(CAN_MB14_TIMESTAMP)
-#define bfin_write_CAN_MB14_TIMESTAMP(val) bfin_write16(CAN_MB14_TIMESTAMP,val)
-#define bfin_read_CAN_MB14_LENGTH() bfin_read16(CAN_MB14_LENGTH)
-#define bfin_write_CAN_MB14_LENGTH(val) bfin_write16(CAN_MB14_LENGTH,val)
-#define bfin_read_CAN_MB14_DATA3() bfin_read16(CAN_MB14_DATA3)
-#define bfin_write_CAN_MB14_DATA3(val) bfin_write16(CAN_MB14_DATA3,val)
-#define bfin_read_CAN_MB14_DATA2() bfin_read16(CAN_MB14_DATA2)
-#define bfin_write_CAN_MB14_DATA2(val) bfin_write16(CAN_MB14_DATA2,val)
-#define bfin_read_CAN_MB14_DATA1() bfin_read16(CAN_MB14_DATA1)
-#define bfin_write_CAN_MB14_DATA1(val) bfin_write16(CAN_MB14_DATA1,val)
-#define bfin_read_CAN_MB14_DATA0() bfin_read16(CAN_MB14_DATA0)
-#define bfin_write_CAN_MB14_DATA0(val) bfin_write16(CAN_MB14_DATA0,val)
-
-#define bfin_read_CAN_MB15_ID1() bfin_read16(CAN_MB15_ID1)
-#define bfin_write_CAN_MB15_ID1(val) bfin_write16(CAN_MB15_ID1,val)
-#define bfin_read_CAN_MB15_ID0() bfin_read16(CAN_MB15_ID0)
-#define bfin_write_CAN_MB15_ID0(val) bfin_write16(CAN_MB15_ID0,val)
-#define bfin_read_CAN_MB15_TIMESTAMP() bfin_read16(CAN_MB15_TIMESTAMP)
-#define bfin_write_CAN_MB15_TIMESTAMP(val) bfin_write16(CAN_MB15_TIMESTAMP,val)
-#define bfin_read_CAN_MB15_LENGTH() bfin_read16(CAN_MB15_LENGTH)
-#define bfin_write_CAN_MB15_LENGTH(val) bfin_write16(CAN_MB15_LENGTH,val)
-#define bfin_read_CAN_MB15_DATA3() bfin_read16(CAN_MB15_DATA3)
-#define bfin_write_CAN_MB15_DATA3(val) bfin_write16(CAN_MB15_DATA3,val)
-#define bfin_read_CAN_MB15_DATA2() bfin_read16(CAN_MB15_DATA2)
-#define bfin_write_CAN_MB15_DATA2(val) bfin_write16(CAN_MB15_DATA2,val)
-#define bfin_read_CAN_MB15_DATA1() bfin_read16(CAN_MB15_DATA1)
-#define bfin_write_CAN_MB15_DATA1(val) bfin_write16(CAN_MB15_DATA1,val)
-#define bfin_read_CAN_MB15_DATA0() bfin_read16(CAN_MB15_DATA0)
-#define bfin_write_CAN_MB15_DATA0(val) bfin_write16(CAN_MB15_DATA0,val)
-
-#define bfin_read_CAN_MB16_ID1() bfin_read16(CAN_MB16_ID1)
-#define bfin_write_CAN_MB16_ID1(val) bfin_write16(CAN_MB16_ID1,val)
-#define bfin_read_CAN_MB16_ID0() bfin_read16(CAN_MB16_ID0)
-#define bfin_write_CAN_MB16_ID0(val) bfin_write16(CAN_MB16_ID0,val)
-#define bfin_read_CAN_MB16_TIMESTAMP() bfin_read16(CAN_MB16_TIMESTAMP)
-#define bfin_write_CAN_MB16_TIMESTAMP(val) bfin_write16(CAN_MB16_TIMESTAMP,val)
-#define bfin_read_CAN_MB16_LENGTH() bfin_read16(CAN_MB16_LENGTH)
-#define bfin_write_CAN_MB16_LENGTH(val) bfin_write16(CAN_MB16_LENGTH,val)
-#define bfin_read_CAN_MB16_DATA3() bfin_read16(CAN_MB16_DATA3)
-#define bfin_write_CAN_MB16_DATA3(val) bfin_write16(CAN_MB16_DATA3,val)
-#define bfin_read_CAN_MB16_DATA2() bfin_read16(CAN_MB16_DATA2)
-#define bfin_write_CAN_MB16_DATA2(val) bfin_write16(CAN_MB16_DATA2,val)
-#define bfin_read_CAN_MB16_DATA1() bfin_read16(CAN_MB16_DATA1)
-#define bfin_write_CAN_MB16_DATA1(val) bfin_write16(CAN_MB16_DATA1,val)
-#define bfin_read_CAN_MB16_DATA0() bfin_read16(CAN_MB16_DATA0)
-#define bfin_write_CAN_MB16_DATA0(val) bfin_write16(CAN_MB16_DATA0,val)
-
-#define bfin_read_CAN_MB17_ID1() bfin_read16(CAN_MB17_ID1)
-#define bfin_write_CAN_MB17_ID1(val) bfin_write16(CAN_MB17_ID1,val)
-#define bfin_read_CAN_MB17_ID0() bfin_read16(CAN_MB17_ID0)
-#define bfin_write_CAN_MB17_ID0(val) bfin_write16(CAN_MB17_ID0,val)
-#define bfin_read_CAN_MB17_TIMESTAMP() bfin_read16(CAN_MB17_TIMESTAMP)
-#define bfin_write_CAN_MB17_TIMESTAMP(val) bfin_write16(CAN_MB17_TIMESTAMP,val)
-#define bfin_read_CAN_MB17_LENGTH() bfin_read16(CAN_MB17_LENGTH)
-#define bfin_write_CAN_MB17_LENGTH(val) bfin_write16(CAN_MB17_LENGTH,val)
-#define bfin_read_CAN_MB17_DATA3() bfin_read16(CAN_MB17_DATA3)
-#define bfin_write_CAN_MB17_DATA3(val) bfin_write16(CAN_MB17_DATA3,val)
-#define bfin_read_CAN_MB17_DATA2() bfin_read16(CAN_MB17_DATA2)
-#define bfin_write_CAN_MB17_DATA2(val) bfin_write16(CAN_MB17_DATA2,val)
-#define bfin_read_CAN_MB17_DATA1() bfin_read16(CAN_MB17_DATA1)
-#define bfin_write_CAN_MB17_DATA1(val) bfin_write16(CAN_MB17_DATA1,val)
-#define bfin_read_CAN_MB17_DATA0() bfin_read16(CAN_MB17_DATA0)
-#define bfin_write_CAN_MB17_DATA0(val) bfin_write16(CAN_MB17_DATA0,val)
-
-#define bfin_read_CAN_MB18_ID1() bfin_read16(CAN_MB18_ID1)
-#define bfin_write_CAN_MB18_ID1(val) bfin_write16(CAN_MB18_ID1,val)
-#define bfin_read_CAN_MB18_ID0() bfin_read16(CAN_MB18_ID0)
-#define bfin_write_CAN_MB18_ID0(val) bfin_write16(CAN_MB18_ID0,val)
-#define bfin_read_CAN_MB18_TIMESTAMP() bfin_read16(CAN_MB18_TIMESTAMP)
-#define bfin_write_CAN_MB18_TIMESTAMP(val) bfin_write16(CAN_MB18_TIMESTAMP,val)
-#define bfin_read_CAN_MB18_LENGTH() bfin_read16(CAN_MB18_LENGTH)
-#define bfin_write_CAN_MB18_LENGTH(val) bfin_write16(CAN_MB18_LENGTH,val)
-#define bfin_read_CAN_MB18_DATA3() bfin_read16(CAN_MB18_DATA3)
-#define bfin_write_CAN_MB18_DATA3(val) bfin_write16(CAN_MB18_DATA3,val)
-#define bfin_read_CAN_MB18_DATA2() bfin_read16(CAN_MB18_DATA2)
-#define bfin_write_CAN_MB18_DATA2(val) bfin_write16(CAN_MB18_DATA2,val)
-#define bfin_read_CAN_MB18_DATA1() bfin_read16(CAN_MB18_DATA1)
-#define bfin_write_CAN_MB18_DATA1(val) bfin_write16(CAN_MB18_DATA1,val)
-#define bfin_read_CAN_MB18_DATA0() bfin_read16(CAN_MB18_DATA0)
-#define bfin_write_CAN_MB18_DATA0(val) bfin_write16(CAN_MB18_DATA0,val)
-
-#define bfin_read_CAN_MB19_ID1() bfin_read16(CAN_MB19_ID1)
-#define bfin_write_CAN_MB19_ID1(val) bfin_write16(CAN_MB19_ID1,val)
-#define bfin_read_CAN_MB19_ID0() bfin_read16(CAN_MB19_ID0)
-#define bfin_write_CAN_MB19_ID0(val) bfin_write16(CAN_MB19_ID0,val)
-#define bfin_read_CAN_MB19_TIMESTAMP() bfin_read16(CAN_MB19_TIMESTAMP)
-#define bfin_write_CAN_MB19_TIMESTAMP(val) bfin_write16(CAN_MB19_TIMESTAMP,val)
-#define bfin_read_CAN_MB19_LENGTH() bfin_read16(CAN_MB19_LENGTH)
-#define bfin_write_CAN_MB19_LENGTH(val) bfin_write16(CAN_MB19_LENGTH,val)
-#define bfin_read_CAN_MB19_DATA3() bfin_read16(CAN_MB19_DATA3)
-#define bfin_write_CAN_MB19_DATA3(val) bfin_write16(CAN_MB19_DATA3,val)
-#define bfin_read_CAN_MB19_DATA2() bfin_read16(CAN_MB19_DATA2)
-#define bfin_write_CAN_MB19_DATA2(val) bfin_write16(CAN_MB19_DATA2,val)
-#define bfin_read_CAN_MB19_DATA1() bfin_read16(CAN_MB19_DATA1)
-#define bfin_write_CAN_MB19_DATA1(val) bfin_write16(CAN_MB19_DATA1,val)
-#define bfin_read_CAN_MB19_DATA0() bfin_read16(CAN_MB19_DATA0)
-#define bfin_write_CAN_MB19_DATA0(val) bfin_write16(CAN_MB19_DATA0,val)
-
-#define bfin_read_CAN_MB20_ID1() bfin_read16(CAN_MB20_ID1)
-#define bfin_write_CAN_MB20_ID1(val) bfin_write16(CAN_MB20_ID1,val)
-#define bfin_read_CAN_MB20_ID0() bfin_read16(CAN_MB20_ID0)
-#define bfin_write_CAN_MB20_ID0(val) bfin_write16(CAN_MB20_ID0,val)
-#define bfin_read_CAN_MB20_TIMESTAMP() bfin_read16(CAN_MB20_TIMESTAMP)
-#define bfin_write_CAN_MB20_TIMESTAMP(val) bfin_write16(CAN_MB20_TIMESTAMP,val)
-#define bfin_read_CAN_MB20_LENGTH() bfin_read16(CAN_MB20_LENGTH)
-#define bfin_write_CAN_MB20_LENGTH(val) bfin_write16(CAN_MB20_LENGTH,val)
-#define bfin_read_CAN_MB20_DATA3() bfin_read16(CAN_MB20_DATA3)
-#define bfin_write_CAN_MB20_DATA3(val) bfin_write16(CAN_MB20_DATA3,val)
-#define bfin_read_CAN_MB20_DATA2() bfin_read16(CAN_MB20_DATA2)
-#define bfin_write_CAN_MB20_DATA2(val) bfin_write16(CAN_MB20_DATA2,val)
-#define bfin_read_CAN_MB20_DATA1() bfin_read16(CAN_MB20_DATA1)
-#define bfin_write_CAN_MB20_DATA1(val) bfin_write16(CAN_MB20_DATA1,val)
-#define bfin_read_CAN_MB20_DATA0() bfin_read16(CAN_MB20_DATA0)
-#define bfin_write_CAN_MB20_DATA0(val) bfin_write16(CAN_MB20_DATA0,val)
-
-#define bfin_read_CAN_MB21_ID1() bfin_read16(CAN_MB21_ID1)
-#define bfin_write_CAN_MB21_ID1(val) bfin_write16(CAN_MB21_ID1,val)
-#define bfin_read_CAN_MB21_ID0() bfin_read16(CAN_MB21_ID0)
-#define bfin_write_CAN_MB21_ID0(val) bfin_write16(CAN_MB21_ID0,val)
-#define bfin_read_CAN_MB21_TIMESTAMP() bfin_read16(CAN_MB21_TIMESTAMP)
-#define bfin_write_CAN_MB21_TIMESTAMP(val) bfin_write16(CAN_MB21_TIMESTAMP,val)
-#define bfin_read_CAN_MB21_LENGTH() bfin_read16(CAN_MB21_LENGTH)
-#define bfin_write_CAN_MB21_LENGTH(val) bfin_write16(CAN_MB21_LENGTH,val)
-#define bfin_read_CAN_MB21_DATA3() bfin_read16(CAN_MB21_DATA3)
-#define bfin_write_CAN_MB21_DATA3(val) bfin_write16(CAN_MB21_DATA3,val)
-#define bfin_read_CAN_MB21_DATA2() bfin_read16(CAN_MB21_DATA2)
-#define bfin_write_CAN_MB21_DATA2(val) bfin_write16(CAN_MB21_DATA2,val)
-#define bfin_read_CAN_MB21_DATA1() bfin_read16(CAN_MB21_DATA1)
-#define bfin_write_CAN_MB21_DATA1(val) bfin_write16(CAN_MB21_DATA1,val)
-#define bfin_read_CAN_MB21_DATA0() bfin_read16(CAN_MB21_DATA0)
-#define bfin_write_CAN_MB21_DATA0(val) bfin_write16(CAN_MB21_DATA0,val)
-
-#define bfin_read_CAN_MB22_ID1() bfin_read16(CAN_MB22_ID1)
-#define bfin_write_CAN_MB22_ID1(val) bfin_write16(CAN_MB22_ID1,val)
-#define bfin_read_CAN_MB22_ID0() bfin_read16(CAN_MB22_ID0)
-#define bfin_write_CAN_MB22_ID0(val) bfin_write16(CAN_MB22_ID0,val)
-#define bfin_read_CAN_MB22_TIMESTAMP() bfin_read16(CAN_MB22_TIMESTAMP)
-#define bfin_write_CAN_MB22_TIMESTAMP(val) bfin_write16(CAN_MB22_TIMESTAMP,val)
-#define bfin_read_CAN_MB22_LENGTH() bfin_read16(CAN_MB22_LENGTH)
-#define bfin_write_CAN_MB22_LENGTH(val) bfin_write16(CAN_MB22_LENGTH,val)
-#define bfin_read_CAN_MB22_DATA3() bfin_read16(CAN_MB22_DATA3)
-#define bfin_write_CAN_MB22_DATA3(val) bfin_write16(CAN_MB22_DATA3,val)
-#define bfin_read_CAN_MB22_DATA2() bfin_read16(CAN_MB22_DATA2)
-#define bfin_write_CAN_MB22_DATA2(val) bfin_write16(CAN_MB22_DATA2,val)
-#define bfin_read_CAN_MB22_DATA1() bfin_read16(CAN_MB22_DATA1)
-#define bfin_write_CAN_MB22_DATA1(val) bfin_write16(CAN_MB22_DATA1,val)
-#define bfin_read_CAN_MB22_DATA0() bfin_read16(CAN_MB22_DATA0)
-#define bfin_write_CAN_MB22_DATA0(val) bfin_write16(CAN_MB22_DATA0,val)
-
-#define bfin_read_CAN_MB23_ID1() bfin_read16(CAN_MB23_ID1)
-#define bfin_write_CAN_MB23_ID1(val) bfin_write16(CAN_MB23_ID1,val)
-#define bfin_read_CAN_MB23_ID0() bfin_read16(CAN_MB23_ID0)
-#define bfin_write_CAN_MB23_ID0(val) bfin_write16(CAN_MB23_ID0,val)
-#define bfin_read_CAN_MB23_TIMESTAMP() bfin_read16(CAN_MB23_TIMESTAMP)
-#define bfin_write_CAN_MB23_TIMESTAMP(val) bfin_write16(CAN_MB23_TIMESTAMP,val)
-#define bfin_read_CAN_MB23_LENGTH() bfin_read16(CAN_MB23_LENGTH)
-#define bfin_write_CAN_MB23_LENGTH(val) bfin_write16(CAN_MB23_LENGTH,val)
-#define bfin_read_CAN_MB23_DATA3() bfin_read16(CAN_MB23_DATA3)
-#define bfin_write_CAN_MB23_DATA3(val) bfin_write16(CAN_MB23_DATA3,val)
-#define bfin_read_CAN_MB23_DATA2() bfin_read16(CAN_MB23_DATA2)
-#define bfin_write_CAN_MB23_DATA2(val) bfin_write16(CAN_MB23_DATA2,val)
-#define bfin_read_CAN_MB23_DATA1() bfin_read16(CAN_MB23_DATA1)
-#define bfin_write_CAN_MB23_DATA1(val) bfin_write16(CAN_MB23_DATA1,val)
-#define bfin_read_CAN_MB23_DATA0() bfin_read16(CAN_MB23_DATA0)
-#define bfin_write_CAN_MB23_DATA0(val) bfin_write16(CAN_MB23_DATA0,val)
-
-#define bfin_read_CAN_MB24_ID1() bfin_read16(CAN_MB24_ID1)
-#define bfin_write_CAN_MB24_ID1(val) bfin_write16(CAN_MB24_ID1,val)
-#define bfin_read_CAN_MB24_ID0() bfin_read16(CAN_MB24_ID0)
-#define bfin_write_CAN_MB24_ID0(val) bfin_write16(CAN_MB24_ID0,val)
-#define bfin_read_CAN_MB24_TIMESTAMP() bfin_read16(CAN_MB24_TIMESTAMP)
-#define bfin_write_CAN_MB24_TIMESTAMP(val) bfin_write16(CAN_MB24_TIMESTAMP,val)
-#define bfin_read_CAN_MB24_LENGTH() bfin_read16(CAN_MB24_LENGTH)
-#define bfin_write_CAN_MB24_LENGTH(val) bfin_write16(CAN_MB24_LENGTH,val)
-#define bfin_read_CAN_MB24_DATA3() bfin_read16(CAN_MB24_DATA3)
-#define bfin_write_CAN_MB24_DATA3(val) bfin_write16(CAN_MB24_DATA3,val)
-#define bfin_read_CAN_MB24_DATA2() bfin_read16(CAN_MB24_DATA2)
-#define bfin_write_CAN_MB24_DATA2(val) bfin_write16(CAN_MB24_DATA2,val)
-#define bfin_read_CAN_MB24_DATA1() bfin_read16(CAN_MB24_DATA1)
-#define bfin_write_CAN_MB24_DATA1(val) bfin_write16(CAN_MB24_DATA1,val)
-#define bfin_read_CAN_MB24_DATA0() bfin_read16(CAN_MB24_DATA0)
-#define bfin_write_CAN_MB24_DATA0(val) bfin_write16(CAN_MB24_DATA0,val)
-
-#define bfin_read_CAN_MB25_ID1() bfin_read16(CAN_MB25_ID1)
-#define bfin_write_CAN_MB25_ID1(val) bfin_write16(CAN_MB25_ID1,val)
-#define bfin_read_CAN_MB25_ID0() bfin_read16(CAN_MB25_ID0)
-#define bfin_write_CAN_MB25_ID0(val) bfin_write16(CAN_MB25_ID0,val)
-#define bfin_read_CAN_MB25_TIMESTAMP() bfin_read16(CAN_MB25_TIMESTAMP)
-#define bfin_write_CAN_MB25_TIMESTAMP(val) bfin_write16(CAN_MB25_TIMESTAMP,val)
-#define bfin_read_CAN_MB25_LENGTH() bfin_read16(CAN_MB25_LENGTH)
-#define bfin_write_CAN_MB25_LENGTH(val) bfin_write16(CAN_MB25_LENGTH,val)
-#define bfin_read_CAN_MB25_DATA3() bfin_read16(CAN_MB25_DATA3)
-#define bfin_write_CAN_MB25_DATA3(val) bfin_write16(CAN_MB25_DATA3,val)
-#define bfin_read_CAN_MB25_DATA2() bfin_read16(CAN_MB25_DATA2)
-#define bfin_write_CAN_MB25_DATA2(val) bfin_write16(CAN_MB25_DATA2,val)
-#define bfin_read_CAN_MB25_DATA1() bfin_read16(CAN_MB25_DATA1)
-#define bfin_write_CAN_MB25_DATA1(val) bfin_write16(CAN_MB25_DATA1,val)
-#define bfin_read_CAN_MB25_DATA0() bfin_read16(CAN_MB25_DATA0)
-#define bfin_write_CAN_MB25_DATA0(val) bfin_write16(CAN_MB25_DATA0,val)
-
-#define bfin_read_CAN_MB26_ID1() bfin_read16(CAN_MB26_ID1)
-#define bfin_write_CAN_MB26_ID1(val) bfin_write16(CAN_MB26_ID1,val)
-#define bfin_read_CAN_MB26_ID0() bfin_read16(CAN_MB26_ID0)
-#define bfin_write_CAN_MB26_ID0(val) bfin_write16(CAN_MB26_ID0,val)
-#define bfin_read_CAN_MB26_TIMESTAMP() bfin_read16(CAN_MB26_TIMESTAMP)
-#define bfin_write_CAN_MB26_TIMESTAMP(val) bfin_write16(CAN_MB26_TIMESTAMP,val)
-#define bfin_read_CAN_MB26_LENGTH() bfin_read16(CAN_MB26_LENGTH)
-#define bfin_write_CAN_MB26_LENGTH(val) bfin_write16(CAN_MB26_LENGTH,val)
-#define bfin_read_CAN_MB26_DATA3() bfin_read16(CAN_MB26_DATA3)
-#define bfin_write_CAN_MB26_DATA3(val) bfin_write16(CAN_MB26_DATA3,val)
-#define bfin_read_CAN_MB26_DATA2() bfin_read16(CAN_MB26_DATA2)
-#define bfin_write_CAN_MB26_DATA2(val) bfin_write16(CAN_MB26_DATA2,val)
-#define bfin_read_CAN_MB26_DATA1() bfin_read16(CAN_MB26_DATA1)
-#define bfin_write_CAN_MB26_DATA1(val) bfin_write16(CAN_MB26_DATA1,val)
-#define bfin_read_CAN_MB26_DATA0() bfin_read16(CAN_MB26_DATA0)
-#define bfin_write_CAN_MB26_DATA0(val) bfin_write16(CAN_MB26_DATA0,val)
-
-#define bfin_read_CAN_MB27_ID1() bfin_read16(CAN_MB27_ID1)
-#define bfin_write_CAN_MB27_ID1(val) bfin_write16(CAN_MB27_ID1,val)
-#define bfin_read_CAN_MB27_ID0() bfin_read16(CAN_MB27_ID0)
-#define bfin_write_CAN_MB27_ID0(val) bfin_write16(CAN_MB27_ID0,val)
-#define bfin_read_CAN_MB27_TIMESTAMP() bfin_read16(CAN_MB27_TIMESTAMP)
-#define bfin_write_CAN_MB27_TIMESTAMP(val) bfin_write16(CAN_MB27_TIMESTAMP,val)
-#define bfin_read_CAN_MB27_LENGTH() bfin_read16(CAN_MB27_LENGTH)
-#define bfin_write_CAN_MB27_LENGTH(val) bfin_write16(CAN_MB27_LENGTH,val)
-#define bfin_read_CAN_MB27_DATA3() bfin_read16(CAN_MB27_DATA3)
-#define bfin_write_CAN_MB27_DATA3(val) bfin_write16(CAN_MB27_DATA3,val)
-#define bfin_read_CAN_MB27_DATA2() bfin_read16(CAN_MB27_DATA2)
-#define bfin_write_CAN_MB27_DATA2(val) bfin_write16(CAN_MB27_DATA2,val)
-#define bfin_read_CAN_MB27_DATA1() bfin_read16(CAN_MB27_DATA1)
-#define bfin_write_CAN_MB27_DATA1(val) bfin_write16(CAN_MB27_DATA1,val)
-#define bfin_read_CAN_MB27_DATA0() bfin_read16(CAN_MB27_DATA0)
-#define bfin_write_CAN_MB27_DATA0(val) bfin_write16(CAN_MB27_DATA0,val)
-
-#define bfin_read_CAN_MB28_ID1() bfin_read16(CAN_MB28_ID1)
-#define bfin_write_CAN_MB28_ID1(val) bfin_write16(CAN_MB28_ID1,val)
-#define bfin_read_CAN_MB28_ID0() bfin_read16(CAN_MB28_ID0)
-#define bfin_write_CAN_MB28_ID0(val) bfin_write16(CAN_MB28_ID0,val)
-#define bfin_read_CAN_MB28_TIMESTAMP() bfin_read16(CAN_MB28_TIMESTAMP)
-#define bfin_write_CAN_MB28_TIMESTAMP(val) bfin_write16(CAN_MB28_TIMESTAMP,val)
-#define bfin_read_CAN_MB28_LENGTH() bfin_read16(CAN_MB28_LENGTH)
-#define bfin_write_CAN_MB28_LENGTH(val) bfin_write16(CAN_MB28_LENGTH,val)
-#define bfin_read_CAN_MB28_DATA3() bfin_read16(CAN_MB28_DATA3)
-#define bfin_write_CAN_MB28_DATA3(val) bfin_write16(CAN_MB28_DATA3,val)
-#define bfin_read_CAN_MB28_DATA2() bfin_read16(CAN_MB28_DATA2)
-#define bfin_write_CAN_MB28_DATA2(val) bfin_write16(CAN_MB28_DATA2,val)
-#define bfin_read_CAN_MB28_DATA1() bfin_read16(CAN_MB28_DATA1)
-#define bfin_write_CAN_MB28_DATA1(val) bfin_write16(CAN_MB28_DATA1,val)
-#define bfin_read_CAN_MB28_DATA0() bfin_read16(CAN_MB28_DATA0)
-#define bfin_write_CAN_MB28_DATA0(val) bfin_write16(CAN_MB28_DATA0,val)
-
-#define bfin_read_CAN_MB29_ID1() bfin_read16(CAN_MB29_ID1)
-#define bfin_write_CAN_MB29_ID1(val) bfin_write16(CAN_MB29_ID1,val)
-#define bfin_read_CAN_MB29_ID0() bfin_read16(CAN_MB29_ID0)
-#define bfin_write_CAN_MB29_ID0(val) bfin_write16(CAN_MB29_ID0,val)
-#define bfin_read_CAN_MB29_TIMESTAMP() bfin_read16(CAN_MB29_TIMESTAMP)
-#define bfin_write_CAN_MB29_TIMESTAMP(val) bfin_write16(CAN_MB29_TIMESTAMP,val)
-#define bfin_read_CAN_MB29_LENGTH() bfin_read16(CAN_MB29_LENGTH)
-#define bfin_write_CAN_MB29_LENGTH(val) bfin_write16(CAN_MB29_LENGTH,val)
-#define bfin_read_CAN_MB29_DATA3() bfin_read16(CAN_MB29_DATA3)
-#define bfin_write_CAN_MB29_DATA3(val) bfin_write16(CAN_MB29_DATA3,val)
-#define bfin_read_CAN_MB29_DATA2() bfin_read16(CAN_MB29_DATA2)
-#define bfin_write_CAN_MB29_DATA2(val) bfin_write16(CAN_MB29_DATA2,val)
-#define bfin_read_CAN_MB29_DATA1() bfin_read16(CAN_MB29_DATA1)
-#define bfin_write_CAN_MB29_DATA1(val) bfin_write16(CAN_MB29_DATA1,val)
-#define bfin_read_CAN_MB29_DATA0() bfin_read16(CAN_MB29_DATA0)
-#define bfin_write_CAN_MB29_DATA0(val) bfin_write16(CAN_MB29_DATA0,val)
-
-#define bfin_read_CAN_MB30_ID1() bfin_read16(CAN_MB30_ID1)
-#define bfin_write_CAN_MB30_ID1(val) bfin_write16(CAN_MB30_ID1,val)
-#define bfin_read_CAN_MB30_ID0() bfin_read16(CAN_MB30_ID0)
-#define bfin_write_CAN_MB30_ID0(val) bfin_write16(CAN_MB30_ID0,val)
-#define bfin_read_CAN_MB30_TIMESTAMP() bfin_read16(CAN_MB30_TIMESTAMP)
-#define bfin_write_CAN_MB30_TIMESTAMP(val) bfin_write16(CAN_MB30_TIMESTAMP,val)
-#define bfin_read_CAN_MB30_LENGTH() bfin_read16(CAN_MB30_LENGTH)
-#define bfin_write_CAN_MB30_LENGTH(val) bfin_write16(CAN_MB30_LENGTH,val)
-#define bfin_read_CAN_MB30_DATA3() bfin_read16(CAN_MB30_DATA3)
-#define bfin_write_CAN_MB30_DATA3(val) bfin_write16(CAN_MB30_DATA3,val)
-#define bfin_read_CAN_MB30_DATA2() bfin_read16(CAN_MB30_DATA2)
-#define bfin_write_CAN_MB30_DATA2(val) bfin_write16(CAN_MB30_DATA2,val)
-#define bfin_read_CAN_MB30_DATA1() bfin_read16(CAN_MB30_DATA1)
-#define bfin_write_CAN_MB30_DATA1(val) bfin_write16(CAN_MB30_DATA1,val)
-#define bfin_read_CAN_MB30_DATA0() bfin_read16(CAN_MB30_DATA0)
-#define bfin_write_CAN_MB30_DATA0(val) bfin_write16(CAN_MB30_DATA0,val)
-
-#define bfin_read_CAN_MB31_ID1() bfin_read16(CAN_MB31_ID1)
-#define bfin_write_CAN_MB31_ID1(val) bfin_write16(CAN_MB31_ID1,val)
-#define bfin_read_CAN_MB31_ID0() bfin_read16(CAN_MB31_ID0)
-#define bfin_write_CAN_MB31_ID0(val) bfin_write16(CAN_MB31_ID0,val)
-#define bfin_read_CAN_MB31_TIMESTAMP() bfin_read16(CAN_MB31_TIMESTAMP)
-#define bfin_write_CAN_MB31_TIMESTAMP(val) bfin_write16(CAN_MB31_TIMESTAMP,val)
-#define bfin_read_CAN_MB31_LENGTH() bfin_read16(CAN_MB31_LENGTH)
-#define bfin_write_CAN_MB31_LENGTH(val) bfin_write16(CAN_MB31_LENGTH,val)
-#define bfin_read_CAN_MB31_DATA3() bfin_read16(CAN_MB31_DATA3)
-#define bfin_write_CAN_MB31_DATA3(val) bfin_write16(CAN_MB31_DATA3,val)
-#define bfin_read_CAN_MB31_DATA2() bfin_read16(CAN_MB31_DATA2)
-#define bfin_write_CAN_MB31_DATA2(val) bfin_write16(CAN_MB31_DATA2,val)
-#define bfin_read_CAN_MB31_DATA1() bfin_read16(CAN_MB31_DATA1)
-#define bfin_write_CAN_MB31_DATA1(val) bfin_write16(CAN_MB31_DATA1,val)
-#define bfin_read_CAN_MB31_DATA0() bfin_read16(CAN_MB31_DATA0)
-#define bfin_write_CAN_MB31_DATA0(val) bfin_write16(CAN_MB31_DATA0,val)
-
-/* CAN Mailbox Area Macros */
-#define bfin_read_CAN_MB_ID1(x)() bfin_read16(CAN_MB_ID1(x))
-#define bfin_write_CAN_MB_ID1(x)(val) bfin_write16(CAN_MB_ID1(x),val)
-#define bfin_read_CAN_MB_ID0(x)() bfin_read16(CAN_MB_ID0(x))
-#define bfin_write_CAN_MB_ID0(x)(val) bfin_write16(CAN_MB_ID0(x),val)
-#define bfin_read_CAN_MB_TIMESTAMP(x)() bfin_read16(CAN_MB_TIMESTAMP(x))
-#define bfin_write_CAN_MB_TIMESTAMP(x)(val) bfin_write16(CAN_MB_TIMESTAMP(x),val)
-#define bfin_read_CAN_MB_LENGTH(x)() bfin_read16(CAN_MB_LENGTH(x))
-#define bfin_write_CAN_MB_LENGTH(x)(val) bfin_write16(CAN_MB_LENGTH(x),val)
-#define bfin_read_CAN_MB_DATA3(x)() bfin_read16(CAN_MB_DATA3(x))
-#define bfin_write_CAN_MB_DATA3(x)(val) bfin_write16(CAN_MB_DATA3(x),val)
-#define bfin_read_CAN_MB_DATA2(x)() bfin_read16(CAN_MB_DATA2(x))
-#define bfin_write_CAN_MB_DATA2(x)(val) bfin_write16(CAN_MB_DATA2(x),val)
-#define bfin_read_CAN_MB_DATA1(x)() bfin_read16(CAN_MB_DATA1(x))
-#define bfin_write_CAN_MB_DATA1(x)(val) bfin_write16(CAN_MB_DATA1(x),val)
-#define bfin_read_CAN_MB_DATA0(x)() bfin_read16(CAN_MB_DATA0(x))
-#define bfin_write_CAN_MB_DATA0(x)(val) bfin_write16(CAN_MB_DATA0(x),val)
-
-/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
-#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER)
-#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER,val)
-#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER)
-#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER,val)
-#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER)
-#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER,val)
-#define bfin_read_PORT_MUX() bfin_read16(BFIN_PORT_MUX)
-#define bfin_write_PORT_MUX(val) bfin_write16(BFIN_PORT_MUX,val)
-
-/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
-#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
-#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL,val)
-#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
-#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT,val)
-#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
-#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT,val)
-#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
-#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT,val)
-#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
-#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW,val)
-#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
-#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT,val)
-#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
-#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT,val)
-
-#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
-#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL,val)
-#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
-#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT,val)
-#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
-#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT,val)
-#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
-#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT,val)
-#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
-#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW,val)
-#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
-#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT,val)
-#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
-#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT,val)
-
-#endif /* _CDEF_BF534_H */
+++ /dev/null
-/*
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _CDEF_BF537_H
-#define _CDEF_BF537_H
-
-/* Include MMRs Common to BF534 */
-#include "cdefBF534.h"
-
-/* Include Macro "Defines" For EMAC (Unique to BF536/BF537 */
-/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
-#define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE)
-#define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE,val)
-#define bfin_read_EMAC_ADDRLO() bfin_read32(EMAC_ADDRLO)
-#define bfin_write_EMAC_ADDRLO(val) bfin_write32(EMAC_ADDRLO,val)
-#define bfin_read_EMAC_ADDRHI() bfin_read32(EMAC_ADDRHI)
-#define bfin_write_EMAC_ADDRHI(val) bfin_write32(EMAC_ADDRHI,val)
-#define bfin_read_EMAC_HASHLO() bfin_read32(EMAC_HASHLO)
-#define bfin_write_EMAC_HASHLO(val) bfin_write32(EMAC_HASHLO,val)
-#define bfin_read_EMAC_HASHHI() bfin_read32(EMAC_HASHHI)
-#define bfin_write_EMAC_HASHHI(val) bfin_write32(EMAC_HASHHI,val)
-#define bfin_read_EMAC_STAADD() bfin_read32(EMAC_STAADD)
-#define bfin_write_EMAC_STAADD(val) bfin_write32(EMAC_STAADD,val)
-#define bfin_read_EMAC_STADAT() bfin_read32(EMAC_STADAT)
-#define bfin_write_EMAC_STADAT(val) bfin_write32(EMAC_STADAT,val)
-#define bfin_read_EMAC_FLC() bfin_read32(EMAC_FLC)
-#define bfin_write_EMAC_FLC(val) bfin_write32(EMAC_FLC,val)
-#define bfin_read_EMAC_VLAN1() bfin_read32(EMAC_VLAN1)
-#define bfin_write_EMAC_VLAN1(val) bfin_write32(EMAC_VLAN1,val)
-#define bfin_read_EMAC_VLAN2() bfin_read32(EMAC_VLAN2)
-#define bfin_write_EMAC_VLAN2(val) bfin_write32(EMAC_VLAN2,val)
-#define bfin_read_EMAC_WKUP_CTL() bfin_read32(EMAC_WKUP_CTL)
-#define bfin_write_EMAC_WKUP_CTL(val) bfin_write32(EMAC_WKUP_CTL,val)
-#define bfin_read_EMAC_WKUP_FFMSK0() bfin_read32(EMAC_WKUP_FFMSK0)
-#define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0,val)
-#define bfin_read_EMAC_WKUP_FFMSK1() bfin_read32(EMAC_WKUP_FFMSK1)
-#define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1,val)
-#define bfin_read_EMAC_WKUP_FFMSK2() bfin_read32(EMAC_WKUP_FFMSK2)
-#define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2,val)
-#define bfin_read_EMAC_WKUP_FFMSK3() bfin_read32(EMAC_WKUP_FFMSK3)
-#define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3,val)
-#define bfin_read_EMAC_WKUP_FFCMD() bfin_read32(EMAC_WKUP_FFCMD)
-#define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD,val)
-#define bfin_read_EMAC_WKUP_FFOFF() bfin_read32(EMAC_WKUP_FFOFF)
-#define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF,val)
-#define bfin_read_EMAC_WKUP_FFCRC0() bfin_read32(EMAC_WKUP_FFCRC0)
-#define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0,val)
-#define bfin_read_EMAC_WKUP_FFCRC1() bfin_read32(EMAC_WKUP_FFCRC1)
-#define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1,val)
-
-#define bfin_read_EMAC_SYSCTL() bfin_read32(EMAC_SYSCTL)
-#define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL,val)
-#define bfin_read_EMAC_SYSTAT() bfin_read32(EMAC_SYSTAT)
-#define bfin_write_EMAC_SYSTAT(val) bfin_write32(EMAC_SYSTAT,val)
-#define bfin_read_EMAC_RX_STAT() bfin_read32(EMAC_RX_STAT)
-#define bfin_write_EMAC_RX_STAT(val) bfin_write32(EMAC_RX_STAT,val)
-#define bfin_read_EMAC_RX_STKY() bfin_read32(EMAC_RX_STKY)
-#define bfin_write_EMAC_RX_STKY(val) bfin_write32(EMAC_RX_STKY,val)
-#define bfin_read_EMAC_RX_IRQE() bfin_read32(EMAC_RX_IRQE)
-#define bfin_write_EMAC_RX_IRQE(val) bfin_write32(EMAC_RX_IRQE,val)
-#define bfin_read_EMAC_TX_STAT() bfin_read32(EMAC_TX_STAT)
-#define bfin_write_EMAC_TX_STAT(val) bfin_write32(EMAC_TX_STAT,val)
-#define bfin_read_EMAC_TX_STKY() bfin_read32(EMAC_TX_STKY)
-#define bfin_write_EMAC_TX_STKY(val) bfin_write32(EMAC_TX_STKY,val)
-#define bfin_read_EMAC_TX_IRQE() bfin_read32(EMAC_TX_IRQE)
-#define bfin_write_EMAC_TX_IRQE(val) bfin_write32(EMAC_TX_IRQE,val)
-
-#define bfin_read_EMAC_MMC_CTL() bfin_read32(EMAC_MMC_CTL)
-#define bfin_write_EMAC_MMC_CTL(val) bfin_write32(EMAC_MMC_CTL,val)
-#define bfin_read_EMAC_MMC_RIRQS() bfin_read32(EMAC_MMC_RIRQS)
-#define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS,val)
-#define bfin_read_EMAC_MMC_RIRQE() bfin_read32(EMAC_MMC_RIRQE)
-#define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE,val)
-#define bfin_read_EMAC_MMC_TIRQS() bfin_read32(EMAC_MMC_TIRQS)
-#define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS,val)
-#define bfin_read_EMAC_MMC_TIRQE() bfin_read32(EMAC_MMC_TIRQE)
-#define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE,val)
-
-#define bfin_read_EMAC_RXC_OK() bfin_read32(EMAC_RXC_OK)
-#define bfin_write_EMAC_RXC_OK(val) bfin_write32(EMAC_RXC_OK,val)
-#define bfin_read_EMAC_RXC_FCS() bfin_read32(EMAC_RXC_FCS)
-#define bfin_write_EMAC_RXC_FCS(val) bfin_write32(EMAC_RXC_FCS,val)
-#define bfin_read_EMAC_RXC_ALIGN() bfin_read32(EMAC_RXC_ALIGN)
-#define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN,val)
-#define bfin_read_EMAC_RXC_OCTET() bfin_read32(EMAC_RXC_OCTET)
-#define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET,val)
-#define bfin_read_EMAC_RXC_DMAOVF() bfin_read32(EMAC_RXC_DMAOVF)
-#define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF,val)
-#define bfin_read_EMAC_RXC_UNICST() bfin_read32(EMAC_RXC_UNICST)
-#define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST,val)
-#define bfin_read_EMAC_RXC_MULTI() bfin_read32(EMAC_RXC_MULTI)
-#define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI,val)
-#define bfin_read_EMAC_RXC_BROAD() bfin_read32(EMAC_RXC_BROAD)
-#define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD,val)
-#define bfin_read_EMAC_RXC_LNERRI() bfin_read32(EMAC_RXC_LNERRI)
-#define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI,val)
-#define bfin_read_EMAC_RXC_LNERRO() bfin_read32(EMAC_RXC_LNERRO)
-#define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO,val)
-#define bfin_read_EMAC_RXC_LONG() bfin_read32(EMAC_RXC_LONG)
-#define bfin_write_EMAC_RXC_LONG(val) bfin_write32(EMAC_RXC_LONG,val)
-#define bfin_read_EMAC_RXC_MACCTL() bfin_read32(EMAC_RXC_MACCTL)
-#define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL,val)
-#define bfin_read_EMAC_RXC_OPCODE() bfin_read32(EMAC_RXC_OPCODE)
-#define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE,val)
-#define bfin_read_EMAC_RXC_PAUSE() bfin_read32(EMAC_RXC_PAUSE)
-#define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE,val)
-#define bfin_read_EMAC_RXC_ALLFRM() bfin_read32(EMAC_RXC_ALLFRM)
-#define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM,val)
-#define bfin_read_EMAC_RXC_ALLOCT() bfin_read32(EMAC_RXC_ALLOCT)
-#define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT,val)
-#define bfin_read_EMAC_RXC_TYPED() bfin_read32(EMAC_RXC_TYPED)
-#define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED,val)
-#define bfin_read_EMAC_RXC_SHORT() bfin_read32(EMAC_RXC_SHORT)
-#define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT,val)
-#define bfin_read_EMAC_RXC_EQ64() bfin_read32(EMAC_RXC_EQ64)
-#define bfin_write_EMAC_RXC_EQ64(val) bfin_write32(EMAC_RXC_EQ64,val)
-#define bfin_read_EMAC_RXC_LT128() bfin_read32(EMAC_RXC_LT128)
-#define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128,val)
-#define bfin_read_EMAC_RXC_LT256() bfin_read32(EMAC_RXC_LT256)
-#define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256,val)
-#define bfin_read_EMAC_RXC_LT512() bfin_read32(EMAC_RXC_LT512)
-#define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512,val)
-#define bfin_read_EMAC_RXC_LT1024() bfin_read32(EMAC_RXC_LT1024)
-#define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024,val)
-#define bfin_read_EMAC_RXC_GE1024() bfin_read32(EMAC_RXC_GE1024)
-#define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024,val)
-
-#define bfin_read_EMAC_TXC_OK() bfin_read32(EMAC_TXC_OK)
-#define bfin_write_EMAC_TXC_OK(val) bfin_write32(EMAC_TXC_OK,val)
-#define bfin_read_EMAC_TXC_1COL() bfin_read32(EMAC_TXC_1COL)
-#define bfin_write_EMAC_TXC_1COL(val) bfin_write32(EMAC_TXC_1COL,val)
-#define bfin_read_EMAC_TXC_GT1COL() bfin_read32(EMAC_TXC_GT1COL)
-#define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL,val)
-#define bfin_read_EMAC_TXC_OCTET() bfin_read32(EMAC_TXC_OCTET)
-#define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET,val)
-#define bfin_read_EMAC_TXC_DEFER() bfin_read32(EMAC_TXC_DEFER)
-#define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER,val)
-#define bfin_read_EMAC_TXC_LATECL() bfin_read32(EMAC_TXC_LATECL)
-#define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL,val)
-#define bfin_read_EMAC_TXC_XS_COL() bfin_read32(EMAC_TXC_XS_COL)
-#define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL,val)
-#define bfin_read_EMAC_TXC_DMAUND() bfin_read32(EMAC_TXC_DMAUND)
-#define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND,val)
-#define bfin_read_EMAC_TXC_CRSERR() bfin_read32(EMAC_TXC_CRSERR)
-#define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR,val)
-#define bfin_read_EMAC_TXC_UNICST() bfin_read32(EMAC_TXC_UNICST)
-#define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST,val)
-#define bfin_read_EMAC_TXC_MULTI() bfin_read32(EMAC_TXC_MULTI)
-#define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI,val)
-#define bfin_read_EMAC_TXC_BROAD() bfin_read32(EMAC_TXC_BROAD)
-#define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD,val)
-#define bfin_read_EMAC_TXC_XS_DFR() bfin_read32(EMAC_TXC_XS_DFR)
-#define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR,val)
-#define bfin_read_EMAC_TXC_MACCTL() bfin_read32(EMAC_TXC_MACCTL)
-#define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL,val)
-#define bfin_read_EMAC_TXC_ALLFRM() bfin_read32(EMAC_TXC_ALLFRM)
-#define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM,val)
-#define bfin_read_EMAC_TXC_ALLOCT() bfin_read32(EMAC_TXC_ALLOCT)
-#define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT,val)
-#define bfin_read_EMAC_TXC_EQ64() bfin_read32(EMAC_TXC_EQ64)
-#define bfin_write_EMAC_TXC_EQ64(val) bfin_write32(EMAC_TXC_EQ64,val)
-#define bfin_read_EMAC_TXC_LT128() bfin_read32(EMAC_TXC_LT128)
-#define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128,val)
-#define bfin_read_EMAC_TXC_LT256() bfin_read32(EMAC_TXC_LT256)
-#define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256,val)
-#define bfin_read_EMAC_TXC_LT512() bfin_read32(EMAC_TXC_LT512)
-#define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512,val)
-#define bfin_read_EMAC_TXC_LT1024() bfin_read32(EMAC_TXC_LT1024)
-#define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024,val)
-#define bfin_read_EMAC_TXC_GE1024() bfin_read32(EMAC_TXC_GE1024)
-#define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024,val)
-#define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT)
-#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT,val)
-
-#endif /* _CDEF_BF537_H */
+++ /dev/null
-/*
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF534_H
-#define _DEF_BF534_H
-
-/************************************************************************************
-** System MMR Register Map
-*************************************************************************************/
-/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
-#define PLL_CTL 0xFFC00000 /* PLL Control Register */
-#define PLL_DIV 0xFFC00004 /* PLL Divide Register */
-#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */
-#define PLL_STAT 0xFFC0000C /* PLL Status Register */
-#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */
-#define CHIPID 0xFFC00014 /* Chip ID Register */
-
-/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
-#define SWRST 0xFFC00100 /* Software Reset Register */
-#define SYSCR 0xFFC00104 /* System Configuration Register */
-#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
-#define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */
-#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
-#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
-#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
-#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */
-#define SIC_ISR 0xFFC00120 /* Interrupt Status Register */
-#define SIC_IWR 0xFFC00124 /* Interrupt Wakeup Register */
-
-/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
-#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
-#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
-#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
-
-/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
-#define RTC_STAT 0xFFC00300 /* RTC Status Register */
-#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
-#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
-#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
-#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */
-#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */
-#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Alternate Macro */
-
-/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
-#define UART0_THR 0xFFC00400 /* Transmit Holding register */
-#define UART0_RBR 0xFFC00400 /* Receive Buffer register */
-#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
-#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */
-#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
-#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */
-#define UART0_LCR 0xFFC0040C /* Line Control Register */
-#define UART0_MCR 0xFFC00410 /* Modem Control Register */
-#define UART0_LSR 0xFFC00414 /* Line Status Register */
-#define UART0_MSR 0xFFC00418 /* Modem Status Register */
-#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */
-#define UART0_GCTL 0xFFC00424 /* Global Control Register */
-
-/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
-#define SPI0_REGBASE 0xFFC00500
-#define SPI_CTL 0xFFC00500 /* SPI Control Register */
-#define SPI_FLG 0xFFC00504 /* SPI Flag register */
-#define SPI_STAT 0xFFC00508 /* SPI Status register */
-#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */
-#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */
-#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */
-#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */
-
-/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
-#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */
-#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */
-#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */
-#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */
-
-#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */
-#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */
-#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */
-#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */
-
-#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */
-#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */
-#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */
-#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */
-
-#define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */
-#define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */
-#define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */
-#define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */
-
-#define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */
-#define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */
-#define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */
-#define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */
-
-#define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */
-#define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */
-#define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */
-#define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */
-
-#define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */
-#define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */
-#define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */
-#define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register */
-
-#define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */
-#define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */
-#define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */
-#define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */
-
-#define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */
-#define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */
-#define TIMER_STATUS 0xFFC00688 /* Timer Status Register */
-
-/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
-#define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */
-#define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */
-#define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */
-#define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */
-#define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */
-#define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */
-#define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */
-#define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */
-#define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */
-#define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */
-#define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */
-#define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */
-#define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */
-#define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */
-#define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */
-#define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */
-#define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */
-
-/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
-#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
-#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
-#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
-#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
-#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
-#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
-#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
-#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
-#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
-#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
-#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
-#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
-#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
-#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
-#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
-#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
-#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
-#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
-
-/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
-#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
-#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
-#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
-#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
-#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
-#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
-#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
-#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
-#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
-#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
-#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
-#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
-#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
-#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
-#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
-#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
-#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
-#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
-
-/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
-#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
-#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
-#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
-#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
-#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
-#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
-#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
-
-/* DMA Traffic Control Registers */
-#define DMAC_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */
-#define DMAC_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */
-
-/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
-#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
-#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
-#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
-#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
-#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
-#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
-#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
-#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
-#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
-#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
-#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
-#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
-#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
-
-#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
-#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
-#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
-#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
-#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
-#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
-#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
-#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
-#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
-#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
-#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
-#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
-#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
-
-#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
-#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
-#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
-#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
-#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
-#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
-#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
-#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
-#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
-#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
-#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
-#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
-#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
-
-#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
-#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
-#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
-#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
-#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
-#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
-#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
-#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
-#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
-#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
-#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
-#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
-#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
-
-#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
-#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
-#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
-#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
-#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
-#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
-#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
-#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
-#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
-#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
-#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
-#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
-#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
-
-#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
-#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
-#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
-#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
-#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
-#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
-#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
-#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
-#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
-#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
-#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
-#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
-#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
-
-#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
-#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
-#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
-#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
-#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
-#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
-#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
-#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
-#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
-#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
-#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
-#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
-#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
-
-#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
-#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
-#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
-#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
-#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
-#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
-#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
-#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
-#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
-#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
-#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
-#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
-#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
-
-#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
-#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */
-#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */
-#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */
-#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */
-#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */
-#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */
-#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
-#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */
-#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
-#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
-#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */
-#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
-
-#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
-#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */
-#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */
-#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */
-#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */
-#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */
-#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */
-#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
-#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */
-#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
-#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
-#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */
-#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
-
-#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
-#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */
-#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */
-#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */
-#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */
-#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */
-#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
-#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
-#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */
-#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
-#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
-#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
-#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
-
-#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
-#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */
-#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */
-#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */
-#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
-#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */
-#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
-#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
-#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */
-#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
-#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
-#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
-#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
-
-#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
-#define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */
-#define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */
-#define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */
-#define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */
-#define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */
-#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */
-#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
-#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */
-#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */
-#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */
-#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */
-#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */
-
-#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
-#define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */
-#define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */
-#define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */
-#define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */
-#define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */
-#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */
-#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
-#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */
-#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */
-#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */
-#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */
-#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */
-
-#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
-#define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */
-#define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */
-#define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */
-#define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */
-#define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */
-#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */
-#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
-#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */
-#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */
-#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */
-#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */
-#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */
-
-#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
-#define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */
-#define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */
-#define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */
-#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */
-#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */
-#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */
-#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
-#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */
-#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */
-#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */
-#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */
-#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */
-
-/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
-#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */
-#define PPI_STATUS 0xFFC01004 /* PPI Status Register */
-#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */
-#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */
-#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
-
-/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
-#define TWI0_REGBASE 0xFFC01400
-#define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
-#define TWI0_CONTROL 0xFFC01404 /* TWI Control Register */
-#define TWI0_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
-#define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
-#define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
-#define TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */
-#define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
-#define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
-#define TWI0_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */
-#define TWI0_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */
-#define TWI0_FIFO_CTL 0xFFC01428 /* FIFO Control Register */
-#define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
-#define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
-#define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
-#define TWI0_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */
-#define TWI0_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */
-
-/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
-#define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */
-#define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */
-#define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */
-#define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */
-#define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */
-#define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */
-#define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */
-#define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */
-#define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */
-#define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */
-#define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */
-#define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */
-#define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */
-#define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */
-#define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */
-#define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */
-#define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */
-
-/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
-#define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */
-#define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */
-#define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */
-#define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */
-#define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */
-#define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */
-#define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */
-#define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */
-#define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */
-#define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */
-#define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */
-#define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */
-#define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */
-#define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */
-#define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */
-#define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */
-#define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */
-
-/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
-#define UART1_THR 0xFFC02000 /* Transmit Holding register */
-#define UART1_RBR 0xFFC02000 /* Receive Buffer register */
-#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */
-#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */
-#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */
-#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */
-#define UART1_LCR 0xFFC0200C /* Line Control Register */
-#define UART1_MCR 0xFFC02010 /* Modem Control Register */
-#define UART1_LSR 0xFFC02014 /* Line Status Register */
-#define UART1_MSR 0xFFC02018 /* Modem Status Register */
-#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */
-#define UART1_GCTL 0xFFC02024 /* Global Control Register */
-
-/* CAN Controller (0xFFC02A00 - 0xFFC02FFF) */
-/* For Mailboxes 0-15 */
-#define CAN_MC1 0xFFC02A00 /* Mailbox config reg 1 */
-#define CAN_MD1 0xFFC02A04 /* Mailbox direction reg 1 */
-#define CAN_TRS1 0xFFC02A08 /* Transmit Request Set reg 1 */
-#define CAN_TRR1 0xFFC02A0C /* Transmit Request Reset reg 1 */
-#define CAN_TA1 0xFFC02A10 /* Transmit Acknowledge reg 1 */
-#define CAN_AA1 0xFFC02A14 /* Transmit Abort Acknowledge reg 1 */
-#define CAN_RMP1 0xFFC02A18 /* Receive Message Pending reg 1 */
-#define CAN_RML1 0xFFC02A1C /* Receive Message Lost reg 1 */
-#define CAN_MBTIF1 0xFFC02A20 /* Mailbox Transmit Interrupt Flag reg 1 */
-#define CAN_MBRIF1 0xFFC02A24 /* Mailbox Receive Interrupt Flag reg 1 */
-#define CAN_MBIM1 0xFFC02A28 /* Mailbox Interrupt Mask reg 1 */
-#define CAN_RFH1 0xFFC02A2C /* Remote Frame Handling reg 1 */
-#define CAN_OPSS1 0xFFC02A30 /* Overwrite Protection Single Shot Xmit reg 1 */
-
-/* For Mailboxes 16-31 */
-#define CAN_MC2 0xFFC02A40 /* Mailbox config reg 2 */
-#define CAN_MD2 0xFFC02A44 /* Mailbox direction reg 2 */
-#define CAN_TRS2 0xFFC02A48 /* Transmit Request Set reg 2 */
-#define CAN_TRR2 0xFFC02A4C /* Transmit Request Reset reg 2 */
-#define CAN_TA2 0xFFC02A50 /* Transmit Acknowledge reg 2 */
-#define CAN_AA2 0xFFC02A54 /* Transmit Abort Acknowledge reg 2 */
-#define CAN_RMP2 0xFFC02A58 /* Receive Message Pending reg 2 */
-#define CAN_RML2 0xFFC02A5C /* Receive Message Lost reg 2 */
-#define CAN_MBTIF2 0xFFC02A60 /* Mailbox Transmit Interrupt Flag reg 2 */
-#define CAN_MBRIF2 0xFFC02A64 /* Mailbox Receive Interrupt Flag reg 2 */
-#define CAN_MBIM2 0xFFC02A68 /* Mailbox Interrupt Mask reg 2 */
-#define CAN_RFH2 0xFFC02A6C /* Remote Frame Handling reg 2 */
-#define CAN_OPSS2 0xFFC02A70 /* Overwrite Protection Single Shot Xmit reg 2 */
-
-/* CAN Configuration, Control, and Status Registers */
-#define CAN_CLOCK 0xFFC02A80 /* Bit Timing Configuration register 0 */
-#define CAN_TIMING 0xFFC02A84 /* Bit Timing Configuration register 1 */
-#define CAN_DEBUG 0xFFC02A88 /* Debug Register */
-#define CAN_STATUS 0xFFC02A8C /* Global Status Register */
-#define CAN_CEC 0xFFC02A90 /* Error Counter Register */
-#define CAN_GIS 0xFFC02A94 /* Global Interrupt Status Register */
-#define CAN_GIM 0xFFC02A98 /* Global Interrupt Mask Register */
-#define CAN_GIF 0xFFC02A9C /* Global Interrupt Flag Register */
-#define CAN_CONTROL 0xFFC02AA0 /* Master Control Register */
-#define CAN_INTR 0xFFC02AA4 /* Interrupt Pending Register */
-
-#define CAN_MBTD 0xFFC02AAC /* Mailbox Temporary Disable Feature */
-#define CAN_EWR 0xFFC02AB0 /* Programmable Warning Level */
-#define CAN_ESR 0xFFC02AB4 /* Error Status Register */
-#define CAN_UCREG 0xFFC02AC0 /* Universal Counter Register/Capture Register */
-#define CAN_UCCNT 0xFFC02AC4 /* Universal Counter */
-#define CAN_UCRC 0xFFC02AC8 /* Universal Counter Force Reload Register */
-#define CAN_UCCNF 0xFFC02ACC /* Universal Counter Configuration Register */
-
-/* Mailbox Acceptance Masks */
-#define CAN_AM00L 0xFFC02B00 /* Mailbox 0 Low Acceptance Mask */
-#define CAN_AM00H 0xFFC02B04 /* Mailbox 0 High Acceptance Mask */
-#define CAN_AM01L 0xFFC02B08 /* Mailbox 1 Low Acceptance Mask */
-#define CAN_AM01H 0xFFC02B0C /* Mailbox 1 High Acceptance Mask */
-#define CAN_AM02L 0xFFC02B10 /* Mailbox 2 Low Acceptance Mask */
-#define CAN_AM02H 0xFFC02B14 /* Mailbox 2 High Acceptance Mask */
-#define CAN_AM03L 0xFFC02B18 /* Mailbox 3 Low Acceptance Mask */
-#define CAN_AM03H 0xFFC02B1C /* Mailbox 3 High Acceptance Mask */
-#define CAN_AM04L 0xFFC02B20 /* Mailbox 4 Low Acceptance Mask */
-#define CAN_AM04H 0xFFC02B24 /* Mailbox 4 High Acceptance Mask */
-#define CAN_AM05L 0xFFC02B28 /* Mailbox 5 Low Acceptance Mask */
-#define CAN_AM05H 0xFFC02B2C /* Mailbox 5 High Acceptance Mask */
-#define CAN_AM06L 0xFFC02B30 /* Mailbox 6 Low Acceptance Mask */
-#define CAN_AM06H 0xFFC02B34 /* Mailbox 6 High Acceptance Mask */
-#define CAN_AM07L 0xFFC02B38 /* Mailbox 7 Low Acceptance Mask */
-#define CAN_AM07H 0xFFC02B3C /* Mailbox 7 High Acceptance Mask */
-#define CAN_AM08L 0xFFC02B40 /* Mailbox 8 Low Acceptance Mask */
-#define CAN_AM08H 0xFFC02B44 /* Mailbox 8 High Acceptance Mask */
-#define CAN_AM09L 0xFFC02B48 /* Mailbox 9 Low Acceptance Mask */
-#define CAN_AM09H 0xFFC02B4C /* Mailbox 9 High Acceptance Mask */
-#define CAN_AM10L 0xFFC02B50 /* Mailbox 10 Low Acceptance Mask */
-#define CAN_AM10H 0xFFC02B54 /* Mailbox 10 High Acceptance Mask */
-#define CAN_AM11L 0xFFC02B58 /* Mailbox 11 Low Acceptance Mask */
-#define CAN_AM11H 0xFFC02B5C /* Mailbox 11 High Acceptance Mask */
-#define CAN_AM12L 0xFFC02B60 /* Mailbox 12 Low Acceptance Mask */
-#define CAN_AM12H 0xFFC02B64 /* Mailbox 12 High Acceptance Mask */
-#define CAN_AM13L 0xFFC02B68 /* Mailbox 13 Low Acceptance Mask */
-#define CAN_AM13H 0xFFC02B6C /* Mailbox 13 High Acceptance Mask */
-#define CAN_AM14L 0xFFC02B70 /* Mailbox 14 Low Acceptance Mask */
-#define CAN_AM14H 0xFFC02B74 /* Mailbox 14 High Acceptance Mask */
-#define CAN_AM15L 0xFFC02B78 /* Mailbox 15 Low Acceptance Mask */
-#define CAN_AM15H 0xFFC02B7C /* Mailbox 15 High Acceptance Mask */
-
-#define CAN_AM16L 0xFFC02B80 /* Mailbox 16 Low Acceptance Mask */
-#define CAN_AM16H 0xFFC02B84 /* Mailbox 16 High Acceptance Mask */
-#define CAN_AM17L 0xFFC02B88 /* Mailbox 17 Low Acceptance Mask */
-#define CAN_AM17H 0xFFC02B8C /* Mailbox 17 High Acceptance Mask */
-#define CAN_AM18L 0xFFC02B90 /* Mailbox 18 Low Acceptance Mask */
-#define CAN_AM18H 0xFFC02B94 /* Mailbox 18 High Acceptance Mask */
-#define CAN_AM19L 0xFFC02B98 /* Mailbox 19 Low Acceptance Mask */
-#define CAN_AM19H 0xFFC02B9C /* Mailbox 19 High Acceptance Mask */
-#define CAN_AM20L 0xFFC02BA0 /* Mailbox 20 Low Acceptance Mask */
-#define CAN_AM20H 0xFFC02BA4 /* Mailbox 20 High Acceptance Mask */
-#define CAN_AM21L 0xFFC02BA8 /* Mailbox 21 Low Acceptance Mask */
-#define CAN_AM21H 0xFFC02BAC /* Mailbox 21 High Acceptance Mask */
-#define CAN_AM22L 0xFFC02BB0 /* Mailbox 22 Low Acceptance Mask */
-#define CAN_AM22H 0xFFC02BB4 /* Mailbox 22 High Acceptance Mask */
-#define CAN_AM23L 0xFFC02BB8 /* Mailbox 23 Low Acceptance Mask */
-#define CAN_AM23H 0xFFC02BBC /* Mailbox 23 High Acceptance Mask */
-#define CAN_AM24L 0xFFC02BC0 /* Mailbox 24 Low Acceptance Mask */
-#define CAN_AM24H 0xFFC02BC4 /* Mailbox 24 High Acceptance Mask */
-#define CAN_AM25L 0xFFC02BC8 /* Mailbox 25 Low Acceptance Mask */
-#define CAN_AM25H 0xFFC02BCC /* Mailbox 25 High Acceptance Mask */
-#define CAN_AM26L 0xFFC02BD0 /* Mailbox 26 Low Acceptance Mask */
-#define CAN_AM26H 0xFFC02BD4 /* Mailbox 26 High Acceptance Mask */
-#define CAN_AM27L 0xFFC02BD8 /* Mailbox 27 Low Acceptance Mask */
-#define CAN_AM27H 0xFFC02BDC /* Mailbox 27 High Acceptance Mask */
-#define CAN_AM28L 0xFFC02BE0 /* Mailbox 28 Low Acceptance Mask */
-#define CAN_AM28H 0xFFC02BE4 /* Mailbox 28 High Acceptance Mask */
-#define CAN_AM29L 0xFFC02BE8 /* Mailbox 29 Low Acceptance Mask */
-#define CAN_AM29H 0xFFC02BEC /* Mailbox 29 High Acceptance Mask */
-#define CAN_AM30L 0xFFC02BF0 /* Mailbox 30 Low Acceptance Mask */
-#define CAN_AM30H 0xFFC02BF4 /* Mailbox 30 High Acceptance Mask */
-#define CAN_AM31L 0xFFC02BF8 /* Mailbox 31 Low Acceptance Mask */
-#define CAN_AM31H 0xFFC02BFC /* Mailbox 31 High Acceptance Mask */
-
-/* CAN Acceptance Mask Macros */
-#define CAN_AM_L(x) (CAN_AM00L+((x)*0x8))
-#define CAN_AM_H(x) (CAN_AM00H+((x)*0x8))
-
-/* Mailbox Registers */
-#define CAN_MB00_DATA0 0xFFC02C00 /* Mailbox 0 Data Word 0 [15:0] Register */
-#define CAN_MB00_DATA1 0xFFC02C04 /* Mailbox 0 Data Word 1 [31:16] Register */
-#define CAN_MB00_DATA2 0xFFC02C08 /* Mailbox 0 Data Word 2 [47:32] Register */
-#define CAN_MB00_DATA3 0xFFC02C0C /* Mailbox 0 Data Word 3 [63:48] Register */
-#define CAN_MB00_LENGTH 0xFFC02C10 /* Mailbox 0 Data Length Code Register */
-#define CAN_MB00_TIMESTAMP 0xFFC02C14 /* Mailbox 0 Time Stamp Value Register */
-#define CAN_MB00_ID0 0xFFC02C18 /* Mailbox 0 Identifier Low Register */
-#define CAN_MB00_ID1 0xFFC02C1C /* Mailbox 0 Identifier High Register */
-
-#define CAN_MB01_DATA0 0xFFC02C20 /* Mailbox 1 Data Word 0 [15:0] Register */
-#define CAN_MB01_DATA1 0xFFC02C24 /* Mailbox 1 Data Word 1 [31:16] Register */
-#define CAN_MB01_DATA2 0xFFC02C28 /* Mailbox 1 Data Word 2 [47:32] Register */
-#define CAN_MB01_DATA3 0xFFC02C2C /* Mailbox 1 Data Word 3 [63:48] Register */
-#define CAN_MB01_LENGTH 0xFFC02C30 /* Mailbox 1 Data Length Code Register */
-#define CAN_MB01_TIMESTAMP 0xFFC02C34 /* Mailbox 1 Time Stamp Value Register */
-#define CAN_MB01_ID0 0xFFC02C38 /* Mailbox 1 Identifier Low Register */
-#define CAN_MB01_ID1 0xFFC02C3C /* Mailbox 1 Identifier High Register */
-
-#define CAN_MB02_DATA0 0xFFC02C40 /* Mailbox 2 Data Word 0 [15:0] Register */
-#define CAN_MB02_DATA1 0xFFC02C44 /* Mailbox 2 Data Word 1 [31:16] Register */
-#define CAN_MB02_DATA2 0xFFC02C48 /* Mailbox 2 Data Word 2 [47:32] Register */
-#define CAN_MB02_DATA3 0xFFC02C4C /* Mailbox 2 Data Word 3 [63:48] Register */
-#define CAN_MB02_LENGTH 0xFFC02C50 /* Mailbox 2 Data Length Code Register */
-#define CAN_MB02_TIMESTAMP 0xFFC02C54 /* Mailbox 2 Time Stamp Value Register */
-#define CAN_MB02_ID0 0xFFC02C58 /* Mailbox 2 Identifier Low Register */
-#define CAN_MB02_ID1 0xFFC02C5C /* Mailbox 2 Identifier High Register */
-
-#define CAN_MB03_DATA0 0xFFC02C60 /* Mailbox 3 Data Word 0 [15:0] Register */
-#define CAN_MB03_DATA1 0xFFC02C64 /* Mailbox 3 Data Word 1 [31:16] Register */
-#define CAN_MB03_DATA2 0xFFC02C68 /* Mailbox 3 Data Word 2 [47:32] Register */
-#define CAN_MB03_DATA3 0xFFC02C6C /* Mailbox 3 Data Word 3 [63:48] Register */
-#define CAN_MB03_LENGTH 0xFFC02C70 /* Mailbox 3 Data Length Code Register */
-#define CAN_MB03_TIMESTAMP 0xFFC02C74 /* Mailbox 3 Time Stamp Value Register */
-#define CAN_MB03_ID0 0xFFC02C78 /* Mailbox 3 Identifier Low Register */
-#define CAN_MB03_ID1 0xFFC02C7C /* Mailbox 3 Identifier High Register */
-
-#define CAN_MB04_DATA0 0xFFC02C80 /* Mailbox 4 Data Word 0 [15:0] Register */
-#define CAN_MB04_DATA1 0xFFC02C84 /* Mailbox 4 Data Word 1 [31:16] Register */
-#define CAN_MB04_DATA2 0xFFC02C88 /* Mailbox 4 Data Word 2 [47:32] Register */
-#define CAN_MB04_DATA3 0xFFC02C8C /* Mailbox 4 Data Word 3 [63:48] Register */
-#define CAN_MB04_LENGTH 0xFFC02C90 /* Mailbox 4 Data Length Code Register */
-#define CAN_MB04_TIMESTAMP 0xFFC02C94 /* Mailbox 4 Time Stamp Value Register */
-#define CAN_MB04_ID0 0xFFC02C98 /* Mailbox 4 Identifier Low Register */
-#define CAN_MB04_ID1 0xFFC02C9C /* Mailbox 4 Identifier High Register */
-
-#define CAN_MB05_DATA0 0xFFC02CA0 /* Mailbox 5 Data Word 0 [15:0] Register */
-#define CAN_MB05_DATA1 0xFFC02CA4 /* Mailbox 5 Data Word 1 [31:16] Register */
-#define CAN_MB05_DATA2 0xFFC02CA8 /* Mailbox 5 Data Word 2 [47:32] Register */
-#define CAN_MB05_DATA3 0xFFC02CAC /* Mailbox 5 Data Word 3 [63:48] Register */
-#define CAN_MB05_LENGTH 0xFFC02CB0 /* Mailbox 5 Data Length Code Register */
-#define CAN_MB05_TIMESTAMP 0xFFC02CB4 /* Mailbox 5 Time Stamp Value Register */
-#define CAN_MB05_ID0 0xFFC02CB8 /* Mailbox 5 Identifier Low Register */
-#define CAN_MB05_ID1 0xFFC02CBC /* Mailbox 5 Identifier High Register */
-
-#define CAN_MB06_DATA0 0xFFC02CC0 /* Mailbox 6 Data Word 0 [15:0] Register */
-#define CAN_MB06_DATA1 0xFFC02CC4 /* Mailbox 6 Data Word 1 [31:16] Register */
-#define CAN_MB06_DATA2 0xFFC02CC8 /* Mailbox 6 Data Word 2 [47:32] Register */
-#define CAN_MB06_DATA3 0xFFC02CCC /* Mailbox 6 Data Word 3 [63:48] Register */
-#define CAN_MB06_LENGTH 0xFFC02CD0 /* Mailbox 6 Data Length Code Register */
-#define CAN_MB06_TIMESTAMP 0xFFC02CD4 /* Mailbox 6 Time Stamp Value Register */
-#define CAN_MB06_ID0 0xFFC02CD8 /* Mailbox 6 Identifier Low Register */
-#define CAN_MB06_ID1 0xFFC02CDC /* Mailbox 6 Identifier High Register */
-
-#define CAN_MB07_DATA0 0xFFC02CE0 /* Mailbox 7 Data Word 0 [15:0] Register */
-#define CAN_MB07_DATA1 0xFFC02CE4 /* Mailbox 7 Data Word 1 [31:16] Register */
-#define CAN_MB07_DATA2 0xFFC02CE8 /* Mailbox 7 Data Word 2 [47:32] Register */
-#define CAN_MB07_DATA3 0xFFC02CEC /* Mailbox 7 Data Word 3 [63:48] Register */
-#define CAN_MB07_LENGTH 0xFFC02CF0 /* Mailbox 7 Data Length Code Register */
-#define CAN_MB07_TIMESTAMP 0xFFC02CF4 /* Mailbox 7 Time Stamp Value Register */
-#define CAN_MB07_ID0 0xFFC02CF8 /* Mailbox 7 Identifier Low Register */
-#define CAN_MB07_ID1 0xFFC02CFC /* Mailbox 7 Identifier High Register */
-
-#define CAN_MB08_DATA0 0xFFC02D00 /* Mailbox 8 Data Word 0 [15:0] Register */
-#define CAN_MB08_DATA1 0xFFC02D04 /* Mailbox 8 Data Word 1 [31:16] Register */
-#define CAN_MB08_DATA2 0xFFC02D08 /* Mailbox 8 Data Word 2 [47:32] Register */
-#define CAN_MB08_DATA3 0xFFC02D0C /* Mailbox 8 Data Word 3 [63:48] Register */
-#define CAN_MB08_LENGTH 0xFFC02D10 /* Mailbox 8 Data Length Code Register */
-#define CAN_MB08_TIMESTAMP 0xFFC02D14 /* Mailbox 8 Time Stamp Value Register */
-#define CAN_MB08_ID0 0xFFC02D18 /* Mailbox 8 Identifier Low Register */
-#define CAN_MB08_ID1 0xFFC02D1C /* Mailbox 8 Identifier High Register */
-
-#define CAN_MB09_DATA0 0xFFC02D20 /* Mailbox 9 Data Word 0 [15:0] Register */
-#define CAN_MB09_DATA1 0xFFC02D24 /* Mailbox 9 Data Word 1 [31:16] Register */
-#define CAN_MB09_DATA2 0xFFC02D28 /* Mailbox 9 Data Word 2 [47:32] Register */
-#define CAN_MB09_DATA3 0xFFC02D2C /* Mailbox 9 Data Word 3 [63:48] Register */
-#define CAN_MB09_LENGTH 0xFFC02D30 /* Mailbox 9 Data Length Code Register */
-#define CAN_MB09_TIMESTAMP 0xFFC02D34 /* Mailbox 9 Time Stamp Value Register */
-#define CAN_MB09_ID0 0xFFC02D38 /* Mailbox 9 Identifier Low Register */
-#define CAN_MB09_ID1 0xFFC02D3C /* Mailbox 9 Identifier High Register */
-
-#define CAN_MB10_DATA0 0xFFC02D40 /* Mailbox 10 Data Word 0 [15:0] Register */
-#define CAN_MB10_DATA1 0xFFC02D44 /* Mailbox 10 Data Word 1 [31:16] Register */
-#define CAN_MB10_DATA2 0xFFC02D48 /* Mailbox 10 Data Word 2 [47:32] Register */
-#define CAN_MB10_DATA3 0xFFC02D4C /* Mailbox 10 Data Word 3 [63:48] Register */
-#define CAN_MB10_LENGTH 0xFFC02D50 /* Mailbox 10 Data Length Code Register */
-#define CAN_MB10_TIMESTAMP 0xFFC02D54 /* Mailbox 10 Time Stamp Value Register */
-#define CAN_MB10_ID0 0xFFC02D58 /* Mailbox 10 Identifier Low Register */
-#define CAN_MB10_ID1 0xFFC02D5C /* Mailbox 10 Identifier High Register */
-
-#define CAN_MB11_DATA0 0xFFC02D60 /* Mailbox 11 Data Word 0 [15:0] Register */
-#define CAN_MB11_DATA1 0xFFC02D64 /* Mailbox 11 Data Word 1 [31:16] Register */
-#define CAN_MB11_DATA2 0xFFC02D68 /* Mailbox 11 Data Word 2 [47:32] Register */
-#define CAN_MB11_DATA3 0xFFC02D6C /* Mailbox 11 Data Word 3 [63:48] Register */
-#define CAN_MB11_LENGTH 0xFFC02D70 /* Mailbox 11 Data Length Code Register */
-#define CAN_MB11_TIMESTAMP 0xFFC02D74 /* Mailbox 11 Time Stamp Value Register */
-#define CAN_MB11_ID0 0xFFC02D78 /* Mailbox 11 Identifier Low Register */
-#define CAN_MB11_ID1 0xFFC02D7C /* Mailbox 11 Identifier High Register */
-
-#define CAN_MB12_DATA0 0xFFC02D80 /* Mailbox 12 Data Word 0 [15:0] Register */
-#define CAN_MB12_DATA1 0xFFC02D84 /* Mailbox 12 Data Word 1 [31:16] Register */
-#define CAN_MB12_DATA2 0xFFC02D88 /* Mailbox 12 Data Word 2 [47:32] Register */
-#define CAN_MB12_DATA3 0xFFC02D8C /* Mailbox 12 Data Word 3 [63:48] Register */
-#define CAN_MB12_LENGTH 0xFFC02D90 /* Mailbox 12 Data Length Code Register */
-#define CAN_MB12_TIMESTAMP 0xFFC02D94 /* Mailbox 12 Time Stamp Value Register */
-#define CAN_MB12_ID0 0xFFC02D98 /* Mailbox 12 Identifier Low Register */
-#define CAN_MB12_ID1 0xFFC02D9C /* Mailbox 12 Identifier High Register */
-
-#define CAN_MB13_DATA0 0xFFC02DA0 /* Mailbox 13 Data Word 0 [15:0] Register */
-#define CAN_MB13_DATA1 0xFFC02DA4 /* Mailbox 13 Data Word 1 [31:16] Register */
-#define CAN_MB13_DATA2 0xFFC02DA8 /* Mailbox 13 Data Word 2 [47:32] Register */
-#define CAN_MB13_DATA3 0xFFC02DAC /* Mailbox 13 Data Word 3 [63:48] Register */
-#define CAN_MB13_LENGTH 0xFFC02DB0 /* Mailbox 13 Data Length Code Register */
-#define CAN_MB13_TIMESTAMP 0xFFC02DB4 /* Mailbox 13 Time Stamp Value Register */
-#define CAN_MB13_ID0 0xFFC02DB8 /* Mailbox 13 Identifier Low Register */
-#define CAN_MB13_ID1 0xFFC02DBC /* Mailbox 13 Identifier High Register */
-
-#define CAN_MB14_DATA0 0xFFC02DC0 /* Mailbox 14 Data Word 0 [15:0] Register */
-#define CAN_MB14_DATA1 0xFFC02DC4 /* Mailbox 14 Data Word 1 [31:16] Register */
-#define CAN_MB14_DATA2 0xFFC02DC8 /* Mailbox 14 Data Word 2 [47:32] Register */
-#define CAN_MB14_DATA3 0xFFC02DCC /* Mailbox 14 Data Word 3 [63:48] Register */
-#define CAN_MB14_LENGTH 0xFFC02DD0 /* Mailbox 14 Data Length Code Register */
-#define CAN_MB14_TIMESTAMP 0xFFC02DD4 /* Mailbox 14 Time Stamp Value Register */
-#define CAN_MB14_ID0 0xFFC02DD8 /* Mailbox 14 Identifier Low Register */
-#define CAN_MB14_ID1 0xFFC02DDC /* Mailbox 14 Identifier High Register */
-
-#define CAN_MB15_DATA0 0xFFC02DE0 /* Mailbox 15 Data Word 0 [15:0] Register */
-#define CAN_MB15_DATA1 0xFFC02DE4 /* Mailbox 15 Data Word 1 [31:16] Register */
-#define CAN_MB15_DATA2 0xFFC02DE8 /* Mailbox 15 Data Word 2 [47:32] Register */
-#define CAN_MB15_DATA3 0xFFC02DEC /* Mailbox 15 Data Word 3 [63:48] Register */
-#define CAN_MB15_LENGTH 0xFFC02DF0 /* Mailbox 15 Data Length Code Register */
-#define CAN_MB15_TIMESTAMP 0xFFC02DF4 /* Mailbox 15 Time Stamp Value Register */
-#define CAN_MB15_ID0 0xFFC02DF8 /* Mailbox 15 Identifier Low Register */
-#define CAN_MB15_ID1 0xFFC02DFC /* Mailbox 15 Identifier High Register */
-
-#define CAN_MB16_DATA0 0xFFC02E00 /* Mailbox 16 Data Word 0 [15:0] Register */
-#define CAN_MB16_DATA1 0xFFC02E04 /* Mailbox 16 Data Word 1 [31:16] Register */
-#define CAN_MB16_DATA2 0xFFC02E08 /* Mailbox 16 Data Word 2 [47:32] Register */
-#define CAN_MB16_DATA3 0xFFC02E0C /* Mailbox 16 Data Word 3 [63:48] Register */
-#define CAN_MB16_LENGTH 0xFFC02E10 /* Mailbox 16 Data Length Code Register */
-#define CAN_MB16_TIMESTAMP 0xFFC02E14 /* Mailbox 16 Time Stamp Value Register */
-#define CAN_MB16_ID0 0xFFC02E18 /* Mailbox 16 Identifier Low Register */
-#define CAN_MB16_ID1 0xFFC02E1C /* Mailbox 16 Identifier High Register */
-
-#define CAN_MB17_DATA0 0xFFC02E20 /* Mailbox 17 Data Word 0 [15:0] Register */
-#define CAN_MB17_DATA1 0xFFC02E24 /* Mailbox 17 Data Word 1 [31:16] Register */
-#define CAN_MB17_DATA2 0xFFC02E28 /* Mailbox 17 Data Word 2 [47:32] Register */
-#define CAN_MB17_DATA3 0xFFC02E2C /* Mailbox 17 Data Word 3 [63:48] Register */
-#define CAN_MB17_LENGTH 0xFFC02E30 /* Mailbox 17 Data Length Code Register */
-#define CAN_MB17_TIMESTAMP 0xFFC02E34 /* Mailbox 17 Time Stamp Value Register */
-#define CAN_MB17_ID0 0xFFC02E38 /* Mailbox 17 Identifier Low Register */
-#define CAN_MB17_ID1 0xFFC02E3C /* Mailbox 17 Identifier High Register */
-
-#define CAN_MB18_DATA0 0xFFC02E40 /* Mailbox 18 Data Word 0 [15:0] Register */
-#define CAN_MB18_DATA1 0xFFC02E44 /* Mailbox 18 Data Word 1 [31:16] Register */
-#define CAN_MB18_DATA2 0xFFC02E48 /* Mailbox 18 Data Word 2 [47:32] Register */
-#define CAN_MB18_DATA3 0xFFC02E4C /* Mailbox 18 Data Word 3 [63:48] Register */
-#define CAN_MB18_LENGTH 0xFFC02E50 /* Mailbox 18 Data Length Code Register */
-#define CAN_MB18_TIMESTAMP 0xFFC02E54 /* Mailbox 18 Time Stamp Value Register */
-#define CAN_MB18_ID0 0xFFC02E58 /* Mailbox 18 Identifier Low Register */
-#define CAN_MB18_ID1 0xFFC02E5C /* Mailbox 18 Identifier High Register */
-
-#define CAN_MB19_DATA0 0xFFC02E60 /* Mailbox 19 Data Word 0 [15:0] Register */
-#define CAN_MB19_DATA1 0xFFC02E64 /* Mailbox 19 Data Word 1 [31:16] Register */
-#define CAN_MB19_DATA2 0xFFC02E68 /* Mailbox 19 Data Word 2 [47:32] Register */
-#define CAN_MB19_DATA3 0xFFC02E6C /* Mailbox 19 Data Word 3 [63:48] Register */
-#define CAN_MB19_LENGTH 0xFFC02E70 /* Mailbox 19 Data Length Code Register */
-#define CAN_MB19_TIMESTAMP 0xFFC02E74 /* Mailbox 19 Time Stamp Value Register */
-#define CAN_MB19_ID0 0xFFC02E78 /* Mailbox 19 Identifier Low Register */
-#define CAN_MB19_ID1 0xFFC02E7C /* Mailbox 19 Identifier High Register */
-
-#define CAN_MB20_DATA0 0xFFC02E80 /* Mailbox 20 Data Word 0 [15:0] Register */
-#define CAN_MB20_DATA1 0xFFC02E84 /* Mailbox 20 Data Word 1 [31:16] Register */
-#define CAN_MB20_DATA2 0xFFC02E88 /* Mailbox 20 Data Word 2 [47:32] Register */
-#define CAN_MB20_DATA3 0xFFC02E8C /* Mailbox 20 Data Word 3 [63:48] Register */
-#define CAN_MB20_LENGTH 0xFFC02E90 /* Mailbox 20 Data Length Code Register */
-#define CAN_MB20_TIMESTAMP 0xFFC02E94 /* Mailbox 20 Time Stamp Value Register */
-#define CAN_MB20_ID0 0xFFC02E98 /* Mailbox 20 Identifier Low Register */
-#define CAN_MB20_ID1 0xFFC02E9C /* Mailbox 20 Identifier High Register */
-
-#define CAN_MB21_DATA0 0xFFC02EA0 /* Mailbox 21 Data Word 0 [15:0] Register */
-#define CAN_MB21_DATA1 0xFFC02EA4 /* Mailbox 21 Data Word 1 [31:16] Register */
-#define CAN_MB21_DATA2 0xFFC02EA8 /* Mailbox 21 Data Word 2 [47:32] Register */
-#define CAN_MB21_DATA3 0xFFC02EAC /* Mailbox 21 Data Word 3 [63:48] Register */
-#define CAN_MB21_LENGTH 0xFFC02EB0 /* Mailbox 21 Data Length Code Register */
-#define CAN_MB21_TIMESTAMP 0xFFC02EB4 /* Mailbox 21 Time Stamp Value Register */
-#define CAN_MB21_ID0 0xFFC02EB8 /* Mailbox 21 Identifier Low Register */
-#define CAN_MB21_ID1 0xFFC02EBC /* Mailbox 21 Identifier High Register */
-
-#define CAN_MB22_DATA0 0xFFC02EC0 /* Mailbox 22 Data Word 0 [15:0] Register */
-#define CAN_MB22_DATA1 0xFFC02EC4 /* Mailbox 22 Data Word 1 [31:16] Register */
-#define CAN_MB22_DATA2 0xFFC02EC8 /* Mailbox 22 Data Word 2 [47:32] Register */
-#define CAN_MB22_DATA3 0xFFC02ECC /* Mailbox 22 Data Word 3 [63:48] Register */
-#define CAN_MB22_LENGTH 0xFFC02ED0 /* Mailbox 22 Data Length Code Register */
-#define CAN_MB22_TIMESTAMP 0xFFC02ED4 /* Mailbox 22 Time Stamp Value Register */
-#define CAN_MB22_ID0 0xFFC02ED8 /* Mailbox 22 Identifier Low Register */
-#define CAN_MB22_ID1 0xFFC02EDC /* Mailbox 22 Identifier High Register */
-
-#define CAN_MB23_DATA0 0xFFC02EE0 /* Mailbox 23 Data Word 0 [15:0] Register */
-#define CAN_MB23_DATA1 0xFFC02EE4 /* Mailbox 23 Data Word 1 [31:16] Register */
-#define CAN_MB23_DATA2 0xFFC02EE8 /* Mailbox 23 Data Word 2 [47:32] Register */
-#define CAN_MB23_DATA3 0xFFC02EEC /* Mailbox 23 Data Word 3 [63:48] Register */
-#define CAN_MB23_LENGTH 0xFFC02EF0 /* Mailbox 23 Data Length Code Register */
-#define CAN_MB23_TIMESTAMP 0xFFC02EF4 /* Mailbox 23 Time Stamp Value Register */
-#define CAN_MB23_ID0 0xFFC02EF8 /* Mailbox 23 Identifier Low Register */
-#define CAN_MB23_ID1 0xFFC02EFC /* Mailbox 23 Identifier High Register */
-
-#define CAN_MB24_DATA0 0xFFC02F00 /* Mailbox 24 Data Word 0 [15:0] Register */
-#define CAN_MB24_DATA1 0xFFC02F04 /* Mailbox 24 Data Word 1 [31:16] Register */
-#define CAN_MB24_DATA2 0xFFC02F08 /* Mailbox 24 Data Word 2 [47:32] Register */
-#define CAN_MB24_DATA3 0xFFC02F0C /* Mailbox 24 Data Word 3 [63:48] Register */
-#define CAN_MB24_LENGTH 0xFFC02F10 /* Mailbox 24 Data Length Code Register */
-#define CAN_MB24_TIMESTAMP 0xFFC02F14 /* Mailbox 24 Time Stamp Value Register */
-#define CAN_MB24_ID0 0xFFC02F18 /* Mailbox 24 Identifier Low Register */
-#define CAN_MB24_ID1 0xFFC02F1C /* Mailbox 24 Identifier High Register */
-
-#define CAN_MB25_DATA0 0xFFC02F20 /* Mailbox 25 Data Word 0 [15:0] Register */
-#define CAN_MB25_DATA1 0xFFC02F24 /* Mailbox 25 Data Word 1 [31:16] Register */
-#define CAN_MB25_DATA2 0xFFC02F28 /* Mailbox 25 Data Word 2 [47:32] Register */
-#define CAN_MB25_DATA3 0xFFC02F2C /* Mailbox 25 Data Word 3 [63:48] Register */
-#define CAN_MB25_LENGTH 0xFFC02F30 /* Mailbox 25 Data Length Code Register */
-#define CAN_MB25_TIMESTAMP 0xFFC02F34 /* Mailbox 25 Time Stamp Value Register */
-#define CAN_MB25_ID0 0xFFC02F38 /* Mailbox 25 Identifier Low Register */
-#define CAN_MB25_ID1 0xFFC02F3C /* Mailbox 25 Identifier High Register */
-
-#define CAN_MB26_DATA0 0xFFC02F40 /* Mailbox 26 Data Word 0 [15:0] Register */
-#define CAN_MB26_DATA1 0xFFC02F44 /* Mailbox 26 Data Word 1 [31:16] Register */
-#define CAN_MB26_DATA2 0xFFC02F48 /* Mailbox 26 Data Word 2 [47:32] Register */
-#define CAN_MB26_DATA3 0xFFC02F4C /* Mailbox 26 Data Word 3 [63:48] Register */
-#define CAN_MB26_LENGTH 0xFFC02F50 /* Mailbox 26 Data Length Code Register */
-#define CAN_MB26_TIMESTAMP 0xFFC02F54 /* Mailbox 26 Time Stamp Value Register */
-#define CAN_MB26_ID0 0xFFC02F58 /* Mailbox 26 Identifier Low Register */
-#define CAN_MB26_ID1 0xFFC02F5C /* Mailbox 26 Identifier High Register */
-
-#define CAN_MB27_DATA0 0xFFC02F60 /* Mailbox 27 Data Word 0 [15:0] Register */
-#define CAN_MB27_DATA1 0xFFC02F64 /* Mailbox 27 Data Word 1 [31:16] Register */
-#define CAN_MB27_DATA2 0xFFC02F68 /* Mailbox 27 Data Word 2 [47:32] Register */
-#define CAN_MB27_DATA3 0xFFC02F6C /* Mailbox 27 Data Word 3 [63:48] Register */
-#define CAN_MB27_LENGTH 0xFFC02F70 /* Mailbox 27 Data Length Code Register */
-#define CAN_MB27_TIMESTAMP 0xFFC02F74 /* Mailbox 27 Time Stamp Value Register */
-#define CAN_MB27_ID0 0xFFC02F78 /* Mailbox 27 Identifier Low Register */
-#define CAN_MB27_ID1 0xFFC02F7C /* Mailbox 27 Identifier High Register */
-
-#define CAN_MB28_DATA0 0xFFC02F80 /* Mailbox 28 Data Word 0 [15:0] Register */
-#define CAN_MB28_DATA1 0xFFC02F84 /* Mailbox 28 Data Word 1 [31:16] Register */
-#define CAN_MB28_DATA2 0xFFC02F88 /* Mailbox 28 Data Word 2 [47:32] Register */
-#define CAN_MB28_DATA3 0xFFC02F8C /* Mailbox 28 Data Word 3 [63:48] Register */
-#define CAN_MB28_LENGTH 0xFFC02F90 /* Mailbox 28 Data Length Code Register */
-#define CAN_MB28_TIMESTAMP 0xFFC02F94 /* Mailbox 28 Time Stamp Value Register */
-#define CAN_MB28_ID0 0xFFC02F98 /* Mailbox 28 Identifier Low Register */
-#define CAN_MB28_ID1 0xFFC02F9C /* Mailbox 28 Identifier High Register */
-
-#define CAN_MB29_DATA0 0xFFC02FA0 /* Mailbox 29 Data Word 0 [15:0] Register */
-#define CAN_MB29_DATA1 0xFFC02FA4 /* Mailbox 29 Data Word 1 [31:16] Register */
-#define CAN_MB29_DATA2 0xFFC02FA8 /* Mailbox 29 Data Word 2 [47:32] Register */
-#define CAN_MB29_DATA3 0xFFC02FAC /* Mailbox 29 Data Word 3 [63:48] Register */
-#define CAN_MB29_LENGTH 0xFFC02FB0 /* Mailbox 29 Data Length Code Register */
-#define CAN_MB29_TIMESTAMP 0xFFC02FB4 /* Mailbox 29 Time Stamp Value Register */
-#define CAN_MB29_ID0 0xFFC02FB8 /* Mailbox 29 Identifier Low Register */
-#define CAN_MB29_ID1 0xFFC02FBC /* Mailbox 29 Identifier High Register */
-
-#define CAN_MB30_DATA0 0xFFC02FC0 /* Mailbox 30 Data Word 0 [15:0] Register */
-#define CAN_MB30_DATA1 0xFFC02FC4 /* Mailbox 30 Data Word 1 [31:16] Register */
-#define CAN_MB30_DATA2 0xFFC02FC8 /* Mailbox 30 Data Word 2 [47:32] Register */
-#define CAN_MB30_DATA3 0xFFC02FCC /* Mailbox 30 Data Word 3 [63:48] Register */
-#define CAN_MB30_LENGTH 0xFFC02FD0 /* Mailbox 30 Data Length Code Register */
-#define CAN_MB30_TIMESTAMP 0xFFC02FD4 /* Mailbox 30 Time Stamp Value Register */
-#define CAN_MB30_ID0 0xFFC02FD8 /* Mailbox 30 Identifier Low Register */
-#define CAN_MB30_ID1 0xFFC02FDC /* Mailbox 30 Identifier High Register */
-
-#define CAN_MB31_DATA0 0xFFC02FE0 /* Mailbox 31 Data Word 0 [15:0] Register */
-#define CAN_MB31_DATA1 0xFFC02FE4 /* Mailbox 31 Data Word 1 [31:16] Register */
-#define CAN_MB31_DATA2 0xFFC02FE8 /* Mailbox 31 Data Word 2 [47:32] Register */
-#define CAN_MB31_DATA3 0xFFC02FEC /* Mailbox 31 Data Word 3 [63:48] Register */
-#define CAN_MB31_LENGTH 0xFFC02FF0 /* Mailbox 31 Data Length Code Register */
-#define CAN_MB31_TIMESTAMP 0xFFC02FF4 /* Mailbox 31 Time Stamp Value Register */
-#define CAN_MB31_ID0 0xFFC02FF8 /* Mailbox 31 Identifier Low Register */
-#define CAN_MB31_ID1 0xFFC02FFC /* Mailbox 31 Identifier High Register */
-
-/* CAN Mailbox Area Macros */
-#define CAN_MB_ID1(x) (CAN_MB00_ID1+((x)*0x20))
-#define CAN_MB_ID0(x) (CAN_MB00_ID0+((x)*0x20))
-#define CAN_MB_TIMESTAMP(x) (CAN_MB00_TIMESTAMP+((x)*0x20))
-#define CAN_MB_LENGTH(x) (CAN_MB00_LENGTH+((x)*0x20))
-#define CAN_MB_DATA3(x) (CAN_MB00_DATA3+((x)*0x20))
-#define CAN_MB_DATA2(x) (CAN_MB00_DATA2+((x)*0x20))
-#define CAN_MB_DATA1(x) (CAN_MB00_DATA1+((x)*0x20))
-#define CAN_MB_DATA0(x) (CAN_MB00_DATA0+((x)*0x20))
-
-/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
-#define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */
-#define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */
-#define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */
-#define BFIN_PORT_MUX 0xFFC0320C /* Port Multiplexer Control Register */
-
-/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
-#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */
-#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */
-#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */
-#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshold Register */
-#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */
-#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */
-#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */
-
-#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */
-#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */
-#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */
-#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshold Register */
-#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */
-#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */
-#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */
-
-/***********************************************************************************
-** System MMR Register Bits And Macros
-**
-** Disclaimer: All macros are intended to make C and Assembly code more readable.
-** Use these macros carefully, as any that do left shifts for field
-** depositing will result in the lower order bits being destroyed. Any
-** macro that shifts left to properly position the bit-field should be
-** used as part of an OR to initialize a register and NOT as a dynamic
-** modifier UNLESS the lower order bits are saved and ORed back in when
-** the macro is used.
-*************************************************************************************/
-
-/* CHIPID Masks */
-#define CHIPID_VERSION 0xF0000000
-#define CHIPID_FAMILY 0x0FFFF000
-#define CHIPID_MANUFACTURE 0x00000FFE
-
-/* SWRST Masks */
-#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
-#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
-#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
-#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
-#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
-
-/* SYSCR Masks */
-#define BMODE 0x0007 /* Boot Mode - Latched During HW Reset From Mode Pins */
-#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
-
-/* ************* SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
-
-/* SIC_IAR0 Macros */
-#define P0_IVG(x) (((x)&0xF)-7) /* Peripheral #0 assigned IVG #x */
-#define P1_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #1 assigned IVG #x */
-#define P2_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #2 assigned IVG #x */
-#define P3_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #3 assigned IVG #x */
-#define P4_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #4 assigned IVG #x */
-#define P5_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #5 assigned IVG #x */
-#define P6_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #6 assigned IVG #x */
-#define P7_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #7 assigned IVG #x */
-
-/* SIC_IAR1 Macros */
-#define P8_IVG(x) (((x)&0xF)-7) /* Peripheral #8 assigned IVG #x */
-#define P9_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #9 assigned IVG #x */
-#define P10_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #10 assigned IVG #x */
-#define P11_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #11 assigned IVG #x */
-#define P12_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #12 assigned IVG #x */
-#define P13_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #13 assigned IVG #x */
-#define P14_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #14 assigned IVG #x */
-#define P15_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #15 assigned IVG #x */
-
-/* SIC_IAR2 Macros */
-#define P16_IVG(x) (((x)&0xF)-7) /* Peripheral #16 assigned IVG #x */
-#define P17_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #17 assigned IVG #x */
-#define P18_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #18 assigned IVG #x */
-#define P19_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #19 assigned IVG #x */
-#define P20_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #20 assigned IVG #x */
-#define P21_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #21 assigned IVG #x */
-#define P22_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #22 assigned IVG #x */
-#define P23_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #23 assigned IVG #x */
-
-/* SIC_IAR3 Macros */
-#define P24_IVG(x) (((x)&0xF)-7) /* Peripheral #24 assigned IVG #x */
-#define P25_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #25 assigned IVG #x */
-#define P26_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #26 assigned IVG #x */
-#define P27_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #27 assigned IVG #x */
-#define P28_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #28 assigned IVG #x */
-#define P29_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #29 assigned IVG #x */
-#define P30_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #30 assigned IVG #x */
-#define P31_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #31 assigned IVG #x */
-
-/* SIC_IMASK Masks */
-#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
-#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
-#define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
-#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
-
-/* SIC_IWR Masks */
-#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
-#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
-#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
-#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
-
-/* **************** GENERAL PURPOSE TIMER MASKS **********************/
-/* TIMER_ENABLE Masks */
-#define TIMEN0 0x0001 /* Enable Timer 0 */
-#define TIMEN1 0x0002 /* Enable Timer 1 */
-#define TIMEN2 0x0004 /* Enable Timer 2 */
-#define TIMEN3 0x0008 /* Enable Timer 3 */
-#define TIMEN4 0x0010 /* Enable Timer 4 */
-#define TIMEN5 0x0020 /* Enable Timer 5 */
-#define TIMEN6 0x0040 /* Enable Timer 6 */
-#define TIMEN7 0x0080 /* Enable Timer 7 */
-
-/* TIMER_DISABLE Masks */
-#define TIMDIS0 TIMEN0 /* Disable Timer 0 */
-#define TIMDIS1 TIMEN1 /* Disable Timer 1 */
-#define TIMDIS2 TIMEN2 /* Disable Timer 2 */
-#define TIMDIS3 TIMEN3 /* Disable Timer 3 */
-#define TIMDIS4 TIMEN4 /* Disable Timer 4 */
-#define TIMDIS5 TIMEN5 /* Disable Timer 5 */
-#define TIMDIS6 TIMEN6 /* Disable Timer 6 */
-#define TIMDIS7 TIMEN7 /* Disable Timer 7 */
-
-/* TIMER_STATUS Masks */
-#define TIMIL0 0x00000001 /* Timer 0 Interrupt */
-#define TIMIL1 0x00000002 /* Timer 1 Interrupt */
-#define TIMIL2 0x00000004 /* Timer 2 Interrupt */
-#define TIMIL3 0x00000008 /* Timer 3 Interrupt */
-#define TOVF_ERR0 0x00000010 /* Timer 0 Counter Overflow */
-#define TOVF_ERR1 0x00000020 /* Timer 1 Counter Overflow */
-#define TOVF_ERR2 0x00000040 /* Timer 2 Counter Overflow */
-#define TOVF_ERR3 0x00000080 /* Timer 3 Counter Overflow */
-#define TRUN0 0x00001000 /* Timer 0 Slave Enable Status */
-#define TRUN1 0x00002000 /* Timer 1 Slave Enable Status */
-#define TRUN2 0x00004000 /* Timer 2 Slave Enable Status */
-#define TRUN3 0x00008000 /* Timer 3 Slave Enable Status */
-#define TIMIL4 0x00010000 /* Timer 4 Interrupt */
-#define TIMIL5 0x00020000 /* Timer 5 Interrupt */
-#define TIMIL6 0x00040000 /* Timer 6 Interrupt */
-#define TIMIL7 0x00080000 /* Timer 7 Interrupt */
-#define TOVF_ERR4 0x00100000 /* Timer 4 Counter Overflow */
-#define TOVF_ERR5 0x00200000 /* Timer 5 Counter Overflow */
-#define TOVF_ERR6 0x00400000 /* Timer 6 Counter Overflow */
-#define TOVF_ERR7 0x00800000 /* Timer 7 Counter Overflow */
-#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */
-#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */
-#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */
-#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define TOVL_ERR0 TOVF_ERR0
-#define TOVL_ERR1 TOVF_ERR1
-#define TOVL_ERR2 TOVF_ERR2
-#define TOVL_ERR3 TOVF_ERR3
-#define TOVL_ERR4 TOVF_ERR4
-#define TOVL_ERR5 TOVF_ERR5
-#define TOVL_ERR6 TOVF_ERR6
-#define TOVL_ERR7 TOVF_ERR7
-/* TIMERx_CONFIG Masks */
-#define PWM_OUT 0x0001 /* Pulse-Width Modulation Output Mode */
-#define WDTH_CAP 0x0002 /* Width Capture Input Mode */
-#define EXT_CLK 0x0003 /* External Clock Mode */
-#define PULSE_HI 0x0004 /* Action Pulse (Positive/Negative*) */
-#define PERIOD_CNT 0x0008 /* Period Count */
-#define IRQ_ENA 0x0010 /* Interrupt Request Enable */
-#define TIN_SEL 0x0020 /* Timer Input Select */
-#define OUT_DIS 0x0040 /* Output Pad Disable */
-#define CLK_SEL 0x0080 /* Timer Clock Select */
-#define TOGGLE_HI 0x0100 /* PWM_OUT PULSE_HI Toggle Mode */
-#define EMU_RUN 0x0200 /* Emulation Behavior Select */
-#define ERR_TYP 0xC000 /* Error Type */
-
-/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/
-/* EBIU_AMGCTL Masks */
-#define AMCKEN 0x0001 /* Enable CLKOUT */
-#define AMBEN_NONE 0x0000 /* All Banks Disabled */
-#define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */
-#define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */
-#define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */
-#define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */
-
-/* EBIU_AMBCTL0 Masks */
-#define B0RDYEN 0x00000001 /* Bank 0 (B0) RDY Enable */
-#define B0RDYPOL 0x00000002 /* B0 RDY Active High */
-#define B0TT_1 0x00000004 /* B0 Transition Time (Read to Write) = 1 cycle */
-#define B0TT_2 0x00000008 /* B0 Transition Time (Read to Write) = 2 cycles */
-#define B0TT_3 0x0000000C /* B0 Transition Time (Read to Write) = 3 cycles */
-#define B0TT_4 0x00000000 /* B0 Transition Time (Read to Write) = 4 cycles */
-#define B0ST_1 0x00000010 /* B0 Setup Time (AOE to Read/Write) = 1 cycle */
-#define B0ST_2 0x00000020 /* B0 Setup Time (AOE to Read/Write) = 2 cycles */
-#define B0ST_3 0x00000030 /* B0 Setup Time (AOE to Read/Write) = 3 cycles */
-#define B0ST_4 0x00000000 /* B0 Setup Time (AOE to Read/Write) = 4 cycles */
-#define B0HT_1 0x00000040 /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle */
-#define B0HT_2 0x00000080 /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles */
-#define B0HT_3 0x000000C0 /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles */
-#define B0HT_0 0x00000000 /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles */
-#define B0RAT_1 0x00000100 /* B0 Read Access Time = 1 cycle */
-#define B0RAT_2 0x00000200 /* B0 Read Access Time = 2 cycles */
-#define B0RAT_3 0x00000300 /* B0 Read Access Time = 3 cycles */
-#define B0RAT_4 0x00000400 /* B0 Read Access Time = 4 cycles */
-#define B0RAT_5 0x00000500 /* B0 Read Access Time = 5 cycles */
-#define B0RAT_6 0x00000600 /* B0 Read Access Time = 6 cycles */
-#define B0RAT_7 0x00000700 /* B0 Read Access Time = 7 cycles */
-#define B0RAT_8 0x00000800 /* B0 Read Access Time = 8 cycles */
-#define B0RAT_9 0x00000900 /* B0 Read Access Time = 9 cycles */
-#define B0RAT_10 0x00000A00 /* B0 Read Access Time = 10 cycles */
-#define B0RAT_11 0x00000B00 /* B0 Read Access Time = 11 cycles */
-#define B0RAT_12 0x00000C00 /* B0 Read Access Time = 12 cycles */
-#define B0RAT_13 0x00000D00 /* B0 Read Access Time = 13 cycles */
-#define B0RAT_14 0x00000E00 /* B0 Read Access Time = 14 cycles */
-#define B0RAT_15 0x00000F00 /* B0 Read Access Time = 15 cycles */
-#define B0WAT_1 0x00001000 /* B0 Write Access Time = 1 cycle */
-#define B0WAT_2 0x00002000 /* B0 Write Access Time = 2 cycles */
-#define B0WAT_3 0x00003000 /* B0 Write Access Time = 3 cycles */
-#define B0WAT_4 0x00004000 /* B0 Write Access Time = 4 cycles */
-#define B0WAT_5 0x00005000 /* B0 Write Access Time = 5 cycles */
-#define B0WAT_6 0x00006000 /* B0 Write Access Time = 6 cycles */
-#define B0WAT_7 0x00007000 /* B0 Write Access Time = 7 cycles */
-#define B0WAT_8 0x00008000 /* B0 Write Access Time = 8 cycles */
-#define B0WAT_9 0x00009000 /* B0 Write Access Time = 9 cycles */
-#define B0WAT_10 0x0000A000 /* B0 Write Access Time = 10 cycles */
-#define B0WAT_11 0x0000B000 /* B0 Write Access Time = 11 cycles */
-#define B0WAT_12 0x0000C000 /* B0 Write Access Time = 12 cycles */
-#define B0WAT_13 0x0000D000 /* B0 Write Access Time = 13 cycles */
-#define B0WAT_14 0x0000E000 /* B0 Write Access Time = 14 cycles */
-#define B0WAT_15 0x0000F000 /* B0 Write Access Time = 15 cycles */
-
-#define B1RDYEN 0x00010000 /* Bank 1 (B1) RDY Enable */
-#define B1RDYPOL 0x00020000 /* B1 RDY Active High */
-#define B1TT_1 0x00040000 /* B1 Transition Time (Read to Write) = 1 cycle */
-#define B1TT_2 0x00080000 /* B1 Transition Time (Read to Write) = 2 cycles */
-#define B1TT_3 0x000C0000 /* B1 Transition Time (Read to Write) = 3 cycles */
-#define B1TT_4 0x00000000 /* B1 Transition Time (Read to Write) = 4 cycles */
-#define B1ST_1 0x00100000 /* B1 Setup Time (AOE to Read/Write) = 1 cycle */
-#define B1ST_2 0x00200000 /* B1 Setup Time (AOE to Read/Write) = 2 cycles */
-#define B1ST_3 0x00300000 /* B1 Setup Time (AOE to Read/Write) = 3 cycles */
-#define B1ST_4 0x00000000 /* B1 Setup Time (AOE to Read/Write) = 4 cycles */
-#define B1HT_1 0x00400000 /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle */
-#define B1HT_2 0x00800000 /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles */
-#define B1HT_3 0x00C00000 /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles */
-#define B1HT_0 0x00000000 /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles */
-#define B1RAT_1 0x01000000 /* B1 Read Access Time = 1 cycle */
-#define B1RAT_2 0x02000000 /* B1 Read Access Time = 2 cycles */
-#define B1RAT_3 0x03000000 /* B1 Read Access Time = 3 cycles */
-#define B1RAT_4 0x04000000 /* B1 Read Access Time = 4 cycles */
-#define B1RAT_5 0x05000000 /* B1 Read Access Time = 5 cycles */
-#define B1RAT_6 0x06000000 /* B1 Read Access Time = 6 cycles */
-#define B1RAT_7 0x07000000 /* B1 Read Access Time = 7 cycles */
-#define B1RAT_8 0x08000000 /* B1 Read Access Time = 8 cycles */
-#define B1RAT_9 0x09000000 /* B1 Read Access Time = 9 cycles */
-#define B1RAT_10 0x0A000000 /* B1 Read Access Time = 10 cycles */
-#define B1RAT_11 0x0B000000 /* B1 Read Access Time = 11 cycles */
-#define B1RAT_12 0x0C000000 /* B1 Read Access Time = 12 cycles */
-#define B1RAT_13 0x0D000000 /* B1 Read Access Time = 13 cycles */
-#define B1RAT_14 0x0E000000 /* B1 Read Access Time = 14 cycles */
-#define B1RAT_15 0x0F000000 /* B1 Read Access Time = 15 cycles */
-#define B1WAT_1 0x10000000 /* B1 Write Access Time = 1 cycle */
-#define B1WAT_2 0x20000000 /* B1 Write Access Time = 2 cycles */
-#define B1WAT_3 0x30000000 /* B1 Write Access Time = 3 cycles */
-#define B1WAT_4 0x40000000 /* B1 Write Access Time = 4 cycles */
-#define B1WAT_5 0x50000000 /* B1 Write Access Time = 5 cycles */
-#define B1WAT_6 0x60000000 /* B1 Write Access Time = 6 cycles */
-#define B1WAT_7 0x70000000 /* B1 Write Access Time = 7 cycles */
-#define B1WAT_8 0x80000000 /* B1 Write Access Time = 8 cycles */
-#define B1WAT_9 0x90000000 /* B1 Write Access Time = 9 cycles */
-#define B1WAT_10 0xA0000000 /* B1 Write Access Time = 10 cycles */
-#define B1WAT_11 0xB0000000 /* B1 Write Access Time = 11 cycles */
-#define B1WAT_12 0xC0000000 /* B1 Write Access Time = 12 cycles */
-#define B1WAT_13 0xD0000000 /* B1 Write Access Time = 13 cycles */
-#define B1WAT_14 0xE0000000 /* B1 Write Access Time = 14 cycles */
-#define B1WAT_15 0xF0000000 /* B1 Write Access Time = 15 cycles */
-
-/* EBIU_AMBCTL1 Masks */
-#define B2RDYEN 0x00000001 /* Bank 2 (B2) RDY Enable */
-#define B2RDYPOL 0x00000002 /* B2 RDY Active High */
-#define B2TT_1 0x00000004 /* B2 Transition Time (Read to Write) = 1 cycle */
-#define B2TT_2 0x00000008 /* B2 Transition Time (Read to Write) = 2 cycles */
-#define B2TT_3 0x0000000C /* B2 Transition Time (Read to Write) = 3 cycles */
-#define B2TT_4 0x00000000 /* B2 Transition Time (Read to Write) = 4 cycles */
-#define B2ST_1 0x00000010 /* B2 Setup Time (AOE to Read/Write) = 1 cycle */
-#define B2ST_2 0x00000020 /* B2 Setup Time (AOE to Read/Write) = 2 cycles */
-#define B2ST_3 0x00000030 /* B2 Setup Time (AOE to Read/Write) = 3 cycles */
-#define B2ST_4 0x00000000 /* B2 Setup Time (AOE to Read/Write) = 4 cycles */
-#define B2HT_1 0x00000040 /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle */
-#define B2HT_2 0x00000080 /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles */
-#define B2HT_3 0x000000C0 /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles */
-#define B2HT_0 0x00000000 /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles */
-#define B2RAT_1 0x00000100 /* B2 Read Access Time = 1 cycle */
-#define B2RAT_2 0x00000200 /* B2 Read Access Time = 2 cycles */
-#define B2RAT_3 0x00000300 /* B2 Read Access Time = 3 cycles */
-#define B2RAT_4 0x00000400 /* B2 Read Access Time = 4 cycles */
-#define B2RAT_5 0x00000500 /* B2 Read Access Time = 5 cycles */
-#define B2RAT_6 0x00000600 /* B2 Read Access Time = 6 cycles */
-#define B2RAT_7 0x00000700 /* B2 Read Access Time = 7 cycles */
-#define B2RAT_8 0x00000800 /* B2 Read Access Time = 8 cycles */
-#define B2RAT_9 0x00000900 /* B2 Read Access Time = 9 cycles */
-#define B2RAT_10 0x00000A00 /* B2 Read Access Time = 10 cycles */
-#define B2RAT_11 0x00000B00 /* B2 Read Access Time = 11 cycles */
-#define B2RAT_12 0x00000C00 /* B2 Read Access Time = 12 cycles */
-#define B2RAT_13 0x00000D00 /* B2 Read Access Time = 13 cycles */
-#define B2RAT_14 0x00000E00 /* B2 Read Access Time = 14 cycles */
-#define B2RAT_15 0x00000F00 /* B2 Read Access Time = 15 cycles */
-#define B2WAT_1 0x00001000 /* B2 Write Access Time = 1 cycle */
-#define B2WAT_2 0x00002000 /* B2 Write Access Time = 2 cycles */
-#define B2WAT_3 0x00003000 /* B2 Write Access Time = 3 cycles */
-#define B2WAT_4 0x00004000 /* B2 Write Access Time = 4 cycles */
-#define B2WAT_5 0x00005000 /* B2 Write Access Time = 5 cycles */
-#define B2WAT_6 0x00006000 /* B2 Write Access Time = 6 cycles */
-#define B2WAT_7 0x00007000 /* B2 Write Access Time = 7 cycles */
-#define B2WAT_8 0x00008000 /* B2 Write Access Time = 8 cycles */
-#define B2WAT_9 0x00009000 /* B2 Write Access Time = 9 cycles */
-#define B2WAT_10 0x0000A000 /* B2 Write Access Time = 10 cycles */
-#define B2WAT_11 0x0000B000 /* B2 Write Access Time = 11 cycles */
-#define B2WAT_12 0x0000C000 /* B2 Write Access Time = 12 cycles */
-#define B2WAT_13 0x0000D000 /* B2 Write Access Time = 13 cycles */
-#define B2WAT_14 0x0000E000 /* B2 Write Access Time = 14 cycles */
-#define B2WAT_15 0x0000F000 /* B2 Write Access Time = 15 cycles */
-
-#define B3RDYEN 0x00010000 /* Bank 3 (B3) RDY Enable */
-#define B3RDYPOL 0x00020000 /* B3 RDY Active High */
-#define B3TT_1 0x00040000 /* B3 Transition Time (Read to Write) = 1 cycle */
-#define B3TT_2 0x00080000 /* B3 Transition Time (Read to Write) = 2 cycles */
-#define B3TT_3 0x000C0000 /* B3 Transition Time (Read to Write) = 3 cycles */
-#define B3TT_4 0x00000000 /* B3 Transition Time (Read to Write) = 4 cycles */
-#define B3ST_1 0x00100000 /* B3 Setup Time (AOE to Read/Write) = 1 cycle */
-#define B3ST_2 0x00200000 /* B3 Setup Time (AOE to Read/Write) = 2 cycles */
-#define B3ST_3 0x00300000 /* B3 Setup Time (AOE to Read/Write) = 3 cycles */
-#define B3ST_4 0x00000000 /* B3 Setup Time (AOE to Read/Write) = 4 cycles */
-#define B3HT_1 0x00400000 /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle */
-#define B3HT_2 0x00800000 /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles */
-#define B3HT_3 0x00C00000 /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles */
-#define B3HT_0 0x00000000 /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles */
-#define B3RAT_1 0x01000000 /* B3 Read Access Time = 1 cycle */
-#define B3RAT_2 0x02000000 /* B3 Read Access Time = 2 cycles */
-#define B3RAT_3 0x03000000 /* B3 Read Access Time = 3 cycles */
-#define B3RAT_4 0x04000000 /* B3 Read Access Time = 4 cycles */
-#define B3RAT_5 0x05000000 /* B3 Read Access Time = 5 cycles */
-#define B3RAT_6 0x06000000 /* B3 Read Access Time = 6 cycles */
-#define B3RAT_7 0x07000000 /* B3 Read Access Time = 7 cycles */
-#define B3RAT_8 0x08000000 /* B3 Read Access Time = 8 cycles */
-#define B3RAT_9 0x09000000 /* B3 Read Access Time = 9 cycles */
-#define B3RAT_10 0x0A000000 /* B3 Read Access Time = 10 cycles */
-#define B3RAT_11 0x0B000000 /* B3 Read Access Time = 11 cycles */
-#define B3RAT_12 0x0C000000 /* B3 Read Access Time = 12 cycles */
-#define B3RAT_13 0x0D000000 /* B3 Read Access Time = 13 cycles */
-#define B3RAT_14 0x0E000000 /* B3 Read Access Time = 14 cycles */
-#define B3RAT_15 0x0F000000 /* B3 Read Access Time = 15 cycles */
-#define B3WAT_1 0x10000000 /* B3 Write Access Time = 1 cycle */
-#define B3WAT_2 0x20000000 /* B3 Write Access Time = 2 cycles */
-#define B3WAT_3 0x30000000 /* B3 Write Access Time = 3 cycles */
-#define B3WAT_4 0x40000000 /* B3 Write Access Time = 4 cycles */
-#define B3WAT_5 0x50000000 /* B3 Write Access Time = 5 cycles */
-#define B3WAT_6 0x60000000 /* B3 Write Access Time = 6 cycles */
-#define B3WAT_7 0x70000000 /* B3 Write Access Time = 7 cycles */
-#define B3WAT_8 0x80000000 /* B3 Write Access Time = 8 cycles */
-#define B3WAT_9 0x90000000 /* B3 Write Access Time = 9 cycles */
-#define B3WAT_10 0xA0000000 /* B3 Write Access Time = 10 cycles */
-#define B3WAT_11 0xB0000000 /* B3 Write Access Time = 11 cycles */
-#define B3WAT_12 0xC0000000 /* B3 Write Access Time = 12 cycles */
-#define B3WAT_13 0xD0000000 /* B3 Write Access Time = 13 cycles */
-#define B3WAT_14 0xE0000000 /* B3 Write Access Time = 14 cycles */
-#define B3WAT_15 0xF0000000 /* B3 Write Access Time = 15 cycles */
-
-/* ********************** SDRAM CONTROLLER MASKS **********************************************/
-/* EBIU_SDGCTL Masks */
-#define SCTLE 0x00000001 /* Enable SDRAM Signals */
-#define CL_2 0x00000008 /* SDRAM CAS Latency = 2 cycles */
-#define CL_3 0x0000000C /* SDRAM CAS Latency = 3 cycles */
-#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
-#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
-#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
-#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
-#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
-#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
-#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
-#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
-#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
-#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
-#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
-#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
-#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
-#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
-#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
-#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
-#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
-#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
-#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
-#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
-#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
-#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
-#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
-#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
-#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
-#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
-#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
-#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
-#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
-#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
-#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
-#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
-#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
-#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
-#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
-#define PUPSD 0x00200000 /* Power-Up Start Delay (15 SCLK Cycles Delay) */
-#define PSM 0x00400000 /* Power-Up Sequence (Mode Register Before/After* Refresh) */
-#define PSS 0x00800000 /* Enable Power-Up Sequence on Next SDRAM Access */
-#define SRFS 0x01000000 /* Enable SDRAM Self-Refresh Mode */
-#define EBUFE 0x02000000 /* Enable External Buffering Timing */
-#define FBBRW 0x04000000 /* Enable Fast Back-To-Back Read To Write */
-#define EMREN 0x10000000 /* Extended Mode Register Enable */
-#define TCSR 0x20000000 /* Temp-Compensated Self-Refresh Value (85/45* Deg C) */
-#define CDDBG 0x40000000 /* Tristate SDRAM Controls During Bus Grant */
-
-/* EBIU_SDBCTL Masks */
-#define EBE 0x0001 /* Enable SDRAM External Bank */
-#define EBSZ_16 0x0000 /* SDRAM External Bank Size = 16MB */
-#define EBSZ_32 0x0002 /* SDRAM External Bank Size = 32MB */
-#define EBSZ_64 0x0004 /* SDRAM External Bank Size = 64MB */
-#define EBSZ_128 0x0006 /* SDRAM External Bank Size = 128MB */
-#define EBSZ_256 0x0008 /* SDRAM External Bank Size = 256MB */
-#define EBSZ_512 0x000A /* SDRAM External Bank Size = 512MB */
-#define EBCAW_8 0x0000 /* SDRAM External Bank Column Address Width = 8 Bits */
-#define EBCAW_9 0x0010 /* SDRAM External Bank Column Address Width = 9 Bits */
-#define EBCAW_10 0x0020 /* SDRAM External Bank Column Address Width = 10 Bits */
-#define EBCAW_11 0x0030 /* SDRAM External Bank Column Address Width = 11 Bits */
-
-/* EBIU_SDSTAT Masks */
-#define SDCI 0x0001 /* SDRAM Controller Idle */
-#define SDSRA 0x0002 /* SDRAM Self-Refresh Active */
-#define SDPUA 0x0004 /* SDRAM Power-Up Active */
-#define SDRS 0x0008 /* SDRAM Will Power-Up On Next Access */
-#define SDEASE 0x0010 /* SDRAM EAB Sticky Error Status */
-#define BGSTAT 0x0020 /* Bus Grant Status */
-
-/* ************************** DMA CONTROLLER MASKS ********************************/
-
-/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
-#define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */
-#define PMAP 0xF000 /* Peripheral Mapped To This Channel */
-#define PMAP_PPI 0x0000 /* PPI Port DMA */
-#define PMAP_EMACRX 0x1000 /* Ethernet Receive DMA */
-#define PMAP_EMACTX 0x2000 /* Ethernet Transmit DMA */
-#define PMAP_SPORT0RX 0x3000 /* SPORT0 Receive DMA */
-#define PMAP_SPORT0TX 0x4000 /* SPORT0 Transmit DMA */
-#define PMAP_SPORT1RX 0x5000 /* SPORT1 Receive DMA */
-#define PMAP_SPORT1TX 0x6000 /* SPORT1 Transmit DMA */
-#define PMAP_SPI 0x7000 /* SPI Port DMA */
-#define PMAP_UART0RX 0x8000 /* UART0 Port Receive DMA */
-#define PMAP_UART0TX 0x9000 /* UART0 Port Transmit DMA */
-#define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */
-#define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */
-
-/* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
-/* PPI_CONTROL Masks */
-#define PORT_EN 0x0001 /* PPI Port Enable */
-#define PORT_DIR 0x0002 /* PPI Port Direction */
-#define XFR_TYPE 0x000C /* PPI Transfer Type */
-#define PORT_CFG 0x0030 /* PPI Port Configuration */
-#define FLD_SEL 0x0040 /* PPI Active Field Select */
-#define PACK_EN 0x0080 /* PPI Packing Mode */
-#define DMA32 0x0100 /* PPI 32-bit DMA Enable */
-#define SKIP_EN 0x0200 /* PPI Skip Element Enable */
-#define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */
-#define DLENGTH 0x3800 /* PPI Data Length */
-#define DLEN_8 0x0000 /* Data Length = 8 Bits */
-#define DLEN_10 0x0800 /* Data Length = 10 Bits */
-#define DLEN_11 0x1000 /* Data Length = 11 Bits */
-#define DLEN_12 0x1800 /* Data Length = 12 Bits */
-#define DLEN_13 0x2000 /* Data Length = 13 Bits */
-#define DLEN_14 0x2800 /* Data Length = 14 Bits */
-#define DLEN_15 0x3000 /* Data Length = 15 Bits */
-#define DLEN_16 0x3800 /* Data Length = 16 Bits */
-#define POLC 0x4000 /* PPI Clock Polarity */
-#define POLS 0x8000 /* PPI Frame Sync Polarity */
-
-/* PPI_STATUS Masks */
-#define FLD 0x0400 /* Field Indicator */
-#define FT_ERR 0x0800 /* Frame Track Error */
-#define OVR 0x1000 /* FIFO Overflow Error */
-#define UNDR 0x2000 /* FIFO Underrun Error */
-#define ERR_DET 0x4000 /* Error Detected Indicator */
-#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */
-
-
-/* ******************* PIN CONTROL REGISTER MASKS ************************/
-/* PORT_MUX Masks */
-#define PJSE 0x0001 /* Port J SPI/SPORT Enable */
-#define PJSE_SPORT 0x0000 /* Enable TFS0/DT0PRI */
-#define PJSE_SPI 0x0001 /* Enable SPI_SSEL3:2 */
-
-#define PJCE(x) (((x)&0x3)<<1) /* Port J CAN/SPI/SPORT Enable */
-#define PJCE_SPORT 0x0000 /* Enable DR0SEC/DT0SEC */
-#define PJCE_CAN 0x0002 /* Enable CAN RX/TX */
-#define PJCE_SPI 0x0004 /* Enable SPI_SSEL7 */
-
-#define PFDE 0x0008 /* Port F DMA Request Enable */
-#define PFDE_UART 0x0000 /* Enable UART0 RX/TX */
-#define PFDE_DMA 0x0008 /* Enable DMAR1:0 */
-
-#define PFTE 0x0010 /* Port F Timer Enable */
-#define PFTE_UART 0x0000 /* Enable UART1 RX/TX */
-#define PFTE_TIMER 0x0010 /* Enable TMR7:6 */
-
-#define PFS6E 0x0020 /* Port F SPI SSEL 6 Enable */
-#define PFS6E_TIMER 0x0000 /* Enable TMR5 */
-#define PFS6E_SPI 0x0020 /* Enable SPI_SSEL6 */
-
-#define PFS5E 0x0040 /* Port F SPI SSEL 5 Enable */
-#define PFS5E_TIMER 0x0000 /* Enable TMR4 */
-#define PFS5E_SPI 0x0040 /* Enable SPI_SSEL5 */
-
-#define PFS4E 0x0080 /* Port F SPI SSEL 4 Enable */
-#define PFS4E_TIMER 0x0000 /* Enable TMR3 */
-#define PFS4E_SPI 0x0080 /* Enable SPI_SSEL4 */
-
-#define PFFE 0x0100 /* Port F PPI Frame Sync Enable */
-#define PFFE_TIMER 0x0000 /* Enable TMR2 */
-#define PFFE_PPI 0x0100 /* Enable PPI FS3 */
-
-#define PGSE 0x0200 /* Port G SPORT1 Secondary Enable */
-#define PGSE_PPI 0x0000 /* Enable PPI D9:8 */
-#define PGSE_SPORT 0x0200 /* Enable DR1SEC/DT1SEC */
-
-#define PGRE 0x0400 /* Port G SPORT1 Receive Enable */
-#define PGRE_PPI 0x0000 /* Enable PPI D12:10 */
-#define PGRE_SPORT 0x0400 /* Enable DR1PRI/RFS1/RSCLK1 */
-
-#define PGTE 0x0800 /* Port G SPORT1 Transmit Enable */
-#define PGTE_PPI 0x0000 /* Enable PPI D15:13 */
-#define PGTE_SPORT 0x0800 /* Enable DT1PRI/TFS1/TSCLK1 */
-
-/* entry addresses of the user-callable Boot ROM functions */
-
-#define _BOOTROM_RESET 0xEF000000
-#define _BOOTROM_FINAL_INIT 0xEF000002
-#define _BOOTROM_DO_MEMORY_DMA 0xEF000006
-#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008
-#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A
-#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C
-#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010
-#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012
-#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define PGDE_UART PFDE_UART
-#define PGDE_DMA PFDE_DMA
-#define CKELOW SCKELOW
-#endif /* _DEF_BF534_H */
+++ /dev/null
-/*
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF537_H
-#define _DEF_BF537_H
-
-/* Include all MMR and bit defines common to BF534 */
-#include "defBF534.h"
-
-/************************************************************************************
-** Define EMAC Section Unique to BF536/BF537
-*************************************************************************************/
-
-/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
-#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */
-#define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */
-#define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */
-#define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */
-#define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */
-#define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */
-#define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */
-#define EMAC_FLC 0xFFC0301C /* Flow Control Register */
-#define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */
-#define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */
-#define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */
-#define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */
-#define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */
-#define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */
-#define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */
-#define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */
-#define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */
-#define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */
-#define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */
-
-#define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */
-#define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */
-#define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */
-#define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */
-#define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */
-#define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */
-#define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */
-#define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */
-
-#define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */
-#define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */
-#define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */
-#define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */
-#define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */
-
-#define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */
-#define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */
-#define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */
-#define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */
-#define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */
-#define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */
-#define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */
-#define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */
-#define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */
-#define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */
-#define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */
-#define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */
-#define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */
-#define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */
-#define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */
-#define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */
-#define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */
-#define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */
-#define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */
-#define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 <= x < 128 */
-#define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
-#define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
-#define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
-#define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */
-
-#define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */
-#define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */
-#define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */
-#define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */
-#define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */
-#define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */
-#define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */
-#define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */
-#define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */
-#define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */
-#define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */
-#define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */
-#define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */
-#define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */
-#define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */
-#define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */
-#define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */
-#define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 <= x < 128 */
-#define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
-#define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */
-#define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
-#define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */
-#define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */
-
-/* Listing for IEEE-Supported Count Registers */
-#define FramesReceivedOK EMAC_RXC_OK /* RX Frame Successful Count */
-#define FrameCheckSequenceErrors EMAC_RXC_FCS /* RX Frame FCS Failure Count */
-#define AlignmentErrors EMAC_RXC_ALIGN /* RX Alignment Error Count */
-#define OctetsReceivedOK EMAC_RXC_OCTET /* RX Octets Successfully Received Count */
-#define FramesLostDueToIntMACRcvError EMAC_RXC_DMAOVF /* Internal MAC Sublayer Error RX Frame Count */
-#define UnicastFramesReceivedOK EMAC_RXC_UNICST /* Unicast RX Frame Count */
-#define MulticastFramesReceivedOK EMAC_RXC_MULTI /* Multicast RX Frame Count */
-#define BroadcastFramesReceivedOK EMAC_RXC_BROAD /* Broadcast RX Frame Count */
-#define InRangeLengthErrors EMAC_RXC_LNERRI /* RX Frame In Range Error Count */
-#define OutOfRangeLengthField EMAC_RXC_LNERRO /* RX Frame Out Of Range Error Count */
-#define FrameTooLongErrors EMAC_RXC_LONG /* RX Frame Too Long Count */
-#define MACControlFramesReceived EMAC_RXC_MACCTL /* MAC Control RX Frame Count */
-#define UnsupportedOpcodesReceived EMAC_RXC_OPCODE /* Unsupported Op-Code RX Frame Count */
-#define PAUSEMACCtrlFramesReceived EMAC_RXC_PAUSE /* MAC Control Pause RX Frame Count */
-#define FramesReceivedAll EMAC_RXC_ALLFRM /* Overall RX Frame Count */
-#define OctetsReceivedAll EMAC_RXC_ALLOCT /* Overall RX Octet Count */
-#define TypedFramesReceived EMAC_RXC_TYPED /* Type/Length Consistent RX Frame Count */
-#define FramesLenLt64Received EMAC_RXC_SHORT /* RX Frame Fragment Count - Byte Count x < 64 */
-#define FramesLenEq64Received EMAC_RXC_EQ64 /* Good RX Frame Count - Byte Count x = 64 */
-#define FramesLen65_127Received EMAC_RXC_LT128 /* Good RX Frame Count - Byte Count 64 <= x < 128 */
-#define FramesLen128_255Received EMAC_RXC_LT256 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
-#define FramesLen256_511Received EMAC_RXC_LT512 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
-#define FramesLen512_1023Received EMAC_RXC_LT1024 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
-#define FramesLen1024_MaxReceived EMAC_RXC_GE1024 /* Good RX Frame Count - Byte Count x >= 1024 */
-
-#define FramesTransmittedOK EMAC_TXC_OK /* TX Frame Successful Count */
-#define SingleCollisionFrames EMAC_TXC_1COL /* TX Frames Successful After Single Collision Count */
-#define MultipleCollisionFrames EMAC_TXC_GT1COL /* TX Frames Successful After Multiple Collisions Count */
-#define OctetsTransmittedOK EMAC_TXC_OCTET /* TX Octets Successfully Received Count */
-#define FramesWithDeferredXmissions EMAC_TXC_DEFER /* TX Frame Delayed Due To Busy Count */
-#define LateCollisions EMAC_TXC_LATECL /* Late TX Collisions Count */
-#define FramesAbortedDueToXSColls EMAC_TXC_XS_COL /* TX Frame Failed Due To Excessive Collisions Count */
-#define FramesLostDueToIntMacXmitError EMAC_TXC_DMAUND /* Internal MAC Sublayer Error TX Frame Count */
-#define CarrierSenseErrors EMAC_TXC_CRSERR /* Carrier Sense Deasserted During TX Frame Count */
-#define UnicastFramesXmittedOK EMAC_TXC_UNICST /* Unicast TX Frame Count */
-#define MulticastFramesXmittedOK EMAC_TXC_MULTI /* Multicast TX Frame Count */
-#define BroadcastFramesXmittedOK EMAC_TXC_BROAD /* Broadcast TX Frame Count */
-#define FramesWithExcessiveDeferral EMAC_TXC_XS_DFR /* TX Frames With Excessive Deferral Count */
-#define MACControlFramesTransmitted EMAC_TXC_MACCTL /* MAC Control TX Frame Count */
-#define FramesTransmittedAll EMAC_TXC_ALLFRM /* Overall TX Frame Count */
-#define OctetsTransmittedAll EMAC_TXC_ALLOCT /* Overall TX Octet Count */
-#define FramesLenEq64Transmitted EMAC_TXC_EQ64 /* Good TX Frame Count - Byte Count x = 64 */
-#define FramesLen65_127Transmitted EMAC_TXC_LT128 /* Good TX Frame Count - Byte Count 64 <= x < 128 */
-#define FramesLen128_255Transmitted EMAC_TXC_LT256 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
-#define FramesLen256_511Transmitted EMAC_TXC_LT512 /* Good TX Frame Count - Byte Count 256 <= x < 512 */
-#define FramesLen512_1023Transmitted EMAC_TXC_LT1024 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
-#define FramesLen1024_MaxTransmitted EMAC_TXC_GE1024 /* Good TX Frame Count - Byte Count x >= 1024 */
-#define TxAbortedFrames EMAC_TXC_ABORT /* Total TX Frames Aborted Count */
-
-/***********************************************************************************
-** System MMR Register Bits And Macros
-**
-** Disclaimer: All macros are intended to make C and Assembly code more readable.
-** Use these macros carefully, as any that do left shifts for field
-** depositing will result in the lower order bits being destroyed. Any
-** macro that shifts left to properly position the bit-field should be
-** used as part of an OR to initialize a register and NOT as a dynamic
-** modifier UNLESS the lower order bits are saved and ORed back in when
-** the macro is used.
-*************************************************************************************/
-/************************ ETHERNET 10/100 CONTROLLER MASKS ************************/
-/* EMAC_OPMODE Masks */
-#define RE 0x00000001 /* Receiver Enable */
-#define ASTP 0x00000002 /* Enable Automatic Pad Stripping On RX Frames */
-#define HU 0x00000010 /* Hash Filter Unicast Address */
-#define HM 0x00000020 /* Hash Filter Multicast Address */
-#define PAM 0x00000040 /* Pass-All-Multicast Mode Enable */
-#define PR 0x00000080 /* Promiscuous Mode Enable */
-#define IFE 0x00000100 /* Inverse Filtering Enable */
-#define DBF 0x00000200 /* Disable Broadcast Frame Reception */
-#define PBF 0x00000400 /* Pass Bad Frames Enable */
-#define PSF 0x00000800 /* Pass Short Frames Enable */
-#define RAF 0x00001000 /* Receive-All Mode */
-#define TE 0x00010000 /* Transmitter Enable */
-#define DTXPAD 0x00020000 /* Disable Automatic TX Padding */
-#define DTXCRC 0x00040000 /* Disable Automatic TX CRC Generation */
-#define DC 0x00080000 /* Deferral Check */
-#define BOLMT 0x00300000 /* Back-Off Limit */
-#define BOLMT_10 0x00000000 /* 10-bit range */
-#define BOLMT_8 0x00100000 /* 8-bit range */
-#define BOLMT_4 0x00200000 /* 4-bit range */
-#define BOLMT_1 0x00300000 /* 1-bit range */
-#define DRTY 0x00400000 /* Disable TX Retry On Collision */
-#define LCTRE 0x00800000 /* Enable TX Retry On Late Collision */
-#define RMII 0x01000000 /* RMII/MII* Mode */
-#define RMII_10 0x02000000 /* Speed Select for RMII Port (10MBit/100MBit*) */
-#define FDMODE 0x04000000 /* Duplex Mode Enable (Full/Half*) */
-#define LB 0x08000000 /* Internal Loopback Enable */
-#define DRO 0x10000000 /* Disable Receive Own Frames (Half-Duplex Mode) */
-
-/* EMAC_STAADD Masks */
-#define STABUSY 0x00000001 /* Initiate Station Mgt Reg Access / STA Busy Stat */
-#define STAOP 0x00000002 /* Station Management Operation Code (Write/Read*) */
-#define STADISPRE 0x00000004 /* Disable Preamble Generation */
-#define STAIE 0x00000008 /* Station Mgt. Transfer Done Interrupt Enable */
-#define REGAD 0x000007C0 /* STA Register Address */
-#define PHYAD 0x0000F800 /* PHY Device Address */
-
-#define SET_REGAD(x) (((x)&0x1F)<< 6 ) /* Set STA Register Address */
-#define SET_PHYAD(x) (((x)&0x1F)<< 11 ) /* Set PHY Device Address */
-
-/* EMAC_STADAT Mask */
-#define STADATA 0x0000FFFF /* Station Management Data */
-
-/* EMAC_FLC Masks */
-#define FLCBUSY 0x00000001 /* Send Flow Ctrl Frame / Flow Ctrl Busy Status */
-#define FLCE 0x00000002 /* Flow Control Enable */
-#define PCF 0x00000004 /* Pass Control Frames */
-#define BKPRSEN 0x00000008 /* Enable Backpressure */
-#define FLCPAUSE 0xFFFF0000 /* Pause Time */
-
-#define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time */
-
-/* EMAC_WKUP_CTL Masks */
-#define CAPWKFRM 0x00000001 /* Capture Wake-Up Frames */
-#define MPKE 0x00000002 /* Magic Packet Enable */
-#define RWKE 0x00000004 /* Remote Wake-Up Frame Enable */
-#define GUWKE 0x00000008 /* Global Unicast Wake Enable */
-#define MPKS 0x00000020 /* Magic Packet Received Status */
-#define RWKS 0x00000F00 /* Wake-Up Frame Received Status, Filters 3:0 */
-
-/* EMAC_WKUP_FFCMD Masks */
-#define WF0_E 0x00000001 /* Enable Wake-Up Filter 0 */
-#define WF0_T 0x00000008 /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*) */
-#define WF1_E 0x00000100 /* Enable Wake-Up Filter 1 */
-#define WF1_T 0x00000800 /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*) */
-#define WF2_E 0x00010000 /* Enable Wake-Up Filter 2 */
-#define WF2_T 0x00080000 /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*) */
-#define WF3_E 0x01000000 /* Enable Wake-Up Filter 3 */
-#define WF3_T 0x08000000 /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*) */
-
-/* EMAC_WKUP_FFOFF Masks */
-#define WF0_OFF 0x000000FF /* Wake-Up Filter 0 Pattern Offset */
-#define WF1_OFF 0x0000FF00 /* Wake-Up Filter 1 Pattern Offset */
-#define WF2_OFF 0x00FF0000 /* Wake-Up Filter 2 Pattern Offset */
-#define WF3_OFF 0xFF000000 /* Wake-Up Filter 3 Pattern Offset */
-
-#define SET_WF0_OFF(x) (((x)&0xFF)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */
-#define SET_WF1_OFF(x) (((x)&0xFF)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */
-#define SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */
-#define SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */
-/* Set ALL Offsets */
-#define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3)))
-
-/* EMAC_WKUP_FFCRC0 Masks */
-#define WF0_CRC 0x0000FFFF /* Wake-Up Filter 0 Pattern CRC */
-#define WF1_CRC 0xFFFF0000 /* Wake-Up Filter 1 Pattern CRC */
-
-#define SET_WF0_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 0 Target CRC */
-#define SET_WF1_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 1 Target CRC */
-
-/* EMAC_WKUP_FFCRC1 Masks */
-#define WF2_CRC 0x0000FFFF /* Wake-Up Filter 2 Pattern CRC */
-#define WF3_CRC 0xFFFF0000 /* Wake-Up Filter 3 Pattern CRC */
-
-#define SET_WF2_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 2 Target CRC */
-#define SET_WF3_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 3 Target CRC */
-
-/* EMAC_SYSCTL Masks */
-#define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */
-#define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */
-#define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */
-#define TXDWA 0x00000010 /* Transmit Frame DMA Word Alignment (Odd/Even*) */
-#define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */
-
-#define SET_MDCDIV(x) (((x)&0x3F)<< 8) /* Set MDC Clock Divisor */
-
-/* EMAC_SYSTAT Masks */
-#define PHYINT 0x00000001 /* PHY_INT Interrupt Status */
-#define MMCINT 0x00000002 /* MMC Counter Interrupt Status */
-#define RXFSINT 0x00000004 /* RX Frame-Status Interrupt Status */
-#define TXFSINT 0x00000008 /* TX Frame-Status Interrupt Status */
-#define WAKEDET 0x00000010 /* Wake-Up Detected Status */
-#define RXDMAERR 0x00000020 /* RX DMA Direction Error Status */
-#define TXDMAERR 0x00000040 /* TX DMA Direction Error Status */
-#define STMDONE 0x00000080 /* Station Mgt. Transfer Done Interrupt Status */
-
-/* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */
-#define RX_FRLEN 0x000007FF /* Frame Length In Bytes */
-#define RX_COMP 0x00001000 /* RX Frame Complete */
-#define RX_OK 0x00002000 /* RX Frame Received With No Errors */
-#define RX_LONG 0x00004000 /* RX Frame Too Long Error */
-#define RX_ALIGN 0x00008000 /* RX Frame Alignment Error */
-#define RX_CRC 0x00010000 /* RX Frame CRC Error */
-#define RX_LEN 0x00020000 /* RX Frame Length Error */
-#define RX_FRAG 0x00040000 /* RX Frame Fragment Error */
-#define RX_ADDR 0x00080000 /* RX Frame Address Filter Failed Error */
-#define RX_DMAO 0x00100000 /* RX Frame DMA Overrun Error */
-#define RX_PHY 0x00200000 /* RX Frame PHY Error */
-#define RX_LATE 0x00400000 /* RX Frame Late Collision Error */
-#define RX_RANGE 0x00800000 /* RX Frame Length Field Out of Range Error */
-#define RX_MULTI 0x01000000 /* RX Multicast Frame Indicator */
-#define RX_BROAD 0x02000000 /* RX Broadcast Frame Indicator */
-#define RX_CTL 0x04000000 /* RX Control Frame Indicator */
-#define RX_UCTL 0x08000000 /* Unsupported RX Control Frame Indicator */
-#define RX_TYPE 0x10000000 /* RX Typed Frame Indicator */
-#define RX_VLAN1 0x20000000 /* RX VLAN1 Frame Indicator */
-#define RX_VLAN2 0x40000000 /* RX VLAN2 Frame Indicator */
-#define RX_ACCEPT 0x80000000 /* RX Frame Accepted Indicator */
-
-/* EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks */
-#define TX_COMP 0x00000001 /* TX Frame Complete */
-#define TX_OK 0x00000002 /* TX Frame Sent With No Errors */
-#define TX_ECOLL 0x00000004 /* TX Frame Excessive Collision Error */
-#define TX_LATE 0x00000008 /* TX Frame Late Collision Error */
-#define TX_DMAU 0x00000010 /* TX Frame DMA Underrun Error (STAT) */
-#define TX_MACE 0x00000010 /* Internal MAC Error Detected (STKY and IRQE) */
-#define TX_EDEFER 0x00000020 /* TX Frame Excessive Deferral Error */
-#define TX_BROAD 0x00000040 /* TX Broadcast Frame Indicator */
-#define TX_MULTI 0x00000080 /* TX Multicast Frame Indicator */
-#define TX_CCNT 0x00000F00 /* TX Frame Collision Count */
-#define TX_DEFER 0x00001000 /* TX Frame Deferred Indicator */
-#define TX_CRS 0x00002000 /* TX Frame Carrier Sense Not Asserted Error */
-#define TX_LOSS 0x00004000 /* TX Frame Carrier Lost During TX Error */
-#define TX_RETRY 0x00008000 /* TX Frame Successful After Retry */
-#define TX_FRLEN 0x07FF0000 /* TX Frame Length (Bytes) */
-
-/* EMAC_MMC_CTL Masks */
-#define RSTC 0x00000001 /* Reset All Counters */
-#define CROLL 0x00000002 /* Counter Roll-Over Enable */
-#define CCOR 0x00000004 /* Counter Clear-On-Read Mode Enable */
-#define MMCE 0x00000008 /* Enable MMC Counter Operation */
-
-/* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */
-#define RX_OK_CNT 0x00000001 /* RX Frames Received With No Errors */
-#define RX_FCS_CNT 0x00000002 /* RX Frames W/Frame Check Sequence Errors */
-#define RX_ALIGN_CNT 0x00000004 /* RX Frames With Alignment Errors */
-#define RX_OCTET_CNT 0x00000008 /* RX Octets Received OK */
-#define RX_LOST_CNT 0x00000010 /* RX Frames Lost Due To Internal MAC RX Error */
-#define RX_UNI_CNT 0x00000020 /* Unicast RX Frames Received OK */
-#define RX_MULTI_CNT 0x00000040 /* Multicast RX Frames Received OK */
-#define RX_BROAD_CNT 0x00000080 /* Broadcast RX Frames Received OK */
-#define RX_IRL_CNT 0x00000100 /* RX Frames With In-Range Length Errors */
-#define RX_ORL_CNT 0x00000200 /* RX Frames With Out-Of-Range Length Errors */
-#define RX_LONG_CNT 0x00000400 /* RX Frames With Frame Too Long Errors */
-#define RX_MACCTL_CNT 0x00000800 /* MAC Control RX Frames Received */
-#define RX_OPCODE_CTL 0x00001000 /* Unsupported Op-Code RX Frames Received */
-#define RX_PAUSE_CNT 0x00002000 /* PAUSEMAC Control RX Frames Received */
-#define RX_ALLF_CNT 0x00004000 /* All RX Frames Received */
-#define RX_ALLO_CNT 0x00008000 /* All RX Octets Received */
-#define RX_TYPED_CNT 0x00010000 /* Typed RX Frames Received */
-#define RX_SHORT_CNT 0x00020000 /* RX Frame Fragments (< 64 Bytes) Received */
-#define RX_EQ64_CNT 0x00040000 /* 64-Byte RX Frames Received */
-#define RX_LT128_CNT 0x00080000 /* 65-127-Byte RX Frames Received */
-#define RX_LT256_CNT 0x00100000 /* 128-255-Byte RX Frames Received */
-#define RX_LT512_CNT 0x00200000 /* 256-511-Byte RX Frames Received */
-#define RX_LT1024_CNT 0x00400000 /* 512-1023-Byte RX Frames Received */
-#define RX_GE1024_CNT 0x00800000 /* 1024-Max-Byte RX Frames Received */
-
-/* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */
-#define TX_OK_CNT 0x00000001 /* TX Frames Sent OK */
-#define TX_SCOLL_CNT 0x00000002 /* TX Frames With Single Collisions */
-#define TX_MCOLL_CNT 0x00000004 /* TX Frames With Multiple Collisions */
-#define TX_OCTET_CNT 0x00000008 /* TX Octets Sent OK */
-#define TX_DEFER_CNT 0x00000010 /* TX Frames With Deferred Transmission */
-#define TX_LATE_CNT 0x00000020 /* TX Frames With Late Collisions */
-#define TX_ABORTC_CNT 0x00000040 /* TX Frames Aborted Due To Excess Collisions */
-#define TX_LOST_CNT 0x00000080 /* TX Frames Lost Due To Internal MAC TX Error */
-#define TX_CRS_CNT 0x00000100 /* TX Frames With Carrier Sense Errors */
-#define TX_UNI_CNT 0x00000200 /* Unicast TX Frames Sent */
-#define TX_MULTI_CNT 0x00000400 /* Multicast TX Frames Sent */
-#define TX_BROAD_CNT 0x00000800 /* Broadcast TX Frames Sent */
-#define TX_EXDEF_CTL 0x00001000 /* TX Frames With Excessive Deferral */
-#define TX_MACCTL_CNT 0x00002000 /* MAC Control TX Frames Sent */
-#define TX_ALLF_CNT 0x00004000 /* All TX Frames Sent */
-#define TX_ALLO_CNT 0x00008000 /* All TX Octets Sent */
-#define TX_EQ64_CNT 0x00010000 /* 64-Byte TX Frames Sent */
-#define TX_LT128_CNT 0x00020000 /* 65-127-Byte TX Frames Sent */
-#define TX_LT256_CNT 0x00040000 /* 128-255-Byte TX Frames Sent */
-#define TX_LT512_CNT 0x00080000 /* 256-511-Byte TX Frames Sent */
-#define TX_LT1024_CNT 0x00100000 /* 512-1023-Byte TX Frames Sent */
-#define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */
-#define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */
-
-#endif /* _DEF_BF537_H */
+++ /dev/null
-/* mach/dma.h - arch-specific DMA defines
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_DMA_H_
-#define _MACH_DMA_H_
-
-#define MAX_DMA_CHANNELS 16
-
-#define CH_PPI 0
-#define CH_EMAC_RX 1
-#define CH_EMAC_TX 2
-#define CH_SPORT0_RX 3
-#define CH_SPORT0_TX 4
-#define CH_SPORT1_RX 5
-#define CH_SPORT1_TX 6
-#define CH_SPI 7
-#define CH_UART0_RX 8
-#define CH_UART0_TX 9
-#define CH_UART1_RX 10
-#define CH_UART1_TX 11
-
-#define CH_MEM_STREAM0_DEST 12 /* TX */
-#define CH_MEM_STREAM0_SRC 13 /* RX */
-#define CH_MEM_STREAM1_DEST 14 /* TX */
-#define CH_MEM_STREAM1_SRC 15 /* RX */
-
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2008 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-
-#ifndef _MACH_GPIO_H_
-#define _MACH_GPIO_H_
-
-#define MAX_BLACKFIN_GPIOS 48
-
-#define GPIO_PF0 0
-#define GPIO_PF1 1
-#define GPIO_PF2 2
-#define GPIO_PF3 3
-#define GPIO_PF4 4
-#define GPIO_PF5 5
-#define GPIO_PF6 6
-#define GPIO_PF7 7
-#define GPIO_PF8 8
-#define GPIO_PF9 9
-#define GPIO_PF10 10
-#define GPIO_PF11 11
-#define GPIO_PF12 12
-#define GPIO_PF13 13
-#define GPIO_PF14 14
-#define GPIO_PF15 15
-#define GPIO_PG0 16
-#define GPIO_PG1 17
-#define GPIO_PG2 18
-#define GPIO_PG3 19
-#define GPIO_PG4 20
-#define GPIO_PG5 21
-#define GPIO_PG6 22
-#define GPIO_PG7 23
-#define GPIO_PG8 24
-#define GPIO_PG9 25
-#define GPIO_PG10 26
-#define GPIO_PG11 27
-#define GPIO_PG12 28
-#define GPIO_PG13 29
-#define GPIO_PG14 30
-#define GPIO_PG15 31
-#define GPIO_PH0 32
-#define GPIO_PH1 33
-#define GPIO_PH2 34
-#define GPIO_PH3 35
-#define GPIO_PH4 36
-#define GPIO_PH5 37
-#define GPIO_PH6 38
-#define GPIO_PH7 39
-#define GPIO_PH8 40
-#define GPIO_PH9 41
-#define GPIO_PH10 42
-#define GPIO_PH11 43
-#define GPIO_PH12 44
-#define GPIO_PH13 45
-#define GPIO_PH14 46
-#define GPIO_PH15 47
-
-#define PORT_F GPIO_PF0
-#define PORT_G GPIO_PG0
-#define PORT_H GPIO_PH0
-
-#include <mach-common/ports-f.h>
-#include <mach-common/ports-g.h>
-#include <mach-common/ports-h.h>
-
-#endif /* _MACH_GPIO_H_ */
+++ /dev/null
-/*
- * Copyright 2005-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _BF537_IRQ_H_
-#define _BF537_IRQ_H_
-
-#include <mach-common/irq.h>
-
-#define NR_PERI_INTS 32
-
-#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
-#define IRQ_DMA_ERROR BFIN_IRQ(1) /* DMA Error (general) */
-#define IRQ_GENERIC_ERROR BFIN_IRQ(2) /* GENERIC Error Interrupt */
-#define IRQ_RTC BFIN_IRQ(3) /* RTC Interrupt */
-#define IRQ_PPI BFIN_IRQ(4) /* DMA0 Interrupt (PPI) */
-#define IRQ_SPORT0_RX BFIN_IRQ(5) /* DMA3 Interrupt (SPORT0 RX) */
-#define IRQ_SPORT0_TX BFIN_IRQ(6) /* DMA4 Interrupt (SPORT0 TX) */
-#define IRQ_SPORT1_RX BFIN_IRQ(7) /* DMA5 Interrupt (SPORT1 RX) */
-#define IRQ_SPORT1_TX BFIN_IRQ(8) /* DMA6 Interrupt (SPORT1 TX) */
-#define IRQ_TWI BFIN_IRQ(9) /* TWI Interrupt */
-#define IRQ_SPI BFIN_IRQ(10) /* DMA7 Interrupt (SPI) */
-#define IRQ_UART0_RX BFIN_IRQ(11) /* DMA8 Interrupt (UART0 RX) */
-#define IRQ_UART0_TX BFIN_IRQ(12) /* DMA9 Interrupt (UART0 TX) */
-#define IRQ_UART1_RX BFIN_IRQ(13) /* DMA10 Interrupt (UART1 RX) */
-#define IRQ_UART1_TX BFIN_IRQ(14) /* DMA11 Interrupt (UART1 TX) */
-#define IRQ_CAN_RX BFIN_IRQ(15) /* CAN Receive Interrupt */
-#define IRQ_CAN_TX BFIN_IRQ(16) /* CAN Transmit Interrupt */
-#define IRQ_PH_INTA_MAC_RX BFIN_IRQ(17) /* Port H Interrupt A & DMA1 Interrupt (Ethernet RX) */
-#define IRQ_PH_INTB_MAC_TX BFIN_IRQ(18) /* Port H Interrupt B & DMA2 Interrupt (Ethernet TX) */
-#define IRQ_TIMER0 BFIN_IRQ(19) /* Timer 0 */
-#define IRQ_TIMER1 BFIN_IRQ(20) /* Timer 1 */
-#define IRQ_TIMER2 BFIN_IRQ(21) /* Timer 2 */
-#define IRQ_TIMER3 BFIN_IRQ(22) /* Timer 3 */
-#define IRQ_TIMER4 BFIN_IRQ(23) /* Timer 4 */
-#define IRQ_TIMER5 BFIN_IRQ(24) /* Timer 5 */
-#define IRQ_TIMER6 BFIN_IRQ(25) /* Timer 6 */
-#define IRQ_TIMER7 BFIN_IRQ(26) /* Timer 7 */
-#define IRQ_PF_INTA_PG_INTA BFIN_IRQ(27) /* Ports F&G Interrupt A */
-#define IRQ_PORTG_INTB BFIN_IRQ(28) /* Port G Interrupt B */
-#define IRQ_MEM_DMA0 BFIN_IRQ(29) /* (Memory DMA Stream 0) */
-#define IRQ_MEM_DMA1 BFIN_IRQ(30) /* (Memory DMA Stream 1) */
-#define IRQ_PF_INTB_WATCH BFIN_IRQ(31) /* Watchdog & Port F Interrupt B */
-
-#define SYS_IRQS 39
-
-#define IRQ_PPI_ERROR 42 /* PPI Error Interrupt */
-#define IRQ_CAN_ERROR 43 /* CAN Error Interrupt */
-#define IRQ_MAC_ERROR 44 /* MAC Status/Error Interrupt */
-#define IRQ_SPORT0_ERROR 45 /* SPORT0 Error Interrupt */
-#define IRQ_SPORT1_ERROR 46 /* SPORT1 Error Interrupt */
-#define IRQ_SPI_ERROR 47 /* SPI Error Interrupt */
-#define IRQ_UART0_ERROR 48 /* UART Error Interrupt */
-#define IRQ_UART1_ERROR 49 /* UART Error Interrupt */
-
-#define IRQ_PF0 50
-#define IRQ_PF1 51
-#define IRQ_PF2 52
-#define IRQ_PF3 53
-#define IRQ_PF4 54
-#define IRQ_PF5 55
-#define IRQ_PF6 56
-#define IRQ_PF7 57
-#define IRQ_PF8 58
-#define IRQ_PF9 59
-#define IRQ_PF10 60
-#define IRQ_PF11 61
-#define IRQ_PF12 62
-#define IRQ_PF13 63
-#define IRQ_PF14 64
-#define IRQ_PF15 65
-
-#define IRQ_PG0 66
-#define IRQ_PG1 67
-#define IRQ_PG2 68
-#define IRQ_PG3 69
-#define IRQ_PG4 70
-#define IRQ_PG5 71
-#define IRQ_PG6 72
-#define IRQ_PG7 73
-#define IRQ_PG8 74
-#define IRQ_PG9 75
-#define IRQ_PG10 76
-#define IRQ_PG11 77
-#define IRQ_PG12 78
-#define IRQ_PG13 79
-#define IRQ_PG14 80
-#define IRQ_PG15 81
-
-#define IRQ_PH0 82
-#define IRQ_PH1 83
-#define IRQ_PH2 84
-#define IRQ_PH3 85
-#define IRQ_PH4 86
-#define IRQ_PH5 87
-#define IRQ_PH6 88
-#define IRQ_PH7 89
-#define IRQ_PH8 90
-#define IRQ_PH9 91
-#define IRQ_PH10 92
-#define IRQ_PH11 93
-#define IRQ_PH12 94
-#define IRQ_PH13 95
-#define IRQ_PH14 96
-#define IRQ_PH15 97
-
-#define GPIO_IRQ_BASE IRQ_PF0
-
-#define IRQ_MAC_PHYINT 98 /* PHY_INT Interrupt */
-#define IRQ_MAC_MMCINT 99 /* MMC Counter Interrupt */
-#define IRQ_MAC_RXFSINT 100 /* RX Frame-Status Interrupt */
-#define IRQ_MAC_TXFSINT 101 /* TX Frame-Status Interrupt */
-#define IRQ_MAC_WAKEDET 102 /* Wake-Up Interrupt */
-#define IRQ_MAC_RXDMAERR 103 /* RX DMA Direction Error Interrupt */
-#define IRQ_MAC_TXDMAERR 104 /* TX DMA Direction Error Interrupt */
-#define IRQ_MAC_STMDONE 105 /* Station Mgt. Transfer Done Interrupt */
-
-#define IRQ_MAC_RX 106 /* DMA1 Interrupt (Ethernet RX) */
-#define IRQ_PORTH_INTA 107 /* Port H Interrupt A */
-
-#if 0 /* No Interrupt B support (yet) */
-#define IRQ_MAC_TX 108 /* DMA2 Interrupt (Ethernet TX) */
-#define IRQ_PORTH_INTB 109 /* Port H Interrupt B */
-#else
-#define IRQ_MAC_TX IRQ_PH_INTB_MAC_TX
-#endif
-
-#define IRQ_PORTF_INTA 110 /* Port F Interrupt A */
-#define IRQ_PORTG_INTA 111 /* Port G Interrupt A */
-
-#if 0 /* No Interrupt B support (yet) */
-#define IRQ_WATCH 112 /* Watchdog Timer */
-#define IRQ_PORTF_INTB 113 /* Port F Interrupt B */
-#else
-#define IRQ_WATCH IRQ_PF_INTB_WATCH
-#endif
-
-#define NR_MACH_IRQS (113 + 1)
-
-/* IAR0 BIT FIELDS */
-#define IRQ_PLL_WAKEUP_POS 0
-#define IRQ_DMA_ERROR_POS 4
-#define IRQ_ERROR_POS 8
-#define IRQ_RTC_POS 12
-#define IRQ_PPI_POS 16
-#define IRQ_SPORT0_RX_POS 20
-#define IRQ_SPORT0_TX_POS 24
-#define IRQ_SPORT1_RX_POS 28
-
-/* IAR1 BIT FIELDS */
-#define IRQ_SPORT1_TX_POS 0
-#define IRQ_TWI_POS 4
-#define IRQ_SPI_POS 8
-#define IRQ_UART0_RX_POS 12
-#define IRQ_UART0_TX_POS 16
-#define IRQ_UART1_RX_POS 20
-#define IRQ_UART1_TX_POS 24
-#define IRQ_CAN_RX_POS 28
-
-/* IAR2 BIT FIELDS */
-#define IRQ_CAN_TX_POS 0
-#define IRQ_MAC_RX_POS 4
-#define IRQ_MAC_TX_POS 8
-#define IRQ_TIMER0_POS 12
-#define IRQ_TIMER1_POS 16
-#define IRQ_TIMER2_POS 20
-#define IRQ_TIMER3_POS 24
-#define IRQ_TIMER4_POS 28
-
-/* IAR3 BIT FIELDS */
-#define IRQ_TIMER5_POS 0
-#define IRQ_TIMER6_POS 4
-#define IRQ_TIMER7_POS 8
-#define IRQ_PROG_INTA_POS 12
-#define IRQ_PORTG_INTB_POS 16
-#define IRQ_MEM_DMA0_POS 20
-#define IRQ_MEM_DMA1_POS 24
-#define IRQ_WATCH_POS 28
-
-#define init_mach_irq init_mach_irq
-
-#endif
+++ /dev/null
-/*
- * BF537 memory map
- *
- * Copyright 2004-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MACH_MEM_MAP_H__
-#define __BFIN_MACH_MEM_MAP_H__
-
-#ifndef __BFIN_MEM_MAP_H__
-# error "do not include mach/mem_map.h directly -- use asm/mem_map.h"
-#endif
-
-/* Async Memory Banks */
-#define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */
-#define ASYNC_BANK3_SIZE 0x00100000 /* 1M */
-#define ASYNC_BANK2_BASE 0x20200000 /* Async Bank 2 */
-#define ASYNC_BANK2_SIZE 0x00100000 /* 1M */
-#define ASYNC_BANK1_BASE 0x20100000 /* Async Bank 1 */
-#define ASYNC_BANK1_SIZE 0x00100000 /* 1M */
-#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
-#define ASYNC_BANK0_SIZE 0x00100000 /* 1M */
-
-/* Boot ROM Memory */
-
-#define BOOT_ROM_START 0xEF000000
-#define BOOT_ROM_LENGTH 0x800
-
-/* Level 1 Memory */
-
-/* Memory Map for ADSP-BF537 processors */
-
-#ifdef CONFIG_BFIN_ICACHE
-#define BFIN_ICACHESIZE (16*1024)
-#else
-#define BFIN_ICACHESIZE (0*1024)
-#endif
-
-
-#ifdef CONFIG_BF537
-#define L1_CODE_START 0xFFA00000
-#define L1_DATA_A_START 0xFF800000
-#define L1_DATA_B_START 0xFF900000
-
-#define L1_CODE_LENGTH 0xC000
-
-#ifdef CONFIG_BFIN_DCACHE
-
-#ifdef CONFIG_BFIN_DCACHE_BANKA
-#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE (16*1024)
-#define BFIN_DSUPBANKS 1
-#else
-#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
-#define BFIN_DCACHESIZE (32*1024)
-#define BFIN_DSUPBANKS 2
-#endif
-
-#else
-#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH 0x8000
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE (0*1024)
-#define BFIN_DSUPBANKS 0
-#endif /*CONFIG_BFIN_DCACHE*/
-
-#endif /*CONFIG_BF537*/
-
-/* Memory Map for ADSP-BF536 processors */
-
-#ifdef CONFIG_BF536
-#define L1_CODE_START 0xFFA00000
-#define L1_DATA_A_START 0xFF804000
-#define L1_DATA_B_START 0xFF904000
-
-#define L1_CODE_LENGTH 0xC000
-
-
-#ifdef CONFIG_BFIN_DCACHE
-
-#ifdef CONFIG_BFIN_DCACHE_BANKA
-#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
-#define L1_DATA_B_LENGTH 0x4000
-#define BFIN_DCACHESIZE (16*1024)
-#define BFIN_DSUPBANKS 1
-
-#else
-#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
-#define L1_DATA_B_LENGTH (0x4000 - 0x4000)
-#define BFIN_DCACHESIZE (32*1024)
-#define BFIN_DSUPBANKS 2
-#endif
-
-#else
-#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH 0x4000
-#define L1_DATA_B_LENGTH 0x4000
-#define BFIN_DCACHESIZE (0*1024)
-#define BFIN_DSUPBANKS 0
-#endif /*CONFIG_BFIN_DCACHE*/
-
-#endif
-
-/* Memory Map for ADSP-BF534 processors */
-
-#ifdef CONFIG_BF534
-#define L1_CODE_START 0xFFA00000
-#define L1_DATA_A_START 0xFF800000
-#define L1_DATA_B_START 0xFF900000
-
-#define L1_CODE_LENGTH 0xC000
-
-#ifdef CONFIG_BFIN_DCACHE
-
-#ifdef CONFIG_BFIN_DCACHE_BANKA
-#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE (16*1024)
-#define BFIN_DSUPBANKS 1
-
-#else
-#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
-#define BFIN_DCACHESIZE (32*1024)
-#define BFIN_DSUPBANKS 2
-#endif
-
-#else
-#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH 0x8000
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE (0*1024)
-#define BFIN_DSUPBANKS 0
-#endif /*CONFIG_BFIN_DCACHE*/
-
-#endif
-
-#endif
+++ /dev/null
-#include <mach-common/pll.h>
+++ /dev/null
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _MACH_PORTMUX_H_
-#define _MACH_PORTMUX_H_
-
-#define MAX_RESOURCES (MAX_BLACKFIN_GPIOS + GPIO_BANKSIZE) /* We additionally handle PORTJ */
-
-#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
-#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
-#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
-#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
-#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
-#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
-#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))
-#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
-#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
-#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
-#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
-#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
-#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
-#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
-#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
-#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
-#define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
-#define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
-#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
-#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
-#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
-#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
-#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
-#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
-#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
-#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
-#define P_TACLK0 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
-#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
-#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF10
-#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL1
-
-#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
-#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
-#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0))
-#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
-#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0))
-#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
-#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
-#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
-#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
-#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
-#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
-#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0))
-#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
-#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
-#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
-#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
-#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1))
-#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1))
-#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1))
-#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
-#define P_SPORT1_DRPRI (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
-#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1))
-#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1))
-#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
-
-#define P_MII0_ETxD0 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
-#define P_MII0_ETxD1 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
-#define P_MII0_ETxD2 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
-#define P_MII0_ETxD3 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0))
-#define P_MII0_ETxEN (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0))
-#define P_MII0_TxCLK (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0))
-#define P_MII0_PHYINT (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0))
-#define P_MII0_COL (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0))
-#define P_MII0_ERxD0 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(0))
-#define P_MII0_ERxD1 (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(0))
-#define P_MII0_ERxD2 (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(0))
-#define P_MII0_ERxD3 (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(0))
-#define P_MII0_ERxDV (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(0))
-#define P_MII0_ERxCLK (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(0))
-#define P_MII0_ERxER (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(0))
-#define P_MII0_CRS (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(0))
-#define P_RMII0_REF_CLK (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(1))
-#define P_RMII0_MDINT (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1))
-#define P_RMII0_CRS_DV (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(1))
-
-#define PORT_PJ0 (GPIO_PH15 + 1)
-#define PORT_PJ1 (GPIO_PH15 + 2)
-#define PORT_PJ2 (GPIO_PH15 + 3)
-#define PORT_PJ3 (GPIO_PH15 + 4)
-#define PORT_PJ4 (GPIO_PH15 + 5)
-#define PORT_PJ5 (GPIO_PH15 + 6)
-#define PORT_PJ6 (GPIO_PH15 + 7)
-#define PORT_PJ7 (GPIO_PH15 + 8)
-#define PORT_PJ8 (GPIO_PH15 + 9)
-#define PORT_PJ9 (GPIO_PH15 + 10)
-#define PORT_PJ10 (GPIO_PH15 + 11)
-#define PORT_PJ11 (GPIO_PH15 + 12)
-
-#define P_MDC (P_DEFINED | P_IDENT(PORT_PJ0) | P_FUNCT(0))
-#define P_MDIO (P_DEFINED | P_IDENT(PORT_PJ1) | P_FUNCT(0))
-#define P_TWI0_SCL (P_DEFINED | P_IDENT(PORT_PJ2) | P_FUNCT(0))
-#define P_TWI0_SDA (P_DEFINED | P_IDENT(PORT_PJ3) | P_FUNCT(0))
-#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(PORT_PJ4) | P_FUNCT(0))
-#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(0))
-#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(PORT_PJ6) | P_FUNCT(0))
-#define P_SPORT0_RFS (P_DEFINED | P_IDENT(PORT_PJ7) | P_FUNCT(0))
-#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(PORT_PJ8) | P_FUNCT(0))
-#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(PORT_PJ9) | P_FUNCT(0))
-#define P_SPORT0_TFS (P_DEFINED | P_IDENT(PORT_PJ10) | P_FUNCT(0))
-#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(PORT_PJ11) | P_FUNCT(0))
-#define P_CAN0_RX (P_DEFINED | P_IDENT(PORT_PJ4) | P_FUNCT(1))
-#define P_CAN0_TX (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(1))
-#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(PORT_PJ10) | P_FUNCT(1))
-#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(PORT_PJ11) | P_FUNCT(1))
-#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(2))
-
-#define P_MII0 {\
- P_MII0_ETxD0, \
- P_MII0_ETxD1, \
- P_MII0_ETxD2, \
- P_MII0_ETxD3, \
- P_MII0_ETxEN, \
- P_MII0_TxCLK, \
- P_MII0_PHYINT, \
- P_MII0_COL, \
- P_MII0_ERxD0, \
- P_MII0_ERxD1, \
- P_MII0_ERxD2, \
- P_MII0_ERxD3, \
- P_MII0_ERxDV, \
- P_MII0_ERxCLK, \
- P_MII0_ERxER, \
- P_MII0_CRS, \
- P_MDC, \
- P_MDIO, 0}
-
-#define P_RMII0 {\
- P_MII0_ETxD0, \
- P_MII0_ETxD1, \
- P_MII0_ETxEN, \
- P_MII0_ERxD0, \
- P_MII0_ERxD1, \
- P_MII0_ERxER, \
- P_RMII0_REF_CLK, \
- P_RMII0_MDINT, \
- P_RMII0_CRS_DV, \
- P_MDC, \
- P_MDIO, 0}
-
-#endif /* _MACH_PORTMUX_H_ */
+++ /dev/null
-/*
- * Copyright 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- *
- * Set up the interrupt priorities
- */
-
-#include <linux/module.h>
-#include <linux/irq.h>
-#include <asm/blackfin.h>
-
-#include <asm/irq_handler.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/bfin_sport.h>
-#include <asm/bfin_can.h>
-#include <asm/bfin_dma.h>
-#include <asm/dpmc.h>
-
-void __init program_IAR(void)
-{
- /* Program the IAR0 Register with the configured priority */
- bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) |
- ((CONFIG_IRQ_DMA_ERROR - 7) << IRQ_DMA_ERROR_POS) |
- ((CONFIG_IRQ_ERROR - 7) << IRQ_ERROR_POS) |
- ((CONFIG_IRQ_RTC - 7) << IRQ_RTC_POS) |
- ((CONFIG_IRQ_PPI - 7) << IRQ_PPI_POS) |
- ((CONFIG_IRQ_SPORT0_RX - 7) << IRQ_SPORT0_RX_POS) |
- ((CONFIG_IRQ_SPORT0_TX - 7) << IRQ_SPORT0_TX_POS) |
- ((CONFIG_IRQ_SPORT1_RX - 7) << IRQ_SPORT1_RX_POS));
-
- bfin_write_SIC_IAR1(((CONFIG_IRQ_SPORT1_TX - 7) << IRQ_SPORT1_TX_POS) |
- ((CONFIG_IRQ_TWI - 7) << IRQ_TWI_POS) |
- ((CONFIG_IRQ_SPI - 7) << IRQ_SPI_POS) |
- ((CONFIG_IRQ_UART0_RX - 7) << IRQ_UART0_RX_POS) |
- ((CONFIG_IRQ_UART0_TX - 7) << IRQ_UART0_TX_POS) |
- ((CONFIG_IRQ_UART1_RX - 7) << IRQ_UART1_RX_POS) |
- ((CONFIG_IRQ_UART1_TX - 7) << IRQ_UART1_TX_POS) |
- ((CONFIG_IRQ_CAN_RX - 7) << IRQ_CAN_RX_POS));
-
- bfin_write_SIC_IAR2(((CONFIG_IRQ_CAN_TX - 7) << IRQ_CAN_TX_POS) |
- ((CONFIG_IRQ_MAC_RX - 7) << IRQ_MAC_RX_POS) |
- ((CONFIG_IRQ_MAC_TX - 7) << IRQ_MAC_TX_POS) |
- ((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) |
- ((CONFIG_IRQ_TIMER1 - 7) << IRQ_TIMER1_POS) |
- ((CONFIG_IRQ_TIMER2 - 7) << IRQ_TIMER2_POS) |
- ((CONFIG_IRQ_TIMER3 - 7) << IRQ_TIMER3_POS) |
- ((CONFIG_IRQ_TIMER4 - 7) << IRQ_TIMER4_POS));
-
- bfin_write_SIC_IAR3(((CONFIG_IRQ_TIMER5 - 7) << IRQ_TIMER5_POS) |
- ((CONFIG_IRQ_TIMER6 - 7) << IRQ_TIMER6_POS) |
- ((CONFIG_IRQ_TIMER7 - 7) << IRQ_TIMER7_POS) |
- ((CONFIG_IRQ_PROG_INTA - 7) << IRQ_PROG_INTA_POS) |
- ((CONFIG_IRQ_PORTG_INTB - 7) << IRQ_PORTG_INTB_POS) |
- ((CONFIG_IRQ_MEM_DMA0 - 7) << IRQ_MEM_DMA0_POS) |
- ((CONFIG_IRQ_MEM_DMA1 - 7) << IRQ_MEM_DMA1_POS) |
- ((CONFIG_IRQ_WATCH - 7) << IRQ_WATCH_POS));
-
- SSYNC();
-}
-
-#define SPI_ERR_MASK (BIT_STAT_TXCOL | BIT_STAT_RBSY | BIT_STAT_MODF | BIT_STAT_TXE) /* SPI_STAT */
-#define SPORT_ERR_MASK (ROVF | RUVF | TOVF | TUVF) /* SPORT_STAT */
-#define PPI_ERR_MASK (0xFFFF & ~FLD) /* PPI_STATUS */
-#define EMAC_ERR_MASK (PHYINT | MMCINT | RXFSINT | TXFSINT | WAKEDET | RXDMAERR | TXDMAERR | STMDONE) /* EMAC_SYSTAT */
-#define UART_ERR_MASK (0x6) /* UART_IIR */
-#define CAN_ERR_MASK (EWTIF | EWRIF | EPIF | BOIF | WUIF | UIAIF | AAIF | RMLIF | UCEIF | EXTIF | ADIF) /* CAN_GIF */
-
-static int error_int_mask;
-
-static void bf537_generic_error_mask_irq(struct irq_data *d)
-{
- error_int_mask &= ~(1L << (d->irq - IRQ_PPI_ERROR));
- if (!error_int_mask)
- bfin_internal_mask_irq(IRQ_GENERIC_ERROR);
-}
-
-static void bf537_generic_error_unmask_irq(struct irq_data *d)
-{
- bfin_internal_unmask_irq(IRQ_GENERIC_ERROR);
- error_int_mask |= 1L << (d->irq - IRQ_PPI_ERROR);
-}
-
-static struct irq_chip bf537_generic_error_irqchip = {
- .name = "ERROR",
- .irq_ack = bfin_ack_noop,
- .irq_mask_ack = bf537_generic_error_mask_irq,
- .irq_mask = bf537_generic_error_mask_irq,
- .irq_unmask = bf537_generic_error_unmask_irq,
-};
-
-static void bf537_demux_error_irq(struct irq_desc *inta_desc)
-{
- int irq = 0;
-
-#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
- if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK)
- irq = IRQ_MAC_ERROR;
- else
-#endif
- if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK)
- irq = IRQ_SPORT0_ERROR;
- else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK)
- irq = IRQ_SPORT1_ERROR;
- else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK)
- irq = IRQ_PPI_ERROR;
- else if (bfin_read_CAN_GIF() & CAN_ERR_MASK)
- irq = IRQ_CAN_ERROR;
- else if (bfin_read_SPI_STAT() & SPI_ERR_MASK)
- irq = IRQ_SPI_ERROR;
- else if ((bfin_read_UART0_IIR() & UART_ERR_MASK) == UART_ERR_MASK)
- irq = IRQ_UART0_ERROR;
- else if ((bfin_read_UART1_IIR() & UART_ERR_MASK) == UART_ERR_MASK)
- irq = IRQ_UART1_ERROR;
-
- if (irq) {
- if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR)))
- bfin_handle_irq(irq);
- else {
-
- switch (irq) {
- case IRQ_PPI_ERROR:
- bfin_write_PPI_STATUS(PPI_ERR_MASK);
- break;
-#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
- case IRQ_MAC_ERROR:
- bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK);
- break;
-#endif
- case IRQ_SPORT0_ERROR:
- bfin_write_SPORT0_STAT(SPORT_ERR_MASK);
- break;
-
- case IRQ_SPORT1_ERROR:
- bfin_write_SPORT1_STAT(SPORT_ERR_MASK);
- break;
-
- case IRQ_CAN_ERROR:
- bfin_write_CAN_GIS(CAN_ERR_MASK);
- break;
-
- case IRQ_SPI_ERROR:
- bfin_write_SPI_STAT(SPI_ERR_MASK);
- break;
-
- default:
- break;
- }
-
- pr_debug("IRQ %d:"
- " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n",
- irq);
- }
- } else
- pr_err("%s: IRQ ?: PERIPHERAL ERROR INTERRUPT ASSERTED BUT NO SOURCE FOUND\n",
- __func__);
-
-}
-
-#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
-static int mac_rx_int_mask;
-
-static void bf537_mac_rx_mask_irq(struct irq_data *d)
-{
- mac_rx_int_mask &= ~(1L << (d->irq - IRQ_MAC_RX));
- if (!mac_rx_int_mask)
- bfin_internal_mask_irq(IRQ_PH_INTA_MAC_RX);
-}
-
-static void bf537_mac_rx_unmask_irq(struct irq_data *d)
-{
- bfin_internal_unmask_irq(IRQ_PH_INTA_MAC_RX);
- mac_rx_int_mask |= 1L << (d->irq - IRQ_MAC_RX);
-}
-
-static struct irq_chip bf537_mac_rx_irqchip = {
- .name = "ERROR",
- .irq_ack = bfin_ack_noop,
- .irq_mask_ack = bf537_mac_rx_mask_irq,
- .irq_mask = bf537_mac_rx_mask_irq,
- .irq_unmask = bf537_mac_rx_unmask_irq,
-};
-
-static void bf537_demux_mac_rx_irq(struct irq_desc *desc)
-{
- if (bfin_read_DMA1_IRQ_STATUS() & (DMA_DONE | DMA_ERR))
- bfin_handle_irq(IRQ_MAC_RX);
- else
- bfin_demux_gpio_irq(desc);
-}
-#endif
-
-void __init init_mach_irq(void)
-{
- int irq;
-
-#if defined(CONFIG_BF537) || defined(CONFIG_BF536)
- /* Clear EMAC Interrupt Status bits so we can demux it later */
- bfin_write_EMAC_SYSTAT(-1);
-#endif
-
- irq_set_chained_handler(IRQ_GENERIC_ERROR, bf537_demux_error_irq);
- for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++)
- irq_set_chip_and_handler(irq, &bf537_generic_error_irqchip,
- handle_level_irq);
-
-#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
- irq_set_chained_handler(IRQ_PH_INTA_MAC_RX, bf537_demux_mac_rx_irq);
- irq_set_chip_and_handler(IRQ_MAC_RX, &bf537_mac_rx_irqchip, handle_level_irq);
- irq_set_chip_and_handler(IRQ_PORTH_INTA, &bf537_mac_rx_irqchip, handle_level_irq);
-
- irq_set_chained_handler(IRQ_MAC_ERROR, bfin_demux_mac_status_irq);
-#endif
-}
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0
-if (BF538 || BF539)
-
-source "arch/blackfin/mach-bf538/boards/Kconfig"
-
-menu "BF538 Specific Configuration"
-
-comment "Interrupt Priority Assignment"
-menu "Priority"
-
-config IRQ_PLL_WAKEUP
- int "IRQ_PLL_WAKEUP"
- default 7
-config IRQ_DMA0_ERROR
- int "IRQ_DMA0_ERROR"
- default 7
-config IRQ_PPI_ERROR
- int "IRQ_PPI_ERROR"
- default 7
-config IRQ_SPORT0_ERROR
- int "IRQ_SPORT0_ERROR"
- default 7
-config IRQ_SPORT1_ERROR
- int "IRQ_SPORT1_ERROR"
- default 7
-config IRQ_SPI0_ERROR
- int "IRQ_SPI0_ERROR"
- default 7
-config IRQ_UART0_ERROR
- int "IRQ_UART0_ERROR"
- default 7
-config IRQ_RTC
- int "IRQ_RTC"
- default 8
-config IRQ_PPI
- int "IRQ_PPI"
- default 8
-config IRQ_SPORT0_RX
- int "IRQ_SPORT0_RX"
- default 9
-config IRQ_SPORT0_TX
- int "IRQ_SPORT0_TX"
- default 9
-config IRQ_SPORT1_RX
- int "IRQ_SPORT1_RX"
- default 9
-config IRQ_SPORT1_TX
- int "IRQ_SPORT1_TX"
- default 9
-config IRQ_SPI0
- int "IRQ_SPI0"
- default 10
-config IRQ_UART0_RX
- int "IRQ_UART0_RX"
- default 10
-config IRQ_UART0_TX
- int "IRQ_UART0_TX"
- default 10
-config IRQ_TIMER0
- int "IRQ_TIMER0"
- default 7 if TICKSOURCE_GPTMR0
- default 8
-config IRQ_TIMER1
- int "IRQ_TIMER1"
- default 11
-config IRQ_TIMER2
- int "IRQ_TIMER2"
- default 11
-config IRQ_PORTF_INTA
- int "IRQ_PORTF_INTA"
- default 12
-config IRQ_PORTF_INTB
- int "IRQ_PORTF_INTB"
- default 12
-config IRQ_MEM0_DMA0
- int "IRQ_MEM0_DMA0"
- default 13
-config IRQ_MEM0_DMA1
- int "IRQ_MEM0_DMA1"
- default 13
-config IRQ_WATCH
- int "IRQ_WATCH"
- default 13
-config IRQ_DMA1_ERROR
- int "IRQ_DMA1_ERROR"
- default 7
-config IRQ_SPORT2_ERROR
- int "IRQ_SPORT2_ERROR"
- default 7
-config IRQ_SPORT3_ERROR
- int "IRQ_SPORT3_ERROR"
- default 7
-config IRQ_SPI1_ERROR
- int "IRQ_SPI1_ERROR"
- default 7
-config IRQ_SPI2_ERROR
- int "IRQ_SPI2_ERROR"
- default 7
-config IRQ_UART1_ERROR
- int "IRQ_UART1_ERROR"
- default 7
-config IRQ_UART2_ERROR
- int "IRQ_UART2_ERROR"
- default 7
-config IRQ_CAN_ERROR
- int "IRQ_CAN_ERROR"
- default 7
-config IRQ_SPORT2_RX
- int "IRQ_SPORT2_RX"
- default 9
-config IRQ_SPORT2_TX
- int "IRQ_SPORT2_TX"
- default 9
-config IRQ_SPORT3_RX
- int "IRQ_SPORT3_RX"
- default 9
-config IRQ_SPORT3_TX
- int "IRQ_SPORT3_TX"
- default 9
-config IRQ_SPI1
- int "IRQ_SPI1"
- default 10
-config IRQ_SPI2
- int "IRQ_SPI2"
- default 10
-config IRQ_UART1_RX
- int "IRQ_UART1_RX"
- default 10
-config IRQ_UART1_TX
- int "IRQ_UART1_TX"
- default 10
-config IRQ_UART2_RX
- int "IRQ_UART2_RX"
- default 10
-config IRQ_UART2_TX
- int "IRQ_UART2_TX"
- default 10
-config IRQ_TWI0
- int "IRQ_TWI0"
- default 11
-config IRQ_TWI1
- int "IRQ_TWI1"
- default 11
-config IRQ_CAN_RX
- int "IRQ_CAN_RX"
- default 11
-config IRQ_CAN_TX
- int "IRQ_CAN_TX"
- default 11
-config IRQ_MEM1_DMA0
- int "IRQ_MEM1_DMA0"
- default 13
-config IRQ_MEM1_DMA1
- int "IRQ_MEM1_DMA1"
- default 13
-
- help
- Enter the priority numbers between 7-13 ONLY. Others are Reserved.
- This applies to all the above. It is not recommended to assign the
- highest priority number 7 to UART or any other device.
-
-endmenu
-
-endmenu
-
-endif
+++ /dev/null
-#
-# arch/blackfin/mach-bf538/Makefile
-#
-
-obj-y := ints-priority.o dma.o
-obj-$(CONFIG_GPIOLIB) += ext-gpio.o
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0
-choice
- prompt "System type"
- default BFIN538_EZKIT
- help
- Select your board!
-
-config BFIN538_EZKIT
- bool "BF538-EZKIT"
- help
- BF538-EZKIT-LITE board support.
-
-endchoice
+++ /dev/null
-#
-# arch/blackfin/mach-bf538/boards/Makefile
-#
-
-obj-$(CONFIG_BFIN538_EZKIT) += ezkit.o
+++ /dev/null
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2
- */
-
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/physmap.h>
-#include <linux/mtd/partitions.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <linux/gpio.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/dma.h>
-#include <asm/nand.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-#include <linux/input.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "ADI BF538-EZKIT";
-
-/*
- * Driver needs to know address, irq and flag pin.
- */
-
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif /* CONFIG_RTC_DRV_BFIN */
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_THR,
- .end = UART0_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-#ifdef CONFIG_BFIN_UART0_CTSRTS
- { /* CTS pin */
- .start = GPIO_PG7,
- .end = GPIO_PG7,
- .flags = IORESOURCE_IO,
- },
- { /* RTS pin */
- .start = GPIO_PG6,
- .end = GPIO_PG6,
- .flags = IORESOURCE_IO,
- },
-#endif
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif /* CONFIG_SERIAL_BFIN_UART0 */
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_THR,
- .end = UART1_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX, 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif /* CONFIG_SERIAL_BFIN_UART1 */
-#ifdef CONFIG_SERIAL_BFIN_UART2
-static struct resource bfin_uart2_resources[] = {
- {
- .start = UART2_THR,
- .end = UART2_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART2_TX,
- .end = IRQ_UART2_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART2_RX,
- .end = IRQ_UART2_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART2_ERROR,
- .end = IRQ_UART2_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART2_TX,
- .end = CH_UART2_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART2_RX,
- .end = CH_UART2_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart2_peripherals[] = {
- P_UART2_TX, P_UART2_RX, 0
-};
-
-static struct platform_device bfin_uart2_device = {
- .name = "bfin-uart",
- .id = 2,
- .num_resources = ARRAY_SIZE(bfin_uart2_resources),
- .resource = bfin_uart2_resources,
- .dev = {
- .platform_data = &bfin_uart2_peripherals, /* Passed to driver */
- },
-};
-#endif /* CONFIG_SERIAL_BFIN_UART2 */
-#endif /* CONFIG_SERIAL_BFIN */
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif /* CONFIG_BFIN_SIR0 */
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif /* CONFIG_BFIN_SIR1 */
-#ifdef CONFIG_BFIN_SIR2
-static struct resource bfin_sir2_resources[] = {
- {
- .start = 0xFFC02100,
- .end = 0xFFC021FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART2_RX,
- .end = IRQ_UART2_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART2_RX,
- .end = CH_UART2_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sir2_device = {
- .name = "bfin_sir",
- .id = 2,
- .num_resources = ARRAY_SIZE(bfin_sir2_resources),
- .resource = bfin_sir2_resources,
-};
-#endif /* CONFIG_BFIN_SIR2 */
-#endif /* CONFIG_BFIN_SIR */
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif /* CONFIG_SERIAL_BFIN_SPORT0_UART */
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif /* CONFIG_SERIAL_BFIN_SPORT1_UART */
-#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
-static struct resource bfin_sport2_uart_resources[] = {
- {
- .start = SPORT2_TCR1,
- .end = SPORT2_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT2_RX,
- .end = IRQ_SPORT2_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT2_ERROR,
- .end = IRQ_SPORT2_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport2_peripherals[] = {
- P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS,
- P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0
-};
-
-static struct platform_device bfin_sport2_uart_device = {
- .name = "bfin-sport-uart",
- .id = 2,
- .num_resources = ARRAY_SIZE(bfin_sport2_uart_resources),
- .resource = bfin_sport2_uart_resources,
- .dev = {
- .platform_data = &bfin_sport2_peripherals, /* Passed to driver */
- },
-};
-#endif /* CONFIG_SERIAL_BFIN_SPORT2_UART */
-#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
-static struct resource bfin_sport3_uart_resources[] = {
- {
- .start = SPORT3_TCR1,
- .end = SPORT3_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT3_RX,
- .end = IRQ_SPORT3_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT3_ERROR,
- .end = IRQ_SPORT3_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport3_peripherals[] = {
- P_SPORT3_TFS, P_SPORT3_DTPRI, P_SPORT3_TSCLK, P_SPORT3_RFS,
- P_SPORT3_DRPRI, P_SPORT3_RSCLK, P_SPORT3_DRSEC, P_SPORT3_DTSEC, 0
-};
-
-static struct platform_device bfin_sport3_uart_device = {
- .name = "bfin-sport-uart",
- .id = 3,
- .num_resources = ARRAY_SIZE(bfin_sport3_uart_resources),
- .resource = bfin_sport3_uart_resources,
- .dev = {
- .platform_data = &bfin_sport3_peripherals, /* Passed to driver */
- },
-};
-#endif /* CONFIG_SERIAL_BFIN_SPORT3_UART */
-#endif /* CONFIG_SERIAL_BFIN_SPORT */
-
-#if IS_ENABLED(CONFIG_CAN_BFIN)
-static unsigned short bfin_can_peripherals[] = {
- P_CAN0_RX, P_CAN0_TX, 0
-};
-
-static struct resource bfin_can_resources[] = {
- {
- .start = 0xFFC02A00,
- .end = 0xFFC02FFF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_CAN_RX,
- .end = IRQ_CAN_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_CAN_TX,
- .end = IRQ_CAN_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_CAN_ERROR,
- .end = IRQ_CAN_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_can_device = {
- .name = "bfin_can",
- .num_resources = ARRAY_SIZE(bfin_can_resources),
- .resource = bfin_can_resources,
- .dev = {
- .platform_data = &bfin_can_peripherals, /* Passed to driver */
- },
-};
-#endif /* CONFIG_CAN_BFIN */
-
-/*
- * USB-LAN EzExtender board
- * Driver needs to know address, irq and flag pin.
- */
-#if IS_ENABLED(CONFIG_SMC91X)
-#include <linux/smc91x.h>
-
-static struct smc91x_platdata smc91x_info = {
- .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
- .leda = RPC_LED_100_10,
- .ledb = RPC_LED_TX_RX,
-};
-
-static struct resource smc91x_resources[] = {
- {
- .name = "smc91x-regs",
- .start = 0x20310300,
- .end = 0x20310300 + 16,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF0,
- .end = IRQ_PF0,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev = {
- .platform_data = &smc91x_info,
- },
-};
-#endif /* CONFIG_SMC91X */
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* all SPI peripherals info goes here */
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-/* SPI flash chip (m25p16) */
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00040000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = 0x1c0000,
- .offset = 0x40000
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p16",
-};
-
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif /* CONFIG_MTD_M25P80 */
-#endif /* CONFIG_SPI_BFIN5XX */
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879)
-#include <linux/platform_data/ad7879.h>
-static const struct ad7879_platform_data bfin_ad7879_ts_info = {
- .model = 7879, /* Model = AD7879 */
- .x_plate_ohms = 620, /* 620 Ohm from the touch datasheet */
- .pressure_max = 10000,
- .pressure_min = 0,
- .first_conversion_delay = 3, /* wait 512us before do a first conversion */
- .acquisition_time = 1, /* 4us acquisition time per sample */
- .median = 2, /* do 8 measurements */
- .averaging = 1, /* take the average of 4 middle samples */
- .pen_down_acc_interval = 255, /* 9.4 ms */
- .gpio_export = 1, /* Export GPIO to gpiolib */
- .gpio_base = -1, /* Dynamic allocation */
-};
-#endif /* CONFIG_TOUCHSCREEN_AD7879 */
-
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
-#include <asm/bfin-lq035q1.h>
-
-static struct bfin_lq035q1fb_disp_info bfin_lq035q1_data = {
- .mode = LQ035_NORM | LQ035_RGB | LQ035_RL | LQ035_TB,
- .ppi_mode = USE_RGB565_16_BIT_PPI,
- .use_bl = 0, /* let something else control the LCD Blacklight */
- .gpio_bl = GPIO_PF7,
-};
-
-static struct resource bfin_lq035q1_resources[] = {
- {
- .start = IRQ_PPI_ERROR,
- .end = IRQ_PPI_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_lq035q1_device = {
- .name = "bfin-lq035q1",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_lq035q1_resources),
- .resource = bfin_lq035q1_resources,
- .dev = {
- .platform_data = &bfin_lq035q1_data,
- },
-};
-#endif /* CONFIG_FB_BFIN_LQ035Q1 */
-
-static struct spi_board_info bf538_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 1, /* SPI_SSEL1*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif /* CONFIG_MTD_M25P80 */
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879_SPI)
- {
- .modalias = "ad7879",
- .platform_data = &bfin_ad7879_ts_info,
- .irq = IRQ_PF3,
- .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- .mode = SPI_CPHA | SPI_CPOL,
- },
-#endif /* CONFIG_TOUCHSCREEN_AD7879_SPI */
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
- {
- .modalias = "bfin-lq035q1-spi",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 2,
- .mode = SPI_CPHA | SPI_CPOL,
- },
-#endif /* CONFIG_FB_BFIN_LQ035Q1 */
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- },
-#endif /* CONFIG_SPI_SPIDEV */
-};
-
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI0,
- .end = CH_SPI0,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI0,
- .end = IRQ_SPI0,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-/* SPI (1) */
-static struct resource bfin_spi1_resource[] = {
- [0] = {
- .start = SPI1_REGBASE,
- .end = SPI1_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI1,
- .end = CH_SPI1,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI1,
- .end = IRQ_SPI1,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-/* SPI (2) */
-static struct resource bfin_spi2_resource[] = {
- [0] = {
- .start = SPI2_REGBASE,
- .end = SPI2_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI2,
- .end = CH_SPI2,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI2,
- .end = IRQ_SPI2,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-/* SPI controller data */
-static struct bfin5xx_spi_master bf538_spi_master_info0 = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct platform_device bf538_spi_master0 = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bf538_spi_master_info0, /* Passed to driver */
- },
-};
-
-static struct bfin5xx_spi_master bf538_spi_master_info1 = {
- .num_chipselect = 2,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
-};
-
-static struct platform_device bf538_spi_master1 = {
- .name = "bfin-spi",
- .id = 1, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi1_resource),
- .resource = bfin_spi1_resource,
- .dev = {
- .platform_data = &bf538_spi_master_info1, /* Passed to driver */
- },
-};
-
-static struct bfin5xx_spi_master bf538_spi_master_info2 = {
- .num_chipselect = 2,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI2_SCK, P_SPI2_MISO, P_SPI2_MOSI, 0},
-};
-
-static struct platform_device bf538_spi_master2 = {
- .name = "bfin-spi",
- .id = 2, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi2_resource),
- .resource = bfin_spi2_resource,
- .dev = {
- .platform_data = &bf538_spi_master_info2, /* Passed to driver */
- },
-};
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_REGBASE,
- .end = TWI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI0,
- .end = IRQ_TWI0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi0_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-
-static const u16 bfin_twi1_pins[] = {P_TWI1_SCL, P_TWI1_SDA, 0};
-
-static struct resource bfin_twi1_resource[] = {
- [0] = {
- .start = TWI1_REGBASE,
- .end = TWI1_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI1,
- .end = IRQ_TWI1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi1_device = {
- .name = "i2c-bfin-twi",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_twi1_resource),
- .resource = bfin_twi1_resource,
-};
-#endif /* CONFIG_I2C_BLACKFIN_TWI */
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
-#include <linux/gpio_keys.h>
-
-static struct gpio_keys_button bfin_gpio_keys_table[] = {
- {BTN_0, GPIO_PC7, 1, "gpio-keys: BTN0"},
-};
-
-static struct gpio_keys_platform_data bfin_gpio_keys_data = {
- .buttons = bfin_gpio_keys_table,
- .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
-};
-
-static struct platform_device bfin_device_gpiokeys = {
- .name = "gpio-keys",
- .dev = {
- .platform_data = &bfin_gpio_keys_data,
- },
-};
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
-/*
- * Internal VLEV BF538SBBC1533
- ****temporarily using these values until data sheet is updated
- */
- VRPAIR(VLEV_100, 150000000),
- VRPAIR(VLEV_100, 250000000),
- VRPAIR(VLEV_110, 276000000),
- VRPAIR(VLEV_115, 301000000),
- VRPAIR(VLEV_120, 525000000),
- VRPAIR(VLEV_125, 550000000),
- VRPAIR(VLEV_130, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
-static struct mtd_partition ezkit_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x40000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0x180000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct physmap_flash_data ezkit_flash_data = {
- .width = 2,
- .parts = ezkit_partitions,
- .nr_parts = ARRAY_SIZE(ezkit_partitions),
-};
-
-static struct resource ezkit_flash_resource = {
- .start = 0x20000000,
-#if IS_ENABLED(CONFIG_SMC91X)
- .end = 0x202fffff,
-#else
- .end = 0x203fffff,
-#endif
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device ezkit_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &ezkit_flash_data,
- },
- .num_resources = 1,
- .resource = &ezkit_flash_resource,
-};
-#endif
-
-static struct platform_device *cm_bf538_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART2
- &bfin_uart2_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bf538_spi_master0,
- &bf538_spi_master1,
- &bf538_spi_master2,
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi0_device,
- &i2c_bfin_twi1_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#ifdef CONFIG_BFIN_SIR2
- &bfin_sir2_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
- &bfin_sport2_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
- &bfin_sport3_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_CAN_BFIN)
- &bfin_can_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
- &smc91x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
- &bfin_lq035q1_device,
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
- &bfin_device_gpiokeys,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
- &ezkit_flash_device,
-#endif
-};
-
-static int __init ezkit_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- platform_add_devices(cm_bf538_devices, ARRAY_SIZE(cm_bf538_devices));
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- spi_register_board_info(bf538_spi_board_info,
- ARRAY_SIZE(bf538_spi_board_info));
-#endif
-
- return 0;
-}
-
-arch_initcall(ezkit_init);
-
-static struct platform_device *ezkit_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART2
- &bfin_uart2_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
- &bfin_sport2_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
- &bfin_sport3_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(ezkit_early_devices,
- ARRAY_SIZE(ezkit_early_devices));
-}
+++ /dev/null
-/*
- * the simple DMA Implementation for Blackfin
- *
- * Copyright 2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-
-#include <asm/blackfin.h>
-#include <asm/dma.h>
-
-struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
- (struct dma_register *) DMA0_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_NEXT_DESC_PTR,
- (struct dma_register *) DMA3_NEXT_DESC_PTR,
- (struct dma_register *) DMA4_NEXT_DESC_PTR,
- (struct dma_register *) DMA5_NEXT_DESC_PTR,
- (struct dma_register *) DMA6_NEXT_DESC_PTR,
- (struct dma_register *) DMA7_NEXT_DESC_PTR,
- (struct dma_register *) DMA8_NEXT_DESC_PTR,
- (struct dma_register *) DMA9_NEXT_DESC_PTR,
- (struct dma_register *) DMA10_NEXT_DESC_PTR,
- (struct dma_register *) DMA11_NEXT_DESC_PTR,
- (struct dma_register *) DMA12_NEXT_DESC_PTR,
- (struct dma_register *) DMA13_NEXT_DESC_PTR,
- (struct dma_register *) DMA14_NEXT_DESC_PTR,
- (struct dma_register *) DMA15_NEXT_DESC_PTR,
- (struct dma_register *) DMA16_NEXT_DESC_PTR,
- (struct dma_register *) DMA17_NEXT_DESC_PTR,
- (struct dma_register *) DMA18_NEXT_DESC_PTR,
- (struct dma_register *) DMA19_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D2_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S2_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D3_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S3_NEXT_DESC_PTR,
-};
-EXPORT_SYMBOL(dma_io_base_addr);
-
-int channel2irq(unsigned int channel)
-{
- int ret_irq = -1;
-
- switch (channel) {
- case CH_PPI:
- ret_irq = IRQ_PPI;
- break;
-
- case CH_UART0_RX:
- ret_irq = IRQ_UART0_RX;
- break;
-
- case CH_UART0_TX:
- ret_irq = IRQ_UART0_TX;
- break;
-
- case CH_UART1_RX:
- ret_irq = IRQ_UART1_RX;
- break;
-
- case CH_UART1_TX:
- ret_irq = IRQ_UART1_TX;
- break;
-
- case CH_UART2_RX:
- ret_irq = IRQ_UART2_RX;
- break;
-
- case CH_UART2_TX:
- ret_irq = IRQ_UART2_TX;
- break;
-
- case CH_SPORT0_RX:
- ret_irq = IRQ_SPORT0_RX;
- break;
-
- case CH_SPORT0_TX:
- ret_irq = IRQ_SPORT0_TX;
- break;
-
- case CH_SPORT1_RX:
- ret_irq = IRQ_SPORT1_RX;
- break;
-
- case CH_SPORT1_TX:
- ret_irq = IRQ_SPORT1_TX;
- break;
-
- case CH_SPORT2_RX:
- ret_irq = IRQ_SPORT2_RX;
- break;
-
- case CH_SPORT2_TX:
- ret_irq = IRQ_SPORT2_TX;
- break;
-
- case CH_SPORT3_RX:
- ret_irq = IRQ_SPORT3_RX;
- break;
-
- case CH_SPORT3_TX:
- ret_irq = IRQ_SPORT3_TX;
- break;
-
- case CH_SPI0:
- ret_irq = IRQ_SPI0;
- break;
-
- case CH_SPI1:
- ret_irq = IRQ_SPI1;
- break;
-
- case CH_SPI2:
- ret_irq = IRQ_SPI2;
- break;
-
- case CH_MEM_STREAM0_SRC:
- case CH_MEM_STREAM0_DEST:
- ret_irq = IRQ_MEM0_DMA0;
- break;
- case CH_MEM_STREAM1_SRC:
- case CH_MEM_STREAM1_DEST:
- ret_irq = IRQ_MEM0_DMA1;
- break;
- case CH_MEM_STREAM2_SRC:
- case CH_MEM_STREAM2_DEST:
- ret_irq = IRQ_MEM1_DMA0;
- break;
- case CH_MEM_STREAM3_SRC:
- case CH_MEM_STREAM3_DEST:
- ret_irq = IRQ_MEM1_DMA1;
- break;
- }
- return ret_irq;
-}
+++ /dev/null
-/*
- * GPIOLIB interface for BF538/9 PORT C, D, and E GPIOs
- *
- * Copyright 2009-2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-#include <linux/err.h>
-#include <linux/gpio.h>
-#include <asm/blackfin.h>
-#include <asm/portmux.h>
-
-#define DEFINE_REG(reg, off) \
-static inline u16 read_##reg(void __iomem *port) \
- { return bfin_read16(port + off); } \
-static inline void write_##reg(void __iomem *port, u16 v) \
- { bfin_write16(port + off, v); }
-
-DEFINE_REG(PORTIO, 0x00)
-DEFINE_REG(PORTIO_CLEAR, 0x10)
-DEFINE_REG(PORTIO_SET, 0x20)
-DEFINE_REG(PORTIO_DIR, 0x40)
-DEFINE_REG(PORTIO_INEN, 0x50)
-
-static void __iomem *gpio_chip_to_mmr(struct gpio_chip *chip)
-{
- switch (chip->base) {
- default: /* not really needed, but keeps gcc happy */
- case GPIO_PC0: return (void __iomem *)PORTCIO;
- case GPIO_PD0: return (void __iomem *)PORTDIO;
- case GPIO_PE0: return (void __iomem *)PORTEIO;
- }
-}
-
-static int bf538_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
-{
- void __iomem *port = gpio_chip_to_mmr(chip);
- return !!(read_PORTIO(port) & (1u << gpio));
-}
-
-static void bf538_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
-{
- void __iomem *port = gpio_chip_to_mmr(chip);
- if (value)
- write_PORTIO_SET(port, (1u << gpio));
- else
- write_PORTIO_CLEAR(port, (1u << gpio));
-}
-
-static int bf538_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
-{
- void __iomem *port = gpio_chip_to_mmr(chip);
- write_PORTIO_DIR(port, read_PORTIO_DIR(port) & ~(1u << gpio));
- write_PORTIO_INEN(port, read_PORTIO_INEN(port) | (1u << gpio));
- return 0;
-}
-
-static int bf538_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
-{
- void __iomem *port = gpio_chip_to_mmr(chip);
- write_PORTIO_INEN(port, read_PORTIO_INEN(port) & ~(1u << gpio));
- bf538_gpio_set_value(port, gpio, value);
- write_PORTIO_DIR(port, read_PORTIO_DIR(port) | (1u << gpio));
- return 0;
-}
-
-static int bf538_gpio_request(struct gpio_chip *chip, unsigned gpio)
-{
- return bfin_special_gpio_request(chip->base + gpio, chip->label);
-}
-
-static void bf538_gpio_free(struct gpio_chip *chip, unsigned gpio)
-{
- return bfin_special_gpio_free(chip->base + gpio);
-}
-
-/* We don't set the irq fields as these banks cannot generate interrupts */
-
-static struct gpio_chip bf538_portc_chip = {
- .label = "GPIO-PC",
- .direction_input = bf538_gpio_direction_input,
- .get = bf538_gpio_get_value,
- .direction_output = bf538_gpio_direction_output,
- .set = bf538_gpio_set_value,
- .request = bf538_gpio_request,
- .free = bf538_gpio_free,
- .base = GPIO_PC0,
- .ngpio = GPIO_PC9 - GPIO_PC0 + 1,
-};
-
-static struct gpio_chip bf538_portd_chip = {
- .label = "GPIO-PD",
- .direction_input = bf538_gpio_direction_input,
- .get = bf538_gpio_get_value,
- .direction_output = bf538_gpio_direction_output,
- .set = bf538_gpio_set_value,
- .request = bf538_gpio_request,
- .free = bf538_gpio_free,
- .base = GPIO_PD0,
- .ngpio = GPIO_PD13 - GPIO_PD0 + 1,
-};
-
-static struct gpio_chip bf538_porte_chip = {
- .label = "GPIO-PE",
- .direction_input = bf538_gpio_direction_input,
- .get = bf538_gpio_get_value,
- .direction_output = bf538_gpio_direction_output,
- .set = bf538_gpio_set_value,
- .request = bf538_gpio_request,
- .free = bf538_gpio_free,
- .base = GPIO_PE0,
- .ngpio = GPIO_PE15 - GPIO_PE0 + 1,
-};
-
-static int __init bf538_extgpio_setup(void)
-{
- return gpiochip_add_data(&bf538_portc_chip, NULL) |
- gpiochip_add_data(&bf538_portd_chip, NULL) |
- gpiochip_add_data(&bf538_porte_chip, NULL);
-}
-arch_initcall(bf538_extgpio_setup);
-
-#ifdef CONFIG_PM
-static struct {
- u16 data, dir, inen;
-} gpio_bank_saved[3];
-
-static void __iomem * const port_bases[3] = {
- (void *)PORTCIO,
- (void *)PORTDIO,
- (void *)PORTEIO,
-};
-
-void bfin_special_gpio_pm_hibernate_suspend(void)
-{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(port_bases); ++i) {
- gpio_bank_saved[i].data = read_PORTIO(port_bases[i]);
- gpio_bank_saved[i].inen = read_PORTIO_INEN(port_bases[i]);
- gpio_bank_saved[i].dir = read_PORTIO_DIR(port_bases[i]);
- }
-}
-
-void bfin_special_gpio_pm_hibernate_restore(void)
-{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(port_bases); ++i) {
- write_PORTIO_INEN(port_bases[i], gpio_bank_saved[i].inen);
- write_PORTIO_SET(port_bases[i],
- gpio_bank_saved[i].data & gpio_bank_saved[i].dir);
- write_PORTIO_DIR(port_bases[i], gpio_bank_saved[i].dir);
- }
-}
-#endif
+++ /dev/null
-/*
- * DO NOT EDIT THIS FILE
- * This file is under version control at
- * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
- * and can be replaced with that version at any time
- * DO NOT EDIT THIS FILE
- *
- * Copyright 2004-2011 Analog Devices Inc.
- * Licensed under the Clear BSD license.
- */
-
-/* This file should be up to date with:
- * - Revision J, 05/23/2011; ADSP-BF538/BF538F Blackfin Processor Anomaly List
- * - Revision O, 05/23/2011; ADSP-BF539/BF539F Blackfin Processor Anomaly List
- */
-
-#ifndef _MACH_ANOMALY_H_
-#define _MACH_ANOMALY_H_
-
-/* We do not support old silicon - sorry */
-#if __SILICON_REVISION__ < 4
-# error will not work on BF538/BF539 silicon version 0.0, 0.1, 0.2, or 0.3
-#endif
-
-#if defined(__ADSPBF538__)
-# define ANOMALY_BF538 1
-#else
-# define ANOMALY_BF538 0
-#endif
-#if defined(__ADSPBF539__)
-# define ANOMALY_BF539 1
-#else
-# define ANOMALY_BF539 0
-#endif
-
-/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
-#define ANOMALY_05000074 (1)
-/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
-#define ANOMALY_05000119 (1)
-/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
-#define ANOMALY_05000122 (1)
-/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */
-#define ANOMALY_05000166 (1)
-/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */
-#define ANOMALY_05000179 (1)
-/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
-#define ANOMALY_05000180 (1)
-/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */
-#define ANOMALY_05000193 (1)
-/* Current DMA Address Shows Wrong Value During Carry Fix */
-#define ANOMALY_05000199 (__SILICON_REVISION__ < 4)
-/* NMI Event at Boot Time Results in Unpredictable State */
-#define ANOMALY_05000219 (1)
-/* SPI Slave Boot Mode Modifies Registers from Reset Value */
-#define ANOMALY_05000229 (1)
-/* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */
-#define ANOMALY_05000233 (1)
-/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
-#define ANOMALY_05000245 (1)
-/* Maximum External Clock Speed for Timers */
-#define ANOMALY_05000253 (1)
-/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
-#define ANOMALY_05000270 (__SILICON_REVISION__ < 4)
-/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
-#define ANOMALY_05000272 (ANOMALY_BF538)
-/* Writes to Synchronous SDRAM Memory May Be Lost */
-#define ANOMALY_05000273 (__SILICON_REVISION__ < 4)
-/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
-#define ANOMALY_05000277 (__SILICON_REVISION__ < 4)
-/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
-#define ANOMALY_05000278 (__SILICON_REVISION__ < 4)
-/* False Hardware Error when ISR Context Is Not Restored */
-#define ANOMALY_05000281 (__SILICON_REVISION__ < 4)
-/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
-#define ANOMALY_05000282 (__SILICON_REVISION__ < 4)
-/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */
-#define ANOMALY_05000283 (__SILICON_REVISION__ < 4)
-/* SPORTs May Receive Bad Data If FIFOs Fill Up */
-#define ANOMALY_05000288 (__SILICON_REVISION__ < 4)
-/* Reads from CAN Mailbox and Acceptance Mask Area Can Fail */
-#define ANOMALY_05000291 (__SILICON_REVISION__ < 4)
-/* Hibernate Leakage Current Is Higher Than Specified */
-#define ANOMALY_05000293 (__SILICON_REVISION__ < 4)
-/* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */
-#define ANOMALY_05000294 (1)
-/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
-#define ANOMALY_05000301 (__SILICON_REVISION__ < 4)
-/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
-#define ANOMALY_05000304 (__SILICON_REVISION__ < 4)
-/* SCKELOW Bit Does Not Maintain State Through Hibernate */
-#define ANOMALY_05000307 (__SILICON_REVISION__ < 4)
-/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
-#define ANOMALY_05000310 (1)
-/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
-#define ANOMALY_05000312 (__SILICON_REVISION__ < 5)
-/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
-#define ANOMALY_05000313 (__SILICON_REVISION__ < 4)
-/* Killed System MMR Write Completes Erroneously on Next System MMR Access */
-#define ANOMALY_05000315 (__SILICON_REVISION__ < 4)
-/* PFx Glitch on Write to PORTFIO or PORTFIO_TOGGLE */
-#define ANOMALY_05000317 (__SILICON_REVISION__ < 4) /* XXX: Same as 05000318 */
-/* PFx Glitch on Write to FIO_FLAG_D or FIO_FLAG_T */
-#define ANOMALY_05000318 (__SILICON_REVISION__ < 4) /* XXX: Same as 05000317 */
-/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
-#define ANOMALY_05000355 (__SILICON_REVISION__ < 5)
-/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
-#define ANOMALY_05000357 (__SILICON_REVISION__ < 5)
-/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
-#define ANOMALY_05000366 (1)
-/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
-#define ANOMALY_05000371 (__SILICON_REVISION__ < 5)
-/* Entering Hibernate State with Peripheral Wakeups Enabled Draws Excess Current */
-#define ANOMALY_05000374 (__SILICON_REVISION__ == 4)
-/* GPIO Pins PC1 and PC4 Can Function as Normal Outputs */
-#define ANOMALY_05000375 (__SILICON_REVISION__ < 4)
-/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
-#define ANOMALY_05000402 (__SILICON_REVISION__ == 3)
-/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
-#define ANOMALY_05000403 (1)
-/* Speculative Fetches Can Cause Undesired External FIFO Operations */
-#define ANOMALY_05000416 (1)
-/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
-#define ANOMALY_05000425 (1)
-/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
-#define ANOMALY_05000426 (1)
-/* Specific GPIO Pins May Change State when Entering Hibernate */
-#define ANOMALY_05000436 (__SILICON_REVISION__ > 3)
-/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
-#define ANOMALY_05000443 (1)
-/* False Hardware Error when RETI Points to Invalid Memory */
-#define ANOMALY_05000461 (1)
-/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
-#define ANOMALY_05000462 (1)
-/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
-#define ANOMALY_05000473 (1)
-/* Possible Lockup Condition when Modifying PLL from External Memory */
-#define ANOMALY_05000475 (1)
-/* TESTSET Instruction Cannot Be Interrupted */
-#define ANOMALY_05000477 (1)
-/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
-#define ANOMALY_05000481 (1)
-/* PLL May Latch Incorrect Values Coming Out of Reset */
-#define ANOMALY_05000489 (1)
-/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
-#define ANOMALY_05000491 (1)
-/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
-#define ANOMALY_05000494 (1)
-/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
-#define ANOMALY_05000501 (1)
-
-/*
- * These anomalies have been "phased" out of analog.com anomaly sheets and are
- * here to show running on older silicon just isn't feasible.
- */
-
-/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
-#define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
-/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
-#define ANOMALY_05000261 (__SILICON_REVISION__ < 3)
-
-/* Anomalies that don't exist on this proc */
-#define ANOMALY_05000099 (0)
-#define ANOMALY_05000120 (0)
-#define ANOMALY_05000125 (0)
-#define ANOMALY_05000149 (0)
-#define ANOMALY_05000158 (0)
-#define ANOMALY_05000171 (0)
-#define ANOMALY_05000182 (0)
-#define ANOMALY_05000189 (0)
-#define ANOMALY_05000198 (0)
-#define ANOMALY_05000202 (0)
-#define ANOMALY_05000215 (0)
-#define ANOMALY_05000220 (0)
-#define ANOMALY_05000227 (0)
-#define ANOMALY_05000230 (0)
-#define ANOMALY_05000231 (0)
-#define ANOMALY_05000234 (0)
-#define ANOMALY_05000242 (0)
-#define ANOMALY_05000248 (0)
-#define ANOMALY_05000250 (0)
-#define ANOMALY_05000254 (0)
-#define ANOMALY_05000257 (0)
-#define ANOMALY_05000263 (0)
-#define ANOMALY_05000266 (0)
-#define ANOMALY_05000274 (0)
-#define ANOMALY_05000287 (0)
-#define ANOMALY_05000305 (0)
-#define ANOMALY_05000311 (0)
-#define ANOMALY_05000323 (0)
-#define ANOMALY_05000353 (1)
-#define ANOMALY_05000362 (1)
-#define ANOMALY_05000363 (0)
-#define ANOMALY_05000364 (0)
-#define ANOMALY_05000380 (0)
-#define ANOMALY_05000383 (0)
-#define ANOMALY_05000386 (1)
-#define ANOMALY_05000389 (0)
-#define ANOMALY_05000400 (0)
-#define ANOMALY_05000412 (0)
-#define ANOMALY_05000430 (0)
-#define ANOMALY_05000432 (0)
-#define ANOMALY_05000435 (0)
-#define ANOMALY_05000440 (0)
-#define ANOMALY_05000447 (0)
-#define ANOMALY_05000448 (0)
-#define ANOMALY_05000456 (0)
-#define ANOMALY_05000450 (0)
-#define ANOMALY_05000465 (0)
-#define ANOMALY_05000467 (0)
-#define ANOMALY_05000474 (0)
-#define ANOMALY_05000480 (0)
-#define ANOMALY_05000485 (0)
-#define ANOMALY_16000030 (0)
-
-#endif
+++ /dev/null
-/*
- * SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF538
- *
- * Copyright 2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __MACH_BF538_H__
-#define __MACH_BF538_H__
-
-#define OFFSET_(x) ((x) & 0x0000FFFF)
-
-/*some misc defines*/
-#define IMASK_IVG15 0x8000
-#define IMASK_IVG14 0x4000
-#define IMASK_IVG13 0x2000
-#define IMASK_IVG12 0x1000
-
-#define IMASK_IVG11 0x0800
-#define IMASK_IVG10 0x0400
-#define IMASK_IVG9 0x0200
-#define IMASK_IVG8 0x0100
-
-#define IMASK_IVG7 0x0080
-#define IMASK_IVGTMR 0x0040
-#define IMASK_IVGHW 0x0020
-
-/***************************/
-
-#define BFIN_DSUBBANKS 4
-#define BFIN_DWAYS 2
-#define BFIN_DLINES 64
-#define BFIN_ISUBBANKS 4
-#define BFIN_IWAYS 4
-#define BFIN_ILINES 32
-
-#define WAY0_L 0x1
-#define WAY1_L 0x2
-#define WAY01_L 0x3
-#define WAY2_L 0x4
-#define WAY02_L 0x5
-#define WAY12_L 0x6
-#define WAY012_L 0x7
-
-#define WAY3_L 0x8
-#define WAY03_L 0x9
-#define WAY13_L 0xA
-#define WAY013_L 0xB
-
-#define WAY32_L 0xC
-#define WAY320_L 0xD
-#define WAY321_L 0xE
-#define WAYALL_L 0xF
-
-#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
-
-/********************************* EBIU Settings ************************************/
-#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
-#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
-
-#ifdef CONFIG_C_AMBEN_ALL
-#define V_AMBEN AMBEN_ALL
-#endif
-#ifdef CONFIG_C_AMBEN
-#define V_AMBEN 0x0
-#endif
-#ifdef CONFIG_C_AMBEN_B0
-#define V_AMBEN AMBEN_B0
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1
-#define V_AMBEN AMBEN_B0_B1
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1_B2
-#define V_AMBEN AMBEN_B0_B1_B2
-#endif
-#ifdef CONFIG_C_AMCKEN
-#define V_AMCKEN AMCKEN
-#else
-#define V_AMCKEN 0x0
-#endif
-#ifdef CONFIG_C_CDPRIO
-#define V_CDPRIO 0x100
-#else
-#define V_CDPRIO 0x0
-#endif
-
-#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO)
-
-#ifdef CONFIG_BF538
-#define CPU "BF538"
-#define CPUID 0x27C4
-#endif
-#ifdef CONFIG_BF539
-#define CPU "BF539"
-#define CPUID 0x27C4 /* FXIME:? */
-#endif
-
-#ifndef CPU
-#error "Unknown CPU type - This kernel doesn't seem to be configured properly"
-#endif
-
-#endif /* __MACH_BF538_H__ */
+++ /dev/null
-/*
- * mach/bfin_serial.h - Blackfin UART/Serial definitions
- *
- * Copyright 2006-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MACH_SERIAL_H__
-#define __BFIN_MACH_SERIAL_H__
-
-#define BFIN_UART_NR_PORTS 3
-
-#endif
+++ /dev/null
-/*
- * Copyright 2008-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_BLACKFIN_H_
-#define _MACH_BLACKFIN_H_
-
-#define BF538_FAMILY
-
-#include "bf538.h"
-#include "anomaly.h"
-
-#include <asm/def_LPBlackfin.h>
-#ifdef CONFIG_BF538
-# include "defBF538.h"
-#endif
-#ifdef CONFIG_BF539
-# include "defBF539.h"
-#endif
-
-#ifndef __ASSEMBLY__
-# include <asm/cdef_LPBlackfin.h>
-# ifdef CONFIG_BF538
-# include "cdefBF538.h"
-# endif
-# ifdef CONFIG_BF539
-# include "cdefBF539.h"
-# endif
-#endif
-
-#endif
+++ /dev/null
-/*
- * Copyright 2008-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CDEF_BF538_H
-#define _CDEF_BF538_H
-
-#define bfin_writePTR(addr, val) bfin_write32(addr, val)
-
-#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
-#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
-#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
-#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
-#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
-#define bfin_read_CHIPID() bfin_read32(CHIPID)
-#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
-#define bfin_read_SWRST() bfin_read16(SWRST)
-#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
-#define bfin_read_SYSCR() bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
-#define bfin_read_SIC_RVECT() bfin_readPTR(SIC_RVECT)
-#define bfin_write_SIC_RVECT(val) bfin_writePTR(SIC_RVECT, val)
-#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
-#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
-#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)
-#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val)
-#define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + x * (SIC_IMASK1 - SIC_IMASK0))
-#define bfin_write_SIC_IMASK(x, val) bfin_write32(SIC_IMASK0 + x * (SIC_IMASK1 - SIC_IMASK0), val)
-#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
-#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
-#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
-#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
-#define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + x * (SIC_ISR1 - SIC_ISR0))
-#define bfin_write_SIC_ISR(x, val) bfin_write32(SIC_ISR0 + x * (SIC_ISR1 - SIC_ISR0), val)
-#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
-#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
-#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
-#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val)
-#define bfin_read_SIC_IWR(x) bfin_read32(SIC_IWR0 + x * (SIC_IWR1 - SIC_IWR0))
-#define bfin_write_SIC_IWR(x, val) bfin_write32(SIC_IWR0 + x * (SIC_IWR1 - SIC_IWR0), val)
-#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
-#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
-#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
-#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val)
-#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
-#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val)
-#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
-#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val)
-#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4)
-#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val)
-#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5)
-#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val)
-#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6)
-#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val)
-#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
-#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
-#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
-#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
-#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val)
-#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
-#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val)
-#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
-#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val)
-#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
-#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val)
-#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
-#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val)
-#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
-#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val)
-#define bfin_read_UART0_THR() bfin_read16(UART0_THR)
-#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val)
-#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR)
-#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val)
-#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL)
-#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val)
-#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH)
-#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val)
-#define bfin_read_UART0_IER() bfin_read16(UART0_IER)
-#define bfin_write_UART0_IER(val) bfin_write16(UART0_IER, val)
-#define bfin_read_UART0_IIR() bfin_read16(UART0_IIR)
-#define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR, val)
-#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR)
-#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val)
-#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR)
-#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val)
-#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR)
-#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val)
-#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR)
-#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val)
-#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL)
-#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val)
-#define bfin_read_UART1_THR() bfin_read16(UART1_THR)
-#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val)
-#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR)
-#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val)
-#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL)
-#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val)
-#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH)
-#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val)
-#define bfin_read_UART1_IER() bfin_read16(UART1_IER)
-#define bfin_write_UART1_IER(val) bfin_write16(UART1_IER, val)
-#define bfin_read_UART1_IIR() bfin_read16(UART1_IIR)
-#define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR, val)
-#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR)
-#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val)
-#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR)
-#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val)
-#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR)
-#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val)
-#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR)
-#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val)
-#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL)
-#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val)
-#define bfin_read_UART2_THR() bfin_read16(UART2_THR)
-#define bfin_write_UART2_THR(val) bfin_write16(UART2_THR, val)
-#define bfin_read_UART2_RBR() bfin_read16(UART2_RBR)
-#define bfin_write_UART2_RBR(val) bfin_write16(UART2_RBR, val)
-#define bfin_read_UART2_DLL() bfin_read16(UART2_DLL)
-#define bfin_write_UART2_DLL(val) bfin_write16(UART2_DLL, val)
-#define bfin_read_UART2_DLH() bfin_read16(UART2_DLH)
-#define bfin_write_UART2_DLH(val) bfin_write16(UART2_DLH, val)
-#define bfin_read_UART2_IER() bfin_read16(UART2_IER)
-#define bfin_write_UART2_IER(val) bfin_write16(UART2_IER, val)
-#define bfin_read_UART2_IIR() bfin_read16(UART2_IIR)
-#define bfin_write_UART2_IIR(val) bfin_write16(UART2_IIR, val)
-#define bfin_read_UART2_LCR() bfin_read16(UART2_LCR)
-#define bfin_write_UART2_LCR(val) bfin_write16(UART2_LCR, val)
-#define bfin_read_UART2_MCR() bfin_read16(UART2_MCR)
-#define bfin_write_UART2_MCR(val) bfin_write16(UART2_MCR, val)
-#define bfin_read_UART2_LSR() bfin_read16(UART2_LSR)
-#define bfin_write_UART2_LSR(val) bfin_write16(UART2_LSR, val)
-#define bfin_read_UART2_SCR() bfin_read16(UART2_SCR)
-#define bfin_write_UART2_SCR(val) bfin_write16(UART2_SCR, val)
-#define bfin_read_UART2_GCTL() bfin_read16(UART2_GCTL)
-#define bfin_write_UART2_GCTL(val) bfin_write16(UART2_GCTL, val)
-#define bfin_read_SPI0_CTL() bfin_read16(SPI0_CTL)
-#define bfin_write_SPI0_CTL(val) bfin_write16(SPI0_CTL, val)
-#define bfin_read_SPI0_FLG() bfin_read16(SPI0_FLG)
-#define bfin_write_SPI0_FLG(val) bfin_write16(SPI0_FLG, val)
-#define bfin_read_SPI0_STAT() bfin_read16(SPI0_STAT)
-#define bfin_write_SPI0_STAT(val) bfin_write16(SPI0_STAT, val)
-#define bfin_read_SPI0_TDBR() bfin_read16(SPI0_TDBR)
-#define bfin_write_SPI0_TDBR(val) bfin_write16(SPI0_TDBR, val)
-#define bfin_read_SPI0_RDBR() bfin_read16(SPI0_RDBR)
-#define bfin_write_SPI0_RDBR(val) bfin_write16(SPI0_RDBR, val)
-#define bfin_read_SPI0_BAUD() bfin_read16(SPI0_BAUD)
-#define bfin_write_SPI0_BAUD(val) bfin_write16(SPI0_BAUD, val)
-#define bfin_read_SPI0_SHADOW() bfin_read16(SPI0_SHADOW)
-#define bfin_write_SPI0_SHADOW(val) bfin_write16(SPI0_SHADOW, val)
-#define bfin_read_SPI1_CTL() bfin_read16(SPI1_CTL)
-#define bfin_write_SPI1_CTL(val) bfin_write16(SPI1_CTL, val)
-#define bfin_read_SPI1_FLG() bfin_read16(SPI1_FLG)
-#define bfin_write_SPI1_FLG(val) bfin_write16(SPI1_FLG, val)
-#define bfin_read_SPI1_STAT() bfin_read16(SPI1_STAT)
-#define bfin_write_SPI1_STAT(val) bfin_write16(SPI1_STAT, val)
-#define bfin_read_SPI1_TDBR() bfin_read16(SPI1_TDBR)
-#define bfin_write_SPI1_TDBR(val) bfin_write16(SPI1_TDBR, val)
-#define bfin_read_SPI1_RDBR() bfin_read16(SPI1_RDBR)
-#define bfin_write_SPI1_RDBR(val) bfin_write16(SPI1_RDBR, val)
-#define bfin_read_SPI1_BAUD() bfin_read16(SPI1_BAUD)
-#define bfin_write_SPI1_BAUD(val) bfin_write16(SPI1_BAUD, val)
-#define bfin_read_SPI1_SHADOW() bfin_read16(SPI1_SHADOW)
-#define bfin_write_SPI1_SHADOW(val) bfin_write16(SPI1_SHADOW, val)
-#define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL)
-#define bfin_write_SPI2_CTL(val) bfin_write16(SPI2_CTL, val)
-#define bfin_read_SPI2_FLG() bfin_read16(SPI2_FLG)
-#define bfin_write_SPI2_FLG(val) bfin_write16(SPI2_FLG, val)
-#define bfin_read_SPI2_STAT() bfin_read16(SPI2_STAT)
-#define bfin_write_SPI2_STAT(val) bfin_write16(SPI2_STAT, val)
-#define bfin_read_SPI2_TDBR() bfin_read16(SPI2_TDBR)
-#define bfin_write_SPI2_TDBR(val) bfin_write16(SPI2_TDBR, val)
-#define bfin_read_SPI2_RDBR() bfin_read16(SPI2_RDBR)
-#define bfin_write_SPI2_RDBR(val) bfin_write16(SPI2_RDBR, val)
-#define bfin_read_SPI2_BAUD() bfin_read16(SPI2_BAUD)
-#define bfin_write_SPI2_BAUD(val) bfin_write16(SPI2_BAUD, val)
-#define bfin_read_SPI2_SHADOW() bfin_read16(SPI2_SHADOW)
-#define bfin_write_SPI2_SHADOW(val) bfin_write16(SPI2_SHADOW, val)
-#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
-#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
-#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
-#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
-#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
-#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
-#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
-#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
-#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
-#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE)
-#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val)
-#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE)
-#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val)
-#define bfin_read_TIMER_STATUS() bfin_read16(TIMER_STATUS)
-#define bfin_write_TIMER_STATUS(val) bfin_write16(TIMER_STATUS, val)
-#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
-#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
-#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
-#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
-#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
-#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
-#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
-#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
-#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
-#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
-#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
-#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
-#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
-#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
-#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
-#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
-#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
-#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
-#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
-#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
-#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
-#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val)
-#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val)
-#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
-#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
-#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
-#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
-#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
-#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val)
-#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
-#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val)
-#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val)
-#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val)
-#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val)
-#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val)
-#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
-#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val)
-#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
-#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val)
-#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
-#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val)
-#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
-#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val)
-#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
-#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val)
-#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
-#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val)
-#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
-#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val)
-#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
-#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val)
-#define bfin_read_SPORT2_TCR1() bfin_read16(SPORT2_TCR1)
-#define bfin_write_SPORT2_TCR1(val) bfin_write16(SPORT2_TCR1, val)
-#define bfin_read_SPORT2_TCR2() bfin_read16(SPORT2_TCR2)
-#define bfin_write_SPORT2_TCR2(val) bfin_write16(SPORT2_TCR2, val)
-#define bfin_read_SPORT2_TCLKDIV() bfin_read16(SPORT2_TCLKDIV)
-#define bfin_write_SPORT2_TCLKDIV(val) bfin_write16(SPORT2_TCLKDIV, val)
-#define bfin_read_SPORT2_TFSDIV() bfin_read16(SPORT2_TFSDIV)
-#define bfin_write_SPORT2_TFSDIV(val) bfin_write16(SPORT2_TFSDIV, val)
-#define bfin_read_SPORT2_TX() bfin_read32(SPORT2_TX)
-#define bfin_write_SPORT2_TX(val) bfin_write32(SPORT2_TX, val)
-#define bfin_read_SPORT2_RX() bfin_read32(SPORT2_RX)
-#define bfin_write_SPORT2_RX(val) bfin_write32(SPORT2_RX, val)
-#define bfin_read_SPORT2_RCR1() bfin_read16(SPORT2_RCR1)
-#define bfin_write_SPORT2_RCR1(val) bfin_write16(SPORT2_RCR1, val)
-#define bfin_read_SPORT2_RCR2() bfin_read16(SPORT2_RCR2)
-#define bfin_write_SPORT2_RCR2(val) bfin_write16(SPORT2_RCR2, val)
-#define bfin_read_SPORT2_RCLKDIV() bfin_read16(SPORT2_RCLKDIV)
-#define bfin_write_SPORT2_RCLKDIV(val) bfin_write16(SPORT2_RCLKDIV, val)
-#define bfin_read_SPORT2_RFSDIV() bfin_read16(SPORT2_RFSDIV)
-#define bfin_write_SPORT2_RFSDIV(val) bfin_write16(SPORT2_RFSDIV, val)
-#define bfin_read_SPORT2_STAT() bfin_read16(SPORT2_STAT)
-#define bfin_write_SPORT2_STAT(val) bfin_write16(SPORT2_STAT, val)
-#define bfin_read_SPORT2_CHNL() bfin_read16(SPORT2_CHNL)
-#define bfin_write_SPORT2_CHNL(val) bfin_write16(SPORT2_CHNL, val)
-#define bfin_read_SPORT2_MCMC1() bfin_read16(SPORT2_MCMC1)
-#define bfin_write_SPORT2_MCMC1(val) bfin_write16(SPORT2_MCMC1, val)
-#define bfin_read_SPORT2_MCMC2() bfin_read16(SPORT2_MCMC2)
-#define bfin_write_SPORT2_MCMC2(val) bfin_write16(SPORT2_MCMC2, val)
-#define bfin_read_SPORT2_MTCS0() bfin_read32(SPORT2_MTCS0)
-#define bfin_write_SPORT2_MTCS0(val) bfin_write32(SPORT2_MTCS0, val)
-#define bfin_read_SPORT2_MTCS1() bfin_read32(SPORT2_MTCS1)
-#define bfin_write_SPORT2_MTCS1(val) bfin_write32(SPORT2_MTCS1, val)
-#define bfin_read_SPORT2_MTCS2() bfin_read32(SPORT2_MTCS2)
-#define bfin_write_SPORT2_MTCS2(val) bfin_write32(SPORT2_MTCS2, val)
-#define bfin_read_SPORT2_MTCS3() bfin_read32(SPORT2_MTCS3)
-#define bfin_write_SPORT2_MTCS3(val) bfin_write32(SPORT2_MTCS3, val)
-#define bfin_read_SPORT2_MRCS0() bfin_read32(SPORT2_MRCS0)
-#define bfin_write_SPORT2_MRCS0(val) bfin_write32(SPORT2_MRCS0, val)
-#define bfin_read_SPORT2_MRCS1() bfin_read32(SPORT2_MRCS1)
-#define bfin_write_SPORT2_MRCS1(val) bfin_write32(SPORT2_MRCS1, val)
-#define bfin_read_SPORT2_MRCS2() bfin_read32(SPORT2_MRCS2)
-#define bfin_write_SPORT2_MRCS2(val) bfin_write32(SPORT2_MRCS2, val)
-#define bfin_read_SPORT2_MRCS3() bfin_read32(SPORT2_MRCS3)
-#define bfin_write_SPORT2_MRCS3(val) bfin_write32(SPORT2_MRCS3, val)
-#define bfin_read_SPORT3_TCR1() bfin_read16(SPORT3_TCR1)
-#define bfin_write_SPORT3_TCR1(val) bfin_write16(SPORT3_TCR1, val)
-#define bfin_read_SPORT3_TCR2() bfin_read16(SPORT3_TCR2)
-#define bfin_write_SPORT3_TCR2(val) bfin_write16(SPORT3_TCR2, val)
-#define bfin_read_SPORT3_TCLKDIV() bfin_read16(SPORT3_TCLKDIV)
-#define bfin_write_SPORT3_TCLKDIV(val) bfin_write16(SPORT3_TCLKDIV, val)
-#define bfin_read_SPORT3_TFSDIV() bfin_read16(SPORT3_TFSDIV)
-#define bfin_write_SPORT3_TFSDIV(val) bfin_write16(SPORT3_TFSDIV, val)
-#define bfin_read_SPORT3_TX() bfin_read32(SPORT3_TX)
-#define bfin_write_SPORT3_TX(val) bfin_write32(SPORT3_TX, val)
-#define bfin_read_SPORT3_RX() bfin_read32(SPORT3_RX)
-#define bfin_write_SPORT3_RX(val) bfin_write32(SPORT3_RX, val)
-#define bfin_read_SPORT3_RCR1() bfin_read16(SPORT3_RCR1)
-#define bfin_write_SPORT3_RCR1(val) bfin_write16(SPORT3_RCR1, val)
-#define bfin_read_SPORT3_RCR2() bfin_read16(SPORT3_RCR2)
-#define bfin_write_SPORT3_RCR2(val) bfin_write16(SPORT3_RCR2, val)
-#define bfin_read_SPORT3_RCLKDIV() bfin_read16(SPORT3_RCLKDIV)
-#define bfin_write_SPORT3_RCLKDIV(val) bfin_write16(SPORT3_RCLKDIV, val)
-#define bfin_read_SPORT3_RFSDIV() bfin_read16(SPORT3_RFSDIV)
-#define bfin_write_SPORT3_RFSDIV(val) bfin_write16(SPORT3_RFSDIV, val)
-#define bfin_read_SPORT3_STAT() bfin_read16(SPORT3_STAT)
-#define bfin_write_SPORT3_STAT(val) bfin_write16(SPORT3_STAT, val)
-#define bfin_read_SPORT3_CHNL() bfin_read16(SPORT3_CHNL)
-#define bfin_write_SPORT3_CHNL(val) bfin_write16(SPORT3_CHNL, val)
-#define bfin_read_SPORT3_MCMC1() bfin_read16(SPORT3_MCMC1)
-#define bfin_write_SPORT3_MCMC1(val) bfin_write16(SPORT3_MCMC1, val)
-#define bfin_read_SPORT3_MCMC2() bfin_read16(SPORT3_MCMC2)
-#define bfin_write_SPORT3_MCMC2(val) bfin_write16(SPORT3_MCMC2, val)
-#define bfin_read_SPORT3_MTCS0() bfin_read32(SPORT3_MTCS0)
-#define bfin_write_SPORT3_MTCS0(val) bfin_write32(SPORT3_MTCS0, val)
-#define bfin_read_SPORT3_MTCS1() bfin_read32(SPORT3_MTCS1)
-#define bfin_write_SPORT3_MTCS1(val) bfin_write32(SPORT3_MTCS1, val)
-#define bfin_read_SPORT3_MTCS2() bfin_read32(SPORT3_MTCS2)
-#define bfin_write_SPORT3_MTCS2(val) bfin_write32(SPORT3_MTCS2, val)
-#define bfin_read_SPORT3_MTCS3() bfin_read32(SPORT3_MTCS3)
-#define bfin_write_SPORT3_MTCS3(val) bfin_write32(SPORT3_MTCS3, val)
-#define bfin_read_SPORT3_MRCS0() bfin_read32(SPORT3_MRCS0)
-#define bfin_write_SPORT3_MRCS0(val) bfin_write32(SPORT3_MRCS0, val)
-#define bfin_read_SPORT3_MRCS1() bfin_read32(SPORT3_MRCS1)
-#define bfin_write_SPORT3_MRCS1(val) bfin_write32(SPORT3_MRCS1, val)
-#define bfin_read_SPORT3_MRCS2() bfin_read32(SPORT3_MRCS2)
-#define bfin_write_SPORT3_MRCS2(val) bfin_write32(SPORT3_MRCS2, val)
-#define bfin_read_SPORT3_MRCS3() bfin_read32(SPORT3_MRCS3)
-#define bfin_write_SPORT3_MRCS3(val) bfin_write32(SPORT3_MRCS3, val)
-#define bfin_read_PORTFIO() bfin_read16(PORTFIO)
-#define bfin_write_PORTFIO(val) bfin_write16(PORTFIO, val)
-#define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR)
-#define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR, val)
-#define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET)
-#define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET, val)
-#define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE)
-#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val)
-#define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA)
-#define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA, val)
-#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR)
-#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val)
-#define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET)
-#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val)
-#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE)
-#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB)
-#define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB, val)
-#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR)
-#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val)
-#define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET)
-#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val)
-#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE)
-#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR)
-#define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR, val)
-#define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR)
-#define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR, val)
-#define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE)
-#define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE, val)
-#define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH)
-#define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH, val)
-#define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN)
-#define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN, val)
-#define bfin_read_PORTCIO_FER() bfin_read16(PORTCIO_FER)
-#define bfin_write_PORTCIO_FER(val) bfin_write16(PORTCIO_FER, val)
-#define bfin_read_PORTCIO() bfin_read16(PORTCIO)
-#define bfin_write_PORTCIO(val) bfin_write16(PORTCIO, val)
-#define bfin_read_PORTCIO_CLEAR() bfin_read16(PORTCIO_CLEAR)
-#define bfin_write_PORTCIO_CLEAR(val) bfin_write16(PORTCIO_CLEAR, val)
-#define bfin_read_PORTCIO_SET() bfin_read16(PORTCIO_SET)
-#define bfin_write_PORTCIO_SET(val) bfin_write16(PORTCIO_SET, val)
-#define bfin_read_PORTCIO_TOGGLE() bfin_read16(PORTCIO_TOGGLE)
-#define bfin_write_PORTCIO_TOGGLE(val) bfin_write16(PORTCIO_TOGGLE, val)
-#define bfin_read_PORTCIO_DIR() bfin_read16(PORTCIO_DIR)
-#define bfin_write_PORTCIO_DIR(val) bfin_write16(PORTCIO_DIR, val)
-#define bfin_read_PORTCIO_INEN() bfin_read16(PORTCIO_INEN)
-#define bfin_write_PORTCIO_INEN(val) bfin_write16(PORTCIO_INEN, val)
-#define bfin_read_PORTDIO_FER() bfin_read16(PORTDIO_FER)
-#define bfin_write_PORTDIO_FER(val) bfin_write16(PORTDIO_FER, val)
-#define bfin_read_PORTDIO() bfin_read16(PORTDIO)
-#define bfin_write_PORTDIO(val) bfin_write16(PORTDIO, val)
-#define bfin_read_PORTDIO_CLEAR() bfin_read16(PORTDIO_CLEAR)
-#define bfin_write_PORTDIO_CLEAR(val) bfin_write16(PORTDIO_CLEAR, val)
-#define bfin_read_PORTDIO_SET() bfin_read16(PORTDIO_SET)
-#define bfin_write_PORTDIO_SET(val) bfin_write16(PORTDIO_SET, val)
-#define bfin_read_PORTDIO_TOGGLE() bfin_read16(PORTDIO_TOGGLE)
-#define bfin_write_PORTDIO_TOGGLE(val) bfin_write16(PORTDIO_TOGGLE, val)
-#define bfin_read_PORTDIO_DIR() bfin_read16(PORTDIO_DIR)
-#define bfin_write_PORTDIO_DIR(val) bfin_write16(PORTDIO_DIR, val)
-#define bfin_read_PORTDIO_INEN() bfin_read16(PORTDIO_INEN)
-#define bfin_write_PORTDIO_INEN(val) bfin_write16(PORTDIO_INEN, val)
-#define bfin_read_PORTEIO_FER() bfin_read16(PORTEIO_FER)
-#define bfin_write_PORTEIO_FER(val) bfin_write16(PORTEIO_FER, val)
-#define bfin_read_PORTEIO() bfin_read16(PORTEIO)
-#define bfin_write_PORTEIO(val) bfin_write16(PORTEIO, val)
-#define bfin_read_PORTEIO_CLEAR() bfin_read16(PORTEIO_CLEAR)
-#define bfin_write_PORTEIO_CLEAR(val) bfin_write16(PORTEIO_CLEAR, val)
-#define bfin_read_PORTEIO_SET() bfin_read16(PORTEIO_SET)
-#define bfin_write_PORTEIO_SET(val) bfin_write16(PORTEIO_SET, val)
-#define bfin_read_PORTEIO_TOGGLE() bfin_read16(PORTEIO_TOGGLE)
-#define bfin_write_PORTEIO_TOGGLE(val) bfin_write16(PORTEIO_TOGGLE, val)
-#define bfin_read_PORTEIO_DIR() bfin_read16(PORTEIO_DIR)
-#define bfin_write_PORTEIO_DIR(val) bfin_write16(PORTEIO_DIR, val)
-#define bfin_read_PORTEIO_INEN() bfin_read16(PORTEIO_INEN)
-#define bfin_write_PORTEIO_INEN(val) bfin_write16(PORTEIO_INEN, val)
-#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val)
-#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
-#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
-#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
-#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val)
-#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL)
-#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val)
-#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
-#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val)
-#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
-#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val)
-#define bfin_read_DMAC0_TC_PER() bfin_read16(DMAC0_TC_PER)
-#define bfin_write_DMAC0_TC_PER(val) bfin_write16(DMAC0_TC_PER, val)
-#define bfin_read_DMAC0_TC_CNT() bfin_read16(DMAC0_TC_CNT)
-#define bfin_write_DMAC0_TC_CNT(val) bfin_write16(DMAC0_TC_CNT, val)
-#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
-#define bfin_read_DMA0_START_ADDR() bfin_readPTR(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
-#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
-#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val)
-#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
-#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val)
-#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val)
-#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
-#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val)
-#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val)
-#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
-#define bfin_read_DMA0_CURR_ADDR() bfin_readPTR(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
-#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
-#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
-#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
-#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
-#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
-#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
-#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
-#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_START_ADDR() bfin_readPTR(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
-#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
-#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val)
-#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
-#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val)
-#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val)
-#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
-#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val)
-#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val)
-#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_CURR_ADDR() bfin_readPTR(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)
-#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
-#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
-#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
-#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
-#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
-#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
-#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_START_ADDR() bfin_readPTR(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)
-#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
-#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val)
-#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
-#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val)
-#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val)
-#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
-#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val)
-#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val)
-#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_CURR_ADDR() bfin_readPTR(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)
-#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
-#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
-#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
-#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
-#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
-#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
-#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
-#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)
-#define bfin_read_DMA3_START_ADDR() bfin_readPTR(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)
-#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
-#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val)
-#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
-#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val)
-#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val)
-#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
-#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val)
-#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val)
-#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)
-#define bfin_read_DMA3_CURR_ADDR() bfin_readPTR(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)
-#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
-#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
-#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
-#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
-#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
-#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
-#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
-#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
-#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)
-#define bfin_read_DMA4_START_ADDR() bfin_readPTR(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
-#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
-#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val)
-#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
-#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val)
-#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val)
-#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
-#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val)
-#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val)
-#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)
-#define bfin_read_DMA4_CURR_ADDR() bfin_readPTR(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)
-#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
-#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
-#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
-#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
-#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
-#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
-#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
-#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
-#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
-#define bfin_read_DMA5_START_ADDR() bfin_readPTR(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
-#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
-#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
-#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
-#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val)
-#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val)
-#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
-#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
-#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val)
-#define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val)
-#define bfin_read_DMA5_CURR_ADDR() bfin_readPTR(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val)
-#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
-#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
-#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
-#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
-#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
-#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
-#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
-#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
-#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_readPTR(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_writePTR(DMA6_NEXT_DESC_PTR, val)
-#define bfin_read_DMA6_START_ADDR() bfin_readPTR(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val)
-#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
-#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val)
-#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
-#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val)
-#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val)
-#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
-#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val)
-#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val)
-#define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val)
-#define bfin_read_DMA6_CURR_ADDR() bfin_readPTR(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val)
-#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
-#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
-#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
-#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
-#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
-#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
-#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
-#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
-#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val)
-#define bfin_read_DMA7_START_ADDR() bfin_readPTR(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val)
-#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
-#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val)
-#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
-#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val)
-#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val)
-#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
-#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val)
-#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val)
-#define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val)
-#define bfin_read_DMA7_CURR_ADDR() bfin_readPTR(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val)
-#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
-#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
-#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
-#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
-#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
-#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
-#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
-#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
-#define bfin_read_DMAC1_TC_PER() bfin_read16(DMAC1_TC_PER)
-#define bfin_write_DMAC1_TC_PER(val) bfin_write16(DMAC1_TC_PER, val)
-#define bfin_read_DMAC1_TC_CNT() bfin_read16(DMAC1_TC_CNT)
-#define bfin_write_DMAC1_TC_CNT(val) bfin_write16(DMAC1_TC_CNT, val)
-#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR)
-#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
-#define bfin_read_DMA8_START_ADDR() bfin_readPTR(DMA8_START_ADDR)
-#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val)
-#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG)
-#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val)
-#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT)
-#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val)
-#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY)
-#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val)
-#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT)
-#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val)
-#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY)
-#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val)
-#define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR)
-#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val)
-#define bfin_read_DMA8_CURR_ADDR() bfin_readPTR(DMA8_CURR_ADDR)
-#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val)
-#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
-#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
-#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
-#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
-#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT)
-#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
-#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT)
-#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
-#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR)
-#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val)
-#define bfin_read_DMA9_START_ADDR() bfin_readPTR(DMA9_START_ADDR)
-#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val)
-#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG)
-#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val)
-#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT)
-#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val)
-#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY)
-#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val)
-#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT)
-#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val)
-#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY)
-#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val)
-#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR)
-#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)
-#define bfin_read_DMA9_CURR_ADDR() bfin_readPTR(DMA9_CURR_ADDR)
-#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)
-#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS)
-#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
-#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
-#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
-#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT)
-#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
-#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT)
-#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
-#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR)
-#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)
-#define bfin_read_DMA10_START_ADDR() bfin_readPTR(DMA10_START_ADDR)
-#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)
-#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG)
-#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val)
-#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT)
-#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val)
-#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY)
-#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
-#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT)
-#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val)
-#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY)
-#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
-#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR)
-#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)
-#define bfin_read_DMA10_CURR_ADDR() bfin_readPTR(DMA10_CURR_ADDR)
-#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)
-#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS)
-#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
-#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
-#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
-#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
-#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
-#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
-#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
-#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR)
-#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)
-#define bfin_read_DMA11_START_ADDR() bfin_readPTR(DMA11_START_ADDR)
-#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)
-#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG)
-#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val)
-#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT)
-#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val)
-#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY)
-#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
-#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT)
-#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val)
-#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY)
-#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
-#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR)
-#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)
-#define bfin_read_DMA11_CURR_ADDR() bfin_readPTR(DMA11_CURR_ADDR)
-#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)
-#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS)
-#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
-#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
-#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
-#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
-#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
-#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
-#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
-#define bfin_read_DMA12_NEXT_DESC_PTR() bfin_readPTR(DMA12_NEXT_DESC_PTR)
-#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_writePTR(DMA12_NEXT_DESC_PTR, val)
-#define bfin_read_DMA12_START_ADDR() bfin_readPTR(DMA12_START_ADDR)
-#define bfin_write_DMA12_START_ADDR(val) bfin_writePTR(DMA12_START_ADDR, val)
-#define bfin_read_DMA12_CONFIG() bfin_read16(DMA12_CONFIG)
-#define bfin_write_DMA12_CONFIG(val) bfin_write16(DMA12_CONFIG, val)
-#define bfin_read_DMA12_X_COUNT() bfin_read16(DMA12_X_COUNT)
-#define bfin_write_DMA12_X_COUNT(val) bfin_write16(DMA12_X_COUNT, val)
-#define bfin_read_DMA12_X_MODIFY() bfin_read16(DMA12_X_MODIFY)
-#define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val)
-#define bfin_read_DMA12_Y_COUNT() bfin_read16(DMA12_Y_COUNT)
-#define bfin_write_DMA12_Y_COUNT(val) bfin_write16(DMA12_Y_COUNT, val)
-#define bfin_read_DMA12_Y_MODIFY() bfin_read16(DMA12_Y_MODIFY)
-#define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val)
-#define bfin_read_DMA12_CURR_DESC_PTR() bfin_readPTR(DMA12_CURR_DESC_PTR)
-#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_writePTR(DMA12_CURR_DESC_PTR, val)
-#define bfin_read_DMA12_CURR_ADDR() bfin_readPTR(DMA12_CURR_ADDR)
-#define bfin_write_DMA12_CURR_ADDR(val) bfin_writePTR(DMA12_CURR_ADDR, val)
-#define bfin_read_DMA12_IRQ_STATUS() bfin_read16(DMA12_IRQ_STATUS)
-#define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val)
-#define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP)
-#define bfin_write_DMA12_PERIPHERAL_MAP(val) bfin_write16(DMA12_PERIPHERAL_MAP, val)
-#define bfin_read_DMA12_CURR_X_COUNT() bfin_read16(DMA12_CURR_X_COUNT)
-#define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write16(DMA12_CURR_X_COUNT, val)
-#define bfin_read_DMA12_CURR_Y_COUNT() bfin_read16(DMA12_CURR_Y_COUNT)
-#define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write16(DMA12_CURR_Y_COUNT, val)
-#define bfin_read_DMA13_NEXT_DESC_PTR() bfin_readPTR(DMA13_NEXT_DESC_PTR)
-#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_writePTR(DMA13_NEXT_DESC_PTR, val)
-#define bfin_read_DMA13_START_ADDR() bfin_readPTR(DMA13_START_ADDR)
-#define bfin_write_DMA13_START_ADDR(val) bfin_writePTR(DMA13_START_ADDR, val)
-#define bfin_read_DMA13_CONFIG() bfin_read16(DMA13_CONFIG)
-#define bfin_write_DMA13_CONFIG(val) bfin_write16(DMA13_CONFIG, val)
-#define bfin_read_DMA13_X_COUNT() bfin_read16(DMA13_X_COUNT)
-#define bfin_write_DMA13_X_COUNT(val) bfin_write16(DMA13_X_COUNT, val)
-#define bfin_read_DMA13_X_MODIFY() bfin_read16(DMA13_X_MODIFY)
-#define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val)
-#define bfin_read_DMA13_Y_COUNT() bfin_read16(DMA13_Y_COUNT)
-#define bfin_write_DMA13_Y_COUNT(val) bfin_write16(DMA13_Y_COUNT, val)
-#define bfin_read_DMA13_Y_MODIFY() bfin_read16(DMA13_Y_MODIFY)
-#define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val)
-#define bfin_read_DMA13_CURR_DESC_PTR() bfin_readPTR(DMA13_CURR_DESC_PTR)
-#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_writePTR(DMA13_CURR_DESC_PTR, val)
-#define bfin_read_DMA13_CURR_ADDR() bfin_readPTR(DMA13_CURR_ADDR)
-#define bfin_write_DMA13_CURR_ADDR(val) bfin_writePTR(DMA13_CURR_ADDR, val)
-#define bfin_read_DMA13_IRQ_STATUS() bfin_read16(DMA13_IRQ_STATUS)
-#define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val)
-#define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP)
-#define bfin_write_DMA13_PERIPHERAL_MAP(val) bfin_write16(DMA13_PERIPHERAL_MAP, val)
-#define bfin_read_DMA13_CURR_X_COUNT() bfin_read16(DMA13_CURR_X_COUNT)
-#define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write16(DMA13_CURR_X_COUNT, val)
-#define bfin_read_DMA13_CURR_Y_COUNT() bfin_read16(DMA13_CURR_Y_COUNT)
-#define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write16(DMA13_CURR_Y_COUNT, val)
-#define bfin_read_DMA14_NEXT_DESC_PTR() bfin_readPTR(DMA14_NEXT_DESC_PTR)
-#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_writePTR(DMA14_NEXT_DESC_PTR, val)
-#define bfin_read_DMA14_START_ADDR() bfin_readPTR(DMA14_START_ADDR)
-#define bfin_write_DMA14_START_ADDR(val) bfin_writePTR(DMA14_START_ADDR, val)
-#define bfin_read_DMA14_CONFIG() bfin_read16(DMA14_CONFIG)
-#define bfin_write_DMA14_CONFIG(val) bfin_write16(DMA14_CONFIG, val)
-#define bfin_read_DMA14_X_COUNT() bfin_read16(DMA14_X_COUNT)
-#define bfin_write_DMA14_X_COUNT(val) bfin_write16(DMA14_X_COUNT, val)
-#define bfin_read_DMA14_X_MODIFY() bfin_read16(DMA14_X_MODIFY)
-#define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val)
-#define bfin_read_DMA14_Y_COUNT() bfin_read16(DMA14_Y_COUNT)
-#define bfin_write_DMA14_Y_COUNT(val) bfin_write16(DMA14_Y_COUNT, val)
-#define bfin_read_DMA14_Y_MODIFY() bfin_read16(DMA14_Y_MODIFY)
-#define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val)
-#define bfin_read_DMA14_CURR_DESC_PTR() bfin_readPTR(DMA14_CURR_DESC_PTR)
-#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_writePTR(DMA14_CURR_DESC_PTR, val)
-#define bfin_read_DMA14_CURR_ADDR() bfin_readPTR(DMA14_CURR_ADDR)
-#define bfin_write_DMA14_CURR_ADDR(val) bfin_writePTR(DMA14_CURR_ADDR, val)
-#define bfin_read_DMA14_IRQ_STATUS() bfin_read16(DMA14_IRQ_STATUS)
-#define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val)
-#define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP)
-#define bfin_write_DMA14_PERIPHERAL_MAP(val) bfin_write16(DMA14_PERIPHERAL_MAP, val)
-#define bfin_read_DMA14_CURR_X_COUNT() bfin_read16(DMA14_CURR_X_COUNT)
-#define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write16(DMA14_CURR_X_COUNT, val)
-#define bfin_read_DMA14_CURR_Y_COUNT() bfin_read16(DMA14_CURR_Y_COUNT)
-#define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write16(DMA14_CURR_Y_COUNT, val)
-#define bfin_read_DMA15_NEXT_DESC_PTR() bfin_readPTR(DMA15_NEXT_DESC_PTR)
-#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_writePTR(DMA15_NEXT_DESC_PTR, val)
-#define bfin_read_DMA15_START_ADDR() bfin_readPTR(DMA15_START_ADDR)
-#define bfin_write_DMA15_START_ADDR(val) bfin_writePTR(DMA15_START_ADDR, val)
-#define bfin_read_DMA15_CONFIG() bfin_read16(DMA15_CONFIG)
-#define bfin_write_DMA15_CONFIG(val) bfin_write16(DMA15_CONFIG, val)
-#define bfin_read_DMA15_X_COUNT() bfin_read16(DMA15_X_COUNT)
-#define bfin_write_DMA15_X_COUNT(val) bfin_write16(DMA15_X_COUNT, val)
-#define bfin_read_DMA15_X_MODIFY() bfin_read16(DMA15_X_MODIFY)
-#define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val)
-#define bfin_read_DMA15_Y_COUNT() bfin_read16(DMA15_Y_COUNT)
-#define bfin_write_DMA15_Y_COUNT(val) bfin_write16(DMA15_Y_COUNT, val)
-#define bfin_read_DMA15_Y_MODIFY() bfin_read16(DMA15_Y_MODIFY)
-#define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val)
-#define bfin_read_DMA15_CURR_DESC_PTR() bfin_readPTR(DMA15_CURR_DESC_PTR)
-#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_writePTR(DMA15_CURR_DESC_PTR, val)
-#define bfin_read_DMA15_CURR_ADDR() bfin_readPTR(DMA15_CURR_ADDR)
-#define bfin_write_DMA15_CURR_ADDR(val) bfin_writePTR(DMA15_CURR_ADDR, val)
-#define bfin_read_DMA15_IRQ_STATUS() bfin_read16(DMA15_IRQ_STATUS)
-#define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val)
-#define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP)
-#define bfin_write_DMA15_PERIPHERAL_MAP(val) bfin_write16(DMA15_PERIPHERAL_MAP, val)
-#define bfin_read_DMA15_CURR_X_COUNT() bfin_read16(DMA15_CURR_X_COUNT)
-#define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write16(DMA15_CURR_X_COUNT, val)
-#define bfin_read_DMA15_CURR_Y_COUNT() bfin_read16(DMA15_CURR_Y_COUNT)
-#define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write16(DMA15_CURR_Y_COUNT, val)
-#define bfin_read_DMA16_NEXT_DESC_PTR() bfin_readPTR(DMA16_NEXT_DESC_PTR)
-#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_writePTR(DMA16_NEXT_DESC_PTR, val)
-#define bfin_read_DMA16_START_ADDR() bfin_readPTR(DMA16_START_ADDR)
-#define bfin_write_DMA16_START_ADDR(val) bfin_writePTR(DMA16_START_ADDR, val)
-#define bfin_read_DMA16_CONFIG() bfin_read16(DMA16_CONFIG)
-#define bfin_write_DMA16_CONFIG(val) bfin_write16(DMA16_CONFIG, val)
-#define bfin_read_DMA16_X_COUNT() bfin_read16(DMA16_X_COUNT)
-#define bfin_write_DMA16_X_COUNT(val) bfin_write16(DMA16_X_COUNT, val)
-#define bfin_read_DMA16_X_MODIFY() bfin_read16(DMA16_X_MODIFY)
-#define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val)
-#define bfin_read_DMA16_Y_COUNT() bfin_read16(DMA16_Y_COUNT)
-#define bfin_write_DMA16_Y_COUNT(val) bfin_write16(DMA16_Y_COUNT, val)
-#define bfin_read_DMA16_Y_MODIFY() bfin_read16(DMA16_Y_MODIFY)
-#define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val)
-#define bfin_read_DMA16_CURR_DESC_PTR() bfin_readPTR(DMA16_CURR_DESC_PTR)
-#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_writePTR(DMA16_CURR_DESC_PTR, val)
-#define bfin_read_DMA16_CURR_ADDR() bfin_readPTR(DMA16_CURR_ADDR)
-#define bfin_write_DMA16_CURR_ADDR(val) bfin_writePTR(DMA16_CURR_ADDR, val)
-#define bfin_read_DMA16_IRQ_STATUS() bfin_read16(DMA16_IRQ_STATUS)
-#define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val)
-#define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP)
-#define bfin_write_DMA16_PERIPHERAL_MAP(val) bfin_write16(DMA16_PERIPHERAL_MAP, val)
-#define bfin_read_DMA16_CURR_X_COUNT() bfin_read16(DMA16_CURR_X_COUNT)
-#define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write16(DMA16_CURR_X_COUNT, val)
-#define bfin_read_DMA16_CURR_Y_COUNT() bfin_read16(DMA16_CURR_Y_COUNT)
-#define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write16(DMA16_CURR_Y_COUNT, val)
-#define bfin_read_DMA17_NEXT_DESC_PTR() bfin_readPTR(DMA17_NEXT_DESC_PTR)
-#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_writePTR(DMA17_NEXT_DESC_PTR, val)
-#define bfin_read_DMA17_START_ADDR() bfin_readPTR(DMA17_START_ADDR)
-#define bfin_write_DMA17_START_ADDR(val) bfin_writePTR(DMA17_START_ADDR, val)
-#define bfin_read_DMA17_CONFIG() bfin_read16(DMA17_CONFIG)
-#define bfin_write_DMA17_CONFIG(val) bfin_write16(DMA17_CONFIG, val)
-#define bfin_read_DMA17_X_COUNT() bfin_read16(DMA17_X_COUNT)
-#define bfin_write_DMA17_X_COUNT(val) bfin_write16(DMA17_X_COUNT, val)
-#define bfin_read_DMA17_X_MODIFY() bfin_read16(DMA17_X_MODIFY)
-#define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val)
-#define bfin_read_DMA17_Y_COUNT() bfin_read16(DMA17_Y_COUNT)
-#define bfin_write_DMA17_Y_COUNT(val) bfin_write16(DMA17_Y_COUNT, val)
-#define bfin_read_DMA17_Y_MODIFY() bfin_read16(DMA17_Y_MODIFY)
-#define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val)
-#define bfin_read_DMA17_CURR_DESC_PTR() bfin_readPTR(DMA17_CURR_DESC_PTR)
-#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_writePTR(DMA17_CURR_DESC_PTR, val)
-#define bfin_read_DMA17_CURR_ADDR() bfin_readPTR(DMA17_CURR_ADDR)
-#define bfin_write_DMA17_CURR_ADDR(val) bfin_writePTR(DMA17_CURR_ADDR, val)
-#define bfin_read_DMA17_IRQ_STATUS() bfin_read16(DMA17_IRQ_STATUS)
-#define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val)
-#define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP)
-#define bfin_write_DMA17_PERIPHERAL_MAP(val) bfin_write16(DMA17_PERIPHERAL_MAP, val)
-#define bfin_read_DMA17_CURR_X_COUNT() bfin_read16(DMA17_CURR_X_COUNT)
-#define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write16(DMA17_CURR_X_COUNT, val)
-#define bfin_read_DMA17_CURR_Y_COUNT() bfin_read16(DMA17_CURR_Y_COUNT)
-#define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write16(DMA17_CURR_Y_COUNT, val)
-#define bfin_read_DMA18_NEXT_DESC_PTR() bfin_readPTR(DMA18_NEXT_DESC_PTR)
-#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_writePTR(DMA18_NEXT_DESC_PTR, val)
-#define bfin_read_DMA18_START_ADDR() bfin_readPTR(DMA18_START_ADDR)
-#define bfin_write_DMA18_START_ADDR(val) bfin_writePTR(DMA18_START_ADDR, val)
-#define bfin_read_DMA18_CONFIG() bfin_read16(DMA18_CONFIG)
-#define bfin_write_DMA18_CONFIG(val) bfin_write16(DMA18_CONFIG, val)
-#define bfin_read_DMA18_X_COUNT() bfin_read16(DMA18_X_COUNT)
-#define bfin_write_DMA18_X_COUNT(val) bfin_write16(DMA18_X_COUNT, val)
-#define bfin_read_DMA18_X_MODIFY() bfin_read16(DMA18_X_MODIFY)
-#define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val)
-#define bfin_read_DMA18_Y_COUNT() bfin_read16(DMA18_Y_COUNT)
-#define bfin_write_DMA18_Y_COUNT(val) bfin_write16(DMA18_Y_COUNT, val)
-#define bfin_read_DMA18_Y_MODIFY() bfin_read16(DMA18_Y_MODIFY)
-#define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val)
-#define bfin_read_DMA18_CURR_DESC_PTR() bfin_readPTR(DMA18_CURR_DESC_PTR)
-#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_writePTR(DMA18_CURR_DESC_PTR, val)
-#define bfin_read_DMA18_CURR_ADDR() bfin_readPTR(DMA18_CURR_ADDR)
-#define bfin_write_DMA18_CURR_ADDR(val) bfin_writePTR(DMA18_CURR_ADDR, val)
-#define bfin_read_DMA18_IRQ_STATUS() bfin_read16(DMA18_IRQ_STATUS)
-#define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val)
-#define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP)
-#define bfin_write_DMA18_PERIPHERAL_MAP(val) bfin_write16(DMA18_PERIPHERAL_MAP, val)
-#define bfin_read_DMA18_CURR_X_COUNT() bfin_read16(DMA18_CURR_X_COUNT)
-#define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write16(DMA18_CURR_X_COUNT, val)
-#define bfin_read_DMA18_CURR_Y_COUNT() bfin_read16(DMA18_CURR_Y_COUNT)
-#define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write16(DMA18_CURR_Y_COUNT, val)
-#define bfin_read_DMA19_NEXT_DESC_PTR() bfin_readPTR(DMA19_NEXT_DESC_PTR)
-#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_writePTR(DMA19_NEXT_DESC_PTR, val)
-#define bfin_read_DMA19_START_ADDR() bfin_readPTR(DMA19_START_ADDR)
-#define bfin_write_DMA19_START_ADDR(val) bfin_writePTR(DMA19_START_ADDR, val)
-#define bfin_read_DMA19_CONFIG() bfin_read16(DMA19_CONFIG)
-#define bfin_write_DMA19_CONFIG(val) bfin_write16(DMA19_CONFIG, val)
-#define bfin_read_DMA19_X_COUNT() bfin_read16(DMA19_X_COUNT)
-#define bfin_write_DMA19_X_COUNT(val) bfin_write16(DMA19_X_COUNT, val)
-#define bfin_read_DMA19_X_MODIFY() bfin_read16(DMA19_X_MODIFY)
-#define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val)
-#define bfin_read_DMA19_Y_COUNT() bfin_read16(DMA19_Y_COUNT)
-#define bfin_write_DMA19_Y_COUNT(val) bfin_write16(DMA19_Y_COUNT, val)
-#define bfin_read_DMA19_Y_MODIFY() bfin_read16(DMA19_Y_MODIFY)
-#define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val)
-#define bfin_read_DMA19_CURR_DESC_PTR() bfin_readPTR(DMA19_CURR_DESC_PTR)
-#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_writePTR(DMA19_CURR_DESC_PTR, val)
-#define bfin_read_DMA19_CURR_ADDR() bfin_readPTR(DMA19_CURR_ADDR)
-#define bfin_write_DMA19_CURR_ADDR(val) bfin_writePTR(DMA19_CURR_ADDR, val)
-#define bfin_read_DMA19_IRQ_STATUS() bfin_read16(DMA19_IRQ_STATUS)
-#define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val)
-#define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP)
-#define bfin_write_DMA19_PERIPHERAL_MAP(val) bfin_write16(DMA19_PERIPHERAL_MAP, val)
-#define bfin_read_DMA19_CURR_X_COUNT() bfin_read16(DMA19_CURR_X_COUNT)
-#define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val)
-#define bfin_read_DMA19_CURR_Y_COUNT() bfin_read16(DMA19_CURR_Y_COUNT)
-#define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR)
-#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val)
-#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
-#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
-#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
-#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
-#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
-#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
-#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
-#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
-#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
-#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
-#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D0_CURR_ADDR() bfin_readPTR(MDMA_D0_CURR_ADDR)
-#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val)
-#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
-#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
-#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
-#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR)
-#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val)
-#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
-#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
-#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
-#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
-#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
-#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
-#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
-#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
-#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
-#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
-#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S0_CURR_ADDR() bfin_readPTR(MDMA_S0_CURR_ADDR)
-#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val)
-#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
-#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
-#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
-#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR)
-#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val)
-#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
-#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
-#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
-#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
-#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
-#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
-#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
-#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
-#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
-#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
-#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D1_CURR_ADDR() bfin_readPTR(MDMA_D1_CURR_ADDR)
-#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val)
-#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
-#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
-#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
-#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR)
-#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val)
-#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
-#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
-#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
-#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
-#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
-#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
-#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
-#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
-#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
-#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
-#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S1_CURR_ADDR() bfin_readPTR(MDMA_S1_CURR_ADDR)
-#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val)
-#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
-#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
-#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
-#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_readPTR(MDMA_D2_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D2_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D2_START_ADDR() bfin_readPTR(MDMA_D2_START_ADDR)
-#define bfin_write_MDMA_D2_START_ADDR(val) bfin_writePTR(MDMA_D2_START_ADDR, val)
-#define bfin_read_MDMA_D2_CONFIG() bfin_read16(MDMA_D2_CONFIG)
-#define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val)
-#define bfin_read_MDMA_D2_X_COUNT() bfin_read16(MDMA_D2_X_COUNT)
-#define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val)
-#define bfin_read_MDMA_D2_X_MODIFY() bfin_read16(MDMA_D2_X_MODIFY)
-#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY, val)
-#define bfin_read_MDMA_D2_Y_COUNT() bfin_read16(MDMA_D2_Y_COUNT)
-#define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val)
-#define bfin_read_MDMA_D2_Y_MODIFY() bfin_read16(MDMA_D2_Y_MODIFY)
-#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY, val)
-#define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_readPTR(MDMA_D2_CURR_DESC_PTR)
-#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D2_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D2_CURR_ADDR() bfin_readPTR(MDMA_D2_CURR_ADDR)
-#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_writePTR(MDMA_D2_CURR_ADDR, val)
-#define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS)
-#define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val)
-#define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT)
-#define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT)
-#define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_readPTR(MDMA_S2_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S2_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S2_START_ADDR() bfin_readPTR(MDMA_S2_START_ADDR)
-#define bfin_write_MDMA_S2_START_ADDR(val) bfin_writePTR(MDMA_S2_START_ADDR, val)
-#define bfin_read_MDMA_S2_CONFIG() bfin_read16(MDMA_S2_CONFIG)
-#define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val)
-#define bfin_read_MDMA_S2_X_COUNT() bfin_read16(MDMA_S2_X_COUNT)
-#define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val)
-#define bfin_read_MDMA_S2_X_MODIFY() bfin_read16(MDMA_S2_X_MODIFY)
-#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY, val)
-#define bfin_read_MDMA_S2_Y_COUNT() bfin_read16(MDMA_S2_Y_COUNT)
-#define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val)
-#define bfin_read_MDMA_S2_Y_MODIFY() bfin_read16(MDMA_S2_Y_MODIFY)
-#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY, val)
-#define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_readPTR(MDMA_S2_CURR_DESC_PTR)
-#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S2_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S2_CURR_ADDR() bfin_readPTR(MDMA_S2_CURR_ADDR)
-#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_writePTR(MDMA_S2_CURR_ADDR, val)
-#define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS)
-#define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val)
-#define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT)
-#define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT)
-#define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_readPTR(MDMA_D3_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D3_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D3_START_ADDR() bfin_readPTR(MDMA_D3_START_ADDR)
-#define bfin_write_MDMA_D3_START_ADDR(val) bfin_writePTR(MDMA_D3_START_ADDR, val)
-#define bfin_read_MDMA_D3_CONFIG() bfin_read16(MDMA_D3_CONFIG)
-#define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val)
-#define bfin_read_MDMA_D3_X_COUNT() bfin_read16(MDMA_D3_X_COUNT)
-#define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val)
-#define bfin_read_MDMA_D3_X_MODIFY() bfin_read16(MDMA_D3_X_MODIFY)
-#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY, val)
-#define bfin_read_MDMA_D3_Y_COUNT() bfin_read16(MDMA_D3_Y_COUNT)
-#define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val)
-#define bfin_read_MDMA_D3_Y_MODIFY() bfin_read16(MDMA_D3_Y_MODIFY)
-#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY, val)
-#define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_readPTR(MDMA_D3_CURR_DESC_PTR)
-#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D3_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D3_CURR_ADDR() bfin_readPTR(MDMA_D3_CURR_ADDR)
-#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_writePTR(MDMA_D3_CURR_ADDR, val)
-#define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS)
-#define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val)
-#define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT)
-#define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT)
-#define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_readPTR(MDMA_S3_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S3_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S3_START_ADDR() bfin_readPTR(MDMA_S3_START_ADDR)
-#define bfin_write_MDMA_S3_START_ADDR(val) bfin_writePTR(MDMA_S3_START_ADDR, val)
-#define bfin_read_MDMA_S3_CONFIG() bfin_read16(MDMA_S3_CONFIG)
-#define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val)
-#define bfin_read_MDMA_S3_X_COUNT() bfin_read16(MDMA_S3_X_COUNT)
-#define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val)
-#define bfin_read_MDMA_S3_X_MODIFY() bfin_read16(MDMA_S3_X_MODIFY)
-#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY, val)
-#define bfin_read_MDMA_S3_Y_COUNT() bfin_read16(MDMA_S3_Y_COUNT)
-#define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val)
-#define bfin_read_MDMA_S3_Y_MODIFY() bfin_read16(MDMA_S3_Y_MODIFY)
-#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY, val)
-#define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_readPTR(MDMA_S3_CURR_DESC_PTR)
-#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S3_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S3_CURR_ADDR() bfin_readPTR(MDMA_S3_CURR_ADDR)
-#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_writePTR(MDMA_S3_CURR_ADDR, val)
-#define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS)
-#define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val)
-#define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT)
-#define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT)
-#define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT, val)
-#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL)
-#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val)
-#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS)
-#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val)
-#define bfin_clear_PPI_STATUS() bfin_read_PPI_STATUS()
-#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY)
-#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val)
-#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT)
-#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val)
-#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME)
-#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val)
-#define bfin_read_CAN_MC1() bfin_read16(CAN_MC1)
-#define bfin_write_CAN_MC1(val) bfin_write16(CAN_MC1, val)
-#define bfin_read_CAN_MD1() bfin_read16(CAN_MD1)
-#define bfin_write_CAN_MD1(val) bfin_write16(CAN_MD1, val)
-#define bfin_read_CAN_TRS1() bfin_read16(CAN_TRS1)
-#define bfin_write_CAN_TRS1(val) bfin_write16(CAN_TRS1, val)
-#define bfin_read_CAN_TRR1() bfin_read16(CAN_TRR1)
-#define bfin_write_CAN_TRR1(val) bfin_write16(CAN_TRR1, val)
-#define bfin_read_CAN_TA1() bfin_read16(CAN_TA1)
-#define bfin_write_CAN_TA1(val) bfin_write16(CAN_TA1, val)
-#define bfin_read_CAN_AA1() bfin_read16(CAN_AA1)
-#define bfin_write_CAN_AA1(val) bfin_write16(CAN_AA1, val)
-#define bfin_read_CAN_RMP1() bfin_read16(CAN_RMP1)
-#define bfin_write_CAN_RMP1(val) bfin_write16(CAN_RMP1, val)
-#define bfin_read_CAN_RML1() bfin_read16(CAN_RML1)
-#define bfin_write_CAN_RML1(val) bfin_write16(CAN_RML1, val)
-#define bfin_read_CAN_MBTIF1() bfin_read16(CAN_MBTIF1)
-#define bfin_write_CAN_MBTIF1(val) bfin_write16(CAN_MBTIF1, val)
-#define bfin_read_CAN_MBRIF1() bfin_read16(CAN_MBRIF1)
-#define bfin_write_CAN_MBRIF1(val) bfin_write16(CAN_MBRIF1, val)
-#define bfin_read_CAN_MBIM1() bfin_read16(CAN_MBIM1)
-#define bfin_write_CAN_MBIM1(val) bfin_write16(CAN_MBIM1, val)
-#define bfin_read_CAN_RFH1() bfin_read16(CAN_RFH1)
-#define bfin_write_CAN_RFH1(val) bfin_write16(CAN_RFH1, val)
-#define bfin_read_CAN_OPSS1() bfin_read16(CAN_OPSS1)
-#define bfin_write_CAN_OPSS1(val) bfin_write16(CAN_OPSS1, val)
-#define bfin_read_CAN_MC2() bfin_read16(CAN_MC2)
-#define bfin_write_CAN_MC2(val) bfin_write16(CAN_MC2, val)
-#define bfin_read_CAN_MD2() bfin_read16(CAN_MD2)
-#define bfin_write_CAN_MD2(val) bfin_write16(CAN_MD2, val)
-#define bfin_read_CAN_TRS2() bfin_read16(CAN_TRS2)
-#define bfin_write_CAN_TRS2(val) bfin_write16(CAN_TRS2, val)
-#define bfin_read_CAN_TRR2() bfin_read16(CAN_TRR2)
-#define bfin_write_CAN_TRR2(val) bfin_write16(CAN_TRR2, val)
-#define bfin_read_CAN_TA2() bfin_read16(CAN_TA2)
-#define bfin_write_CAN_TA2(val) bfin_write16(CAN_TA2, val)
-#define bfin_read_CAN_AA2() bfin_read16(CAN_AA2)
-#define bfin_write_CAN_AA2(val) bfin_write16(CAN_AA2, val)
-#define bfin_read_CAN_RMP2() bfin_read16(CAN_RMP2)
-#define bfin_write_CAN_RMP2(val) bfin_write16(CAN_RMP2, val)
-#define bfin_read_CAN_RML2() bfin_read16(CAN_RML2)
-#define bfin_write_CAN_RML2(val) bfin_write16(CAN_RML2, val)
-#define bfin_read_CAN_MBTIF2() bfin_read16(CAN_MBTIF2)
-#define bfin_write_CAN_MBTIF2(val) bfin_write16(CAN_MBTIF2, val)
-#define bfin_read_CAN_MBRIF2() bfin_read16(CAN_MBRIF2)
-#define bfin_write_CAN_MBRIF2(val) bfin_write16(CAN_MBRIF2, val)
-#define bfin_read_CAN_MBIM2() bfin_read16(CAN_MBIM2)
-#define bfin_write_CAN_MBIM2(val) bfin_write16(CAN_MBIM2, val)
-#define bfin_read_CAN_RFH2() bfin_read16(CAN_RFH2)
-#define bfin_write_CAN_RFH2(val) bfin_write16(CAN_RFH2, val)
-#define bfin_read_CAN_OPSS2() bfin_read16(CAN_OPSS2)
-#define bfin_write_CAN_OPSS2(val) bfin_write16(CAN_OPSS2, val)
-#define bfin_read_CAN_CLOCK() bfin_read16(CAN_CLOCK)
-#define bfin_write_CAN_CLOCK(val) bfin_write16(CAN_CLOCK, val)
-#define bfin_read_CAN_TIMING() bfin_read16(CAN_TIMING)
-#define bfin_write_CAN_TIMING(val) bfin_write16(CAN_TIMING, val)
-#define bfin_read_CAN_DEBUG() bfin_read16(CAN_DEBUG)
-#define bfin_write_CAN_DEBUG(val) bfin_write16(CAN_DEBUG, val)
-#define bfin_read_CAN_STATUS() bfin_read16(CAN_STATUS)
-#define bfin_write_CAN_STATUS(val) bfin_write16(CAN_STATUS, val)
-#define bfin_read_CAN_CEC() bfin_read16(CAN_CEC)
-#define bfin_write_CAN_CEC(val) bfin_write16(CAN_CEC, val)
-#define bfin_read_CAN_GIS() bfin_read16(CAN_GIS)
-#define bfin_write_CAN_GIS(val) bfin_write16(CAN_GIS, val)
-#define bfin_read_CAN_GIM() bfin_read16(CAN_GIM)
-#define bfin_write_CAN_GIM(val) bfin_write16(CAN_GIM, val)
-#define bfin_read_CAN_GIF() bfin_read16(CAN_GIF)
-#define bfin_write_CAN_GIF(val) bfin_write16(CAN_GIF, val)
-#define bfin_read_CAN_CONTROL() bfin_read16(CAN_CONTROL)
-#define bfin_write_CAN_CONTROL(val) bfin_write16(CAN_CONTROL, val)
-#define bfin_read_CAN_INTR() bfin_read16(CAN_INTR)
-#define bfin_write_CAN_INTR(val) bfin_write16(CAN_INTR, val)
-#define bfin_read_CAN_VERSION() bfin_read16(CAN_VERSION)
-#define bfin_write_CAN_VERSION(val) bfin_write16(CAN_VERSION, val)
-#define bfin_read_CAN_MBTD() bfin_read16(CAN_MBTD)
-#define bfin_write_CAN_MBTD(val) bfin_write16(CAN_MBTD, val)
-#define bfin_read_CAN_EWR() bfin_read16(CAN_EWR)
-#define bfin_write_CAN_EWR(val) bfin_write16(CAN_EWR, val)
-#define bfin_read_CAN_ESR() bfin_read16(CAN_ESR)
-#define bfin_write_CAN_ESR(val) bfin_write16(CAN_ESR, val)
-#define bfin_read_CAN_UCREG() bfin_read16(CAN_UCREG)
-#define bfin_write_CAN_UCREG(val) bfin_write16(CAN_UCREG, val)
-#define bfin_read_CAN_UCCNT() bfin_read16(CAN_UCCNT)
-#define bfin_write_CAN_UCCNT(val) bfin_write16(CAN_UCCNT, val)
-#define bfin_read_CAN_UCRC() bfin_read16(CAN_UCRC)
-#define bfin_write_CAN_UCRC(val) bfin_write16(CAN_UCRC, val)
-#define bfin_read_CAN_UCCNF() bfin_read16(CAN_UCCNF)
-#define bfin_write_CAN_UCCNF(val) bfin_write16(CAN_UCCNF, val)
-#define bfin_read_CAN_VERSION2() bfin_read16(CAN_VERSION2)
-#define bfin_write_CAN_VERSION2(val) bfin_write16(CAN_VERSION2, val)
-#define bfin_read_CAN_AM00L() bfin_read16(CAN_AM00L)
-#define bfin_write_CAN_AM00L(val) bfin_write16(CAN_AM00L, val)
-#define bfin_read_CAN_AM00H() bfin_read16(CAN_AM00H)
-#define bfin_write_CAN_AM00H(val) bfin_write16(CAN_AM00H, val)
-#define bfin_read_CAN_AM01L() bfin_read16(CAN_AM01L)
-#define bfin_write_CAN_AM01L(val) bfin_write16(CAN_AM01L, val)
-#define bfin_read_CAN_AM01H() bfin_read16(CAN_AM01H)
-#define bfin_write_CAN_AM01H(val) bfin_write16(CAN_AM01H, val)
-#define bfin_read_CAN_AM02L() bfin_read16(CAN_AM02L)
-#define bfin_write_CAN_AM02L(val) bfin_write16(CAN_AM02L, val)
-#define bfin_read_CAN_AM02H() bfin_read16(CAN_AM02H)
-#define bfin_write_CAN_AM02H(val) bfin_write16(CAN_AM02H, val)
-#define bfin_read_CAN_AM03L() bfin_read16(CAN_AM03L)
-#define bfin_write_CAN_AM03L(val) bfin_write16(CAN_AM03L, val)
-#define bfin_read_CAN_AM03H() bfin_read16(CAN_AM03H)
-#define bfin_write_CAN_AM03H(val) bfin_write16(CAN_AM03H, val)
-#define bfin_read_CAN_AM04L() bfin_read16(CAN_AM04L)
-#define bfin_write_CAN_AM04L(val) bfin_write16(CAN_AM04L, val)
-#define bfin_read_CAN_AM04H() bfin_read16(CAN_AM04H)
-#define bfin_write_CAN_AM04H(val) bfin_write16(CAN_AM04H, val)
-#define bfin_read_CAN_AM05L() bfin_read16(CAN_AM05L)
-#define bfin_write_CAN_AM05L(val) bfin_write16(CAN_AM05L, val)
-#define bfin_read_CAN_AM05H() bfin_read16(CAN_AM05H)
-#define bfin_write_CAN_AM05H(val) bfin_write16(CAN_AM05H, val)
-#define bfin_read_CAN_AM06L() bfin_read16(CAN_AM06L)
-#define bfin_write_CAN_AM06L(val) bfin_write16(CAN_AM06L, val)
-#define bfin_read_CAN_AM06H() bfin_read16(CAN_AM06H)
-#define bfin_write_CAN_AM06H(val) bfin_write16(CAN_AM06H, val)
-#define bfin_read_CAN_AM07L() bfin_read16(CAN_AM07L)
-#define bfin_write_CAN_AM07L(val) bfin_write16(CAN_AM07L, val)
-#define bfin_read_CAN_AM07H() bfin_read16(CAN_AM07H)
-#define bfin_write_CAN_AM07H(val) bfin_write16(CAN_AM07H, val)
-#define bfin_read_CAN_AM08L() bfin_read16(CAN_AM08L)
-#define bfin_write_CAN_AM08L(val) bfin_write16(CAN_AM08L, val)
-#define bfin_read_CAN_AM08H() bfin_read16(CAN_AM08H)
-#define bfin_write_CAN_AM08H(val) bfin_write16(CAN_AM08H, val)
-#define bfin_read_CAN_AM09L() bfin_read16(CAN_AM09L)
-#define bfin_write_CAN_AM09L(val) bfin_write16(CAN_AM09L, val)
-#define bfin_read_CAN_AM09H() bfin_read16(CAN_AM09H)
-#define bfin_write_CAN_AM09H(val) bfin_write16(CAN_AM09H, val)
-#define bfin_read_CAN_AM10L() bfin_read16(CAN_AM10L)
-#define bfin_write_CAN_AM10L(val) bfin_write16(CAN_AM10L, val)
-#define bfin_read_CAN_AM10H() bfin_read16(CAN_AM10H)
-#define bfin_write_CAN_AM10H(val) bfin_write16(CAN_AM10H, val)
-#define bfin_read_CAN_AM11L() bfin_read16(CAN_AM11L)
-#define bfin_write_CAN_AM11L(val) bfin_write16(CAN_AM11L, val)
-#define bfin_read_CAN_AM11H() bfin_read16(CAN_AM11H)
-#define bfin_write_CAN_AM11H(val) bfin_write16(CAN_AM11H, val)
-#define bfin_read_CAN_AM12L() bfin_read16(CAN_AM12L)
-#define bfin_write_CAN_AM12L(val) bfin_write16(CAN_AM12L, val)
-#define bfin_read_CAN_AM12H() bfin_read16(CAN_AM12H)
-#define bfin_write_CAN_AM12H(val) bfin_write16(CAN_AM12H, val)
-#define bfin_read_CAN_AM13L() bfin_read16(CAN_AM13L)
-#define bfin_write_CAN_AM13L(val) bfin_write16(CAN_AM13L, val)
-#define bfin_read_CAN_AM13H() bfin_read16(CAN_AM13H)
-#define bfin_write_CAN_AM13H(val) bfin_write16(CAN_AM13H, val)
-#define bfin_read_CAN_AM14L() bfin_read16(CAN_AM14L)
-#define bfin_write_CAN_AM14L(val) bfin_write16(CAN_AM14L, val)
-#define bfin_read_CAN_AM14H() bfin_read16(CAN_AM14H)
-#define bfin_write_CAN_AM14H(val) bfin_write16(CAN_AM14H, val)
-#define bfin_read_CAN_AM15L() bfin_read16(CAN_AM15L)
-#define bfin_write_CAN_AM15L(val) bfin_write16(CAN_AM15L, val)
-#define bfin_read_CAN_AM15H() bfin_read16(CAN_AM15H)
-#define bfin_write_CAN_AM15H(val) bfin_write16(CAN_AM15H, val)
-#define bfin_read_CAN_AM16L() bfin_read16(CAN_AM16L)
-#define bfin_write_CAN_AM16L(val) bfin_write16(CAN_AM16L, val)
-#define bfin_read_CAN_AM16H() bfin_read16(CAN_AM16H)
-#define bfin_write_CAN_AM16H(val) bfin_write16(CAN_AM16H, val)
-#define bfin_read_CAN_AM17L() bfin_read16(CAN_AM17L)
-#define bfin_write_CAN_AM17L(val) bfin_write16(CAN_AM17L, val)
-#define bfin_read_CAN_AM17H() bfin_read16(CAN_AM17H)
-#define bfin_write_CAN_AM17H(val) bfin_write16(CAN_AM17H, val)
-#define bfin_read_CAN_AM18L() bfin_read16(CAN_AM18L)
-#define bfin_write_CAN_AM18L(val) bfin_write16(CAN_AM18L, val)
-#define bfin_read_CAN_AM18H() bfin_read16(CAN_AM18H)
-#define bfin_write_CAN_AM18H(val) bfin_write16(CAN_AM18H, val)
-#define bfin_read_CAN_AM19L() bfin_read16(CAN_AM19L)
-#define bfin_write_CAN_AM19L(val) bfin_write16(CAN_AM19L, val)
-#define bfin_read_CAN_AM19H() bfin_read16(CAN_AM19H)
-#define bfin_write_CAN_AM19H(val) bfin_write16(CAN_AM19H, val)
-#define bfin_read_CAN_AM20L() bfin_read16(CAN_AM20L)
-#define bfin_write_CAN_AM20L(val) bfin_write16(CAN_AM20L, val)
-#define bfin_read_CAN_AM20H() bfin_read16(CAN_AM20H)
-#define bfin_write_CAN_AM20H(val) bfin_write16(CAN_AM20H, val)
-#define bfin_read_CAN_AM21L() bfin_read16(CAN_AM21L)
-#define bfin_write_CAN_AM21L(val) bfin_write16(CAN_AM21L, val)
-#define bfin_read_CAN_AM21H() bfin_read16(CAN_AM21H)
-#define bfin_write_CAN_AM21H(val) bfin_write16(CAN_AM21H, val)
-#define bfin_read_CAN_AM22L() bfin_read16(CAN_AM22L)
-#define bfin_write_CAN_AM22L(val) bfin_write16(CAN_AM22L, val)
-#define bfin_read_CAN_AM22H() bfin_read16(CAN_AM22H)
-#define bfin_write_CAN_AM22H(val) bfin_write16(CAN_AM22H, val)
-#define bfin_read_CAN_AM23L() bfin_read16(CAN_AM23L)
-#define bfin_write_CAN_AM23L(val) bfin_write16(CAN_AM23L, val)
-#define bfin_read_CAN_AM23H() bfin_read16(CAN_AM23H)
-#define bfin_write_CAN_AM23H(val) bfin_write16(CAN_AM23H, val)
-#define bfin_read_CAN_AM24L() bfin_read16(CAN_AM24L)
-#define bfin_write_CAN_AM24L(val) bfin_write16(CAN_AM24L, val)
-#define bfin_read_CAN_AM24H() bfin_read16(CAN_AM24H)
-#define bfin_write_CAN_AM24H(val) bfin_write16(CAN_AM24H, val)
-#define bfin_read_CAN_AM25L() bfin_read16(CAN_AM25L)
-#define bfin_write_CAN_AM25L(val) bfin_write16(CAN_AM25L, val)
-#define bfin_read_CAN_AM25H() bfin_read16(CAN_AM25H)
-#define bfin_write_CAN_AM25H(val) bfin_write16(CAN_AM25H, val)
-#define bfin_read_CAN_AM26L() bfin_read16(CAN_AM26L)
-#define bfin_write_CAN_AM26L(val) bfin_write16(CAN_AM26L, val)
-#define bfin_read_CAN_AM26H() bfin_read16(CAN_AM26H)
-#define bfin_write_CAN_AM26H(val) bfin_write16(CAN_AM26H, val)
-#define bfin_read_CAN_AM27L() bfin_read16(CAN_AM27L)
-#define bfin_write_CAN_AM27L(val) bfin_write16(CAN_AM27L, val)
-#define bfin_read_CAN_AM27H() bfin_read16(CAN_AM27H)
-#define bfin_write_CAN_AM27H(val) bfin_write16(CAN_AM27H, val)
-#define bfin_read_CAN_AM28L() bfin_read16(CAN_AM28L)
-#define bfin_write_CAN_AM28L(val) bfin_write16(CAN_AM28L, val)
-#define bfin_read_CAN_AM28H() bfin_read16(CAN_AM28H)
-#define bfin_write_CAN_AM28H(val) bfin_write16(CAN_AM28H, val)
-#define bfin_read_CAN_AM29L() bfin_read16(CAN_AM29L)
-#define bfin_write_CAN_AM29L(val) bfin_write16(CAN_AM29L, val)
-#define bfin_read_CAN_AM29H() bfin_read16(CAN_AM29H)
-#define bfin_write_CAN_AM29H(val) bfin_write16(CAN_AM29H, val)
-#define bfin_read_CAN_AM30L() bfin_read16(CAN_AM30L)
-#define bfin_write_CAN_AM30L(val) bfin_write16(CAN_AM30L, val)
-#define bfin_read_CAN_AM30H() bfin_read16(CAN_AM30H)
-#define bfin_write_CAN_AM30H(val) bfin_write16(CAN_AM30H, val)
-#define bfin_read_CAN_AM31L() bfin_read16(CAN_AM31L)
-#define bfin_write_CAN_AM31L(val) bfin_write16(CAN_AM31L, val)
-#define bfin_read_CAN_AM31H() bfin_read16(CAN_AM31H)
-#define bfin_write_CAN_AM31H(val) bfin_write16(CAN_AM31H, val)
-#define bfin_read_CAN_MB00_DATA0() bfin_read16(CAN_MB00_DATA0)
-#define bfin_write_CAN_MB00_DATA0(val) bfin_write16(CAN_MB00_DATA0, val)
-#define bfin_read_CAN_MB00_DATA1() bfin_read16(CAN_MB00_DATA1)
-#define bfin_write_CAN_MB00_DATA1(val) bfin_write16(CAN_MB00_DATA1, val)
-#define bfin_read_CAN_MB00_DATA2() bfin_read16(CAN_MB00_DATA2)
-#define bfin_write_CAN_MB00_DATA2(val) bfin_write16(CAN_MB00_DATA2, val)
-#define bfin_read_CAN_MB00_DATA3() bfin_read16(CAN_MB00_DATA3)
-#define bfin_write_CAN_MB00_DATA3(val) bfin_write16(CAN_MB00_DATA3, val)
-#define bfin_read_CAN_MB00_LENGTH() bfin_read16(CAN_MB00_LENGTH)
-#define bfin_write_CAN_MB00_LENGTH(val) bfin_write16(CAN_MB00_LENGTH, val)
-#define bfin_read_CAN_MB00_TIMESTAMP() bfin_read16(CAN_MB00_TIMESTAMP)
-#define bfin_write_CAN_MB00_TIMESTAMP(val) bfin_write16(CAN_MB00_TIMESTAMP, val)
-#define bfin_read_CAN_MB00_ID0() bfin_read16(CAN_MB00_ID0)
-#define bfin_write_CAN_MB00_ID0(val) bfin_write16(CAN_MB00_ID0, val)
-#define bfin_read_CAN_MB00_ID1() bfin_read16(CAN_MB00_ID1)
-#define bfin_write_CAN_MB00_ID1(val) bfin_write16(CAN_MB00_ID1, val)
-#define bfin_read_CAN_MB01_DATA0() bfin_read16(CAN_MB01_DATA0)
-#define bfin_write_CAN_MB01_DATA0(val) bfin_write16(CAN_MB01_DATA0, val)
-#define bfin_read_CAN_MB01_DATA1() bfin_read16(CAN_MB01_DATA1)
-#define bfin_write_CAN_MB01_DATA1(val) bfin_write16(CAN_MB01_DATA1, val)
-#define bfin_read_CAN_MB01_DATA2() bfin_read16(CAN_MB01_DATA2)
-#define bfin_write_CAN_MB01_DATA2(val) bfin_write16(CAN_MB01_DATA2, val)
-#define bfin_read_CAN_MB01_DATA3() bfin_read16(CAN_MB01_DATA3)
-#define bfin_write_CAN_MB01_DATA3(val) bfin_write16(CAN_MB01_DATA3, val)
-#define bfin_read_CAN_MB01_LENGTH() bfin_read16(CAN_MB01_LENGTH)
-#define bfin_write_CAN_MB01_LENGTH(val) bfin_write16(CAN_MB01_LENGTH, val)
-#define bfin_read_CAN_MB01_TIMESTAMP() bfin_read16(CAN_MB01_TIMESTAMP)
-#define bfin_write_CAN_MB01_TIMESTAMP(val) bfin_write16(CAN_MB01_TIMESTAMP, val)
-#define bfin_read_CAN_MB01_ID0() bfin_read16(CAN_MB01_ID0)
-#define bfin_write_CAN_MB01_ID0(val) bfin_write16(CAN_MB01_ID0, val)
-#define bfin_read_CAN_MB01_ID1() bfin_read16(CAN_MB01_ID1)
-#define bfin_write_CAN_MB01_ID1(val) bfin_write16(CAN_MB01_ID1, val)
-#define bfin_read_CAN_MB02_DATA0() bfin_read16(CAN_MB02_DATA0)
-#define bfin_write_CAN_MB02_DATA0(val) bfin_write16(CAN_MB02_DATA0, val)
-#define bfin_read_CAN_MB02_DATA1() bfin_read16(CAN_MB02_DATA1)
-#define bfin_write_CAN_MB02_DATA1(val) bfin_write16(CAN_MB02_DATA1, val)
-#define bfin_read_CAN_MB02_DATA2() bfin_read16(CAN_MB02_DATA2)
-#define bfin_write_CAN_MB02_DATA2(val) bfin_write16(CAN_MB02_DATA2, val)
-#define bfin_read_CAN_MB02_DATA3() bfin_read16(CAN_MB02_DATA3)
-#define bfin_write_CAN_MB02_DATA3(val) bfin_write16(CAN_MB02_DATA3, val)
-#define bfin_read_CAN_MB02_LENGTH() bfin_read16(CAN_MB02_LENGTH)
-#define bfin_write_CAN_MB02_LENGTH(val) bfin_write16(CAN_MB02_LENGTH, val)
-#define bfin_read_CAN_MB02_TIMESTAMP() bfin_read16(CAN_MB02_TIMESTAMP)
-#define bfin_write_CAN_MB02_TIMESTAMP(val) bfin_write16(CAN_MB02_TIMESTAMP, val)
-#define bfin_read_CAN_MB02_ID0() bfin_read16(CAN_MB02_ID0)
-#define bfin_write_CAN_MB02_ID0(val) bfin_write16(CAN_MB02_ID0, val)
-#define bfin_read_CAN_MB02_ID1() bfin_read16(CAN_MB02_ID1)
-#define bfin_write_CAN_MB02_ID1(val) bfin_write16(CAN_MB02_ID1, val)
-#define bfin_read_CAN_MB03_DATA0() bfin_read16(CAN_MB03_DATA0)
-#define bfin_write_CAN_MB03_DATA0(val) bfin_write16(CAN_MB03_DATA0, val)
-#define bfin_read_CAN_MB03_DATA1() bfin_read16(CAN_MB03_DATA1)
-#define bfin_write_CAN_MB03_DATA1(val) bfin_write16(CAN_MB03_DATA1, val)
-#define bfin_read_CAN_MB03_DATA2() bfin_read16(CAN_MB03_DATA2)
-#define bfin_write_CAN_MB03_DATA2(val) bfin_write16(CAN_MB03_DATA2, val)
-#define bfin_read_CAN_MB03_DATA3() bfin_read16(CAN_MB03_DATA3)
-#define bfin_write_CAN_MB03_DATA3(val) bfin_write16(CAN_MB03_DATA3, val)
-#define bfin_read_CAN_MB03_LENGTH() bfin_read16(CAN_MB03_LENGTH)
-#define bfin_write_CAN_MB03_LENGTH(val) bfin_write16(CAN_MB03_LENGTH, val)
-#define bfin_read_CAN_MB03_TIMESTAMP() bfin_read16(CAN_MB03_TIMESTAMP)
-#define bfin_write_CAN_MB03_TIMESTAMP(val) bfin_write16(CAN_MB03_TIMESTAMP, val)
-#define bfin_read_CAN_MB03_ID0() bfin_read16(CAN_MB03_ID0)
-#define bfin_write_CAN_MB03_ID0(val) bfin_write16(CAN_MB03_ID0, val)
-#define bfin_read_CAN_MB03_ID1() bfin_read16(CAN_MB03_ID1)
-#define bfin_write_CAN_MB03_ID1(val) bfin_write16(CAN_MB03_ID1, val)
-#define bfin_read_CAN_MB04_DATA0() bfin_read16(CAN_MB04_DATA0)
-#define bfin_write_CAN_MB04_DATA0(val) bfin_write16(CAN_MB04_DATA0, val)
-#define bfin_read_CAN_MB04_DATA1() bfin_read16(CAN_MB04_DATA1)
-#define bfin_write_CAN_MB04_DATA1(val) bfin_write16(CAN_MB04_DATA1, val)
-#define bfin_read_CAN_MB04_DATA2() bfin_read16(CAN_MB04_DATA2)
-#define bfin_write_CAN_MB04_DATA2(val) bfin_write16(CAN_MB04_DATA2, val)
-#define bfin_read_CAN_MB04_DATA3() bfin_read16(CAN_MB04_DATA3)
-#define bfin_write_CAN_MB04_DATA3(val) bfin_write16(CAN_MB04_DATA3, val)
-#define bfin_read_CAN_MB04_LENGTH() bfin_read16(CAN_MB04_LENGTH)
-#define bfin_write_CAN_MB04_LENGTH(val) bfin_write16(CAN_MB04_LENGTH, val)
-#define bfin_read_CAN_MB04_TIMESTAMP() bfin_read16(CAN_MB04_TIMESTAMP)
-#define bfin_write_CAN_MB04_TIMESTAMP(val) bfin_write16(CAN_MB04_TIMESTAMP, val)
-#define bfin_read_CAN_MB04_ID0() bfin_read16(CAN_MB04_ID0)
-#define bfin_write_CAN_MB04_ID0(val) bfin_write16(CAN_MB04_ID0, val)
-#define bfin_read_CAN_MB04_ID1() bfin_read16(CAN_MB04_ID1)
-#define bfin_write_CAN_MB04_ID1(val) bfin_write16(CAN_MB04_ID1, val)
-#define bfin_read_CAN_MB05_DATA0() bfin_read16(CAN_MB05_DATA0)
-#define bfin_write_CAN_MB05_DATA0(val) bfin_write16(CAN_MB05_DATA0, val)
-#define bfin_read_CAN_MB05_DATA1() bfin_read16(CAN_MB05_DATA1)
-#define bfin_write_CAN_MB05_DATA1(val) bfin_write16(CAN_MB05_DATA1, val)
-#define bfin_read_CAN_MB05_DATA2() bfin_read16(CAN_MB05_DATA2)
-#define bfin_write_CAN_MB05_DATA2(val) bfin_write16(CAN_MB05_DATA2, val)
-#define bfin_read_CAN_MB05_DATA3() bfin_read16(CAN_MB05_DATA3)
-#define bfin_write_CAN_MB05_DATA3(val) bfin_write16(CAN_MB05_DATA3, val)
-#define bfin_read_CAN_MB05_LENGTH() bfin_read16(CAN_MB05_LENGTH)
-#define bfin_write_CAN_MB05_LENGTH(val) bfin_write16(CAN_MB05_LENGTH, val)
-#define bfin_read_CAN_MB05_TIMESTAMP() bfin_read16(CAN_MB05_TIMESTAMP)
-#define bfin_write_CAN_MB05_TIMESTAMP(val) bfin_write16(CAN_MB05_TIMESTAMP, val)
-#define bfin_read_CAN_MB05_ID0() bfin_read16(CAN_MB05_ID0)
-#define bfin_write_CAN_MB05_ID0(val) bfin_write16(CAN_MB05_ID0, val)
-#define bfin_read_CAN_MB05_ID1() bfin_read16(CAN_MB05_ID1)
-#define bfin_write_CAN_MB05_ID1(val) bfin_write16(CAN_MB05_ID1, val)
-#define bfin_read_CAN_MB06_DATA0() bfin_read16(CAN_MB06_DATA0)
-#define bfin_write_CAN_MB06_DATA0(val) bfin_write16(CAN_MB06_DATA0, val)
-#define bfin_read_CAN_MB06_DATA1() bfin_read16(CAN_MB06_DATA1)
-#define bfin_write_CAN_MB06_DATA1(val) bfin_write16(CAN_MB06_DATA1, val)
-#define bfin_read_CAN_MB06_DATA2() bfin_read16(CAN_MB06_DATA2)
-#define bfin_write_CAN_MB06_DATA2(val) bfin_write16(CAN_MB06_DATA2, val)
-#define bfin_read_CAN_MB06_DATA3() bfin_read16(CAN_MB06_DATA3)
-#define bfin_write_CAN_MB06_DATA3(val) bfin_write16(CAN_MB06_DATA3, val)
-#define bfin_read_CAN_MB06_LENGTH() bfin_read16(CAN_MB06_LENGTH)
-#define bfin_write_CAN_MB06_LENGTH(val) bfin_write16(CAN_MB06_LENGTH, val)
-#define bfin_read_CAN_MB06_TIMESTAMP() bfin_read16(CAN_MB06_TIMESTAMP)
-#define bfin_write_CAN_MB06_TIMESTAMP(val) bfin_write16(CAN_MB06_TIMESTAMP, val)
-#define bfin_read_CAN_MB06_ID0() bfin_read16(CAN_MB06_ID0)
-#define bfin_write_CAN_MB06_ID0(val) bfin_write16(CAN_MB06_ID0, val)
-#define bfin_read_CAN_MB06_ID1() bfin_read16(CAN_MB06_ID1)
-#define bfin_write_CAN_MB06_ID1(val) bfin_write16(CAN_MB06_ID1, val)
-#define bfin_read_CAN_MB07_DATA0() bfin_read16(CAN_MB07_DATA0)
-#define bfin_write_CAN_MB07_DATA0(val) bfin_write16(CAN_MB07_DATA0, val)
-#define bfin_read_CAN_MB07_DATA1() bfin_read16(CAN_MB07_DATA1)
-#define bfin_write_CAN_MB07_DATA1(val) bfin_write16(CAN_MB07_DATA1, val)
-#define bfin_read_CAN_MB07_DATA2() bfin_read16(CAN_MB07_DATA2)
-#define bfin_write_CAN_MB07_DATA2(val) bfin_write16(CAN_MB07_DATA2, val)
-#define bfin_read_CAN_MB07_DATA3() bfin_read16(CAN_MB07_DATA3)
-#define bfin_write_CAN_MB07_DATA3(val) bfin_write16(CAN_MB07_DATA3, val)
-#define bfin_read_CAN_MB07_LENGTH() bfin_read16(CAN_MB07_LENGTH)
-#define bfin_write_CAN_MB07_LENGTH(val) bfin_write16(CAN_MB07_LENGTH, val)
-#define bfin_read_CAN_MB07_TIMESTAMP() bfin_read16(CAN_MB07_TIMESTAMP)
-#define bfin_write_CAN_MB07_TIMESTAMP(val) bfin_write16(CAN_MB07_TIMESTAMP, val)
-#define bfin_read_CAN_MB07_ID0() bfin_read16(CAN_MB07_ID0)
-#define bfin_write_CAN_MB07_ID0(val) bfin_write16(CAN_MB07_ID0, val)
-#define bfin_read_CAN_MB07_ID1() bfin_read16(CAN_MB07_ID1)
-#define bfin_write_CAN_MB07_ID1(val) bfin_write16(CAN_MB07_ID1, val)
-#define bfin_read_CAN_MB08_DATA0() bfin_read16(CAN_MB08_DATA0)
-#define bfin_write_CAN_MB08_DATA0(val) bfin_write16(CAN_MB08_DATA0, val)
-#define bfin_read_CAN_MB08_DATA1() bfin_read16(CAN_MB08_DATA1)
-#define bfin_write_CAN_MB08_DATA1(val) bfin_write16(CAN_MB08_DATA1, val)
-#define bfin_read_CAN_MB08_DATA2() bfin_read16(CAN_MB08_DATA2)
-#define bfin_write_CAN_MB08_DATA2(val) bfin_write16(CAN_MB08_DATA2, val)
-#define bfin_read_CAN_MB08_DATA3() bfin_read16(CAN_MB08_DATA3)
-#define bfin_write_CAN_MB08_DATA3(val) bfin_write16(CAN_MB08_DATA3, val)
-#define bfin_read_CAN_MB08_LENGTH() bfin_read16(CAN_MB08_LENGTH)
-#define bfin_write_CAN_MB08_LENGTH(val) bfin_write16(CAN_MB08_LENGTH, val)
-#define bfin_read_CAN_MB08_TIMESTAMP() bfin_read16(CAN_MB08_TIMESTAMP)
-#define bfin_write_CAN_MB08_TIMESTAMP(val) bfin_write16(CAN_MB08_TIMESTAMP, val)
-#define bfin_read_CAN_MB08_ID0() bfin_read16(CAN_MB08_ID0)
-#define bfin_write_CAN_MB08_ID0(val) bfin_write16(CAN_MB08_ID0, val)
-#define bfin_read_CAN_MB08_ID1() bfin_read16(CAN_MB08_ID1)
-#define bfin_write_CAN_MB08_ID1(val) bfin_write16(CAN_MB08_ID1, val)
-#define bfin_read_CAN_MB09_DATA0() bfin_read16(CAN_MB09_DATA0)
-#define bfin_write_CAN_MB09_DATA0(val) bfin_write16(CAN_MB09_DATA0, val)
-#define bfin_read_CAN_MB09_DATA1() bfin_read16(CAN_MB09_DATA1)
-#define bfin_write_CAN_MB09_DATA1(val) bfin_write16(CAN_MB09_DATA1, val)
-#define bfin_read_CAN_MB09_DATA2() bfin_read16(CAN_MB09_DATA2)
-#define bfin_write_CAN_MB09_DATA2(val) bfin_write16(CAN_MB09_DATA2, val)
-#define bfin_read_CAN_MB09_DATA3() bfin_read16(CAN_MB09_DATA3)
-#define bfin_write_CAN_MB09_DATA3(val) bfin_write16(CAN_MB09_DATA3, val)
-#define bfin_read_CAN_MB09_LENGTH() bfin_read16(CAN_MB09_LENGTH)
-#define bfin_write_CAN_MB09_LENGTH(val) bfin_write16(CAN_MB09_LENGTH, val)
-#define bfin_read_CAN_MB09_TIMESTAMP() bfin_read16(CAN_MB09_TIMESTAMP)
-#define bfin_write_CAN_MB09_TIMESTAMP(val) bfin_write16(CAN_MB09_TIMESTAMP, val)
-#define bfin_read_CAN_MB09_ID0() bfin_read16(CAN_MB09_ID0)
-#define bfin_write_CAN_MB09_ID0(val) bfin_write16(CAN_MB09_ID0, val)
-#define bfin_read_CAN_MB09_ID1() bfin_read16(CAN_MB09_ID1)
-#define bfin_write_CAN_MB09_ID1(val) bfin_write16(CAN_MB09_ID1, val)
-#define bfin_read_CAN_MB10_DATA0() bfin_read16(CAN_MB10_DATA0)
-#define bfin_write_CAN_MB10_DATA0(val) bfin_write16(CAN_MB10_DATA0, val)
-#define bfin_read_CAN_MB10_DATA1() bfin_read16(CAN_MB10_DATA1)
-#define bfin_write_CAN_MB10_DATA1(val) bfin_write16(CAN_MB10_DATA1, val)
-#define bfin_read_CAN_MB10_DATA2() bfin_read16(CAN_MB10_DATA2)
-#define bfin_write_CAN_MB10_DATA2(val) bfin_write16(CAN_MB10_DATA2, val)
-#define bfin_read_CAN_MB10_DATA3() bfin_read16(CAN_MB10_DATA3)
-#define bfin_write_CAN_MB10_DATA3(val) bfin_write16(CAN_MB10_DATA3, val)
-#define bfin_read_CAN_MB10_LENGTH() bfin_read16(CAN_MB10_LENGTH)
-#define bfin_write_CAN_MB10_LENGTH(val) bfin_write16(CAN_MB10_LENGTH, val)
-#define bfin_read_CAN_MB10_TIMESTAMP() bfin_read16(CAN_MB10_TIMESTAMP)
-#define bfin_write_CAN_MB10_TIMESTAMP(val) bfin_write16(CAN_MB10_TIMESTAMP, val)
-#define bfin_read_CAN_MB10_ID0() bfin_read16(CAN_MB10_ID0)
-#define bfin_write_CAN_MB10_ID0(val) bfin_write16(CAN_MB10_ID0, val)
-#define bfin_read_CAN_MB10_ID1() bfin_read16(CAN_MB10_ID1)
-#define bfin_write_CAN_MB10_ID1(val) bfin_write16(CAN_MB10_ID1, val)
-#define bfin_read_CAN_MB11_DATA0() bfin_read16(CAN_MB11_DATA0)
-#define bfin_write_CAN_MB11_DATA0(val) bfin_write16(CAN_MB11_DATA0, val)
-#define bfin_read_CAN_MB11_DATA1() bfin_read16(CAN_MB11_DATA1)
-#define bfin_write_CAN_MB11_DATA1(val) bfin_write16(CAN_MB11_DATA1, val)
-#define bfin_read_CAN_MB11_DATA2() bfin_read16(CAN_MB11_DATA2)
-#define bfin_write_CAN_MB11_DATA2(val) bfin_write16(CAN_MB11_DATA2, val)
-#define bfin_read_CAN_MB11_DATA3() bfin_read16(CAN_MB11_DATA3)
-#define bfin_write_CAN_MB11_DATA3(val) bfin_write16(CAN_MB11_DATA3, val)
-#define bfin_read_CAN_MB11_LENGTH() bfin_read16(CAN_MB11_LENGTH)
-#define bfin_write_CAN_MB11_LENGTH(val) bfin_write16(CAN_MB11_LENGTH, val)
-#define bfin_read_CAN_MB11_TIMESTAMP() bfin_read16(CAN_MB11_TIMESTAMP)
-#define bfin_write_CAN_MB11_TIMESTAMP(val) bfin_write16(CAN_MB11_TIMESTAMP, val)
-#define bfin_read_CAN_MB11_ID0() bfin_read16(CAN_MB11_ID0)
-#define bfin_write_CAN_MB11_ID0(val) bfin_write16(CAN_MB11_ID0, val)
-#define bfin_read_CAN_MB11_ID1() bfin_read16(CAN_MB11_ID1)
-#define bfin_write_CAN_MB11_ID1(val) bfin_write16(CAN_MB11_ID1, val)
-#define bfin_read_CAN_MB12_DATA0() bfin_read16(CAN_MB12_DATA0)
-#define bfin_write_CAN_MB12_DATA0(val) bfin_write16(CAN_MB12_DATA0, val)
-#define bfin_read_CAN_MB12_DATA1() bfin_read16(CAN_MB12_DATA1)
-#define bfin_write_CAN_MB12_DATA1(val) bfin_write16(CAN_MB12_DATA1, val)
-#define bfin_read_CAN_MB12_DATA2() bfin_read16(CAN_MB12_DATA2)
-#define bfin_write_CAN_MB12_DATA2(val) bfin_write16(CAN_MB12_DATA2, val)
-#define bfin_read_CAN_MB12_DATA3() bfin_read16(CAN_MB12_DATA3)
-#define bfin_write_CAN_MB12_DATA3(val) bfin_write16(CAN_MB12_DATA3, val)
-#define bfin_read_CAN_MB12_LENGTH() bfin_read16(CAN_MB12_LENGTH)
-#define bfin_write_CAN_MB12_LENGTH(val) bfin_write16(CAN_MB12_LENGTH, val)
-#define bfin_read_CAN_MB12_TIMESTAMP() bfin_read16(CAN_MB12_TIMESTAMP)
-#define bfin_write_CAN_MB12_TIMESTAMP(val) bfin_write16(CAN_MB12_TIMESTAMP, val)
-#define bfin_read_CAN_MB12_ID0() bfin_read16(CAN_MB12_ID0)
-#define bfin_write_CAN_MB12_ID0(val) bfin_write16(CAN_MB12_ID0, val)
-#define bfin_read_CAN_MB12_ID1() bfin_read16(CAN_MB12_ID1)
-#define bfin_write_CAN_MB12_ID1(val) bfin_write16(CAN_MB12_ID1, val)
-#define bfin_read_CAN_MB13_DATA0() bfin_read16(CAN_MB13_DATA0)
-#define bfin_write_CAN_MB13_DATA0(val) bfin_write16(CAN_MB13_DATA0, val)
-#define bfin_read_CAN_MB13_DATA1() bfin_read16(CAN_MB13_DATA1)
-#define bfin_write_CAN_MB13_DATA1(val) bfin_write16(CAN_MB13_DATA1, val)
-#define bfin_read_CAN_MB13_DATA2() bfin_read16(CAN_MB13_DATA2)
-#define bfin_write_CAN_MB13_DATA2(val) bfin_write16(CAN_MB13_DATA2, val)
-#define bfin_read_CAN_MB13_DATA3() bfin_read16(CAN_MB13_DATA3)
-#define bfin_write_CAN_MB13_DATA3(val) bfin_write16(CAN_MB13_DATA3, val)
-#define bfin_read_CAN_MB13_LENGTH() bfin_read16(CAN_MB13_LENGTH)
-#define bfin_write_CAN_MB13_LENGTH(val) bfin_write16(CAN_MB13_LENGTH, val)
-#define bfin_read_CAN_MB13_TIMESTAMP() bfin_read16(CAN_MB13_TIMESTAMP)
-#define bfin_write_CAN_MB13_TIMESTAMP(val) bfin_write16(CAN_MB13_TIMESTAMP, val)
-#define bfin_read_CAN_MB13_ID0() bfin_read16(CAN_MB13_ID0)
-#define bfin_write_CAN_MB13_ID0(val) bfin_write16(CAN_MB13_ID0, val)
-#define bfin_read_CAN_MB13_ID1() bfin_read16(CAN_MB13_ID1)
-#define bfin_write_CAN_MB13_ID1(val) bfin_write16(CAN_MB13_ID1, val)
-#define bfin_read_CAN_MB14_DATA0() bfin_read16(CAN_MB14_DATA0)
-#define bfin_write_CAN_MB14_DATA0(val) bfin_write16(CAN_MB14_DATA0, val)
-#define bfin_read_CAN_MB14_DATA1() bfin_read16(CAN_MB14_DATA1)
-#define bfin_write_CAN_MB14_DATA1(val) bfin_write16(CAN_MB14_DATA1, val)
-#define bfin_read_CAN_MB14_DATA2() bfin_read16(CAN_MB14_DATA2)
-#define bfin_write_CAN_MB14_DATA2(val) bfin_write16(CAN_MB14_DATA2, val)
-#define bfin_read_CAN_MB14_DATA3() bfin_read16(CAN_MB14_DATA3)
-#define bfin_write_CAN_MB14_DATA3(val) bfin_write16(CAN_MB14_DATA3, val)
-#define bfin_read_CAN_MB14_LENGTH() bfin_read16(CAN_MB14_LENGTH)
-#define bfin_write_CAN_MB14_LENGTH(val) bfin_write16(CAN_MB14_LENGTH, val)
-#define bfin_read_CAN_MB14_TIMESTAMP() bfin_read16(CAN_MB14_TIMESTAMP)
-#define bfin_write_CAN_MB14_TIMESTAMP(val) bfin_write16(CAN_MB14_TIMESTAMP, val)
-#define bfin_read_CAN_MB14_ID0() bfin_read16(CAN_MB14_ID0)
-#define bfin_write_CAN_MB14_ID0(val) bfin_write16(CAN_MB14_ID0, val)
-#define bfin_read_CAN_MB14_ID1() bfin_read16(CAN_MB14_ID1)
-#define bfin_write_CAN_MB14_ID1(val) bfin_write16(CAN_MB14_ID1, val)
-#define bfin_read_CAN_MB15_DATA0() bfin_read16(CAN_MB15_DATA0)
-#define bfin_write_CAN_MB15_DATA0(val) bfin_write16(CAN_MB15_DATA0, val)
-#define bfin_read_CAN_MB15_DATA1() bfin_read16(CAN_MB15_DATA1)
-#define bfin_write_CAN_MB15_DATA1(val) bfin_write16(CAN_MB15_DATA1, val)
-#define bfin_read_CAN_MB15_DATA2() bfin_read16(CAN_MB15_DATA2)
-#define bfin_write_CAN_MB15_DATA2(val) bfin_write16(CAN_MB15_DATA2, val)
-#define bfin_read_CAN_MB15_DATA3() bfin_read16(CAN_MB15_DATA3)
-#define bfin_write_CAN_MB15_DATA3(val) bfin_write16(CAN_MB15_DATA3, val)
-#define bfin_read_CAN_MB15_LENGTH() bfin_read16(CAN_MB15_LENGTH)
-#define bfin_write_CAN_MB15_LENGTH(val) bfin_write16(CAN_MB15_LENGTH, val)
-#define bfin_read_CAN_MB15_TIMESTAMP() bfin_read16(CAN_MB15_TIMESTAMP)
-#define bfin_write_CAN_MB15_TIMESTAMP(val) bfin_write16(CAN_MB15_TIMESTAMP, val)
-#define bfin_read_CAN_MB15_ID0() bfin_read16(CAN_MB15_ID0)
-#define bfin_write_CAN_MB15_ID0(val) bfin_write16(CAN_MB15_ID0, val)
-#define bfin_read_CAN_MB15_ID1() bfin_read16(CAN_MB15_ID1)
-#define bfin_write_CAN_MB15_ID1(val) bfin_write16(CAN_MB15_ID1, val)
-#define bfin_read_CAN_MB16_DATA0() bfin_read16(CAN_MB16_DATA0)
-#define bfin_write_CAN_MB16_DATA0(val) bfin_write16(CAN_MB16_DATA0, val)
-#define bfin_read_CAN_MB16_DATA1() bfin_read16(CAN_MB16_DATA1)
-#define bfin_write_CAN_MB16_DATA1(val) bfin_write16(CAN_MB16_DATA1, val)
-#define bfin_read_CAN_MB16_DATA2() bfin_read16(CAN_MB16_DATA2)
-#define bfin_write_CAN_MB16_DATA2(val) bfin_write16(CAN_MB16_DATA2, val)
-#define bfin_read_CAN_MB16_DATA3() bfin_read16(CAN_MB16_DATA3)
-#define bfin_write_CAN_MB16_DATA3(val) bfin_write16(CAN_MB16_DATA3, val)
-#define bfin_read_CAN_MB16_LENGTH() bfin_read16(CAN_MB16_LENGTH)
-#define bfin_write_CAN_MB16_LENGTH(val) bfin_write16(CAN_MB16_LENGTH, val)
-#define bfin_read_CAN_MB16_TIMESTAMP() bfin_read16(CAN_MB16_TIMESTAMP)
-#define bfin_write_CAN_MB16_TIMESTAMP(val) bfin_write16(CAN_MB16_TIMESTAMP, val)
-#define bfin_read_CAN_MB16_ID0() bfin_read16(CAN_MB16_ID0)
-#define bfin_write_CAN_MB16_ID0(val) bfin_write16(CAN_MB16_ID0, val)
-#define bfin_read_CAN_MB16_ID1() bfin_read16(CAN_MB16_ID1)
-#define bfin_write_CAN_MB16_ID1(val) bfin_write16(CAN_MB16_ID1, val)
-#define bfin_read_CAN_MB17_DATA0() bfin_read16(CAN_MB17_DATA0)
-#define bfin_write_CAN_MB17_DATA0(val) bfin_write16(CAN_MB17_DATA0, val)
-#define bfin_read_CAN_MB17_DATA1() bfin_read16(CAN_MB17_DATA1)
-#define bfin_write_CAN_MB17_DATA1(val) bfin_write16(CAN_MB17_DATA1, val)
-#define bfin_read_CAN_MB17_DATA2() bfin_read16(CAN_MB17_DATA2)
-#define bfin_write_CAN_MB17_DATA2(val) bfin_write16(CAN_MB17_DATA2, val)
-#define bfin_read_CAN_MB17_DATA3() bfin_read16(CAN_MB17_DATA3)
-#define bfin_write_CAN_MB17_DATA3(val) bfin_write16(CAN_MB17_DATA3, val)
-#define bfin_read_CAN_MB17_LENGTH() bfin_read16(CAN_MB17_LENGTH)
-#define bfin_write_CAN_MB17_LENGTH(val) bfin_write16(CAN_MB17_LENGTH, val)
-#define bfin_read_CAN_MB17_TIMESTAMP() bfin_read16(CAN_MB17_TIMESTAMP)
-#define bfin_write_CAN_MB17_TIMESTAMP(val) bfin_write16(CAN_MB17_TIMESTAMP, val)
-#define bfin_read_CAN_MB17_ID0() bfin_read16(CAN_MB17_ID0)
-#define bfin_write_CAN_MB17_ID0(val) bfin_write16(CAN_MB17_ID0, val)
-#define bfin_read_CAN_MB17_ID1() bfin_read16(CAN_MB17_ID1)
-#define bfin_write_CAN_MB17_ID1(val) bfin_write16(CAN_MB17_ID1, val)
-#define bfin_read_CAN_MB18_DATA0() bfin_read16(CAN_MB18_DATA0)
-#define bfin_write_CAN_MB18_DATA0(val) bfin_write16(CAN_MB18_DATA0, val)
-#define bfin_read_CAN_MB18_DATA1() bfin_read16(CAN_MB18_DATA1)
-#define bfin_write_CAN_MB18_DATA1(val) bfin_write16(CAN_MB18_DATA1, val)
-#define bfin_read_CAN_MB18_DATA2() bfin_read16(CAN_MB18_DATA2)
-#define bfin_write_CAN_MB18_DATA2(val) bfin_write16(CAN_MB18_DATA2, val)
-#define bfin_read_CAN_MB18_DATA3() bfin_read16(CAN_MB18_DATA3)
-#define bfin_write_CAN_MB18_DATA3(val) bfin_write16(CAN_MB18_DATA3, val)
-#define bfin_read_CAN_MB18_LENGTH() bfin_read16(CAN_MB18_LENGTH)
-#define bfin_write_CAN_MB18_LENGTH(val) bfin_write16(CAN_MB18_LENGTH, val)
-#define bfin_read_CAN_MB18_TIMESTAMP() bfin_read16(CAN_MB18_TIMESTAMP)
-#define bfin_write_CAN_MB18_TIMESTAMP(val) bfin_write16(CAN_MB18_TIMESTAMP, val)
-#define bfin_read_CAN_MB18_ID0() bfin_read16(CAN_MB18_ID0)
-#define bfin_write_CAN_MB18_ID0(val) bfin_write16(CAN_MB18_ID0, val)
-#define bfin_read_CAN_MB18_ID1() bfin_read16(CAN_MB18_ID1)
-#define bfin_write_CAN_MB18_ID1(val) bfin_write16(CAN_MB18_ID1, val)
-#define bfin_read_CAN_MB19_DATA0() bfin_read16(CAN_MB19_DATA0)
-#define bfin_write_CAN_MB19_DATA0(val) bfin_write16(CAN_MB19_DATA0, val)
-#define bfin_read_CAN_MB19_DATA1() bfin_read16(CAN_MB19_DATA1)
-#define bfin_write_CAN_MB19_DATA1(val) bfin_write16(CAN_MB19_DATA1, val)
-#define bfin_read_CAN_MB19_DATA2() bfin_read16(CAN_MB19_DATA2)
-#define bfin_write_CAN_MB19_DATA2(val) bfin_write16(CAN_MB19_DATA2, val)
-#define bfin_read_CAN_MB19_DATA3() bfin_read16(CAN_MB19_DATA3)
-#define bfin_write_CAN_MB19_DATA3(val) bfin_write16(CAN_MB19_DATA3, val)
-#define bfin_read_CAN_MB19_LENGTH() bfin_read16(CAN_MB19_LENGTH)
-#define bfin_write_CAN_MB19_LENGTH(val) bfin_write16(CAN_MB19_LENGTH, val)
-#define bfin_read_CAN_MB19_TIMESTAMP() bfin_read16(CAN_MB19_TIMESTAMP)
-#define bfin_write_CAN_MB19_TIMESTAMP(val) bfin_write16(CAN_MB19_TIMESTAMP, val)
-#define bfin_read_CAN_MB19_ID0() bfin_read16(CAN_MB19_ID0)
-#define bfin_write_CAN_MB19_ID0(val) bfin_write16(CAN_MB19_ID0, val)
-#define bfin_read_CAN_MB19_ID1() bfin_read16(CAN_MB19_ID1)
-#define bfin_write_CAN_MB19_ID1(val) bfin_write16(CAN_MB19_ID1, val)
-#define bfin_read_CAN_MB20_DATA0() bfin_read16(CAN_MB20_DATA0)
-#define bfin_write_CAN_MB20_DATA0(val) bfin_write16(CAN_MB20_DATA0, val)
-#define bfin_read_CAN_MB20_DATA1() bfin_read16(CAN_MB20_DATA1)
-#define bfin_write_CAN_MB20_DATA1(val) bfin_write16(CAN_MB20_DATA1, val)
-#define bfin_read_CAN_MB20_DATA2() bfin_read16(CAN_MB20_DATA2)
-#define bfin_write_CAN_MB20_DATA2(val) bfin_write16(CAN_MB20_DATA2, val)
-#define bfin_read_CAN_MB20_DATA3() bfin_read16(CAN_MB20_DATA3)
-#define bfin_write_CAN_MB20_DATA3(val) bfin_write16(CAN_MB20_DATA3, val)
-#define bfin_read_CAN_MB20_LENGTH() bfin_read16(CAN_MB20_LENGTH)
-#define bfin_write_CAN_MB20_LENGTH(val) bfin_write16(CAN_MB20_LENGTH, val)
-#define bfin_read_CAN_MB20_TIMESTAMP() bfin_read16(CAN_MB20_TIMESTAMP)
-#define bfin_write_CAN_MB20_TIMESTAMP(val) bfin_write16(CAN_MB20_TIMESTAMP, val)
-#define bfin_read_CAN_MB20_ID0() bfin_read16(CAN_MB20_ID0)
-#define bfin_write_CAN_MB20_ID0(val) bfin_write16(CAN_MB20_ID0, val)
-#define bfin_read_CAN_MB20_ID1() bfin_read16(CAN_MB20_ID1)
-#define bfin_write_CAN_MB20_ID1(val) bfin_write16(CAN_MB20_ID1, val)
-#define bfin_read_CAN_MB21_DATA0() bfin_read16(CAN_MB21_DATA0)
-#define bfin_write_CAN_MB21_DATA0(val) bfin_write16(CAN_MB21_DATA0, val)
-#define bfin_read_CAN_MB21_DATA1() bfin_read16(CAN_MB21_DATA1)
-#define bfin_write_CAN_MB21_DATA1(val) bfin_write16(CAN_MB21_DATA1, val)
-#define bfin_read_CAN_MB21_DATA2() bfin_read16(CAN_MB21_DATA2)
-#define bfin_write_CAN_MB21_DATA2(val) bfin_write16(CAN_MB21_DATA2, val)
-#define bfin_read_CAN_MB21_DATA3() bfin_read16(CAN_MB21_DATA3)
-#define bfin_write_CAN_MB21_DATA3(val) bfin_write16(CAN_MB21_DATA3, val)
-#define bfin_read_CAN_MB21_LENGTH() bfin_read16(CAN_MB21_LENGTH)
-#define bfin_write_CAN_MB21_LENGTH(val) bfin_write16(CAN_MB21_LENGTH, val)
-#define bfin_read_CAN_MB21_TIMESTAMP() bfin_read16(CAN_MB21_TIMESTAMP)
-#define bfin_write_CAN_MB21_TIMESTAMP(val) bfin_write16(CAN_MB21_TIMESTAMP, val)
-#define bfin_read_CAN_MB21_ID0() bfin_read16(CAN_MB21_ID0)
-#define bfin_write_CAN_MB21_ID0(val) bfin_write16(CAN_MB21_ID0, val)
-#define bfin_read_CAN_MB21_ID1() bfin_read16(CAN_MB21_ID1)
-#define bfin_write_CAN_MB21_ID1(val) bfin_write16(CAN_MB21_ID1, val)
-#define bfin_read_CAN_MB22_DATA0() bfin_read16(CAN_MB22_DATA0)
-#define bfin_write_CAN_MB22_DATA0(val) bfin_write16(CAN_MB22_DATA0, val)
-#define bfin_read_CAN_MB22_DATA1() bfin_read16(CAN_MB22_DATA1)
-#define bfin_write_CAN_MB22_DATA1(val) bfin_write16(CAN_MB22_DATA1, val)
-#define bfin_read_CAN_MB22_DATA2() bfin_read16(CAN_MB22_DATA2)
-#define bfin_write_CAN_MB22_DATA2(val) bfin_write16(CAN_MB22_DATA2, val)
-#define bfin_read_CAN_MB22_DATA3() bfin_read16(CAN_MB22_DATA3)
-#define bfin_write_CAN_MB22_DATA3(val) bfin_write16(CAN_MB22_DATA3, val)
-#define bfin_read_CAN_MB22_LENGTH() bfin_read16(CAN_MB22_LENGTH)
-#define bfin_write_CAN_MB22_LENGTH(val) bfin_write16(CAN_MB22_LENGTH, val)
-#define bfin_read_CAN_MB22_TIMESTAMP() bfin_read16(CAN_MB22_TIMESTAMP)
-#define bfin_write_CAN_MB22_TIMESTAMP(val) bfin_write16(CAN_MB22_TIMESTAMP, val)
-#define bfin_read_CAN_MB22_ID0() bfin_read16(CAN_MB22_ID0)
-#define bfin_write_CAN_MB22_ID0(val) bfin_write16(CAN_MB22_ID0, val)
-#define bfin_read_CAN_MB22_ID1() bfin_read16(CAN_MB22_ID1)
-#define bfin_write_CAN_MB22_ID1(val) bfin_write16(CAN_MB22_ID1, val)
-#define bfin_read_CAN_MB23_DATA0() bfin_read16(CAN_MB23_DATA0)
-#define bfin_write_CAN_MB23_DATA0(val) bfin_write16(CAN_MB23_DATA0, val)
-#define bfin_read_CAN_MB23_DATA1() bfin_read16(CAN_MB23_DATA1)
-#define bfin_write_CAN_MB23_DATA1(val) bfin_write16(CAN_MB23_DATA1, val)
-#define bfin_read_CAN_MB23_DATA2() bfin_read16(CAN_MB23_DATA2)
-#define bfin_write_CAN_MB23_DATA2(val) bfin_write16(CAN_MB23_DATA2, val)
-#define bfin_read_CAN_MB23_DATA3() bfin_read16(CAN_MB23_DATA3)
-#define bfin_write_CAN_MB23_DATA3(val) bfin_write16(CAN_MB23_DATA3, val)
-#define bfin_read_CAN_MB23_LENGTH() bfin_read16(CAN_MB23_LENGTH)
-#define bfin_write_CAN_MB23_LENGTH(val) bfin_write16(CAN_MB23_LENGTH, val)
-#define bfin_read_CAN_MB23_TIMESTAMP() bfin_read16(CAN_MB23_TIMESTAMP)
-#define bfin_write_CAN_MB23_TIMESTAMP(val) bfin_write16(CAN_MB23_TIMESTAMP, val)
-#define bfin_read_CAN_MB23_ID0() bfin_read16(CAN_MB23_ID0)
-#define bfin_write_CAN_MB23_ID0(val) bfin_write16(CAN_MB23_ID0, val)
-#define bfin_read_CAN_MB23_ID1() bfin_read16(CAN_MB23_ID1)
-#define bfin_write_CAN_MB23_ID1(val) bfin_write16(CAN_MB23_ID1, val)
-#define bfin_read_CAN_MB24_DATA0() bfin_read16(CAN_MB24_DATA0)
-#define bfin_write_CAN_MB24_DATA0(val) bfin_write16(CAN_MB24_DATA0, val)
-#define bfin_read_CAN_MB24_DATA1() bfin_read16(CAN_MB24_DATA1)
-#define bfin_write_CAN_MB24_DATA1(val) bfin_write16(CAN_MB24_DATA1, val)
-#define bfin_read_CAN_MB24_DATA2() bfin_read16(CAN_MB24_DATA2)
-#define bfin_write_CAN_MB24_DATA2(val) bfin_write16(CAN_MB24_DATA2, val)
-#define bfin_read_CAN_MB24_DATA3() bfin_read16(CAN_MB24_DATA3)
-#define bfin_write_CAN_MB24_DATA3(val) bfin_write16(CAN_MB24_DATA3, val)
-#define bfin_read_CAN_MB24_LENGTH() bfin_read16(CAN_MB24_LENGTH)
-#define bfin_write_CAN_MB24_LENGTH(val) bfin_write16(CAN_MB24_LENGTH, val)
-#define bfin_read_CAN_MB24_TIMESTAMP() bfin_read16(CAN_MB24_TIMESTAMP)
-#define bfin_write_CAN_MB24_TIMESTAMP(val) bfin_write16(CAN_MB24_TIMESTAMP, val)
-#define bfin_read_CAN_MB24_ID0() bfin_read16(CAN_MB24_ID0)
-#define bfin_write_CAN_MB24_ID0(val) bfin_write16(CAN_MB24_ID0, val)
-#define bfin_read_CAN_MB24_ID1() bfin_read16(CAN_MB24_ID1)
-#define bfin_write_CAN_MB24_ID1(val) bfin_write16(CAN_MB24_ID1, val)
-#define bfin_read_CAN_MB25_DATA0() bfin_read16(CAN_MB25_DATA0)
-#define bfin_write_CAN_MB25_DATA0(val) bfin_write16(CAN_MB25_DATA0, val)
-#define bfin_read_CAN_MB25_DATA1() bfin_read16(CAN_MB25_DATA1)
-#define bfin_write_CAN_MB25_DATA1(val) bfin_write16(CAN_MB25_DATA1, val)
-#define bfin_read_CAN_MB25_DATA2() bfin_read16(CAN_MB25_DATA2)
-#define bfin_write_CAN_MB25_DATA2(val) bfin_write16(CAN_MB25_DATA2, val)
-#define bfin_read_CAN_MB25_DATA3() bfin_read16(CAN_MB25_DATA3)
-#define bfin_write_CAN_MB25_DATA3(val) bfin_write16(CAN_MB25_DATA3, val)
-#define bfin_read_CAN_MB25_LENGTH() bfin_read16(CAN_MB25_LENGTH)
-#define bfin_write_CAN_MB25_LENGTH(val) bfin_write16(CAN_MB25_LENGTH, val)
-#define bfin_read_CAN_MB25_TIMESTAMP() bfin_read16(CAN_MB25_TIMESTAMP)
-#define bfin_write_CAN_MB25_TIMESTAMP(val) bfin_write16(CAN_MB25_TIMESTAMP, val)
-#define bfin_read_CAN_MB25_ID0() bfin_read16(CAN_MB25_ID0)
-#define bfin_write_CAN_MB25_ID0(val) bfin_write16(CAN_MB25_ID0, val)
-#define bfin_read_CAN_MB25_ID1() bfin_read16(CAN_MB25_ID1)
-#define bfin_write_CAN_MB25_ID1(val) bfin_write16(CAN_MB25_ID1, val)
-#define bfin_read_CAN_MB26_DATA0() bfin_read16(CAN_MB26_DATA0)
-#define bfin_write_CAN_MB26_DATA0(val) bfin_write16(CAN_MB26_DATA0, val)
-#define bfin_read_CAN_MB26_DATA1() bfin_read16(CAN_MB26_DATA1)
-#define bfin_write_CAN_MB26_DATA1(val) bfin_write16(CAN_MB26_DATA1, val)
-#define bfin_read_CAN_MB26_DATA2() bfin_read16(CAN_MB26_DATA2)
-#define bfin_write_CAN_MB26_DATA2(val) bfin_write16(CAN_MB26_DATA2, val)
-#define bfin_read_CAN_MB26_DATA3() bfin_read16(CAN_MB26_DATA3)
-#define bfin_write_CAN_MB26_DATA3(val) bfin_write16(CAN_MB26_DATA3, val)
-#define bfin_read_CAN_MB26_LENGTH() bfin_read16(CAN_MB26_LENGTH)
-#define bfin_write_CAN_MB26_LENGTH(val) bfin_write16(CAN_MB26_LENGTH, val)
-#define bfin_read_CAN_MB26_TIMESTAMP() bfin_read16(CAN_MB26_TIMESTAMP)
-#define bfin_write_CAN_MB26_TIMESTAMP(val) bfin_write16(CAN_MB26_TIMESTAMP, val)
-#define bfin_read_CAN_MB26_ID0() bfin_read16(CAN_MB26_ID0)
-#define bfin_write_CAN_MB26_ID0(val) bfin_write16(CAN_MB26_ID0, val)
-#define bfin_read_CAN_MB26_ID1() bfin_read16(CAN_MB26_ID1)
-#define bfin_write_CAN_MB26_ID1(val) bfin_write16(CAN_MB26_ID1, val)
-#define bfin_read_CAN_MB27_DATA0() bfin_read16(CAN_MB27_DATA0)
-#define bfin_write_CAN_MB27_DATA0(val) bfin_write16(CAN_MB27_DATA0, val)
-#define bfin_read_CAN_MB27_DATA1() bfin_read16(CAN_MB27_DATA1)
-#define bfin_write_CAN_MB27_DATA1(val) bfin_write16(CAN_MB27_DATA1, val)
-#define bfin_read_CAN_MB27_DATA2() bfin_read16(CAN_MB27_DATA2)
-#define bfin_write_CAN_MB27_DATA2(val) bfin_write16(CAN_MB27_DATA2, val)
-#define bfin_read_CAN_MB27_DATA3() bfin_read16(CAN_MB27_DATA3)
-#define bfin_write_CAN_MB27_DATA3(val) bfin_write16(CAN_MB27_DATA3, val)
-#define bfin_read_CAN_MB27_LENGTH() bfin_read16(CAN_MB27_LENGTH)
-#define bfin_write_CAN_MB27_LENGTH(val) bfin_write16(CAN_MB27_LENGTH, val)
-#define bfin_read_CAN_MB27_TIMESTAMP() bfin_read16(CAN_MB27_TIMESTAMP)
-#define bfin_write_CAN_MB27_TIMESTAMP(val) bfin_write16(CAN_MB27_TIMESTAMP, val)
-#define bfin_read_CAN_MB27_ID0() bfin_read16(CAN_MB27_ID0)
-#define bfin_write_CAN_MB27_ID0(val) bfin_write16(CAN_MB27_ID0, val)
-#define bfin_read_CAN_MB27_ID1() bfin_read16(CAN_MB27_ID1)
-#define bfin_write_CAN_MB27_ID1(val) bfin_write16(CAN_MB27_ID1, val)
-#define bfin_read_CAN_MB28_DATA0() bfin_read16(CAN_MB28_DATA0)
-#define bfin_write_CAN_MB28_DATA0(val) bfin_write16(CAN_MB28_DATA0, val)
-#define bfin_read_CAN_MB28_DATA1() bfin_read16(CAN_MB28_DATA1)
-#define bfin_write_CAN_MB28_DATA1(val) bfin_write16(CAN_MB28_DATA1, val)
-#define bfin_read_CAN_MB28_DATA2() bfin_read16(CAN_MB28_DATA2)
-#define bfin_write_CAN_MB28_DATA2(val) bfin_write16(CAN_MB28_DATA2, val)
-#define bfin_read_CAN_MB28_DATA3() bfin_read16(CAN_MB28_DATA3)
-#define bfin_write_CAN_MB28_DATA3(val) bfin_write16(CAN_MB28_DATA3, val)
-#define bfin_read_CAN_MB28_LENGTH() bfin_read16(CAN_MB28_LENGTH)
-#define bfin_write_CAN_MB28_LENGTH(val) bfin_write16(CAN_MB28_LENGTH, val)
-#define bfin_read_CAN_MB28_TIMESTAMP() bfin_read16(CAN_MB28_TIMESTAMP)
-#define bfin_write_CAN_MB28_TIMESTAMP(val) bfin_write16(CAN_MB28_TIMESTAMP, val)
-#define bfin_read_CAN_MB28_ID0() bfin_read16(CAN_MB28_ID0)
-#define bfin_write_CAN_MB28_ID0(val) bfin_write16(CAN_MB28_ID0, val)
-#define bfin_read_CAN_MB28_ID1() bfin_read16(CAN_MB28_ID1)
-#define bfin_write_CAN_MB28_ID1(val) bfin_write16(CAN_MB28_ID1, val)
-#define bfin_read_CAN_MB29_DATA0() bfin_read16(CAN_MB29_DATA0)
-#define bfin_write_CAN_MB29_DATA0(val) bfin_write16(CAN_MB29_DATA0, val)
-#define bfin_read_CAN_MB29_DATA1() bfin_read16(CAN_MB29_DATA1)
-#define bfin_write_CAN_MB29_DATA1(val) bfin_write16(CAN_MB29_DATA1, val)
-#define bfin_read_CAN_MB29_DATA2() bfin_read16(CAN_MB29_DATA2)
-#define bfin_write_CAN_MB29_DATA2(val) bfin_write16(CAN_MB29_DATA2, val)
-#define bfin_read_CAN_MB29_DATA3() bfin_read16(CAN_MB29_DATA3)
-#define bfin_write_CAN_MB29_DATA3(val) bfin_write16(CAN_MB29_DATA3, val)
-#define bfin_read_CAN_MB29_LENGTH() bfin_read16(CAN_MB29_LENGTH)
-#define bfin_write_CAN_MB29_LENGTH(val) bfin_write16(CAN_MB29_LENGTH, val)
-#define bfin_read_CAN_MB29_TIMESTAMP() bfin_read16(CAN_MB29_TIMESTAMP)
-#define bfin_write_CAN_MB29_TIMESTAMP(val) bfin_write16(CAN_MB29_TIMESTAMP, val)
-#define bfin_read_CAN_MB29_ID0() bfin_read16(CAN_MB29_ID0)
-#define bfin_write_CAN_MB29_ID0(val) bfin_write16(CAN_MB29_ID0, val)
-#define bfin_read_CAN_MB29_ID1() bfin_read16(CAN_MB29_ID1)
-#define bfin_write_CAN_MB29_ID1(val) bfin_write16(CAN_MB29_ID1, val)
-#define bfin_read_CAN_MB30_DATA0() bfin_read16(CAN_MB30_DATA0)
-#define bfin_write_CAN_MB30_DATA0(val) bfin_write16(CAN_MB30_DATA0, val)
-#define bfin_read_CAN_MB30_DATA1() bfin_read16(CAN_MB30_DATA1)
-#define bfin_write_CAN_MB30_DATA1(val) bfin_write16(CAN_MB30_DATA1, val)
-#define bfin_read_CAN_MB30_DATA2() bfin_read16(CAN_MB30_DATA2)
-#define bfin_write_CAN_MB30_DATA2(val) bfin_write16(CAN_MB30_DATA2, val)
-#define bfin_read_CAN_MB30_DATA3() bfin_read16(CAN_MB30_DATA3)
-#define bfin_write_CAN_MB30_DATA3(val) bfin_write16(CAN_MB30_DATA3, val)
-#define bfin_read_CAN_MB30_LENGTH() bfin_read16(CAN_MB30_LENGTH)
-#define bfin_write_CAN_MB30_LENGTH(val) bfin_write16(CAN_MB30_LENGTH, val)
-#define bfin_read_CAN_MB30_TIMESTAMP() bfin_read16(CAN_MB30_TIMESTAMP)
-#define bfin_write_CAN_MB30_TIMESTAMP(val) bfin_write16(CAN_MB30_TIMESTAMP, val)
-#define bfin_read_CAN_MB30_ID0() bfin_read16(CAN_MB30_ID0)
-#define bfin_write_CAN_MB30_ID0(val) bfin_write16(CAN_MB30_ID0, val)
-#define bfin_read_CAN_MB30_ID1() bfin_read16(CAN_MB30_ID1)
-#define bfin_write_CAN_MB30_ID1(val) bfin_write16(CAN_MB30_ID1, val)
-#define bfin_read_CAN_MB31_DATA0() bfin_read16(CAN_MB31_DATA0)
-#define bfin_write_CAN_MB31_DATA0(val) bfin_write16(CAN_MB31_DATA0, val)
-#define bfin_read_CAN_MB31_DATA1() bfin_read16(CAN_MB31_DATA1)
-#define bfin_write_CAN_MB31_DATA1(val) bfin_write16(CAN_MB31_DATA1, val)
-#define bfin_read_CAN_MB31_DATA2() bfin_read16(CAN_MB31_DATA2)
-#define bfin_write_CAN_MB31_DATA2(val) bfin_write16(CAN_MB31_DATA2, val)
-#define bfin_read_CAN_MB31_DATA3() bfin_read16(CAN_MB31_DATA3)
-#define bfin_write_CAN_MB31_DATA3(val) bfin_write16(CAN_MB31_DATA3, val)
-#define bfin_read_CAN_MB31_LENGTH() bfin_read16(CAN_MB31_LENGTH)
-#define bfin_write_CAN_MB31_LENGTH(val) bfin_write16(CAN_MB31_LENGTH, val)
-#define bfin_read_CAN_MB31_TIMESTAMP() bfin_read16(CAN_MB31_TIMESTAMP)
-#define bfin_write_CAN_MB31_TIMESTAMP(val) bfin_write16(CAN_MB31_TIMESTAMP, val)
-#define bfin_read_CAN_MB31_ID0() bfin_read16(CAN_MB31_ID0)
-#define bfin_write_CAN_MB31_ID0(val) bfin_write16(CAN_MB31_ID0, val)
-#define bfin_read_CAN_MB31_ID1() bfin_read16(CAN_MB31_ID1)
-#define bfin_write_CAN_MB31_ID1(val) bfin_write16(CAN_MB31_ID1, val)
-
-#endif
+++ /dev/null
-/*
- * Copyright 2008-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CDEF_BF539_H
-#define _CDEF_BF539_H
-
-/* Include MMRs Common to BF538 */
-#include "cdefBF538.h"
-
-#define bfin_read_MXVR_CONFIG() bfin_read16(MXVR_CONFIG)
-#define bfin_write_MXVR_CONFIG(val) bfin_write16(MXVR_CONFIG, val)
-#define bfin_read_MXVR_PLL_CTL_0() bfin_read32(MXVR_PLL_CTL_0)
-#define bfin_write_MXVR_PLL_CTL_0(val) bfin_write32(MXVR_PLL_CTL_0, val)
-#define bfin_read_MXVR_STATE_0() bfin_read32(MXVR_STATE_0)
-#define bfin_write_MXVR_STATE_0(val) bfin_write32(MXVR_STATE_0, val)
-#define bfin_read_MXVR_STATE_1() bfin_read32(MXVR_STATE_1)
-#define bfin_write_MXVR_STATE_1(val) bfin_write32(MXVR_STATE_1, val)
-#define bfin_read_MXVR_INT_STAT_0() bfin_read32(MXVR_INT_STAT_0)
-#define bfin_write_MXVR_INT_STAT_0(val) bfin_write32(MXVR_INT_STAT_0, val)
-#define bfin_read_MXVR_INT_STAT_1() bfin_read32(MXVR_INT_STAT_1)
-#define bfin_write_MXVR_INT_STAT_1(val) bfin_write32(MXVR_INT_STAT_1, val)
-#define bfin_read_MXVR_INT_EN_0() bfin_read32(MXVR_INT_EN_0)
-#define bfin_write_MXVR_INT_EN_0(val) bfin_write32(MXVR_INT_EN_0, val)
-#define bfin_read_MXVR_INT_EN_1() bfin_read32(MXVR_INT_EN_1)
-#define bfin_write_MXVR_INT_EN_1(val) bfin_write32(MXVR_INT_EN_1, val)
-#define bfin_read_MXVR_POSITION() bfin_read16(MXVR_POSITION)
-#define bfin_write_MXVR_POSITION(val) bfin_write16(MXVR_POSITION, val)
-#define bfin_read_MXVR_MAX_POSITION() bfin_read16(MXVR_MAX_POSITION)
-#define bfin_write_MXVR_MAX_POSITION(val) bfin_write16(MXVR_MAX_POSITION, val)
-#define bfin_read_MXVR_DELAY() bfin_read16(MXVR_DELAY)
-#define bfin_write_MXVR_DELAY(val) bfin_write16(MXVR_DELAY, val)
-#define bfin_read_MXVR_MAX_DELAY() bfin_read16(MXVR_MAX_DELAY)
-#define bfin_write_MXVR_MAX_DELAY(val) bfin_write16(MXVR_MAX_DELAY, val)
-#define bfin_read_MXVR_LADDR() bfin_read32(MXVR_LADDR)
-#define bfin_write_MXVR_LADDR(val) bfin_write32(MXVR_LADDR, val)
-#define bfin_read_MXVR_GADDR() bfin_read16(MXVR_GADDR)
-#define bfin_write_MXVR_GADDR(val) bfin_write16(MXVR_GADDR, val)
-#define bfin_read_MXVR_AADDR() bfin_read32(MXVR_AADDR)
-#define bfin_write_MXVR_AADDR(val) bfin_write32(MXVR_AADDR, val)
-#define bfin_read_MXVR_ALLOC_0() bfin_read32(MXVR_ALLOC_0)
-#define bfin_write_MXVR_ALLOC_0(val) bfin_write32(MXVR_ALLOC_0, val)
-#define bfin_read_MXVR_ALLOC_1() bfin_read32(MXVR_ALLOC_1)
-#define bfin_write_MXVR_ALLOC_1(val) bfin_write32(MXVR_ALLOC_1, val)
-#define bfin_read_MXVR_ALLOC_2() bfin_read32(MXVR_ALLOC_2)
-#define bfin_write_MXVR_ALLOC_2(val) bfin_write32(MXVR_ALLOC_2, val)
-#define bfin_read_MXVR_ALLOC_3() bfin_read32(MXVR_ALLOC_3)
-#define bfin_write_MXVR_ALLOC_3(val) bfin_write32(MXVR_ALLOC_3, val)
-#define bfin_read_MXVR_ALLOC_4() bfin_read32(MXVR_ALLOC_4)
-#define bfin_write_MXVR_ALLOC_4(val) bfin_write32(MXVR_ALLOC_4, val)
-#define bfin_read_MXVR_ALLOC_5() bfin_read32(MXVR_ALLOC_5)
-#define bfin_write_MXVR_ALLOC_5(val) bfin_write32(MXVR_ALLOC_5, val)
-#define bfin_read_MXVR_ALLOC_6() bfin_read32(MXVR_ALLOC_6)
-#define bfin_write_MXVR_ALLOC_6(val) bfin_write32(MXVR_ALLOC_6, val)
-#define bfin_read_MXVR_ALLOC_7() bfin_read32(MXVR_ALLOC_7)
-#define bfin_write_MXVR_ALLOC_7(val) bfin_write32(MXVR_ALLOC_7, val)
-#define bfin_read_MXVR_ALLOC_8() bfin_read32(MXVR_ALLOC_8)
-#define bfin_write_MXVR_ALLOC_8(val) bfin_write32(MXVR_ALLOC_8, val)
-#define bfin_read_MXVR_ALLOC_9() bfin_read32(MXVR_ALLOC_9)
-#define bfin_write_MXVR_ALLOC_9(val) bfin_write32(MXVR_ALLOC_9, val)
-#define bfin_read_MXVR_ALLOC_10() bfin_read32(MXVR_ALLOC_10)
-#define bfin_write_MXVR_ALLOC_10(val) bfin_write32(MXVR_ALLOC_10, val)
-#define bfin_read_MXVR_ALLOC_11() bfin_read32(MXVR_ALLOC_11)
-#define bfin_write_MXVR_ALLOC_11(val) bfin_write32(MXVR_ALLOC_11, val)
-#define bfin_read_MXVR_ALLOC_12() bfin_read32(MXVR_ALLOC_12)
-#define bfin_write_MXVR_ALLOC_12(val) bfin_write32(MXVR_ALLOC_12, val)
-#define bfin_read_MXVR_ALLOC_13() bfin_read32(MXVR_ALLOC_13)
-#define bfin_write_MXVR_ALLOC_13(val) bfin_write32(MXVR_ALLOC_13, val)
-#define bfin_read_MXVR_ALLOC_14() bfin_read32(MXVR_ALLOC_14)
-#define bfin_write_MXVR_ALLOC_14(val) bfin_write32(MXVR_ALLOC_14, val)
-#define bfin_read_MXVR_SYNC_LCHAN_0() bfin_read32(MXVR_SYNC_LCHAN_0)
-#define bfin_write_MXVR_SYNC_LCHAN_0(val) bfin_write32(MXVR_SYNC_LCHAN_0, val)
-#define bfin_read_MXVR_SYNC_LCHAN_1() bfin_read32(MXVR_SYNC_LCHAN_1)
-#define bfin_write_MXVR_SYNC_LCHAN_1(val) bfin_write32(MXVR_SYNC_LCHAN_1, val)
-#define bfin_read_MXVR_SYNC_LCHAN_2() bfin_read32(MXVR_SYNC_LCHAN_2)
-#define bfin_write_MXVR_SYNC_LCHAN_2(val) bfin_write32(MXVR_SYNC_LCHAN_2, val)
-#define bfin_read_MXVR_SYNC_LCHAN_3() bfin_read32(MXVR_SYNC_LCHAN_3)
-#define bfin_write_MXVR_SYNC_LCHAN_3(val) bfin_write32(MXVR_SYNC_LCHAN_3, val)
-#define bfin_read_MXVR_SYNC_LCHAN_4() bfin_read32(MXVR_SYNC_LCHAN_4)
-#define bfin_write_MXVR_SYNC_LCHAN_4(val) bfin_write32(MXVR_SYNC_LCHAN_4, val)
-#define bfin_read_MXVR_SYNC_LCHAN_5() bfin_read32(MXVR_SYNC_LCHAN_5)
-#define bfin_write_MXVR_SYNC_LCHAN_5(val) bfin_write32(MXVR_SYNC_LCHAN_5, val)
-#define bfin_read_MXVR_SYNC_LCHAN_6() bfin_read32(MXVR_SYNC_LCHAN_6)
-#define bfin_write_MXVR_SYNC_LCHAN_6(val) bfin_write32(MXVR_SYNC_LCHAN_6, val)
-#define bfin_read_MXVR_SYNC_LCHAN_7() bfin_read32(MXVR_SYNC_LCHAN_7)
-#define bfin_write_MXVR_SYNC_LCHAN_7(val) bfin_write32(MXVR_SYNC_LCHAN_7, val)
-#define bfin_read_MXVR_DMA0_CONFIG() bfin_read32(MXVR_DMA0_CONFIG)
-#define bfin_write_MXVR_DMA0_CONFIG(val) bfin_write32(MXVR_DMA0_CONFIG, val)
-#define bfin_read_MXVR_DMA0_START_ADDR() bfin_readPTR(MXVR_DMA0_START_ADDR)
-#define bfin_write_MXVR_DMA0_START_ADDR(val) bfin_writePTR(MXVR_DMA0_START_ADDR, val)
-#define bfin_read_MXVR_DMA0_COUNT() bfin_read16(MXVR_DMA0_COUNT)
-#define bfin_write_MXVR_DMA0_COUNT(val) bfin_write16(MXVR_DMA0_COUNT, val)
-#define bfin_read_MXVR_DMA0_CURR_ADDR() bfin_readPTR(MXVR_DMA0_CURR_ADDR)
-#define bfin_write_MXVR_DMA0_CURR_ADDR(val) bfin_writePTR(MXVR_DMA0_CURR_ADDR, val)
-#define bfin_read_MXVR_DMA0_CURR_COUNT() bfin_read16(MXVR_DMA0_CURR_COUNT)
-#define bfin_write_MXVR_DMA0_CURR_COUNT(val) bfin_write16(MXVR_DMA0_CURR_COUNT, val)
-#define bfin_read_MXVR_DMA1_CONFIG() bfin_read32(MXVR_DMA1_CONFIG)
-#define bfin_write_MXVR_DMA1_CONFIG(val) bfin_write32(MXVR_DMA1_CONFIG, val)
-#define bfin_read_MXVR_DMA1_START_ADDR() bfin_readPTR(MXVR_DMA1_START_ADDR)
-#define bfin_write_MXVR_DMA1_START_ADDR(val) bfin_writePTR(MXVR_DMA1_START_ADDR, val)
-#define bfin_read_MXVR_DMA1_COUNT() bfin_read16(MXVR_DMA1_COUNT)
-#define bfin_write_MXVR_DMA1_COUNT(val) bfin_write16(MXVR_DMA1_COUNT, val)
-#define bfin_read_MXVR_DMA1_CURR_ADDR() bfin_readPTR(MXVR_DMA1_CURR_ADDR)
-#define bfin_write_MXVR_DMA1_CURR_ADDR(val) bfin_writePTR(MXVR_DMA1_CURR_ADDR, val)
-#define bfin_read_MXVR_DMA1_CURR_COUNT() bfin_read16(MXVR_DMA1_CURR_COUNT)
-#define bfin_write_MXVR_DMA1_CURR_COUNT(val) bfin_write16(MXVR_DMA1_CURR_COUNT, val)
-#define bfin_read_MXVR_DMA2_CONFIG() bfin_read32(MXVR_DMA2_CONFIG)
-#define bfin_write_MXVR_DMA2_CONFIG(val) bfin_write32(MXVR_DMA2_CONFIG, val)
-#define bfin_read_MXVR_DMA2_START_ADDR() bfin_readPTR(MXVR_DMA2_START_ADDR)
-#define bfin_write_MXVR_DMA2_START_ADDR(val) bfin_writePTR(MXVR_DMA2_START_ADDR, val)
-#define bfin_read_MXVR_DMA2_COUNT() bfin_read16(MXVR_DMA2_COUNT)
-#define bfin_write_MXVR_DMA2_COUNT(val) bfin_write16(MXVR_DMA2_COUNT, val)
-#define bfin_read_MXVR_DMA2_CURR_ADDR() bfin_readPTR(MXVR_DMA2_CURR_ADDR)
-#define bfin_write_MXVR_DMA2_CURR_ADDR(val) bfin_writePTR(MXVR_DMA2_CURR_ADDR, val)
-#define bfin_read_MXVR_DMA2_CURR_COUNT() bfin_read16(MXVR_DMA2_CURR_COUNT)
-#define bfin_write_MXVR_DMA2_CURR_COUNT(val) bfin_write16(MXVR_DMA2_CURR_COUNT, val)
-#define bfin_read_MXVR_DMA3_CONFIG() bfin_read32(MXVR_DMA3_CONFIG)
-#define bfin_write_MXVR_DMA3_CONFIG(val) bfin_write32(MXVR_DMA3_CONFIG, val)
-#define bfin_read_MXVR_DMA3_START_ADDR() bfin_readPTR(MXVR_DMA3_START_ADDR)
-#define bfin_write_MXVR_DMA3_START_ADDR(val) bfin_writePTR(MXVR_DMA3_START_ADDR, val)
-#define bfin_read_MXVR_DMA3_COUNT() bfin_read16(MXVR_DMA3_COUNT)
-#define bfin_write_MXVR_DMA3_COUNT(val) bfin_write16(MXVR_DMA3_COUNT, val)
-#define bfin_read_MXVR_DMA3_CURR_ADDR() bfin_readPTR(MXVR_DMA3_CURR_ADDR)
-#define bfin_write_MXVR_DMA3_CURR_ADDR(val) bfin_writePTR(MXVR_DMA3_CURR_ADDR, val)
-#define bfin_read_MXVR_DMA3_CURR_COUNT() bfin_read16(MXVR_DMA3_CURR_COUNT)
-#define bfin_write_MXVR_DMA3_CURR_COUNT(val) bfin_write16(MXVR_DMA3_CURR_COUNT, val)
-#define bfin_read_MXVR_DMA4_CONFIG() bfin_read32(MXVR_DMA4_CONFIG)
-#define bfin_write_MXVR_DMA4_CONFIG(val) bfin_write32(MXVR_DMA4_CONFIG, val)
-#define bfin_read_MXVR_DMA4_START_ADDR() bfin_readPTR(MXVR_DMA4_START_ADDR)
-#define bfin_write_MXVR_DMA4_START_ADDR(val) bfin_writePTR(MXVR_DMA4_START_ADDR, val)
-#define bfin_read_MXVR_DMA4_COUNT() bfin_read16(MXVR_DMA4_COUNT)
-#define bfin_write_MXVR_DMA4_COUNT(val) bfin_write16(MXVR_DMA4_COUNT, val)
-#define bfin_read_MXVR_DMA4_CURR_ADDR() bfin_readPTR(MXVR_DMA4_CURR_ADDR)
-#define bfin_write_MXVR_DMA4_CURR_ADDR(val) bfin_writePTR(MXVR_DMA4_CURR_ADDR, val)
-#define bfin_read_MXVR_DMA4_CURR_COUNT() bfin_read16(MXVR_DMA4_CURR_COUNT)
-#define bfin_write_MXVR_DMA4_CURR_COUNT(val) bfin_write16(MXVR_DMA4_CURR_COUNT, val)
-#define bfin_read_MXVR_DMA5_CONFIG() bfin_read32(MXVR_DMA5_CONFIG)
-#define bfin_write_MXVR_DMA5_CONFIG(val) bfin_write32(MXVR_DMA5_CONFIG, val)
-#define bfin_read_MXVR_DMA5_START_ADDR() bfin_readPTR(MXVR_DMA5_START_ADDR)
-#define bfin_write_MXVR_DMA5_START_ADDR(val) bfin_writePTR(MXVR_DMA5_START_ADDR, val)
-#define bfin_read_MXVR_DMA5_COUNT() bfin_read16(MXVR_DMA5_COUNT)
-#define bfin_write_MXVR_DMA5_COUNT(val) bfin_write16(MXVR_DMA5_COUNT, val)
-#define bfin_read_MXVR_DMA5_CURR_ADDR() bfin_readPTR(MXVR_DMA5_CURR_ADDR)
-#define bfin_write_MXVR_DMA5_CURR_ADDR(val) bfin_writePTR(MXVR_DMA5_CURR_ADDR, val)
-#define bfin_read_MXVR_DMA5_CURR_COUNT() bfin_read16(MXVR_DMA5_CURR_COUNT)
-#define bfin_write_MXVR_DMA5_CURR_COUNT(val) bfin_write16(MXVR_DMA5_CURR_COUNT, val)
-#define bfin_read_MXVR_DMA6_CONFIG() bfin_read32(MXVR_DMA6_CONFIG)
-#define bfin_write_MXVR_DMA6_CONFIG(val) bfin_write32(MXVR_DMA6_CONFIG, val)
-#define bfin_read_MXVR_DMA6_START_ADDR() bfin_readPTR(MXVR_DMA6_START_ADDR)
-#define bfin_write_MXVR_DMA6_START_ADDR(val) bfin_writePTR(MXVR_DMA6_START_ADDR, val)
-#define bfin_read_MXVR_DMA6_COUNT() bfin_read16(MXVR_DMA6_COUNT)
-#define bfin_write_MXVR_DMA6_COUNT(val) bfin_write16(MXVR_DMA6_COUNT, val)
-#define bfin_read_MXVR_DMA6_CURR_ADDR() bfin_readPTR(MXVR_DMA6_CURR_ADDR)
-#define bfin_write_MXVR_DMA6_CURR_ADDR(val) bfin_writePTR(MXVR_DMA6_CURR_ADDR, val)
-#define bfin_read_MXVR_DMA6_CURR_COUNT() bfin_read16(MXVR_DMA6_CURR_COUNT)
-#define bfin_write_MXVR_DMA6_CURR_COUNT(val) bfin_write16(MXVR_DMA6_CURR_COUNT, val)
-#define bfin_read_MXVR_DMA7_CONFIG() bfin_read32(MXVR_DMA7_CONFIG)
-#define bfin_write_MXVR_DMA7_CONFIG(val) bfin_write32(MXVR_DMA7_CONFIG, val)
-#define bfin_read_MXVR_DMA7_START_ADDR() bfin_readPTR(MXVR_DMA7_START_ADDR)
-#define bfin_write_MXVR_DMA7_START_ADDR(val) bfin_writePTR(MXVR_DMA7_START_ADDR, val)
-#define bfin_read_MXVR_DMA7_COUNT() bfin_read16(MXVR_DMA7_COUNT)
-#define bfin_write_MXVR_DMA7_COUNT(val) bfin_write16(MXVR_DMA7_COUNT, val)
-#define bfin_read_MXVR_DMA7_CURR_ADDR() bfin_readPTR(MXVR_DMA7_CURR_ADDR)
-#define bfin_write_MXVR_DMA7_CURR_ADDR(val) bfin_writePTR(MXVR_DMA7_CURR_ADDR, val)
-#define bfin_read_MXVR_DMA7_CURR_COUNT() bfin_read16(MXVR_DMA7_CURR_COUNT)
-#define bfin_write_MXVR_DMA7_CURR_COUNT(val) bfin_write16(MXVR_DMA7_CURR_COUNT, val)
-#define bfin_read_MXVR_AP_CTL() bfin_read16(MXVR_AP_CTL)
-#define bfin_write_MXVR_AP_CTL(val) bfin_write16(MXVR_AP_CTL, val)
-#define bfin_read_MXVR_APRB_START_ADDR() bfin_readPTR(MXVR_APRB_START_ADDR)
-#define bfin_write_MXVR_APRB_START_ADDR(val) bfin_writePTR(MXVR_APRB_START_ADDR, val)
-#define bfin_read_MXVR_APRB_CURR_ADDR() bfin_readPTR(MXVR_APRB_CURR_ADDR)
-#define bfin_write_MXVR_APRB_CURR_ADDR(val) bfin_writePTR(MXVR_APRB_CURR_ADDR, val)
-#define bfin_read_MXVR_APTB_START_ADDR() bfin_readPTR(MXVR_APTB_START_ADDR)
-#define bfin_write_MXVR_APTB_START_ADDR(val) bfin_writePTR(MXVR_APTB_START_ADDR, val)
-#define bfin_read_MXVR_APTB_CURR_ADDR() bfin_readPTR(MXVR_APTB_CURR_ADDR)
-#define bfin_write_MXVR_APTB_CURR_ADDR(val) bfin_writePTR(MXVR_APTB_CURR_ADDR, val)
-#define bfin_read_MXVR_CM_CTL() bfin_read32(MXVR_CM_CTL)
-#define bfin_write_MXVR_CM_CTL(val) bfin_write32(MXVR_CM_CTL, val)
-#define bfin_read_MXVR_CMRB_START_ADDR() bfin_readPTR(MXVR_CMRB_START_ADDR)
-#define bfin_write_MXVR_CMRB_START_ADDR(val) bfin_writePTR(MXVR_CMRB_START_ADDR, val)
-#define bfin_read_MXVR_CMRB_CURR_ADDR() bfin_readPTR(MXVR_CMRB_CURR_ADDR)
-#define bfin_write_MXVR_CMRB_CURR_ADDR(val) bfin_writePTR(MXVR_CMRB_CURR_ADDR, val)
-#define bfin_read_MXVR_CMTB_START_ADDR() bfin_readPTR(MXVR_CMTB_START_ADDR)
-#define bfin_write_MXVR_CMTB_START_ADDR(val) bfin_writePTR(MXVR_CMTB_START_ADDR, val)
-#define bfin_read_MXVR_CMTB_CURR_ADDR() bfin_readPTR(MXVR_CMTB_CURR_ADDR)
-#define bfin_write_MXVR_CMTB_CURR_ADDR(val) bfin_writePTR(MXVR_CMTB_CURR_ADDR, val)
-#define bfin_read_MXVR_RRDB_START_ADDR() bfin_readPTR(MXVR_RRDB_START_ADDR)
-#define bfin_write_MXVR_RRDB_START_ADDR(val) bfin_writePTR(MXVR_RRDB_START_ADDR, val)
-#define bfin_read_MXVR_RRDB_CURR_ADDR() bfin_readPTR(MXVR_RRDB_CURR_ADDR)
-#define bfin_write_MXVR_RRDB_CURR_ADDR(val) bfin_writePTR(MXVR_RRDB_CURR_ADDR, val)
-#define bfin_read_MXVR_PAT_DATA_0() bfin_read32(MXVR_PAT_DATA_0)
-#define bfin_write_MXVR_PAT_DATA_0(val) bfin_write32(MXVR_PAT_DATA_0, val)
-#define bfin_read_MXVR_PAT_EN_0() bfin_read32(MXVR_PAT_EN_0)
-#define bfin_write_MXVR_PAT_EN_0(val) bfin_write32(MXVR_PAT_EN_0, val)
-#define bfin_read_MXVR_PAT_DATA_1() bfin_read32(MXVR_PAT_DATA_1)
-#define bfin_write_MXVR_PAT_DATA_1(val) bfin_write32(MXVR_PAT_DATA_1, val)
-#define bfin_read_MXVR_PAT_EN_1() bfin_read32(MXVR_PAT_EN_1)
-#define bfin_write_MXVR_PAT_EN_1(val) bfin_write32(MXVR_PAT_EN_1, val)
-#define bfin_read_MXVR_FRAME_CNT_0() bfin_read16(MXVR_FRAME_CNT_0)
-#define bfin_write_MXVR_FRAME_CNT_0(val) bfin_write16(MXVR_FRAME_CNT_0, val)
-#define bfin_read_MXVR_FRAME_CNT_1() bfin_read16(MXVR_FRAME_CNT_1)
-#define bfin_write_MXVR_FRAME_CNT_1(val) bfin_write16(MXVR_FRAME_CNT_1, val)
-#define bfin_read_MXVR_ROUTING_0() bfin_read32(MXVR_ROUTING_0)
-#define bfin_write_MXVR_ROUTING_0(val) bfin_write32(MXVR_ROUTING_0, val)
-#define bfin_read_MXVR_ROUTING_1() bfin_read32(MXVR_ROUTING_1)
-#define bfin_write_MXVR_ROUTING_1(val) bfin_write32(MXVR_ROUTING_1, val)
-#define bfin_read_MXVR_ROUTING_2() bfin_read32(MXVR_ROUTING_2)
-#define bfin_write_MXVR_ROUTING_2(val) bfin_write32(MXVR_ROUTING_2, val)
-#define bfin_read_MXVR_ROUTING_3() bfin_read32(MXVR_ROUTING_3)
-#define bfin_write_MXVR_ROUTING_3(val) bfin_write32(MXVR_ROUTING_3, val)
-#define bfin_read_MXVR_ROUTING_4() bfin_read32(MXVR_ROUTING_4)
-#define bfin_write_MXVR_ROUTING_4(val) bfin_write32(MXVR_ROUTING_4, val)
-#define bfin_read_MXVR_ROUTING_5() bfin_read32(MXVR_ROUTING_5)
-#define bfin_write_MXVR_ROUTING_5(val) bfin_write32(MXVR_ROUTING_5, val)
-#define bfin_read_MXVR_ROUTING_6() bfin_read32(MXVR_ROUTING_6)
-#define bfin_write_MXVR_ROUTING_6(val) bfin_write32(MXVR_ROUTING_6, val)
-#define bfin_read_MXVR_ROUTING_7() bfin_read32(MXVR_ROUTING_7)
-#define bfin_write_MXVR_ROUTING_7(val) bfin_write32(MXVR_ROUTING_7, val)
-#define bfin_read_MXVR_ROUTING_8() bfin_read32(MXVR_ROUTING_8)
-#define bfin_write_MXVR_ROUTING_8(val) bfin_write32(MXVR_ROUTING_8, val)
-#define bfin_read_MXVR_ROUTING_9() bfin_read32(MXVR_ROUTING_9)
-#define bfin_write_MXVR_ROUTING_9(val) bfin_write32(MXVR_ROUTING_9, val)
-#define bfin_read_MXVR_ROUTING_10() bfin_read32(MXVR_ROUTING_10)
-#define bfin_write_MXVR_ROUTING_10(val) bfin_write32(MXVR_ROUTING_10, val)
-#define bfin_read_MXVR_ROUTING_11() bfin_read32(MXVR_ROUTING_11)
-#define bfin_write_MXVR_ROUTING_11(val) bfin_write32(MXVR_ROUTING_11, val)
-#define bfin_read_MXVR_ROUTING_12() bfin_read32(MXVR_ROUTING_12)
-#define bfin_write_MXVR_ROUTING_12(val) bfin_write32(MXVR_ROUTING_12, val)
-#define bfin_read_MXVR_ROUTING_13() bfin_read32(MXVR_ROUTING_13)
-#define bfin_write_MXVR_ROUTING_13(val) bfin_write32(MXVR_ROUTING_13, val)
-#define bfin_read_MXVR_ROUTING_14() bfin_read32(MXVR_ROUTING_14)
-#define bfin_write_MXVR_ROUTING_14(val) bfin_write32(MXVR_ROUTING_14, val)
-#define bfin_read_MXVR_PLL_CTL_1() bfin_read32(MXVR_PLL_CTL_1)
-#define bfin_write_MXVR_PLL_CTL_1(val) bfin_write32(MXVR_PLL_CTL_1, val)
-#define bfin_read_MXVR_BLOCK_CNT() bfin_read16(MXVR_BLOCK_CNT)
-#define bfin_write_MXVR_BLOCK_CNT(val) bfin_write16(MXVR_BLOCK_CNT, val)
-
-#endif /* _CDEF_BF539_H */
+++ /dev/null
-/*
- * Copyright 2008-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF538_H
-#define _DEF_BF538_H
-
-/* Clock/Regulator Control (0xFFC00000 - 0xFFC000FF) */
-#define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */
-#define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */
-#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */
-#define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */
-#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */
-#define CHIPID 0xFFC00014 /* Chip ID Register */
-
-/* CHIPID Masks */
-#define CHIPID_VERSION 0xF0000000
-#define CHIPID_FAMILY 0x0FFFF000
-#define CHIPID_MANUFACTURE 0x00000FFE
-
-/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
-#define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */
-#define SYSCR 0xFFC00104 /* System Configuration registe */
-#define SIC_RVECT 0xFFC00108
-#define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */
-#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
-#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
-#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
-#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */
-#define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */
-#define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */
-#define SIC_IMASK1 0xFFC00128 /* Interrupt Mask Register 1 */
-#define SIC_ISR1 0xFFC0012C /* Interrupt Status Register 1 */
-#define SIC_IWR1 0xFFC00130 /* Interrupt Wakeup Register 1 */
-#define SIC_IAR4 0xFFC00134 /* Interrupt Assignment Register 4 */
-#define SIC_IAR5 0xFFC00138 /* Interrupt Assignment Register 5 */
-#define SIC_IAR6 0xFFC0013C /* Interrupt Assignment Register 6 */
-
-
-/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
-#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
-#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
-#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
-
-
-/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
-#define RTC_STAT 0xFFC00300 /* RTC Status Register */
-#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
-#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
-#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
-#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */
-#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */
-#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register (alternate macro) */
-
-
-/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
-#define UART0_THR 0xFFC00400 /* Transmit Holding register */
-#define UART0_RBR 0xFFC00400 /* Receive Buffer register */
-#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
-#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */
-#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
-#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */
-#define UART0_LCR 0xFFC0040C /* Line Control Register */
-#define UART0_MCR 0xFFC00410 /* Modem Control Register */
-#define UART0_LSR 0xFFC00414 /* Line Status Register */
-#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */
-#define UART0_GCTL 0xFFC00424 /* Global Control Register */
-
-
-/* SPI0 Controller (0xFFC00500 - 0xFFC005FF) */
-
-#define SPI0_CTL 0xFFC00500 /* SPI0 Control Register */
-#define SPI0_FLG 0xFFC00504 /* SPI0 Flag register */
-#define SPI0_STAT 0xFFC00508 /* SPI0 Status register */
-#define SPI0_TDBR 0xFFC0050C /* SPI0 Transmit Data Buffer Register */
-#define SPI0_RDBR 0xFFC00510 /* SPI0 Receive Data Buffer Register */
-#define SPI0_BAUD 0xFFC00514 /* SPI0 Baud rate Register */
-#define SPI0_SHADOW 0xFFC00518 /* SPI0_RDBR Shadow Register */
-#define SPI0_REGBASE SPI0_CTL
-
-
-/* TIMER 0, 1, 2 Registers (0xFFC00600 - 0xFFC006FF) */
-#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */
-#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */
-#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */
-#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */
-
-#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */
-#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */
-#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */
-#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */
-
-#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */
-#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */
-#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */
-#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */
-
-#define TIMER_ENABLE 0xFFC00640 /* Timer Enable Register */
-#define TIMER_DISABLE 0xFFC00644 /* Timer Disable Register */
-#define TIMER_STATUS 0xFFC00648 /* Timer Status Register */
-
-
-/* Programmable Flags (0xFFC00700 - 0xFFC007FF) */
-#define FIO_FLAG_D 0xFFC00700 /* Flag Mask to directly specify state of pins */
-#define FIO_FLAG_C 0xFFC00704 /* Peripheral Interrupt Flag Register (clear) */
-#define FIO_FLAG_S 0xFFC00708 /* Peripheral Interrupt Flag Register (set) */
-#define FIO_FLAG_T 0xFFC0070C /* Flag Mask to directly toggle state of pins */
-#define FIO_MASKA_D 0xFFC00710 /* Flag Mask Interrupt A Register (set directly) */
-#define FIO_MASKA_C 0xFFC00714 /* Flag Mask Interrupt A Register (clear) */
-#define FIO_MASKA_S 0xFFC00718 /* Flag Mask Interrupt A Register (set) */
-#define FIO_MASKA_T 0xFFC0071C /* Flag Mask Interrupt A Register (toggle) */
-#define FIO_MASKB_D 0xFFC00720 /* Flag Mask Interrupt B Register (set directly) */
-#define FIO_MASKB_C 0xFFC00724 /* Flag Mask Interrupt B Register (clear) */
-#define FIO_MASKB_S 0xFFC00728 /* Flag Mask Interrupt B Register (set) */
-#define FIO_MASKB_T 0xFFC0072C /* Flag Mask Interrupt B Register (toggle) */
-#define FIO_DIR 0xFFC00730 /* Peripheral Flag Direction Register */
-#define FIO_POLAR 0xFFC00734 /* Flag Source Polarity Register */
-#define FIO_EDGE 0xFFC00738 /* Flag Source Sensitivity Register */
-#define FIO_BOTH 0xFFC0073C /* Flag Set on BOTH Edges Register */
-#define FIO_INEN 0xFFC00740 /* Flag Input Enable Register */
-
-
-/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
-#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
-#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
-#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
-#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
-#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
-#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
-#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
-#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
-#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
-#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
-#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
-#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
-#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
-#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
-#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
-#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
-#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
-#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
-
-
-/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
-#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
-#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
-#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
-#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
-#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
-#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
-#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
-#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
-#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
-#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
-#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
-#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
-#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
-#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
-#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
-#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
-#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
-#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
-
-
-/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
-/* Asynchronous Memory Controller */
-#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
-#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
-#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
-
-/* SDRAM Controller */
-#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
-#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
-#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
-#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
-
-
-
-/* DMA Controller 0 Traffic Control Registers (0xFFC00B00 - 0xFFC00BFF) */
-
-#define DMAC0_TC_PER 0xFFC00B0C /* DMA Controller 0 Traffic Control Periods Register */
-#define DMAC0_TC_CNT 0xFFC00B10 /* DMA Controller 0 Traffic Control Current Counts Register */
-
-
-
-/* DMA Controller 0 (0xFFC00C00 - 0xFFC00FFF) */
-
-#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
-#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
-#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
-#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
-#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
-#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
-#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
-#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
-#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
-#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
-#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
-#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
-#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
-
-#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
-#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
-#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
-#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
-#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
-#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
-#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
-#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
-#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
-#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
-#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
-#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
-#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
-
-#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
-#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
-#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
-#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
-#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
-#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
-#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
-#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
-#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
-#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
-#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
-#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
-#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
-
-#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
-#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
-#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
-#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
-#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
-#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
-#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
-#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
-#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
-#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
-#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
-#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
-#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
-
-#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
-#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
-#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
-#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
-#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
-#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
-#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
-#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
-#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
-#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
-#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
-#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
-#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
-
-#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
-#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
-#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
-#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
-#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
-#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
-#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
-#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
-#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
-#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
-#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
-#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
-#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
-
-#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
-#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
-#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
-#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
-#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
-#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
-#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
-#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
-#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
-#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
-#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
-#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
-#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
-
-#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
-#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
-#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
-#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
-#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
-#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
-#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
-#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
-#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
-#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
-#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
-#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
-#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
-
-#define MDMA_D0_NEXT_DESC_PTR 0xFFC00E00 /* MemDMA0 Stream 0 Destination Next Descriptor Pointer Register */
-#define MDMA_D0_START_ADDR 0xFFC00E04 /* MemDMA0 Stream 0 Destination Start Address Register */
-#define MDMA_D0_CONFIG 0xFFC00E08 /* MemDMA0 Stream 0 Destination Configuration Register */
-#define MDMA_D0_X_COUNT 0xFFC00E10 /* MemDMA0 Stream 0 Destination X Count Register */
-#define MDMA_D0_X_MODIFY 0xFFC00E14 /* MemDMA0 Stream 0 Destination X Modify Register */
-#define MDMA_D0_Y_COUNT 0xFFC00E18 /* MemDMA0 Stream 0 Destination Y Count Register */
-#define MDMA_D0_Y_MODIFY 0xFFC00E1C /* MemDMA0 Stream 0 Destination Y Modify Register */
-#define MDMA_D0_CURR_DESC_PTR 0xFFC00E20 /* MemDMA0 Stream 0 Destination Current Descriptor Pointer Register */
-#define MDMA_D0_CURR_ADDR 0xFFC00E24 /* MemDMA0 Stream 0 Destination Current Address Register */
-#define MDMA_D0_IRQ_STATUS 0xFFC00E28 /* MemDMA0 Stream 0 Destination Interrupt/Status Register */
-#define MDMA_D0_PERIPHERAL_MAP 0xFFC00E2C /* MemDMA0 Stream 0 Destination Peripheral Map Register */
-#define MDMA_D0_CURR_X_COUNT 0xFFC00E30 /* MemDMA0 Stream 0 Destination Current X Count Register */
-#define MDMA_D0_CURR_Y_COUNT 0xFFC00E38 /* MemDMA0 Stream 0 Destination Current Y Count Register */
-
-#define MDMA_S0_NEXT_DESC_PTR 0xFFC00E40 /* MemDMA0 Stream 0 Source Next Descriptor Pointer Register */
-#define MDMA_S0_START_ADDR 0xFFC00E44 /* MemDMA0 Stream 0 Source Start Address Register */
-#define MDMA_S0_CONFIG 0xFFC00E48 /* MemDMA0 Stream 0 Source Configuration Register */
-#define MDMA_S0_X_COUNT 0xFFC00E50 /* MemDMA0 Stream 0 Source X Count Register */
-#define MDMA_S0_X_MODIFY 0xFFC00E54 /* MemDMA0 Stream 0 Source X Modify Register */
-#define MDMA_S0_Y_COUNT 0xFFC00E58 /* MemDMA0 Stream 0 Source Y Count Register */
-#define MDMA_S0_Y_MODIFY 0xFFC00E5C /* MemDMA0 Stream 0 Source Y Modify Register */
-#define MDMA_S0_CURR_DESC_PTR 0xFFC00E60 /* MemDMA0 Stream 0 Source Current Descriptor Pointer Register */
-#define MDMA_S0_CURR_ADDR 0xFFC00E64 /* MemDMA0 Stream 0 Source Current Address Register */
-#define MDMA_S0_IRQ_STATUS 0xFFC00E68 /* MemDMA0 Stream 0 Source Interrupt/Status Register */
-#define MDMA_S0_PERIPHERAL_MAP 0xFFC00E6C /* MemDMA0 Stream 0 Source Peripheral Map Register */
-#define MDMA_S0_CURR_X_COUNT 0xFFC00E70 /* MemDMA0 Stream 0 Source Current X Count Register */
-#define MDMA_S0_CURR_Y_COUNT 0xFFC00E78 /* MemDMA0 Stream 0 Source Current Y Count Register */
-
-#define MDMA_D1_NEXT_DESC_PTR 0xFFC00E80 /* MemDMA0 Stream 1 Destination Next Descriptor Pointer Register */
-#define MDMA_D1_START_ADDR 0xFFC00E84 /* MemDMA0 Stream 1 Destination Start Address Register */
-#define MDMA_D1_CONFIG 0xFFC00E88 /* MemDMA0 Stream 1 Destination Configuration Register */
-#define MDMA_D1_X_COUNT 0xFFC00E90 /* MemDMA0 Stream 1 Destination X Count Register */
-#define MDMA_D1_X_MODIFY 0xFFC00E94 /* MemDMA0 Stream 1 Destination X Modify Register */
-#define MDMA_D1_Y_COUNT 0xFFC00E98 /* MemDMA0 Stream 1 Destination Y Count Register */
-#define MDMA_D1_Y_MODIFY 0xFFC00E9C /* MemDMA0 Stream 1 Destination Y Modify Register */
-#define MDMA_D1_CURR_DESC_PTR 0xFFC00EA0 /* MemDMA0 Stream 1 Destination Current Descriptor Pointer Register */
-#define MDMA_D1_CURR_ADDR 0xFFC00EA4 /* MemDMA0 Stream 1 Destination Current Address Register */
-#define MDMA_D1_IRQ_STATUS 0xFFC00EA8 /* MemDMA0 Stream 1 Destination Interrupt/Status Register */
-#define MDMA_D1_PERIPHERAL_MAP 0xFFC00EAC /* MemDMA0 Stream 1 Destination Peripheral Map Register */
-#define MDMA_D1_CURR_X_COUNT 0xFFC00EB0 /* MemDMA0 Stream 1 Destination Current X Count Register */
-#define MDMA_D1_CURR_Y_COUNT 0xFFC00EB8 /* MemDMA0 Stream 1 Destination Current Y Count Register */
-
-#define MDMA_S1_NEXT_DESC_PTR 0xFFC00EC0 /* MemDMA0 Stream 1 Source Next Descriptor Pointer Register */
-#define MDMA_S1_START_ADDR 0xFFC00EC4 /* MemDMA0 Stream 1 Source Start Address Register */
-#define MDMA_S1_CONFIG 0xFFC00EC8 /* MemDMA0 Stream 1 Source Configuration Register */
-#define MDMA_S1_X_COUNT 0xFFC00ED0 /* MemDMA0 Stream 1 Source X Count Register */
-#define MDMA_S1_X_MODIFY 0xFFC00ED4 /* MemDMA0 Stream 1 Source X Modify Register */
-#define MDMA_S1_Y_COUNT 0xFFC00ED8 /* MemDMA0 Stream 1 Source Y Count Register */
-#define MDMA_S1_Y_MODIFY 0xFFC00EDC /* MemDMA0 Stream 1 Source Y Modify Register */
-#define MDMA_S1_CURR_DESC_PTR 0xFFC00EE0 /* MemDMA0 Stream 1 Source Current Descriptor Pointer Register */
-#define MDMA_S1_CURR_ADDR 0xFFC00EE4 /* MemDMA0 Stream 1 Source Current Address Register */
-#define MDMA_S1_IRQ_STATUS 0xFFC00EE8 /* MemDMA0 Stream 1 Source Interrupt/Status Register */
-#define MDMA_S1_PERIPHERAL_MAP 0xFFC00EEC /* MemDMA0 Stream 1 Source Peripheral Map Register */
-#define MDMA_S1_CURR_X_COUNT 0xFFC00EF0 /* MemDMA0 Stream 1 Source Current X Count Register */
-#define MDMA_S1_CURR_Y_COUNT 0xFFC00EF8 /* MemDMA0 Stream 1 Source Current Y Count Register */
-
-
-/* Parallel Peripheral Interface (PPI) (0xFFC01000 - 0xFFC010FF) */
-#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */
-#define PPI_STATUS 0xFFC01004 /* PPI Status Register */
-#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */
-#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */
-#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
-
-
-/* Two-Wire Interface 0 (0xFFC01400 - 0xFFC014FF) */
-#define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
-#define TWI0_CONTROL 0xFFC01404 /* TWI0 Master Internal Time Reference Register */
-#define TWI0_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
-#define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
-#define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
-#define TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */
-#define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
-#define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
-#define TWI0_INT_STAT 0xFFC01420 /* TWI0 Master Interrupt Register */
-#define TWI0_INT_MASK 0xFFC01424 /* TWI0 Master Interrupt Mask Register */
-#define TWI0_FIFO_CTL 0xFFC01428 /* FIFO Control Register */
-#define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
-#define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
-#define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
-#define TWI0_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */
-#define TWI0_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */
-
-#define TWI0_REGBASE TWI0_CLKDIV
-
-/* the following are for backwards compatibility */
-#define TWI0_PRESCALE TWI0_CONTROL
-#define TWI0_INT_SRC TWI0_INT_STAT
-#define TWI0_INT_ENABLE TWI0_INT_MASK
-
-
-/* General-Purpose Ports (0xFFC01500 - 0xFFC015FF) */
-
-/* GPIO Port C Register Names */
-#define PORTCIO_FER 0xFFC01500 /* GPIO Pin Port C Configuration Register */
-#define PORTCIO 0xFFC01510 /* GPIO Pin Port C Data Register */
-#define PORTCIO_CLEAR 0xFFC01520 /* Clear GPIO Pin Port C Register */
-#define PORTCIO_SET 0xFFC01530 /* Set GPIO Pin Port C Register */
-#define PORTCIO_TOGGLE 0xFFC01540 /* Toggle GPIO Pin Port C Register */
-#define PORTCIO_DIR 0xFFC01550 /* GPIO Pin Port C Direction Register */
-#define PORTCIO_INEN 0xFFC01560 /* GPIO Pin Port C Input Enable Register */
-
-/* GPIO Port D Register Names */
-#define PORTDIO_FER 0xFFC01504 /* GPIO Pin Port D Configuration Register */
-#define PORTDIO 0xFFC01514 /* GPIO Pin Port D Data Register */
-#define PORTDIO_CLEAR 0xFFC01524 /* Clear GPIO Pin Port D Register */
-#define PORTDIO_SET 0xFFC01534 /* Set GPIO Pin Port D Register */
-#define PORTDIO_TOGGLE 0xFFC01544 /* Toggle GPIO Pin Port D Register */
-#define PORTDIO_DIR 0xFFC01554 /* GPIO Pin Port D Direction Register */
-#define PORTDIO_INEN 0xFFC01564 /* GPIO Pin Port D Input Enable Register */
-
-/* GPIO Port E Register Names */
-#define PORTEIO_FER 0xFFC01508 /* GPIO Pin Port E Configuration Register */
-#define PORTEIO 0xFFC01518 /* GPIO Pin Port E Data Register */
-#define PORTEIO_CLEAR 0xFFC01528 /* Clear GPIO Pin Port E Register */
-#define PORTEIO_SET 0xFFC01538 /* Set GPIO Pin Port E Register */
-#define PORTEIO_TOGGLE 0xFFC01548 /* Toggle GPIO Pin Port E Register */
-#define PORTEIO_DIR 0xFFC01558 /* GPIO Pin Port E Direction Register */
-#define PORTEIO_INEN 0xFFC01568 /* GPIO Pin Port E Input Enable Register */
-
-/* DMA Controller 1 Traffic Control Registers (0xFFC01B00 - 0xFFC01BFF) */
-
-#define DMAC1_TC_PER 0xFFC01B0C /* DMA Controller 1 Traffic Control Periods Register */
-#define DMAC1_TC_CNT 0xFFC01B10 /* DMA Controller 1 Traffic Control Current Counts Register */
-
-
-
-/* DMA Controller 1 (0xFFC01C00 - 0xFFC01FFF) */
-#define DMA8_NEXT_DESC_PTR 0xFFC01C00 /* DMA Channel 8 Next Descriptor Pointer Register */
-#define DMA8_START_ADDR 0xFFC01C04 /* DMA Channel 8 Start Address Register */
-#define DMA8_CONFIG 0xFFC01C08 /* DMA Channel 8 Configuration Register */
-#define DMA8_X_COUNT 0xFFC01C10 /* DMA Channel 8 X Count Register */
-#define DMA8_X_MODIFY 0xFFC01C14 /* DMA Channel 8 X Modify Register */
-#define DMA8_Y_COUNT 0xFFC01C18 /* DMA Channel 8 Y Count Register */
-#define DMA8_Y_MODIFY 0xFFC01C1C /* DMA Channel 8 Y Modify Register */
-#define DMA8_CURR_DESC_PTR 0xFFC01C20 /* DMA Channel 8 Current Descriptor Pointer Register */
-#define DMA8_CURR_ADDR 0xFFC01C24 /* DMA Channel 8 Current Address Register */
-#define DMA8_IRQ_STATUS 0xFFC01C28 /* DMA Channel 8 Interrupt/Status Register */
-#define DMA8_PERIPHERAL_MAP 0xFFC01C2C /* DMA Channel 8 Peripheral Map Register */
-#define DMA8_CURR_X_COUNT 0xFFC01C30 /* DMA Channel 8 Current X Count Register */
-#define DMA8_CURR_Y_COUNT 0xFFC01C38 /* DMA Channel 8 Current Y Count Register */
-
-#define DMA9_NEXT_DESC_PTR 0xFFC01C40 /* DMA Channel 9 Next Descriptor Pointer Register */
-#define DMA9_START_ADDR 0xFFC01C44 /* DMA Channel 9 Start Address Register */
-#define DMA9_CONFIG 0xFFC01C48 /* DMA Channel 9 Configuration Register */
-#define DMA9_X_COUNT 0xFFC01C50 /* DMA Channel 9 X Count Register */
-#define DMA9_X_MODIFY 0xFFC01C54 /* DMA Channel 9 X Modify Register */
-#define DMA9_Y_COUNT 0xFFC01C58 /* DMA Channel 9 Y Count Register */
-#define DMA9_Y_MODIFY 0xFFC01C5C /* DMA Channel 9 Y Modify Register */
-#define DMA9_CURR_DESC_PTR 0xFFC01C60 /* DMA Channel 9 Current Descriptor Pointer Register */
-#define DMA9_CURR_ADDR 0xFFC01C64 /* DMA Channel 9 Current Address Register */
-#define DMA9_IRQ_STATUS 0xFFC01C68 /* DMA Channel 9 Interrupt/Status Register */
-#define DMA9_PERIPHERAL_MAP 0xFFC01C6C /* DMA Channel 9 Peripheral Map Register */
-#define DMA9_CURR_X_COUNT 0xFFC01C70 /* DMA Channel 9 Current X Count Register */
-#define DMA9_CURR_Y_COUNT 0xFFC01C78 /* DMA Channel 9 Current Y Count Register */
-
-#define DMA10_NEXT_DESC_PTR 0xFFC01C80 /* DMA Channel 10 Next Descriptor Pointer Register */
-#define DMA10_START_ADDR 0xFFC01C84 /* DMA Channel 10 Start Address Register */
-#define DMA10_CONFIG 0xFFC01C88 /* DMA Channel 10 Configuration Register */
-#define DMA10_X_COUNT 0xFFC01C90 /* DMA Channel 10 X Count Register */
-#define DMA10_X_MODIFY 0xFFC01C94 /* DMA Channel 10 X Modify Register */
-#define DMA10_Y_COUNT 0xFFC01C98 /* DMA Channel 10 Y Count Register */
-#define DMA10_Y_MODIFY 0xFFC01C9C /* DMA Channel 10 Y Modify Register */
-#define DMA10_CURR_DESC_PTR 0xFFC01CA0 /* DMA Channel 10 Current Descriptor Pointer Register */
-#define DMA10_CURR_ADDR 0xFFC01CA4 /* DMA Channel 10 Current Address Register */
-#define DMA10_IRQ_STATUS 0xFFC01CA8 /* DMA Channel 10 Interrupt/Status Register */
-#define DMA10_PERIPHERAL_MAP 0xFFC01CAC /* DMA Channel 10 Peripheral Map Register */
-#define DMA10_CURR_X_COUNT 0xFFC01CB0 /* DMA Channel 10 Current X Count Register */
-#define DMA10_CURR_Y_COUNT 0xFFC01CB8 /* DMA Channel 10 Current Y Count Register */
-
-#define DMA11_NEXT_DESC_PTR 0xFFC01CC0 /* DMA Channel 11 Next Descriptor Pointer Register */
-#define DMA11_START_ADDR 0xFFC01CC4 /* DMA Channel 11 Start Address Register */
-#define DMA11_CONFIG 0xFFC01CC8 /* DMA Channel 11 Configuration Register */
-#define DMA11_X_COUNT 0xFFC01CD0 /* DMA Channel 11 X Count Register */
-#define DMA11_X_MODIFY 0xFFC01CD4 /* DMA Channel 11 X Modify Register */
-#define DMA11_Y_COUNT 0xFFC01CD8 /* DMA Channel 11 Y Count Register */
-#define DMA11_Y_MODIFY 0xFFC01CDC /* DMA Channel 11 Y Modify Register */
-#define DMA11_CURR_DESC_PTR 0xFFC01CE0 /* DMA Channel 11 Current Descriptor Pointer Register */
-#define DMA11_CURR_ADDR 0xFFC01CE4 /* DMA Channel 11 Current Address Register */
-#define DMA11_IRQ_STATUS 0xFFC01CE8 /* DMA Channel 11 Interrupt/Status Register */
-#define DMA11_PERIPHERAL_MAP 0xFFC01CEC /* DMA Channel 11 Peripheral Map Register */
-#define DMA11_CURR_X_COUNT 0xFFC01CF0 /* DMA Channel 11 Current X Count Register */
-#define DMA11_CURR_Y_COUNT 0xFFC01CF8 /* DMA Channel 11 Current Y Count Register */
-
-#define DMA12_NEXT_DESC_PTR 0xFFC01D00 /* DMA Channel 12 Next Descriptor Pointer Register */
-#define DMA12_START_ADDR 0xFFC01D04 /* DMA Channel 12 Start Address Register */
-#define DMA12_CONFIG 0xFFC01D08 /* DMA Channel 12 Configuration Register */
-#define DMA12_X_COUNT 0xFFC01D10 /* DMA Channel 12 X Count Register */
-#define DMA12_X_MODIFY 0xFFC01D14 /* DMA Channel 12 X Modify Register */
-#define DMA12_Y_COUNT 0xFFC01D18 /* DMA Channel 12 Y Count Register */
-#define DMA12_Y_MODIFY 0xFFC01D1C /* DMA Channel 12 Y Modify Register */
-#define DMA12_CURR_DESC_PTR 0xFFC01D20 /* DMA Channel 12 Current Descriptor Pointer Register */
-#define DMA12_CURR_ADDR 0xFFC01D24 /* DMA Channel 12 Current Address Register */
-#define DMA12_IRQ_STATUS 0xFFC01D28 /* DMA Channel 12 Interrupt/Status Register */
-#define DMA12_PERIPHERAL_MAP 0xFFC01D2C /* DMA Channel 12 Peripheral Map Register */
-#define DMA12_CURR_X_COUNT 0xFFC01D30 /* DMA Channel 12 Current X Count Register */
-#define DMA12_CURR_Y_COUNT 0xFFC01D38 /* DMA Channel 12 Current Y Count Register */
-
-#define DMA13_NEXT_DESC_PTR 0xFFC01D40 /* DMA Channel 13 Next Descriptor Pointer Register */
-#define DMA13_START_ADDR 0xFFC01D44 /* DMA Channel 13 Start Address Register */
-#define DMA13_CONFIG 0xFFC01D48 /* DMA Channel 13 Configuration Register */
-#define DMA13_X_COUNT 0xFFC01D50 /* DMA Channel 13 X Count Register */
-#define DMA13_X_MODIFY 0xFFC01D54 /* DMA Channel 13 X Modify Register */
-#define DMA13_Y_COUNT 0xFFC01D58 /* DMA Channel 13 Y Count Register */
-#define DMA13_Y_MODIFY 0xFFC01D5C /* DMA Channel 13 Y Modify Register */
-#define DMA13_CURR_DESC_PTR 0xFFC01D60 /* DMA Channel 13 Current Descriptor Pointer Register */
-#define DMA13_CURR_ADDR 0xFFC01D64 /* DMA Channel 13 Current Address Register */
-#define DMA13_IRQ_STATUS 0xFFC01D68 /* DMA Channel 13 Interrupt/Status Register */
-#define DMA13_PERIPHERAL_MAP 0xFFC01D6C /* DMA Channel 13 Peripheral Map Register */
-#define DMA13_CURR_X_COUNT 0xFFC01D70 /* DMA Channel 13 Current X Count Register */
-#define DMA13_CURR_Y_COUNT 0xFFC01D78 /* DMA Channel 13 Current Y Count Register */
-
-#define DMA14_NEXT_DESC_PTR 0xFFC01D80 /* DMA Channel 14 Next Descriptor Pointer Register */
-#define DMA14_START_ADDR 0xFFC01D84 /* DMA Channel 14 Start Address Register */
-#define DMA14_CONFIG 0xFFC01D88 /* DMA Channel 14 Configuration Register */
-#define DMA14_X_COUNT 0xFFC01D90 /* DMA Channel 14 X Count Register */
-#define DMA14_X_MODIFY 0xFFC01D94 /* DMA Channel 14 X Modify Register */
-#define DMA14_Y_COUNT 0xFFC01D98 /* DMA Channel 14 Y Count Register */
-#define DMA14_Y_MODIFY 0xFFC01D9C /* DMA Channel 14 Y Modify Register */
-#define DMA14_CURR_DESC_PTR 0xFFC01DA0 /* DMA Channel 14 Current Descriptor Pointer Register */
-#define DMA14_CURR_ADDR 0xFFC01DA4 /* DMA Channel 14 Current Address Register */
-#define DMA14_IRQ_STATUS 0xFFC01DA8 /* DMA Channel 14 Interrupt/Status Register */
-#define DMA14_PERIPHERAL_MAP 0xFFC01DAC /* DMA Channel 14 Peripheral Map Register */
-#define DMA14_CURR_X_COUNT 0xFFC01DB0 /* DMA Channel 14 Current X Count Register */
-#define DMA14_CURR_Y_COUNT 0xFFC01DB8 /* DMA Channel 14 Current Y Count Register */
-
-#define DMA15_NEXT_DESC_PTR 0xFFC01DC0 /* DMA Channel 15 Next Descriptor Pointer Register */
-#define DMA15_START_ADDR 0xFFC01DC4 /* DMA Channel 15 Start Address Register */
-#define DMA15_CONFIG 0xFFC01DC8 /* DMA Channel 15 Configuration Register */
-#define DMA15_X_COUNT 0xFFC01DD0 /* DMA Channel 15 X Count Register */
-#define DMA15_X_MODIFY 0xFFC01DD4 /* DMA Channel 15 X Modify Register */
-#define DMA15_Y_COUNT 0xFFC01DD8 /* DMA Channel 15 Y Count Register */
-#define DMA15_Y_MODIFY 0xFFC01DDC /* DMA Channel 15 Y Modify Register */
-#define DMA15_CURR_DESC_PTR 0xFFC01DE0 /* DMA Channel 15 Current Descriptor Pointer Register */
-#define DMA15_CURR_ADDR 0xFFC01DE4 /* DMA Channel 15 Current Address Register */
-#define DMA15_IRQ_STATUS 0xFFC01DE8 /* DMA Channel 15 Interrupt/Status Register */
-#define DMA15_PERIPHERAL_MAP 0xFFC01DEC /* DMA Channel 15 Peripheral Map Register */
-#define DMA15_CURR_X_COUNT 0xFFC01DF0 /* DMA Channel 15 Current X Count Register */
-#define DMA15_CURR_Y_COUNT 0xFFC01DF8 /* DMA Channel 15 Current Y Count Register */
-
-#define DMA16_NEXT_DESC_PTR 0xFFC01E00 /* DMA Channel 16 Next Descriptor Pointer Register */
-#define DMA16_START_ADDR 0xFFC01E04 /* DMA Channel 16 Start Address Register */
-#define DMA16_CONFIG 0xFFC01E08 /* DMA Channel 16 Configuration Register */
-#define DMA16_X_COUNT 0xFFC01E10 /* DMA Channel 16 X Count Register */
-#define DMA16_X_MODIFY 0xFFC01E14 /* DMA Channel 16 X Modify Register */
-#define DMA16_Y_COUNT 0xFFC01E18 /* DMA Channel 16 Y Count Register */
-#define DMA16_Y_MODIFY 0xFFC01E1C /* DMA Channel 16 Y Modify Register */
-#define DMA16_CURR_DESC_PTR 0xFFC01E20 /* DMA Channel 16 Current Descriptor Pointer Register */
-#define DMA16_CURR_ADDR 0xFFC01E24 /* DMA Channel 16 Current Address Register */
-#define DMA16_IRQ_STATUS 0xFFC01E28 /* DMA Channel 16 Interrupt/Status Register */
-#define DMA16_PERIPHERAL_MAP 0xFFC01E2C /* DMA Channel 16 Peripheral Map Register */
-#define DMA16_CURR_X_COUNT 0xFFC01E30 /* DMA Channel 16 Current X Count Register */
-#define DMA16_CURR_Y_COUNT 0xFFC01E38 /* DMA Channel 16 Current Y Count Register */
-
-#define DMA17_NEXT_DESC_PTR 0xFFC01E40 /* DMA Channel 17 Next Descriptor Pointer Register */
-#define DMA17_START_ADDR 0xFFC01E44 /* DMA Channel 17 Start Address Register */
-#define DMA17_CONFIG 0xFFC01E48 /* DMA Channel 17 Configuration Register */
-#define DMA17_X_COUNT 0xFFC01E50 /* DMA Channel 17 X Count Register */
-#define DMA17_X_MODIFY 0xFFC01E54 /* DMA Channel 17 X Modify Register */
-#define DMA17_Y_COUNT 0xFFC01E58 /* DMA Channel 17 Y Count Register */
-#define DMA17_Y_MODIFY 0xFFC01E5C /* DMA Channel 17 Y Modify Register */
-#define DMA17_CURR_DESC_PTR 0xFFC01E60 /* DMA Channel 17 Current Descriptor Pointer Register */
-#define DMA17_CURR_ADDR 0xFFC01E64 /* DMA Channel 17 Current Address Register */
-#define DMA17_IRQ_STATUS 0xFFC01E68 /* DMA Channel 17 Interrupt/Status Register */
-#define DMA17_PERIPHERAL_MAP 0xFFC01E6C /* DMA Channel 17 Peripheral Map Register */
-#define DMA17_CURR_X_COUNT 0xFFC01E70 /* DMA Channel 17 Current X Count Register */
-#define DMA17_CURR_Y_COUNT 0xFFC01E78 /* DMA Channel 17 Current Y Count Register */
-
-#define DMA18_NEXT_DESC_PTR 0xFFC01E80 /* DMA Channel 18 Next Descriptor Pointer Register */
-#define DMA18_START_ADDR 0xFFC01E84 /* DMA Channel 18 Start Address Register */
-#define DMA18_CONFIG 0xFFC01E88 /* DMA Channel 18 Configuration Register */
-#define DMA18_X_COUNT 0xFFC01E90 /* DMA Channel 18 X Count Register */
-#define DMA18_X_MODIFY 0xFFC01E94 /* DMA Channel 18 X Modify Register */
-#define DMA18_Y_COUNT 0xFFC01E98 /* DMA Channel 18 Y Count Register */
-#define DMA18_Y_MODIFY 0xFFC01E9C /* DMA Channel 18 Y Modify Register */
-#define DMA18_CURR_DESC_PTR 0xFFC01EA0 /* DMA Channel 18 Current Descriptor Pointer Register */
-#define DMA18_CURR_ADDR 0xFFC01EA4 /* DMA Channel 18 Current Address Register */
-#define DMA18_IRQ_STATUS 0xFFC01EA8 /* DMA Channel 18 Interrupt/Status Register */
-#define DMA18_PERIPHERAL_MAP 0xFFC01EAC /* DMA Channel 18 Peripheral Map Register */
-#define DMA18_CURR_X_COUNT 0xFFC01EB0 /* DMA Channel 18 Current X Count Register */
-#define DMA18_CURR_Y_COUNT 0xFFC01EB8 /* DMA Channel 18 Current Y Count Register */
-
-#define DMA19_NEXT_DESC_PTR 0xFFC01EC0 /* DMA Channel 19 Next Descriptor Pointer Register */
-#define DMA19_START_ADDR 0xFFC01EC4 /* DMA Channel 19 Start Address Register */
-#define DMA19_CONFIG 0xFFC01EC8 /* DMA Channel 19 Configuration Register */
-#define DMA19_X_COUNT 0xFFC01ED0 /* DMA Channel 19 X Count Register */
-#define DMA19_X_MODIFY 0xFFC01ED4 /* DMA Channel 19 X Modify Register */
-#define DMA19_Y_COUNT 0xFFC01ED8 /* DMA Channel 19 Y Count Register */
-#define DMA19_Y_MODIFY 0xFFC01EDC /* DMA Channel 19 Y Modify Register */
-#define DMA19_CURR_DESC_PTR 0xFFC01EE0 /* DMA Channel 19 Current Descriptor Pointer Register */
-#define DMA19_CURR_ADDR 0xFFC01EE4 /* DMA Channel 19 Current Address Register */
-#define DMA19_IRQ_STATUS 0xFFC01EE8 /* DMA Channel 19 Interrupt/Status Register */
-#define DMA19_PERIPHERAL_MAP 0xFFC01EEC /* DMA Channel 19 Peripheral Map Register */
-#define DMA19_CURR_X_COUNT 0xFFC01EF0 /* DMA Channel 19 Current X Count Register */
-#define DMA19_CURR_Y_COUNT 0xFFC01EF8 /* DMA Channel 19 Current Y Count Register */
-
-#define MDMA_D2_NEXT_DESC_PTR 0xFFC01F00 /* MemDMA1 Stream 0 Destination Next Descriptor Pointer Register */
-#define MDMA_D2_START_ADDR 0xFFC01F04 /* MemDMA1 Stream 0 Destination Start Address Register */
-#define MDMA_D2_CONFIG 0xFFC01F08 /* MemDMA1 Stream 0 Destination Configuration Register */
-#define MDMA_D2_X_COUNT 0xFFC01F10 /* MemDMA1 Stream 0 Destination X Count Register */
-#define MDMA_D2_X_MODIFY 0xFFC01F14 /* MemDMA1 Stream 0 Destination X Modify Register */
-#define MDMA_D2_Y_COUNT 0xFFC01F18 /* MemDMA1 Stream 0 Destination Y Count Register */
-#define MDMA_D2_Y_MODIFY 0xFFC01F1C /* MemDMA1 Stream 0 Destination Y Modify Register */
-#define MDMA_D2_CURR_DESC_PTR 0xFFC01F20 /* MemDMA1 Stream 0 Destination Current Descriptor Pointer Register */
-#define MDMA_D2_CURR_ADDR 0xFFC01F24 /* MemDMA1 Stream 0 Destination Current Address Register */
-#define MDMA_D2_IRQ_STATUS 0xFFC01F28 /* MemDMA1 Stream 0 Destination Interrupt/Status Register */
-#define MDMA_D2_PERIPHERAL_MAP 0xFFC01F2C /* MemDMA1 Stream 0 Destination Peripheral Map Register */
-#define MDMA_D2_CURR_X_COUNT 0xFFC01F30 /* MemDMA1 Stream 0 Destination Current X Count Register */
-#define MDMA_D2_CURR_Y_COUNT 0xFFC01F38 /* MemDMA1 Stream 0 Destination Current Y Count Register */
-
-#define MDMA_S2_NEXT_DESC_PTR 0xFFC01F40 /* MemDMA1 Stream 0 Source Next Descriptor Pointer Register */
-#define MDMA_S2_START_ADDR 0xFFC01F44 /* MemDMA1 Stream 0 Source Start Address Register */
-#define MDMA_S2_CONFIG 0xFFC01F48 /* MemDMA1 Stream 0 Source Configuration Register */
-#define MDMA_S2_X_COUNT 0xFFC01F50 /* MemDMA1 Stream 0 Source X Count Register */
-#define MDMA_S2_X_MODIFY 0xFFC01F54 /* MemDMA1 Stream 0 Source X Modify Register */
-#define MDMA_S2_Y_COUNT 0xFFC01F58 /* MemDMA1 Stream 0 Source Y Count Register */
-#define MDMA_S2_Y_MODIFY 0xFFC01F5C /* MemDMA1 Stream 0 Source Y Modify Register */
-#define MDMA_S2_CURR_DESC_PTR 0xFFC01F60 /* MemDMA1 Stream 0 Source Current Descriptor Pointer Register */
-#define MDMA_S2_CURR_ADDR 0xFFC01F64 /* MemDMA1 Stream 0 Source Current Address Register */
-#define MDMA_S2_IRQ_STATUS 0xFFC01F68 /* MemDMA1 Stream 0 Source Interrupt/Status Register */
-#define MDMA_S2_PERIPHERAL_MAP 0xFFC01F6C /* MemDMA1 Stream 0 Source Peripheral Map Register */
-#define MDMA_S2_CURR_X_COUNT 0xFFC01F70 /* MemDMA1 Stream 0 Source Current X Count Register */
-#define MDMA_S2_CURR_Y_COUNT 0xFFC01F78 /* MemDMA1 Stream 0 Source Current Y Count Register */
-
-#define MDMA_D3_NEXT_DESC_PTR 0xFFC01F80 /* MemDMA1 Stream 1 Destination Next Descriptor Pointer Register */
-#define MDMA_D3_START_ADDR 0xFFC01F84 /* MemDMA1 Stream 1 Destination Start Address Register */
-#define MDMA_D3_CONFIG 0xFFC01F88 /* MemDMA1 Stream 1 Destination Configuration Register */
-#define MDMA_D3_X_COUNT 0xFFC01F90 /* MemDMA1 Stream 1 Destination X Count Register */
-#define MDMA_D3_X_MODIFY 0xFFC01F94 /* MemDMA1 Stream 1 Destination X Modify Register */
-#define MDMA_D3_Y_COUNT 0xFFC01F98 /* MemDMA1 Stream 1 Destination Y Count Register */
-#define MDMA_D3_Y_MODIFY 0xFFC01F9C /* MemDMA1 Stream 1 Destination Y Modify Register */
-#define MDMA_D3_CURR_DESC_PTR 0xFFC01FA0 /* MemDMA1 Stream 1 Destination Current Descriptor Pointer Register */
-#define MDMA_D3_CURR_ADDR 0xFFC01FA4 /* MemDMA1 Stream 1 Destination Current Address Register */
-#define MDMA_D3_IRQ_STATUS 0xFFC01FA8 /* MemDMA1 Stream 1 Destination Interrupt/Status Register */
-#define MDMA_D3_PERIPHERAL_MAP 0xFFC01FAC /* MemDMA1 Stream 1 Destination Peripheral Map Register */
-#define MDMA_D3_CURR_X_COUNT 0xFFC01FB0 /* MemDMA1 Stream 1 Destination Current X Count Register */
-#define MDMA_D3_CURR_Y_COUNT 0xFFC01FB8 /* MemDMA1 Stream 1 Destination Current Y Count Register */
-
-#define MDMA_S3_NEXT_DESC_PTR 0xFFC01FC0 /* MemDMA1 Stream 1 Source Next Descriptor Pointer Register */
-#define MDMA_S3_START_ADDR 0xFFC01FC4 /* MemDMA1 Stream 1 Source Start Address Register */
-#define MDMA_S3_CONFIG 0xFFC01FC8 /* MemDMA1 Stream 1 Source Configuration Register */
-#define MDMA_S3_X_COUNT 0xFFC01FD0 /* MemDMA1 Stream 1 Source X Count Register */
-#define MDMA_S3_X_MODIFY 0xFFC01FD4 /* MemDMA1 Stream 1 Source X Modify Register */
-#define MDMA_S3_Y_COUNT 0xFFC01FD8 /* MemDMA1 Stream 1 Source Y Count Register */
-#define MDMA_S3_Y_MODIFY 0xFFC01FDC /* MemDMA1 Stream 1 Source Y Modify Register */
-#define MDMA_S3_CURR_DESC_PTR 0xFFC01FE0 /* MemDMA1 Stream 1 Source Current Descriptor Pointer Register */
-#define MDMA_S3_CURR_ADDR 0xFFC01FE4 /* MemDMA1 Stream 1 Source Current Address Register */
-#define MDMA_S3_IRQ_STATUS 0xFFC01FE8 /* MemDMA1 Stream 1 Source Interrupt/Status Register */
-#define MDMA_S3_PERIPHERAL_MAP 0xFFC01FEC /* MemDMA1 Stream 1 Source Peripheral Map Register */
-#define MDMA_S3_CURR_X_COUNT 0xFFC01FF0 /* MemDMA1 Stream 1 Source Current X Count Register */
-#define MDMA_S3_CURR_Y_COUNT 0xFFC01FF8 /* MemDMA1 Stream 1 Source Current Y Count Register */
-
-
-/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
-#define UART1_THR 0xFFC02000 /* Transmit Holding register */
-#define UART1_RBR 0xFFC02000 /* Receive Buffer register */
-#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */
-#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */
-#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */
-#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */
-#define UART1_LCR 0xFFC0200C /* Line Control Register */
-#define UART1_MCR 0xFFC02010 /* Modem Control Register */
-#define UART1_LSR 0xFFC02014 /* Line Status Register */
-#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */
-#define UART1_GCTL 0xFFC02024 /* Global Control Register */
-
-
-/* UART2 Controller (0xFFC02100 - 0xFFC021FF) */
-#define UART2_THR 0xFFC02100 /* Transmit Holding register */
-#define UART2_RBR 0xFFC02100 /* Receive Buffer register */
-#define UART2_DLL 0xFFC02100 /* Divisor Latch (Low-Byte) */
-#define UART2_IER 0xFFC02104 /* Interrupt Enable Register */
-#define UART2_DLH 0xFFC02104 /* Divisor Latch (High-Byte) */
-#define UART2_IIR 0xFFC02108 /* Interrupt Identification Register */
-#define UART2_LCR 0xFFC0210C /* Line Control Register */
-#define UART2_MCR 0xFFC02110 /* Modem Control Register */
-#define UART2_LSR 0xFFC02114 /* Line Status Register */
-#define UART2_SCR 0xFFC0211C /* SCR Scratch Register */
-#define UART2_GCTL 0xFFC02124 /* Global Control Register */
-
-
-/* Two-Wire Interface 1 (0xFFC02200 - 0xFFC022FF) */
-#define TWI1_CLKDIV 0xFFC02200 /* Serial Clock Divider Register */
-#define TWI1_CONTROL 0xFFC02204 /* TWI1 Master Internal Time Reference Register */
-#define TWI1_SLAVE_CTL 0xFFC02208 /* Slave Mode Control Register */
-#define TWI1_SLAVE_STAT 0xFFC0220C /* Slave Mode Status Register */
-#define TWI1_SLAVE_ADDR 0xFFC02210 /* Slave Mode Address Register */
-#define TWI1_MASTER_CTL 0xFFC02214 /* Master Mode Control Register */
-#define TWI1_MASTER_STAT 0xFFC02218 /* Master Mode Status Register */
-#define TWI1_MASTER_ADDR 0xFFC0221C /* Master Mode Address Register */
-#define TWI1_INT_STAT 0xFFC02220 /* TWI1 Master Interrupt Register */
-#define TWI1_INT_MASK 0xFFC02224 /* TWI1 Master Interrupt Mask Register */
-#define TWI1_FIFO_CTL 0xFFC02228 /* FIFO Control Register */
-#define TWI1_FIFO_STAT 0xFFC0222C /* FIFO Status Register */
-#define TWI1_XMT_DATA8 0xFFC02280 /* FIFO Transmit Data Single Byte Register */
-#define TWI1_XMT_DATA16 0xFFC02284 /* FIFO Transmit Data Double Byte Register */
-#define TWI1_RCV_DATA8 0xFFC02288 /* FIFO Receive Data Single Byte Register */
-#define TWI1_RCV_DATA16 0xFFC0228C /* FIFO Receive Data Double Byte Register */
-#define TWI1_REGBASE TWI1_CLKDIV
-
-
-/* the following are for backwards compatibility */
-#define TWI1_PRESCALE TWI1_CONTROL
-#define TWI1_INT_SRC TWI1_INT_STAT
-#define TWI1_INT_ENABLE TWI1_INT_MASK
-
-
-/* SPI1 Controller (0xFFC02300 - 0xFFC023FF) */
-#define SPI1_CTL 0xFFC02300 /* SPI1 Control Register */
-#define SPI1_FLG 0xFFC02304 /* SPI1 Flag register */
-#define SPI1_STAT 0xFFC02308 /* SPI1 Status register */
-#define SPI1_TDBR 0xFFC0230C /* SPI1 Transmit Data Buffer Register */
-#define SPI1_RDBR 0xFFC02310 /* SPI1 Receive Data Buffer Register */
-#define SPI1_BAUD 0xFFC02314 /* SPI1 Baud rate Register */
-#define SPI1_SHADOW 0xFFC02318 /* SPI1_RDBR Shadow Register */
-#define SPI1_REGBASE SPI1_CTL
-
-/* SPI2 Controller (0xFFC02400 - 0xFFC024FF) */
-#define SPI2_CTL 0xFFC02400 /* SPI2 Control Register */
-#define SPI2_FLG 0xFFC02404 /* SPI2 Flag register */
-#define SPI2_STAT 0xFFC02408 /* SPI2 Status register */
-#define SPI2_TDBR 0xFFC0240C /* SPI2 Transmit Data Buffer Register */
-#define SPI2_RDBR 0xFFC02410 /* SPI2 Receive Data Buffer Register */
-#define SPI2_BAUD 0xFFC02414 /* SPI2 Baud rate Register */
-#define SPI2_SHADOW 0xFFC02418 /* SPI2_RDBR Shadow Register */
-#define SPI2_REGBASE SPI2_CTL
-
-/* SPORT2 Controller (0xFFC02500 - 0xFFC025FF) */
-#define SPORT2_TCR1 0xFFC02500 /* SPORT2 Transmit Configuration 1 Register */
-#define SPORT2_TCR2 0xFFC02504 /* SPORT2 Transmit Configuration 2 Register */
-#define SPORT2_TCLKDIV 0xFFC02508 /* SPORT2 Transmit Clock Divider */
-#define SPORT2_TFSDIV 0xFFC0250C /* SPORT2 Transmit Frame Sync Divider */
-#define SPORT2_TX 0xFFC02510 /* SPORT2 TX Data Register */
-#define SPORT2_RX 0xFFC02518 /* SPORT2 RX Data Register */
-#define SPORT2_RCR1 0xFFC02520 /* SPORT2 Transmit Configuration 1 Register */
-#define SPORT2_RCR2 0xFFC02524 /* SPORT2 Transmit Configuration 2 Register */
-#define SPORT2_RCLKDIV 0xFFC02528 /* SPORT2 Receive Clock Divider */
-#define SPORT2_RFSDIV 0xFFC0252C /* SPORT2 Receive Frame Sync Divider */
-#define SPORT2_STAT 0xFFC02530 /* SPORT2 Status Register */
-#define SPORT2_CHNL 0xFFC02534 /* SPORT2 Current Channel Register */
-#define SPORT2_MCMC1 0xFFC02538 /* SPORT2 Multi-Channel Configuration Register 1 */
-#define SPORT2_MCMC2 0xFFC0253C /* SPORT2 Multi-Channel Configuration Register 2 */
-#define SPORT2_MTCS0 0xFFC02540 /* SPORT2 Multi-Channel Transmit Select Register 0 */
-#define SPORT2_MTCS1 0xFFC02544 /* SPORT2 Multi-Channel Transmit Select Register 1 */
-#define SPORT2_MTCS2 0xFFC02548 /* SPORT2 Multi-Channel Transmit Select Register 2 */
-#define SPORT2_MTCS3 0xFFC0254C /* SPORT2 Multi-Channel Transmit Select Register 3 */
-#define SPORT2_MRCS0 0xFFC02550 /* SPORT2 Multi-Channel Receive Select Register 0 */
-#define SPORT2_MRCS1 0xFFC02554 /* SPORT2 Multi-Channel Receive Select Register 1 */
-#define SPORT2_MRCS2 0xFFC02558 /* SPORT2 Multi-Channel Receive Select Register 2 */
-#define SPORT2_MRCS3 0xFFC0255C /* SPORT2 Multi-Channel Receive Select Register 3 */
-
-
-/* SPORT3 Controller (0xFFC02600 - 0xFFC026FF) */
-#define SPORT3_TCR1 0xFFC02600 /* SPORT3 Transmit Configuration 1 Register */
-#define SPORT3_TCR2 0xFFC02604 /* SPORT3 Transmit Configuration 2 Register */
-#define SPORT3_TCLKDIV 0xFFC02608 /* SPORT3 Transmit Clock Divider */
-#define SPORT3_TFSDIV 0xFFC0260C /* SPORT3 Transmit Frame Sync Divider */
-#define SPORT3_TX 0xFFC02610 /* SPORT3 TX Data Register */
-#define SPORT3_RX 0xFFC02618 /* SPORT3 RX Data Register */
-#define SPORT3_RCR1 0xFFC02620 /* SPORT3 Transmit Configuration 1 Register */
-#define SPORT3_RCR2 0xFFC02624 /* SPORT3 Transmit Configuration 2 Register */
-#define SPORT3_RCLKDIV 0xFFC02628 /* SPORT3 Receive Clock Divider */
-#define SPORT3_RFSDIV 0xFFC0262C /* SPORT3 Receive Frame Sync Divider */
-#define SPORT3_STAT 0xFFC02630 /* SPORT3 Status Register */
-#define SPORT3_CHNL 0xFFC02634 /* SPORT3 Current Channel Register */
-#define SPORT3_MCMC1 0xFFC02638 /* SPORT3 Multi-Channel Configuration Register 1 */
-#define SPORT3_MCMC2 0xFFC0263C /* SPORT3 Multi-Channel Configuration Register 2 */
-#define SPORT3_MTCS0 0xFFC02640 /* SPORT3 Multi-Channel Transmit Select Register 0 */
-#define SPORT3_MTCS1 0xFFC02644 /* SPORT3 Multi-Channel Transmit Select Register 1 */
-#define SPORT3_MTCS2 0xFFC02648 /* SPORT3 Multi-Channel Transmit Select Register 2 */
-#define SPORT3_MTCS3 0xFFC0264C /* SPORT3 Multi-Channel Transmit Select Register 3 */
-#define SPORT3_MRCS0 0xFFC02650 /* SPORT3 Multi-Channel Receive Select Register 0 */
-#define SPORT3_MRCS1 0xFFC02654 /* SPORT3 Multi-Channel Receive Select Register 1 */
-#define SPORT3_MRCS2 0xFFC02658 /* SPORT3 Multi-Channel Receive Select Register 2 */
-#define SPORT3_MRCS3 0xFFC0265C /* SPORT3 Multi-Channel Receive Select Register 3 */
-
-
-/* CAN Controller (0xFFC02A00 - 0xFFC02FFF) */
-/* For Mailboxes 0-15 */
-#define CAN_MC1 0xFFC02A00 /* Mailbox config reg 1 */
-#define CAN_MD1 0xFFC02A04 /* Mailbox direction reg 1 */
-#define CAN_TRS1 0xFFC02A08 /* Transmit Request Set reg 1 */
-#define CAN_TRR1 0xFFC02A0C /* Transmit Request Reset reg 1 */
-#define CAN_TA1 0xFFC02A10 /* Transmit Acknowledge reg 1 */
-#define CAN_AA1 0xFFC02A14 /* Transmit Abort Acknowledge reg 1 */
-#define CAN_RMP1 0xFFC02A18 /* Receive Message Pending reg 1 */
-#define CAN_RML1 0xFFC02A1C /* Receive Message Lost reg 1 */
-#define CAN_MBTIF1 0xFFC02A20 /* Mailbox Transmit Interrupt Flag reg 1 */
-#define CAN_MBRIF1 0xFFC02A24 /* Mailbox Receive Interrupt Flag reg 1 */
-#define CAN_MBIM1 0xFFC02A28 /* Mailbox Interrupt Mask reg 1 */
-#define CAN_RFH1 0xFFC02A2C /* Remote Frame Handling reg 1 */
-#define CAN_OPSS1 0xFFC02A30 /* Overwrite Protection Single Shot Xmission reg 1 */
-
-/* For Mailboxes 16-31 */
-#define CAN_MC2 0xFFC02A40 /* Mailbox config reg 2 */
-#define CAN_MD2 0xFFC02A44 /* Mailbox direction reg 2 */
-#define CAN_TRS2 0xFFC02A48 /* Transmit Request Set reg 2 */
-#define CAN_TRR2 0xFFC02A4C /* Transmit Request Reset reg 2 */
-#define CAN_TA2 0xFFC02A50 /* Transmit Acknowledge reg 2 */
-#define CAN_AA2 0xFFC02A54 /* Transmit Abort Acknowledge reg 2 */
-#define CAN_RMP2 0xFFC02A58 /* Receive Message Pending reg 2 */
-#define CAN_RML2 0xFFC02A5C /* Receive Message Lost reg 2 */
-#define CAN_MBTIF2 0xFFC02A60 /* Mailbox Transmit Interrupt Flag reg 2 */
-#define CAN_MBRIF2 0xFFC02A64 /* Mailbox Receive Interrupt Flag reg 2 */
-#define CAN_MBIM2 0xFFC02A68 /* Mailbox Interrupt Mask reg 2 */
-#define CAN_RFH2 0xFFC02A6C /* Remote Frame Handling reg 2 */
-#define CAN_OPSS2 0xFFC02A70 /* Overwrite Protection Single Shot Xmission reg 2 */
-
-#define CAN_CLOCK 0xFFC02A80 /* Bit Timing Configuration register 0 */
-#define CAN_TIMING 0xFFC02A84 /* Bit Timing Configuration register 1 */
-
-#define CAN_DEBUG 0xFFC02A88 /* Debug Register */
-/* the following is for backwards compatibility */
-#define CAN_CNF CAN_DEBUG
-
-#define CAN_STATUS 0xFFC02A8C /* Global Status Register */
-#define CAN_CEC 0xFFC02A90 /* Error Counter Register */
-#define CAN_GIS 0xFFC02A94 /* Global Interrupt Status Register */
-#define CAN_GIM 0xFFC02A98 /* Global Interrupt Mask Register */
-#define CAN_GIF 0xFFC02A9C /* Global Interrupt Flag Register */
-#define CAN_CONTROL 0xFFC02AA0 /* Master Control Register */
-#define CAN_INTR 0xFFC02AA4 /* Interrupt Pending Register */
-#define CAN_MBTD 0xFFC02AAC /* Mailbox Temporary Disable Feature */
-#define CAN_EWR 0xFFC02AB0 /* Programmable Warning Level */
-#define CAN_ESR 0xFFC02AB4 /* Error Status Register */
-#define CAN_UCCNT 0xFFC02AC4 /* Universal Counter */
-#define CAN_UCRC 0xFFC02AC8 /* Universal Counter Reload/Capture Register */
-#define CAN_UCCNF 0xFFC02ACC /* Universal Counter Configuration Register */
-
-/* Mailbox Acceptance Masks */
-#define CAN_AM00L 0xFFC02B00 /* Mailbox 0 Low Acceptance Mask */
-#define CAN_AM00H 0xFFC02B04 /* Mailbox 0 High Acceptance Mask */
-#define CAN_AM01L 0xFFC02B08 /* Mailbox 1 Low Acceptance Mask */
-#define CAN_AM01H 0xFFC02B0C /* Mailbox 1 High Acceptance Mask */
-#define CAN_AM02L 0xFFC02B10 /* Mailbox 2 Low Acceptance Mask */
-#define CAN_AM02H 0xFFC02B14 /* Mailbox 2 High Acceptance Mask */
-#define CAN_AM03L 0xFFC02B18 /* Mailbox 3 Low Acceptance Mask */
-#define CAN_AM03H 0xFFC02B1C /* Mailbox 3 High Acceptance Mask */
-#define CAN_AM04L 0xFFC02B20 /* Mailbox 4 Low Acceptance Mask */
-#define CAN_AM04H 0xFFC02B24 /* Mailbox 4 High Acceptance Mask */
-#define CAN_AM05L 0xFFC02B28 /* Mailbox 5 Low Acceptance Mask */
-#define CAN_AM05H 0xFFC02B2C /* Mailbox 5 High Acceptance Mask */
-#define CAN_AM06L 0xFFC02B30 /* Mailbox 6 Low Acceptance Mask */
-#define CAN_AM06H 0xFFC02B34 /* Mailbox 6 High Acceptance Mask */
-#define CAN_AM07L 0xFFC02B38 /* Mailbox 7 Low Acceptance Mask */
-#define CAN_AM07H 0xFFC02B3C /* Mailbox 7 High Acceptance Mask */
-#define CAN_AM08L 0xFFC02B40 /* Mailbox 8 Low Acceptance Mask */
-#define CAN_AM08H 0xFFC02B44 /* Mailbox 8 High Acceptance Mask */
-#define CAN_AM09L 0xFFC02B48 /* Mailbox 9 Low Acceptance Mask */
-#define CAN_AM09H 0xFFC02B4C /* Mailbox 9 High Acceptance Mask */
-#define CAN_AM10L 0xFFC02B50 /* Mailbox 10 Low Acceptance Mask */
-#define CAN_AM10H 0xFFC02B54 /* Mailbox 10 High Acceptance Mask */
-#define CAN_AM11L 0xFFC02B58 /* Mailbox 11 Low Acceptance Mask */
-#define CAN_AM11H 0xFFC02B5C /* Mailbox 11 High Acceptance Mask */
-#define CAN_AM12L 0xFFC02B60 /* Mailbox 12 Low Acceptance Mask */
-#define CAN_AM12H 0xFFC02B64 /* Mailbox 12 High Acceptance Mask */
-#define CAN_AM13L 0xFFC02B68 /* Mailbox 13 Low Acceptance Mask */
-#define CAN_AM13H 0xFFC02B6C /* Mailbox 13 High Acceptance Mask */
-#define CAN_AM14L 0xFFC02B70 /* Mailbox 14 Low Acceptance Mask */
-#define CAN_AM14H 0xFFC02B74 /* Mailbox 14 High Acceptance Mask */
-#define CAN_AM15L 0xFFC02B78 /* Mailbox 15 Low Acceptance Mask */
-#define CAN_AM15H 0xFFC02B7C /* Mailbox 15 High Acceptance Mask */
-
-#define CAN_AM16L 0xFFC02B80 /* Mailbox 16 Low Acceptance Mask */
-#define CAN_AM16H 0xFFC02B84 /* Mailbox 16 High Acceptance Mask */
-#define CAN_AM17L 0xFFC02B88 /* Mailbox 17 Low Acceptance Mask */
-#define CAN_AM17H 0xFFC02B8C /* Mailbox 17 High Acceptance Mask */
-#define CAN_AM18L 0xFFC02B90 /* Mailbox 18 Low Acceptance Mask */
-#define CAN_AM18H 0xFFC02B94 /* Mailbox 18 High Acceptance Mask */
-#define CAN_AM19L 0xFFC02B98 /* Mailbox 19 Low Acceptance Mask */
-#define CAN_AM19H 0xFFC02B9C /* Mailbox 19 High Acceptance Mask */
-#define CAN_AM20L 0xFFC02BA0 /* Mailbox 20 Low Acceptance Mask */
-#define CAN_AM20H 0xFFC02BA4 /* Mailbox 20 High Acceptance Mask */
-#define CAN_AM21L 0xFFC02BA8 /* Mailbox 21 Low Acceptance Mask */
-#define CAN_AM21H 0xFFC02BAC /* Mailbox 21 High Acceptance Mask */
-#define CAN_AM22L 0xFFC02BB0 /* Mailbox 22 Low Acceptance Mask */
-#define CAN_AM22H 0xFFC02BB4 /* Mailbox 22 High Acceptance Mask */
-#define CAN_AM23L 0xFFC02BB8 /* Mailbox 23 Low Acceptance Mask */
-#define CAN_AM23H 0xFFC02BBC /* Mailbox 23 High Acceptance Mask */
-#define CAN_AM24L 0xFFC02BC0 /* Mailbox 24 Low Acceptance Mask */
-#define CAN_AM24H 0xFFC02BC4 /* Mailbox 24 High Acceptance Mask */
-#define CAN_AM25L 0xFFC02BC8 /* Mailbox 25 Low Acceptance Mask */
-#define CAN_AM25H 0xFFC02BCC /* Mailbox 25 High Acceptance Mask */
-#define CAN_AM26L 0xFFC02BD0 /* Mailbox 26 Low Acceptance Mask */
-#define CAN_AM26H 0xFFC02BD4 /* Mailbox 26 High Acceptance Mask */
-#define CAN_AM27L 0xFFC02BD8 /* Mailbox 27 Low Acceptance Mask */
-#define CAN_AM27H 0xFFC02BDC /* Mailbox 27 High Acceptance Mask */
-#define CAN_AM28L 0xFFC02BE0 /* Mailbox 28 Low Acceptance Mask */
-#define CAN_AM28H 0xFFC02BE4 /* Mailbox 28 High Acceptance Mask */
-#define CAN_AM29L 0xFFC02BE8 /* Mailbox 29 Low Acceptance Mask */
-#define CAN_AM29H 0xFFC02BEC /* Mailbox 29 High Acceptance Mask */
-#define CAN_AM30L 0xFFC02BF0 /* Mailbox 30 Low Acceptance Mask */
-#define CAN_AM30H 0xFFC02BF4 /* Mailbox 30 High Acceptance Mask */
-#define CAN_AM31L 0xFFC02BF8 /* Mailbox 31 Low Acceptance Mask */
-#define CAN_AM31H 0xFFC02BFC /* Mailbox 31 High Acceptance Mask */
-
-/* CAN Acceptance Mask Macros */
-#define CAN_AM_L(x) (CAN_AM00L+((x)*0x8))
-#define CAN_AM_H(x) (CAN_AM00H+((x)*0x8))
-
-/* Mailbox Registers */
-#define CAN_MB00_DATA0 0xFFC02C00 /* Mailbox 0 Data Word 0 [15:0] Register */
-#define CAN_MB00_DATA1 0xFFC02C04 /* Mailbox 0 Data Word 1 [31:16] Register */
-#define CAN_MB00_DATA2 0xFFC02C08 /* Mailbox 0 Data Word 2 [47:32] Register */
-#define CAN_MB00_DATA3 0xFFC02C0C /* Mailbox 0 Data Word 3 [63:48] Register */
-#define CAN_MB00_LENGTH 0xFFC02C10 /* Mailbox 0 Data Length Code Register */
-#define CAN_MB00_TIMESTAMP 0xFFC02C14 /* Mailbox 0 Time Stamp Value Register */
-#define CAN_MB00_ID0 0xFFC02C18 /* Mailbox 0 Identifier Low Register */
-#define CAN_MB00_ID1 0xFFC02C1C /* Mailbox 0 Identifier High Register */
-
-#define CAN_MB01_DATA0 0xFFC02C20 /* Mailbox 1 Data Word 0 [15:0] Register */
-#define CAN_MB01_DATA1 0xFFC02C24 /* Mailbox 1 Data Word 1 [31:16] Register */
-#define CAN_MB01_DATA2 0xFFC02C28 /* Mailbox 1 Data Word 2 [47:32] Register */
-#define CAN_MB01_DATA3 0xFFC02C2C /* Mailbox 1 Data Word 3 [63:48] Register */
-#define CAN_MB01_LENGTH 0xFFC02C30 /* Mailbox 1 Data Length Code Register */
-#define CAN_MB01_TIMESTAMP 0xFFC02C34 /* Mailbox 1 Time Stamp Value Register */
-#define CAN_MB01_ID0 0xFFC02C38 /* Mailbox 1 Identifier Low Register */
-#define CAN_MB01_ID1 0xFFC02C3C /* Mailbox 1 Identifier High Register */
-
-#define CAN_MB02_DATA0 0xFFC02C40 /* Mailbox 2 Data Word 0 [15:0] Register */
-#define CAN_MB02_DATA1 0xFFC02C44 /* Mailbox 2 Data Word 1 [31:16] Register */
-#define CAN_MB02_DATA2 0xFFC02C48 /* Mailbox 2 Data Word 2 [47:32] Register */
-#define CAN_MB02_DATA3 0xFFC02C4C /* Mailbox 2 Data Word 3 [63:48] Register */
-#define CAN_MB02_LENGTH 0xFFC02C50 /* Mailbox 2 Data Length Code Register */
-#define CAN_MB02_TIMESTAMP 0xFFC02C54 /* Mailbox 2 Time Stamp Value Register */
-#define CAN_MB02_ID0 0xFFC02C58 /* Mailbox 2 Identifier Low Register */
-#define CAN_MB02_ID1 0xFFC02C5C /* Mailbox 2 Identifier High Register */
-
-#define CAN_MB03_DATA0 0xFFC02C60 /* Mailbox 3 Data Word 0 [15:0] Register */
-#define CAN_MB03_DATA1 0xFFC02C64 /* Mailbox 3 Data Word 1 [31:16] Register */
-#define CAN_MB03_DATA2 0xFFC02C68 /* Mailbox 3 Data Word 2 [47:32] Register */
-#define CAN_MB03_DATA3 0xFFC02C6C /* Mailbox 3 Data Word 3 [63:48] Register */
-#define CAN_MB03_LENGTH 0xFFC02C70 /* Mailbox 3 Data Length Code Register */
-#define CAN_MB03_TIMESTAMP 0xFFC02C74 /* Mailbox 3 Time Stamp Value Register */
-#define CAN_MB03_ID0 0xFFC02C78 /* Mailbox 3 Identifier Low Register */
-#define CAN_MB03_ID1 0xFFC02C7C /* Mailbox 3 Identifier High Register */
-
-#define CAN_MB04_DATA0 0xFFC02C80 /* Mailbox 4 Data Word 0 [15:0] Register */
-#define CAN_MB04_DATA1 0xFFC02C84 /* Mailbox 4 Data Word 1 [31:16] Register */
-#define CAN_MB04_DATA2 0xFFC02C88 /* Mailbox 4 Data Word 2 [47:32] Register */
-#define CAN_MB04_DATA3 0xFFC02C8C /* Mailbox 4 Data Word 3 [63:48] Register */
-#define CAN_MB04_LENGTH 0xFFC02C90 /* Mailbox 4 Data Length Code Register */
-#define CAN_MB04_TIMESTAMP 0xFFC02C94 /* Mailbox 4 Time Stamp Value Register */
-#define CAN_MB04_ID0 0xFFC02C98 /* Mailbox 4 Identifier Low Register */
-#define CAN_MB04_ID1 0xFFC02C9C /* Mailbox 4 Identifier High Register */
-
-#define CAN_MB05_DATA0 0xFFC02CA0 /* Mailbox 5 Data Word 0 [15:0] Register */
-#define CAN_MB05_DATA1 0xFFC02CA4 /* Mailbox 5 Data Word 1 [31:16] Register */
-#define CAN_MB05_DATA2 0xFFC02CA8 /* Mailbox 5 Data Word 2 [47:32] Register */
-#define CAN_MB05_DATA3 0xFFC02CAC /* Mailbox 5 Data Word 3 [63:48] Register */
-#define CAN_MB05_LENGTH 0xFFC02CB0 /* Mailbox 5 Data Length Code Register */
-#define CAN_MB05_TIMESTAMP 0xFFC02CB4 /* Mailbox 5 Time Stamp Value Register */
-#define CAN_MB05_ID0 0xFFC02CB8 /* Mailbox 5 Identifier Low Register */
-#define CAN_MB05_ID1 0xFFC02CBC /* Mailbox 5 Identifier High Register */
-
-#define CAN_MB06_DATA0 0xFFC02CC0 /* Mailbox 6 Data Word 0 [15:0] Register */
-#define CAN_MB06_DATA1 0xFFC02CC4 /* Mailbox 6 Data Word 1 [31:16] Register */
-#define CAN_MB06_DATA2 0xFFC02CC8 /* Mailbox 6 Data Word 2 [47:32] Register */
-#define CAN_MB06_DATA3 0xFFC02CCC /* Mailbox 6 Data Word 3 [63:48] Register */
-#define CAN_MB06_LENGTH 0xFFC02CD0 /* Mailbox 6 Data Length Code Register */
-#define CAN_MB06_TIMESTAMP 0xFFC02CD4 /* Mailbox 6 Time Stamp Value Register */
-#define CAN_MB06_ID0 0xFFC02CD8 /* Mailbox 6 Identifier Low Register */
-#define CAN_MB06_ID1 0xFFC02CDC /* Mailbox 6 Identifier High Register */
-
-#define CAN_MB07_DATA0 0xFFC02CE0 /* Mailbox 7 Data Word 0 [15:0] Register */
-#define CAN_MB07_DATA1 0xFFC02CE4 /* Mailbox 7 Data Word 1 [31:16] Register */
-#define CAN_MB07_DATA2 0xFFC02CE8 /* Mailbox 7 Data Word 2 [47:32] Register */
-#define CAN_MB07_DATA3 0xFFC02CEC /* Mailbox 7 Data Word 3 [63:48] Register */
-#define CAN_MB07_LENGTH 0xFFC02CF0 /* Mailbox 7 Data Length Code Register */
-#define CAN_MB07_TIMESTAMP 0xFFC02CF4 /* Mailbox 7 Time Stamp Value Register */
-#define CAN_MB07_ID0 0xFFC02CF8 /* Mailbox 7 Identifier Low Register */
-#define CAN_MB07_ID1 0xFFC02CFC /* Mailbox 7 Identifier High Register */
-
-#define CAN_MB08_DATA0 0xFFC02D00 /* Mailbox 8 Data Word 0 [15:0] Register */
-#define CAN_MB08_DATA1 0xFFC02D04 /* Mailbox 8 Data Word 1 [31:16] Register */
-#define CAN_MB08_DATA2 0xFFC02D08 /* Mailbox 8 Data Word 2 [47:32] Register */
-#define CAN_MB08_DATA3 0xFFC02D0C /* Mailbox 8 Data Word 3 [63:48] Register */
-#define CAN_MB08_LENGTH 0xFFC02D10 /* Mailbox 8 Data Length Code Register */
-#define CAN_MB08_TIMESTAMP 0xFFC02D14 /* Mailbox 8 Time Stamp Value Register */
-#define CAN_MB08_ID0 0xFFC02D18 /* Mailbox 8 Identifier Low Register */
-#define CAN_MB08_ID1 0xFFC02D1C /* Mailbox 8 Identifier High Register */
-
-#define CAN_MB09_DATA0 0xFFC02D20 /* Mailbox 9 Data Word 0 [15:0] Register */
-#define CAN_MB09_DATA1 0xFFC02D24 /* Mailbox 9 Data Word 1 [31:16] Register */
-#define CAN_MB09_DATA2 0xFFC02D28 /* Mailbox 9 Data Word 2 [47:32] Register */
-#define CAN_MB09_DATA3 0xFFC02D2C /* Mailbox 9 Data Word 3 [63:48] Register */
-#define CAN_MB09_LENGTH 0xFFC02D30 /* Mailbox 9 Data Length Code Register */
-#define CAN_MB09_TIMESTAMP 0xFFC02D34 /* Mailbox 9 Time Stamp Value Register */
-#define CAN_MB09_ID0 0xFFC02D38 /* Mailbox 9 Identifier Low Register */
-#define CAN_MB09_ID1 0xFFC02D3C /* Mailbox 9 Identifier High Register */
-
-#define CAN_MB10_DATA0 0xFFC02D40 /* Mailbox 10 Data Word 0 [15:0] Register */
-#define CAN_MB10_DATA1 0xFFC02D44 /* Mailbox 10 Data Word 1 [31:16] Register */
-#define CAN_MB10_DATA2 0xFFC02D48 /* Mailbox 10 Data Word 2 [47:32] Register */
-#define CAN_MB10_DATA3 0xFFC02D4C /* Mailbox 10 Data Word 3 [63:48] Register */
-#define CAN_MB10_LENGTH 0xFFC02D50 /* Mailbox 10 Data Length Code Register */
-#define CAN_MB10_TIMESTAMP 0xFFC02D54 /* Mailbox 10 Time Stamp Value Register */
-#define CAN_MB10_ID0 0xFFC02D58 /* Mailbox 10 Identifier Low Register */
-#define CAN_MB10_ID1 0xFFC02D5C /* Mailbox 10 Identifier High Register */
-
-#define CAN_MB11_DATA0 0xFFC02D60 /* Mailbox 11 Data Word 0 [15:0] Register */
-#define CAN_MB11_DATA1 0xFFC02D64 /* Mailbox 11 Data Word 1 [31:16] Register */
-#define CAN_MB11_DATA2 0xFFC02D68 /* Mailbox 11 Data Word 2 [47:32] Register */
-#define CAN_MB11_DATA3 0xFFC02D6C /* Mailbox 11 Data Word 3 [63:48] Register */
-#define CAN_MB11_LENGTH 0xFFC02D70 /* Mailbox 11 Data Length Code Register */
-#define CAN_MB11_TIMESTAMP 0xFFC02D74 /* Mailbox 11 Time Stamp Value Register */
-#define CAN_MB11_ID0 0xFFC02D78 /* Mailbox 11 Identifier Low Register */
-#define CAN_MB11_ID1 0xFFC02D7C /* Mailbox 11 Identifier High Register */
-
-#define CAN_MB12_DATA0 0xFFC02D80 /* Mailbox 12 Data Word 0 [15:0] Register */
-#define CAN_MB12_DATA1 0xFFC02D84 /* Mailbox 12 Data Word 1 [31:16] Register */
-#define CAN_MB12_DATA2 0xFFC02D88 /* Mailbox 12 Data Word 2 [47:32] Register */
-#define CAN_MB12_DATA3 0xFFC02D8C /* Mailbox 12 Data Word 3 [63:48] Register */
-#define CAN_MB12_LENGTH 0xFFC02D90 /* Mailbox 12 Data Length Code Register */
-#define CAN_MB12_TIMESTAMP 0xFFC02D94 /* Mailbox 12 Time Stamp Value Register */
-#define CAN_MB12_ID0 0xFFC02D98 /* Mailbox 12 Identifier Low Register */
-#define CAN_MB12_ID1 0xFFC02D9C /* Mailbox 12 Identifier High Register */
-
-#define CAN_MB13_DATA0 0xFFC02DA0 /* Mailbox 13 Data Word 0 [15:0] Register */
-#define CAN_MB13_DATA1 0xFFC02DA4 /* Mailbox 13 Data Word 1 [31:16] Register */
-#define CAN_MB13_DATA2 0xFFC02DA8 /* Mailbox 13 Data Word 2 [47:32] Register */
-#define CAN_MB13_DATA3 0xFFC02DAC /* Mailbox 13 Data Word 3 [63:48] Register */
-#define CAN_MB13_LENGTH 0xFFC02DB0 /* Mailbox 13 Data Length Code Register */
-#define CAN_MB13_TIMESTAMP 0xFFC02DB4 /* Mailbox 13 Time Stamp Value Register */
-#define CAN_MB13_ID0 0xFFC02DB8 /* Mailbox 13 Identifier Low Register */
-#define CAN_MB13_ID1 0xFFC02DBC /* Mailbox 13 Identifier High Register */
-
-#define CAN_MB14_DATA0 0xFFC02DC0 /* Mailbox 14 Data Word 0 [15:0] Register */
-#define CAN_MB14_DATA1 0xFFC02DC4 /* Mailbox 14 Data Word 1 [31:16] Register */
-#define CAN_MB14_DATA2 0xFFC02DC8 /* Mailbox 14 Data Word 2 [47:32] Register */
-#define CAN_MB14_DATA3 0xFFC02DCC /* Mailbox 14 Data Word 3 [63:48] Register */
-#define CAN_MB14_LENGTH 0xFFC02DD0 /* Mailbox 14 Data Length Code Register */
-#define CAN_MB14_TIMESTAMP 0xFFC02DD4 /* Mailbox 14 Time Stamp Value Register */
-#define CAN_MB14_ID0 0xFFC02DD8 /* Mailbox 14 Identifier Low Register */
-#define CAN_MB14_ID1 0xFFC02DDC /* Mailbox 14 Identifier High Register */
-
-#define CAN_MB15_DATA0 0xFFC02DE0 /* Mailbox 15 Data Word 0 [15:0] Register */
-#define CAN_MB15_DATA1 0xFFC02DE4 /* Mailbox 15 Data Word 1 [31:16] Register */
-#define CAN_MB15_DATA2 0xFFC02DE8 /* Mailbox 15 Data Word 2 [47:32] Register */
-#define CAN_MB15_DATA3 0xFFC02DEC /* Mailbox 15 Data Word 3 [63:48] Register */
-#define CAN_MB15_LENGTH 0xFFC02DF0 /* Mailbox 15 Data Length Code Register */
-#define CAN_MB15_TIMESTAMP 0xFFC02DF4 /* Mailbox 15 Time Stamp Value Register */
-#define CAN_MB15_ID0 0xFFC02DF8 /* Mailbox 15 Identifier Low Register */
-#define CAN_MB15_ID1 0xFFC02DFC /* Mailbox 15 Identifier High Register */
-
-#define CAN_MB16_DATA0 0xFFC02E00 /* Mailbox 16 Data Word 0 [15:0] Register */
-#define CAN_MB16_DATA1 0xFFC02E04 /* Mailbox 16 Data Word 1 [31:16] Register */
-#define CAN_MB16_DATA2 0xFFC02E08 /* Mailbox 16 Data Word 2 [47:32] Register */
-#define CAN_MB16_DATA3 0xFFC02E0C /* Mailbox 16 Data Word 3 [63:48] Register */
-#define CAN_MB16_LENGTH 0xFFC02E10 /* Mailbox 16 Data Length Code Register */
-#define CAN_MB16_TIMESTAMP 0xFFC02E14 /* Mailbox 16 Time Stamp Value Register */
-#define CAN_MB16_ID0 0xFFC02E18 /* Mailbox 16 Identifier Low Register */
-#define CAN_MB16_ID1 0xFFC02E1C /* Mailbox 16 Identifier High Register */
-
-#define CAN_MB17_DATA0 0xFFC02E20 /* Mailbox 17 Data Word 0 [15:0] Register */
-#define CAN_MB17_DATA1 0xFFC02E24 /* Mailbox 17 Data Word 1 [31:16] Register */
-#define CAN_MB17_DATA2 0xFFC02E28 /* Mailbox 17 Data Word 2 [47:32] Register */
-#define CAN_MB17_DATA3 0xFFC02E2C /* Mailbox 17 Data Word 3 [63:48] Register */
-#define CAN_MB17_LENGTH 0xFFC02E30 /* Mailbox 17 Data Length Code Register */
-#define CAN_MB17_TIMESTAMP 0xFFC02E34 /* Mailbox 17 Time Stamp Value Register */
-#define CAN_MB17_ID0 0xFFC02E38 /* Mailbox 17 Identifier Low Register */
-#define CAN_MB17_ID1 0xFFC02E3C /* Mailbox 17 Identifier High Register */
-
-#define CAN_MB18_DATA0 0xFFC02E40 /* Mailbox 18 Data Word 0 [15:0] Register */
-#define CAN_MB18_DATA1 0xFFC02E44 /* Mailbox 18 Data Word 1 [31:16] Register */
-#define CAN_MB18_DATA2 0xFFC02E48 /* Mailbox 18 Data Word 2 [47:32] Register */
-#define CAN_MB18_DATA3 0xFFC02E4C /* Mailbox 18 Data Word 3 [63:48] Register */
-#define CAN_MB18_LENGTH 0xFFC02E50 /* Mailbox 18 Data Length Code Register */
-#define CAN_MB18_TIMESTAMP 0xFFC02E54 /* Mailbox 18 Time Stamp Value Register */
-#define CAN_MB18_ID0 0xFFC02E58 /* Mailbox 18 Identifier Low Register */
-#define CAN_MB18_ID1 0xFFC02E5C /* Mailbox 18 Identifier High Register */
-
-#define CAN_MB19_DATA0 0xFFC02E60 /* Mailbox 19 Data Word 0 [15:0] Register */
-#define CAN_MB19_DATA1 0xFFC02E64 /* Mailbox 19 Data Word 1 [31:16] Register */
-#define CAN_MB19_DATA2 0xFFC02E68 /* Mailbox 19 Data Word 2 [47:32] Register */
-#define CAN_MB19_DATA3 0xFFC02E6C /* Mailbox 19 Data Word 3 [63:48] Register */
-#define CAN_MB19_LENGTH 0xFFC02E70 /* Mailbox 19 Data Length Code Register */
-#define CAN_MB19_TIMESTAMP 0xFFC02E74 /* Mailbox 19 Time Stamp Value Register */
-#define CAN_MB19_ID0 0xFFC02E78 /* Mailbox 19 Identifier Low Register */
-#define CAN_MB19_ID1 0xFFC02E7C /* Mailbox 19 Identifier High Register */
-
-#define CAN_MB20_DATA0 0xFFC02E80 /* Mailbox 20 Data Word 0 [15:0] Register */
-#define CAN_MB20_DATA1 0xFFC02E84 /* Mailbox 20 Data Word 1 [31:16] Register */
-#define CAN_MB20_DATA2 0xFFC02E88 /* Mailbox 20 Data Word 2 [47:32] Register */
-#define CAN_MB20_DATA3 0xFFC02E8C /* Mailbox 20 Data Word 3 [63:48] Register */
-#define CAN_MB20_LENGTH 0xFFC02E90 /* Mailbox 20 Data Length Code Register */
-#define CAN_MB20_TIMESTAMP 0xFFC02E94 /* Mailbox 20 Time Stamp Value Register */
-#define CAN_MB20_ID0 0xFFC02E98 /* Mailbox 20 Identifier Low Register */
-#define CAN_MB20_ID1 0xFFC02E9C /* Mailbox 20 Identifier High Register */
-
-#define CAN_MB21_DATA0 0xFFC02EA0 /* Mailbox 21 Data Word 0 [15:0] Register */
-#define CAN_MB21_DATA1 0xFFC02EA4 /* Mailbox 21 Data Word 1 [31:16] Register */
-#define CAN_MB21_DATA2 0xFFC02EA8 /* Mailbox 21 Data Word 2 [47:32] Register */
-#define CAN_MB21_DATA3 0xFFC02EAC /* Mailbox 21 Data Word 3 [63:48] Register */
-#define CAN_MB21_LENGTH 0xFFC02EB0 /* Mailbox 21 Data Length Code Register */
-#define CAN_MB21_TIMESTAMP 0xFFC02EB4 /* Mailbox 21 Time Stamp Value Register */
-#define CAN_MB21_ID0 0xFFC02EB8 /* Mailbox 21 Identifier Low Register */
-#define CAN_MB21_ID1 0xFFC02EBC /* Mailbox 21 Identifier High Register */
-
-#define CAN_MB22_DATA0 0xFFC02EC0 /* Mailbox 22 Data Word 0 [15:0] Register */
-#define CAN_MB22_DATA1 0xFFC02EC4 /* Mailbox 22 Data Word 1 [31:16] Register */
-#define CAN_MB22_DATA2 0xFFC02EC8 /* Mailbox 22 Data Word 2 [47:32] Register */
-#define CAN_MB22_DATA3 0xFFC02ECC /* Mailbox 22 Data Word 3 [63:48] Register */
-#define CAN_MB22_LENGTH 0xFFC02ED0 /* Mailbox 22 Data Length Code Register */
-#define CAN_MB22_TIMESTAMP 0xFFC02ED4 /* Mailbox 22 Time Stamp Value Register */
-#define CAN_MB22_ID0 0xFFC02ED8 /* Mailbox 22 Identifier Low Register */
-#define CAN_MB22_ID1 0xFFC02EDC /* Mailbox 22 Identifier High Register */
-
-#define CAN_MB23_DATA0 0xFFC02EE0 /* Mailbox 23 Data Word 0 [15:0] Register */
-#define CAN_MB23_DATA1 0xFFC02EE4 /* Mailbox 23 Data Word 1 [31:16] Register */
-#define CAN_MB23_DATA2 0xFFC02EE8 /* Mailbox 23 Data Word 2 [47:32] Register */
-#define CAN_MB23_DATA3 0xFFC02EEC /* Mailbox 23 Data Word 3 [63:48] Register */
-#define CAN_MB23_LENGTH 0xFFC02EF0 /* Mailbox 23 Data Length Code Register */
-#define CAN_MB23_TIMESTAMP 0xFFC02EF4 /* Mailbox 23 Time Stamp Value Register */
-#define CAN_MB23_ID0 0xFFC02EF8 /* Mailbox 23 Identifier Low Register */
-#define CAN_MB23_ID1 0xFFC02EFC /* Mailbox 23 Identifier High Register */
-
-#define CAN_MB24_DATA0 0xFFC02F00 /* Mailbox 24 Data Word 0 [15:0] Register */
-#define CAN_MB24_DATA1 0xFFC02F04 /* Mailbox 24 Data Word 1 [31:16] Register */
-#define CAN_MB24_DATA2 0xFFC02F08 /* Mailbox 24 Data Word 2 [47:32] Register */
-#define CAN_MB24_DATA3 0xFFC02F0C /* Mailbox 24 Data Word 3 [63:48] Register */
-#define CAN_MB24_LENGTH 0xFFC02F10 /* Mailbox 24 Data Length Code Register */
-#define CAN_MB24_TIMESTAMP 0xFFC02F14 /* Mailbox 24 Time Stamp Value Register */
-#define CAN_MB24_ID0 0xFFC02F18 /* Mailbox 24 Identifier Low Register */
-#define CAN_MB24_ID1 0xFFC02F1C /* Mailbox 24 Identifier High Register */
-
-#define CAN_MB25_DATA0 0xFFC02F20 /* Mailbox 25 Data Word 0 [15:0] Register */
-#define CAN_MB25_DATA1 0xFFC02F24 /* Mailbox 25 Data Word 1 [31:16] Register */
-#define CAN_MB25_DATA2 0xFFC02F28 /* Mailbox 25 Data Word 2 [47:32] Register */
-#define CAN_MB25_DATA3 0xFFC02F2C /* Mailbox 25 Data Word 3 [63:48] Register */
-#define CAN_MB25_LENGTH 0xFFC02F30 /* Mailbox 25 Data Length Code Register */
-#define CAN_MB25_TIMESTAMP 0xFFC02F34 /* Mailbox 25 Time Stamp Value Register */
-#define CAN_MB25_ID0 0xFFC02F38 /* Mailbox 25 Identifier Low Register */
-#define CAN_MB25_ID1 0xFFC02F3C /* Mailbox 25 Identifier High Register */
-
-#define CAN_MB26_DATA0 0xFFC02F40 /* Mailbox 26 Data Word 0 [15:0] Register */
-#define CAN_MB26_DATA1 0xFFC02F44 /* Mailbox 26 Data Word 1 [31:16] Register */
-#define CAN_MB26_DATA2 0xFFC02F48 /* Mailbox 26 Data Word 2 [47:32] Register */
-#define CAN_MB26_DATA3 0xFFC02F4C /* Mailbox 26 Data Word 3 [63:48] Register */
-#define CAN_MB26_LENGTH 0xFFC02F50 /* Mailbox 26 Data Length Code Register */
-#define CAN_MB26_TIMESTAMP 0xFFC02F54 /* Mailbox 26 Time Stamp Value Register */
-#define CAN_MB26_ID0 0xFFC02F58 /* Mailbox 26 Identifier Low Register */
-#define CAN_MB26_ID1 0xFFC02F5C /* Mailbox 26 Identifier High Register */
-
-#define CAN_MB27_DATA0 0xFFC02F60 /* Mailbox 27 Data Word 0 [15:0] Register */
-#define CAN_MB27_DATA1 0xFFC02F64 /* Mailbox 27 Data Word 1 [31:16] Register */
-#define CAN_MB27_DATA2 0xFFC02F68 /* Mailbox 27 Data Word 2 [47:32] Register */
-#define CAN_MB27_DATA3 0xFFC02F6C /* Mailbox 27 Data Word 3 [63:48] Register */
-#define CAN_MB27_LENGTH 0xFFC02F70 /* Mailbox 27 Data Length Code Register */
-#define CAN_MB27_TIMESTAMP 0xFFC02F74 /* Mailbox 27 Time Stamp Value Register */
-#define CAN_MB27_ID0 0xFFC02F78 /* Mailbox 27 Identifier Low Register */
-#define CAN_MB27_ID1 0xFFC02F7C /* Mailbox 27 Identifier High Register */
-
-#define CAN_MB28_DATA0 0xFFC02F80 /* Mailbox 28 Data Word 0 [15:0] Register */
-#define CAN_MB28_DATA1 0xFFC02F84 /* Mailbox 28 Data Word 1 [31:16] Register */
-#define CAN_MB28_DATA2 0xFFC02F88 /* Mailbox 28 Data Word 2 [47:32] Register */
-#define CAN_MB28_DATA3 0xFFC02F8C /* Mailbox 28 Data Word 3 [63:48] Register */
-#define CAN_MB28_LENGTH 0xFFC02F90 /* Mailbox 28 Data Length Code Register */
-#define CAN_MB28_TIMESTAMP 0xFFC02F94 /* Mailbox 28 Time Stamp Value Register */
-#define CAN_MB28_ID0 0xFFC02F98 /* Mailbox 28 Identifier Low Register */
-#define CAN_MB28_ID1 0xFFC02F9C /* Mailbox 28 Identifier High Register */
-
-#define CAN_MB29_DATA0 0xFFC02FA0 /* Mailbox 29 Data Word 0 [15:0] Register */
-#define CAN_MB29_DATA1 0xFFC02FA4 /* Mailbox 29 Data Word 1 [31:16] Register */
-#define CAN_MB29_DATA2 0xFFC02FA8 /* Mailbox 29 Data Word 2 [47:32] Register */
-#define CAN_MB29_DATA3 0xFFC02FAC /* Mailbox 29 Data Word 3 [63:48] Register */
-#define CAN_MB29_LENGTH 0xFFC02FB0 /* Mailbox 29 Data Length Code Register */
-#define CAN_MB29_TIMESTAMP 0xFFC02FB4 /* Mailbox 29 Time Stamp Value Register */
-#define CAN_MB29_ID0 0xFFC02FB8 /* Mailbox 29 Identifier Low Register */
-#define CAN_MB29_ID1 0xFFC02FBC /* Mailbox 29 Identifier High Register */
-
-#define CAN_MB30_DATA0 0xFFC02FC0 /* Mailbox 30 Data Word 0 [15:0] Register */
-#define CAN_MB30_DATA1 0xFFC02FC4 /* Mailbox 30 Data Word 1 [31:16] Register */
-#define CAN_MB30_DATA2 0xFFC02FC8 /* Mailbox 30 Data Word 2 [47:32] Register */
-#define CAN_MB30_DATA3 0xFFC02FCC /* Mailbox 30 Data Word 3 [63:48] Register */
-#define CAN_MB30_LENGTH 0xFFC02FD0 /* Mailbox 30 Data Length Code Register */
-#define CAN_MB30_TIMESTAMP 0xFFC02FD4 /* Mailbox 30 Time Stamp Value Register */
-#define CAN_MB30_ID0 0xFFC02FD8 /* Mailbox 30 Identifier Low Register */
-#define CAN_MB30_ID1 0xFFC02FDC /* Mailbox 30 Identifier High Register */
-
-#define CAN_MB31_DATA0 0xFFC02FE0 /* Mailbox 31 Data Word 0 [15:0] Register */
-#define CAN_MB31_DATA1 0xFFC02FE4 /* Mailbox 31 Data Word 1 [31:16] Register */
-#define CAN_MB31_DATA2 0xFFC02FE8 /* Mailbox 31 Data Word 2 [47:32] Register */
-#define CAN_MB31_DATA3 0xFFC02FEC /* Mailbox 31 Data Word 3 [63:48] Register */
-#define CAN_MB31_LENGTH 0xFFC02FF0 /* Mailbox 31 Data Length Code Register */
-#define CAN_MB31_TIMESTAMP 0xFFC02FF4 /* Mailbox 31 Time Stamp Value Register */
-#define CAN_MB31_ID0 0xFFC02FF8 /* Mailbox 31 Identifier Low Register */
-#define CAN_MB31_ID1 0xFFC02FFC /* Mailbox 31 Identifier High Register */
-
-/* CAN Mailbox Area Macros */
-#define CAN_MB_ID1(x) (CAN_MB00_ID1+((x)*0x20))
-#define CAN_MB_ID0(x) (CAN_MB00_ID0+((x)*0x20))
-#define CAN_MB_TIMESTAMP(x) (CAN_MB00_TIMESTAMP+((x)*0x20))
-#define CAN_MB_LENGTH(x) (CAN_MB00_LENGTH+((x)*0x20))
-#define CAN_MB_DATA3(x) (CAN_MB00_DATA3+((x)*0x20))
-#define CAN_MB_DATA2(x) (CAN_MB00_DATA2+((x)*0x20))
-#define CAN_MB_DATA1(x) (CAN_MB00_DATA1+((x)*0x20))
-#define CAN_MB_DATA0(x) (CAN_MB00_DATA0+((x)*0x20))
-
-
-/*********************************************************************************** */
-/* System MMR Register Bits and Macros */
-/******************************************************************************* */
-
-/* SWRST Mask */
-#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
-#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
-#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
-#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
-#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
-
-/* SYSCR Masks */
-#define BMODE 0x0006 /* Boot Mode - Latched During HW Reset From Mode Pins */
-#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
-
-
-/* ************* SYSTEM INTERRUPT CONTROLLER MASKS ***************** */
-
-/* Peripheral Masks For SIC0_ISR, SIC0_IWR, SIC0_IMASK */
-#define PLL_WAKEUP_IRQ 0x00000001 /* PLL Wakeup Interrupt Request */
-#define DMAC0_ERR_IRQ 0x00000002 /* DMA Controller 0 Error Interrupt Request */
-#define PPI_ERR_IRQ 0x00000004 /* PPI Error Interrupt Request */
-#define SPORT0_ERR_IRQ 0x00000008 /* SPORT0 Error Interrupt Request */
-#define SPORT1_ERR_IRQ 0x00000010 /* SPORT1 Error Interrupt Request */
-#define SPI0_ERR_IRQ 0x00000020 /* SPI0 Error Interrupt Request */
-#define UART0_ERR_IRQ 0x00000040 /* UART0 Error Interrupt Request */
-#define RTC_IRQ 0x00000080 /* Real-Time Clock Interrupt Request */
-#define DMA0_IRQ 0x00000100 /* DMA Channel 0 (PPI) Interrupt Request */
-#define DMA1_IRQ 0x00000200 /* DMA Channel 1 (SPORT0 RX) Interrupt Request */
-#define DMA2_IRQ 0x00000400 /* DMA Channel 2 (SPORT0 TX) Interrupt Request */
-#define DMA3_IRQ 0x00000800 /* DMA Channel 3 (SPORT1 RX) Interrupt Request */
-#define DMA4_IRQ 0x00001000 /* DMA Channel 4 (SPORT1 TX) Interrupt Request */
-#define DMA5_IRQ 0x00002000 /* DMA Channel 5 (SPI) Interrupt Request */
-#define DMA6_IRQ 0x00004000 /* DMA Channel 6 (UART RX) Interrupt Request */
-#define DMA7_IRQ 0x00008000 /* DMA Channel 7 (UART TX) Interrupt Request */
-#define TIMER0_IRQ 0x00010000 /* Timer 0 Interrupt Request */
-#define TIMER1_IRQ 0x00020000 /* Timer 1 Interrupt Request */
-#define TIMER2_IRQ 0x00040000 /* Timer 2 Interrupt Request */
-#define PFA_IRQ 0x00080000 /* Programmable Flag Interrupt Request A */
-#define PFB_IRQ 0x00100000 /* Programmable Flag Interrupt Request B */
-#define MDMA0_0_IRQ 0x00200000 /* MemDMA0 Stream 0 Interrupt Request */
-#define MDMA0_1_IRQ 0x00400000 /* MemDMA0 Stream 1 Interrupt Request */
-#define WDOG_IRQ 0x00800000 /* Software Watchdog Timer Interrupt Request */
-#define DMAC1_ERR_IRQ 0x01000000 /* DMA Controller 1 Error Interrupt Request */
-#define SPORT2_ERR_IRQ 0x02000000 /* SPORT2 Error Interrupt Request */
-#define SPORT3_ERR_IRQ 0x04000000 /* SPORT3 Error Interrupt Request */
-#define MXVR_SD_IRQ 0x08000000 /* MXVR Synchronous Data Interrupt Request */
-#define SPI1_ERR_IRQ 0x10000000 /* SPI1 Error Interrupt Request */
-#define SPI2_ERR_IRQ 0x20000000 /* SPI2 Error Interrupt Request */
-#define UART1_ERR_IRQ 0x40000000 /* UART1 Error Interrupt Request */
-#define UART2_ERR_IRQ 0x80000000 /* UART2 Error Interrupt Request */
-
-/* the following are for backwards compatibility */
-#define DMA0_ERR_IRQ DMAC0_ERR_IRQ
-#define DMA1_ERR_IRQ DMAC1_ERR_IRQ
-
-
-/* Peripheral Masks For SIC_ISR1, SIC_IWR1, SIC_IMASK1 */
-#define CAN_ERR_IRQ 0x00000001 /* CAN Error Interrupt Request */
-#define DMA8_IRQ 0x00000002 /* DMA Channel 8 (SPORT2 RX) Interrupt Request */
-#define DMA9_IRQ 0x00000004 /* DMA Channel 9 (SPORT2 TX) Interrupt Request */
-#define DMA10_IRQ 0x00000008 /* DMA Channel 10 (SPORT3 RX) Interrupt Request */
-#define DMA11_IRQ 0x00000010 /* DMA Channel 11 (SPORT3 TX) Interrupt Request */
-#define DMA12_IRQ 0x00000020 /* DMA Channel 12 Interrupt Request */
-#define DMA13_IRQ 0x00000040 /* DMA Channel 13 Interrupt Request */
-#define DMA14_IRQ 0x00000080 /* DMA Channel 14 (SPI1) Interrupt Request */
-#define DMA15_IRQ 0x00000100 /* DMA Channel 15 (SPI2) Interrupt Request */
-#define DMA16_IRQ 0x00000200 /* DMA Channel 16 (UART1 RX) Interrupt Request */
-#define DMA17_IRQ 0x00000400 /* DMA Channel 17 (UART1 TX) Interrupt Request */
-#define DMA18_IRQ 0x00000800 /* DMA Channel 18 (UART2 RX) Interrupt Request */
-#define DMA19_IRQ 0x00001000 /* DMA Channel 19 (UART2 TX) Interrupt Request */
-#define TWI0_IRQ 0x00002000 /* TWI0 Interrupt Request */
-#define TWI1_IRQ 0x00004000 /* TWI1 Interrupt Request */
-#define CAN_RX_IRQ 0x00008000 /* CAN Receive Interrupt Request */
-#define CAN_TX_IRQ 0x00010000 /* CAN Transmit Interrupt Request */
-#define MDMA1_0_IRQ 0x00020000 /* MemDMA1 Stream 0 Interrupt Request */
-#define MDMA1_1_IRQ 0x00040000 /* MemDMA1 Stream 1 Interrupt Request */
-#define MXVR_STAT_IRQ 0x00080000 /* MXVR Status Interrupt Request */
-#define MXVR_CM_IRQ 0x00100000 /* MXVR Control Message Interrupt Request */
-#define MXVR_AP_IRQ 0x00200000 /* MXVR Asynchronous Packet Interrupt */
-
-/* the following are for backwards compatibility */
-#define MDMA0_IRQ MDMA1_0_IRQ
-#define MDMA1_IRQ MDMA1_1_IRQ
-
-#ifdef _MISRA_RULES
-#define _MF15 0xFu
-#define _MF7 7u
-#else
-#define _MF15 0xF
-#define _MF7 7
-#endif /* _MISRA_RULES */
-
-/* SIC_IMASKx Masks */
-#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
-#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
-#ifdef _MISRA_RULES
-#define SIC_MASK(x) (1 << ((x)&0x1Fu)) /* Mask Peripheral #x interrupt */
-#define SIC_UNMASK(x) (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu))) /* Unmask Peripheral #x interrupt */
-#else
-#define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
-#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
-#endif /* _MISRA_RULES */
-
-/* SIC_IWRx Masks */
-#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
-#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
-#ifdef _MISRA_RULES
-#define IWR_ENABLE(x) (1 << ((x)&0x1Fu)) /* Wakeup Enable Peripheral #x */
-#define IWR_DISABLE(x) (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu))) /* Wakeup Disable Peripheral #x */
-#else
-#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
-#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
-#endif /* _MISRA_RULES */
-
-/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */
-/* PPI_CONTROL Masks */
-#define PORT_EN 0x0001 /* PPI Port Enable */
-#define PORT_DIR 0x0002 /* PPI Port Direction */
-#define XFR_TYPE 0x000C /* PPI Transfer Type */
-#define PORT_CFG 0x0030 /* PPI Port Configuration */
-#define FLD_SEL 0x0040 /* PPI Active Field Select */
-#define PACK_EN 0x0080 /* PPI Packing Mode */
-/* previous versions of defBF539.h erroneously included DMA32 (PPI 32-bit DMA Enable) */
-#define SKIP_EN 0x0200 /* PPI Skip Element Enable */
-#define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */
-#define DLENGTH 0x3800 /* PPI Data Length */
-#define DLEN_8 0x0 /* PPI Data Length mask for DLEN=8 */
-#define DLEN_10 0x0800 /* Data Length = 10 Bits */
-#define DLEN_11 0x1000 /* Data Length = 11 Bits */
-#define DLEN_12 0x1800 /* Data Length = 12 Bits */
-#define DLEN_13 0x2000 /* Data Length = 13 Bits */
-#define DLEN_14 0x2800 /* Data Length = 14 Bits */
-#define DLEN_15 0x3000 /* Data Length = 15 Bits */
-#define DLEN_16 0x3800 /* Data Length = 16 Bits */
-#ifdef _MISRA_RULES
-#define DLEN(x) ((((x)-9u) & 0x07u) << 11) /* PPI Data Length (only works for x=10-->x=16) */
-#else
-#define DLEN(x) ((((x)-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */
-#endif /* _MISRA_RULES */
-#define POL 0xC000 /* PPI Signal Polarities */
-#define POLC 0x4000 /* PPI Clock Polarity */
-#define POLS 0x8000 /* PPI Frame Sync Polarity */
-
-
-/* PPI_STATUS Masks */
-#define FLD 0x0400 /* Field Indicator */
-#define FT_ERR 0x0800 /* Frame Track Error */
-#define OVR 0x1000 /* FIFO Overflow Error */
-#define UNDR 0x2000 /* FIFO Underrun Error */
-#define ERR_DET 0x4000 /* Error Detected Indicator */
-#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */
-
-
-/* ********** DMA CONTROLLER MASKS ***********************/
-
-/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
-
-#define CTYPE 0x0040 /* DMA Channel Type Indicator */
-#define CTYPE_P 0x6 /* DMA Channel Type Indicator BIT POSITION */
-#define PCAP8 0x0080 /* DMA 8-bit Operation Indicator */
-#define PCAP16 0x0100 /* DMA 16-bit Operation Indicator */
-#define PCAP32 0x0200 /* DMA 32-bit Operation Indicator */
-#define PCAPWR 0x0400 /* DMA Write Operation Indicator */
-#define PCAPRD 0x0800 /* DMA Read Operation Indicator */
-#define PMAP 0xF000 /* DMA Peripheral Map Field */
-
-/* PMAP Encodings For DMA Controller 0 */
-#define PMAP_PPI 0x0000 /* PMAP PPI Port DMA */
-#define PMAP_SPORT0RX 0x1000 /* PMAP SPORT0 Receive DMA */
-#define PMAP_SPORT0TX 0x2000 /* PMAP SPORT0 Transmit DMA */
-#define PMAP_SPORT1RX 0x3000 /* PMAP SPORT1 Receive DMA */
-#define PMAP_SPORT1TX 0x4000 /* PMAP SPORT1 Transmit DMA */
-#define PMAP_SPI0 0x5000 /* PMAP SPI DMA */
-#define PMAP_UART0RX 0x6000 /* PMAP UART Receive DMA */
-#define PMAP_UART0TX 0x7000 /* PMAP UART Transmit DMA */
-
-/* PMAP Encodings For DMA Controller 1 */
-#define PMAP_SPORT2RX 0x0000 /* PMAP SPORT2 Receive DMA */
-#define PMAP_SPORT2TX 0x1000 /* PMAP SPORT2 Transmit DMA */
-#define PMAP_SPORT3RX 0x2000 /* PMAP SPORT3 Receive DMA */
-#define PMAP_SPORT3TX 0x3000 /* PMAP SPORT3 Transmit DMA */
-#define PMAP_SPI1 0x6000 /* PMAP SPI1 DMA */
-#define PMAP_SPI2 0x7000 /* PMAP SPI2 DMA */
-#define PMAP_UART1RX 0x8000 /* PMAP UART1 Receive DMA */
-#define PMAP_UART1TX 0x9000 /* PMAP UART1 Transmit DMA */
-#define PMAP_UART2RX 0xA000 /* PMAP UART2 Receive DMA */
-#define PMAP_UART2TX 0xB000 /* PMAP UART2 Transmit DMA */
-
-
-/* ************* GENERAL PURPOSE TIMER MASKS ******************** */
-/* PWM Timer bit definitions */
-/* TIMER_ENABLE Register */
-#define TIMEN0 0x0001 /* Enable Timer 0 */
-#define TIMEN1 0x0002 /* Enable Timer 1 */
-#define TIMEN2 0x0004 /* Enable Timer 2 */
-
-#define TIMEN0_P 0x00
-#define TIMEN1_P 0x01
-#define TIMEN2_P 0x02
-
-/* TIMER_DISABLE Register */
-#define TIMDIS0 0x0001 /* Disable Timer 0 */
-#define TIMDIS1 0x0002 /* Disable Timer 1 */
-#define TIMDIS2 0x0004 /* Disable Timer 2 */
-
-#define TIMDIS0_P 0x00
-#define TIMDIS1_P 0x01
-#define TIMDIS2_P 0x02
-
-/* TIMER_STATUS Register */
-#define TIMIL0 0x0001 /* Timer 0 Interrupt */
-#define TIMIL1 0x0002 /* Timer 1 Interrupt */
-#define TIMIL2 0x0004 /* Timer 2 Interrupt */
-#define TOVF_ERR0 0x0010 /* Timer 0 Counter Overflow */
-#define TOVF_ERR1 0x0020 /* Timer 1 Counter Overflow */
-#define TOVF_ERR2 0x0040 /* Timer 2 Counter Overflow */
-#define TRUN0 0x1000 /* Timer 0 Slave Enable Status */
-#define TRUN1 0x2000 /* Timer 1 Slave Enable Status */
-#define TRUN2 0x4000 /* Timer 2 Slave Enable Status */
-
-#define TIMIL0_P 0x00
-#define TIMIL1_P 0x01
-#define TIMIL2_P 0x02
-#define TOVF_ERR0_P 0x04
-#define TOVF_ERR1_P 0x05
-#define TOVF_ERR2_P 0x06
-#define TRUN0_P 0x0C
-#define TRUN1_P 0x0D
-#define TRUN2_P 0x0E
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define TOVL_ERR0 TOVF_ERR0
-#define TOVL_ERR1 TOVF_ERR1
-#define TOVL_ERR2 TOVF_ERR2
-#define TOVL_ERR0_P TOVF_ERR0_P
-#define TOVL_ERR1_P TOVF_ERR1_P
-#define TOVL_ERR2_P TOVF_ERR2_P
-
-/* TIMERx_CONFIG Registers */
-#define PWM_OUT 0x0001
-#define WDTH_CAP 0x0002
-#define EXT_CLK 0x0003
-#define PULSE_HI 0x0004
-#define PERIOD_CNT 0x0008
-#define IRQ_ENA 0x0010
-#define TIN_SEL 0x0020
-#define OUT_DIS 0x0040
-#define CLK_SEL 0x0080
-#define TOGGLE_HI 0x0100
-#define EMU_RUN 0x0200
-#ifdef _MISRA_RULES
-#define ERR_TYP(x) (((x) & 0x03u) << 14)
-#else
-#define ERR_TYP(x) (((x) & 0x03) << 14)
-#endif /* _MISRA_RULES */
-
-#define TMODE_P0 0x00
-#define TMODE_P1 0x01
-#define PULSE_HI_P 0x02
-#define PERIOD_CNT_P 0x03
-#define IRQ_ENA_P 0x04
-#define TIN_SEL_P 0x05
-#define OUT_DIS_P 0x06
-#define CLK_SEL_P 0x07
-#define TOGGLE_HI_P 0x08
-#define EMU_RUN_P 0x09
-#define ERR_TYP_P0 0x0E
-#define ERR_TYP_P1 0x0F
-
-/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */
-/* EBIU_AMGCTL Masks */
-#define AMCKEN 0x0001 /* Enable CLKOUT */
-#define AMBEN_NONE 0x0000 /* All Banks Disabled */
-#define AMBEN_B0 0x0002 /* Enable Asynchronous Memory Bank 0 only */
-#define AMBEN_B0_B1 0x0004 /* Enable Asynchronous Memory Banks 0 & 1 only */
-#define AMBEN_B0_B1_B2 0x0006 /* Enable Asynchronous Memory Banks 0, 1, and 2 */
-#define AMBEN_ALL 0x0008 /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */
-#define CDPRIO 0x0100 /* DMA has priority over core for external accesses */
-
-/* EBIU_AMGCTL Bit Positions */
-#define AMCKEN_P 0x0000 /* Enable CLKOUT */
-#define AMBEN_P0 0x0001 /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */
-#define AMBEN_P1 0x0002 /* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 enabled */
-#define AMBEN_P2 0x0003 /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */
-
-/* EBIU_AMBCTL0 Masks */
-#define B0RDYEN 0x00000001 /* Bank 0 RDY Enable, 0=disable, 1=enable */
-#define B0RDYPOL 0x00000002 /* Bank 0 RDY Active high, 0=active low, 1=active high */
-#define B0TT_1 0x00000004 /* Bank 0 Transition Time from Read to Write = 1 cycle */
-#define B0TT_2 0x00000008 /* Bank 0 Transition Time from Read to Write = 2 cycles */
-#define B0TT_3 0x0000000C /* Bank 0 Transition Time from Read to Write = 3 cycles */
-#define B0TT_4 0x00000000 /* Bank 0 Transition Time from Read to Write = 4 cycles */
-#define B0ST_1 0x00000010 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */
-#define B0ST_2 0x00000020 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */
-#define B0ST_3 0x00000030 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */
-#define B0ST_4 0x00000000 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */
-#define B0HT_1 0x00000040 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */
-#define B0HT_2 0x00000080 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */
-#define B0HT_3 0x000000C0 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */
-#define B0HT_0 0x00000000 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */
-#define B0RAT_1 0x00000100 /* Bank 0 Read Access Time = 1 cycle */
-#define B0RAT_2 0x00000200 /* Bank 0 Read Access Time = 2 cycles */
-#define B0RAT_3 0x00000300 /* Bank 0 Read Access Time = 3 cycles */
-#define B0RAT_4 0x00000400 /* Bank 0 Read Access Time = 4 cycles */
-#define B0RAT_5 0x00000500 /* Bank 0 Read Access Time = 5 cycles */
-#define B0RAT_6 0x00000600 /* Bank 0 Read Access Time = 6 cycles */
-#define B0RAT_7 0x00000700 /* Bank 0 Read Access Time = 7 cycles */
-#define B0RAT_8 0x00000800 /* Bank 0 Read Access Time = 8 cycles */
-#define B0RAT_9 0x00000900 /* Bank 0 Read Access Time = 9 cycles */
-#define B0RAT_10 0x00000A00 /* Bank 0 Read Access Time = 10 cycles */
-#define B0RAT_11 0x00000B00 /* Bank 0 Read Access Time = 11 cycles */
-#define B0RAT_12 0x00000C00 /* Bank 0 Read Access Time = 12 cycles */
-#define B0RAT_13 0x00000D00 /* Bank 0 Read Access Time = 13 cycles */
-#define B0RAT_14 0x00000E00 /* Bank 0 Read Access Time = 14 cycles */
-#define B0RAT_15 0x00000F00 /* Bank 0 Read Access Time = 15 cycles */
-#define B0WAT_1 0x00001000 /* Bank 0 Write Access Time = 1 cycle */
-#define B0WAT_2 0x00002000 /* Bank 0 Write Access Time = 2 cycles */
-#define B0WAT_3 0x00003000 /* Bank 0 Write Access Time = 3 cycles */
-#define B0WAT_4 0x00004000 /* Bank 0 Write Access Time = 4 cycles */
-#define B0WAT_5 0x00005000 /* Bank 0 Write Access Time = 5 cycles */
-#define B0WAT_6 0x00006000 /* Bank 0 Write Access Time = 6 cycles */
-#define B0WAT_7 0x00007000 /* Bank 0 Write Access Time = 7 cycles */
-#define B0WAT_8 0x00008000 /* Bank 0 Write Access Time = 8 cycles */
-#define B0WAT_9 0x00009000 /* Bank 0 Write Access Time = 9 cycles */
-#define B0WAT_10 0x0000A000 /* Bank 0 Write Access Time = 10 cycles */
-#define B0WAT_11 0x0000B000 /* Bank 0 Write Access Time = 11 cycles */
-#define B0WAT_12 0x0000C000 /* Bank 0 Write Access Time = 12 cycles */
-#define B0WAT_13 0x0000D000 /* Bank 0 Write Access Time = 13 cycles */
-#define B0WAT_14 0x0000E000 /* Bank 0 Write Access Time = 14 cycles */
-#define B0WAT_15 0x0000F000 /* Bank 0 Write Access Time = 15 cycles */
-#define B1RDYEN 0x00010000 /* Bank 1 RDY enable, 0=disable, 1=enable */
-#define B1RDYPOL 0x00020000 /* Bank 1 RDY Active high, 0=active low, 1=active high */
-#define B1TT_1 0x00040000 /* Bank 1 Transition Time from Read to Write = 1 cycle */
-#define B1TT_2 0x00080000 /* Bank 1 Transition Time from Read to Write = 2 cycles */
-#define B1TT_3 0x000C0000 /* Bank 1 Transition Time from Read to Write = 3 cycles */
-#define B1TT_4 0x00000000 /* Bank 1 Transition Time from Read to Write = 4 cycles */
-#define B1ST_1 0x00100000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B1ST_2 0x00200000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B1ST_3 0x00300000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B1ST_4 0x00000000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B1HT_1 0x00400000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B1HT_2 0x00800000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B1HT_3 0x00C00000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B1HT_0 0x00000000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B1RAT_1 0x01000000 /* Bank 1 Read Access Time = 1 cycle */
-#define B1RAT_2 0x02000000 /* Bank 1 Read Access Time = 2 cycles */
-#define B1RAT_3 0x03000000 /* Bank 1 Read Access Time = 3 cycles */
-#define B1RAT_4 0x04000000 /* Bank 1 Read Access Time = 4 cycles */
-#define B1RAT_5 0x05000000 /* Bank 1 Read Access Time = 5 cycles */
-#define B1RAT_6 0x06000000 /* Bank 1 Read Access Time = 6 cycles */
-#define B1RAT_7 0x07000000 /* Bank 1 Read Access Time = 7 cycles */
-#define B1RAT_8 0x08000000 /* Bank 1 Read Access Time = 8 cycles */
-#define B1RAT_9 0x09000000 /* Bank 1 Read Access Time = 9 cycles */
-#define B1RAT_10 0x0A000000 /* Bank 1 Read Access Time = 10 cycles */
-#define B1RAT_11 0x0B000000 /* Bank 1 Read Access Time = 11 cycles */
-#define B1RAT_12 0x0C000000 /* Bank 1 Read Access Time = 12 cycles */
-#define B1RAT_13 0x0D000000 /* Bank 1 Read Access Time = 13 cycles */
-#define B1RAT_14 0x0E000000 /* Bank 1 Read Access Time = 14 cycles */
-#define B1RAT_15 0x0F000000 /* Bank 1 Read Access Time = 15 cycles */
-#define B1WAT_1 0x10000000 /* Bank 1 Write Access Time = 1 cycle */
-#define B1WAT_2 0x20000000 /* Bank 1 Write Access Time = 2 cycles */
-#define B1WAT_3 0x30000000 /* Bank 1 Write Access Time = 3 cycles */
-#define B1WAT_4 0x40000000 /* Bank 1 Write Access Time = 4 cycles */
-#define B1WAT_5 0x50000000 /* Bank 1 Write Access Time = 5 cycles */
-#define B1WAT_6 0x60000000 /* Bank 1 Write Access Time = 6 cycles */
-#define B1WAT_7 0x70000000 /* Bank 1 Write Access Time = 7 cycles */
-#define B1WAT_8 0x80000000 /* Bank 1 Write Access Time = 8 cycles */
-#define B1WAT_9 0x90000000 /* Bank 1 Write Access Time = 9 cycles */
-#define B1WAT_10 0xA0000000 /* Bank 1 Write Access Time = 10 cycles */
-#define B1WAT_11 0xB0000000 /* Bank 1 Write Access Time = 11 cycles */
-#define B1WAT_12 0xC0000000 /* Bank 1 Write Access Time = 12 cycles */
-#define B1WAT_13 0xD0000000 /* Bank 1 Write Access Time = 13 cycles */
-#define B1WAT_14 0xE0000000 /* Bank 1 Write Access Time = 14 cycles */
-#define B1WAT_15 0xF0000000 /* Bank 1 Write Access Time = 15 cycles */
-
-/* EBIU_AMBCTL1 Masks */
-#define B2RDYEN 0x00000001 /* Bank 2 RDY Enable, 0=disable, 1=enable */
-#define B2RDYPOL 0x00000002 /* Bank 2 RDY Active high, 0=active low, 1=active high */
-#define B2TT_1 0x00000004 /* Bank 2 Transition Time from Read to Write = 1 cycle */
-#define B2TT_2 0x00000008 /* Bank 2 Transition Time from Read to Write = 2 cycles */
-#define B2TT_3 0x0000000C /* Bank 2 Transition Time from Read to Write = 3 cycles */
-#define B2TT_4 0x00000000 /* Bank 2 Transition Time from Read to Write = 4 cycles */
-#define B2ST_1 0x00000010 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B2ST_2 0x00000020 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B2ST_3 0x00000030 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B2ST_4 0x00000000 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B2HT_1 0x00000040 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B2HT_2 0x00000080 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B2HT_3 0x000000C0 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B2HT_0 0x00000000 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B2RAT_1 0x00000100 /* Bank 2 Read Access Time = 1 cycle */
-#define B2RAT_2 0x00000200 /* Bank 2 Read Access Time = 2 cycles */
-#define B2RAT_3 0x00000300 /* Bank 2 Read Access Time = 3 cycles */
-#define B2RAT_4 0x00000400 /* Bank 2 Read Access Time = 4 cycles */
-#define B2RAT_5 0x00000500 /* Bank 2 Read Access Time = 5 cycles */
-#define B2RAT_6 0x00000600 /* Bank 2 Read Access Time = 6 cycles */
-#define B2RAT_7 0x00000700 /* Bank 2 Read Access Time = 7 cycles */
-#define B2RAT_8 0x00000800 /* Bank 2 Read Access Time = 8 cycles */
-#define B2RAT_9 0x00000900 /* Bank 2 Read Access Time = 9 cycles */
-#define B2RAT_10 0x00000A00 /* Bank 2 Read Access Time = 10 cycles */
-#define B2RAT_11 0x00000B00 /* Bank 2 Read Access Time = 11 cycles */
-#define B2RAT_12 0x00000C00 /* Bank 2 Read Access Time = 12 cycles */
-#define B2RAT_13 0x00000D00 /* Bank 2 Read Access Time = 13 cycles */
-#define B2RAT_14 0x00000E00 /* Bank 2 Read Access Time = 14 cycles */
-#define B2RAT_15 0x00000F00 /* Bank 2 Read Access Time = 15 cycles */
-#define B2WAT_1 0x00001000 /* Bank 2 Write Access Time = 1 cycle */
-#define B2WAT_2 0x00002000 /* Bank 2 Write Access Time = 2 cycles */
-#define B2WAT_3 0x00003000 /* Bank 2 Write Access Time = 3 cycles */
-#define B2WAT_4 0x00004000 /* Bank 2 Write Access Time = 4 cycles */
-#define B2WAT_5 0x00005000 /* Bank 2 Write Access Time = 5 cycles */
-#define B2WAT_6 0x00006000 /* Bank 2 Write Access Time = 6 cycles */
-#define B2WAT_7 0x00007000 /* Bank 2 Write Access Time = 7 cycles */
-#define B2WAT_8 0x00008000 /* Bank 2 Write Access Time = 8 cycles */
-#define B2WAT_9 0x00009000 /* Bank 2 Write Access Time = 9 cycles */
-#define B2WAT_10 0x0000A000 /* Bank 2 Write Access Time = 10 cycles */
-#define B2WAT_11 0x0000B000 /* Bank 2 Write Access Time = 11 cycles */
-#define B2WAT_12 0x0000C000 /* Bank 2 Write Access Time = 12 cycles */
-#define B2WAT_13 0x0000D000 /* Bank 2 Write Access Time = 13 cycles */
-#define B2WAT_14 0x0000E000 /* Bank 2 Write Access Time = 14 cycles */
-#define B2WAT_15 0x0000F000 /* Bank 2 Write Access Time = 15 cycles */
-#define B3RDYEN 0x00010000 /* Bank 3 RDY enable, 0=disable, 1=enable */
-#define B3RDYPOL 0x00020000 /* Bank 3 RDY Active high, 0=active low, 1=active high */
-#define B3TT_1 0x00040000 /* Bank 3 Transition Time from Read to Write = 1 cycle */
-#define B3TT_2 0x00080000 /* Bank 3 Transition Time from Read to Write = 2 cycles */
-#define B3TT_3 0x000C0000 /* Bank 3 Transition Time from Read to Write = 3 cycles */
-#define B3TT_4 0x00000000 /* Bank 3 Transition Time from Read to Write = 4 cycles */
-#define B3ST_1 0x00100000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B3ST_2 0x00200000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B3ST_3 0x00300000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B3ST_4 0x00000000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B3HT_1 0x00400000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B3HT_2 0x00800000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B3HT_3 0x00C00000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B3HT_0 0x00000000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B3RAT_1 0x01000000 /* Bank 3 Read Access Time = 1 cycle */
-#define B3RAT_2 0x02000000 /* Bank 3 Read Access Time = 2 cycles */
-#define B3RAT_3 0x03000000 /* Bank 3 Read Access Time = 3 cycles */
-#define B3RAT_4 0x04000000 /* Bank 3 Read Access Time = 4 cycles */
-#define B3RAT_5 0x05000000 /* Bank 3 Read Access Time = 5 cycles */
-#define B3RAT_6 0x06000000 /* Bank 3 Read Access Time = 6 cycles */
-#define B3RAT_7 0x07000000 /* Bank 3 Read Access Time = 7 cycles */
-#define B3RAT_8 0x08000000 /* Bank 3 Read Access Time = 8 cycles */
-#define B3RAT_9 0x09000000 /* Bank 3 Read Access Time = 9 cycles */
-#define B3RAT_10 0x0A000000 /* Bank 3 Read Access Time = 10 cycles */
-#define B3RAT_11 0x0B000000 /* Bank 3 Read Access Time = 11 cycles */
-#define B3RAT_12 0x0C000000 /* Bank 3 Read Access Time = 12 cycles */
-#define B3RAT_13 0x0D000000 /* Bank 3 Read Access Time = 13 cycles */
-#define B3RAT_14 0x0E000000 /* Bank 3 Read Access Time = 14 cycles */
-#define B3RAT_15 0x0F000000 /* Bank 3 Read Access Time = 15 cycles */
-#define B3WAT_1 0x10000000 /* Bank 3 Write Access Time = 1 cycle */
-#define B3WAT_2 0x20000000 /* Bank 3 Write Access Time = 2 cycles */
-#define B3WAT_3 0x30000000 /* Bank 3 Write Access Time = 3 cycles */
-#define B3WAT_4 0x40000000 /* Bank 3 Write Access Time = 4 cycles */
-#define B3WAT_5 0x50000000 /* Bank 3 Write Access Time = 5 cycles */
-#define B3WAT_6 0x60000000 /* Bank 3 Write Access Time = 6 cycles */
-#define B3WAT_7 0x70000000 /* Bank 3 Write Access Time = 7 cycles */
-#define B3WAT_8 0x80000000 /* Bank 3 Write Access Time = 8 cycles */
-#define B3WAT_9 0x90000000 /* Bank 3 Write Access Time = 9 cycles */
-#define B3WAT_10 0xA0000000 /* Bank 3 Write Access Time = 10 cycles */
-#define B3WAT_11 0xB0000000 /* Bank 3 Write Access Time = 11 cycles */
-#define B3WAT_12 0xC0000000 /* Bank 3 Write Access Time = 12 cycles */
-#define B3WAT_13 0xD0000000 /* Bank 3 Write Access Time = 13 cycles */
-#define B3WAT_14 0xE0000000 /* Bank 3 Write Access Time = 14 cycles */
-#define B3WAT_15 0xF0000000 /* Bank 3 Write Access Time = 15 cycles */
-
-/* ********************** SDRAM CONTROLLER MASKS *************************** */
-/* EBIU_SDGCTL Masks */
-#define SCTLE 0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */
-#define CL_2 0x00000008 /* SDRAM CAS latency = 2 cycles */
-#define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */
-#define PFE 0x00000010 /* Enable SDRAM prefetch */
-#define PFP 0x00000020 /* Prefetch has priority over AMC requests */
-#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
-#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
-#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
-#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
-#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
-#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
-#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
-#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
-#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
-#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
-#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
-#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
-#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
-#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
-#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
-#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
-#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
-#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
-#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
-#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
-#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
-#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
-#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
-#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
-#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
-#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
-#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
-#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
-#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
-#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
-#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
-#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
-#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
-#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
-#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
-#define PUPSD 0x00200000 /*Power-up start delay */
-#define PSM 0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */
-#define PSS 0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */
-#define SRFS 0x01000000 /* Start SDRAM self-refresh mode */
-#define EBUFE 0x02000000 /* Enable external buffering timing */
-#define FBBRW 0x04000000 /* Fast back-to-back read write enable */
-#define EMREN 0x10000000 /* Extended mode register enable */
-#define TCSR 0x20000000 /* Temp compensated self refresh value 85 deg C */
-#define CDDBG 0x40000000 /* Tristate SDRAM controls during bus grant */
-
-/* EBIU_SDBCTL Masks */
-#define EBE 0x00000001 /* Enable SDRAM external bank */
-#define EBSZ_16 0x00000000 /* SDRAM external bank size = 16MB */
-#define EBSZ_32 0x00000002 /* SDRAM external bank size = 32MB */
-#define EBSZ_64 0x00000004 /* SDRAM external bank size = 64MB */
-#define EBSZ_128 0x00000006 /* SDRAM external bank size = 128MB */
-#define EBSZ_256 0x00000008 /* SDRAM External Bank Size = 256MB */
-#define EBSZ_512 0x0000000A /* SDRAM External Bank Size = 512MB */
-#define EBCAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */
-#define EBCAW_9 0x00000010 /* SDRAM external bank column address width = 9 bits */
-#define EBCAW_10 0x00000020 /* SDRAM external bank column address width = 9 bits */
-#define EBCAW_11 0x00000030 /* SDRAM external bank column address width = 9 bits */
-
-/* EBIU_SDSTAT Masks */
-#define SDCI 0x00000001 /* SDRAM controller is idle */
-#define SDSRA 0x00000002 /* SDRAM SDRAM self refresh is active */
-#define SDPUA 0x00000004 /* SDRAM power up active */
-#define SDRS 0x00000008 /* SDRAM is in reset state */
-#define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */
-#define BGSTAT 0x00000020 /* Bus granted */
-
-#endif
+++ /dev/null
-/*
- * Copyright 2008-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF539_H
-#define _DEF_BF539_H
-
-#include "defBF538.h"
-
-/* Media Transceiver (MXVR) (0xFFC02700 - 0xFFC028FF) */
-
-#define MXVR_CONFIG 0xFFC02700 /* MXVR Configuration Register */
-#define MXVR_PLL_CTL_0 0xFFC02704 /* MXVR Phase Lock Loop Control Register 0 */
-
-#define MXVR_STATE_0 0xFFC02708 /* MXVR State Register 0 */
-#define MXVR_STATE_1 0xFFC0270C /* MXVR State Register 1 */
-
-#define MXVR_INT_STAT_0 0xFFC02710 /* MXVR Interrupt Status Register 0 */
-#define MXVR_INT_STAT_1 0xFFC02714 /* MXVR Interrupt Status Register 1 */
-
-#define MXVR_INT_EN_0 0xFFC02718 /* MXVR Interrupt Enable Register 0 */
-#define MXVR_INT_EN_1 0xFFC0271C /* MXVR Interrupt Enable Register 1 */
-
-#define MXVR_POSITION 0xFFC02720 /* MXVR Node Position Register */
-#define MXVR_MAX_POSITION 0xFFC02724 /* MXVR Maximum Node Position Register */
-
-#define MXVR_DELAY 0xFFC02728 /* MXVR Node Frame Delay Register */
-#define MXVR_MAX_DELAY 0xFFC0272C /* MXVR Maximum Node Frame Delay Register */
-
-#define MXVR_LADDR 0xFFC02730 /* MXVR Logical Address Register */
-#define MXVR_GADDR 0xFFC02734 /* MXVR Group Address Register */
-#define MXVR_AADDR 0xFFC02738 /* MXVR Alternate Address Register */
-
-#define MXVR_ALLOC_0 0xFFC0273C /* MXVR Allocation Table Register 0 */
-#define MXVR_ALLOC_1 0xFFC02740 /* MXVR Allocation Table Register 1 */
-#define MXVR_ALLOC_2 0xFFC02744 /* MXVR Allocation Table Register 2 */
-#define MXVR_ALLOC_3 0xFFC02748 /* MXVR Allocation Table Register 3 */
-#define MXVR_ALLOC_4 0xFFC0274C /* MXVR Allocation Table Register 4 */
-#define MXVR_ALLOC_5 0xFFC02750 /* MXVR Allocation Table Register 5 */
-#define MXVR_ALLOC_6 0xFFC02754 /* MXVR Allocation Table Register 6 */
-#define MXVR_ALLOC_7 0xFFC02758 /* MXVR Allocation Table Register 7 */
-#define MXVR_ALLOC_8 0xFFC0275C /* MXVR Allocation Table Register 8 */
-#define MXVR_ALLOC_9 0xFFC02760 /* MXVR Allocation Table Register 9 */
-#define MXVR_ALLOC_10 0xFFC02764 /* MXVR Allocation Table Register 10 */
-#define MXVR_ALLOC_11 0xFFC02768 /* MXVR Allocation Table Register 11 */
-#define MXVR_ALLOC_12 0xFFC0276C /* MXVR Allocation Table Register 12 */
-#define MXVR_ALLOC_13 0xFFC02770 /* MXVR Allocation Table Register 13 */
-#define MXVR_ALLOC_14 0xFFC02774 /* MXVR Allocation Table Register 14 */
-
-#define MXVR_SYNC_LCHAN_0 0xFFC02778 /* MXVR Sync Data Logical Channel Assign Register 0 */
-#define MXVR_SYNC_LCHAN_1 0xFFC0277C /* MXVR Sync Data Logical Channel Assign Register 1 */
-#define MXVR_SYNC_LCHAN_2 0xFFC02780 /* MXVR Sync Data Logical Channel Assign Register 2 */
-#define MXVR_SYNC_LCHAN_3 0xFFC02784 /* MXVR Sync Data Logical Channel Assign Register 3 */
-#define MXVR_SYNC_LCHAN_4 0xFFC02788 /* MXVR Sync Data Logical Channel Assign Register 4 */
-#define MXVR_SYNC_LCHAN_5 0xFFC0278C /* MXVR Sync Data Logical Channel Assign Register 5 */
-#define MXVR_SYNC_LCHAN_6 0xFFC02790 /* MXVR Sync Data Logical Channel Assign Register 6 */
-#define MXVR_SYNC_LCHAN_7 0xFFC02794 /* MXVR Sync Data Logical Channel Assign Register 7 */
-
-#define MXVR_DMA0_CONFIG 0xFFC02798 /* MXVR Sync Data DMA0 Config Register */
-#define MXVR_DMA0_START_ADDR 0xFFC0279C /* MXVR Sync Data DMA0 Start Address Register */
-#define MXVR_DMA0_COUNT 0xFFC027A0 /* MXVR Sync Data DMA0 Loop Count Register */
-#define MXVR_DMA0_CURR_ADDR 0xFFC027A4 /* MXVR Sync Data DMA0 Current Address Register */
-#define MXVR_DMA0_CURR_COUNT 0xFFC027A8 /* MXVR Sync Data DMA0 Current Loop Count Register */
-
-#define MXVR_DMA1_CONFIG 0xFFC027AC /* MXVR Sync Data DMA1 Config Register */
-#define MXVR_DMA1_START_ADDR 0xFFC027B0 /* MXVR Sync Data DMA1 Start Address Register */
-#define MXVR_DMA1_COUNT 0xFFC027B4 /* MXVR Sync Data DMA1 Loop Count Register */
-#define MXVR_DMA1_CURR_ADDR 0xFFC027B8 /* MXVR Sync Data DMA1 Current Address Register */
-#define MXVR_DMA1_CURR_COUNT 0xFFC027BC /* MXVR Sync Data DMA1 Current Loop Count Register */
-
-#define MXVR_DMA2_CONFIG 0xFFC027C0 /* MXVR Sync Data DMA2 Config Register */
-#define MXVR_DMA2_START_ADDR 0xFFC027C4 /* MXVR Sync Data DMA2 Start Address Register */
-#define MXVR_DMA2_COUNT 0xFFC027C8 /* MXVR Sync Data DMA2 Loop Count Register */
-#define MXVR_DMA2_CURR_ADDR 0xFFC027CC /* MXVR Sync Data DMA2 Current Address Register */
-#define MXVR_DMA2_CURR_COUNT 0xFFC027D0 /* MXVR Sync Data DMA2 Current Loop Count Register */
-
-#define MXVR_DMA3_CONFIG 0xFFC027D4 /* MXVR Sync Data DMA3 Config Register */
-#define MXVR_DMA3_START_ADDR 0xFFC027D8 /* MXVR Sync Data DMA3 Start Address Register */
-#define MXVR_DMA3_COUNT 0xFFC027DC /* MXVR Sync Data DMA3 Loop Count Register */
-#define MXVR_DMA3_CURR_ADDR 0xFFC027E0 /* MXVR Sync Data DMA3 Current Address Register */
-#define MXVR_DMA3_CURR_COUNT 0xFFC027E4 /* MXVR Sync Data DMA3 Current Loop Count Register */
-
-#define MXVR_DMA4_CONFIG 0xFFC027E8 /* MXVR Sync Data DMA4 Config Register */
-#define MXVR_DMA4_START_ADDR 0xFFC027EC /* MXVR Sync Data DMA4 Start Address Register */
-#define MXVR_DMA4_COUNT 0xFFC027F0 /* MXVR Sync Data DMA4 Loop Count Register */
-#define MXVR_DMA4_CURR_ADDR 0xFFC027F4 /* MXVR Sync Data DMA4 Current Address Register */
-#define MXVR_DMA4_CURR_COUNT 0xFFC027F8 /* MXVR Sync Data DMA4 Current Loop Count Register */
-
-#define MXVR_DMA5_CONFIG 0xFFC027FC /* MXVR Sync Data DMA5 Config Register */
-#define MXVR_DMA5_START_ADDR 0xFFC02800 /* MXVR Sync Data DMA5 Start Address Register */
-#define MXVR_DMA5_COUNT 0xFFC02804 /* MXVR Sync Data DMA5 Loop Count Register */
-#define MXVR_DMA5_CURR_ADDR 0xFFC02808 /* MXVR Sync Data DMA5 Current Address Register */
-#define MXVR_DMA5_CURR_COUNT 0xFFC0280C /* MXVR Sync Data DMA5 Current Loop Count Register */
-
-#define MXVR_DMA6_CONFIG 0xFFC02810 /* MXVR Sync Data DMA6 Config Register */
-#define MXVR_DMA6_START_ADDR 0xFFC02814 /* MXVR Sync Data DMA6 Start Address Register */
-#define MXVR_DMA6_COUNT 0xFFC02818 /* MXVR Sync Data DMA6 Loop Count Register */
-#define MXVR_DMA6_CURR_ADDR 0xFFC0281C /* MXVR Sync Data DMA6 Current Address Register */
-#define MXVR_DMA6_CURR_COUNT 0xFFC02820 /* MXVR Sync Data DMA6 Current Loop Count Register */
-
-#define MXVR_DMA7_CONFIG 0xFFC02824 /* MXVR Sync Data DMA7 Config Register */
-#define MXVR_DMA7_START_ADDR 0xFFC02828 /* MXVR Sync Data DMA7 Start Address Register */
-#define MXVR_DMA7_COUNT 0xFFC0282C /* MXVR Sync Data DMA7 Loop Count Register */
-#define MXVR_DMA7_CURR_ADDR 0xFFC02830 /* MXVR Sync Data DMA7 Current Address Register */
-#define MXVR_DMA7_CURR_COUNT 0xFFC02834 /* MXVR Sync Data DMA7 Current Loop Count Register */
-
-#define MXVR_AP_CTL 0xFFC02838 /* MXVR Async Packet Control Register */
-#define MXVR_APRB_START_ADDR 0xFFC0283C /* MXVR Async Packet RX Buffer Start Addr Register */
-#define MXVR_APRB_CURR_ADDR 0xFFC02840 /* MXVR Async Packet RX Buffer Current Addr Register */
-#define MXVR_APTB_START_ADDR 0xFFC02844 /* MXVR Async Packet TX Buffer Start Addr Register */
-#define MXVR_APTB_CURR_ADDR 0xFFC02848 /* MXVR Async Packet TX Buffer Current Addr Register */
-
-#define MXVR_CM_CTL 0xFFC0284C /* MXVR Control Message Control Register */
-#define MXVR_CMRB_START_ADDR 0xFFC02850 /* MXVR Control Message RX Buffer Start Addr Register */
-#define MXVR_CMRB_CURR_ADDR 0xFFC02854 /* MXVR Control Message RX Buffer Current Address */
-#define MXVR_CMTB_START_ADDR 0xFFC02858 /* MXVR Control Message TX Buffer Start Addr Register */
-#define MXVR_CMTB_CURR_ADDR 0xFFC0285C /* MXVR Control Message TX Buffer Current Address */
-
-#define MXVR_RRDB_START_ADDR 0xFFC02860 /* MXVR Remote Read Buffer Start Addr Register */
-#define MXVR_RRDB_CURR_ADDR 0xFFC02864 /* MXVR Remote Read Buffer Current Addr Register */
-
-#define MXVR_PAT_DATA_0 0xFFC02868 /* MXVR Pattern Data Register 0 */
-#define MXVR_PAT_EN_0 0xFFC0286C /* MXVR Pattern Enable Register 0 */
-#define MXVR_PAT_DATA_1 0xFFC02870 /* MXVR Pattern Data Register 1 */
-#define MXVR_PAT_EN_1 0xFFC02874 /* MXVR Pattern Enable Register 1 */
-
-#define MXVR_FRAME_CNT_0 0xFFC02878 /* MXVR Frame Counter 0 */
-#define MXVR_FRAME_CNT_1 0xFFC0287C /* MXVR Frame Counter 1 */
-
-#define MXVR_ROUTING_0 0xFFC02880 /* MXVR Routing Table Register 0 */
-#define MXVR_ROUTING_1 0xFFC02884 /* MXVR Routing Table Register 1 */
-#define MXVR_ROUTING_2 0xFFC02888 /* MXVR Routing Table Register 2 */
-#define MXVR_ROUTING_3 0xFFC0288C /* MXVR Routing Table Register 3 */
-#define MXVR_ROUTING_4 0xFFC02890 /* MXVR Routing Table Register 4 */
-#define MXVR_ROUTING_5 0xFFC02894 /* MXVR Routing Table Register 5 */
-#define MXVR_ROUTING_6 0xFFC02898 /* MXVR Routing Table Register 6 */
-#define MXVR_ROUTING_7 0xFFC0289C /* MXVR Routing Table Register 7 */
-#define MXVR_ROUTING_8 0xFFC028A0 /* MXVR Routing Table Register 8 */
-#define MXVR_ROUTING_9 0xFFC028A4 /* MXVR Routing Table Register 9 */
-#define MXVR_ROUTING_10 0xFFC028A8 /* MXVR Routing Table Register 10 */
-#define MXVR_ROUTING_11 0xFFC028AC /* MXVR Routing Table Register 11 */
-#define MXVR_ROUTING_12 0xFFC028B0 /* MXVR Routing Table Register 12 */
-#define MXVR_ROUTING_13 0xFFC028B4 /* MXVR Routing Table Register 13 */
-#define MXVR_ROUTING_14 0xFFC028B8 /* MXVR Routing Table Register 14 */
-
-#define MXVR_PLL_CTL_1 0xFFC028BC /* MXVR Phase Lock Loop Control Register 1 */
-#define MXVR_BLOCK_CNT 0xFFC028C0 /* MXVR Block Counter */
-#define MXVR_PLL_CTL_2 0xFFC028C4 /* MXVR Phase Lock Loop Control Register 2 */
-
-#endif /* _DEF_BF539_H */
+++ /dev/null
-/* mach/dma.h - arch-specific DMA defines
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_DMA_H_
-#define _MACH_DMA_H_
-
-#define CH_PPI 0
-#define CH_SPORT0_RX 1
-#define CH_SPORT0_TX 2
-#define CH_SPORT1_RX 3
-#define CH_SPORT1_TX 4
-#define CH_SPI0 5
-#define CH_UART0_RX 6
-#define CH_UART0_TX 7
-#define CH_SPORT2_RX 8
-#define CH_SPORT2_TX 9
-#define CH_SPORT3_RX 10
-#define CH_SPORT3_TX 11
-#define CH_SPI1 14
-#define CH_SPI2 15
-#define CH_UART1_RX 16
-#define CH_UART1_TX 17
-#define CH_UART2_RX 18
-#define CH_UART2_TX 19
-
-#define CH_MEM_STREAM0_DEST 20
-#define CH_MEM_STREAM0_SRC 21
-#define CH_MEM_STREAM1_DEST 22
-#define CH_MEM_STREAM1_SRC 23
-#define CH_MEM_STREAM2_DEST 24
-#define CH_MEM_STREAM2_SRC 25
-#define CH_MEM_STREAM3_DEST 26
-#define CH_MEM_STREAM3_SRC 27
-
-#define MAX_DMA_CHANNELS 28
-
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2008-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-
-#ifndef _MACH_GPIO_H_
-#define _MACH_GPIO_H_
-
-#define MAX_BLACKFIN_GPIOS 16
-#ifdef CONFIG_GPIOLIB
-/* We only use the special logic with GPIOLIB devices */
-#define BFIN_SPECIAL_GPIO_BANKS 3
-#endif
-
-#define GPIO_PF0 0 /* PF */
-#define GPIO_PF1 1
-#define GPIO_PF2 2
-#define GPIO_PF3 3
-#define GPIO_PF4 4
-#define GPIO_PF5 5
-#define GPIO_PF6 6
-#define GPIO_PF7 7
-#define GPIO_PF8 8
-#define GPIO_PF9 9
-#define GPIO_PF10 10
-#define GPIO_PF11 11
-#define GPIO_PF12 12
-#define GPIO_PF13 13
-#define GPIO_PF14 14
-#define GPIO_PF15 15
-#define GPIO_PC0 16 /* PC */
-#define GPIO_PC1 17
-#define GPIO_PC4 20
-#define GPIO_PC5 21
-#define GPIO_PC6 22
-#define GPIO_PC7 23
-#define GPIO_PC8 24
-#define GPIO_PC9 25
-#define GPIO_PD0 32 /* PD */
-#define GPIO_PD1 33
-#define GPIO_PD2 34
-#define GPIO_PD3 35
-#define GPIO_PD4 36
-#define GPIO_PD5 37
-#define GPIO_PD6 38
-#define GPIO_PD7 39
-#define GPIO_PD8 40
-#define GPIO_PD9 41
-#define GPIO_PD10 42
-#define GPIO_PD11 43
-#define GPIO_PD12 44
-#define GPIO_PD13 45
-#define GPIO_PE0 48 /* PE */
-#define GPIO_PE1 49
-#define GPIO_PE2 50
-#define GPIO_PE3 51
-#define GPIO_PE4 52
-#define GPIO_PE5 53
-#define GPIO_PE6 54
-#define GPIO_PE7 55
-#define GPIO_PE8 56
-#define GPIO_PE9 57
-#define GPIO_PE10 58
-#define GPIO_PE11 59
-#define GPIO_PE12 60
-#define GPIO_PE13 61
-#define GPIO_PE14 62
-#define GPIO_PE15 63
-
-#define PORT_F GPIO_PF0
-#define PORT_C GPIO_PC0
-#define PORT_D GPIO_PD0
-#define PORT_E GPIO_PE0
-
-#include <mach-common/ports-c.h>
-#include <mach-common/ports-d.h>
-#include <mach-common/ports-e.h>
-#include <mach-common/ports-f.h>
-
-#endif /* _MACH_GPIO_H_ */
+++ /dev/null
-/*
- * Copyright 2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BF538_IRQ_H_
-#define _BF538_IRQ_H_
-
-#include <mach-common/irq.h>
-
-#define NR_PERI_INTS (2 * 32)
-
-#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
-#define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */
-#define IRQ_PPI_ERROR BFIN_IRQ(2) /* PPI Error */
-#define IRQ_SPORT0_ERROR BFIN_IRQ(3) /* SPORT0 Status */
-#define IRQ_SPORT1_ERROR BFIN_IRQ(4) /* SPORT1 Status */
-#define IRQ_SPI0_ERROR BFIN_IRQ(5) /* SPI0 Status */
-#define IRQ_UART0_ERROR BFIN_IRQ(6) /* UART0 Status */
-#define IRQ_RTC BFIN_IRQ(7) /* RTC */
-#define IRQ_PPI BFIN_IRQ(8) /* DMA Channel 0 (PPI) */
-#define IRQ_SPORT0_RX BFIN_IRQ(9) /* DMA 1 Channel (SPORT0 RX) */
-#define IRQ_SPORT0_TX BFIN_IRQ(10) /* DMA 2 Channel (SPORT0 TX) */
-#define IRQ_SPORT1_RX BFIN_IRQ(11) /* DMA 3 Channel (SPORT1 RX) */
-#define IRQ_SPORT1_TX BFIN_IRQ(12) /* DMA 4 Channel (SPORT1 TX) */
-#define IRQ_SPI0 BFIN_IRQ(13) /* DMA 5 Channel (SPI0) */
-#define IRQ_UART0_RX BFIN_IRQ(14) /* DMA 6 Channel (UART0 RX) */
-#define IRQ_UART0_TX BFIN_IRQ(15) /* DMA 7 Channel (UART0 TX) */
-#define IRQ_TIMER0 BFIN_IRQ(16) /* Timer 0 */
-#define IRQ_TIMER1 BFIN_IRQ(17) /* Timer 1 */
-#define IRQ_TIMER2 BFIN_IRQ(18) /* Timer 2 */
-#define IRQ_PORTF_INTA BFIN_IRQ(19) /* Port F Interrupt A */
-#define IRQ_PORTF_INTB BFIN_IRQ(20) /* Port F Interrupt B */
-#define IRQ_MEM0_DMA0 BFIN_IRQ(21) /* MDMA0 Stream 0 */
-#define IRQ_MEM0_DMA1 BFIN_IRQ(22) /* MDMA0 Stream 1 */
-#define IRQ_WATCH BFIN_IRQ(23) /* Software Watchdog Timer */
-#define IRQ_DMA1_ERROR BFIN_IRQ(24) /* DMA Error 1 (generic) */
-#define IRQ_SPORT2_ERROR BFIN_IRQ(25) /* SPORT2 Status */
-#define IRQ_SPORT3_ERROR BFIN_IRQ(26) /* SPORT3 Status */
-#define IRQ_SPI1_ERROR BFIN_IRQ(28) /* SPI1 Status */
-#define IRQ_SPI2_ERROR BFIN_IRQ(29) /* SPI2 Status */
-#define IRQ_UART1_ERROR BFIN_IRQ(30) /* UART1 Status */
-#define IRQ_UART2_ERROR BFIN_IRQ(31) /* UART2 Status */
-#define IRQ_CAN_ERROR BFIN_IRQ(32) /* CAN Status (Error) Interrupt */
-#define IRQ_SPORT2_RX BFIN_IRQ(33) /* DMA 8 Channel (SPORT2 RX) */
-#define IRQ_SPORT2_TX BFIN_IRQ(34) /* DMA 9 Channel (SPORT2 TX) */
-#define IRQ_SPORT3_RX BFIN_IRQ(35) /* DMA 10 Channel (SPORT3 RX) */
-#define IRQ_SPORT3_TX BFIN_IRQ(36) /* DMA 11 Channel (SPORT3 TX) */
-#define IRQ_SPI1 BFIN_IRQ(39) /* DMA 14 Channel (SPI1) */
-#define IRQ_SPI2 BFIN_IRQ(40) /* DMA 15 Channel (SPI2) */
-#define IRQ_UART1_RX BFIN_IRQ(41) /* DMA 16 Channel (UART1 RX) */
-#define IRQ_UART1_TX BFIN_IRQ(42) /* DMA 17 Channel (UART1 TX) */
-#define IRQ_UART2_RX BFIN_IRQ(43) /* DMA 18 Channel (UART2 RX) */
-#define IRQ_UART2_TX BFIN_IRQ(44) /* DMA 19 Channel (UART2 TX) */
-#define IRQ_TWI0 BFIN_IRQ(45) /* TWI0 */
-#define IRQ_TWI1 BFIN_IRQ(46) /* TWI1 */
-#define IRQ_CAN_RX BFIN_IRQ(47) /* CAN Receive Interrupt */
-#define IRQ_CAN_TX BFIN_IRQ(48) /* CAN Transmit Interrupt */
-#define IRQ_MEM1_DMA0 BFIN_IRQ(49) /* MDMA1 Stream 0 */
-#define IRQ_MEM1_DMA1 BFIN_IRQ(50) /* MDMA1 Stream 1 */
-
-#define SYS_IRQS BFIN_IRQ(63) /* 70 */
-
-#define IRQ_PF0 71
-#define IRQ_PF1 72
-#define IRQ_PF2 73
-#define IRQ_PF3 74
-#define IRQ_PF4 75
-#define IRQ_PF5 76
-#define IRQ_PF6 77
-#define IRQ_PF7 78
-#define IRQ_PF8 79
-#define IRQ_PF9 80
-#define IRQ_PF10 81
-#define IRQ_PF11 82
-#define IRQ_PF12 83
-#define IRQ_PF13 84
-#define IRQ_PF14 85
-#define IRQ_PF15 86
-
-#define GPIO_IRQ_BASE IRQ_PF0
-
-#define NR_MACH_IRQS (IRQ_PF15 + 1)
-
-/* IAR0 BIT FIELDS */
-#define IRQ_PLL_WAKEUP_POS 0
-#define IRQ_DMA0_ERROR_POS 4
-#define IRQ_PPI_ERROR_POS 8
-#define IRQ_SPORT0_ERROR_POS 12
-#define IRQ_SPORT1_ERROR_POS 16
-#define IRQ_SPI0_ERROR_POS 20
-#define IRQ_UART0_ERROR_POS 24
-#define IRQ_RTC_POS 28
-
-/* IAR1 BIT FIELDS */
-#define IRQ_PPI_POS 0
-#define IRQ_SPORT0_RX_POS 4
-#define IRQ_SPORT0_TX_POS 8
-#define IRQ_SPORT1_RX_POS 12
-#define IRQ_SPORT1_TX_POS 16
-#define IRQ_SPI0_POS 20
-#define IRQ_UART0_RX_POS 24
-#define IRQ_UART0_TX_POS 28
-
-/* IAR2 BIT FIELDS */
-#define IRQ_TIMER0_POS 0
-#define IRQ_TIMER1_POS 4
-#define IRQ_TIMER2_POS 8
-#define IRQ_PORTF_INTA_POS 12
-#define IRQ_PORTF_INTB_POS 16
-#define IRQ_MEM0_DMA0_POS 20
-#define IRQ_MEM0_DMA1_POS 24
-#define IRQ_WATCH_POS 28
-
-/* IAR3 BIT FIELDS */
-#define IRQ_DMA1_ERROR_POS 0
-#define IRQ_SPORT2_ERROR_POS 4
-#define IRQ_SPORT3_ERROR_POS 8
-#define IRQ_SPI1_ERROR_POS 16
-#define IRQ_SPI2_ERROR_POS 20
-#define IRQ_UART1_ERROR_POS 24
-#define IRQ_UART2_ERROR_POS 28
-
-/* IAR4 BIT FIELDS */
-#define IRQ_CAN_ERROR_POS 0
-#define IRQ_SPORT2_RX_POS 4
-#define IRQ_SPORT2_TX_POS 8
-#define IRQ_SPORT3_RX_POS 12
-#define IRQ_SPORT3_TX_POS 16
-#define IRQ_SPI1_POS 28
-
-/* IAR5 BIT FIELDS */
-#define IRQ_SPI2_POS 0
-#define IRQ_UART1_RX_POS 4
-#define IRQ_UART1_TX_POS 8
-#define IRQ_UART2_RX_POS 12
-#define IRQ_UART2_TX_POS 16
-#define IRQ_TWI0_POS 20
-#define IRQ_TWI1_POS 24
-#define IRQ_CAN_RX_POS 28
-
-/* IAR6 BIT FIELDS */
-#define IRQ_CAN_TX_POS 0
-#define IRQ_MEM1_DMA0_POS 4
-#define IRQ_MEM1_DMA1_POS 8
-
-#endif
+++ /dev/null
-/*
- * BF538 memory map
- *
- * Copyright 2004-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MACH_MEM_MAP_H__
-#define __BFIN_MACH_MEM_MAP_H__
-
-#ifndef __BFIN_MEM_MAP_H__
-# error "do not include mach/mem_map.h directly -- use asm/mem_map.h"
-#endif
-
-/* Async Memory Banks */
-#define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */
-#define ASYNC_BANK3_SIZE 0x00100000 /* 1M */
-#define ASYNC_BANK2_BASE 0x20200000 /* Async Bank 2 */
-#define ASYNC_BANK2_SIZE 0x00100000 /* 1M */
-#define ASYNC_BANK1_BASE 0x20100000 /* Async Bank 1 */
-#define ASYNC_BANK1_SIZE 0x00100000 /* 1M */
-#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
-#define ASYNC_BANK0_SIZE 0x00100000 /* 1M */
-
-/* Boot ROM Memory */
-
-#define BOOT_ROM_START 0xEF000000
-#define BOOT_ROM_LENGTH 0x400
-
-/* Level 1 Memory */
-
-#ifdef CONFIG_BFIN_ICACHE
-#define BFIN_ICACHESIZE (16*1024)
-#else
-#define BFIN_ICACHESIZE (0*1024)
-#endif
-
-/* Memory Map for ADSP-BF538/9 processors */
-
-#define L1_CODE_START 0xFFA00000
-#define L1_DATA_A_START 0xFF800000
-#define L1_DATA_B_START 0xFF900000
-
-#ifdef CONFIG_BFIN_ICACHE
-#define L1_CODE_LENGTH (0x14000 - 0x4000)
-#else
-#define L1_CODE_LENGTH 0x14000
-#endif
-
-#ifdef CONFIG_BFIN_DCACHE
-
-#ifdef CONFIG_BFIN_DCACHE_BANKA
-#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE (16*1024)
-#define BFIN_DSUPBANKS 1
-#else
-#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
-#define BFIN_DCACHESIZE (32*1024)
-#define BFIN_DSUPBANKS 2
-#endif
-
-#else
-#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH 0x8000
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE (0*1024)
-#define BFIN_DSUPBANKS 0
-#endif /*CONFIG_BFIN_DCACHE*/
-
-#endif
+++ /dev/null
-#include <mach-common/pll.h>
+++ /dev/null
-/*
- * Copyright 2008-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_PORTMUX_H_
-#define _MACH_PORTMUX_H_
-
-#define MAX_RESOURCES 64
-
-#define P_TMR2 (P_DONTCARE)
-#define P_TMR1 (P_DONTCARE)
-#define P_TMR0 (P_DONTCARE)
-#define P_TMRCLK (P_DONTCARE)
-#define P_PPI0_CLK (P_DONTCARE)
-#define P_PPI0_FS1 (P_DONTCARE)
-#define P_PPI0_FS2 (P_DONTCARE)
-
-#define P_TWI0_SCL (P_DONTCARE)
-#define P_TWI0_SDA (P_DONTCARE)
-#define P_TWI1_SCL (P_DONTCARE)
-#define P_TWI1_SDA (P_DONTCARE)
-
-#define P_SPORT1_TSCLK (P_DONTCARE)
-#define P_SPORT1_RSCLK (P_DONTCARE)
-#define P_SPORT0_TSCLK (P_DONTCARE)
-#define P_SPORT0_RSCLK (P_DONTCARE)
-#define P_SPORT1_DRSEC (P_DONTCARE)
-#define P_SPORT1_RFS (P_DONTCARE)
-#define P_SPORT1_DTPRI (P_DONTCARE)
-#define P_SPORT1_DTSEC (P_DONTCARE)
-#define P_SPORT1_TFS (P_DONTCARE)
-#define P_SPORT1_DRPRI (P_DONTCARE)
-#define P_SPORT0_DRSEC (P_DONTCARE)
-#define P_SPORT0_RFS (P_DONTCARE)
-#define P_SPORT0_DTPRI (P_DONTCARE)
-#define P_SPORT0_DTSEC (P_DONTCARE)
-#define P_SPORT0_TFS (P_DONTCARE)
-#define P_SPORT0_DRPRI (P_DONTCARE)
-
-#define P_UART0_RX (P_DONTCARE)
-#define P_UART0_TX (P_DONTCARE)
-
-#define P_SPI0_MOSI (P_DONTCARE)
-#define P_SPI0_MISO (P_DONTCARE)
-#define P_SPI0_SCK (P_DONTCARE)
-
-#define P_PPI0_D0 (P_DONTCARE)
-#define P_PPI0_D1 (P_DONTCARE)
-#define P_PPI0_D2 (P_DONTCARE)
-#define P_PPI0_D3 (P_DONTCARE)
-
-#define P_CAN0_TX (P_DEFINED | P_IDENT(GPIO_PC0))
-#define P_CAN0_RX (P_DEFINED | P_IDENT(GPIO_PC1))
-
-#define P_SPI1_MOSI (P_DEFINED | P_IDENT(GPIO_PD0))
-#define P_SPI1_MISO (P_DEFINED | P_IDENT(GPIO_PD1))
-#define P_SPI1_SCK (P_DEFINED | P_IDENT(GPIO_PD2))
-#define P_SPI1_SS (P_DEFINED | P_IDENT(GPIO_PD3))
-#define P_SPI1_SSEL1 (P_DEFINED | P_IDENT(GPIO_PD4))
-#define P_SPI2_MOSI (P_DEFINED | P_IDENT(GPIO_PD5))
-#define P_SPI2_MISO (P_DEFINED | P_IDENT(GPIO_PD6))
-#define P_SPI2_SCK (P_DEFINED | P_IDENT(GPIO_PD7))
-#define P_SPI2_SS (P_DEFINED | P_IDENT(GPIO_PD8))
-#define P_SPI2_SSEL1 (P_DEFINED | P_IDENT(GPIO_PD9))
-#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PD10))
-#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PD11))
-#define P_UART2_RX (P_DEFINED | P_IDENT(GPIO_PD12))
-#define P_UART2_TX (P_DEFINED | P_IDENT(GPIO_PD13))
-
-#define P_SPORT2_RSCLK (P_DEFINED | P_IDENT(GPIO_PE0))
-#define P_SPORT2_RFS (P_DEFINED | P_IDENT(GPIO_PE1))
-#define P_SPORT2_DRPRI (P_DEFINED | P_IDENT(GPIO_PE2))
-#define P_SPORT2_DRSEC (P_DEFINED | P_IDENT(GPIO_PE3))
-#define P_SPORT2_TSCLK (P_DEFINED | P_IDENT(GPIO_PE4))
-#define P_SPORT2_TFS (P_DEFINED | P_IDENT(GPIO_PE5))
-#define P_SPORT2_DTPRI (P_DEFINED | P_IDENT(GPIO_PE6))
-#define P_SPORT2_DTSEC (P_DEFINED | P_IDENT(GPIO_PE7))
-#define P_SPORT3_RSCLK (P_DEFINED | P_IDENT(GPIO_PE8))
-#define P_SPORT3_RFS (P_DEFINED | P_IDENT(GPIO_PE9))
-#define P_SPORT3_DRPRI (P_DEFINED | P_IDENT(GPIO_PE10))
-#define P_SPORT3_DRSEC (P_DEFINED | P_IDENT(GPIO_PE11))
-#define P_SPORT3_TSCLK (P_DEFINED | P_IDENT(GPIO_PE12))
-#define P_SPORT3_TFS (P_DEFINED | P_IDENT(GPIO_PE13))
-#define P_SPORT3_DTPRI (P_DEFINED | P_IDENT(GPIO_PE14))
-#define P_SPORT3_DTSEC (P_DEFINED | P_IDENT(GPIO_PE15))
-
-#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PF3))
-#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF4))
-#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF5))
-#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF6))
-#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF7))
-#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF8))
-#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF9))
-#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF10))
-#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF11))
-
-#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF15))
-#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF14))
-#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF13))
-#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF12))
-#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF7))
-#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF6))
-#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5))
-#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF4))
-#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF3))
-#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2))
-#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1))
-#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0))
-#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF2
-#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2
-
-#endif /* _MACH_PORTMUX_H_ */
+++ /dev/null
-/*
- * Set up the interrupt priorities
- *
- * Copyright 2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-#include <linux/irq.h>
-#include <asm/blackfin.h>
-
-void __init program_IAR(void)
-{
-
- /* Program the IAR0 Register with the configured priority */
- bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) |
- ((CONFIG_IRQ_DMA0_ERROR - 7) << IRQ_DMA0_ERROR_POS) |
- ((CONFIG_IRQ_PPI_ERROR - 7) << IRQ_PPI_ERROR_POS) |
- ((CONFIG_IRQ_SPORT0_ERROR - 7) << IRQ_SPORT0_ERROR_POS) |
- ((CONFIG_IRQ_SPORT1_ERROR - 7) << IRQ_SPORT1_ERROR_POS) |
- ((CONFIG_IRQ_SPI0_ERROR - 7) << IRQ_SPI0_ERROR_POS) |
- ((CONFIG_IRQ_UART0_ERROR - 7) << IRQ_UART0_ERROR_POS) |
- ((CONFIG_IRQ_RTC - 7) << IRQ_RTC_POS));
-
- bfin_write_SIC_IAR1(((CONFIG_IRQ_PPI - 7) << IRQ_PPI_POS) |
- ((CONFIG_IRQ_SPORT0_RX - 7) << IRQ_SPORT0_RX_POS) |
- ((CONFIG_IRQ_SPORT0_TX - 7) << IRQ_SPORT0_TX_POS) |
- ((CONFIG_IRQ_SPORT1_RX - 7) << IRQ_SPORT1_RX_POS) |
- ((CONFIG_IRQ_SPORT1_TX - 7) << IRQ_SPORT1_TX_POS) |
- ((CONFIG_IRQ_SPI0 - 7) << IRQ_SPI0_POS) |
- ((CONFIG_IRQ_UART0_RX - 7) << IRQ_UART0_RX_POS) |
- ((CONFIG_IRQ_UART0_TX - 7) << IRQ_UART0_TX_POS));
-
- bfin_write_SIC_IAR2(((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) |
- ((CONFIG_IRQ_TIMER1 - 7) << IRQ_TIMER1_POS) |
- ((CONFIG_IRQ_TIMER2 - 7) << IRQ_TIMER2_POS) |
- ((CONFIG_IRQ_PORTF_INTA - 7) << IRQ_PORTF_INTA_POS) |
- ((CONFIG_IRQ_PORTF_INTB - 7) << IRQ_PORTF_INTB_POS) |
- ((CONFIG_IRQ_MEM0_DMA0 - 7) << IRQ_MEM0_DMA0_POS) |
- ((CONFIG_IRQ_MEM0_DMA1 - 7) << IRQ_MEM0_DMA1_POS) |
- ((CONFIG_IRQ_WATCH - 7) << IRQ_WATCH_POS));
-
- bfin_write_SIC_IAR3(((CONFIG_IRQ_DMA1_ERROR - 7) << IRQ_DMA1_ERROR_POS) |
- ((CONFIG_IRQ_SPORT2_ERROR - 7) << IRQ_SPORT2_ERROR_POS) |
- ((CONFIG_IRQ_SPORT3_ERROR - 7) << IRQ_SPORT3_ERROR_POS) |
- ((CONFIG_IRQ_SPI1_ERROR - 7) << IRQ_SPI1_ERROR_POS) |
- ((CONFIG_IRQ_SPI2_ERROR - 7) << IRQ_SPI2_ERROR_POS) |
- ((CONFIG_IRQ_UART1_ERROR - 7) << IRQ_UART1_ERROR_POS) |
- ((CONFIG_IRQ_UART2_ERROR - 7) << IRQ_UART2_ERROR_POS));
-
- bfin_write_SIC_IAR4(((CONFIG_IRQ_CAN_ERROR - 7) << IRQ_CAN_ERROR_POS) |
- ((CONFIG_IRQ_SPORT2_RX - 7) << IRQ_SPORT2_RX_POS) |
- ((CONFIG_IRQ_SPORT2_TX - 7) << IRQ_SPORT2_TX_POS) |
- ((CONFIG_IRQ_SPORT3_RX - 7) << IRQ_SPORT3_RX_POS) |
- ((CONFIG_IRQ_SPORT3_TX - 7) << IRQ_SPORT3_TX_POS) |
- ((CONFIG_IRQ_SPI1 - 7) << IRQ_SPI1_POS));
-
- bfin_write_SIC_IAR5(((CONFIG_IRQ_SPI2 - 7) << IRQ_SPI2_POS) |
- ((CONFIG_IRQ_UART1_RX - 7) << IRQ_UART1_RX_POS) |
- ((CONFIG_IRQ_UART1_TX - 7) << IRQ_UART1_TX_POS) |
- ((CONFIG_IRQ_UART2_RX - 7) << IRQ_UART2_RX_POS) |
- ((CONFIG_IRQ_UART2_TX - 7) << IRQ_UART2_TX_POS) |
- ((CONFIG_IRQ_TWI0 - 7) << IRQ_TWI0_POS) |
- ((CONFIG_IRQ_TWI1 - 7) << IRQ_TWI1_POS) |
- ((CONFIG_IRQ_CAN_RX - 7) << IRQ_CAN_RX_POS));
-
- bfin_write_SIC_IAR6(((CONFIG_IRQ_CAN_TX - 7) << IRQ_CAN_TX_POS) |
- ((CONFIG_IRQ_MEM1_DMA0 - 7) << IRQ_MEM1_DMA0_POS) |
- ((CONFIG_IRQ_MEM1_DMA1 - 7) << IRQ_MEM1_DMA1_POS));
-
- SSYNC();
-}
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0
-config BF542
- def_bool y
- depends on BF542_std || BF542M
-config BF544
- def_bool y
- depends on BF544_std || BF544M
-config BF547
- def_bool y
- depends on BF547_std || BF547M
-config BF548
- def_bool y
- depends on BF548_std || BF548M
-config BF549
- def_bool y
- depends on BF549_std || BF549M
-
-config BF54xM
- def_bool y
- depends on (BF542M || BF544M || BF547M || BF548M || BF549M)
-
-config BF54x
- def_bool y
- depends on (BF542 || BF544 || BF547 || BF548 || BF549)
-
-if (BF54x)
-
-source "arch/blackfin/mach-bf548/boards/Kconfig"
-
-menu "BF548 Specific Configuration"
-
-config DEB_DMA_URGENT
- bool "DMA has priority over core for ext. accesses"
- depends on BF54x
- default y
- help
- Treat any DEB1, DEB2 and DEB3 request as Urgent
-
-config BF548_ATAPI_ALTERNATIVE_PORT
- bool "BF548 ATAPI alternative port via GPIO"
- help
- BF548 ATAPI data and address PINs can be routed through
- async address or GPIO port F and G. Select y to route it
- to GPIO.
-
-choice
- prompt "UART2 DMA channel selection"
- depends on SERIAL_BFIN_UART2
- default UART2_DMA_RX_ON_DMA18
- help
- UART2 DMA channel selection
- RX -> DMA18
- TX -> DMA19
- or
- RX -> DMA13
- TX -> DMA14
-
-config UART2_DMA_RX_ON_DMA18
- bool "UART2 DMA RX -> DMA18 TX -> DMA19"
- help
- UART2 DMA channel assignment
- RX -> DMA18
- TX -> DMA19
- use SPORT2 default DMA channel
-
-config UART2_DMA_RX_ON_DMA13
- bool "UART2 DMA RX -> DMA13 TX -> DMA14"
- help
- UART2 DMA channel assignment
- RX -> DMA13
- TX -> DMA14
- use EPPI1 EPPI2 default DMA channel
-endchoice
-
-choice
- prompt "UART3 DMA channel selection"
- depends on SERIAL_BFIN_UART3
- default UART3_DMA_RX_ON_DMA20
- help
- UART3 DMA channel selection
- RX -> DMA20
- TX -> DMA21
- or
- RX -> DMA15
- TX -> DMA16
-
-config UART3_DMA_RX_ON_DMA20
- bool "UART3 DMA RX -> DMA20 TX -> DMA21"
- help
- UART3 DMA channel assignment
- RX -> DMA20
- TX -> DMA21
- use SPORT3 default DMA channel
-
-config UART3_DMA_RX_ON_DMA15
- bool "UART3 DMA RX -> DMA15 TX -> DMA16"
- help
- UART3 DMA channel assignment
- RX -> DMA15
- TX -> DMA16
- use PIXC default DMA channel
-
-endchoice
-
-comment "Interrupt Priority Assignment"
-menu "Priority"
-
-config IRQ_PLL_WAKEUP
- int "IRQ_PLL_WAKEUP"
- default 7
-config IRQ_DMAC0_ERR
- int "IRQ_DMAC0_ERR"
- default 7
-config IRQ_EPPI0_ERR
- int "IRQ_EPPI0_ERR"
- default 7
-config IRQ_SPORT0_ERR
- int "IRQ_SPORT0_ERR"
- default 7
-config IRQ_SPORT1_ERR
- int "IRQ_SPORT1_ERR"
- default 7
-config IRQ_SPI0_ERR
- int "IRQ_SPI0_ERR"
- default 7
-config IRQ_UART0_ERR
- int "IRQ_UART0_ERR"
- default 7
-config IRQ_RTC
- int "IRQ_RTC"
- default 8
-config IRQ_EPPI0
- int "IRQ_EPPI0"
- default 8
-config IRQ_SPORT0_RX
- int "IRQ_SPORT0_RX"
- default 9
-config IRQ_SPORT0_TX
- int "IRQ_SPORT0_TX"
- default 9
-config IRQ_SPORT1_RX
- int "IRQ_SPORT1_RX"
- default 9
-config IRQ_SPORT1_TX
- int "IRQ_SPORT1_TX"
- default 9
-config IRQ_SPI0
- int "IRQ_SPI0"
- default 10
-config IRQ_UART0_RX
- int "IRQ_UART0_RX"
- default 10
-config IRQ_UART0_TX
- int "IRQ_UART0_TX"
- default 10
-config IRQ_TIMER8
- int "IRQ_TIMER8"
- default 11
-config IRQ_TIMER9
- int "IRQ_TIMER9"
- default 11
-config IRQ_TIMER10
- int "IRQ_TIMER10"
- default 11
-config IRQ_PINT0
- int "IRQ_PINT0"
- default 12
-config IRQ_PINT1
- int "IRQ_PINT0"
- default 12
-config IRQ_MDMAS0
- int "IRQ_MDMAS0"
- default 13
-config IRQ_MDMAS1
- int "IRQ_DMDMAS1"
- default 13
-config IRQ_WATCHDOG
- int "IRQ_WATCHDOG"
- default 13
-config IRQ_DMAC1_ERR
- int "IRQ_DMAC1_ERR"
- default 7
-config IRQ_SPORT2_ERR
- int "IRQ_SPORT2_ERR"
- default 7
-config IRQ_SPORT3_ERR
- int "IRQ_SPORT3_ERR"
- default 7
-config IRQ_MXVR_DATA
- int "IRQ MXVR Data"
- default 7
-config IRQ_SPI1_ERR
- int "IRQ_SPI1_ERR"
- default 7
-config IRQ_SPI2_ERR
- int "IRQ_SPI2_ERR"
- default 7
-config IRQ_UART1_ERR
- int "IRQ_UART1_ERR"
- default 7
-config IRQ_UART2_ERR
- int "IRQ_UART2_ERR"
- default 7
-config IRQ_CAN0_ERR
- int "IRQ_CAN0_ERR"
- default 7
-config IRQ_SPORT2_RX
- int "IRQ_SPORT2_RX"
- default 9
-config IRQ_SPORT2_TX
- int "IRQ_SPORT2_TX"
- default 9
-config IRQ_SPORT3_RX
- int "IRQ_SPORT3_RX"
- default 9
-config IRQ_SPORT3_TX
- int "IRQ_SPORT3_TX"
- default 9
-config IRQ_EPPI1
- int "IRQ_EPPI1"
- default 9
-config IRQ_EPPI2
- int "IRQ_EPPI2"
- default 9
-config IRQ_SPI1
- int "IRQ_SPI1"
- default 10
-config IRQ_SPI2
- int "IRQ_SPI2"
- default 10
-config IRQ_UART1_RX
- int "IRQ_UART1_RX"
- default 10
-config IRQ_UART1_TX
- int "IRQ_UART1_TX"
- default 10
-config IRQ_ATAPI_RX
- int "IRQ_ATAPI_RX"
- default 10
-config IRQ_ATAPI_TX
- int "IRQ_ATAPI_TX"
- default 10
-config IRQ_TWI0
- int "IRQ_TWI0"
- default 11
-config IRQ_TWI1
- int "IRQ_TWI1"
- default 11
-config IRQ_CAN0_RX
- int "IRQ_CAN_RX"
- default 11
-config IRQ_CAN0_TX
- int "IRQ_CAN_TX"
- default 11
-config IRQ_MDMAS2
- int "IRQ_MDMAS2"
- default 13
-config IRQ_MDMAS3
- int "IRQ_DMMAS3"
- default 13
-config IRQ_MXVR_ERR
- int "IRQ_MXVR_ERR"
- default 11
-config IRQ_MXVR_MSG
- int "IRQ_MXVR_MSG"
- default 11
-config IRQ_MXVR_PKT
- int "IRQ_MXVR_PKT"
- default 11
-config IRQ_EPPI1_ERR
- int "IRQ_EPPI1_ERR"
- default 7
-config IRQ_EPPI2_ERR
- int "IRQ_EPPI2_ERR"
- default 7
-config IRQ_UART3_ERR
- int "IRQ_UART3_ERR"
- default 7
-config IRQ_HOST_ERR
- int "IRQ_HOST_ERR"
- default 7
-config IRQ_PIXC_ERR
- int "IRQ_PIXC_ERR"
- default 7
-config IRQ_NFC_ERR
- int "IRQ_NFC_ERR"
- default 7
-config IRQ_ATAPI_ERR
- int "IRQ_ATAPI_ERR"
- default 7
-config IRQ_CAN1_ERR
- int "IRQ_CAN1_ERR"
- default 7
-config IRQ_HS_DMA_ERR
- int "IRQ Handshake DMA Status"
- default 7
-config IRQ_PIXC_IN0
- int "IRQ PIXC IN0"
- default 8
-config IRQ_PIXC_IN1
- int "IRQ PIXC IN1"
- default 8
-config IRQ_PIXC_OUT
- int "IRQ PIXC OUT"
- default 8
-config IRQ_SDH
- int "IRQ SDH"
- default 8
-config IRQ_CNT
- int "IRQ CNT"
- default 8
-config IRQ_KEY
- int "IRQ KEY"
- default 8
-config IRQ_CAN1_RX
- int "IRQ CAN1 RX"
- default 11
-config IRQ_CAN1_TX
- int "IRQ_CAN1_TX"
- default 11
-config IRQ_SDH_MASK0
- int "IRQ_SDH_MASK0"
- default 11
-config IRQ_SDH_MASK1
- int "IRQ_SDH_MASK1"
- default 11
-config IRQ_USB_INT0
- int "IRQ USB INT0"
- default 11
-config IRQ_USB_INT1
- int "IRQ USB INT1"
- default 11
-config IRQ_USB_INT2
- int "IRQ USB INT2"
- default 11
-config IRQ_USB_DMA
- int "IRQ USB DMA"
- default 11
-config IRQ_OTPSEC
- int "IRQ OPTSEC"
- default 11
-config IRQ_TIMER0
- int "IRQ_TIMER0"
- default 7 if TICKSOURCE_GPTMR0
- default 8
-config IRQ_TIMER1
- int "IRQ_TIMER1"
- default 11
-config IRQ_TIMER2
- int "IRQ_TIMER2"
- default 11
-config IRQ_TIMER3
- int "IRQ_TIMER3"
- default 11
-config IRQ_TIMER4
- int "IRQ_TIMER4"
- default 11
-config IRQ_TIMER5
- int "IRQ_TIMER5"
- default 11
-config IRQ_TIMER6
- int "IRQ_TIMER6"
- default 11
-config IRQ_TIMER7
- int "IRQ_TIMER7"
- default 11
-config IRQ_PINT2
- int "IRQ_PIN2"
- default 11
-config IRQ_PINT3
- int "IRQ_PIN3"
- default 11
-
- help
- Enter the priority numbers between 7-13 ONLY. Others are Reserved.
- This applies to all the above. It is not recommended to assign the
- highest priority number 7 to UART or any other device.
-
-endmenu
-
-endmenu
-
-endif
+++ /dev/null
-#
-# arch/blackfin/mach-bf537/Makefile
-#
-
-obj-y := ints-priority.o dma.o
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0
-choice
- prompt "System type"
- default BFIN548_EZKIT
- help
- Select your board!
-
-config BFIN548_EZKIT
- bool "BF548-EZKIT"
- help
- BFIN548-EZKIT board support.
-
-config BFIN548_BLUETECHNIX_CM
- bool "Bluetechnix CM-BF548"
- depends on (BF548)
- help
- CM-BF548 support for DEV-Board.
-
-endchoice
+++ /dev/null
-#
-# arch/blackfin/mach-bf548/boards/Makefile
-#
-
-obj-$(CONFIG_BFIN548_EZKIT) += ezkit.o
-obj-$(CONFIG_BFIN548_BLUETECHNIX_CM) += cm_bf548.o
+++ /dev/null
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2008-2009 Bluetechnix
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <linux/usb/musb.h>
-#include <linux/gpio.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/dma.h>
-#include <asm/nand.h>
-#include <asm/portmux.h>
-#include <asm/bfin_sdh.h>
-#include <mach/bf54x_keys.h>
-#include <asm/dpmc.h>
-#include <linux/input.h>
-#include <linux/spi/ad7877.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "Bluetechnix CM-BF548";
-
-/*
- * Driver needs to know address, irq and flag pin.
- */
-
-#if IS_ENABLED(CONFIG_FB_BF54X_LQ043)
-
-#include <mach/bf54x-lq043.h>
-
-static struct bfin_bf54xfb_mach_info bf54x_lq043_data = {
- .width = 480,
- .height = 272,
- .xres = {480, 480, 480},
- .yres = {272, 272, 272},
- .bpp = {24, 24, 24},
- .disp = GPIO_PE3,
-};
-
-static struct resource bf54x_lq043_resources[] = {
- {
- .start = IRQ_EPPI0_ERR,
- .end = IRQ_EPPI0_ERR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bf54x_lq043_device = {
- .name = "bf54x-lq043",
- .id = -1,
- .num_resources = ARRAY_SIZE(bf54x_lq043_resources),
- .resource = bf54x_lq043_resources,
- .dev = {
- .platform_data = &bf54x_lq043_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_BFIN)
-static unsigned int bf548_keymap[] = {
- KEYVAL(0, 0, KEY_ENTER),
- KEYVAL(0, 1, KEY_HELP),
- KEYVAL(0, 2, KEY_0),
- KEYVAL(0, 3, KEY_BACKSPACE),
- KEYVAL(1, 0, KEY_TAB),
- KEYVAL(1, 1, KEY_9),
- KEYVAL(1, 2, KEY_8),
- KEYVAL(1, 3, KEY_7),
- KEYVAL(2, 0, KEY_DOWN),
- KEYVAL(2, 1, KEY_6),
- KEYVAL(2, 2, KEY_5),
- KEYVAL(2, 3, KEY_4),
- KEYVAL(3, 0, KEY_UP),
- KEYVAL(3, 1, KEY_3),
- KEYVAL(3, 2, KEY_2),
- KEYVAL(3, 3, KEY_1),
-};
-
-static struct bfin_kpad_platform_data bf54x_kpad_data = {
- .rows = 4,
- .cols = 4,
- .keymap = bf548_keymap,
- .keymapsize = ARRAY_SIZE(bf548_keymap),
- .repeat = 0,
- .debounce_time = 5000, /* ns (5ms) */
- .coldrive_time = 1000, /* ns (1ms) */
- .keyup_test_interval = 50, /* ms (50ms) */
-};
-
-static struct resource bf54x_kpad_resources[] = {
- {
- .start = IRQ_KEY,
- .end = IRQ_KEY,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bf54x_kpad_device = {
- .name = "bf54x-keys",
- .id = -1,
- .num_resources = ARRAY_SIZE(bf54x_kpad_resources),
- .resource = bf54x_kpad_resources,
- .dev = {
- .platform_data = &bf54x_kpad_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_DLL,
- .end = UART0_RBR+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_DLL,
- .end = UART1_RBR+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-#ifdef CONFIG_BFIN_UART1_CTSRTS
- { /* CTS pin -- 0 means not supported */
- .start = GPIO_PE10,
- .end = GPIO_PE10,
- .flags = IORESOURCE_IO,
- },
- { /* RTS pin -- 0 means not supported */
- .start = GPIO_PE9,
- .end = GPIO_PE9,
- .flags = IORESOURCE_IO,
- },
-#endif
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX,
-#ifdef CONFIG_BFIN_UART1_CTSRTS
- P_UART1_RTS, P_UART1_CTS,
-#endif
- 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART2
-static struct resource bfin_uart2_resources[] = {
- {
- .start = UART2_DLL,
- .end = UART2_RBR+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART2_TX,
- .end = IRQ_UART2_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART2_RX,
- .end = IRQ_UART2_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART2_ERROR,
- .end = IRQ_UART2_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART2_TX,
- .end = CH_UART2_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART2_RX,
- .end = CH_UART2_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart2_peripherals[] = {
- P_UART2_TX, P_UART2_RX, 0
-};
-
-static struct platform_device bfin_uart2_device = {
- .name = "bfin-uart",
- .id = 2,
- .num_resources = ARRAY_SIZE(bfin_uart2_resources),
- .resource = bfin_uart2_resources,
- .dev = {
- .platform_data = &bfin_uart2_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART3
-static struct resource bfin_uart3_resources[] = {
- {
- .start = UART3_DLL,
- .end = UART3_RBR+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART3_TX,
- .end = IRQ_UART3_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART3_RX,
- .end = IRQ_UART3_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART3_ERROR,
- .end = IRQ_UART3_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART3_TX,
- .end = CH_UART3_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART3_RX,
- .end = CH_UART3_RX,
- .flags = IORESOURCE_DMA,
- },
-#ifdef CONFIG_BFIN_UART3_CTSRTS
- { /* CTS pin -- 0 means not supported */
- .start = GPIO_PB3,
- .end = GPIO_PB3,
- .flags = IORESOURCE_IO,
- },
- { /* RTS pin -- 0 means not supported */
- .start = GPIO_PB2,
- .end = GPIO_PB2,
- .flags = IORESOURCE_IO,
- },
-#endif
-};
-
-static unsigned short bfin_uart3_peripherals[] = {
- P_UART3_TX, P_UART3_RX,
-#ifdef CONFIG_BFIN_UART3_CTSRTS
- P_UART3_RTS, P_UART3_CTS,
-#endif
- 0
-};
-
-static struct platform_device bfin_uart3_device = {
- .name = "bfin-uart",
- .id = 3,
- .num_resources = ARRAY_SIZE(bfin_uart3_resources),
- .resource = bfin_uart3_resources,
- .dev = {
- .platform_data = &bfin_uart3_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR2
-static struct resource bfin_sir2_resources[] = {
- {
- .start = 0xFFC02100,
- .end = 0xFFC021FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART2_RX,
- .end = IRQ_UART2_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART2_RX,
- .end = CH_UART2_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sir2_device = {
- .name = "bfin_sir",
- .id = 2,
- .num_resources = ARRAY_SIZE(bfin_sir2_resources),
- .resource = bfin_sir2_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR3
-static struct resource bfin_sir3_resources[] = {
- {
- .start = 0xFFC03100,
- .end = 0xFFC031FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART3_RX,
- .end = IRQ_UART3_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART3_RX,
- .end = CH_UART3_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sir3_device = {
- .name = "bfin_sir",
- .id = 3,
- .num_resources = ARRAY_SIZE(bfin_sir3_resources),
- .resource = bfin_sir3_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_SMSC911X)
-#include <linux/smsc911x.h>
-
-static struct resource smsc911x_resources[] = {
- {
- .name = "smsc911x-memory",
- .start = 0x24000000,
- .end = 0x24000000 + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PE6,
- .end = IRQ_PE6,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
- },
-};
-
-static struct smsc911x_platform_config smsc911x_config = {
- .flags = SMSC911X_USE_16BIT,
- .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
- .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
- .phy_interface = PHY_INTERFACE_MODE_MII,
-};
-
-static struct platform_device smsc911x_device = {
- .name = "smsc911x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smsc911x_resources),
- .resource = smsc911x_resources,
- .dev = {
- .platform_data = &smsc911x_config,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
-static struct resource musb_resources[] = {
- [0] = {
- .start = 0xFFC03C00,
- .end = 0xFFC040FF,
- .flags = IORESOURCE_MEM,
- },
- [1] = { /* general IRQ */
- .start = IRQ_USB_INT0,
- .end = IRQ_USB_INT0,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- .name = "mc"
- },
- [2] = { /* DMA IRQ */
- .start = IRQ_USB_DMA,
- .end = IRQ_USB_DMA,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- .name = "dma"
- },
-};
-
-static struct musb_hdrc_config musb_config = {
- .multipoint = 0,
- .dyn_fifo = 0,
- .soft_con = 1,
- .dma = 1,
- .num_eps = 8,
- .dma_channels = 8,
- .gpio_vrsel = GPIO_PH6,
- /* Some custom boards need to be active low, just set it to "0"
- * if it is the case.
- */
- .gpio_vrsel_active = 1,
- .clkin = 24, /* musb CLKIN in MHZ */
-};
-
-static struct musb_hdrc_platform_data musb_plat = {
-#if defined(CONFIG_USB_MUSB_OTG)
- .mode = MUSB_OTG,
-#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
- .mode = MUSB_HOST,
-#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
- .mode = MUSB_PERIPHERAL,
-#endif
- .config = &musb_config,
-};
-
-static u64 musb_dmamask = ~(u32)0;
-
-static struct platform_device musb_device = {
- .name = "musb-blackfin",
- .id = 0,
- .dev = {
- .dma_mask = &musb_dmamask,
- .coherent_dma_mask = 0xffffffff,
- .platform_data = &musb_plat,
- },
- .num_resources = ARRAY_SIZE(musb_resources),
- .resource = musb_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
-static struct resource bfin_sport2_uart_resources[] = {
- {
- .start = SPORT2_TCR1,
- .end = SPORT2_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT2_RX,
- .end = IRQ_SPORT2_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT2_ERROR,
- .end = IRQ_SPORT2_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport2_peripherals[] = {
- P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS,
- P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0
-};
-
-static struct platform_device bfin_sport2_uart_device = {
- .name = "bfin-sport-uart",
- .id = 2,
- .num_resources = ARRAY_SIZE(bfin_sport2_uart_resources),
- .resource = bfin_sport2_uart_resources,
- .dev = {
- .platform_data = &bfin_sport2_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
-static struct resource bfin_sport3_uart_resources[] = {
- {
- .start = SPORT3_TCR1,
- .end = SPORT3_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT3_RX,
- .end = IRQ_SPORT3_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT3_ERROR,
- .end = IRQ_SPORT3_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport3_peripherals[] = {
- P_SPORT3_TFS, P_SPORT3_DTPRI, P_SPORT3_TSCLK, P_SPORT3_RFS,
- P_SPORT3_DRPRI, P_SPORT3_RSCLK, P_SPORT3_DRSEC, P_SPORT3_DTSEC, 0
-};
-
-static struct platform_device bfin_sport3_uart_device = {
- .name = "bfin-sport-uart",
- .id = 3,
- .num_resources = ARRAY_SIZE(bfin_sport3_uart_resources),
- .resource = bfin_sport3_uart_resources,
- .dev = {
- .platform_data = &bfin_sport3_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_PATA_BF54X)
-static struct resource bfin_atapi_resources[] = {
- {
- .start = 0xFFC03800,
- .end = 0xFFC0386F,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_ATAPI_ERR,
- .end = IRQ_ATAPI_ERR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_atapi_device = {
- .name = "pata-bf54x",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_atapi_resources),
- .resource = bfin_atapi_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
-static struct mtd_partition partition_info[] = {
- {
- .name = "linux kernel(nand)",
- .offset = 0,
- .size = 4 * 1024 * 1024,
- },
- {
- .name = "file system(nand)",
- .offset = 4 * 1024 * 1024,
- .size = (256 - 4) * 1024 * 1024,
- },
-};
-
-static struct bf5xx_nand_platform bf5xx_nand_platform = {
- .data_width = NFC_NWIDTH_8,
- .partitions = partition_info,
- .nr_partitions = ARRAY_SIZE(partition_info),
- .rd_dly = 3,
- .wr_dly = 3,
-};
-
-static struct resource bf5xx_nand_resources[] = {
- {
- .start = 0xFFC03B00,
- .end = 0xFFC03B4F,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = CH_NFC,
- .end = CH_NFC,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bf5xx_nand_device = {
- .name = "bf5xx-nand",
- .id = 0,
- .num_resources = ARRAY_SIZE(bf5xx_nand_resources),
- .resource = bf5xx_nand_resources,
- .dev = {
- .platform_data = &bf5xx_nand_platform,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SDH_BFIN)
-static struct bfin_sd_host bfin_sdh_data = {
- .dma_chan = CH_SDH,
- .irq_int0 = IRQ_SDH_MASK0,
- .pin_req = {P_SD_D0, P_SD_D1, P_SD_D2, P_SD_D3, P_SD_CLK, P_SD_CMD, 0},
-};
-
-static struct platform_device bf54x_sdh_device = {
- .name = "bfin-sdh",
- .id = 0,
- .dev = {
- .platform_data = &bfin_sdh_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_CAN_BFIN)
-static unsigned short bfin_can_peripherals[] = {
- P_CAN0_RX, P_CAN0_TX, 0
-};
-
-static struct resource bfin_can_resources[] = {
- {
- .start = 0xFFC02A00,
- .end = 0xFFC02FFF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_CAN0_RX,
- .end = IRQ_CAN0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_CAN0_TX,
- .end = IRQ_CAN0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_CAN0_ERROR,
- .end = IRQ_CAN0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_can_device = {
- .name = "bfin_can",
- .num_resources = ARRAY_SIZE(bfin_can_resources),
- .resource = bfin_can_resources,
- .dev = {
- .platform_data = &bfin_can_peripherals, /* Passed to driver */
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
-static struct mtd_partition para_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x40000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0x100000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct physmap_flash_data para_flash_data = {
- .width = 2,
- .parts = para_partitions,
- .nr_parts = ARRAY_SIZE(para_partitions),
-};
-
-static struct resource para_flash_resource = {
- .start = 0x20000000,
- .end = 0x207fffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device para_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = ¶_flash_data,
- },
- .num_resources = 1,
- .resource = ¶_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* all SPI peripherals info goes here */
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-/* SPI flash chip (m25p16) */
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00040000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = 0x1c0000,
- .offset = 0x40000
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p16",
-};
-
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
-static const struct ad7877_platform_data bfin_ad7877_ts_info = {
- .model = 7877,
- .vref_delay_usecs = 50, /* internal, no capacitor */
- .x_plate_ohms = 419,
- .y_plate_ohms = 486,
- .pressure_max = 1000,
- .pressure_min = 0,
- .stopacq_polarity = 1,
- .first_conversion_delay = 3,
- .acquisition_time = 1,
- .averaging = 1,
- .pen_down_acc_interval = 1,
-};
-#endif
-
-static struct spi_board_info bf54x_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 1, /* SPI_SSEL1*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
-{
- .modalias = "ad7877",
- .platform_data = &bfin_ad7877_ts_info,
- .irq = IRQ_PJ11,
- .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 2,
-},
-#endif
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- },
-#endif
-};
-
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI0,
- .end = CH_SPI0,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI0,
- .end = IRQ_SPI0,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-/* SPI (1) */
-static struct resource bfin_spi1_resource[] = {
- [0] = {
- .start = SPI1_REGBASE,
- .end = SPI1_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI1,
- .end = CH_SPI1,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI1,
- .end = IRQ_SPI1,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-/* SPI controller data */
-static struct bfin5xx_spi_master bf54x_spi_master_info0 = {
- .num_chipselect = 4,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct platform_device bf54x_spi_master0 = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bf54x_spi_master_info0, /* Passed to driver */
- },
-};
-
-static struct bfin5xx_spi_master bf54x_spi_master_info1 = {
- .num_chipselect = 4,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
-};
-
-static struct platform_device bf54x_spi_master1 = {
- .name = "bfin-spi",
- .id = 1, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi1_resource),
- .resource = bfin_spi1_resource,
- .dev = {
- .platform_data = &bf54x_spi_master_info1, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_REGBASE,
- .end = TWI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI0,
- .end = IRQ_TWI0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi0_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-
-#if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */
-static const u16 bfin_twi1_pins[] = {P_TWI1_SCL, P_TWI1_SDA, 0};
-
-static struct resource bfin_twi1_resource[] = {
- [0] = {
- .start = TWI1_REGBASE,
- .end = TWI1_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI1,
- .end = IRQ_TWI1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi1_device = {
- .name = "i2c-bfin-twi",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_twi1_resource),
- .resource = bfin_twi1_resource,
- .dev = {
- .platform_data = &bfin_twi1_pins,
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
-#include <linux/gpio_keys.h>
-
-static struct gpio_keys_button bfin_gpio_keys_table[] = {
- {BTN_0, GPIO_PH7, 1, "gpio-keys: BTN0"},
-};
-
-static struct gpio_keys_platform_data bfin_gpio_keys_data = {
- .buttons = bfin_gpio_keys_table,
- .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
-};
-
-static struct platform_device bfin_device_gpiokeys = {
- .name = "gpio-keys",
- .dev = {
- .platform_data = &bfin_gpio_keys_data,
- },
-};
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
-/*
- * Internal VLEV BF54XSBBC1533
- ****temporarily using these values until data sheet is updated
- */
- VRPAIR(VLEV_085, 150000000),
- VRPAIR(VLEV_090, 250000000),
- VRPAIR(VLEV_110, 276000000),
- VRPAIR(VLEV_115, 301000000),
- VRPAIR(VLEV_120, 525000000),
- VRPAIR(VLEV_125, 550000000),
- VRPAIR(VLEV_130, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-static struct platform_device *cm_bf548_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART2
- &bfin_uart2_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART3
- &bfin_uart3_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#ifdef CONFIG_BFIN_SIR2
- &bfin_sir2_device,
-#endif
-#ifdef CONFIG_BFIN_SIR3
- &bfin_sir3_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BF54X_LQ043)
- &bf54x_lq043_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SMSC911X)
- &smsc911x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
- &musb_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
- &bfin_sport2_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
- &bfin_sport3_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_PATA_BF54X)
- &bfin_atapi_device,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
- &bf5xx_nand_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SDH_BFIN)
- &bf54x_sdh_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bf54x_spi_master0,
- &bf54x_spi_master1,
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_BFIN)
- &bf54x_kpad_device,
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi0_device,
-#if !defined(CONFIG_BF542)
- &i2c_bfin_twi1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
- &bfin_device_gpiokeys,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
- ¶_flash_device,
-#endif
-
-#if IS_ENABLED(CONFIG_CAN_BFIN)
- &bfin_can_device,
-#endif
-
-};
-
-static int __init cm_bf548_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- platform_add_devices(cm_bf548_devices, ARRAY_SIZE(cm_bf548_devices));
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- spi_register_board_info(bf54x_spi_board_info,
- ARRAY_SIZE(bf54x_spi_board_info));
-#endif
-
- return 0;
-}
-
-arch_initcall(cm_bf548_init);
-
-static struct platform_device *cm_bf548_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART2
- &bfin_uart2_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART3
- &bfin_uart3_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
- &bfin_sport2_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
- &bfin_sport3_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(cm_bf548_early_devices,
- ARRAY_SIZE(cm_bf548_early_devices));
-}
+++ /dev/null
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <linux/irq.h>
-#include <linux/i2c.h>
-#include <linux/interrupt.h>
-#include <linux/usb/musb.h>
-#include <linux/pinctrl/machine.h>
-#include <linux/pinctrl/pinconf-generic.h>
-#include <linux/platform_data/pinctrl-adi2.h>
-#include <linux/gpio.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/dma.h>
-#include <asm/nand.h>
-#include <asm/dpmc.h>
-#include <asm/bfin_sport.h>
-#include <asm/portmux.h>
-#include <asm/bfin_sdh.h>
-#include <mach/bf54x_keys.h>
-#include <linux/input.h>
-#include <linux/spi/ad7877.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "ADI BF548-EZKIT";
-
-/*
- * Driver needs to know address, irq and flag pin.
- */
-
-#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
-#include <linux/usb/isp1760.h>
-static struct resource bfin_isp1760_resources[] = {
- [0] = {
- .start = 0x2C0C0000,
- .end = 0x2C0C0000 + 0xfffff,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_PG7,
- .end = IRQ_PG7,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct isp1760_platform_data isp1760_priv = {
- .is_isp1761 = 0,
- .bus_width_16 = 1,
- .port1_otg = 0,
- .analog_oc = 0,
- .dack_polarity_high = 0,
- .dreq_polarity_high = 0,
-};
-
-static struct platform_device bfin_isp1760_device = {
- .name = "isp1760",
- .id = 0,
- .dev = {
- .platform_data = &isp1760_priv,
- },
- .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
- .resource = bfin_isp1760_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BF54X_LQ043)
-
-#include <mach/bf54x-lq043.h>
-
-static struct bfin_bf54xfb_mach_info bf54x_lq043_data = {
- .width = 95,
- .height = 54,
- .xres = {480, 480, 480},
- .yres = {272, 272, 272},
- .bpp = {24, 24, 24},
- .disp = GPIO_PE3,
-};
-
-static struct resource bf54x_lq043_resources[] = {
- {
- .start = IRQ_EPPI0_ERR,
- .end = IRQ_EPPI0_ERR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bf54x_lq043_device = {
- .name = "bf54x-lq043",
- .id = -1,
- .num_resources = ARRAY_SIZE(bf54x_lq043_resources),
- .resource = bf54x_lq043_resources,
- .dev = {
- .platform_data = &bf54x_lq043_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_BFIN)
-static const unsigned int bf548_keymap[] = {
- KEYVAL(0, 0, KEY_ENTER),
- KEYVAL(0, 1, KEY_HELP),
- KEYVAL(0, 2, KEY_0),
- KEYVAL(0, 3, KEY_BACKSPACE),
- KEYVAL(1, 0, KEY_TAB),
- KEYVAL(1, 1, KEY_9),
- KEYVAL(1, 2, KEY_8),
- KEYVAL(1, 3, KEY_7),
- KEYVAL(2, 0, KEY_DOWN),
- KEYVAL(2, 1, KEY_6),
- KEYVAL(2, 2, KEY_5),
- KEYVAL(2, 3, KEY_4),
- KEYVAL(3, 0, KEY_UP),
- KEYVAL(3, 1, KEY_3),
- KEYVAL(3, 2, KEY_2),
- KEYVAL(3, 3, KEY_1),
-};
-
-static struct bfin_kpad_platform_data bf54x_kpad_data = {
- .rows = 4,
- .cols = 4,
- .keymap = bf548_keymap,
- .keymapsize = ARRAY_SIZE(bf548_keymap),
- .repeat = 0,
- .debounce_time = 5000, /* ns (5ms) */
- .coldrive_time = 1000, /* ns (1ms) */
- .keyup_test_interval = 50, /* ms (50ms) */
-};
-
-static struct resource bf54x_kpad_resources[] = {
- {
- .start = IRQ_KEY,
- .end = IRQ_KEY,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bf54x_kpad_device = {
- .name = "bf54x-keys",
- .id = -1,
- .num_resources = ARRAY_SIZE(bf54x_kpad_resources),
- .resource = bf54x_kpad_resources,
- .dev = {
- .platform_data = &bf54x_kpad_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_BFIN_ROTARY)
-#include <linux/platform_data/bfin_rotary.h>
-
-static struct bfin_rotary_platform_data bfin_rotary_data = {
- /*.rotary_up_key = KEY_UP,*/
- /*.rotary_down_key = KEY_DOWN,*/
- .rotary_rel_code = REL_WHEEL,
- .rotary_button_key = KEY_ENTER,
- .debounce = 10, /* 0..17 */
- .mode = ROT_QUAD_ENC | ROT_DEBE,
- .pm_wakeup = 1,
-};
-
-static struct resource bfin_rotary_resources[] = {
- {
- .start = CNT_CONFIG,
- .end = CNT_CONFIG + 0xff,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_CNT,
- .end = IRQ_CNT,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_rotary_device = {
- .name = "bfin-rotary",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_rotary_resources),
- .resource = bfin_rotary_resources,
- .dev = {
- .platform_data = &bfin_rotary_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_ADXL34X)
-#include <linux/input/adxl34x.h>
-static const struct adxl34x_platform_data adxl34x_info = {
- .x_axis_offset = 0,
- .y_axis_offset = 0,
- .z_axis_offset = 0,
- .tap_threshold = 0x31,
- .tap_duration = 0x10,
- .tap_latency = 0x60,
- .tap_window = 0xF0,
- .tap_axis_control = ADXL_TAP_X_EN | ADXL_TAP_Y_EN | ADXL_TAP_Z_EN,
- .act_axis_control = 0xFF,
- .activity_threshold = 5,
- .inactivity_threshold = 3,
- .inactivity_time = 4,
- .free_fall_threshold = 0x7,
- .free_fall_time = 0x20,
- .data_rate = 0x8,
- .data_range = ADXL_FULL_RES,
-
- .ev_type = EV_ABS,
- .ev_code_x = ABS_X, /* EV_REL */
- .ev_code_y = ABS_Y, /* EV_REL */
- .ev_code_z = ABS_Z, /* EV_REL */
-
- .ev_code_tap = {BTN_TOUCH, BTN_TOUCH, BTN_TOUCH}, /* EV_KEY x,y,z */
-
-/* .ev_code_ff = KEY_F,*/ /* EV_KEY */
-/* .ev_code_act_inactivity = KEY_A,*/ /* EV_KEY */
- .power_mode = ADXL_AUTO_SLEEP | ADXL_LINK,
- .fifo_mode = ADXL_FIFO_STREAM,
- .orientation_enable = ADXL_EN_ORIENTATION_3D,
- .deadzone_angle = ADXL_DEADZONE_ANGLE_10p8,
- .divisor_length = ADXL_LP_FILTER_DIVISOR_16,
- /* EV_KEY {+Z, +Y, +X, -X, -Y, -Z} */
- .ev_codes_orient_3d = {BTN_Z, BTN_Y, BTN_X, BTN_A, BTN_B, BTN_C},
-};
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_DLL,
- .end = UART0_RBR+2,
- .flags = IORESOURCE_MEM,
- },
-#ifdef CONFIG_EARLY_PRINTK
- {
- .start = PORTE_FER,
- .end = PORTE_FER+2,
- .flags = IORESOURCE_REG,
- },
-#endif
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_DLL,
- .end = UART1_RBR+2,
- .flags = IORESOURCE_MEM,
- },
-#ifdef CONFIG_EARLY_PRINTK
- {
- .start = PORTH_FER,
- .end = PORTH_FER+2,
- .flags = IORESOURCE_REG,
- },
-#endif
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-#ifdef CONFIG_BFIN_UART1_CTSRTS
- { /* CTS pin -- 0 means not supported */
- .start = GPIO_PE10,
- .end = GPIO_PE10,
- .flags = IORESOURCE_IO,
- },
- { /* RTS pin -- 0 means not supported */
- .start = GPIO_PE9,
- .end = GPIO_PE9,
- .flags = IORESOURCE_IO,
- },
-#endif
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX,
-#ifdef CONFIG_BFIN_UART1_CTSRTS
- P_UART1_RTS, P_UART1_CTS,
-#endif
- 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART2
-static struct resource bfin_uart2_resources[] = {
- {
- .start = UART2_DLL,
- .end = UART2_RBR+2,
- .flags = IORESOURCE_MEM,
- },
-#ifdef CONFIG_EARLY_PRINTK
- {
- .start = PORTB_FER,
- .end = PORTB_FER+2,
- .flags = IORESOURCE_REG,
- },
-#endif
- {
- .start = IRQ_UART2_TX,
- .end = IRQ_UART2_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART2_RX,
- .end = IRQ_UART2_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART2_ERROR,
- .end = IRQ_UART2_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART2_TX,
- .end = CH_UART2_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART2_RX,
- .end = CH_UART2_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart2_peripherals[] = {
- P_UART2_TX, P_UART2_RX, 0
-};
-
-static struct platform_device bfin_uart2_device = {
- .name = "bfin-uart",
- .id = 2,
- .num_resources = ARRAY_SIZE(bfin_uart2_resources),
- .resource = bfin_uart2_resources,
- .dev = {
- .platform_data = &bfin_uart2_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART3
-static struct resource bfin_uart3_resources[] = {
- {
- .start = UART3_DLL,
- .end = UART3_RBR+2,
- .flags = IORESOURCE_MEM,
- },
-#ifdef CONFIG_EARLY_PRINTK
- {
- .start = PORTB_FER,
- .end = PORTB_FER+2,
- .flags = IORESOURCE_REG,
- },
-#endif
- {
- .start = IRQ_UART3_TX,
- .end = IRQ_UART3_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART3_RX,
- .end = IRQ_UART3_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART3_ERROR,
- .end = IRQ_UART3_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART3_TX,
- .end = CH_UART3_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART3_RX,
- .end = CH_UART3_RX,
- .flags = IORESOURCE_DMA,
- },
-#ifdef CONFIG_BFIN_UART3_CTSRTS
- { /* CTS pin -- 0 means not supported */
- .start = GPIO_PB3,
- .end = GPIO_PB3,
- .flags = IORESOURCE_IO,
- },
- { /* RTS pin -- 0 means not supported */
- .start = GPIO_PB2,
- .end = GPIO_PB2,
- .flags = IORESOURCE_IO,
- },
-#endif
-};
-
-static unsigned short bfin_uart3_peripherals[] = {
- P_UART3_TX, P_UART3_RX,
-#ifdef CONFIG_BFIN_UART3_CTSRTS
- P_UART3_RTS, P_UART3_CTS,
-#endif
- 0
-};
-
-static struct platform_device bfin_uart3_device = {
- .name = "bfin-uart",
- .id = 3,
- .num_resources = ARRAY_SIZE(bfin_uart3_resources),
- .resource = bfin_uart3_resources,
- .dev = {
- .platform_data = &bfin_uart3_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR2
-static struct resource bfin_sir2_resources[] = {
- {
- .start = 0xFFC02100,
- .end = 0xFFC021FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART2_RX,
- .end = IRQ_UART2_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART2_RX,
- .end = CH_UART2_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sir2_device = {
- .name = "bfin_sir",
- .id = 2,
- .num_resources = ARRAY_SIZE(bfin_sir2_resources),
- .resource = bfin_sir2_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR3
-static struct resource bfin_sir3_resources[] = {
- {
- .start = 0xFFC03100,
- .end = 0xFFC031FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART3_RX,
- .end = IRQ_UART3_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART3_RX,
- .end = CH_UART3_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sir3_device = {
- .name = "bfin_sir",
- .id = 3,
- .num_resources = ARRAY_SIZE(bfin_sir3_resources),
- .resource = bfin_sir3_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_SMSC911X)
-#include <linux/smsc911x.h>
-
-static struct resource smsc911x_resources[] = {
- {
- .name = "smsc911x-memory",
- .start = 0x24000000,
- .end = 0x24000000 + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PE8,
- .end = IRQ_PE8,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
- },
-};
-
-static struct smsc911x_platform_config smsc911x_config = {
- .flags = SMSC911X_USE_32BIT,
- .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
- .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
- .phy_interface = PHY_INTERFACE_MODE_MII,
-};
-
-static struct platform_device smsc911x_device = {
- .name = "smsc911x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smsc911x_resources),
- .resource = smsc911x_resources,
- .dev = {
- .platform_data = &smsc911x_config,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
-static struct resource musb_resources[] = {
- [0] = {
- .start = 0xFFC03C00,
- .end = 0xFFC040FF,
- .flags = IORESOURCE_MEM,
- },
- [1] = { /* general IRQ */
- .start = IRQ_USB_INT0,
- .end = IRQ_USB_INT0,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- .name = "mc"
- },
- [2] = { /* DMA IRQ */
- .start = IRQ_USB_DMA,
- .end = IRQ_USB_DMA,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- .name = "dma"
- },
-};
-
-static struct musb_hdrc_config musb_config = {
- .multipoint = 0,
- .dyn_fifo = 0,
- .soft_con = 1,
- .dma = 1,
- .num_eps = 8,
- .dma_channels = 8,
- .gpio_vrsel = GPIO_PE7,
- /* Some custom boards need to be active low, just set it to "0"
- * if it is the case.
- */
- .gpio_vrsel_active = 1,
- .clkin = 24, /* musb CLKIN in MHZ */
-};
-
-static struct musb_hdrc_platform_data musb_plat = {
-#if defined(CONFIG_USB_MUSB_HDRC) && defined(CONFIG_USB_GADGET_MUSB_HDRC)
- .mode = MUSB_OTG,
-#elif defined(CONFIG_USB_MUSB_HDRC)
- .mode = MUSB_HOST,
-#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
- .mode = MUSB_PERIPHERAL,
-#endif
- .config = &musb_config,
-};
-
-static u64 musb_dmamask = ~(u32)0;
-
-static struct platform_device musb_device = {
- .name = "musb-blackfin",
- .id = 0,
- .dev = {
- .dma_mask = &musb_dmamask,
- .coherent_dma_mask = 0xffffffff,
- .platform_data = &musb_plat,
- },
- .num_resources = ARRAY_SIZE(musb_resources),
- .resource = musb_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
-static struct resource bfin_sport2_uart_resources[] = {
- {
- .start = SPORT2_TCR1,
- .end = SPORT2_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT2_RX,
- .end = IRQ_SPORT2_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT2_ERROR,
- .end = IRQ_SPORT2_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport2_peripherals[] = {
- P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS,
- P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0
-};
-
-static struct platform_device bfin_sport2_uart_device = {
- .name = "bfin-sport-uart",
- .id = 2,
- .num_resources = ARRAY_SIZE(bfin_sport2_uart_resources),
- .resource = bfin_sport2_uart_resources,
- .dev = {
- .platform_data = &bfin_sport2_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
-static struct resource bfin_sport3_uart_resources[] = {
- {
- .start = SPORT3_TCR1,
- .end = SPORT3_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT3_RX,
- .end = IRQ_SPORT3_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT3_ERROR,
- .end = IRQ_SPORT3_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport3_peripherals[] = {
- P_SPORT3_TFS, P_SPORT3_DTPRI, P_SPORT3_TSCLK, P_SPORT3_RFS,
- P_SPORT3_DRPRI, P_SPORT3_RSCLK, P_SPORT3_DRSEC, P_SPORT3_DTSEC, 0
-};
-
-static struct platform_device bfin_sport3_uart_device = {
- .name = "bfin-sport-uart",
- .id = 3,
- .num_resources = ARRAY_SIZE(bfin_sport3_uart_resources),
- .resource = bfin_sport3_uart_resources,
- .dev = {
- .platform_data = &bfin_sport3_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_CAN_BFIN)
-
-static unsigned short bfin_can0_peripherals[] = {
- P_CAN0_RX, P_CAN0_TX, 0
-};
-
-static struct resource bfin_can0_resources[] = {
- {
- .start = 0xFFC02A00,
- .end = 0xFFC02FFF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_CAN0_RX,
- .end = IRQ_CAN0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_CAN0_TX,
- .end = IRQ_CAN0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_CAN0_ERROR,
- .end = IRQ_CAN0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_can0_device = {
- .name = "bfin_can",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_can0_resources),
- .resource = bfin_can0_resources,
- .dev = {
- .platform_data = &bfin_can0_peripherals, /* Passed to driver */
- },
-};
-
-static unsigned short bfin_can1_peripherals[] = {
- P_CAN1_RX, P_CAN1_TX, 0
-};
-
-static struct resource bfin_can1_resources[] = {
- {
- .start = 0xFFC03200,
- .end = 0xFFC037FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_CAN1_RX,
- .end = IRQ_CAN1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_CAN1_TX,
- .end = IRQ_CAN1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_CAN1_ERROR,
- .end = IRQ_CAN1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_can1_device = {
- .name = "bfin_can",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_can1_resources),
- .resource = bfin_can1_resources,
- .dev = {
- .platform_data = &bfin_can1_peripherals, /* Passed to driver */
- },
-};
-
-#endif
-
-#if IS_ENABLED(CONFIG_PATA_BF54X)
-static struct resource bfin_atapi_resources[] = {
- {
- .start = 0xFFC03800,
- .end = 0xFFC0386F,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_ATAPI_ERR,
- .end = IRQ_ATAPI_ERR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_atapi_device = {
- .name = "pata-bf54x",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_atapi_resources),
- .resource = bfin_atapi_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
-static struct mtd_partition partition_info[] = {
- {
- .name = "bootloader(nand)",
- .offset = 0,
- .size = 0x80000,
- }, {
- .name = "linux kernel(nand)",
- .offset = MTDPART_OFS_APPEND,
- .size = 4 * 1024 * 1024,
- },
- {
- .name = "file system(nand)",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- },
-};
-
-static struct bf5xx_nand_platform bf5xx_nand_platform = {
- .data_width = NFC_NWIDTH_8,
- .partitions = partition_info,
- .nr_partitions = ARRAY_SIZE(partition_info),
- .rd_dly = 3,
- .wr_dly = 3,
-};
-
-static struct resource bf5xx_nand_resources[] = {
- {
- .start = 0xFFC03B00,
- .end = 0xFFC03B4F,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = CH_NFC,
- .end = CH_NFC,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bf5xx_nand_device = {
- .name = "bf5xx-nand",
- .id = 0,
- .num_resources = ARRAY_SIZE(bf5xx_nand_resources),
- .resource = bf5xx_nand_resources,
- .dev = {
- .platform_data = &bf5xx_nand_platform,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SDH_BFIN)
-
-static struct bfin_sd_host bfin_sdh_data = {
- .dma_chan = CH_SDH,
- .irq_int0 = IRQ_SDH_MASK0,
- .pin_req = {P_SD_D0, P_SD_D1, P_SD_D2, P_SD_D3, P_SD_CLK, P_SD_CMD, 0},
-};
-
-static struct platform_device bf54x_sdh_device = {
- .name = "bfin-sdh",
- .id = 0,
- .dev = {
- .platform_data = &bfin_sdh_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
-static struct mtd_partition ezkit_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x80000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0x400000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = 0x1000000 - 0x80000 - 0x400000 - 0x8000 * 4,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "config(nor)",
- .size = 0x8000 * 3,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "u-boot env(nor)",
- .size = 0x8000,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct physmap_flash_data ezkit_flash_data = {
- .width = 2,
- .parts = ezkit_partitions,
- .nr_parts = ARRAY_SIZE(ezkit_partitions),
-};
-
-static struct resource ezkit_flash_resource = {
- .start = 0x20000000,
- .end = 0x21ffffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device ezkit_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &ezkit_flash_data,
- },
- .num_resources = 1,
- .resource = &ezkit_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-/* SPI flash chip (m25p16) */
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00080000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p16",
-};
-
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
-static const struct ad7877_platform_data bfin_ad7877_ts_info = {
- .model = 7877,
- .vref_delay_usecs = 50, /* internal, no capacitor */
- .x_plate_ohms = 419,
- .y_plate_ohms = 486,
- .pressure_max = 1000,
- .pressure_min = 0,
- .stopacq_polarity = 1,
- .first_conversion_delay = 3,
- .acquisition_time = 1,
- .averaging = 1,
- .pen_down_acc_interval = 1,
-};
-#endif
-
-#ifdef CONFIG_PINCTRL_ADI2
-
-# define ADI_PINT_DEVNAME "adi-gpio-pint"
-# define ADI_GPIO_DEVNAME "adi-gpio"
-# define ADI_PINCTRL_DEVNAME "pinctrl-adi2"
-
-static struct platform_device bfin_pinctrl_device = {
- .name = ADI_PINCTRL_DEVNAME,
- .id = 0,
-};
-
-static struct resource bfin_pint0_resources[] = {
- {
- .start = PINT0_MASK_SET,
- .end = PINT0_LATCH + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PINT0,
- .end = IRQ_PINT0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_pint0_device = {
- .name = ADI_PINT_DEVNAME,
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_pint0_resources),
- .resource = bfin_pint0_resources,
-};
-
-static struct resource bfin_pint1_resources[] = {
- {
- .start = PINT1_MASK_SET,
- .end = PINT1_LATCH + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PINT1,
- .end = IRQ_PINT1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_pint1_device = {
- .name = ADI_PINT_DEVNAME,
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_pint1_resources),
- .resource = bfin_pint1_resources,
-};
-
-static struct resource bfin_pint2_resources[] = {
- {
- .start = PINT2_MASK_SET,
- .end = PINT2_LATCH + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PINT2,
- .end = IRQ_PINT2,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_pint2_device = {
- .name = ADI_PINT_DEVNAME,
- .id = 2,
- .num_resources = ARRAY_SIZE(bfin_pint2_resources),
- .resource = bfin_pint2_resources,
-};
-
-static struct resource bfin_pint3_resources[] = {
- {
- .start = PINT3_MASK_SET,
- .end = PINT3_LATCH + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PINT3,
- .end = IRQ_PINT3,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_pint3_device = {
- .name = ADI_PINT_DEVNAME,
- .id = 3,
- .num_resources = ARRAY_SIZE(bfin_pint3_resources),
- .resource = bfin_pint3_resources,
-};
-
-static struct resource bfin_gpa_resources[] = {
- {
- .start = PORTA_FER,
- .end = PORTA_MUX + 3,
- .flags = IORESOURCE_MEM,
- },
- { /* optional */
- .start = IRQ_PA0,
- .end = IRQ_PA0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpa_pdata = {
- .port_gpio_base = GPIO_PA0, /* Optional */
- .port_pin_base = GPIO_PA0,
- .port_width = GPIO_BANKSIZE,
- .pint_id = 0, /* PINT0 */
- .pint_assign = true, /* PINT upper 16 bit */
- .pint_map = 0, /* mapping mask in PINT */
-};
-
-static struct platform_device bfin_gpa_device = {
- .name = ADI_GPIO_DEVNAME,
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_gpa_resources),
- .resource = bfin_gpa_resources,
- .dev = {
- .platform_data = &bfin_gpa_pdata, /* Passed to driver */
- },
-};
-
-static struct resource bfin_gpb_resources[] = {
- {
- .start = PORTB_FER,
- .end = PORTB_MUX + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PB0,
- .end = IRQ_PB0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpb_pdata = {
- .port_gpio_base = GPIO_PB0,
- .port_pin_base = GPIO_PB0,
- .port_width = 15,
- .pint_id = 0,
- .pint_assign = true,
- .pint_map = 1,
-};
-
-static struct platform_device bfin_gpb_device = {
- .name = ADI_GPIO_DEVNAME,
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_gpb_resources),
- .resource = bfin_gpb_resources,
- .dev = {
- .platform_data = &bfin_gpb_pdata, /* Passed to driver */
- },
-};
-
-static struct resource bfin_gpc_resources[] = {
- {
- .start = PORTC_FER,
- .end = PORTC_MUX + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PC0,
- .end = IRQ_PC0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpc_pdata = {
- .port_gpio_base = GPIO_PC0,
- .port_pin_base = GPIO_PC0,
- .port_width = 14,
- .pint_id = 2,
- .pint_assign = true,
- .pint_map = 0,
-};
-
-static struct platform_device bfin_gpc_device = {
- .name = ADI_GPIO_DEVNAME,
- .id = 2,
- .num_resources = ARRAY_SIZE(bfin_gpc_resources),
- .resource = bfin_gpc_resources,
- .dev = {
- .platform_data = &bfin_gpc_pdata, /* Passed to driver */
- },
-};
-
-static struct resource bfin_gpd_resources[] = {
- {
- .start = PORTD_FER,
- .end = PORTD_MUX + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PD0,
- .end = IRQ_PD0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpd_pdata = {
- .port_gpio_base = GPIO_PD0,
- .port_pin_base = GPIO_PD0,
- .port_width = GPIO_BANKSIZE,
- .pint_id = 2,
- .pint_assign = false,
- .pint_map = 1,
-};
-
-static struct platform_device bfin_gpd_device = {
- .name = ADI_GPIO_DEVNAME,
- .id = 3,
- .num_resources = ARRAY_SIZE(bfin_gpd_resources),
- .resource = bfin_gpd_resources,
- .dev = {
- .platform_data = &bfin_gpd_pdata, /* Passed to driver */
- },
-};
-
-static struct resource bfin_gpe_resources[] = {
- {
- .start = PORTE_FER,
- .end = PORTE_MUX + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PE0,
- .end = IRQ_PE0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpe_pdata = {
- .port_gpio_base = GPIO_PE0,
- .port_pin_base = GPIO_PE0,
- .port_width = GPIO_BANKSIZE,
- .pint_id = 3,
- .pint_assign = true,
- .pint_map = 2,
-};
-
-static struct platform_device bfin_gpe_device = {
- .name = ADI_GPIO_DEVNAME,
- .id = 4,
- .num_resources = ARRAY_SIZE(bfin_gpe_resources),
- .resource = bfin_gpe_resources,
- .dev = {
- .platform_data = &bfin_gpe_pdata, /* Passed to driver */
- },
-};
-
-static struct resource bfin_gpf_resources[] = {
- {
- .start = PORTF_FER,
- .end = PORTF_MUX + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PF0,
- .end = IRQ_PF0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpf_pdata = {
- .port_gpio_base = GPIO_PF0,
- .port_pin_base = GPIO_PF0,
- .port_width = GPIO_BANKSIZE,
- .pint_id = 3,
- .pint_assign = false,
- .pint_map = 3,
-};
-
-static struct platform_device bfin_gpf_device = {
- .name = ADI_GPIO_DEVNAME,
- .id = 5,
- .num_resources = ARRAY_SIZE(bfin_gpf_resources),
- .resource = bfin_gpf_resources,
- .dev = {
- .platform_data = &bfin_gpf_pdata, /* Passed to driver */
- },
-};
-
-static struct resource bfin_gpg_resources[] = {
- {
- .start = PORTG_FER,
- .end = PORTG_MUX + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PG0,
- .end = IRQ_PG0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpg_pdata = {
- .port_gpio_base = GPIO_PG0,
- .port_pin_base = GPIO_PG0,
- .port_width = GPIO_BANKSIZE,
- .pint_id = -1,
-};
-
-static struct platform_device bfin_gpg_device = {
- .name = ADI_GPIO_DEVNAME,
- .id = 6,
- .num_resources = ARRAY_SIZE(bfin_gpg_resources),
- .resource = bfin_gpg_resources,
- .dev = {
- .platform_data = &bfin_gpg_pdata, /* Passed to driver */
- },
-};
-
-static struct resource bfin_gph_resources[] = {
- {
- .start = PORTH_FER,
- .end = PORTH_MUX + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PH0,
- .end = IRQ_PH0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gph_pdata = {
- .port_gpio_base = GPIO_PH0,
- .port_pin_base = GPIO_PH0,
- .port_width = 14,
- .pint_id = -1,
-};
-
-static struct platform_device bfin_gph_device = {
- .name = ADI_GPIO_DEVNAME,
- .id = 7,
- .num_resources = ARRAY_SIZE(bfin_gph_resources),
- .resource = bfin_gph_resources,
- .dev = {
- .platform_data = &bfin_gph_pdata, /* Passed to driver */
- },
-};
-
-static struct resource bfin_gpi_resources[] = {
- {
- .start = PORTI_FER,
- .end = PORTI_MUX + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PI0,
- .end = IRQ_PI0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpi_pdata = {
- .port_gpio_base = GPIO_PI0,
- .port_pin_base = GPIO_PI0,
- .port_width = GPIO_BANKSIZE,
- .pint_id = -1,
-};
-
-static struct platform_device bfin_gpi_device = {
- .name = ADI_GPIO_DEVNAME,
- .id = 8,
- .num_resources = ARRAY_SIZE(bfin_gpi_resources),
- .resource = bfin_gpi_resources,
- .dev = {
- .platform_data = &bfin_gpi_pdata, /* Passed to driver */
- },
-};
-
-static struct resource bfin_gpj_resources[] = {
- {
- .start = PORTJ_FER,
- .end = PORTJ_MUX + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PJ0,
- .end = IRQ_PJ0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpj_pdata = {
- .port_gpio_base = GPIO_PJ0,
- .port_pin_base = GPIO_PJ0,
- .port_width = 14,
- .pint_id = -1,
-};
-
-static struct platform_device bfin_gpj_device = {
- .name = ADI_GPIO_DEVNAME,
- .id = 9,
- .num_resources = ARRAY_SIZE(bfin_gpj_resources),
- .resource = bfin_gpj_resources,
- .dev = {
- .platform_data = &bfin_gpj_pdata, /* Passed to driver */
- },
-};
-
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = MAX_CTRL_CS + GPIO_PE4, /* SPI_SSEL1*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
- {
- .modalias = "ad183x",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 1,
- .chip_select = MAX_CTRL_CS + GPIO_PG6, /* SPI_SSEL2 */
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
- {
- .modalias = "ad7877",
- .platform_data = &bfin_ad7877_ts_info,
- .irq = IRQ_PB4, /* old boards (<=Rev 1.3) use IRQ_PJ11 */
- .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = MAX_CTRL_CS + GPIO_PE5, /* SPI_SSEL2 */
- },
-#endif
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = MAX_CTRL_CS + GPIO_PE4, /* SPI_SSEL1 */
- },
-#endif
-#if IS_ENABLED(CONFIG_INPUT_ADXL34X_SPI)
- {
- .modalias = "adxl34x",
- .platform_data = &adxl34x_info,
- .irq = IRQ_PC5,
- .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 1,
- .chip_select = MAX_CTRL_CS + GPIO_PG6, /* SPI_SSEL2 */
- .mode = SPI_MODE_3,
- },
-#endif
-};
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI0,
- .end = CH_SPI0,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI0,
- .end = IRQ_SPI0,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-/* SPI (1) */
-static struct resource bfin_spi1_resource[] = {
- [0] = {
- .start = SPI1_REGBASE,
- .end = SPI1_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI1,
- .end = CH_SPI1,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI1,
- .end = IRQ_SPI1,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-/* SPI controller data */
-static struct bfin5xx_spi_master bf54x_spi_master_info0 = {
- .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct platform_device bf54x_spi_master0 = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bf54x_spi_master_info0, /* Passed to driver */
- },
-};
-
-static struct bfin5xx_spi_master bf54x_spi_master_info1 = {
- .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
-};
-
-static struct platform_device bf54x_spi_master1 = {
- .name = "bfin-spi",
- .id = 1, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi1_resource),
- .resource = bfin_spi1_resource,
- .dev = {
- .platform_data = &bf54x_spi_master_info1, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_CAPTURE)
-#include <linux/videodev2.h>
-#include <media/blackfin/bfin_capture.h>
-#include <media/blackfin/ppi.h>
-
-static const unsigned short ppi_req[] = {
- P_PPI1_D0, P_PPI1_D1, P_PPI1_D2, P_PPI1_D3,
- P_PPI1_D4, P_PPI1_D5, P_PPI1_D6, P_PPI1_D7,
- P_PPI1_CLK, P_PPI1_FS1, P_PPI1_FS2,
- 0,
-};
-
-static const struct ppi_info ppi_info = {
- .type = PPI_TYPE_EPPI,
- .dma_ch = CH_EPPI1,
- .irq_err = IRQ_EPPI1_ERROR,
- .base = (void __iomem *)EPPI1_STATUS,
- .pin_req = ppi_req,
-};
-
-#if IS_ENABLED(CONFIG_VIDEO_VS6624)
-static struct v4l2_input vs6624_inputs[] = {
- {
- .index = 0,
- .name = "Camera",
- .type = V4L2_INPUT_TYPE_CAMERA,
- .std = V4L2_STD_UNKNOWN,
- },
-};
-
-static struct bcap_route vs6624_routes[] = {
- {
- .input = 0,
- .output = 0,
- },
-};
-
-static const unsigned vs6624_ce_pin = GPIO_PG6;
-
-static struct bfin_capture_config bfin_capture_data = {
- .card_name = "BF548",
- .inputs = vs6624_inputs,
- .num_inputs = ARRAY_SIZE(vs6624_inputs),
- .routes = vs6624_routes,
- .i2c_adapter_id = 0,
- .board_info = {
- .type = "vs6624",
- .addr = 0x10,
- .platform_data = (void *)&vs6624_ce_pin,
- },
- .ppi_info = &ppi_info,
- .ppi_control = (POLC | PACKEN | DLEN_8 | XFR_TYPE | 0x20),
- .int_mask = 0xFFFFFFFF, /* disable error interrupt on eppi */
- .blank_clocks = 8, /* 8 clocks as SAV and EAV */
-};
-#endif
-
-static struct platform_device bfin_capture_device = {
- .name = "bfin_capture",
- .dev = {
- .platform_data = &bfin_capture_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_REGBASE,
- .end = TWI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI0,
- .end = IRQ_TWI0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi0_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-
-#if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */
-static const u16 bfin_twi1_pins[] = {P_TWI1_SCL, P_TWI1_SDA, 0};
-
-static struct resource bfin_twi1_resource[] = {
- [0] = {
- .start = TWI1_REGBASE,
- .end = TWI1_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI1,
- .end = IRQ_TWI1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi1_device = {
- .name = "i2c-bfin-twi",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_twi1_resource),
- .resource = bfin_twi1_resource,
- .dev = {
- .platform_data = &bfin_twi1_pins,
- },
-};
-#endif
-#endif
-
-static struct i2c_board_info __initdata bfin_i2c_board_info0[] = {
-#if IS_ENABLED(CONFIG_SND_SOC_SSM2602)
- {
- I2C_BOARD_INFO("ssm2602", 0x1b),
- },
-#endif
-};
-
-#if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */
-static struct i2c_board_info __initdata bfin_i2c_board_info1[] = {
-#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
- {
- I2C_BOARD_INFO("pcf8574_lcd", 0x22),
- },
-#endif
-#if IS_ENABLED(CONFIG_INPUT_PCF8574)
- {
- I2C_BOARD_INFO("pcf8574_keypad", 0x27),
- .irq = 212,
- },
-#endif
-#if IS_ENABLED(CONFIG_INPUT_ADXL34X_I2C)
- {
- I2C_BOARD_INFO("adxl34x", 0x53),
- .irq = IRQ_PC5,
- .platform_data = (void *)&adxl34x_info,
- },
-#endif
-#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
- {
- I2C_BOARD_INFO("ad5252", 0x2f),
- },
-#endif
-};
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
-#include <linux/gpio_keys.h>
-
-static struct gpio_keys_button bfin_gpio_keys_table[] = {
- {BTN_0, GPIO_PB8, 1, "gpio-keys: BTN0"},
- {BTN_1, GPIO_PB9, 1, "gpio-keys: BTN1"},
- {BTN_2, GPIO_PB10, 1, "gpio-keys: BTN2"},
- {BTN_3, GPIO_PB11, 1, "gpio-keys: BTN3"},
-};
-
-static struct gpio_keys_platform_data bfin_gpio_keys_data = {
- .buttons = bfin_gpio_keys_table,
- .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
-};
-
-static struct platform_device bfin_device_gpiokeys = {
- .name = "gpio-keys",
- .dev = {
- .platform_data = &bfin_gpio_keys_data,
- },
-};
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
-/*
- * Internal VLEV BF54XSBBC1533
- ****temporarily using these values until data sheet is updated
- */
- VRPAIR(VLEV_085, 150000000),
- VRPAIR(VLEV_090, 250000000),
- VRPAIR(VLEV_110, 276000000),
- VRPAIR(VLEV_115, 301000000),
- VRPAIR(VLEV_120, 525000000),
- VRPAIR(VLEV_125, 550000000),
- VRPAIR(VLEV_130, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S) || \
- IS_ENABLED(CONFIG_SND_BF5XX_AC97)
-
-#define SPORT_REQ(x) \
- [x] = {P_SPORT##x##_TFS, P_SPORT##x##_DTPRI, P_SPORT##x##_TSCLK, \
- P_SPORT##x##_RFS, P_SPORT##x##_DRPRI, P_SPORT##x##_RSCLK, 0}
-
-static const u16 bfin_snd_pin[][7] = {
- SPORT_REQ(0),
- SPORT_REQ(1),
- SPORT_REQ(2),
- SPORT_REQ(3),
-};
-
-static struct bfin_snd_platform_data bfin_snd_data[] = {
- {
- .pin_req = &bfin_snd_pin[0][0],
- },
- {
- .pin_req = &bfin_snd_pin[1][0],
- },
- {
- .pin_req = &bfin_snd_pin[2][0],
- },
- {
- .pin_req = &bfin_snd_pin[3][0],
- },
-};
-
-#define BFIN_SND_RES(x) \
- [x] = { \
- { \
- .start = SPORT##x##_TCR1, \
- .end = SPORT##x##_TCR1, \
- .flags = IORESOURCE_MEM \
- }, \
- { \
- .start = CH_SPORT##x##_RX, \
- .end = CH_SPORT##x##_RX, \
- .flags = IORESOURCE_DMA, \
- }, \
- { \
- .start = CH_SPORT##x##_TX, \
- .end = CH_SPORT##x##_TX, \
- .flags = IORESOURCE_DMA, \
- }, \
- { \
- .start = IRQ_SPORT##x##_ERROR, \
- .end = IRQ_SPORT##x##_ERROR, \
- .flags = IORESOURCE_IRQ, \
- } \
- }
-
-static struct resource bfin_snd_resources[][4] = {
- BFIN_SND_RES(0),
- BFIN_SND_RES(1),
- BFIN_SND_RES(2),
- BFIN_SND_RES(3),
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
-static struct platform_device bfin_i2s_pcm = {
- .name = "bfin-i2s-pcm-audio",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
-static struct platform_device bfin_ac97_pcm = {
- .name = "bfin-ac97-pcm-audio",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD73311)
-static struct platform_device bfin_ad73311_codec_device = {
- .name = "ad73311",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1980)
-static struct platform_device bfin_ad1980_codec_device = {
- .name = "ad1980",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_I2S)
-static struct platform_device bfin_i2s = {
- .name = "bfin-i2s",
- .id = CONFIG_SND_BF5XX_SPORT_NUM,
- .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
- .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
- .dev = {
- .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AC97)
-static struct platform_device bfin_ac97 = {
- .name = "bfin-ac97",
- .id = CONFIG_SND_BF5XX_SPORT_NUM,
- .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
- .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
- .dev = {
- .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
- },
-};
-#endif
-
-static struct platform_device *ezkit_devices[] __initdata = {
-
- &bfin_dpmc,
-#if defined(CONFIG_PINCTRL_ADI2)
- &bfin_pinctrl_device,
- &bfin_pint0_device,
- &bfin_pint1_device,
- &bfin_pint2_device,
- &bfin_pint3_device,
- &bfin_gpa_device,
- &bfin_gpb_device,
- &bfin_gpc_device,
- &bfin_gpd_device,
- &bfin_gpe_device,
- &bfin_gpf_device,
- &bfin_gpg_device,
- &bfin_gph_device,
- &bfin_gpi_device,
- &bfin_gpj_device,
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART2
- &bfin_uart2_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART3
- &bfin_uart3_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#ifdef CONFIG_BFIN_SIR2
- &bfin_sir2_device,
-#endif
-#ifdef CONFIG_BFIN_SIR3
- &bfin_sir3_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BF54X_LQ043)
- &bf54x_lq043_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SMSC911X)
- &smsc911x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
- &musb_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
- &bfin_isp1760_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
- &bfin_sport2_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
- &bfin_sport3_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_CAN_BFIN)
- &bfin_can0_device,
- &bfin_can1_device,
-#endif
-
-#if IS_ENABLED(CONFIG_PATA_BF54X)
- &bfin_atapi_device,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
- &bf5xx_nand_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SDH_BFIN)
- &bf54x_sdh_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bf54x_spi_master0,
- &bf54x_spi_master1,
-#endif
-#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_CAPTURE)
- &bfin_capture_device,
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_BFIN)
- &bf54x_kpad_device,
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_BFIN_ROTARY)
- &bfin_rotary_device,
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi0_device,
-#if !defined(CONFIG_BF542)
- &i2c_bfin_twi1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
- &bfin_device_gpiokeys,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
- &ezkit_flash_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
- &bfin_i2s_pcm,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
- &bfin_ac97_pcm,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1980)
- &bfin_ad1980_codec_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
- &bfin_i2s,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
- &bfin_ac97,
-#endif
-};
-
-/* Pin control settings */
-static struct pinctrl_map __initdata bfin_pinmux_map[] = {
- /* per-device maps */
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.0", "pinctrl-adi2.0", NULL, "uart0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.1", "pinctrl-adi2.0", NULL, "uart1"),
-#ifdef CONFIG_BFIN_UART1_CTSRTS
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.1", "pinctrl-adi2.0", NULL, "uart1_ctsrts"),
-#endif
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.2", "pinctrl-adi2.0", NULL, "uart2"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.3", "pinctrl-adi2.0", NULL, "uart3"),
-#ifdef CONFIG_BFIN_UART3_CTSRTS
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.3", "pinctrl-adi2.0", NULL, "uart3_ctsrts"),
-#endif
- PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.0", "pinctrl-adi2.0", NULL, "uart0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.1", "pinctrl-adi2.0", NULL, "uart1"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.2", "pinctrl-adi2.0", NULL, "uart2"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.3", "pinctrl-adi2.0", NULL, "uart3"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-sdh.0", "pinctrl-adi2.0", NULL, "rsi0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-spi.0", "pinctrl-adi2.0", NULL, "spi0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-spi.1", "pinctrl-adi2.0", NULL, "spi1"),
- PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.0", "pinctrl-adi2.0", NULL, "twi0"),
-#if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */
- PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.1", "pinctrl-adi2.0", NULL, "twi1"),
-#endif
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-rotary", "pinctrl-adi2.0", NULL, "rotary"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin_can.0", "pinctrl-adi2.0", NULL, "can0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin_can.1", "pinctrl-adi2.0", NULL, "can1"),
- PIN_MAP_MUX_GROUP_DEFAULT("bf54x-lq043", "pinctrl-adi2.0", "ppi0_24bgrp", "ppi0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.0", "pinctrl-adi2.0", NULL, "sport0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.0", "pinctrl-adi2.0", NULL, "sport0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-ac97.0", "pinctrl-adi2.0", NULL, "sport0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.1", "pinctrl-adi2.0", NULL, "sport1"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.1", "pinctrl-adi2.0", NULL, "sport1"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-ac97.1", "pinctrl-adi2.0", NULL, "sport1"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.2", "pinctrl-adi2.0", NULL, "sport2"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.2", "pinctrl-adi2.0", NULL, "sport2"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-ac97.2", "pinctrl-adi2.0", NULL, "sport2"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.3", "pinctrl-adi2.0", NULL, "sport3"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.3", "pinctrl-adi2.0", NULL, "sport3"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-ac97.3", "pinctrl-adi2.0", NULL, "sport3"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-sport-uart.0", "pinctrl-adi2.0", NULL, "sport0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-sport-uart.1", "pinctrl-adi2.0", NULL, "sport1"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-sport-uart.2", "pinctrl-adi2.0", NULL, "sport2"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-sport-uart.3", "pinctrl-adi2.0", NULL, "sport3"),
- PIN_MAP_MUX_GROUP_DEFAULT("pata-bf54x", "pinctrl-adi2.0", NULL, "atapi"),
-#ifdef CONFIG_BF548_ATAPI_ALTERNATIVE_PORT
- PIN_MAP_MUX_GROUP_DEFAULT("pata-bf54x", "pinctrl-adi2.0", NULL, "atapi_alter"),
-#endif
- PIN_MAP_MUX_GROUP_DEFAULT("bf5xx-nand.0", "pinctrl-adi2.0", NULL, "nfc0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bf54x-keys", "pinctrl-adi2.0", "keys_4x4grp", "keys"),
- PIN_MAP_MUX_GROUP("bf54x-keys", "4bit", "pinctrl-adi2.0", "keys_4x4grp", "keys"),
- PIN_MAP_MUX_GROUP("bf54x-keys", "8bit", "pinctrl-adi2.0", "keys_8x8grp", "keys"),
-};
-
-static int __init ezkit_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
-
- /* Initialize pinmuxing */
- pinctrl_register_mappings(bfin_pinmux_map,
- ARRAY_SIZE(bfin_pinmux_map));
-
- i2c_register_board_info(0, bfin_i2c_board_info0,
- ARRAY_SIZE(bfin_i2c_board_info0));
-#if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */
- i2c_register_board_info(1, bfin_i2c_board_info1,
- ARRAY_SIZE(bfin_i2c_board_info1));
-#endif
-
- platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices));
-
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
-
- return 0;
-}
-
-arch_initcall(ezkit_init);
-
-static struct platform_device *ezkit_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART2
- &bfin_uart2_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART3
- &bfin_uart3_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(ezkit_early_devices,
- ARRAY_SIZE(ezkit_early_devices));
-}
+++ /dev/null
-/*
- * the simple DMA Implementation for Blackfin
- *
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-
-#include <asm/blackfin.h>
-#include <asm/dma.h>
-
-struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
- (struct dma_register *) DMA0_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_NEXT_DESC_PTR,
- (struct dma_register *) DMA3_NEXT_DESC_PTR,
- (struct dma_register *) DMA4_NEXT_DESC_PTR,
- (struct dma_register *) DMA5_NEXT_DESC_PTR,
- (struct dma_register *) DMA6_NEXT_DESC_PTR,
- (struct dma_register *) DMA7_NEXT_DESC_PTR,
- (struct dma_register *) DMA8_NEXT_DESC_PTR,
- (struct dma_register *) DMA9_NEXT_DESC_PTR,
- (struct dma_register *) DMA10_NEXT_DESC_PTR,
- (struct dma_register *) DMA11_NEXT_DESC_PTR,
- (struct dma_register *) DMA12_NEXT_DESC_PTR,
- (struct dma_register *) DMA13_NEXT_DESC_PTR,
- (struct dma_register *) DMA14_NEXT_DESC_PTR,
- (struct dma_register *) DMA15_NEXT_DESC_PTR,
- (struct dma_register *) DMA16_NEXT_DESC_PTR,
- (struct dma_register *) DMA17_NEXT_DESC_PTR,
- (struct dma_register *) DMA18_NEXT_DESC_PTR,
- (struct dma_register *) DMA19_NEXT_DESC_PTR,
- (struct dma_register *) DMA20_NEXT_DESC_PTR,
- (struct dma_register *) DMA21_NEXT_DESC_PTR,
- (struct dma_register *) DMA22_NEXT_DESC_PTR,
- (struct dma_register *) DMA23_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D2_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S2_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D3_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S3_NEXT_DESC_PTR,
-};
-EXPORT_SYMBOL(dma_io_base_addr);
-
-int channel2irq(unsigned int channel)
-{
- int ret_irq = -1;
-
- switch (channel) {
- case CH_SPORT0_RX:
- ret_irq = IRQ_SPORT0_RX;
- break;
- case CH_SPORT0_TX:
- ret_irq = IRQ_SPORT0_TX;
- break;
- case CH_SPORT1_RX:
- ret_irq = IRQ_SPORT1_RX;
- break;
- case CH_SPORT1_TX:
- ret_irq = IRQ_SPORT1_TX;
- break;
- case CH_SPI0:
- ret_irq = IRQ_SPI0;
- break;
- case CH_SPI1:
- ret_irq = IRQ_SPI1;
- break;
- case CH_UART0_RX:
- ret_irq = IRQ_UART0_RX;
- break;
- case CH_UART0_TX:
- ret_irq = IRQ_UART0_TX;
- break;
- case CH_UART1_RX:
- ret_irq = IRQ_UART1_RX;
- break;
- case CH_UART1_TX:
- ret_irq = IRQ_UART1_TX;
- break;
- case CH_EPPI0:
- ret_irq = IRQ_EPPI0;
- break;
- case CH_EPPI1:
- ret_irq = IRQ_EPPI1;
- break;
- case CH_EPPI2:
- ret_irq = IRQ_EPPI2;
- break;
- case CH_PIXC_IMAGE:
- ret_irq = IRQ_PIXC_IN0;
- break;
- case CH_PIXC_OVERLAY:
- ret_irq = IRQ_PIXC_IN1;
- break;
- case CH_PIXC_OUTPUT:
- ret_irq = IRQ_PIXC_OUT;
- break;
- case CH_SPORT2_RX:
- ret_irq = IRQ_SPORT2_RX;
- break;
- case CH_SPORT2_TX:
- ret_irq = IRQ_SPORT2_TX;
- break;
- case CH_SPORT3_RX:
- ret_irq = IRQ_SPORT3_RX;
- break;
- case CH_SPORT3_TX:
- ret_irq = IRQ_SPORT3_TX;
- break;
- case CH_SDH:
- ret_irq = IRQ_SDH;
- break;
- case CH_SPI2:
- ret_irq = IRQ_SPI2;
- break;
- case CH_MEM_STREAM0_SRC:
- case CH_MEM_STREAM0_DEST:
- ret_irq = IRQ_MDMAS0;
- break;
- case CH_MEM_STREAM1_SRC:
- case CH_MEM_STREAM1_DEST:
- ret_irq = IRQ_MDMAS1;
- break;
- case CH_MEM_STREAM2_SRC:
- case CH_MEM_STREAM2_DEST:
- ret_irq = IRQ_MDMAS2;
- break;
- case CH_MEM_STREAM3_SRC:
- case CH_MEM_STREAM3_DEST:
- ret_irq = IRQ_MDMAS3;
- break;
- }
- return ret_irq;
-}
+++ /dev/null
-/*
- * DO NOT EDIT THIS FILE
- * This file is under version control at
- * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
- * and can be replaced with that version at any time
- * DO NOT EDIT THIS FILE
- *
- * Copyright 2004-2011 Analog Devices Inc.
- * Licensed under the Clear BSD license.
- */
-
-/* This file should be up to date with:
- * - Revision K, 05/23/2011; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
- */
-
-#ifndef _MACH_ANOMALY_H_
-#define _MACH_ANOMALY_H_
-
-/* We do not support 0.0 or 0.1 silicon - sorry */
-#if __SILICON_REVISION__ < 2
-# error will not work on BF548 silicon version 0.0, or 0.1
-#endif
-
-/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
-#define ANOMALY_05000074 (1)
-/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
-#define ANOMALY_05000119 (1)
-/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
-#define ANOMALY_05000122 (1)
-/* Data Corruption/Core Hang with L2/L3 Configured in Writeback Cache Mode */
-#define ANOMALY_05000220 (__SILICON_REVISION__ < 4)
-/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
-#define ANOMALY_05000245 (1)
-/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
-#define ANOMALY_05000265 (1)
-/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
-#define ANOMALY_05000272 (1)
-/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
-#define ANOMALY_05000310 (1)
-/* FIFO Boot Mode Not Functional */
-#define ANOMALY_05000325 (__SILICON_REVISION__ < 2)
-/* bfrom_SysControl() Firmware Function Performs Improper System Reset */
-/*
- * Note: anomaly sheet says this is fixed with bf54x-0.2+, but testing
- * shows that the fix itself does not cover all cases.
- */
-#define ANOMALY_05000353 (1)
-/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
-#define ANOMALY_05000357 (1)
-/* External Memory Read Access Hangs Core With PLL Bypass */
-#define ANOMALY_05000360 (1)
-/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
-#define ANOMALY_05000365 (1)
-/* Addressing Conflict between Boot ROM and Asynchronous Memory */
-#define ANOMALY_05000369 (1)
-/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
-#define ANOMALY_05000371 (__SILICON_REVISION__ < 2)
-/* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */
-#define ANOMALY_05000378 (__SILICON_REVISION__ < 2)
-/* 16-Bit NAND FLASH Boot Mode Is Not Functional */
-#define ANOMALY_05000379 (1)
-/* Lockbox SESR Disallows Certain User Interrupts */
-#define ANOMALY_05000404 (__SILICON_REVISION__ < 2)
-/* Lockbox SESR Firmware Does Not Save/Restore Full Context */
-#define ANOMALY_05000405 (1)
-/* Lockbox SESR Argument Checking Does Not Check L2 Memory Protection Range */
-#define ANOMALY_05000406 (__SILICON_REVISION__ < 2)
-/* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */
-#define ANOMALY_05000407 (__SILICON_REVISION__ < 2)
-/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
-#define ANOMALY_05000408 (1)
-/* Lockbox firmware leaves MDMA0 channel enabled */
-#define ANOMALY_05000409 (__SILICON_REVISION__ < 2)
-/* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */
-#define ANOMALY_05000411 (__SILICON_REVISION__ < 2)
-/* NAND Boot Mode Not Compatible With Some NAND Flash Devices */
-#define ANOMALY_05000413 (__SILICON_REVISION__ < 2)
-/* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */
-#define ANOMALY_05000414 (__SILICON_REVISION__ < 2)
-/* Speculative Fetches Can Cause Undesired External FIFO Operations */
-#define ANOMALY_05000416 (1)
-/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
-#define ANOMALY_05000425 (__SILICON_REVISION__ < 4)
-/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
-#define ANOMALY_05000426 (1)
-/* CORE_EPPI_PRIO bit and SYS_EPPI_PRIO bit in the HMDMA1_CONTROL register are not functional */
-#define ANOMALY_05000427 (__SILICON_REVISION__ < 2)
-/* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Reflects Buffer Status Instead of IRQ Status */
-#define ANOMALY_05000429 (__SILICON_REVISION__ < 2)
-/* Software System Reset Corrupts PLL_LOCKCNT Register */
-#define ANOMALY_05000430 (__SILICON_REVISION__ >= 2)
-/* Incorrect Use of Stack in Lockbox Firmware During Authentication */
-#define ANOMALY_05000431 (__SILICON_REVISION__ < 3)
-/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */
-#define ANOMALY_05000434 (1)
-/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
-#define ANOMALY_05000443 (1)
-/* CDMAPRIO and L2DMAPRIO Bits in the SYSCR Register Are Not Functional */
-#define ANOMALY_05000446 (1)
-/* UART IrDA Receiver Fails on Extended Bit Pulses */
-#define ANOMALY_05000447 (1)
-/* DDR Clock Duty Cycle Spec Violation (tCH, tCL) */
-#define ANOMALY_05000448 (__SILICON_REVISION__ == 1)
-/* Reduced Timing Margins on DDR Output Setup and Hold (tDS and tDH) */
-#define ANOMALY_05000449 (__SILICON_REVISION__ == 1)
-/* USB DMA Short Packet Data Corruption */
-#define ANOMALY_05000450 (1)
-/* USB Receive Interrupt Is Not Generated in DMA Mode 1 */
-#define ANOMALY_05000456 (1)
-/* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */
-#define ANOMALY_05000457 (1)
-/* USB DMA Mode 1 Failure When Multiple USB DMA Channels Are Concurrently Enabled */
-#define ANOMALY_05000460 (__SILICON_REVISION__ < 4)
-/* False Hardware Error when RETI Points to Invalid Memory */
-#define ANOMALY_05000461 (1)
-/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
-#define ANOMALY_05000462 (__SILICON_REVISION__ < 4)
-/* USB DMA RX Data Corruption */
-#define ANOMALY_05000463 (__SILICON_REVISION__ < 4)
-/* USB TX DMA Hang */
-#define ANOMALY_05000464 (__SILICON_REVISION__ < 4)
-/* USB Rx DMA Hang */
-#define ANOMALY_05000465 (1)
-/* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */
-#define ANOMALY_05000466 (__SILICON_REVISION__ < 4)
-/* Possible USB RX Data Corruption When Control & Data EP FIFOs are Accessed via the Core */
-#define ANOMALY_05000467 (__SILICON_REVISION__ < 4)
-/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
-#define ANOMALY_05000473 (1)
-/* Access to DDR SDRAM Causes System Hang with Certain PLL Settings */
-#define ANOMALY_05000474 (__SILICON_REVISION__ < 4)
-/* TESTSET Instruction Cannot Be Interrupted */
-#define ANOMALY_05000477 (1)
-/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
-#define ANOMALY_05000481 (1)
-/* Possible USB Data Corruption When Multiple Endpoints Are Accessed by the Core */
-#define ANOMALY_05000483 (1)
-/* DDR Trim May Not Be Performed for Certain VLEV Values in OTP Page PBS00L */
-#define ANOMALY_05000484 (__SILICON_REVISION__ < 3)
-/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
-#define ANOMALY_05000485 (__SILICON_REVISION__ > 1 && __SILICON_REVISION__ < 4)
-/* PLL May Latch Incorrect Values Coming Out of Reset */
-#define ANOMALY_05000489 (1)
-/* SPI Master Boot Can Fail Under Certain Conditions */
-#define ANOMALY_05000490 (1)
-/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
-#define ANOMALY_05000491 (1)
-/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
-#define ANOMALY_05000494 (1)
-/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */
-#define ANOMALY_05000498 (1)
-/* Nand Flash Controller Hangs When the AMC Requests the Async Pins During the last 16 Bytes of a Page Write Operation. */
-#define ANOMALY_05000500 (1)
-/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
-#define ANOMALY_05000501 (1)
-/* Async Memory Writes May Be Skipped When Using Odd Clock Ratios */
-#define ANOMALY_05000502 (1)
-
-/*
- * These anomalies have been "phased" out of analog.com anomaly sheets and are
- * here to show running on older silicon just isn't feasible.
- */
-
-/* False Hardware Error when ISR Context Is Not Restored */
-#define ANOMALY_05000281 (__SILICON_REVISION__ < 1)
-/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
-#define ANOMALY_05000304 (__SILICON_REVISION__ < 1)
-/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
-#define ANOMALY_05000312 (__SILICON_REVISION__ < 1)
-/* TWI Slave Boot Mode Is Not Functional */
-#define ANOMALY_05000324 (__SILICON_REVISION__ < 1)
-/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */
-#define ANOMALY_05000327 (__SILICON_REVISION__ < 1)
-/* Incorrect Access of OTP_STATUS During otp_write() Function */
-#define ANOMALY_05000328 (__SILICON_REVISION__ < 1)
-/* Synchronous Burst Flash Boot Mode Is Not Functional */
-#define ANOMALY_05000329 (__SILICON_REVISION__ < 1)
-/* Host DMA Boot Modes Are Not Functional */
-#define ANOMALY_05000330 (__SILICON_REVISION__ < 1)
-/* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */
-#define ANOMALY_05000334 (__SILICON_REVISION__ < 1)
-/* Inadequate Rotary Debounce Logic Duration */
-#define ANOMALY_05000335 (__SILICON_REVISION__ < 1)
-/* Phantom Interrupt Occurs After First Configuration of Host DMA Port */
-#define ANOMALY_05000336 (__SILICON_REVISION__ < 1)
-/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
-#define ANOMALY_05000337 (__SILICON_REVISION__ < 1)
-/* Slave-Mode SPI0 MISO Failure With CPHA = 0 */
-#define ANOMALY_05000338 (__SILICON_REVISION__ < 1)
-/* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */
-#define ANOMALY_05000340 (__SILICON_REVISION__ < 1)
-/* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */
-#define ANOMALY_05000344 (__SILICON_REVISION__ < 1)
-/* USB Calibration Value Is Not Initialized */
-#define ANOMALY_05000346 (__SILICON_REVISION__ < 1)
-/* USB Calibration Value to use */
-#define ANOMALY_05000346_value 0x5411
-/* Preboot Routine Incorrectly Alters Reset Value of USB Register */
-#define ANOMALY_05000347 (__SILICON_REVISION__ < 1)
-/* Data Lost when Core Reads SDH Data FIFO */
-#define ANOMALY_05000349 (__SILICON_REVISION__ < 1)
-/* PLL Status Register Is Inaccurate */
-#define ANOMALY_05000351 (__SILICON_REVISION__ < 1)
-/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
-#define ANOMALY_05000355 (__SILICON_REVISION__ < 1)
-/* System Stalled During A Core Access To AMC While A Core Access To NFC FIFO Is Required */
-#define ANOMALY_05000356 (__SILICON_REVISION__ < 1)
-/* WURESET Bit In SYSCR Register Does Not Properly Indicate Hibernate Wake-Up */
-#define ANOMALY_05000367 (__SILICON_REVISION__ < 1)
-/* Default PLL MSEL and SSEL Settings Can Cause 400MHz Product To Violate Specifications */
-#define ANOMALY_05000370 (__SILICON_REVISION__ < 1)
-/* USB DP/DM Data Pins May Lose State When Entering Hibernate */
-#define ANOMALY_05000372 (__SILICON_REVISION__ < 1)
-/* 8-Bit NAND Flash Boot Mode Not Functional */
-#define ANOMALY_05000382 (__SILICON_REVISION__ < 1)
-/* Boot from OTP Memory Not Functional */
-#define ANOMALY_05000385 (__SILICON_REVISION__ < 1)
-/* bfrom_SysControl() Firmware Routine Not Functional */
-#define ANOMALY_05000386 (__SILICON_REVISION__ < 1)
-/* Programmable Preboot Settings Not Functional */
-#define ANOMALY_05000387 (__SILICON_REVISION__ < 1)
-/* CRC32 Checksum Support Not Functional */
-#define ANOMALY_05000388 (__SILICON_REVISION__ < 1)
-/* Reset Vector Must Not Be in SDRAM Memory Space */
-#define ANOMALY_05000389 (__SILICON_REVISION__ < 1)
-/* Changed Meaning of BCODE Field in SYSCR Register */
-#define ANOMALY_05000390 (__SILICON_REVISION__ < 1)
-/* Repeated Boot from Page-Mode or Burst-Mode Flash Memory May Fail */
-#define ANOMALY_05000391 (__SILICON_REVISION__ < 1)
-/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */
-#define ANOMALY_05000392 (__SILICON_REVISION__ < 1)
-/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */
-#define ANOMALY_05000393 (__SILICON_REVISION__ < 1)
-/* Log Buffer Not Functional */
-#define ANOMALY_05000394 (__SILICON_REVISION__ < 1)
-/* Hook Routine Not Functional */
-#define ANOMALY_05000395 (__SILICON_REVISION__ < 1)
-/* Header Indirect Bit Not Functional */
-#define ANOMALY_05000396 (__SILICON_REVISION__ < 1)
-/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */
-#define ANOMALY_05000397 (__SILICON_REVISION__ < 1)
-/* OTP Write Accesses Not Supported */
-#define ANOMALY_05000442 (__SILICON_REVISION__ < 1)
-/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
-#define ANOMALY_05000452 (__SILICON_REVISION__ < 1)
-
-/* Anomalies that don't exist on this proc */
-#define ANOMALY_05000099 (0)
-#define ANOMALY_05000120 (0)
-#define ANOMALY_05000125 (0)
-#define ANOMALY_05000149 (0)
-#define ANOMALY_05000158 (0)
-#define ANOMALY_05000171 (0)
-#define ANOMALY_05000179 (0)
-#define ANOMALY_05000182 (0)
-#define ANOMALY_05000183 (0)
-#define ANOMALY_05000189 (0)
-#define ANOMALY_05000198 (0)
-#define ANOMALY_05000202 (0)
-#define ANOMALY_05000215 (0)
-#define ANOMALY_05000219 (0)
-#define ANOMALY_05000227 (0)
-#define ANOMALY_05000230 (0)
-#define ANOMALY_05000231 (0)
-#define ANOMALY_05000233 (0)
-#define ANOMALY_05000234 (0)
-#define ANOMALY_05000242 (0)
-#define ANOMALY_05000244 (0)
-#define ANOMALY_05000248 (0)
-#define ANOMALY_05000250 (0)
-#define ANOMALY_05000254 (0)
-#define ANOMALY_05000257 (0)
-#define ANOMALY_05000261 (0)
-#define ANOMALY_05000263 (0)
-#define ANOMALY_05000266 (0)
-#define ANOMALY_05000273 (0)
-#define ANOMALY_05000274 (0)
-#define ANOMALY_05000278 (0)
-#define ANOMALY_05000283 (0)
-#define ANOMALY_05000287 (0)
-#define ANOMALY_05000301 (0)
-#define ANOMALY_05000305 (0)
-#define ANOMALY_05000307 (0)
-#define ANOMALY_05000311 (0)
-#define ANOMALY_05000315 (0)
-#define ANOMALY_05000323 (0)
-#define ANOMALY_05000362 (1)
-#define ANOMALY_05000363 (0)
-#define ANOMALY_05000364 (0)
-#define ANOMALY_05000380 (0)
-#define ANOMALY_05000400 (0)
-#define ANOMALY_05000402 (0)
-#define ANOMALY_05000412 (0)
-#define ANOMALY_05000432 (0)
-#define ANOMALY_05000435 (0)
-#define ANOMALY_05000440 (0)
-#define ANOMALY_05000475 (0)
-#define ANOMALY_05000480 (0)
-#define ANOMALY_16000030 (0)
-
-#endif
+++ /dev/null
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __MACH_BF548_H__
-#define __MACH_BF548_H__
-
-#define OFFSET_(x) ((x) & 0x0000FFFF)
-
-/*some misc defines*/
-#define IMASK_IVG15 0x8000
-#define IMASK_IVG14 0x4000
-#define IMASK_IVG13 0x2000
-#define IMASK_IVG12 0x1000
-
-#define IMASK_IVG11 0x0800
-#define IMASK_IVG10 0x0400
-#define IMASK_IVG9 0x0200
-#define IMASK_IVG8 0x0100
-
-#define IMASK_IVG7 0x0080
-#define IMASK_IVGTMR 0x0040
-#define IMASK_IVGHW 0x0020
-
-/***************************/
-
-
-#define BFIN_DSUBBANKS 4
-#define BFIN_DWAYS 2
-#define BFIN_DLINES 64
-#define BFIN_ISUBBANKS 4
-#define BFIN_IWAYS 4
-#define BFIN_ILINES 32
-
-#define WAY0_L 0x1
-#define WAY1_L 0x2
-#define WAY01_L 0x3
-#define WAY2_L 0x4
-#define WAY02_L 0x5
-#define WAY12_L 0x6
-#define WAY012_L 0x7
-
-#define WAY3_L 0x8
-#define WAY03_L 0x9
-#define WAY13_L 0xA
-#define WAY013_L 0xB
-
-#define WAY32_L 0xC
-#define WAY320_L 0xD
-#define WAY321_L 0xE
-#define WAYALL_L 0xF
-
-#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
-
-/********************************* EBIU Settings ************************************/
-#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
-#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
-
-#ifdef CONFIG_C_AMBEN_ALL
-#define V_AMBEN AMBEN_ALL
-#endif
-#ifdef CONFIG_C_AMBEN
-#define V_AMBEN 0x0
-#endif
-#ifdef CONFIG_C_AMBEN_B0
-#define V_AMBEN AMBEN_B0
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1
-#define V_AMBEN AMBEN_B0_B1
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1_B2
-#define V_AMBEN AMBEN_B0_B1_B2
-#endif
-#ifdef CONFIG_C_AMCKEN
-#define V_AMCKEN AMCKEN
-#else
-#define V_AMCKEN 0x0
-#endif
-
-#define AMGCTLVAL (V_AMBEN | V_AMCKEN)
-
-#if defined(CONFIG_BF542)
-# define CPU "BF542"
-# define CPUID 0x27de
-#elif defined(CONFIG_BF544)
-# define CPU "BF544"
-# define CPUID 0x27de
-#elif defined(CONFIG_BF547)
-# define CPU "BF547"
-# define CPUID 0x27de
-#elif defined(CONFIG_BF548)
-# define CPU "BF548"
-# define CPUID 0x27de
-#elif defined(CONFIG_BF549)
-# define CPU "BF549"
-# define CPUID 0x27de
-#endif
-
-#ifndef CPU
-#error "Unknown CPU type - This kernel doesn't seem to be configured properly"
-#endif
-
-#endif /* __MACH_BF48_H__ */
+++ /dev/null
-/*
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef BF54X_LQ043_H
-#define BF54X_LQ043_H
-
-struct bfin_bf54xfb_val {
- unsigned int defval;
- unsigned int min;
- unsigned int max;
-};
-
-struct bfin_bf54xfb_mach_info {
- unsigned char fixed_syncs; /* do not update sync/border */
-
- /* LCD types */
- int type;
-
- /* Screen size */
- int width;
- int height;
-
- /* Screen info */
- struct bfin_bf54xfb_val xres;
- struct bfin_bf54xfb_val yres;
- struct bfin_bf54xfb_val bpp;
-
- /* GPIOs */
- unsigned short disp;
-
-};
-
-#endif /* BF54X_LQ043_H */
+++ /dev/null
-/*
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BFIN_KPAD_H
-#define _BFIN_KPAD_H
-
-struct bfin_kpad_platform_data {
- int rows;
- int cols;
- const unsigned int *keymap;
- unsigned short keymapsize;
- unsigned short repeat;
- u32 debounce_time; /* in ns */
- u32 coldrive_time; /* in ns */
- u32 keyup_test_interval; /* in ms */
-};
-
-#define KEYVAL(col, row, val) (((1 << col) << 24) | ((1 << row) << 16) | (val))
-
-#endif
+++ /dev/null
-/*
- * mach/bfin_serial.h - Blackfin UART/Serial definitions
- *
- * Copyright 2006-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MACH_SERIAL_H__
-#define __BFIN_MACH_SERIAL_H__
-
-#define BFIN_UART_NR_PORTS 4
-
-#define BFIN_UART_BF54X_STYLE
-
-#endif
+++ /dev/null
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_BLACKFIN_H_
-#define _MACH_BLACKFIN_H_
-
-#include "bf548.h"
-#include "anomaly.h"
-
-#include <asm/def_LPBlackfin.h>
-#ifdef CONFIG_BF542
-# include "defBF542.h"
-#endif
-#ifdef CONFIG_BF544
-# include "defBF544.h"
-#endif
-#ifdef CONFIG_BF547
-# include "defBF547.h"
-#endif
-#ifdef CONFIG_BF548
-# include "defBF548.h"
-#endif
-#ifdef CONFIG_BF549
-# include "defBF549.h"
-#endif
-
-#ifndef __ASSEMBLY__
-# include <asm/cdef_LPBlackfin.h>
-# ifdef CONFIG_BF542
-# include "cdefBF542.h"
-# endif
-# ifdef CONFIG_BF544
-# include "cdefBF544.h"
-# endif
-# ifdef CONFIG_BF547
-# include "cdefBF547.h"
-# endif
-# ifdef CONFIG_BF548
-# include "cdefBF548.h"
-# endif
-# ifdef CONFIG_BF549
-# include "cdefBF549.h"
-# endif
-#endif
-
-#endif
+++ /dev/null
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CDEF_BF542_H
-#define _CDEF_BF542_H
-
-/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
-#include "cdefBF54x_base.h"
-
-/* The following are the #defines needed by ADSP-BF542 that are not in the common header */
-
-/* ATAPI Registers */
-
-#define bfin_read_ATAPI_CONTROL() bfin_read16(ATAPI_CONTROL)
-#define bfin_write_ATAPI_CONTROL(val) bfin_write16(ATAPI_CONTROL, val)
-#define bfin_read_ATAPI_STATUS() bfin_read16(ATAPI_STATUS)
-#define bfin_write_ATAPI_STATUS(val) bfin_write16(ATAPI_STATUS, val)
-#define bfin_read_ATAPI_DEV_ADDR() bfin_read16(ATAPI_DEV_ADDR)
-#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val)
-#define bfin_read_ATAPI_DEV_TXBUF() bfin_read16(ATAPI_DEV_TXBUF)
-#define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val)
-#define bfin_read_ATAPI_DEV_RXBUF() bfin_read16(ATAPI_DEV_RXBUF)
-#define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val)
-#define bfin_read_ATAPI_INT_MASK() bfin_read16(ATAPI_INT_MASK)
-#define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val)
-#define bfin_read_ATAPI_INT_STATUS() bfin_read16(ATAPI_INT_STATUS)
-#define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val)
-#define bfin_read_ATAPI_XFER_LEN() bfin_read16(ATAPI_XFER_LEN)
-#define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val)
-#define bfin_read_ATAPI_LINE_STATUS() bfin_read16(ATAPI_LINE_STATUS)
-#define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val)
-#define bfin_read_ATAPI_SM_STATE() bfin_read16(ATAPI_SM_STATE)
-#define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val)
-#define bfin_read_ATAPI_TERMINATE() bfin_read16(ATAPI_TERMINATE)
-#define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val)
-#define bfin_read_ATAPI_PIO_TFRCNT() bfin_read16(ATAPI_PIO_TFRCNT)
-#define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val)
-#define bfin_read_ATAPI_DMA_TFRCNT() bfin_read16(ATAPI_DMA_TFRCNT)
-#define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val)
-#define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT)
-#define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val)
-#define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT)
-#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val)
-#define bfin_read_ATAPI_REG_TIM_0() bfin_read16(ATAPI_REG_TIM_0)
-#define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val)
-#define bfin_read_ATAPI_PIO_TIM_0() bfin_read16(ATAPI_PIO_TIM_0)
-#define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val)
-#define bfin_read_ATAPI_PIO_TIM_1() bfin_read16(ATAPI_PIO_TIM_1)
-#define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val)
-#define bfin_read_ATAPI_MULTI_TIM_0() bfin_read16(ATAPI_MULTI_TIM_0)
-#define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val)
-#define bfin_read_ATAPI_MULTI_TIM_1() bfin_read16(ATAPI_MULTI_TIM_1)
-#define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val)
-#define bfin_read_ATAPI_MULTI_TIM_2() bfin_read16(ATAPI_MULTI_TIM_2)
-#define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val)
-#define bfin_read_ATAPI_ULTRA_TIM_0() bfin_read16(ATAPI_ULTRA_TIM_0)
-#define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val)
-#define bfin_read_ATAPI_ULTRA_TIM_1() bfin_read16(ATAPI_ULTRA_TIM_1)
-#define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val)
-#define bfin_read_ATAPI_ULTRA_TIM_2() bfin_read16(ATAPI_ULTRA_TIM_2)
-#define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val)
-#define bfin_read_ATAPI_ULTRA_TIM_3() bfin_read16(ATAPI_ULTRA_TIM_3)
-#define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val)
-
-/* SDH Registers */
-
-#define bfin_read_SDH_PWR_CTL() bfin_read16(SDH_PWR_CTL)
-#define bfin_write_SDH_PWR_CTL(val) bfin_write16(SDH_PWR_CTL, val)
-#define bfin_read_SDH_CLK_CTL() bfin_read16(SDH_CLK_CTL)
-#define bfin_write_SDH_CLK_CTL(val) bfin_write16(SDH_CLK_CTL, val)
-#define bfin_read_SDH_ARGUMENT() bfin_read32(SDH_ARGUMENT)
-#define bfin_write_SDH_ARGUMENT(val) bfin_write32(SDH_ARGUMENT, val)
-#define bfin_read_SDH_COMMAND() bfin_read16(SDH_COMMAND)
-#define bfin_write_SDH_COMMAND(val) bfin_write16(SDH_COMMAND, val)
-#define bfin_read_SDH_RESP_CMD() bfin_read16(SDH_RESP_CMD)
-#define bfin_write_SDH_RESP_CMD(val) bfin_write16(SDH_RESP_CMD, val)
-#define bfin_read_SDH_RESPONSE0() bfin_read32(SDH_RESPONSE0)
-#define bfin_write_SDH_RESPONSE0(val) bfin_write32(SDH_RESPONSE0, val)
-#define bfin_read_SDH_RESPONSE1() bfin_read32(SDH_RESPONSE1)
-#define bfin_write_SDH_RESPONSE1(val) bfin_write32(SDH_RESPONSE1, val)
-#define bfin_read_SDH_RESPONSE2() bfin_read32(SDH_RESPONSE2)
-#define bfin_write_SDH_RESPONSE2(val) bfin_write32(SDH_RESPONSE2, val)
-#define bfin_read_SDH_RESPONSE3() bfin_read32(SDH_RESPONSE3)
-#define bfin_write_SDH_RESPONSE3(val) bfin_write32(SDH_RESPONSE3, val)
-#define bfin_read_SDH_DATA_TIMER() bfin_read32(SDH_DATA_TIMER)
-#define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val)
-#define bfin_read_SDH_DATA_LGTH() bfin_read16(SDH_DATA_LGTH)
-#define bfin_write_SDH_DATA_LGTH(val) bfin_write16(SDH_DATA_LGTH, val)
-#define bfin_read_SDH_DATA_CTL() bfin_read16(SDH_DATA_CTL)
-#define bfin_write_SDH_DATA_CTL(val) bfin_write16(SDH_DATA_CTL, val)
-#define bfin_read_SDH_DATA_CNT() bfin_read16(SDH_DATA_CNT)
-#define bfin_write_SDH_DATA_CNT(val) bfin_write16(SDH_DATA_CNT, val)
-#define bfin_read_SDH_STATUS() bfin_read32(SDH_STATUS)
-#define bfin_write_SDH_STATUS(val) bfin_write32(SDH_STATUS, val)
-#define bfin_read_SDH_STATUS_CLR() bfin_read16(SDH_STATUS_CLR)
-#define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val)
-#define bfin_read_SDH_MASK0() bfin_read32(SDH_MASK0)
-#define bfin_write_SDH_MASK0(val) bfin_write32(SDH_MASK0, val)
-#define bfin_read_SDH_MASK1() bfin_read32(SDH_MASK1)
-#define bfin_write_SDH_MASK1(val) bfin_write32(SDH_MASK1, val)
-#define bfin_read_SDH_FIFO_CNT() bfin_read16(SDH_FIFO_CNT)
-#define bfin_write_SDH_FIFO_CNT(val) bfin_write16(SDH_FIFO_CNT, val)
-#define bfin_read_SDH_FIFO() bfin_read32(SDH_FIFO)
-#define bfin_write_SDH_FIFO(val) bfin_write32(SDH_FIFO, val)
-#define bfin_read_SDH_E_STATUS() bfin_read16(SDH_E_STATUS)
-#define bfin_write_SDH_E_STATUS(val) bfin_write16(SDH_E_STATUS, val)
-#define bfin_read_SDH_E_MASK() bfin_read16(SDH_E_MASK)
-#define bfin_write_SDH_E_MASK(val) bfin_write16(SDH_E_MASK, val)
-#define bfin_read_SDH_CFG() bfin_read16(SDH_CFG)
-#define bfin_write_SDH_CFG(val) bfin_write16(SDH_CFG, val)
-#define bfin_read_SDH_RD_WAIT_EN() bfin_read16(SDH_RD_WAIT_EN)
-#define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val)
-#define bfin_read_SDH_PID0() bfin_read16(SDH_PID0)
-#define bfin_write_SDH_PID0(val) bfin_write16(SDH_PID0, val)
-#define bfin_read_SDH_PID1() bfin_read16(SDH_PID1)
-#define bfin_write_SDH_PID1(val) bfin_write16(SDH_PID1, val)
-#define bfin_read_SDH_PID2() bfin_read16(SDH_PID2)
-#define bfin_write_SDH_PID2(val) bfin_write16(SDH_PID2, val)
-#define bfin_read_SDH_PID3() bfin_read16(SDH_PID3)
-#define bfin_write_SDH_PID3(val) bfin_write16(SDH_PID3, val)
-#define bfin_read_SDH_PID4() bfin_read16(SDH_PID4)
-#define bfin_write_SDH_PID4(val) bfin_write16(SDH_PID4, val)
-#define bfin_read_SDH_PID5() bfin_read16(SDH_PID5)
-#define bfin_write_SDH_PID5(val) bfin_write16(SDH_PID5, val)
-#define bfin_read_SDH_PID6() bfin_read16(SDH_PID6)
-#define bfin_write_SDH_PID6(val) bfin_write16(SDH_PID6, val)
-#define bfin_read_SDH_PID7() bfin_read16(SDH_PID7)
-#define bfin_write_SDH_PID7(val) bfin_write16(SDH_PID7, val)
-
-/* USB Control Registers */
-
-#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
-#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
-#define bfin_read_USB_POWER() bfin_read16(USB_POWER)
-#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val)
-#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX)
-#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val)
-#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX)
-#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val)
-#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE)
-#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val)
-#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE)
-#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val)
-#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB)
-#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val)
-#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE)
-#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val)
-#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME)
-#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val)
-#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX)
-#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val)
-#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE)
-#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val)
-#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR)
-#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val)
-#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL)
-#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
-
-/* USB Packet Control Registers */
-
-#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET)
-#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
-#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0)
-#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val)
-#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR)
-#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val)
-#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET)
-#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
-#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR)
-#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val)
-#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0)
-#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val)
-#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT)
-#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val)
-#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE)
-#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val)
-#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0)
-#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val)
-#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL)
-#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
-#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE)
-#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val)
-#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL)
-#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
-#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT)
-#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val)
-
-/* USB Endbfin_read_()oint FIFO Registers */
-
-#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO)
-#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val)
-#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO)
-#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val)
-#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO)
-#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val)
-#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO)
-#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val)
-#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO)
-#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val)
-#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO)
-#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val)
-#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO)
-#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val)
-#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO)
-#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val)
-
-/* USB OTG Control Registers */
-
-#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL)
-#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
-#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ)
-#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
-#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK)
-#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
-
-/* USB Phy Control Registers */
-
-#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO)
-#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val)
-#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN)
-#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val)
-#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1)
-#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val)
-#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1)
-#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val)
-#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1)
-#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val)
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL)
-#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB)
-#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
-#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2)
-#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
-
-#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL)
-#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
-#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV)
-#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
-
-/* USB Endbfin_read_()oint 0 Control Registers */
-
-#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP)
-#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
-#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR)
-#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
-#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP)
-#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
-#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR)
-#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
-#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
-#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
-#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE)
-#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
-#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
-#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE)
-#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
-#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
-#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 1 Control Registers */
-
-#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
-#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
-#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP)
-#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
-#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR)
-#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
-#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP)
-#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
-#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR)
-#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
-#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
-#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
-#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE)
-#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
-#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
-#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE)
-#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
-#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
-#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 2 Control Registers */
-
-#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
-#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
-#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP)
-#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
-#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR)
-#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
-#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP)
-#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
-#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR)
-#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
-#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
-#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
-#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE)
-#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
-#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
-#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE)
-#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
-#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
-#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 3 Control Registers */
-
-#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
-#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
-#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP)
-#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
-#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR)
-#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
-#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP)
-#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
-#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR)
-#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
-#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
-#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
-#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE)
-#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
-#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
-#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE)
-#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
-#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
-#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 4 Control Registers */
-
-#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
-#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
-#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP)
-#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
-#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR)
-#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
-#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP)
-#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
-#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR)
-#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
-#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
-#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
-#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE)
-#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
-#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
-#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE)
-#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
-#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
-#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 5 Control Registers */
-
-#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
-#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
-#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP)
-#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
-#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR)
-#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
-#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP)
-#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
-#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR)
-#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
-#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
-#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
-#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE)
-#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
-#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
-#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE)
-#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
-#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
-#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 6 Control Registers */
-
-#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
-#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
-#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP)
-#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
-#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR)
-#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
-#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP)
-#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
-#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR)
-#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
-#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
-#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
-#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE)
-#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
-#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
-#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE)
-#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
-#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
-#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 7 Control Registers */
-
-#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
-#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
-#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP)
-#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
-#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR)
-#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
-#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP)
-#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
-#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR)
-#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
-#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
-#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
-#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE)
-#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
-#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
-#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE)
-#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
-#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
-#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
-#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
-#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT)
-#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
-
-/* USB Channel 0 Config Registers */
-
-#define bfin_read_USB_DMA0CONTROL() bfin_read16(USB_DMA0CONTROL)
-#define bfin_write_USB_DMA0CONTROL(val) bfin_write16(USB_DMA0CONTROL, val)
-#define bfin_read_USB_DMA0ADDRLOW() bfin_read16(USB_DMA0ADDRLOW)
-#define bfin_write_USB_DMA0ADDRLOW(val) bfin_write16(USB_DMA0ADDRLOW, val)
-#define bfin_read_USB_DMA0ADDRHIGH() bfin_read16(USB_DMA0ADDRHIGH)
-#define bfin_write_USB_DMA0ADDRHIGH(val) bfin_write16(USB_DMA0ADDRHIGH, val)
-#define bfin_read_USB_DMA0COUNTLOW() bfin_read16(USB_DMA0COUNTLOW)
-#define bfin_write_USB_DMA0COUNTLOW(val) bfin_write16(USB_DMA0COUNTLOW, val)
-#define bfin_read_USB_DMA0COUNTHIGH() bfin_read16(USB_DMA0COUNTHIGH)
-#define bfin_write_USB_DMA0COUNTHIGH(val) bfin_write16(USB_DMA0COUNTHIGH, val)
-
-/* USB Channel 1 Config Registers */
-
-#define bfin_read_USB_DMA1CONTROL() bfin_read16(USB_DMA1CONTROL)
-#define bfin_write_USB_DMA1CONTROL(val) bfin_write16(USB_DMA1CONTROL, val)
-#define bfin_read_USB_DMA1ADDRLOW() bfin_read16(USB_DMA1ADDRLOW)
-#define bfin_write_USB_DMA1ADDRLOW(val) bfin_write16(USB_DMA1ADDRLOW, val)
-#define bfin_read_USB_DMA1ADDRHIGH() bfin_read16(USB_DMA1ADDRHIGH)
-#define bfin_write_USB_DMA1ADDRHIGH(val) bfin_write16(USB_DMA1ADDRHIGH, val)
-#define bfin_read_USB_DMA1COUNTLOW() bfin_read16(USB_DMA1COUNTLOW)
-#define bfin_write_USB_DMA1COUNTLOW(val) bfin_write16(USB_DMA1COUNTLOW, val)
-#define bfin_read_USB_DMA1COUNTHIGH() bfin_read16(USB_DMA1COUNTHIGH)
-#define bfin_write_USB_DMA1COUNTHIGH(val) bfin_write16(USB_DMA1COUNTHIGH, val)
-
-/* USB Channel 2 Config Registers */
-
-#define bfin_read_USB_DMA2CONTROL() bfin_read16(USB_DMA2CONTROL)
-#define bfin_write_USB_DMA2CONTROL(val) bfin_write16(USB_DMA2CONTROL, val)
-#define bfin_read_USB_DMA2ADDRLOW() bfin_read16(USB_DMA2ADDRLOW)
-#define bfin_write_USB_DMA2ADDRLOW(val) bfin_write16(USB_DMA2ADDRLOW, val)
-#define bfin_read_USB_DMA2ADDRHIGH() bfin_read16(USB_DMA2ADDRHIGH)
-#define bfin_write_USB_DMA2ADDRHIGH(val) bfin_write16(USB_DMA2ADDRHIGH, val)
-#define bfin_read_USB_DMA2COUNTLOW() bfin_read16(USB_DMA2COUNTLOW)
-#define bfin_write_USB_DMA2COUNTLOW(val) bfin_write16(USB_DMA2COUNTLOW, val)
-#define bfin_read_USB_DMA2COUNTHIGH() bfin_read16(USB_DMA2COUNTHIGH)
-#define bfin_write_USB_DMA2COUNTHIGH(val) bfin_write16(USB_DMA2COUNTHIGH, val)
-
-/* USB Channel 3 Config Registers */
-
-#define bfin_read_USB_DMA3CONTROL() bfin_read16(USB_DMA3CONTROL)
-#define bfin_write_USB_DMA3CONTROL(val) bfin_write16(USB_DMA3CONTROL, val)
-#define bfin_read_USB_DMA3ADDRLOW() bfin_read16(USB_DMA3ADDRLOW)
-#define bfin_write_USB_DMA3ADDRLOW(val) bfin_write16(USB_DMA3ADDRLOW, val)
-#define bfin_read_USB_DMA3ADDRHIGH() bfin_read16(USB_DMA3ADDRHIGH)
-#define bfin_write_USB_DMA3ADDRHIGH(val) bfin_write16(USB_DMA3ADDRHIGH, val)
-#define bfin_read_USB_DMA3COUNTLOW() bfin_read16(USB_DMA3COUNTLOW)
-#define bfin_write_USB_DMA3COUNTLOW(val) bfin_write16(USB_DMA3COUNTLOW, val)
-#define bfin_read_USB_DMA3COUNTHIGH() bfin_read16(USB_DMA3COUNTHIGH)
-#define bfin_write_USB_DMA3COUNTHIGH(val) bfin_write16(USB_DMA3COUNTHIGH, val)
-
-/* USB Channel 4 Config Registers */
-
-#define bfin_read_USB_DMA4CONTROL() bfin_read16(USB_DMA4CONTROL)
-#define bfin_write_USB_DMA4CONTROL(val) bfin_write16(USB_DMA4CONTROL, val)
-#define bfin_read_USB_DMA4ADDRLOW() bfin_read16(USB_DMA4ADDRLOW)
-#define bfin_write_USB_DMA4ADDRLOW(val) bfin_write16(USB_DMA4ADDRLOW, val)
-#define bfin_read_USB_DMA4ADDRHIGH() bfin_read16(USB_DMA4ADDRHIGH)
-#define bfin_write_USB_DMA4ADDRHIGH(val) bfin_write16(USB_DMA4ADDRHIGH, val)
-#define bfin_read_USB_DMA4COUNTLOW() bfin_read16(USB_DMA4COUNTLOW)
-#define bfin_write_USB_DMA4COUNTLOW(val) bfin_write16(USB_DMA4COUNTLOW, val)
-#define bfin_read_USB_DMA4COUNTHIGH() bfin_read16(USB_DMA4COUNTHIGH)
-#define bfin_write_USB_DMA4COUNTHIGH(val) bfin_write16(USB_DMA4COUNTHIGH, val)
-
-/* USB Channel 5 Config Registers */
-
-#define bfin_read_USB_DMA5CONTROL() bfin_read16(USB_DMA5CONTROL)
-#define bfin_write_USB_DMA5CONTROL(val) bfin_write16(USB_DMA5CONTROL, val)
-#define bfin_read_USB_DMA5ADDRLOW() bfin_read16(USB_DMA5ADDRLOW)
-#define bfin_write_USB_DMA5ADDRLOW(val) bfin_write16(USB_DMA5ADDRLOW, val)
-#define bfin_read_USB_DMA5ADDRHIGH() bfin_read16(USB_DMA5ADDRHIGH)
-#define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val)
-#define bfin_read_USB_DMA5COUNTLOW() bfin_read16(USB_DMA5COUNTLOW)
-#define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val)
-#define bfin_read_USB_DMA5COUNTHIGH() bfin_read16(USB_DMA5COUNTHIGH)
-#define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val)
-
-/* USB Channel 6 Config Registers */
-
-#define bfin_read_USB_DMA6CONTROL() bfin_read16(USB_DMA6CONTROL)
-#define bfin_write_USB_DMA6CONTROL(val) bfin_write16(USB_DMA6CONTROL, val)
-#define bfin_read_USB_DMA6ADDRLOW() bfin_read16(USB_DMA6ADDRLOW)
-#define bfin_write_USB_DMA6ADDRLOW(val) bfin_write16(USB_DMA6ADDRLOW, val)
-#define bfin_read_USB_DMA6ADDRHIGH() bfin_read16(USB_DMA6ADDRHIGH)
-#define bfin_write_USB_DMA6ADDRHIGH(val) bfin_write16(USB_DMA6ADDRHIGH, val)
-#define bfin_read_USB_DMA6COUNTLOW() bfin_read16(USB_DMA6COUNTLOW)
-#define bfin_write_USB_DMA6COUNTLOW(val) bfin_write16(USB_DMA6COUNTLOW, val)
-#define bfin_read_USB_DMA6COUNTHIGH() bfin_read16(USB_DMA6COUNTHIGH)
-#define bfin_write_USB_DMA6COUNTHIGH(val) bfin_write16(USB_DMA6COUNTHIGH, val)
-
-/* USB Channel 7 Config Registers */
-
-#define bfin_read_USB_DMA7CONTROL() bfin_read16(USB_DMA7CONTROL)
-#define bfin_write_USB_DMA7CONTROL(val) bfin_write16(USB_DMA7CONTROL, val)
-#define bfin_read_USB_DMA7ADDRLOW() bfin_read16(USB_DMA7ADDRLOW)
-#define bfin_write_USB_DMA7ADDRLOW(val) bfin_write16(USB_DMA7ADDRLOW, val)
-#define bfin_read_USB_DMA7ADDRHIGH() bfin_read16(USB_DMA7ADDRHIGH)
-#define bfin_write_USB_DMA7ADDRHIGH(val) bfin_write16(USB_DMA7ADDRHIGH, val)
-#define bfin_read_USB_DMA7COUNTLOW() bfin_read16(USB_DMA7COUNTLOW)
-#define bfin_write_USB_DMA7COUNTLOW(val) bfin_write16(USB_DMA7COUNTLOW, val)
-#define bfin_read_USB_DMA7COUNTHIGH() bfin_read16(USB_DMA7COUNTHIGH)
-#define bfin_write_USB_DMA7COUNTHIGH(val) bfin_write16(USB_DMA7COUNTHIGH, val)
-
-/* Keybfin_read_()ad Registers */
-
-#define bfin_read_KPAD_CTL() bfin_read16(KPAD_CTL)
-#define bfin_write_KPAD_CTL(val) bfin_write16(KPAD_CTL, val)
-#define bfin_read_KPAD_PRESCALE() bfin_read16(KPAD_PRESCALE)
-#define bfin_write_KPAD_PRESCALE(val) bfin_write16(KPAD_PRESCALE, val)
-#define bfin_read_KPAD_MSEL() bfin_read16(KPAD_MSEL)
-#define bfin_write_KPAD_MSEL(val) bfin_write16(KPAD_MSEL, val)
-#define bfin_read_KPAD_ROWCOL() bfin_read16(KPAD_ROWCOL)
-#define bfin_write_KPAD_ROWCOL(val) bfin_write16(KPAD_ROWCOL, val)
-#define bfin_read_KPAD_STAT() bfin_read16(KPAD_STAT)
-#define bfin_write_KPAD_STAT(val) bfin_write16(KPAD_STAT, val)
-#define bfin_read_KPAD_SOFTEVAL() bfin_read16(KPAD_SOFTEVAL)
-#define bfin_write_KPAD_SOFTEVAL(val) bfin_write16(KPAD_SOFTEVAL, val)
-
-#endif /* _CDEF_BF542_H */
+++ /dev/null
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CDEF_BF544_H
-#define _CDEF_BF544_H
-
-/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
-#include "cdefBF54x_base.h"
-
-/* The following are the #defines needed by ADSP-BF544 that are not in the common header */
-
-/* Timer Registers */
-
-#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG)
-#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val)
-#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER)
-#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
-#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD)
-#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val)
-#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH)
-#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val)
-#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG)
-#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val)
-#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER)
-#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
-#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD)
-#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val)
-#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH)
-#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val)
-#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG)
-#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)
-#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER)
-#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
-#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD)
-#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
-#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH)
-#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val)
-
-/* Timer Groubfin_read_() of 3 */
-
-#define bfin_read_TIMER_ENABLE1() bfin_read16(TIMER_ENABLE1)
-#define bfin_write_TIMER_ENABLE1(val) bfin_write16(TIMER_ENABLE1, val)
-#define bfin_read_TIMER_DISABLE1() bfin_read16(TIMER_DISABLE1)
-#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val)
-#define bfin_read_TIMER_STATUS1() bfin_read32(TIMER_STATUS1)
-#define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val)
-
-/* EPPI0 Registers */
-
-#define bfin_read_EPPI0_STATUS() bfin_read16(EPPI0_STATUS)
-#define bfin_write_EPPI0_STATUS(val) bfin_write16(EPPI0_STATUS, val)
-#define bfin_read_EPPI0_HCOUNT() bfin_read16(EPPI0_HCOUNT)
-#define bfin_write_EPPI0_HCOUNT(val) bfin_write16(EPPI0_HCOUNT, val)
-#define bfin_read_EPPI0_HDELAY() bfin_read16(EPPI0_HDELAY)
-#define bfin_write_EPPI0_HDELAY(val) bfin_write16(EPPI0_HDELAY, val)
-#define bfin_read_EPPI0_VCOUNT() bfin_read16(EPPI0_VCOUNT)
-#define bfin_write_EPPI0_VCOUNT(val) bfin_write16(EPPI0_VCOUNT, val)
-#define bfin_read_EPPI0_VDELAY() bfin_read16(EPPI0_VDELAY)
-#define bfin_write_EPPI0_VDELAY(val) bfin_write16(EPPI0_VDELAY, val)
-#define bfin_read_EPPI0_FRAME() bfin_read16(EPPI0_FRAME)
-#define bfin_write_EPPI0_FRAME(val) bfin_write16(EPPI0_FRAME, val)
-#define bfin_read_EPPI0_LINE() bfin_read16(EPPI0_LINE)
-#define bfin_write_EPPI0_LINE(val) bfin_write16(EPPI0_LINE, val)
-#define bfin_read_EPPI0_CLKDIV() bfin_read16(EPPI0_CLKDIV)
-#define bfin_write_EPPI0_CLKDIV(val) bfin_write16(EPPI0_CLKDIV, val)
-#define bfin_read_EPPI0_CONTROL() bfin_read32(EPPI0_CONTROL)
-#define bfin_write_EPPI0_CONTROL(val) bfin_write32(EPPI0_CONTROL, val)
-#define bfin_read_EPPI0_FS1W_HBL() bfin_read32(EPPI0_FS1W_HBL)
-#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val)
-#define bfin_read_EPPI0_FS1P_AVPL() bfin_read32(EPPI0_FS1P_AVPL)
-#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val)
-#define bfin_read_EPPI0_FS2W_LVB() bfin_read32(EPPI0_FS2W_LVB)
-#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val)
-#define bfin_read_EPPI0_FS2P_LAVF() bfin_read32(EPPI0_FS2P_LAVF)
-#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val)
-#define bfin_read_EPPI0_CLIP() bfin_read32(EPPI0_CLIP)
-#define bfin_write_EPPI0_CLIP(val) bfin_write32(EPPI0_CLIP, val)
-
-/* Two Wire Interface Registers (TWI1) */
-
-/* CAN Controller 1 Config 1 Registers */
-
-#define bfin_read_CAN1_MC1() bfin_read16(CAN1_MC1)
-#define bfin_write_CAN1_MC1(val) bfin_write16(CAN1_MC1, val)
-#define bfin_read_CAN1_MD1() bfin_read16(CAN1_MD1)
-#define bfin_write_CAN1_MD1(val) bfin_write16(CAN1_MD1, val)
-#define bfin_read_CAN1_TRS1() bfin_read16(CAN1_TRS1)
-#define bfin_write_CAN1_TRS1(val) bfin_write16(CAN1_TRS1, val)
-#define bfin_read_CAN1_TRR1() bfin_read16(CAN1_TRR1)
-#define bfin_write_CAN1_TRR1(val) bfin_write16(CAN1_TRR1, val)
-#define bfin_read_CAN1_TA1() bfin_read16(CAN1_TA1)
-#define bfin_write_CAN1_TA1(val) bfin_write16(CAN1_TA1, val)
-#define bfin_read_CAN1_AA1() bfin_read16(CAN1_AA1)
-#define bfin_write_CAN1_AA1(val) bfin_write16(CAN1_AA1, val)
-#define bfin_read_CAN1_RMP1() bfin_read16(CAN1_RMP1)
-#define bfin_write_CAN1_RMP1(val) bfin_write16(CAN1_RMP1, val)
-#define bfin_read_CAN1_RML1() bfin_read16(CAN1_RML1)
-#define bfin_write_CAN1_RML1(val) bfin_write16(CAN1_RML1, val)
-#define bfin_read_CAN1_MBTIF1() bfin_read16(CAN1_MBTIF1)
-#define bfin_write_CAN1_MBTIF1(val) bfin_write16(CAN1_MBTIF1, val)
-#define bfin_read_CAN1_MBRIF1() bfin_read16(CAN1_MBRIF1)
-#define bfin_write_CAN1_MBRIF1(val) bfin_write16(CAN1_MBRIF1, val)
-#define bfin_read_CAN1_MBIM1() bfin_read16(CAN1_MBIM1)
-#define bfin_write_CAN1_MBIM1(val) bfin_write16(CAN1_MBIM1, val)
-#define bfin_read_CAN1_RFH1() bfin_read16(CAN1_RFH1)
-#define bfin_write_CAN1_RFH1(val) bfin_write16(CAN1_RFH1, val)
-#define bfin_read_CAN1_OPSS1() bfin_read16(CAN1_OPSS1)
-#define bfin_write_CAN1_OPSS1(val) bfin_write16(CAN1_OPSS1, val)
-
-/* CAN Controller 1 Config 2 Registers */
-
-#define bfin_read_CAN1_MC2() bfin_read16(CAN1_MC2)
-#define bfin_write_CAN1_MC2(val) bfin_write16(CAN1_MC2, val)
-#define bfin_read_CAN1_MD2() bfin_read16(CAN1_MD2)
-#define bfin_write_CAN1_MD2(val) bfin_write16(CAN1_MD2, val)
-#define bfin_read_CAN1_TRS2() bfin_read16(CAN1_TRS2)
-#define bfin_write_CAN1_TRS2(val) bfin_write16(CAN1_TRS2, val)
-#define bfin_read_CAN1_TRR2() bfin_read16(CAN1_TRR2)
-#define bfin_write_CAN1_TRR2(val) bfin_write16(CAN1_TRR2, val)
-#define bfin_read_CAN1_TA2() bfin_read16(CAN1_TA2)
-#define bfin_write_CAN1_TA2(val) bfin_write16(CAN1_TA2, val)
-#define bfin_read_CAN1_AA2() bfin_read16(CAN1_AA2)
-#define bfin_write_CAN1_AA2(val) bfin_write16(CAN1_AA2, val)
-#define bfin_read_CAN1_RMP2() bfin_read16(CAN1_RMP2)
-#define bfin_write_CAN1_RMP2(val) bfin_write16(CAN1_RMP2, val)
-#define bfin_read_CAN1_RML2() bfin_read16(CAN1_RML2)
-#define bfin_write_CAN1_RML2(val) bfin_write16(CAN1_RML2, val)
-#define bfin_read_CAN1_MBTIF2() bfin_read16(CAN1_MBTIF2)
-#define bfin_write_CAN1_MBTIF2(val) bfin_write16(CAN1_MBTIF2, val)
-#define bfin_read_CAN1_MBRIF2() bfin_read16(CAN1_MBRIF2)
-#define bfin_write_CAN1_MBRIF2(val) bfin_write16(CAN1_MBRIF2, val)
-#define bfin_read_CAN1_MBIM2() bfin_read16(CAN1_MBIM2)
-#define bfin_write_CAN1_MBIM2(val) bfin_write16(CAN1_MBIM2, val)
-#define bfin_read_CAN1_RFH2() bfin_read16(CAN1_RFH2)
-#define bfin_write_CAN1_RFH2(val) bfin_write16(CAN1_RFH2, val)
-#define bfin_read_CAN1_OPSS2() bfin_read16(CAN1_OPSS2)
-#define bfin_write_CAN1_OPSS2(val) bfin_write16(CAN1_OPSS2, val)
-
-/* CAN Controller 1 Clock/Interrubfin_read_()t/Counter Registers */
-
-#define bfin_read_CAN1_CLOCK() bfin_read16(CAN1_CLOCK)
-#define bfin_write_CAN1_CLOCK(val) bfin_write16(CAN1_CLOCK, val)
-#define bfin_read_CAN1_TIMING() bfin_read16(CAN1_TIMING)
-#define bfin_write_CAN1_TIMING(val) bfin_write16(CAN1_TIMING, val)
-#define bfin_read_CAN1_DEBUG() bfin_read16(CAN1_DEBUG)
-#define bfin_write_CAN1_DEBUG(val) bfin_write16(CAN1_DEBUG, val)
-#define bfin_read_CAN1_STATUS() bfin_read16(CAN1_STATUS)
-#define bfin_write_CAN1_STATUS(val) bfin_write16(CAN1_STATUS, val)
-#define bfin_read_CAN1_CEC() bfin_read16(CAN1_CEC)
-#define bfin_write_CAN1_CEC(val) bfin_write16(CAN1_CEC, val)
-#define bfin_read_CAN1_GIS() bfin_read16(CAN1_GIS)
-#define bfin_write_CAN1_GIS(val) bfin_write16(CAN1_GIS, val)
-#define bfin_read_CAN1_GIM() bfin_read16(CAN1_GIM)
-#define bfin_write_CAN1_GIM(val) bfin_write16(CAN1_GIM, val)
-#define bfin_read_CAN1_GIF() bfin_read16(CAN1_GIF)
-#define bfin_write_CAN1_GIF(val) bfin_write16(CAN1_GIF, val)
-#define bfin_read_CAN1_CONTROL() bfin_read16(CAN1_CONTROL)
-#define bfin_write_CAN1_CONTROL(val) bfin_write16(CAN1_CONTROL, val)
-#define bfin_read_CAN1_INTR() bfin_read16(CAN1_INTR)
-#define bfin_write_CAN1_INTR(val) bfin_write16(CAN1_INTR, val)
-#define bfin_read_CAN1_MBTD() bfin_read16(CAN1_MBTD)
-#define bfin_write_CAN1_MBTD(val) bfin_write16(CAN1_MBTD, val)
-#define bfin_read_CAN1_EWR() bfin_read16(CAN1_EWR)
-#define bfin_write_CAN1_EWR(val) bfin_write16(CAN1_EWR, val)
-#define bfin_read_CAN1_ESR() bfin_read16(CAN1_ESR)
-#define bfin_write_CAN1_ESR(val) bfin_write16(CAN1_ESR, val)
-#define bfin_read_CAN1_UCCNT() bfin_read16(CAN1_UCCNT)
-#define bfin_write_CAN1_UCCNT(val) bfin_write16(CAN1_UCCNT, val)
-#define bfin_read_CAN1_UCRC() bfin_read16(CAN1_UCRC)
-#define bfin_write_CAN1_UCRC(val) bfin_write16(CAN1_UCRC, val)
-#define bfin_read_CAN1_UCCNF() bfin_read16(CAN1_UCCNF)
-#define bfin_write_CAN1_UCCNF(val) bfin_write16(CAN1_UCCNF, val)
-
-/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */
-
-#define bfin_read_CAN1_AM00L() bfin_read16(CAN1_AM00L)
-#define bfin_write_CAN1_AM00L(val) bfin_write16(CAN1_AM00L, val)
-#define bfin_read_CAN1_AM00H() bfin_read16(CAN1_AM00H)
-#define bfin_write_CAN1_AM00H(val) bfin_write16(CAN1_AM00H, val)
-#define bfin_read_CAN1_AM01L() bfin_read16(CAN1_AM01L)
-#define bfin_write_CAN1_AM01L(val) bfin_write16(CAN1_AM01L, val)
-#define bfin_read_CAN1_AM01H() bfin_read16(CAN1_AM01H)
-#define bfin_write_CAN1_AM01H(val) bfin_write16(CAN1_AM01H, val)
-#define bfin_read_CAN1_AM02L() bfin_read16(CAN1_AM02L)
-#define bfin_write_CAN1_AM02L(val) bfin_write16(CAN1_AM02L, val)
-#define bfin_read_CAN1_AM02H() bfin_read16(CAN1_AM02H)
-#define bfin_write_CAN1_AM02H(val) bfin_write16(CAN1_AM02H, val)
-#define bfin_read_CAN1_AM03L() bfin_read16(CAN1_AM03L)
-#define bfin_write_CAN1_AM03L(val) bfin_write16(CAN1_AM03L, val)
-#define bfin_read_CAN1_AM03H() bfin_read16(CAN1_AM03H)
-#define bfin_write_CAN1_AM03H(val) bfin_write16(CAN1_AM03H, val)
-#define bfin_read_CAN1_AM04L() bfin_read16(CAN1_AM04L)
-#define bfin_write_CAN1_AM04L(val) bfin_write16(CAN1_AM04L, val)
-#define bfin_read_CAN1_AM04H() bfin_read16(CAN1_AM04H)
-#define bfin_write_CAN1_AM04H(val) bfin_write16(CAN1_AM04H, val)
-#define bfin_read_CAN1_AM05L() bfin_read16(CAN1_AM05L)
-#define bfin_write_CAN1_AM05L(val) bfin_write16(CAN1_AM05L, val)
-#define bfin_read_CAN1_AM05H() bfin_read16(CAN1_AM05H)
-#define bfin_write_CAN1_AM05H(val) bfin_write16(CAN1_AM05H, val)
-#define bfin_read_CAN1_AM06L() bfin_read16(CAN1_AM06L)
-#define bfin_write_CAN1_AM06L(val) bfin_write16(CAN1_AM06L, val)
-#define bfin_read_CAN1_AM06H() bfin_read16(CAN1_AM06H)
-#define bfin_write_CAN1_AM06H(val) bfin_write16(CAN1_AM06H, val)
-#define bfin_read_CAN1_AM07L() bfin_read16(CAN1_AM07L)
-#define bfin_write_CAN1_AM07L(val) bfin_write16(CAN1_AM07L, val)
-#define bfin_read_CAN1_AM07H() bfin_read16(CAN1_AM07H)
-#define bfin_write_CAN1_AM07H(val) bfin_write16(CAN1_AM07H, val)
-#define bfin_read_CAN1_AM08L() bfin_read16(CAN1_AM08L)
-#define bfin_write_CAN1_AM08L(val) bfin_write16(CAN1_AM08L, val)
-#define bfin_read_CAN1_AM08H() bfin_read16(CAN1_AM08H)
-#define bfin_write_CAN1_AM08H(val) bfin_write16(CAN1_AM08H, val)
-#define bfin_read_CAN1_AM09L() bfin_read16(CAN1_AM09L)
-#define bfin_write_CAN1_AM09L(val) bfin_write16(CAN1_AM09L, val)
-#define bfin_read_CAN1_AM09H() bfin_read16(CAN1_AM09H)
-#define bfin_write_CAN1_AM09H(val) bfin_write16(CAN1_AM09H, val)
-#define bfin_read_CAN1_AM10L() bfin_read16(CAN1_AM10L)
-#define bfin_write_CAN1_AM10L(val) bfin_write16(CAN1_AM10L, val)
-#define bfin_read_CAN1_AM10H() bfin_read16(CAN1_AM10H)
-#define bfin_write_CAN1_AM10H(val) bfin_write16(CAN1_AM10H, val)
-#define bfin_read_CAN1_AM11L() bfin_read16(CAN1_AM11L)
-#define bfin_write_CAN1_AM11L(val) bfin_write16(CAN1_AM11L, val)
-#define bfin_read_CAN1_AM11H() bfin_read16(CAN1_AM11H)
-#define bfin_write_CAN1_AM11H(val) bfin_write16(CAN1_AM11H, val)
-#define bfin_read_CAN1_AM12L() bfin_read16(CAN1_AM12L)
-#define bfin_write_CAN1_AM12L(val) bfin_write16(CAN1_AM12L, val)
-#define bfin_read_CAN1_AM12H() bfin_read16(CAN1_AM12H)
-#define bfin_write_CAN1_AM12H(val) bfin_write16(CAN1_AM12H, val)
-#define bfin_read_CAN1_AM13L() bfin_read16(CAN1_AM13L)
-#define bfin_write_CAN1_AM13L(val) bfin_write16(CAN1_AM13L, val)
-#define bfin_read_CAN1_AM13H() bfin_read16(CAN1_AM13H)
-#define bfin_write_CAN1_AM13H(val) bfin_write16(CAN1_AM13H, val)
-#define bfin_read_CAN1_AM14L() bfin_read16(CAN1_AM14L)
-#define bfin_write_CAN1_AM14L(val) bfin_write16(CAN1_AM14L, val)
-#define bfin_read_CAN1_AM14H() bfin_read16(CAN1_AM14H)
-#define bfin_write_CAN1_AM14H(val) bfin_write16(CAN1_AM14H, val)
-#define bfin_read_CAN1_AM15L() bfin_read16(CAN1_AM15L)
-#define bfin_write_CAN1_AM15L(val) bfin_write16(CAN1_AM15L, val)
-#define bfin_read_CAN1_AM15H() bfin_read16(CAN1_AM15H)
-#define bfin_write_CAN1_AM15H(val) bfin_write16(CAN1_AM15H, val)
-
-/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */
-
-#define bfin_read_CAN1_AM16L() bfin_read16(CAN1_AM16L)
-#define bfin_write_CAN1_AM16L(val) bfin_write16(CAN1_AM16L, val)
-#define bfin_read_CAN1_AM16H() bfin_read16(CAN1_AM16H)
-#define bfin_write_CAN1_AM16H(val) bfin_write16(CAN1_AM16H, val)
-#define bfin_read_CAN1_AM17L() bfin_read16(CAN1_AM17L)
-#define bfin_write_CAN1_AM17L(val) bfin_write16(CAN1_AM17L, val)
-#define bfin_read_CAN1_AM17H() bfin_read16(CAN1_AM17H)
-#define bfin_write_CAN1_AM17H(val) bfin_write16(CAN1_AM17H, val)
-#define bfin_read_CAN1_AM18L() bfin_read16(CAN1_AM18L)
-#define bfin_write_CAN1_AM18L(val) bfin_write16(CAN1_AM18L, val)
-#define bfin_read_CAN1_AM18H() bfin_read16(CAN1_AM18H)
-#define bfin_write_CAN1_AM18H(val) bfin_write16(CAN1_AM18H, val)
-#define bfin_read_CAN1_AM19L() bfin_read16(CAN1_AM19L)
-#define bfin_write_CAN1_AM19L(val) bfin_write16(CAN1_AM19L, val)
-#define bfin_read_CAN1_AM19H() bfin_read16(CAN1_AM19H)
-#define bfin_write_CAN1_AM19H(val) bfin_write16(CAN1_AM19H, val)
-#define bfin_read_CAN1_AM20L() bfin_read16(CAN1_AM20L)
-#define bfin_write_CAN1_AM20L(val) bfin_write16(CAN1_AM20L, val)
-#define bfin_read_CAN1_AM20H() bfin_read16(CAN1_AM20H)
-#define bfin_write_CAN1_AM20H(val) bfin_write16(CAN1_AM20H, val)
-#define bfin_read_CAN1_AM21L() bfin_read16(CAN1_AM21L)
-#define bfin_write_CAN1_AM21L(val) bfin_write16(CAN1_AM21L, val)
-#define bfin_read_CAN1_AM21H() bfin_read16(CAN1_AM21H)
-#define bfin_write_CAN1_AM21H(val) bfin_write16(CAN1_AM21H, val)
-#define bfin_read_CAN1_AM22L() bfin_read16(CAN1_AM22L)
-#define bfin_write_CAN1_AM22L(val) bfin_write16(CAN1_AM22L, val)
-#define bfin_read_CAN1_AM22H() bfin_read16(CAN1_AM22H)
-#define bfin_write_CAN1_AM22H(val) bfin_write16(CAN1_AM22H, val)
-#define bfin_read_CAN1_AM23L() bfin_read16(CAN1_AM23L)
-#define bfin_write_CAN1_AM23L(val) bfin_write16(CAN1_AM23L, val)
-#define bfin_read_CAN1_AM23H() bfin_read16(CAN1_AM23H)
-#define bfin_write_CAN1_AM23H(val) bfin_write16(CAN1_AM23H, val)
-#define bfin_read_CAN1_AM24L() bfin_read16(CAN1_AM24L)
-#define bfin_write_CAN1_AM24L(val) bfin_write16(CAN1_AM24L, val)
-#define bfin_read_CAN1_AM24H() bfin_read16(CAN1_AM24H)
-#define bfin_write_CAN1_AM24H(val) bfin_write16(CAN1_AM24H, val)
-#define bfin_read_CAN1_AM25L() bfin_read16(CAN1_AM25L)
-#define bfin_write_CAN1_AM25L(val) bfin_write16(CAN1_AM25L, val)
-#define bfin_read_CAN1_AM25H() bfin_read16(CAN1_AM25H)
-#define bfin_write_CAN1_AM25H(val) bfin_write16(CAN1_AM25H, val)
-#define bfin_read_CAN1_AM26L() bfin_read16(CAN1_AM26L)
-#define bfin_write_CAN1_AM26L(val) bfin_write16(CAN1_AM26L, val)
-#define bfin_read_CAN1_AM26H() bfin_read16(CAN1_AM26H)
-#define bfin_write_CAN1_AM26H(val) bfin_write16(CAN1_AM26H, val)
-#define bfin_read_CAN1_AM27L() bfin_read16(CAN1_AM27L)
-#define bfin_write_CAN1_AM27L(val) bfin_write16(CAN1_AM27L, val)
-#define bfin_read_CAN1_AM27H() bfin_read16(CAN1_AM27H)
-#define bfin_write_CAN1_AM27H(val) bfin_write16(CAN1_AM27H, val)
-#define bfin_read_CAN1_AM28L() bfin_read16(CAN1_AM28L)
-#define bfin_write_CAN1_AM28L(val) bfin_write16(CAN1_AM28L, val)
-#define bfin_read_CAN1_AM28H() bfin_read16(CAN1_AM28H)
-#define bfin_write_CAN1_AM28H(val) bfin_write16(CAN1_AM28H, val)
-#define bfin_read_CAN1_AM29L() bfin_read16(CAN1_AM29L)
-#define bfin_write_CAN1_AM29L(val) bfin_write16(CAN1_AM29L, val)
-#define bfin_read_CAN1_AM29H() bfin_read16(CAN1_AM29H)
-#define bfin_write_CAN1_AM29H(val) bfin_write16(CAN1_AM29H, val)
-#define bfin_read_CAN1_AM30L() bfin_read16(CAN1_AM30L)
-#define bfin_write_CAN1_AM30L(val) bfin_write16(CAN1_AM30L, val)
-#define bfin_read_CAN1_AM30H() bfin_read16(CAN1_AM30H)
-#define bfin_write_CAN1_AM30H(val) bfin_write16(CAN1_AM30H, val)
-#define bfin_read_CAN1_AM31L() bfin_read16(CAN1_AM31L)
-#define bfin_write_CAN1_AM31L(val) bfin_write16(CAN1_AM31L, val)
-#define bfin_read_CAN1_AM31H() bfin_read16(CAN1_AM31H)
-#define bfin_write_CAN1_AM31H(val) bfin_write16(CAN1_AM31H, val)
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define bfin_read_CAN1_MB00_DATA0() bfin_read16(CAN1_MB00_DATA0)
-#define bfin_write_CAN1_MB00_DATA0(val) bfin_write16(CAN1_MB00_DATA0, val)
-#define bfin_read_CAN1_MB00_DATA1() bfin_read16(CAN1_MB00_DATA1)
-#define bfin_write_CAN1_MB00_DATA1(val) bfin_write16(CAN1_MB00_DATA1, val)
-#define bfin_read_CAN1_MB00_DATA2() bfin_read16(CAN1_MB00_DATA2)
-#define bfin_write_CAN1_MB00_DATA2(val) bfin_write16(CAN1_MB00_DATA2, val)
-#define bfin_read_CAN1_MB00_DATA3() bfin_read16(CAN1_MB00_DATA3)
-#define bfin_write_CAN1_MB00_DATA3(val) bfin_write16(CAN1_MB00_DATA3, val)
-#define bfin_read_CAN1_MB00_LENGTH() bfin_read16(CAN1_MB00_LENGTH)
-#define bfin_write_CAN1_MB00_LENGTH(val) bfin_write16(CAN1_MB00_LENGTH, val)
-#define bfin_read_CAN1_MB00_TIMESTAMP() bfin_read16(CAN1_MB00_TIMESTAMP)
-#define bfin_write_CAN1_MB00_TIMESTAMP(val) bfin_write16(CAN1_MB00_TIMESTAMP, val)
-#define bfin_read_CAN1_MB00_ID0() bfin_read16(CAN1_MB00_ID0)
-#define bfin_write_CAN1_MB00_ID0(val) bfin_write16(CAN1_MB00_ID0, val)
-#define bfin_read_CAN1_MB00_ID1() bfin_read16(CAN1_MB00_ID1)
-#define bfin_write_CAN1_MB00_ID1(val) bfin_write16(CAN1_MB00_ID1, val)
-#define bfin_read_CAN1_MB01_DATA0() bfin_read16(CAN1_MB01_DATA0)
-#define bfin_write_CAN1_MB01_DATA0(val) bfin_write16(CAN1_MB01_DATA0, val)
-#define bfin_read_CAN1_MB01_DATA1() bfin_read16(CAN1_MB01_DATA1)
-#define bfin_write_CAN1_MB01_DATA1(val) bfin_write16(CAN1_MB01_DATA1, val)
-#define bfin_read_CAN1_MB01_DATA2() bfin_read16(CAN1_MB01_DATA2)
-#define bfin_write_CAN1_MB01_DATA2(val) bfin_write16(CAN1_MB01_DATA2, val)
-#define bfin_read_CAN1_MB01_DATA3() bfin_read16(CAN1_MB01_DATA3)
-#define bfin_write_CAN1_MB01_DATA3(val) bfin_write16(CAN1_MB01_DATA3, val)
-#define bfin_read_CAN1_MB01_LENGTH() bfin_read16(CAN1_MB01_LENGTH)
-#define bfin_write_CAN1_MB01_LENGTH(val) bfin_write16(CAN1_MB01_LENGTH, val)
-#define bfin_read_CAN1_MB01_TIMESTAMP() bfin_read16(CAN1_MB01_TIMESTAMP)
-#define bfin_write_CAN1_MB01_TIMESTAMP(val) bfin_write16(CAN1_MB01_TIMESTAMP, val)
-#define bfin_read_CAN1_MB01_ID0() bfin_read16(CAN1_MB01_ID0)
-#define bfin_write_CAN1_MB01_ID0(val) bfin_write16(CAN1_MB01_ID0, val)
-#define bfin_read_CAN1_MB01_ID1() bfin_read16(CAN1_MB01_ID1)
-#define bfin_write_CAN1_MB01_ID1(val) bfin_write16(CAN1_MB01_ID1, val)
-#define bfin_read_CAN1_MB02_DATA0() bfin_read16(CAN1_MB02_DATA0)
-#define bfin_write_CAN1_MB02_DATA0(val) bfin_write16(CAN1_MB02_DATA0, val)
-#define bfin_read_CAN1_MB02_DATA1() bfin_read16(CAN1_MB02_DATA1)
-#define bfin_write_CAN1_MB02_DATA1(val) bfin_write16(CAN1_MB02_DATA1, val)
-#define bfin_read_CAN1_MB02_DATA2() bfin_read16(CAN1_MB02_DATA2)
-#define bfin_write_CAN1_MB02_DATA2(val) bfin_write16(CAN1_MB02_DATA2, val)
-#define bfin_read_CAN1_MB02_DATA3() bfin_read16(CAN1_MB02_DATA3)
-#define bfin_write_CAN1_MB02_DATA3(val) bfin_write16(CAN1_MB02_DATA3, val)
-#define bfin_read_CAN1_MB02_LENGTH() bfin_read16(CAN1_MB02_LENGTH)
-#define bfin_write_CAN1_MB02_LENGTH(val) bfin_write16(CAN1_MB02_LENGTH, val)
-#define bfin_read_CAN1_MB02_TIMESTAMP() bfin_read16(CAN1_MB02_TIMESTAMP)
-#define bfin_write_CAN1_MB02_TIMESTAMP(val) bfin_write16(CAN1_MB02_TIMESTAMP, val)
-#define bfin_read_CAN1_MB02_ID0() bfin_read16(CAN1_MB02_ID0)
-#define bfin_write_CAN1_MB02_ID0(val) bfin_write16(CAN1_MB02_ID0, val)
-#define bfin_read_CAN1_MB02_ID1() bfin_read16(CAN1_MB02_ID1)
-#define bfin_write_CAN1_MB02_ID1(val) bfin_write16(CAN1_MB02_ID1, val)
-#define bfin_read_CAN1_MB03_DATA0() bfin_read16(CAN1_MB03_DATA0)
-#define bfin_write_CAN1_MB03_DATA0(val) bfin_write16(CAN1_MB03_DATA0, val)
-#define bfin_read_CAN1_MB03_DATA1() bfin_read16(CAN1_MB03_DATA1)
-#define bfin_write_CAN1_MB03_DATA1(val) bfin_write16(CAN1_MB03_DATA1, val)
-#define bfin_read_CAN1_MB03_DATA2() bfin_read16(CAN1_MB03_DATA2)
-#define bfin_write_CAN1_MB03_DATA2(val) bfin_write16(CAN1_MB03_DATA2, val)
-#define bfin_read_CAN1_MB03_DATA3() bfin_read16(CAN1_MB03_DATA3)
-#define bfin_write_CAN1_MB03_DATA3(val) bfin_write16(CAN1_MB03_DATA3, val)
-#define bfin_read_CAN1_MB03_LENGTH() bfin_read16(CAN1_MB03_LENGTH)
-#define bfin_write_CAN1_MB03_LENGTH(val) bfin_write16(CAN1_MB03_LENGTH, val)
-#define bfin_read_CAN1_MB03_TIMESTAMP() bfin_read16(CAN1_MB03_TIMESTAMP)
-#define bfin_write_CAN1_MB03_TIMESTAMP(val) bfin_write16(CAN1_MB03_TIMESTAMP, val)
-#define bfin_read_CAN1_MB03_ID0() bfin_read16(CAN1_MB03_ID0)
-#define bfin_write_CAN1_MB03_ID0(val) bfin_write16(CAN1_MB03_ID0, val)
-#define bfin_read_CAN1_MB03_ID1() bfin_read16(CAN1_MB03_ID1)
-#define bfin_write_CAN1_MB03_ID1(val) bfin_write16(CAN1_MB03_ID1, val)
-#define bfin_read_CAN1_MB04_DATA0() bfin_read16(CAN1_MB04_DATA0)
-#define bfin_write_CAN1_MB04_DATA0(val) bfin_write16(CAN1_MB04_DATA0, val)
-#define bfin_read_CAN1_MB04_DATA1() bfin_read16(CAN1_MB04_DATA1)
-#define bfin_write_CAN1_MB04_DATA1(val) bfin_write16(CAN1_MB04_DATA1, val)
-#define bfin_read_CAN1_MB04_DATA2() bfin_read16(CAN1_MB04_DATA2)
-#define bfin_write_CAN1_MB04_DATA2(val) bfin_write16(CAN1_MB04_DATA2, val)
-#define bfin_read_CAN1_MB04_DATA3() bfin_read16(CAN1_MB04_DATA3)
-#define bfin_write_CAN1_MB04_DATA3(val) bfin_write16(CAN1_MB04_DATA3, val)
-#define bfin_read_CAN1_MB04_LENGTH() bfin_read16(CAN1_MB04_LENGTH)
-#define bfin_write_CAN1_MB04_LENGTH(val) bfin_write16(CAN1_MB04_LENGTH, val)
-#define bfin_read_CAN1_MB04_TIMESTAMP() bfin_read16(CAN1_MB04_TIMESTAMP)
-#define bfin_write_CAN1_MB04_TIMESTAMP(val) bfin_write16(CAN1_MB04_TIMESTAMP, val)
-#define bfin_read_CAN1_MB04_ID0() bfin_read16(CAN1_MB04_ID0)
-#define bfin_write_CAN1_MB04_ID0(val) bfin_write16(CAN1_MB04_ID0, val)
-#define bfin_read_CAN1_MB04_ID1() bfin_read16(CAN1_MB04_ID1)
-#define bfin_write_CAN1_MB04_ID1(val) bfin_write16(CAN1_MB04_ID1, val)
-#define bfin_read_CAN1_MB05_DATA0() bfin_read16(CAN1_MB05_DATA0)
-#define bfin_write_CAN1_MB05_DATA0(val) bfin_write16(CAN1_MB05_DATA0, val)
-#define bfin_read_CAN1_MB05_DATA1() bfin_read16(CAN1_MB05_DATA1)
-#define bfin_write_CAN1_MB05_DATA1(val) bfin_write16(CAN1_MB05_DATA1, val)
-#define bfin_read_CAN1_MB05_DATA2() bfin_read16(CAN1_MB05_DATA2)
-#define bfin_write_CAN1_MB05_DATA2(val) bfin_write16(CAN1_MB05_DATA2, val)
-#define bfin_read_CAN1_MB05_DATA3() bfin_read16(CAN1_MB05_DATA3)
-#define bfin_write_CAN1_MB05_DATA3(val) bfin_write16(CAN1_MB05_DATA3, val)
-#define bfin_read_CAN1_MB05_LENGTH() bfin_read16(CAN1_MB05_LENGTH)
-#define bfin_write_CAN1_MB05_LENGTH(val) bfin_write16(CAN1_MB05_LENGTH, val)
-#define bfin_read_CAN1_MB05_TIMESTAMP() bfin_read16(CAN1_MB05_TIMESTAMP)
-#define bfin_write_CAN1_MB05_TIMESTAMP(val) bfin_write16(CAN1_MB05_TIMESTAMP, val)
-#define bfin_read_CAN1_MB05_ID0() bfin_read16(CAN1_MB05_ID0)
-#define bfin_write_CAN1_MB05_ID0(val) bfin_write16(CAN1_MB05_ID0, val)
-#define bfin_read_CAN1_MB05_ID1() bfin_read16(CAN1_MB05_ID1)
-#define bfin_write_CAN1_MB05_ID1(val) bfin_write16(CAN1_MB05_ID1, val)
-#define bfin_read_CAN1_MB06_DATA0() bfin_read16(CAN1_MB06_DATA0)
-#define bfin_write_CAN1_MB06_DATA0(val) bfin_write16(CAN1_MB06_DATA0, val)
-#define bfin_read_CAN1_MB06_DATA1() bfin_read16(CAN1_MB06_DATA1)
-#define bfin_write_CAN1_MB06_DATA1(val) bfin_write16(CAN1_MB06_DATA1, val)
-#define bfin_read_CAN1_MB06_DATA2() bfin_read16(CAN1_MB06_DATA2)
-#define bfin_write_CAN1_MB06_DATA2(val) bfin_write16(CAN1_MB06_DATA2, val)
-#define bfin_read_CAN1_MB06_DATA3() bfin_read16(CAN1_MB06_DATA3)
-#define bfin_write_CAN1_MB06_DATA3(val) bfin_write16(CAN1_MB06_DATA3, val)
-#define bfin_read_CAN1_MB06_LENGTH() bfin_read16(CAN1_MB06_LENGTH)
-#define bfin_write_CAN1_MB06_LENGTH(val) bfin_write16(CAN1_MB06_LENGTH, val)
-#define bfin_read_CAN1_MB06_TIMESTAMP() bfin_read16(CAN1_MB06_TIMESTAMP)
-#define bfin_write_CAN1_MB06_TIMESTAMP(val) bfin_write16(CAN1_MB06_TIMESTAMP, val)
-#define bfin_read_CAN1_MB06_ID0() bfin_read16(CAN1_MB06_ID0)
-#define bfin_write_CAN1_MB06_ID0(val) bfin_write16(CAN1_MB06_ID0, val)
-#define bfin_read_CAN1_MB06_ID1() bfin_read16(CAN1_MB06_ID1)
-#define bfin_write_CAN1_MB06_ID1(val) bfin_write16(CAN1_MB06_ID1, val)
-#define bfin_read_CAN1_MB07_DATA0() bfin_read16(CAN1_MB07_DATA0)
-#define bfin_write_CAN1_MB07_DATA0(val) bfin_write16(CAN1_MB07_DATA0, val)
-#define bfin_read_CAN1_MB07_DATA1() bfin_read16(CAN1_MB07_DATA1)
-#define bfin_write_CAN1_MB07_DATA1(val) bfin_write16(CAN1_MB07_DATA1, val)
-#define bfin_read_CAN1_MB07_DATA2() bfin_read16(CAN1_MB07_DATA2)
-#define bfin_write_CAN1_MB07_DATA2(val) bfin_write16(CAN1_MB07_DATA2, val)
-#define bfin_read_CAN1_MB07_DATA3() bfin_read16(CAN1_MB07_DATA3)
-#define bfin_write_CAN1_MB07_DATA3(val) bfin_write16(CAN1_MB07_DATA3, val)
-#define bfin_read_CAN1_MB07_LENGTH() bfin_read16(CAN1_MB07_LENGTH)
-#define bfin_write_CAN1_MB07_LENGTH(val) bfin_write16(CAN1_MB07_LENGTH, val)
-#define bfin_read_CAN1_MB07_TIMESTAMP() bfin_read16(CAN1_MB07_TIMESTAMP)
-#define bfin_write_CAN1_MB07_TIMESTAMP(val) bfin_write16(CAN1_MB07_TIMESTAMP, val)
-#define bfin_read_CAN1_MB07_ID0() bfin_read16(CAN1_MB07_ID0)
-#define bfin_write_CAN1_MB07_ID0(val) bfin_write16(CAN1_MB07_ID0, val)
-#define bfin_read_CAN1_MB07_ID1() bfin_read16(CAN1_MB07_ID1)
-#define bfin_write_CAN1_MB07_ID1(val) bfin_write16(CAN1_MB07_ID1, val)
-#define bfin_read_CAN1_MB08_DATA0() bfin_read16(CAN1_MB08_DATA0)
-#define bfin_write_CAN1_MB08_DATA0(val) bfin_write16(CAN1_MB08_DATA0, val)
-#define bfin_read_CAN1_MB08_DATA1() bfin_read16(CAN1_MB08_DATA1)
-#define bfin_write_CAN1_MB08_DATA1(val) bfin_write16(CAN1_MB08_DATA1, val)
-#define bfin_read_CAN1_MB08_DATA2() bfin_read16(CAN1_MB08_DATA2)
-#define bfin_write_CAN1_MB08_DATA2(val) bfin_write16(CAN1_MB08_DATA2, val)
-#define bfin_read_CAN1_MB08_DATA3() bfin_read16(CAN1_MB08_DATA3)
-#define bfin_write_CAN1_MB08_DATA3(val) bfin_write16(CAN1_MB08_DATA3, val)
-#define bfin_read_CAN1_MB08_LENGTH() bfin_read16(CAN1_MB08_LENGTH)
-#define bfin_write_CAN1_MB08_LENGTH(val) bfin_write16(CAN1_MB08_LENGTH, val)
-#define bfin_read_CAN1_MB08_TIMESTAMP() bfin_read16(CAN1_MB08_TIMESTAMP)
-#define bfin_write_CAN1_MB08_TIMESTAMP(val) bfin_write16(CAN1_MB08_TIMESTAMP, val)
-#define bfin_read_CAN1_MB08_ID0() bfin_read16(CAN1_MB08_ID0)
-#define bfin_write_CAN1_MB08_ID0(val) bfin_write16(CAN1_MB08_ID0, val)
-#define bfin_read_CAN1_MB08_ID1() bfin_read16(CAN1_MB08_ID1)
-#define bfin_write_CAN1_MB08_ID1(val) bfin_write16(CAN1_MB08_ID1, val)
-#define bfin_read_CAN1_MB09_DATA0() bfin_read16(CAN1_MB09_DATA0)
-#define bfin_write_CAN1_MB09_DATA0(val) bfin_write16(CAN1_MB09_DATA0, val)
-#define bfin_read_CAN1_MB09_DATA1() bfin_read16(CAN1_MB09_DATA1)
-#define bfin_write_CAN1_MB09_DATA1(val) bfin_write16(CAN1_MB09_DATA1, val)
-#define bfin_read_CAN1_MB09_DATA2() bfin_read16(CAN1_MB09_DATA2)
-#define bfin_write_CAN1_MB09_DATA2(val) bfin_write16(CAN1_MB09_DATA2, val)
-#define bfin_read_CAN1_MB09_DATA3() bfin_read16(CAN1_MB09_DATA3)
-#define bfin_write_CAN1_MB09_DATA3(val) bfin_write16(CAN1_MB09_DATA3, val)
-#define bfin_read_CAN1_MB09_LENGTH() bfin_read16(CAN1_MB09_LENGTH)
-#define bfin_write_CAN1_MB09_LENGTH(val) bfin_write16(CAN1_MB09_LENGTH, val)
-#define bfin_read_CAN1_MB09_TIMESTAMP() bfin_read16(CAN1_MB09_TIMESTAMP)
-#define bfin_write_CAN1_MB09_TIMESTAMP(val) bfin_write16(CAN1_MB09_TIMESTAMP, val)
-#define bfin_read_CAN1_MB09_ID0() bfin_read16(CAN1_MB09_ID0)
-#define bfin_write_CAN1_MB09_ID0(val) bfin_write16(CAN1_MB09_ID0, val)
-#define bfin_read_CAN1_MB09_ID1() bfin_read16(CAN1_MB09_ID1)
-#define bfin_write_CAN1_MB09_ID1(val) bfin_write16(CAN1_MB09_ID1, val)
-#define bfin_read_CAN1_MB10_DATA0() bfin_read16(CAN1_MB10_DATA0)
-#define bfin_write_CAN1_MB10_DATA0(val) bfin_write16(CAN1_MB10_DATA0, val)
-#define bfin_read_CAN1_MB10_DATA1() bfin_read16(CAN1_MB10_DATA1)
-#define bfin_write_CAN1_MB10_DATA1(val) bfin_write16(CAN1_MB10_DATA1, val)
-#define bfin_read_CAN1_MB10_DATA2() bfin_read16(CAN1_MB10_DATA2)
-#define bfin_write_CAN1_MB10_DATA2(val) bfin_write16(CAN1_MB10_DATA2, val)
-#define bfin_read_CAN1_MB10_DATA3() bfin_read16(CAN1_MB10_DATA3)
-#define bfin_write_CAN1_MB10_DATA3(val) bfin_write16(CAN1_MB10_DATA3, val)
-#define bfin_read_CAN1_MB10_LENGTH() bfin_read16(CAN1_MB10_LENGTH)
-#define bfin_write_CAN1_MB10_LENGTH(val) bfin_write16(CAN1_MB10_LENGTH, val)
-#define bfin_read_CAN1_MB10_TIMESTAMP() bfin_read16(CAN1_MB10_TIMESTAMP)
-#define bfin_write_CAN1_MB10_TIMESTAMP(val) bfin_write16(CAN1_MB10_TIMESTAMP, val)
-#define bfin_read_CAN1_MB10_ID0() bfin_read16(CAN1_MB10_ID0)
-#define bfin_write_CAN1_MB10_ID0(val) bfin_write16(CAN1_MB10_ID0, val)
-#define bfin_read_CAN1_MB10_ID1() bfin_read16(CAN1_MB10_ID1)
-#define bfin_write_CAN1_MB10_ID1(val) bfin_write16(CAN1_MB10_ID1, val)
-#define bfin_read_CAN1_MB11_DATA0() bfin_read16(CAN1_MB11_DATA0)
-#define bfin_write_CAN1_MB11_DATA0(val) bfin_write16(CAN1_MB11_DATA0, val)
-#define bfin_read_CAN1_MB11_DATA1() bfin_read16(CAN1_MB11_DATA1)
-#define bfin_write_CAN1_MB11_DATA1(val) bfin_write16(CAN1_MB11_DATA1, val)
-#define bfin_read_CAN1_MB11_DATA2() bfin_read16(CAN1_MB11_DATA2)
-#define bfin_write_CAN1_MB11_DATA2(val) bfin_write16(CAN1_MB11_DATA2, val)
-#define bfin_read_CAN1_MB11_DATA3() bfin_read16(CAN1_MB11_DATA3)
-#define bfin_write_CAN1_MB11_DATA3(val) bfin_write16(CAN1_MB11_DATA3, val)
-#define bfin_read_CAN1_MB11_LENGTH() bfin_read16(CAN1_MB11_LENGTH)
-#define bfin_write_CAN1_MB11_LENGTH(val) bfin_write16(CAN1_MB11_LENGTH, val)
-#define bfin_read_CAN1_MB11_TIMESTAMP() bfin_read16(CAN1_MB11_TIMESTAMP)
-#define bfin_write_CAN1_MB11_TIMESTAMP(val) bfin_write16(CAN1_MB11_TIMESTAMP, val)
-#define bfin_read_CAN1_MB11_ID0() bfin_read16(CAN1_MB11_ID0)
-#define bfin_write_CAN1_MB11_ID0(val) bfin_write16(CAN1_MB11_ID0, val)
-#define bfin_read_CAN1_MB11_ID1() bfin_read16(CAN1_MB11_ID1)
-#define bfin_write_CAN1_MB11_ID1(val) bfin_write16(CAN1_MB11_ID1, val)
-#define bfin_read_CAN1_MB12_DATA0() bfin_read16(CAN1_MB12_DATA0)
-#define bfin_write_CAN1_MB12_DATA0(val) bfin_write16(CAN1_MB12_DATA0, val)
-#define bfin_read_CAN1_MB12_DATA1() bfin_read16(CAN1_MB12_DATA1)
-#define bfin_write_CAN1_MB12_DATA1(val) bfin_write16(CAN1_MB12_DATA1, val)
-#define bfin_read_CAN1_MB12_DATA2() bfin_read16(CAN1_MB12_DATA2)
-#define bfin_write_CAN1_MB12_DATA2(val) bfin_write16(CAN1_MB12_DATA2, val)
-#define bfin_read_CAN1_MB12_DATA3() bfin_read16(CAN1_MB12_DATA3)
-#define bfin_write_CAN1_MB12_DATA3(val) bfin_write16(CAN1_MB12_DATA3, val)
-#define bfin_read_CAN1_MB12_LENGTH() bfin_read16(CAN1_MB12_LENGTH)
-#define bfin_write_CAN1_MB12_LENGTH(val) bfin_write16(CAN1_MB12_LENGTH, val)
-#define bfin_read_CAN1_MB12_TIMESTAMP() bfin_read16(CAN1_MB12_TIMESTAMP)
-#define bfin_write_CAN1_MB12_TIMESTAMP(val) bfin_write16(CAN1_MB12_TIMESTAMP, val)
-#define bfin_read_CAN1_MB12_ID0() bfin_read16(CAN1_MB12_ID0)
-#define bfin_write_CAN1_MB12_ID0(val) bfin_write16(CAN1_MB12_ID0, val)
-#define bfin_read_CAN1_MB12_ID1() bfin_read16(CAN1_MB12_ID1)
-#define bfin_write_CAN1_MB12_ID1(val) bfin_write16(CAN1_MB12_ID1, val)
-#define bfin_read_CAN1_MB13_DATA0() bfin_read16(CAN1_MB13_DATA0)
-#define bfin_write_CAN1_MB13_DATA0(val) bfin_write16(CAN1_MB13_DATA0, val)
-#define bfin_read_CAN1_MB13_DATA1() bfin_read16(CAN1_MB13_DATA1)
-#define bfin_write_CAN1_MB13_DATA1(val) bfin_write16(CAN1_MB13_DATA1, val)
-#define bfin_read_CAN1_MB13_DATA2() bfin_read16(CAN1_MB13_DATA2)
-#define bfin_write_CAN1_MB13_DATA2(val) bfin_write16(CAN1_MB13_DATA2, val)
-#define bfin_read_CAN1_MB13_DATA3() bfin_read16(CAN1_MB13_DATA3)
-#define bfin_write_CAN1_MB13_DATA3(val) bfin_write16(CAN1_MB13_DATA3, val)
-#define bfin_read_CAN1_MB13_LENGTH() bfin_read16(CAN1_MB13_LENGTH)
-#define bfin_write_CAN1_MB13_LENGTH(val) bfin_write16(CAN1_MB13_LENGTH, val)
-#define bfin_read_CAN1_MB13_TIMESTAMP() bfin_read16(CAN1_MB13_TIMESTAMP)
-#define bfin_write_CAN1_MB13_TIMESTAMP(val) bfin_write16(CAN1_MB13_TIMESTAMP, val)
-#define bfin_read_CAN1_MB13_ID0() bfin_read16(CAN1_MB13_ID0)
-#define bfin_write_CAN1_MB13_ID0(val) bfin_write16(CAN1_MB13_ID0, val)
-#define bfin_read_CAN1_MB13_ID1() bfin_read16(CAN1_MB13_ID1)
-#define bfin_write_CAN1_MB13_ID1(val) bfin_write16(CAN1_MB13_ID1, val)
-#define bfin_read_CAN1_MB14_DATA0() bfin_read16(CAN1_MB14_DATA0)
-#define bfin_write_CAN1_MB14_DATA0(val) bfin_write16(CAN1_MB14_DATA0, val)
-#define bfin_read_CAN1_MB14_DATA1() bfin_read16(CAN1_MB14_DATA1)
-#define bfin_write_CAN1_MB14_DATA1(val) bfin_write16(CAN1_MB14_DATA1, val)
-#define bfin_read_CAN1_MB14_DATA2() bfin_read16(CAN1_MB14_DATA2)
-#define bfin_write_CAN1_MB14_DATA2(val) bfin_write16(CAN1_MB14_DATA2, val)
-#define bfin_read_CAN1_MB14_DATA3() bfin_read16(CAN1_MB14_DATA3)
-#define bfin_write_CAN1_MB14_DATA3(val) bfin_write16(CAN1_MB14_DATA3, val)
-#define bfin_read_CAN1_MB14_LENGTH() bfin_read16(CAN1_MB14_LENGTH)
-#define bfin_write_CAN1_MB14_LENGTH(val) bfin_write16(CAN1_MB14_LENGTH, val)
-#define bfin_read_CAN1_MB14_TIMESTAMP() bfin_read16(CAN1_MB14_TIMESTAMP)
-#define bfin_write_CAN1_MB14_TIMESTAMP(val) bfin_write16(CAN1_MB14_TIMESTAMP, val)
-#define bfin_read_CAN1_MB14_ID0() bfin_read16(CAN1_MB14_ID0)
-#define bfin_write_CAN1_MB14_ID0(val) bfin_write16(CAN1_MB14_ID0, val)
-#define bfin_read_CAN1_MB14_ID1() bfin_read16(CAN1_MB14_ID1)
-#define bfin_write_CAN1_MB14_ID1(val) bfin_write16(CAN1_MB14_ID1, val)
-#define bfin_read_CAN1_MB15_DATA0() bfin_read16(CAN1_MB15_DATA0)
-#define bfin_write_CAN1_MB15_DATA0(val) bfin_write16(CAN1_MB15_DATA0, val)
-#define bfin_read_CAN1_MB15_DATA1() bfin_read16(CAN1_MB15_DATA1)
-#define bfin_write_CAN1_MB15_DATA1(val) bfin_write16(CAN1_MB15_DATA1, val)
-#define bfin_read_CAN1_MB15_DATA2() bfin_read16(CAN1_MB15_DATA2)
-#define bfin_write_CAN1_MB15_DATA2(val) bfin_write16(CAN1_MB15_DATA2, val)
-#define bfin_read_CAN1_MB15_DATA3() bfin_read16(CAN1_MB15_DATA3)
-#define bfin_write_CAN1_MB15_DATA3(val) bfin_write16(CAN1_MB15_DATA3, val)
-#define bfin_read_CAN1_MB15_LENGTH() bfin_read16(CAN1_MB15_LENGTH)
-#define bfin_write_CAN1_MB15_LENGTH(val) bfin_write16(CAN1_MB15_LENGTH, val)
-#define bfin_read_CAN1_MB15_TIMESTAMP() bfin_read16(CAN1_MB15_TIMESTAMP)
-#define bfin_write_CAN1_MB15_TIMESTAMP(val) bfin_write16(CAN1_MB15_TIMESTAMP, val)
-#define bfin_read_CAN1_MB15_ID0() bfin_read16(CAN1_MB15_ID0)
-#define bfin_write_CAN1_MB15_ID0(val) bfin_write16(CAN1_MB15_ID0, val)
-#define bfin_read_CAN1_MB15_ID1() bfin_read16(CAN1_MB15_ID1)
-#define bfin_write_CAN1_MB15_ID1(val) bfin_write16(CAN1_MB15_ID1, val)
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define bfin_read_CAN1_MB16_DATA0() bfin_read16(CAN1_MB16_DATA0)
-#define bfin_write_CAN1_MB16_DATA0(val) bfin_write16(CAN1_MB16_DATA0, val)
-#define bfin_read_CAN1_MB16_DATA1() bfin_read16(CAN1_MB16_DATA1)
-#define bfin_write_CAN1_MB16_DATA1(val) bfin_write16(CAN1_MB16_DATA1, val)
-#define bfin_read_CAN1_MB16_DATA2() bfin_read16(CAN1_MB16_DATA2)
-#define bfin_write_CAN1_MB16_DATA2(val) bfin_write16(CAN1_MB16_DATA2, val)
-#define bfin_read_CAN1_MB16_DATA3() bfin_read16(CAN1_MB16_DATA3)
-#define bfin_write_CAN1_MB16_DATA3(val) bfin_write16(CAN1_MB16_DATA3, val)
-#define bfin_read_CAN1_MB16_LENGTH() bfin_read16(CAN1_MB16_LENGTH)
-#define bfin_write_CAN1_MB16_LENGTH(val) bfin_write16(CAN1_MB16_LENGTH, val)
-#define bfin_read_CAN1_MB16_TIMESTAMP() bfin_read16(CAN1_MB16_TIMESTAMP)
-#define bfin_write_CAN1_MB16_TIMESTAMP(val) bfin_write16(CAN1_MB16_TIMESTAMP, val)
-#define bfin_read_CAN1_MB16_ID0() bfin_read16(CAN1_MB16_ID0)
-#define bfin_write_CAN1_MB16_ID0(val) bfin_write16(CAN1_MB16_ID0, val)
-#define bfin_read_CAN1_MB16_ID1() bfin_read16(CAN1_MB16_ID1)
-#define bfin_write_CAN1_MB16_ID1(val) bfin_write16(CAN1_MB16_ID1, val)
-#define bfin_read_CAN1_MB17_DATA0() bfin_read16(CAN1_MB17_DATA0)
-#define bfin_write_CAN1_MB17_DATA0(val) bfin_write16(CAN1_MB17_DATA0, val)
-#define bfin_read_CAN1_MB17_DATA1() bfin_read16(CAN1_MB17_DATA1)
-#define bfin_write_CAN1_MB17_DATA1(val) bfin_write16(CAN1_MB17_DATA1, val)
-#define bfin_read_CAN1_MB17_DATA2() bfin_read16(CAN1_MB17_DATA2)
-#define bfin_write_CAN1_MB17_DATA2(val) bfin_write16(CAN1_MB17_DATA2, val)
-#define bfin_read_CAN1_MB17_DATA3() bfin_read16(CAN1_MB17_DATA3)
-#define bfin_write_CAN1_MB17_DATA3(val) bfin_write16(CAN1_MB17_DATA3, val)
-#define bfin_read_CAN1_MB17_LENGTH() bfin_read16(CAN1_MB17_LENGTH)
-#define bfin_write_CAN1_MB17_LENGTH(val) bfin_write16(CAN1_MB17_LENGTH, val)
-#define bfin_read_CAN1_MB17_TIMESTAMP() bfin_read16(CAN1_MB17_TIMESTAMP)
-#define bfin_write_CAN1_MB17_TIMESTAMP(val) bfin_write16(CAN1_MB17_TIMESTAMP, val)
-#define bfin_read_CAN1_MB17_ID0() bfin_read16(CAN1_MB17_ID0)
-#define bfin_write_CAN1_MB17_ID0(val) bfin_write16(CAN1_MB17_ID0, val)
-#define bfin_read_CAN1_MB17_ID1() bfin_read16(CAN1_MB17_ID1)
-#define bfin_write_CAN1_MB17_ID1(val) bfin_write16(CAN1_MB17_ID1, val)
-#define bfin_read_CAN1_MB18_DATA0() bfin_read16(CAN1_MB18_DATA0)
-#define bfin_write_CAN1_MB18_DATA0(val) bfin_write16(CAN1_MB18_DATA0, val)
-#define bfin_read_CAN1_MB18_DATA1() bfin_read16(CAN1_MB18_DATA1)
-#define bfin_write_CAN1_MB18_DATA1(val) bfin_write16(CAN1_MB18_DATA1, val)
-#define bfin_read_CAN1_MB18_DATA2() bfin_read16(CAN1_MB18_DATA2)
-#define bfin_write_CAN1_MB18_DATA2(val) bfin_write16(CAN1_MB18_DATA2, val)
-#define bfin_read_CAN1_MB18_DATA3() bfin_read16(CAN1_MB18_DATA3)
-#define bfin_write_CAN1_MB18_DATA3(val) bfin_write16(CAN1_MB18_DATA3, val)
-#define bfin_read_CAN1_MB18_LENGTH() bfin_read16(CAN1_MB18_LENGTH)
-#define bfin_write_CAN1_MB18_LENGTH(val) bfin_write16(CAN1_MB18_LENGTH, val)
-#define bfin_read_CAN1_MB18_TIMESTAMP() bfin_read16(CAN1_MB18_TIMESTAMP)
-#define bfin_write_CAN1_MB18_TIMESTAMP(val) bfin_write16(CAN1_MB18_TIMESTAMP, val)
-#define bfin_read_CAN1_MB18_ID0() bfin_read16(CAN1_MB18_ID0)
-#define bfin_write_CAN1_MB18_ID0(val) bfin_write16(CAN1_MB18_ID0, val)
-#define bfin_read_CAN1_MB18_ID1() bfin_read16(CAN1_MB18_ID1)
-#define bfin_write_CAN1_MB18_ID1(val) bfin_write16(CAN1_MB18_ID1, val)
-#define bfin_read_CAN1_MB19_DATA0() bfin_read16(CAN1_MB19_DATA0)
-#define bfin_write_CAN1_MB19_DATA0(val) bfin_write16(CAN1_MB19_DATA0, val)
-#define bfin_read_CAN1_MB19_DATA1() bfin_read16(CAN1_MB19_DATA1)
-#define bfin_write_CAN1_MB19_DATA1(val) bfin_write16(CAN1_MB19_DATA1, val)
-#define bfin_read_CAN1_MB19_DATA2() bfin_read16(CAN1_MB19_DATA2)
-#define bfin_write_CAN1_MB19_DATA2(val) bfin_write16(CAN1_MB19_DATA2, val)
-#define bfin_read_CAN1_MB19_DATA3() bfin_read16(CAN1_MB19_DATA3)
-#define bfin_write_CAN1_MB19_DATA3(val) bfin_write16(CAN1_MB19_DATA3, val)
-#define bfin_read_CAN1_MB19_LENGTH() bfin_read16(CAN1_MB19_LENGTH)
-#define bfin_write_CAN1_MB19_LENGTH(val) bfin_write16(CAN1_MB19_LENGTH, val)
-#define bfin_read_CAN1_MB19_TIMESTAMP() bfin_read16(CAN1_MB19_TIMESTAMP)
-#define bfin_write_CAN1_MB19_TIMESTAMP(val) bfin_write16(CAN1_MB19_TIMESTAMP, val)
-#define bfin_read_CAN1_MB19_ID0() bfin_read16(CAN1_MB19_ID0)
-#define bfin_write_CAN1_MB19_ID0(val) bfin_write16(CAN1_MB19_ID0, val)
-#define bfin_read_CAN1_MB19_ID1() bfin_read16(CAN1_MB19_ID1)
-#define bfin_write_CAN1_MB19_ID1(val) bfin_write16(CAN1_MB19_ID1, val)
-#define bfin_read_CAN1_MB20_DATA0() bfin_read16(CAN1_MB20_DATA0)
-#define bfin_write_CAN1_MB20_DATA0(val) bfin_write16(CAN1_MB20_DATA0, val)
-#define bfin_read_CAN1_MB20_DATA1() bfin_read16(CAN1_MB20_DATA1)
-#define bfin_write_CAN1_MB20_DATA1(val) bfin_write16(CAN1_MB20_DATA1, val)
-#define bfin_read_CAN1_MB20_DATA2() bfin_read16(CAN1_MB20_DATA2)
-#define bfin_write_CAN1_MB20_DATA2(val) bfin_write16(CAN1_MB20_DATA2, val)
-#define bfin_read_CAN1_MB20_DATA3() bfin_read16(CAN1_MB20_DATA3)
-#define bfin_write_CAN1_MB20_DATA3(val) bfin_write16(CAN1_MB20_DATA3, val)
-#define bfin_read_CAN1_MB20_LENGTH() bfin_read16(CAN1_MB20_LENGTH)
-#define bfin_write_CAN1_MB20_LENGTH(val) bfin_write16(CAN1_MB20_LENGTH, val)
-#define bfin_read_CAN1_MB20_TIMESTAMP() bfin_read16(CAN1_MB20_TIMESTAMP)
-#define bfin_write_CAN1_MB20_TIMESTAMP(val) bfin_write16(CAN1_MB20_TIMESTAMP, val)
-#define bfin_read_CAN1_MB20_ID0() bfin_read16(CAN1_MB20_ID0)
-#define bfin_write_CAN1_MB20_ID0(val) bfin_write16(CAN1_MB20_ID0, val)
-#define bfin_read_CAN1_MB20_ID1() bfin_read16(CAN1_MB20_ID1)
-#define bfin_write_CAN1_MB20_ID1(val) bfin_write16(CAN1_MB20_ID1, val)
-#define bfin_read_CAN1_MB21_DATA0() bfin_read16(CAN1_MB21_DATA0)
-#define bfin_write_CAN1_MB21_DATA0(val) bfin_write16(CAN1_MB21_DATA0, val)
-#define bfin_read_CAN1_MB21_DATA1() bfin_read16(CAN1_MB21_DATA1)
-#define bfin_write_CAN1_MB21_DATA1(val) bfin_write16(CAN1_MB21_DATA1, val)
-#define bfin_read_CAN1_MB21_DATA2() bfin_read16(CAN1_MB21_DATA2)
-#define bfin_write_CAN1_MB21_DATA2(val) bfin_write16(CAN1_MB21_DATA2, val)
-#define bfin_read_CAN1_MB21_DATA3() bfin_read16(CAN1_MB21_DATA3)
-#define bfin_write_CAN1_MB21_DATA3(val) bfin_write16(CAN1_MB21_DATA3, val)
-#define bfin_read_CAN1_MB21_LENGTH() bfin_read16(CAN1_MB21_LENGTH)
-#define bfin_write_CAN1_MB21_LENGTH(val) bfin_write16(CAN1_MB21_LENGTH, val)
-#define bfin_read_CAN1_MB21_TIMESTAMP() bfin_read16(CAN1_MB21_TIMESTAMP)
-#define bfin_write_CAN1_MB21_TIMESTAMP(val) bfin_write16(CAN1_MB21_TIMESTAMP, val)
-#define bfin_read_CAN1_MB21_ID0() bfin_read16(CAN1_MB21_ID0)
-#define bfin_write_CAN1_MB21_ID0(val) bfin_write16(CAN1_MB21_ID0, val)
-#define bfin_read_CAN1_MB21_ID1() bfin_read16(CAN1_MB21_ID1)
-#define bfin_write_CAN1_MB21_ID1(val) bfin_write16(CAN1_MB21_ID1, val)
-#define bfin_read_CAN1_MB22_DATA0() bfin_read16(CAN1_MB22_DATA0)
-#define bfin_write_CAN1_MB22_DATA0(val) bfin_write16(CAN1_MB22_DATA0, val)
-#define bfin_read_CAN1_MB22_DATA1() bfin_read16(CAN1_MB22_DATA1)
-#define bfin_write_CAN1_MB22_DATA1(val) bfin_write16(CAN1_MB22_DATA1, val)
-#define bfin_read_CAN1_MB22_DATA2() bfin_read16(CAN1_MB22_DATA2)
-#define bfin_write_CAN1_MB22_DATA2(val) bfin_write16(CAN1_MB22_DATA2, val)
-#define bfin_read_CAN1_MB22_DATA3() bfin_read16(CAN1_MB22_DATA3)
-#define bfin_write_CAN1_MB22_DATA3(val) bfin_write16(CAN1_MB22_DATA3, val)
-#define bfin_read_CAN1_MB22_LENGTH() bfin_read16(CAN1_MB22_LENGTH)
-#define bfin_write_CAN1_MB22_LENGTH(val) bfin_write16(CAN1_MB22_LENGTH, val)
-#define bfin_read_CAN1_MB22_TIMESTAMP() bfin_read16(CAN1_MB22_TIMESTAMP)
-#define bfin_write_CAN1_MB22_TIMESTAMP(val) bfin_write16(CAN1_MB22_TIMESTAMP, val)
-#define bfin_read_CAN1_MB22_ID0() bfin_read16(CAN1_MB22_ID0)
-#define bfin_write_CAN1_MB22_ID0(val) bfin_write16(CAN1_MB22_ID0, val)
-#define bfin_read_CAN1_MB22_ID1() bfin_read16(CAN1_MB22_ID1)
-#define bfin_write_CAN1_MB22_ID1(val) bfin_write16(CAN1_MB22_ID1, val)
-#define bfin_read_CAN1_MB23_DATA0() bfin_read16(CAN1_MB23_DATA0)
-#define bfin_write_CAN1_MB23_DATA0(val) bfin_write16(CAN1_MB23_DATA0, val)
-#define bfin_read_CAN1_MB23_DATA1() bfin_read16(CAN1_MB23_DATA1)
-#define bfin_write_CAN1_MB23_DATA1(val) bfin_write16(CAN1_MB23_DATA1, val)
-#define bfin_read_CAN1_MB23_DATA2() bfin_read16(CAN1_MB23_DATA2)
-#define bfin_write_CAN1_MB23_DATA2(val) bfin_write16(CAN1_MB23_DATA2, val)
-#define bfin_read_CAN1_MB23_DATA3() bfin_read16(CAN1_MB23_DATA3)
-#define bfin_write_CAN1_MB23_DATA3(val) bfin_write16(CAN1_MB23_DATA3, val)
-#define bfin_read_CAN1_MB23_LENGTH() bfin_read16(CAN1_MB23_LENGTH)
-#define bfin_write_CAN1_MB23_LENGTH(val) bfin_write16(CAN1_MB23_LENGTH, val)
-#define bfin_read_CAN1_MB23_TIMESTAMP() bfin_read16(CAN1_MB23_TIMESTAMP)
-#define bfin_write_CAN1_MB23_TIMESTAMP(val) bfin_write16(CAN1_MB23_TIMESTAMP, val)
-#define bfin_read_CAN1_MB23_ID0() bfin_read16(CAN1_MB23_ID0)
-#define bfin_write_CAN1_MB23_ID0(val) bfin_write16(CAN1_MB23_ID0, val)
-#define bfin_read_CAN1_MB23_ID1() bfin_read16(CAN1_MB23_ID1)
-#define bfin_write_CAN1_MB23_ID1(val) bfin_write16(CAN1_MB23_ID1, val)
-#define bfin_read_CAN1_MB24_DATA0() bfin_read16(CAN1_MB24_DATA0)
-#define bfin_write_CAN1_MB24_DATA0(val) bfin_write16(CAN1_MB24_DATA0, val)
-#define bfin_read_CAN1_MB24_DATA1() bfin_read16(CAN1_MB24_DATA1)
-#define bfin_write_CAN1_MB24_DATA1(val) bfin_write16(CAN1_MB24_DATA1, val)
-#define bfin_read_CAN1_MB24_DATA2() bfin_read16(CAN1_MB24_DATA2)
-#define bfin_write_CAN1_MB24_DATA2(val) bfin_write16(CAN1_MB24_DATA2, val)
-#define bfin_read_CAN1_MB24_DATA3() bfin_read16(CAN1_MB24_DATA3)
-#define bfin_write_CAN1_MB24_DATA3(val) bfin_write16(CAN1_MB24_DATA3, val)
-#define bfin_read_CAN1_MB24_LENGTH() bfin_read16(CAN1_MB24_LENGTH)
-#define bfin_write_CAN1_MB24_LENGTH(val) bfin_write16(CAN1_MB24_LENGTH, val)
-#define bfin_read_CAN1_MB24_TIMESTAMP() bfin_read16(CAN1_MB24_TIMESTAMP)
-#define bfin_write_CAN1_MB24_TIMESTAMP(val) bfin_write16(CAN1_MB24_TIMESTAMP, val)
-#define bfin_read_CAN1_MB24_ID0() bfin_read16(CAN1_MB24_ID0)
-#define bfin_write_CAN1_MB24_ID0(val) bfin_write16(CAN1_MB24_ID0, val)
-#define bfin_read_CAN1_MB24_ID1() bfin_read16(CAN1_MB24_ID1)
-#define bfin_write_CAN1_MB24_ID1(val) bfin_write16(CAN1_MB24_ID1, val)
-#define bfin_read_CAN1_MB25_DATA0() bfin_read16(CAN1_MB25_DATA0)
-#define bfin_write_CAN1_MB25_DATA0(val) bfin_write16(CAN1_MB25_DATA0, val)
-#define bfin_read_CAN1_MB25_DATA1() bfin_read16(CAN1_MB25_DATA1)
-#define bfin_write_CAN1_MB25_DATA1(val) bfin_write16(CAN1_MB25_DATA1, val)
-#define bfin_read_CAN1_MB25_DATA2() bfin_read16(CAN1_MB25_DATA2)
-#define bfin_write_CAN1_MB25_DATA2(val) bfin_write16(CAN1_MB25_DATA2, val)
-#define bfin_read_CAN1_MB25_DATA3() bfin_read16(CAN1_MB25_DATA3)
-#define bfin_write_CAN1_MB25_DATA3(val) bfin_write16(CAN1_MB25_DATA3, val)
-#define bfin_read_CAN1_MB25_LENGTH() bfin_read16(CAN1_MB25_LENGTH)
-#define bfin_write_CAN1_MB25_LENGTH(val) bfin_write16(CAN1_MB25_LENGTH, val)
-#define bfin_read_CAN1_MB25_TIMESTAMP() bfin_read16(CAN1_MB25_TIMESTAMP)
-#define bfin_write_CAN1_MB25_TIMESTAMP(val) bfin_write16(CAN1_MB25_TIMESTAMP, val)
-#define bfin_read_CAN1_MB25_ID0() bfin_read16(CAN1_MB25_ID0)
-#define bfin_write_CAN1_MB25_ID0(val) bfin_write16(CAN1_MB25_ID0, val)
-#define bfin_read_CAN1_MB25_ID1() bfin_read16(CAN1_MB25_ID1)
-#define bfin_write_CAN1_MB25_ID1(val) bfin_write16(CAN1_MB25_ID1, val)
-#define bfin_read_CAN1_MB26_DATA0() bfin_read16(CAN1_MB26_DATA0)
-#define bfin_write_CAN1_MB26_DATA0(val) bfin_write16(CAN1_MB26_DATA0, val)
-#define bfin_read_CAN1_MB26_DATA1() bfin_read16(CAN1_MB26_DATA1)
-#define bfin_write_CAN1_MB26_DATA1(val) bfin_write16(CAN1_MB26_DATA1, val)
-#define bfin_read_CAN1_MB26_DATA2() bfin_read16(CAN1_MB26_DATA2)
-#define bfin_write_CAN1_MB26_DATA2(val) bfin_write16(CAN1_MB26_DATA2, val)
-#define bfin_read_CAN1_MB26_DATA3() bfin_read16(CAN1_MB26_DATA3)
-#define bfin_write_CAN1_MB26_DATA3(val) bfin_write16(CAN1_MB26_DATA3, val)
-#define bfin_read_CAN1_MB26_LENGTH() bfin_read16(CAN1_MB26_LENGTH)
-#define bfin_write_CAN1_MB26_LENGTH(val) bfin_write16(CAN1_MB26_LENGTH, val)
-#define bfin_read_CAN1_MB26_TIMESTAMP() bfin_read16(CAN1_MB26_TIMESTAMP)
-#define bfin_write_CAN1_MB26_TIMESTAMP(val) bfin_write16(CAN1_MB26_TIMESTAMP, val)
-#define bfin_read_CAN1_MB26_ID0() bfin_read16(CAN1_MB26_ID0)
-#define bfin_write_CAN1_MB26_ID0(val) bfin_write16(CAN1_MB26_ID0, val)
-#define bfin_read_CAN1_MB26_ID1() bfin_read16(CAN1_MB26_ID1)
-#define bfin_write_CAN1_MB26_ID1(val) bfin_write16(CAN1_MB26_ID1, val)
-#define bfin_read_CAN1_MB27_DATA0() bfin_read16(CAN1_MB27_DATA0)
-#define bfin_write_CAN1_MB27_DATA0(val) bfin_write16(CAN1_MB27_DATA0, val)
-#define bfin_read_CAN1_MB27_DATA1() bfin_read16(CAN1_MB27_DATA1)
-#define bfin_write_CAN1_MB27_DATA1(val) bfin_write16(CAN1_MB27_DATA1, val)
-#define bfin_read_CAN1_MB27_DATA2() bfin_read16(CAN1_MB27_DATA2)
-#define bfin_write_CAN1_MB27_DATA2(val) bfin_write16(CAN1_MB27_DATA2, val)
-#define bfin_read_CAN1_MB27_DATA3() bfin_read16(CAN1_MB27_DATA3)
-#define bfin_write_CAN1_MB27_DATA3(val) bfin_write16(CAN1_MB27_DATA3, val)
-#define bfin_read_CAN1_MB27_LENGTH() bfin_read16(CAN1_MB27_LENGTH)
-#define bfin_write_CAN1_MB27_LENGTH(val) bfin_write16(CAN1_MB27_LENGTH, val)
-#define bfin_read_CAN1_MB27_TIMESTAMP() bfin_read16(CAN1_MB27_TIMESTAMP)
-#define bfin_write_CAN1_MB27_TIMESTAMP(val) bfin_write16(CAN1_MB27_TIMESTAMP, val)
-#define bfin_read_CAN1_MB27_ID0() bfin_read16(CAN1_MB27_ID0)
-#define bfin_write_CAN1_MB27_ID0(val) bfin_write16(CAN1_MB27_ID0, val)
-#define bfin_read_CAN1_MB27_ID1() bfin_read16(CAN1_MB27_ID1)
-#define bfin_write_CAN1_MB27_ID1(val) bfin_write16(CAN1_MB27_ID1, val)
-#define bfin_read_CAN1_MB28_DATA0() bfin_read16(CAN1_MB28_DATA0)
-#define bfin_write_CAN1_MB28_DATA0(val) bfin_write16(CAN1_MB28_DATA0, val)
-#define bfin_read_CAN1_MB28_DATA1() bfin_read16(CAN1_MB28_DATA1)
-#define bfin_write_CAN1_MB28_DATA1(val) bfin_write16(CAN1_MB28_DATA1, val)
-#define bfin_read_CAN1_MB28_DATA2() bfin_read16(CAN1_MB28_DATA2)
-#define bfin_write_CAN1_MB28_DATA2(val) bfin_write16(CAN1_MB28_DATA2, val)
-#define bfin_read_CAN1_MB28_DATA3() bfin_read16(CAN1_MB28_DATA3)
-#define bfin_write_CAN1_MB28_DATA3(val) bfin_write16(CAN1_MB28_DATA3, val)
-#define bfin_read_CAN1_MB28_LENGTH() bfin_read16(CAN1_MB28_LENGTH)
-#define bfin_write_CAN1_MB28_LENGTH(val) bfin_write16(CAN1_MB28_LENGTH, val)
-#define bfin_read_CAN1_MB28_TIMESTAMP() bfin_read16(CAN1_MB28_TIMESTAMP)
-#define bfin_write_CAN1_MB28_TIMESTAMP(val) bfin_write16(CAN1_MB28_TIMESTAMP, val)
-#define bfin_read_CAN1_MB28_ID0() bfin_read16(CAN1_MB28_ID0)
-#define bfin_write_CAN1_MB28_ID0(val) bfin_write16(CAN1_MB28_ID0, val)
-#define bfin_read_CAN1_MB28_ID1() bfin_read16(CAN1_MB28_ID1)
-#define bfin_write_CAN1_MB28_ID1(val) bfin_write16(CAN1_MB28_ID1, val)
-#define bfin_read_CAN1_MB29_DATA0() bfin_read16(CAN1_MB29_DATA0)
-#define bfin_write_CAN1_MB29_DATA0(val) bfin_write16(CAN1_MB29_DATA0, val)
-#define bfin_read_CAN1_MB29_DATA1() bfin_read16(CAN1_MB29_DATA1)
-#define bfin_write_CAN1_MB29_DATA1(val) bfin_write16(CAN1_MB29_DATA1, val)
-#define bfin_read_CAN1_MB29_DATA2() bfin_read16(CAN1_MB29_DATA2)
-#define bfin_write_CAN1_MB29_DATA2(val) bfin_write16(CAN1_MB29_DATA2, val)
-#define bfin_read_CAN1_MB29_DATA3() bfin_read16(CAN1_MB29_DATA3)
-#define bfin_write_CAN1_MB29_DATA3(val) bfin_write16(CAN1_MB29_DATA3, val)
-#define bfin_read_CAN1_MB29_LENGTH() bfin_read16(CAN1_MB29_LENGTH)
-#define bfin_write_CAN1_MB29_LENGTH(val) bfin_write16(CAN1_MB29_LENGTH, val)
-#define bfin_read_CAN1_MB29_TIMESTAMP() bfin_read16(CAN1_MB29_TIMESTAMP)
-#define bfin_write_CAN1_MB29_TIMESTAMP(val) bfin_write16(CAN1_MB29_TIMESTAMP, val)
-#define bfin_read_CAN1_MB29_ID0() bfin_read16(CAN1_MB29_ID0)
-#define bfin_write_CAN1_MB29_ID0(val) bfin_write16(CAN1_MB29_ID0, val)
-#define bfin_read_CAN1_MB29_ID1() bfin_read16(CAN1_MB29_ID1)
-#define bfin_write_CAN1_MB29_ID1(val) bfin_write16(CAN1_MB29_ID1, val)
-#define bfin_read_CAN1_MB30_DATA0() bfin_read16(CAN1_MB30_DATA0)
-#define bfin_write_CAN1_MB30_DATA0(val) bfin_write16(CAN1_MB30_DATA0, val)
-#define bfin_read_CAN1_MB30_DATA1() bfin_read16(CAN1_MB30_DATA1)
-#define bfin_write_CAN1_MB30_DATA1(val) bfin_write16(CAN1_MB30_DATA1, val)
-#define bfin_read_CAN1_MB30_DATA2() bfin_read16(CAN1_MB30_DATA2)
-#define bfin_write_CAN1_MB30_DATA2(val) bfin_write16(CAN1_MB30_DATA2, val)
-#define bfin_read_CAN1_MB30_DATA3() bfin_read16(CAN1_MB30_DATA3)
-#define bfin_write_CAN1_MB30_DATA3(val) bfin_write16(CAN1_MB30_DATA3, val)
-#define bfin_read_CAN1_MB30_LENGTH() bfin_read16(CAN1_MB30_LENGTH)
-#define bfin_write_CAN1_MB30_LENGTH(val) bfin_write16(CAN1_MB30_LENGTH, val)
-#define bfin_read_CAN1_MB30_TIMESTAMP() bfin_read16(CAN1_MB30_TIMESTAMP)
-#define bfin_write_CAN1_MB30_TIMESTAMP(val) bfin_write16(CAN1_MB30_TIMESTAMP, val)
-#define bfin_read_CAN1_MB30_ID0() bfin_read16(CAN1_MB30_ID0)
-#define bfin_write_CAN1_MB30_ID0(val) bfin_write16(CAN1_MB30_ID0, val)
-#define bfin_read_CAN1_MB30_ID1() bfin_read16(CAN1_MB30_ID1)
-#define bfin_write_CAN1_MB30_ID1(val) bfin_write16(CAN1_MB30_ID1, val)
-#define bfin_read_CAN1_MB31_DATA0() bfin_read16(CAN1_MB31_DATA0)
-#define bfin_write_CAN1_MB31_DATA0(val) bfin_write16(CAN1_MB31_DATA0, val)
-#define bfin_read_CAN1_MB31_DATA1() bfin_read16(CAN1_MB31_DATA1)
-#define bfin_write_CAN1_MB31_DATA1(val) bfin_write16(CAN1_MB31_DATA1, val)
-#define bfin_read_CAN1_MB31_DATA2() bfin_read16(CAN1_MB31_DATA2)
-#define bfin_write_CAN1_MB31_DATA2(val) bfin_write16(CAN1_MB31_DATA2, val)
-#define bfin_read_CAN1_MB31_DATA3() bfin_read16(CAN1_MB31_DATA3)
-#define bfin_write_CAN1_MB31_DATA3(val) bfin_write16(CAN1_MB31_DATA3, val)
-#define bfin_read_CAN1_MB31_LENGTH() bfin_read16(CAN1_MB31_LENGTH)
-#define bfin_write_CAN1_MB31_LENGTH(val) bfin_write16(CAN1_MB31_LENGTH, val)
-#define bfin_read_CAN1_MB31_TIMESTAMP() bfin_read16(CAN1_MB31_TIMESTAMP)
-#define bfin_write_CAN1_MB31_TIMESTAMP(val) bfin_write16(CAN1_MB31_TIMESTAMP, val)
-#define bfin_read_CAN1_MB31_ID0() bfin_read16(CAN1_MB31_ID0)
-#define bfin_write_CAN1_MB31_ID0(val) bfin_write16(CAN1_MB31_ID0, val)
-#define bfin_read_CAN1_MB31_ID1() bfin_read16(CAN1_MB31_ID1)
-#define bfin_write_CAN1_MB31_ID1(val) bfin_write16(CAN1_MB31_ID1, val)
-
-/* HOST Port Registers */
-
-#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL)
-#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val)
-#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS)
-#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val)
-#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT)
-#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val)
-
-/* Pixel Combfin_read_()ositor (PIXC) Registers */
-
-#define bfin_read_PIXC_CTL() bfin_read16(PIXC_CTL)
-#define bfin_write_PIXC_CTL(val) bfin_write16(PIXC_CTL, val)
-#define bfin_read_PIXC_PPL() bfin_read16(PIXC_PPL)
-#define bfin_write_PIXC_PPL(val) bfin_write16(PIXC_PPL, val)
-#define bfin_read_PIXC_LPF() bfin_read16(PIXC_LPF)
-#define bfin_write_PIXC_LPF(val) bfin_write16(PIXC_LPF, val)
-#define bfin_read_PIXC_AHSTART() bfin_read16(PIXC_AHSTART)
-#define bfin_write_PIXC_AHSTART(val) bfin_write16(PIXC_AHSTART, val)
-#define bfin_read_PIXC_AHEND() bfin_read16(PIXC_AHEND)
-#define bfin_write_PIXC_AHEND(val) bfin_write16(PIXC_AHEND, val)
-#define bfin_read_PIXC_AVSTART() bfin_read16(PIXC_AVSTART)
-#define bfin_write_PIXC_AVSTART(val) bfin_write16(PIXC_AVSTART, val)
-#define bfin_read_PIXC_AVEND() bfin_read16(PIXC_AVEND)
-#define bfin_write_PIXC_AVEND(val) bfin_write16(PIXC_AVEND, val)
-#define bfin_read_PIXC_ATRANSP() bfin_read16(PIXC_ATRANSP)
-#define bfin_write_PIXC_ATRANSP(val) bfin_write16(PIXC_ATRANSP, val)
-#define bfin_read_PIXC_BHSTART() bfin_read16(PIXC_BHSTART)
-#define bfin_write_PIXC_BHSTART(val) bfin_write16(PIXC_BHSTART, val)
-#define bfin_read_PIXC_BHEND() bfin_read16(PIXC_BHEND)
-#define bfin_write_PIXC_BHEND(val) bfin_write16(PIXC_BHEND, val)
-#define bfin_read_PIXC_BVSTART() bfin_read16(PIXC_BVSTART)
-#define bfin_write_PIXC_BVSTART(val) bfin_write16(PIXC_BVSTART, val)
-#define bfin_read_PIXC_BVEND() bfin_read16(PIXC_BVEND)
-#define bfin_write_PIXC_BVEND(val) bfin_write16(PIXC_BVEND, val)
-#define bfin_read_PIXC_BTRANSP() bfin_read16(PIXC_BTRANSP)
-#define bfin_write_PIXC_BTRANSP(val) bfin_write16(PIXC_BTRANSP, val)
-#define bfin_read_PIXC_INTRSTAT() bfin_read16(PIXC_INTRSTAT)
-#define bfin_write_PIXC_INTRSTAT(val) bfin_write16(PIXC_INTRSTAT, val)
-#define bfin_read_PIXC_RYCON() bfin_read32(PIXC_RYCON)
-#define bfin_write_PIXC_RYCON(val) bfin_write32(PIXC_RYCON, val)
-#define bfin_read_PIXC_GUCON() bfin_read32(PIXC_GUCON)
-#define bfin_write_PIXC_GUCON(val) bfin_write32(PIXC_GUCON, val)
-#define bfin_read_PIXC_BVCON() bfin_read32(PIXC_BVCON)
-#define bfin_write_PIXC_BVCON(val) bfin_write32(PIXC_BVCON, val)
-#define bfin_read_PIXC_CCBIAS() bfin_read32(PIXC_CCBIAS)
-#define bfin_write_PIXC_CCBIAS(val) bfin_write32(PIXC_CCBIAS, val)
-#define bfin_read_PIXC_TC() bfin_read32(PIXC_TC)
-#define bfin_write_PIXC_TC(val) bfin_write32(PIXC_TC, val)
-
-/* Handshake MDMA 0 Registers */
-
-#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
-#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
-#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
-#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
-#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
-#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
-#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
-#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
-#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
-#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
-#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
-#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
-#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
-#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
-
-/* Handshake MDMA 1 Registers */
-
-#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
-#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
-#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
-#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
-#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
-#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
-#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
-#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
-#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
-#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
-#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
-#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
-#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
-#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
-
-#endif /* _CDEF_BF544_H */
+++ /dev/null
-/*
- * Copyright 2008-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CDEF_BF547_H
-#define _CDEF_BF547_H
-
-/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
-#include "cdefBF54x_base.h"
-
-/* The following are the #defines needed by ADSP-BF547 that are not in the common header */
-
-/* Timer Registers */
-
-#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG)
-#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val)
-#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER)
-#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
-#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD)
-#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val)
-#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH)
-#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val)
-#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG)
-#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val)
-#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER)
-#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
-#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD)
-#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val)
-#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH)
-#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val)
-#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG)
-#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)
-#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER)
-#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
-#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD)
-#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
-#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH)
-#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val)
-
-/* Timer Groubfin_read_() of 3 */
-
-#define bfin_read_TIMER_ENABLE1() bfin_read16(TIMER_ENABLE1)
-#define bfin_write_TIMER_ENABLE1(val) bfin_write16(TIMER_ENABLE1, val)
-#define bfin_read_TIMER_DISABLE1() bfin_read16(TIMER_DISABLE1)
-#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val)
-#define bfin_read_TIMER_STATUS1() bfin_read32(TIMER_STATUS1)
-#define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val)
-
-/* SPORT0 Registers */
-
-#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
-#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
-#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
-#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
-#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
-#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
-#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
-#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
-#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
-#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
-#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
-#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
-#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
-#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
-#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
-#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
-#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
-#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
-#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
-#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
-#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
-
-/* EPPI0 Registers */
-
-#define bfin_read_EPPI0_STATUS() bfin_read16(EPPI0_STATUS)
-#define bfin_write_EPPI0_STATUS(val) bfin_write16(EPPI0_STATUS, val)
-#define bfin_read_EPPI0_HCOUNT() bfin_read16(EPPI0_HCOUNT)
-#define bfin_write_EPPI0_HCOUNT(val) bfin_write16(EPPI0_HCOUNT, val)
-#define bfin_read_EPPI0_HDELAY() bfin_read16(EPPI0_HDELAY)
-#define bfin_write_EPPI0_HDELAY(val) bfin_write16(EPPI0_HDELAY, val)
-#define bfin_read_EPPI0_VCOUNT() bfin_read16(EPPI0_VCOUNT)
-#define bfin_write_EPPI0_VCOUNT(val) bfin_write16(EPPI0_VCOUNT, val)
-#define bfin_read_EPPI0_VDELAY() bfin_read16(EPPI0_VDELAY)
-#define bfin_write_EPPI0_VDELAY(val) bfin_write16(EPPI0_VDELAY, val)
-#define bfin_read_EPPI0_FRAME() bfin_read16(EPPI0_FRAME)
-#define bfin_write_EPPI0_FRAME(val) bfin_write16(EPPI0_FRAME, val)
-#define bfin_read_EPPI0_LINE() bfin_read16(EPPI0_LINE)
-#define bfin_write_EPPI0_LINE(val) bfin_write16(EPPI0_LINE, val)
-#define bfin_read_EPPI0_CLKDIV() bfin_read16(EPPI0_CLKDIV)
-#define bfin_write_EPPI0_CLKDIV(val) bfin_write16(EPPI0_CLKDIV, val)
-#define bfin_read_EPPI0_CONTROL() bfin_read32(EPPI0_CONTROL)
-#define bfin_write_EPPI0_CONTROL(val) bfin_write32(EPPI0_CONTROL, val)
-#define bfin_read_EPPI0_FS1W_HBL() bfin_read32(EPPI0_FS1W_HBL)
-#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val)
-#define bfin_read_EPPI0_FS1P_AVPL() bfin_read32(EPPI0_FS1P_AVPL)
-#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val)
-#define bfin_read_EPPI0_FS2W_LVB() bfin_read32(EPPI0_FS2W_LVB)
-#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val)
-#define bfin_read_EPPI0_FS2P_LAVF() bfin_read32(EPPI0_FS2P_LAVF)
-#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val)
-#define bfin_read_EPPI0_CLIP() bfin_read32(EPPI0_CLIP)
-#define bfin_write_EPPI0_CLIP(val) bfin_write32(EPPI0_CLIP, val)
-
-/* UART2 Registers */
-
-#define bfin_read_UART2_DLL() bfin_read16(UART2_DLL)
-#define bfin_write_UART2_DLL(val) bfin_write16(UART2_DLL, val)
-#define bfin_read_UART2_DLH() bfin_read16(UART2_DLH)
-#define bfin_write_UART2_DLH(val) bfin_write16(UART2_DLH, val)
-#define bfin_read_UART2_GCTL() bfin_read16(UART2_GCTL)
-#define bfin_write_UART2_GCTL(val) bfin_write16(UART2_GCTL, val)
-#define bfin_read_UART2_LCR() bfin_read16(UART2_LCR)
-#define bfin_write_UART2_LCR(val) bfin_write16(UART2_LCR, val)
-#define bfin_read_UART2_MCR() bfin_read16(UART2_MCR)
-#define bfin_write_UART2_MCR(val) bfin_write16(UART2_MCR, val)
-#define bfin_read_UART2_LSR() bfin_read16(UART2_LSR)
-#define bfin_write_UART2_LSR(val) bfin_write16(UART2_LSR, val)
-#define bfin_read_UART2_MSR() bfin_read16(UART2_MSR)
-#define bfin_write_UART2_MSR(val) bfin_write16(UART2_MSR, val)
-#define bfin_read_UART2_SCR() bfin_read16(UART2_SCR)
-#define bfin_write_UART2_SCR(val) bfin_write16(UART2_SCR, val)
-#define bfin_read_UART2_IER_SET() bfin_read16(UART2_IER_SET)
-#define bfin_write_UART2_IER_SET(val) bfin_write16(UART2_IER_SET, val)
-#define bfin_read_UART2_IER_CLEAR() bfin_read16(UART2_IER_CLEAR)
-#define bfin_write_UART2_IER_CLEAR(val) bfin_write16(UART2_IER_CLEAR, val)
-#define bfin_read_UART2_RBR() bfin_read16(UART2_RBR)
-#define bfin_write_UART2_RBR(val) bfin_write16(UART2_RBR, val)
-
-/* Two Wire Interface Registers (TWI1) */
-
-/* SPI2 Registers */
-
-#define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL)
-#define bfin_write_SPI2_CTL(val) bfin_write16(SPI2_CTL, val)
-#define bfin_read_SPI2_FLG() bfin_read16(SPI2_FLG)
-#define bfin_write_SPI2_FLG(val) bfin_write16(SPI2_FLG, val)
-#define bfin_read_SPI2_STAT() bfin_read16(SPI2_STAT)
-#define bfin_write_SPI2_STAT(val) bfin_write16(SPI2_STAT, val)
-#define bfin_read_SPI2_TDBR() bfin_read16(SPI2_TDBR)
-#define bfin_write_SPI2_TDBR(val) bfin_write16(SPI2_TDBR, val)
-#define bfin_read_SPI2_RDBR() bfin_read16(SPI2_RDBR)
-#define bfin_write_SPI2_RDBR(val) bfin_write16(SPI2_RDBR, val)
-#define bfin_read_SPI2_BAUD() bfin_read16(SPI2_BAUD)
-#define bfin_write_SPI2_BAUD(val) bfin_write16(SPI2_BAUD, val)
-#define bfin_read_SPI2_SHADOW() bfin_read16(SPI2_SHADOW)
-#define bfin_write_SPI2_SHADOW(val) bfin_write16(SPI2_SHADOW, val)
-
-/* ATAPI Registers */
-
-#define bfin_read_ATAPI_CONTROL() bfin_read16(ATAPI_CONTROL)
-#define bfin_write_ATAPI_CONTROL(val) bfin_write16(ATAPI_CONTROL, val)
-#define bfin_read_ATAPI_STATUS() bfin_read16(ATAPI_STATUS)
-#define bfin_write_ATAPI_STATUS(val) bfin_write16(ATAPI_STATUS, val)
-#define bfin_read_ATAPI_DEV_ADDR() bfin_read16(ATAPI_DEV_ADDR)
-#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val)
-#define bfin_read_ATAPI_DEV_TXBUF() bfin_read16(ATAPI_DEV_TXBUF)
-#define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val)
-#define bfin_read_ATAPI_DEV_RXBUF() bfin_read16(ATAPI_DEV_RXBUF)
-#define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val)
-#define bfin_read_ATAPI_INT_MASK() bfin_read16(ATAPI_INT_MASK)
-#define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val)
-#define bfin_read_ATAPI_INT_STATUS() bfin_read16(ATAPI_INT_STATUS)
-#define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val)
-#define bfin_read_ATAPI_XFER_LEN() bfin_read16(ATAPI_XFER_LEN)
-#define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val)
-#define bfin_read_ATAPI_LINE_STATUS() bfin_read16(ATAPI_LINE_STATUS)
-#define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val)
-#define bfin_read_ATAPI_SM_STATE() bfin_read16(ATAPI_SM_STATE)
-#define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val)
-#define bfin_read_ATAPI_TERMINATE() bfin_read16(ATAPI_TERMINATE)
-#define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val)
-#define bfin_read_ATAPI_PIO_TFRCNT() bfin_read16(ATAPI_PIO_TFRCNT)
-#define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val)
-#define bfin_read_ATAPI_DMA_TFRCNT() bfin_read16(ATAPI_DMA_TFRCNT)
-#define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val)
-#define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT)
-#define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val)
-#define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT)
-#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val)
-#define bfin_read_ATAPI_REG_TIM_0() bfin_read16(ATAPI_REG_TIM_0)
-#define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val)
-#define bfin_read_ATAPI_PIO_TIM_0() bfin_read16(ATAPI_PIO_TIM_0)
-#define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val)
-#define bfin_read_ATAPI_PIO_TIM_1() bfin_read16(ATAPI_PIO_TIM_1)
-#define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val)
-#define bfin_read_ATAPI_MULTI_TIM_0() bfin_read16(ATAPI_MULTI_TIM_0)
-#define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val)
-#define bfin_read_ATAPI_MULTI_TIM_1() bfin_read16(ATAPI_MULTI_TIM_1)
-#define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val)
-#define bfin_read_ATAPI_MULTI_TIM_2() bfin_read16(ATAPI_MULTI_TIM_2)
-#define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val)
-#define bfin_read_ATAPI_ULTRA_TIM_0() bfin_read16(ATAPI_ULTRA_TIM_0)
-#define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val)
-#define bfin_read_ATAPI_ULTRA_TIM_1() bfin_read16(ATAPI_ULTRA_TIM_1)
-#define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val)
-#define bfin_read_ATAPI_ULTRA_TIM_2() bfin_read16(ATAPI_ULTRA_TIM_2)
-#define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val)
-#define bfin_read_ATAPI_ULTRA_TIM_3() bfin_read16(ATAPI_ULTRA_TIM_3)
-#define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val)
-
-/* SDH Registers */
-
-#define bfin_read_SDH_PWR_CTL() bfin_read16(SDH_PWR_CTL)
-#define bfin_write_SDH_PWR_CTL(val) bfin_write16(SDH_PWR_CTL, val)
-#define bfin_read_SDH_CLK_CTL() bfin_read16(SDH_CLK_CTL)
-#define bfin_write_SDH_CLK_CTL(val) bfin_write16(SDH_CLK_CTL, val)
-#define bfin_read_SDH_ARGUMENT() bfin_read32(SDH_ARGUMENT)
-#define bfin_write_SDH_ARGUMENT(val) bfin_write32(SDH_ARGUMENT, val)
-#define bfin_read_SDH_COMMAND() bfin_read16(SDH_COMMAND)
-#define bfin_write_SDH_COMMAND(val) bfin_write16(SDH_COMMAND, val)
-#define bfin_read_SDH_RESP_CMD() bfin_read16(SDH_RESP_CMD)
-#define bfin_write_SDH_RESP_CMD(val) bfin_write16(SDH_RESP_CMD, val)
-#define bfin_read_SDH_RESPONSE0() bfin_read32(SDH_RESPONSE0)
-#define bfin_write_SDH_RESPONSE0(val) bfin_write32(SDH_RESPONSE0, val)
-#define bfin_read_SDH_RESPONSE1() bfin_read32(SDH_RESPONSE1)
-#define bfin_write_SDH_RESPONSE1(val) bfin_write32(SDH_RESPONSE1, val)
-#define bfin_read_SDH_RESPONSE2() bfin_read32(SDH_RESPONSE2)
-#define bfin_write_SDH_RESPONSE2(val) bfin_write32(SDH_RESPONSE2, val)
-#define bfin_read_SDH_RESPONSE3() bfin_read32(SDH_RESPONSE3)
-#define bfin_write_SDH_RESPONSE3(val) bfin_write32(SDH_RESPONSE3, val)
-#define bfin_read_SDH_DATA_TIMER() bfin_read32(SDH_DATA_TIMER)
-#define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val)
-#define bfin_read_SDH_DATA_LGTH() bfin_read16(SDH_DATA_LGTH)
-#define bfin_write_SDH_DATA_LGTH(val) bfin_write16(SDH_DATA_LGTH, val)
-#define bfin_read_SDH_DATA_CTL() bfin_read16(SDH_DATA_CTL)
-#define bfin_write_SDH_DATA_CTL(val) bfin_write16(SDH_DATA_CTL, val)
-#define bfin_read_SDH_DATA_CNT() bfin_read16(SDH_DATA_CNT)
-#define bfin_write_SDH_DATA_CNT(val) bfin_write16(SDH_DATA_CNT, val)
-#define bfin_read_SDH_STATUS() bfin_read32(SDH_STATUS)
-#define bfin_write_SDH_STATUS(val) bfin_write32(SDH_STATUS, val)
-#define bfin_read_SDH_STATUS_CLR() bfin_read16(SDH_STATUS_CLR)
-#define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val)
-#define bfin_read_SDH_MASK0() bfin_read32(SDH_MASK0)
-#define bfin_write_SDH_MASK0(val) bfin_write32(SDH_MASK0, val)
-#define bfin_read_SDH_MASK1() bfin_read32(SDH_MASK1)
-#define bfin_write_SDH_MASK1(val) bfin_write32(SDH_MASK1, val)
-#define bfin_read_SDH_FIFO_CNT() bfin_read16(SDH_FIFO_CNT)
-#define bfin_write_SDH_FIFO_CNT(val) bfin_write16(SDH_FIFO_CNT, val)
-#define bfin_read_SDH_FIFO() bfin_read32(SDH_FIFO)
-#define bfin_write_SDH_FIFO(val) bfin_write32(SDH_FIFO, val)
-#define bfin_read_SDH_E_STATUS() bfin_read16(SDH_E_STATUS)
-#define bfin_write_SDH_E_STATUS(val) bfin_write16(SDH_E_STATUS, val)
-#define bfin_read_SDH_E_MASK() bfin_read16(SDH_E_MASK)
-#define bfin_write_SDH_E_MASK(val) bfin_write16(SDH_E_MASK, val)
-#define bfin_read_SDH_CFG() bfin_read16(SDH_CFG)
-#define bfin_write_SDH_CFG(val) bfin_write16(SDH_CFG, val)
-#define bfin_read_SDH_RD_WAIT_EN() bfin_read16(SDH_RD_WAIT_EN)
-#define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val)
-#define bfin_read_SDH_PID0() bfin_read16(SDH_PID0)
-#define bfin_write_SDH_PID0(val) bfin_write16(SDH_PID0, val)
-#define bfin_read_SDH_PID1() bfin_read16(SDH_PID1)
-#define bfin_write_SDH_PID1(val) bfin_write16(SDH_PID1, val)
-#define bfin_read_SDH_PID2() bfin_read16(SDH_PID2)
-#define bfin_write_SDH_PID2(val) bfin_write16(SDH_PID2, val)
-#define bfin_read_SDH_PID3() bfin_read16(SDH_PID3)
-#define bfin_write_SDH_PID3(val) bfin_write16(SDH_PID3, val)
-#define bfin_read_SDH_PID4() bfin_read16(SDH_PID4)
-#define bfin_write_SDH_PID4(val) bfin_write16(SDH_PID4, val)
-#define bfin_read_SDH_PID5() bfin_read16(SDH_PID5)
-#define bfin_write_SDH_PID5(val) bfin_write16(SDH_PID5, val)
-#define bfin_read_SDH_PID6() bfin_read16(SDH_PID6)
-#define bfin_write_SDH_PID6(val) bfin_write16(SDH_PID6, val)
-#define bfin_read_SDH_PID7() bfin_read16(SDH_PID7)
-#define bfin_write_SDH_PID7(val) bfin_write16(SDH_PID7, val)
-
-/* HOST Port Registers */
-
-#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL)
-#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val)
-#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS)
-#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val)
-#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT)
-#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val)
-
-/* USB Control Registers */
-
-#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
-#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
-#define bfin_read_USB_POWER() bfin_read16(USB_POWER)
-#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val)
-#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX)
-#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val)
-#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX)
-#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val)
-#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE)
-#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val)
-#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE)
-#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val)
-#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB)
-#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val)
-#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE)
-#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val)
-#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME)
-#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val)
-#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX)
-#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val)
-#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE)
-#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val)
-#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR)
-#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val)
-#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL)
-#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
-
-/* USB Packet Control Registers */
-
-#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET)
-#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
-#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0)
-#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val)
-#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR)
-#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val)
-#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET)
-#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
-#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR)
-#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val)
-#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0)
-#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val)
-#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT)
-#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val)
-#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE)
-#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val)
-#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0)
-#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val)
-#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL)
-#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
-#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE)
-#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val)
-#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL)
-#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
-#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT)
-#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val)
-
-/* USB Endbfin_read_()oint FIFO Registers */
-
-#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO)
-#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val)
-#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO)
-#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val)
-#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO)
-#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val)
-#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO)
-#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val)
-#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO)
-#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val)
-#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO)
-#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val)
-#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO)
-#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val)
-#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO)
-#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val)
-
-/* USB OTG Control Registers */
-
-#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL)
-#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
-#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ)
-#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
-#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK)
-#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
-
-/* USB Phy Control Registers */
-
-#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO)
-#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val)
-#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN)
-#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val)
-#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1)
-#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val)
-#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1)
-#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val)
-#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1)
-#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val)
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL)
-#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB)
-#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
-#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2)
-#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
-
-#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL)
-#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
-#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV)
-#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
-
-/* USB Endbfin_read_()oint 0 Control Registers */
-
-#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP)
-#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
-#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR)
-#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
-#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP)
-#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
-#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR)
-#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
-#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
-#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
-#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE)
-#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
-#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
-#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE)
-#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
-#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
-#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 1 Control Registers */
-
-#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
-#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
-#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP)
-#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
-#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR)
-#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
-#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP)
-#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
-#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR)
-#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
-#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
-#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
-#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE)
-#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
-#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
-#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE)
-#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
-#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
-#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 2 Control Registers */
-
-#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
-#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
-#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP)
-#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
-#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR)
-#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
-#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP)
-#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
-#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR)
-#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
-#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
-#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
-#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE)
-#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
-#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
-#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE)
-#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
-#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
-#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 3 Control Registers */
-
-#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
-#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
-#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP)
-#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
-#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR)
-#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
-#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP)
-#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
-#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR)
-#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
-#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
-#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
-#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE)
-#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
-#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
-#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE)
-#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
-#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
-#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 4 Control Registers */
-
-#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
-#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
-#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP)
-#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
-#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR)
-#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
-#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP)
-#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
-#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR)
-#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
-#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
-#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
-#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE)
-#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
-#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
-#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE)
-#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
-#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
-#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 5 Control Registers */
-
-#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
-#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
-#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP)
-#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
-#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR)
-#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
-#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP)
-#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
-#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR)
-#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
-#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
-#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
-#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE)
-#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
-#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
-#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE)
-#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
-#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
-#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 6 Control Registers */
-
-#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
-#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
-#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP)
-#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
-#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR)
-#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
-#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP)
-#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
-#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR)
-#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
-#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
-#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
-#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE)
-#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
-#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
-#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE)
-#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
-#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
-#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 7 Control Registers */
-
-#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
-#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
-#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP)
-#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
-#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR)
-#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
-#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP)
-#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
-#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR)
-#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
-#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
-#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
-#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE)
-#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
-#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
-#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE)
-#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
-#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
-#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
-#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
-#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT)
-#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
-
-/* USB Channel 0 Config Registers */
-
-#define bfin_read_USB_DMA0CONTROL() bfin_read16(USB_DMA0CONTROL)
-#define bfin_write_USB_DMA0CONTROL(val) bfin_write16(USB_DMA0CONTROL, val)
-#define bfin_read_USB_DMA0ADDRLOW() bfin_read16(USB_DMA0ADDRLOW)
-#define bfin_write_USB_DMA0ADDRLOW(val) bfin_write16(USB_DMA0ADDRLOW, val)
-#define bfin_read_USB_DMA0ADDRHIGH() bfin_read16(USB_DMA0ADDRHIGH)
-#define bfin_write_USB_DMA0ADDRHIGH(val) bfin_write16(USB_DMA0ADDRHIGH, val)
-#define bfin_read_USB_DMA0COUNTLOW() bfin_read16(USB_DMA0COUNTLOW)
-#define bfin_write_USB_DMA0COUNTLOW(val) bfin_write16(USB_DMA0COUNTLOW, val)
-#define bfin_read_USB_DMA0COUNTHIGH() bfin_read16(USB_DMA0COUNTHIGH)
-#define bfin_write_USB_DMA0COUNTHIGH(val) bfin_write16(USB_DMA0COUNTHIGH, val)
-
-/* USB Channel 1 Config Registers */
-
-#define bfin_read_USB_DMA1CONTROL() bfin_read16(USB_DMA1CONTROL)
-#define bfin_write_USB_DMA1CONTROL(val) bfin_write16(USB_DMA1CONTROL, val)
-#define bfin_read_USB_DMA1ADDRLOW() bfin_read16(USB_DMA1ADDRLOW)
-#define bfin_write_USB_DMA1ADDRLOW(val) bfin_write16(USB_DMA1ADDRLOW, val)
-#define bfin_read_USB_DMA1ADDRHIGH() bfin_read16(USB_DMA1ADDRHIGH)
-#define bfin_write_USB_DMA1ADDRHIGH(val) bfin_write16(USB_DMA1ADDRHIGH, val)
-#define bfin_read_USB_DMA1COUNTLOW() bfin_read16(USB_DMA1COUNTLOW)
-#define bfin_write_USB_DMA1COUNTLOW(val) bfin_write16(USB_DMA1COUNTLOW, val)
-#define bfin_read_USB_DMA1COUNTHIGH() bfin_read16(USB_DMA1COUNTHIGH)
-#define bfin_write_USB_DMA1COUNTHIGH(val) bfin_write16(USB_DMA1COUNTHIGH, val)
-
-/* USB Channel 2 Config Registers */
-
-#define bfin_read_USB_DMA2CONTROL() bfin_read16(USB_DMA2CONTROL)
-#define bfin_write_USB_DMA2CONTROL(val) bfin_write16(USB_DMA2CONTROL, val)
-#define bfin_read_USB_DMA2ADDRLOW() bfin_read16(USB_DMA2ADDRLOW)
-#define bfin_write_USB_DMA2ADDRLOW(val) bfin_write16(USB_DMA2ADDRLOW, val)
-#define bfin_read_USB_DMA2ADDRHIGH() bfin_read16(USB_DMA2ADDRHIGH)
-#define bfin_write_USB_DMA2ADDRHIGH(val) bfin_write16(USB_DMA2ADDRHIGH, val)
-#define bfin_read_USB_DMA2COUNTLOW() bfin_read16(USB_DMA2COUNTLOW)
-#define bfin_write_USB_DMA2COUNTLOW(val) bfin_write16(USB_DMA2COUNTLOW, val)
-#define bfin_read_USB_DMA2COUNTHIGH() bfin_read16(USB_DMA2COUNTHIGH)
-#define bfin_write_USB_DMA2COUNTHIGH(val) bfin_write16(USB_DMA2COUNTHIGH, val)
-
-/* USB Channel 3 Config Registers */
-
-#define bfin_read_USB_DMA3CONTROL() bfin_read16(USB_DMA3CONTROL)
-#define bfin_write_USB_DMA3CONTROL(val) bfin_write16(USB_DMA3CONTROL, val)
-#define bfin_read_USB_DMA3ADDRLOW() bfin_read16(USB_DMA3ADDRLOW)
-#define bfin_write_USB_DMA3ADDRLOW(val) bfin_write16(USB_DMA3ADDRLOW, val)
-#define bfin_read_USB_DMA3ADDRHIGH() bfin_read16(USB_DMA3ADDRHIGH)
-#define bfin_write_USB_DMA3ADDRHIGH(val) bfin_write16(USB_DMA3ADDRHIGH, val)
-#define bfin_read_USB_DMA3COUNTLOW() bfin_read16(USB_DMA3COUNTLOW)
-#define bfin_write_USB_DMA3COUNTLOW(val) bfin_write16(USB_DMA3COUNTLOW, val)
-#define bfin_read_USB_DMA3COUNTHIGH() bfin_read16(USB_DMA3COUNTHIGH)
-#define bfin_write_USB_DMA3COUNTHIGH(val) bfin_write16(USB_DMA3COUNTHIGH, val)
-
-/* USB Channel 4 Config Registers */
-
-#define bfin_read_USB_DMA4CONTROL() bfin_read16(USB_DMA4CONTROL)
-#define bfin_write_USB_DMA4CONTROL(val) bfin_write16(USB_DMA4CONTROL, val)
-#define bfin_read_USB_DMA4ADDRLOW() bfin_read16(USB_DMA4ADDRLOW)
-#define bfin_write_USB_DMA4ADDRLOW(val) bfin_write16(USB_DMA4ADDRLOW, val)
-#define bfin_read_USB_DMA4ADDRHIGH() bfin_read16(USB_DMA4ADDRHIGH)
-#define bfin_write_USB_DMA4ADDRHIGH(val) bfin_write16(USB_DMA4ADDRHIGH, val)
-#define bfin_read_USB_DMA4COUNTLOW() bfin_read16(USB_DMA4COUNTLOW)
-#define bfin_write_USB_DMA4COUNTLOW(val) bfin_write16(USB_DMA4COUNTLOW, val)
-#define bfin_read_USB_DMA4COUNTHIGH() bfin_read16(USB_DMA4COUNTHIGH)
-#define bfin_write_USB_DMA4COUNTHIGH(val) bfin_write16(USB_DMA4COUNTHIGH, val)
-
-/* USB Channel 5 Config Registers */
-
-#define bfin_read_USB_DMA5CONTROL() bfin_read16(USB_DMA5CONTROL)
-#define bfin_write_USB_DMA5CONTROL(val) bfin_write16(USB_DMA5CONTROL, val)
-#define bfin_read_USB_DMA5ADDRLOW() bfin_read16(USB_DMA5ADDRLOW)
-#define bfin_write_USB_DMA5ADDRLOW(val) bfin_write16(USB_DMA5ADDRLOW, val)
-#define bfin_read_USB_DMA5ADDRHIGH() bfin_read16(USB_DMA5ADDRHIGH)
-#define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val)
-#define bfin_read_USB_DMA5COUNTLOW() bfin_read16(USB_DMA5COUNTLOW)
-#define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val)
-#define bfin_read_USB_DMA5COUNTHIGH() bfin_read16(USB_DMA5COUNTHIGH)
-#define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val)
-
-/* USB Channel 6 Config Registers */
-
-#define bfin_read_USB_DMA6CONTROL() bfin_read16(USB_DMA6CONTROL)
-#define bfin_write_USB_DMA6CONTROL(val) bfin_write16(USB_DMA6CONTROL, val)
-#define bfin_read_USB_DMA6ADDRLOW() bfin_read16(USB_DMA6ADDRLOW)
-#define bfin_write_USB_DMA6ADDRLOW(val) bfin_write16(USB_DMA6ADDRLOW, val)
-#define bfin_read_USB_DMA6ADDRHIGH() bfin_read16(USB_DMA6ADDRHIGH)
-#define bfin_write_USB_DMA6ADDRHIGH(val) bfin_write16(USB_DMA6ADDRHIGH, val)
-#define bfin_read_USB_DMA6COUNTLOW() bfin_read16(USB_DMA6COUNTLOW)
-#define bfin_write_USB_DMA6COUNTLOW(val) bfin_write16(USB_DMA6COUNTLOW, val)
-#define bfin_read_USB_DMA6COUNTHIGH() bfin_read16(USB_DMA6COUNTHIGH)
-#define bfin_write_USB_DMA6COUNTHIGH(val) bfin_write16(USB_DMA6COUNTHIGH, val)
-
-/* USB Channel 7 Config Registers */
-
-#define bfin_read_USB_DMA7CONTROL() bfin_read16(USB_DMA7CONTROL)
-#define bfin_write_USB_DMA7CONTROL(val) bfin_write16(USB_DMA7CONTROL, val)
-#define bfin_read_USB_DMA7ADDRLOW() bfin_read16(USB_DMA7ADDRLOW)
-#define bfin_write_USB_DMA7ADDRLOW(val) bfin_write16(USB_DMA7ADDRLOW, val)
-#define bfin_read_USB_DMA7ADDRHIGH() bfin_read16(USB_DMA7ADDRHIGH)
-#define bfin_write_USB_DMA7ADDRHIGH(val) bfin_write16(USB_DMA7ADDRHIGH, val)
-#define bfin_read_USB_DMA7COUNTLOW() bfin_read16(USB_DMA7COUNTLOW)
-#define bfin_write_USB_DMA7COUNTLOW(val) bfin_write16(USB_DMA7COUNTLOW, val)
-#define bfin_read_USB_DMA7COUNTHIGH() bfin_read16(USB_DMA7COUNTHIGH)
-#define bfin_write_USB_DMA7COUNTHIGH(val) bfin_write16(USB_DMA7COUNTHIGH, val)
-
-/* Keybfin_read_()ad Registers */
-
-#define bfin_read_KPAD_CTL() bfin_read16(KPAD_CTL)
-#define bfin_write_KPAD_CTL(val) bfin_write16(KPAD_CTL, val)
-#define bfin_read_KPAD_PRESCALE() bfin_read16(KPAD_PRESCALE)
-#define bfin_write_KPAD_PRESCALE(val) bfin_write16(KPAD_PRESCALE, val)
-#define bfin_read_KPAD_MSEL() bfin_read16(KPAD_MSEL)
-#define bfin_write_KPAD_MSEL(val) bfin_write16(KPAD_MSEL, val)
-#define bfin_read_KPAD_ROWCOL() bfin_read16(KPAD_ROWCOL)
-#define bfin_write_KPAD_ROWCOL(val) bfin_write16(KPAD_ROWCOL, val)
-#define bfin_read_KPAD_STAT() bfin_read16(KPAD_STAT)
-#define bfin_write_KPAD_STAT(val) bfin_write16(KPAD_STAT, val)
-#define bfin_read_KPAD_SOFTEVAL() bfin_read16(KPAD_SOFTEVAL)
-#define bfin_write_KPAD_SOFTEVAL(val) bfin_write16(KPAD_SOFTEVAL, val)
-
-/* Pixel Combfin_read_()ositor (PIXC) Registers */
-
-#define bfin_read_PIXC_CTL() bfin_read16(PIXC_CTL)
-#define bfin_write_PIXC_CTL(val) bfin_write16(PIXC_CTL, val)
-#define bfin_read_PIXC_PPL() bfin_read16(PIXC_PPL)
-#define bfin_write_PIXC_PPL(val) bfin_write16(PIXC_PPL, val)
-#define bfin_read_PIXC_LPF() bfin_read16(PIXC_LPF)
-#define bfin_write_PIXC_LPF(val) bfin_write16(PIXC_LPF, val)
-#define bfin_read_PIXC_AHSTART() bfin_read16(PIXC_AHSTART)
-#define bfin_write_PIXC_AHSTART(val) bfin_write16(PIXC_AHSTART, val)
-#define bfin_read_PIXC_AHEND() bfin_read16(PIXC_AHEND)
-#define bfin_write_PIXC_AHEND(val) bfin_write16(PIXC_AHEND, val)
-#define bfin_read_PIXC_AVSTART() bfin_read16(PIXC_AVSTART)
-#define bfin_write_PIXC_AVSTART(val) bfin_write16(PIXC_AVSTART, val)
-#define bfin_read_PIXC_AVEND() bfin_read16(PIXC_AVEND)
-#define bfin_write_PIXC_AVEND(val) bfin_write16(PIXC_AVEND, val)
-#define bfin_read_PIXC_ATRANSP() bfin_read16(PIXC_ATRANSP)
-#define bfin_write_PIXC_ATRANSP(val) bfin_write16(PIXC_ATRANSP, val)
-#define bfin_read_PIXC_BHSTART() bfin_read16(PIXC_BHSTART)
-#define bfin_write_PIXC_BHSTART(val) bfin_write16(PIXC_BHSTART, val)
-#define bfin_read_PIXC_BHEND() bfin_read16(PIXC_BHEND)
-#define bfin_write_PIXC_BHEND(val) bfin_write16(PIXC_BHEND, val)
-#define bfin_read_PIXC_BVSTART() bfin_read16(PIXC_BVSTART)
-#define bfin_write_PIXC_BVSTART(val) bfin_write16(PIXC_BVSTART, val)
-#define bfin_read_PIXC_BVEND() bfin_read16(PIXC_BVEND)
-#define bfin_write_PIXC_BVEND(val) bfin_write16(PIXC_BVEND, val)
-#define bfin_read_PIXC_BTRANSP() bfin_read16(PIXC_BTRANSP)
-#define bfin_write_PIXC_BTRANSP(val) bfin_write16(PIXC_BTRANSP, val)
-#define bfin_read_PIXC_INTRSTAT() bfin_read16(PIXC_INTRSTAT)
-#define bfin_write_PIXC_INTRSTAT(val) bfin_write16(PIXC_INTRSTAT, val)
-#define bfin_read_PIXC_RYCON() bfin_read32(PIXC_RYCON)
-#define bfin_write_PIXC_RYCON(val) bfin_write32(PIXC_RYCON, val)
-#define bfin_read_PIXC_GUCON() bfin_read32(PIXC_GUCON)
-#define bfin_write_PIXC_GUCON(val) bfin_write32(PIXC_GUCON, val)
-#define bfin_read_PIXC_BVCON() bfin_read32(PIXC_BVCON)
-#define bfin_write_PIXC_BVCON(val) bfin_write32(PIXC_BVCON, val)
-#define bfin_read_PIXC_CCBIAS() bfin_read32(PIXC_CCBIAS)
-#define bfin_write_PIXC_CCBIAS(val) bfin_write32(PIXC_CCBIAS, val)
-#define bfin_read_PIXC_TC() bfin_read32(PIXC_TC)
-#define bfin_write_PIXC_TC(val) bfin_write32(PIXC_TC, val)
-
-/* Handshake MDMA 0 Registers */
-
-#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
-#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
-#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
-#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
-#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
-#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
-#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
-#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
-#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
-#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
-#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
-#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
-#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
-#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
-
-/* Handshake MDMA 1 Registers */
-
-#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
-#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
-#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
-#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
-#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
-#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
-#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
-#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
-#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
-#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
-#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
-#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
-#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
-#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
-
-#endif /* _CDEF_BF547_H */
+++ /dev/null
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CDEF_BF548_H
-#define _CDEF_BF548_H
-
-/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
-#include "cdefBF54x_base.h"
-
-/* The BF548 is like the BF547, but has additional CANs */
-#include "cdefBF547.h"
-
-/* CAN Controller 1 Config 1 Registers */
-
-#define bfin_read_CAN1_MC1() bfin_read16(CAN1_MC1)
-#define bfin_write_CAN1_MC1(val) bfin_write16(CAN1_MC1, val)
-#define bfin_read_CAN1_MD1() bfin_read16(CAN1_MD1)
-#define bfin_write_CAN1_MD1(val) bfin_write16(CAN1_MD1, val)
-#define bfin_read_CAN1_TRS1() bfin_read16(CAN1_TRS1)
-#define bfin_write_CAN1_TRS1(val) bfin_write16(CAN1_TRS1, val)
-#define bfin_read_CAN1_TRR1() bfin_read16(CAN1_TRR1)
-#define bfin_write_CAN1_TRR1(val) bfin_write16(CAN1_TRR1, val)
-#define bfin_read_CAN1_TA1() bfin_read16(CAN1_TA1)
-#define bfin_write_CAN1_TA1(val) bfin_write16(CAN1_TA1, val)
-#define bfin_read_CAN1_AA1() bfin_read16(CAN1_AA1)
-#define bfin_write_CAN1_AA1(val) bfin_write16(CAN1_AA1, val)
-#define bfin_read_CAN1_RMP1() bfin_read16(CAN1_RMP1)
-#define bfin_write_CAN1_RMP1(val) bfin_write16(CAN1_RMP1, val)
-#define bfin_read_CAN1_RML1() bfin_read16(CAN1_RML1)
-#define bfin_write_CAN1_RML1(val) bfin_write16(CAN1_RML1, val)
-#define bfin_read_CAN1_MBTIF1() bfin_read16(CAN1_MBTIF1)
-#define bfin_write_CAN1_MBTIF1(val) bfin_write16(CAN1_MBTIF1, val)
-#define bfin_read_CAN1_MBRIF1() bfin_read16(CAN1_MBRIF1)
-#define bfin_write_CAN1_MBRIF1(val) bfin_write16(CAN1_MBRIF1, val)
-#define bfin_read_CAN1_MBIM1() bfin_read16(CAN1_MBIM1)
-#define bfin_write_CAN1_MBIM1(val) bfin_write16(CAN1_MBIM1, val)
-#define bfin_read_CAN1_RFH1() bfin_read16(CAN1_RFH1)
-#define bfin_write_CAN1_RFH1(val) bfin_write16(CAN1_RFH1, val)
-#define bfin_read_CAN1_OPSS1() bfin_read16(CAN1_OPSS1)
-#define bfin_write_CAN1_OPSS1(val) bfin_write16(CAN1_OPSS1, val)
-
-/* CAN Controller 1 Config 2 Registers */
-
-#define bfin_read_CAN1_MC2() bfin_read16(CAN1_MC2)
-#define bfin_write_CAN1_MC2(val) bfin_write16(CAN1_MC2, val)
-#define bfin_read_CAN1_MD2() bfin_read16(CAN1_MD2)
-#define bfin_write_CAN1_MD2(val) bfin_write16(CAN1_MD2, val)
-#define bfin_read_CAN1_TRS2() bfin_read16(CAN1_TRS2)
-#define bfin_write_CAN1_TRS2(val) bfin_write16(CAN1_TRS2, val)
-#define bfin_read_CAN1_TRR2() bfin_read16(CAN1_TRR2)
-#define bfin_write_CAN1_TRR2(val) bfin_write16(CAN1_TRR2, val)
-#define bfin_read_CAN1_TA2() bfin_read16(CAN1_TA2)
-#define bfin_write_CAN1_TA2(val) bfin_write16(CAN1_TA2, val)
-#define bfin_read_CAN1_AA2() bfin_read16(CAN1_AA2)
-#define bfin_write_CAN1_AA2(val) bfin_write16(CAN1_AA2, val)
-#define bfin_read_CAN1_RMP2() bfin_read16(CAN1_RMP2)
-#define bfin_write_CAN1_RMP2(val) bfin_write16(CAN1_RMP2, val)
-#define bfin_read_CAN1_RML2() bfin_read16(CAN1_RML2)
-#define bfin_write_CAN1_RML2(val) bfin_write16(CAN1_RML2, val)
-#define bfin_read_CAN1_MBTIF2() bfin_read16(CAN1_MBTIF2)
-#define bfin_write_CAN1_MBTIF2(val) bfin_write16(CAN1_MBTIF2, val)
-#define bfin_read_CAN1_MBRIF2() bfin_read16(CAN1_MBRIF2)
-#define bfin_write_CAN1_MBRIF2(val) bfin_write16(CAN1_MBRIF2, val)
-#define bfin_read_CAN1_MBIM2() bfin_read16(CAN1_MBIM2)
-#define bfin_write_CAN1_MBIM2(val) bfin_write16(CAN1_MBIM2, val)
-#define bfin_read_CAN1_RFH2() bfin_read16(CAN1_RFH2)
-#define bfin_write_CAN1_RFH2(val) bfin_write16(CAN1_RFH2, val)
-#define bfin_read_CAN1_OPSS2() bfin_read16(CAN1_OPSS2)
-#define bfin_write_CAN1_OPSS2(val) bfin_write16(CAN1_OPSS2, val)
-
-/* CAN Controller 1 Clock/Interrubfin_read_()t/Counter Registers */
-
-#define bfin_read_CAN1_CLOCK() bfin_read16(CAN1_CLOCK)
-#define bfin_write_CAN1_CLOCK(val) bfin_write16(CAN1_CLOCK, val)
-#define bfin_read_CAN1_TIMING() bfin_read16(CAN1_TIMING)
-#define bfin_write_CAN1_TIMING(val) bfin_write16(CAN1_TIMING, val)
-#define bfin_read_CAN1_DEBUG() bfin_read16(CAN1_DEBUG)
-#define bfin_write_CAN1_DEBUG(val) bfin_write16(CAN1_DEBUG, val)
-#define bfin_read_CAN1_STATUS() bfin_read16(CAN1_STATUS)
-#define bfin_write_CAN1_STATUS(val) bfin_write16(CAN1_STATUS, val)
-#define bfin_read_CAN1_CEC() bfin_read16(CAN1_CEC)
-#define bfin_write_CAN1_CEC(val) bfin_write16(CAN1_CEC, val)
-#define bfin_read_CAN1_GIS() bfin_read16(CAN1_GIS)
-#define bfin_write_CAN1_GIS(val) bfin_write16(CAN1_GIS, val)
-#define bfin_read_CAN1_GIM() bfin_read16(CAN1_GIM)
-#define bfin_write_CAN1_GIM(val) bfin_write16(CAN1_GIM, val)
-#define bfin_read_CAN1_GIF() bfin_read16(CAN1_GIF)
-#define bfin_write_CAN1_GIF(val) bfin_write16(CAN1_GIF, val)
-#define bfin_read_CAN1_CONTROL() bfin_read16(CAN1_CONTROL)
-#define bfin_write_CAN1_CONTROL(val) bfin_write16(CAN1_CONTROL, val)
-#define bfin_read_CAN1_INTR() bfin_read16(CAN1_INTR)
-#define bfin_write_CAN1_INTR(val) bfin_write16(CAN1_INTR, val)
-#define bfin_read_CAN1_MBTD() bfin_read16(CAN1_MBTD)
-#define bfin_write_CAN1_MBTD(val) bfin_write16(CAN1_MBTD, val)
-#define bfin_read_CAN1_EWR() bfin_read16(CAN1_EWR)
-#define bfin_write_CAN1_EWR(val) bfin_write16(CAN1_EWR, val)
-#define bfin_read_CAN1_ESR() bfin_read16(CAN1_ESR)
-#define bfin_write_CAN1_ESR(val) bfin_write16(CAN1_ESR, val)
-#define bfin_read_CAN1_UCCNT() bfin_read16(CAN1_UCCNT)
-#define bfin_write_CAN1_UCCNT(val) bfin_write16(CAN1_UCCNT, val)
-#define bfin_read_CAN1_UCRC() bfin_read16(CAN1_UCRC)
-#define bfin_write_CAN1_UCRC(val) bfin_write16(CAN1_UCRC, val)
-#define bfin_read_CAN1_UCCNF() bfin_read16(CAN1_UCCNF)
-#define bfin_write_CAN1_UCCNF(val) bfin_write16(CAN1_UCCNF, val)
-
-/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */
-
-#define bfin_read_CAN1_AM00L() bfin_read16(CAN1_AM00L)
-#define bfin_write_CAN1_AM00L(val) bfin_write16(CAN1_AM00L, val)
-#define bfin_read_CAN1_AM00H() bfin_read16(CAN1_AM00H)
-#define bfin_write_CAN1_AM00H(val) bfin_write16(CAN1_AM00H, val)
-#define bfin_read_CAN1_AM01L() bfin_read16(CAN1_AM01L)
-#define bfin_write_CAN1_AM01L(val) bfin_write16(CAN1_AM01L, val)
-#define bfin_read_CAN1_AM01H() bfin_read16(CAN1_AM01H)
-#define bfin_write_CAN1_AM01H(val) bfin_write16(CAN1_AM01H, val)
-#define bfin_read_CAN1_AM02L() bfin_read16(CAN1_AM02L)
-#define bfin_write_CAN1_AM02L(val) bfin_write16(CAN1_AM02L, val)
-#define bfin_read_CAN1_AM02H() bfin_read16(CAN1_AM02H)
-#define bfin_write_CAN1_AM02H(val) bfin_write16(CAN1_AM02H, val)
-#define bfin_read_CAN1_AM03L() bfin_read16(CAN1_AM03L)
-#define bfin_write_CAN1_AM03L(val) bfin_write16(CAN1_AM03L, val)
-#define bfin_read_CAN1_AM03H() bfin_read16(CAN1_AM03H)
-#define bfin_write_CAN1_AM03H(val) bfin_write16(CAN1_AM03H, val)
-#define bfin_read_CAN1_AM04L() bfin_read16(CAN1_AM04L)
-#define bfin_write_CAN1_AM04L(val) bfin_write16(CAN1_AM04L, val)
-#define bfin_read_CAN1_AM04H() bfin_read16(CAN1_AM04H)
-#define bfin_write_CAN1_AM04H(val) bfin_write16(CAN1_AM04H, val)
-#define bfin_read_CAN1_AM05L() bfin_read16(CAN1_AM05L)
-#define bfin_write_CAN1_AM05L(val) bfin_write16(CAN1_AM05L, val)
-#define bfin_read_CAN1_AM05H() bfin_read16(CAN1_AM05H)
-#define bfin_write_CAN1_AM05H(val) bfin_write16(CAN1_AM05H, val)
-#define bfin_read_CAN1_AM06L() bfin_read16(CAN1_AM06L)
-#define bfin_write_CAN1_AM06L(val) bfin_write16(CAN1_AM06L, val)
-#define bfin_read_CAN1_AM06H() bfin_read16(CAN1_AM06H)
-#define bfin_write_CAN1_AM06H(val) bfin_write16(CAN1_AM06H, val)
-#define bfin_read_CAN1_AM07L() bfin_read16(CAN1_AM07L)
-#define bfin_write_CAN1_AM07L(val) bfin_write16(CAN1_AM07L, val)
-#define bfin_read_CAN1_AM07H() bfin_read16(CAN1_AM07H)
-#define bfin_write_CAN1_AM07H(val) bfin_write16(CAN1_AM07H, val)
-#define bfin_read_CAN1_AM08L() bfin_read16(CAN1_AM08L)
-#define bfin_write_CAN1_AM08L(val) bfin_write16(CAN1_AM08L, val)
-#define bfin_read_CAN1_AM08H() bfin_read16(CAN1_AM08H)
-#define bfin_write_CAN1_AM08H(val) bfin_write16(CAN1_AM08H, val)
-#define bfin_read_CAN1_AM09L() bfin_read16(CAN1_AM09L)
-#define bfin_write_CAN1_AM09L(val) bfin_write16(CAN1_AM09L, val)
-#define bfin_read_CAN1_AM09H() bfin_read16(CAN1_AM09H)
-#define bfin_write_CAN1_AM09H(val) bfin_write16(CAN1_AM09H, val)
-#define bfin_read_CAN1_AM10L() bfin_read16(CAN1_AM10L)
-#define bfin_write_CAN1_AM10L(val) bfin_write16(CAN1_AM10L, val)
-#define bfin_read_CAN1_AM10H() bfin_read16(CAN1_AM10H)
-#define bfin_write_CAN1_AM10H(val) bfin_write16(CAN1_AM10H, val)
-#define bfin_read_CAN1_AM11L() bfin_read16(CAN1_AM11L)
-#define bfin_write_CAN1_AM11L(val) bfin_write16(CAN1_AM11L, val)
-#define bfin_read_CAN1_AM11H() bfin_read16(CAN1_AM11H)
-#define bfin_write_CAN1_AM11H(val) bfin_write16(CAN1_AM11H, val)
-#define bfin_read_CAN1_AM12L() bfin_read16(CAN1_AM12L)
-#define bfin_write_CAN1_AM12L(val) bfin_write16(CAN1_AM12L, val)
-#define bfin_read_CAN1_AM12H() bfin_read16(CAN1_AM12H)
-#define bfin_write_CAN1_AM12H(val) bfin_write16(CAN1_AM12H, val)
-#define bfin_read_CAN1_AM13L() bfin_read16(CAN1_AM13L)
-#define bfin_write_CAN1_AM13L(val) bfin_write16(CAN1_AM13L, val)
-#define bfin_read_CAN1_AM13H() bfin_read16(CAN1_AM13H)
-#define bfin_write_CAN1_AM13H(val) bfin_write16(CAN1_AM13H, val)
-#define bfin_read_CAN1_AM14L() bfin_read16(CAN1_AM14L)
-#define bfin_write_CAN1_AM14L(val) bfin_write16(CAN1_AM14L, val)
-#define bfin_read_CAN1_AM14H() bfin_read16(CAN1_AM14H)
-#define bfin_write_CAN1_AM14H(val) bfin_write16(CAN1_AM14H, val)
-#define bfin_read_CAN1_AM15L() bfin_read16(CAN1_AM15L)
-#define bfin_write_CAN1_AM15L(val) bfin_write16(CAN1_AM15L, val)
-#define bfin_read_CAN1_AM15H() bfin_read16(CAN1_AM15H)
-#define bfin_write_CAN1_AM15H(val) bfin_write16(CAN1_AM15H, val)
-
-/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */
-
-#define bfin_read_CAN1_AM16L() bfin_read16(CAN1_AM16L)
-#define bfin_write_CAN1_AM16L(val) bfin_write16(CAN1_AM16L, val)
-#define bfin_read_CAN1_AM16H() bfin_read16(CAN1_AM16H)
-#define bfin_write_CAN1_AM16H(val) bfin_write16(CAN1_AM16H, val)
-#define bfin_read_CAN1_AM17L() bfin_read16(CAN1_AM17L)
-#define bfin_write_CAN1_AM17L(val) bfin_write16(CAN1_AM17L, val)
-#define bfin_read_CAN1_AM17H() bfin_read16(CAN1_AM17H)
-#define bfin_write_CAN1_AM17H(val) bfin_write16(CAN1_AM17H, val)
-#define bfin_read_CAN1_AM18L() bfin_read16(CAN1_AM18L)
-#define bfin_write_CAN1_AM18L(val) bfin_write16(CAN1_AM18L, val)
-#define bfin_read_CAN1_AM18H() bfin_read16(CAN1_AM18H)
-#define bfin_write_CAN1_AM18H(val) bfin_write16(CAN1_AM18H, val)
-#define bfin_read_CAN1_AM19L() bfin_read16(CAN1_AM19L)
-#define bfin_write_CAN1_AM19L(val) bfin_write16(CAN1_AM19L, val)
-#define bfin_read_CAN1_AM19H() bfin_read16(CAN1_AM19H)
-#define bfin_write_CAN1_AM19H(val) bfin_write16(CAN1_AM19H, val)
-#define bfin_read_CAN1_AM20L() bfin_read16(CAN1_AM20L)
-#define bfin_write_CAN1_AM20L(val) bfin_write16(CAN1_AM20L, val)
-#define bfin_read_CAN1_AM20H() bfin_read16(CAN1_AM20H)
-#define bfin_write_CAN1_AM20H(val) bfin_write16(CAN1_AM20H, val)
-#define bfin_read_CAN1_AM21L() bfin_read16(CAN1_AM21L)
-#define bfin_write_CAN1_AM21L(val) bfin_write16(CAN1_AM21L, val)
-#define bfin_read_CAN1_AM21H() bfin_read16(CAN1_AM21H)
-#define bfin_write_CAN1_AM21H(val) bfin_write16(CAN1_AM21H, val)
-#define bfin_read_CAN1_AM22L() bfin_read16(CAN1_AM22L)
-#define bfin_write_CAN1_AM22L(val) bfin_write16(CAN1_AM22L, val)
-#define bfin_read_CAN1_AM22H() bfin_read16(CAN1_AM22H)
-#define bfin_write_CAN1_AM22H(val) bfin_write16(CAN1_AM22H, val)
-#define bfin_read_CAN1_AM23L() bfin_read16(CAN1_AM23L)
-#define bfin_write_CAN1_AM23L(val) bfin_write16(CAN1_AM23L, val)
-#define bfin_read_CAN1_AM23H() bfin_read16(CAN1_AM23H)
-#define bfin_write_CAN1_AM23H(val) bfin_write16(CAN1_AM23H, val)
-#define bfin_read_CAN1_AM24L() bfin_read16(CAN1_AM24L)
-#define bfin_write_CAN1_AM24L(val) bfin_write16(CAN1_AM24L, val)
-#define bfin_read_CAN1_AM24H() bfin_read16(CAN1_AM24H)
-#define bfin_write_CAN1_AM24H(val) bfin_write16(CAN1_AM24H, val)
-#define bfin_read_CAN1_AM25L() bfin_read16(CAN1_AM25L)
-#define bfin_write_CAN1_AM25L(val) bfin_write16(CAN1_AM25L, val)
-#define bfin_read_CAN1_AM25H() bfin_read16(CAN1_AM25H)
-#define bfin_write_CAN1_AM25H(val) bfin_write16(CAN1_AM25H, val)
-#define bfin_read_CAN1_AM26L() bfin_read16(CAN1_AM26L)
-#define bfin_write_CAN1_AM26L(val) bfin_write16(CAN1_AM26L, val)
-#define bfin_read_CAN1_AM26H() bfin_read16(CAN1_AM26H)
-#define bfin_write_CAN1_AM26H(val) bfin_write16(CAN1_AM26H, val)
-#define bfin_read_CAN1_AM27L() bfin_read16(CAN1_AM27L)
-#define bfin_write_CAN1_AM27L(val) bfin_write16(CAN1_AM27L, val)
-#define bfin_read_CAN1_AM27H() bfin_read16(CAN1_AM27H)
-#define bfin_write_CAN1_AM27H(val) bfin_write16(CAN1_AM27H, val)
-#define bfin_read_CAN1_AM28L() bfin_read16(CAN1_AM28L)
-#define bfin_write_CAN1_AM28L(val) bfin_write16(CAN1_AM28L, val)
-#define bfin_read_CAN1_AM28H() bfin_read16(CAN1_AM28H)
-#define bfin_write_CAN1_AM28H(val) bfin_write16(CAN1_AM28H, val)
-#define bfin_read_CAN1_AM29L() bfin_read16(CAN1_AM29L)
-#define bfin_write_CAN1_AM29L(val) bfin_write16(CAN1_AM29L, val)
-#define bfin_read_CAN1_AM29H() bfin_read16(CAN1_AM29H)
-#define bfin_write_CAN1_AM29H(val) bfin_write16(CAN1_AM29H, val)
-#define bfin_read_CAN1_AM30L() bfin_read16(CAN1_AM30L)
-#define bfin_write_CAN1_AM30L(val) bfin_write16(CAN1_AM30L, val)
-#define bfin_read_CAN1_AM30H() bfin_read16(CAN1_AM30H)
-#define bfin_write_CAN1_AM30H(val) bfin_write16(CAN1_AM30H, val)
-#define bfin_read_CAN1_AM31L() bfin_read16(CAN1_AM31L)
-#define bfin_write_CAN1_AM31L(val) bfin_write16(CAN1_AM31L, val)
-#define bfin_read_CAN1_AM31H() bfin_read16(CAN1_AM31H)
-#define bfin_write_CAN1_AM31H(val) bfin_write16(CAN1_AM31H, val)
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define bfin_read_CAN1_MB00_DATA0() bfin_read16(CAN1_MB00_DATA0)
-#define bfin_write_CAN1_MB00_DATA0(val) bfin_write16(CAN1_MB00_DATA0, val)
-#define bfin_read_CAN1_MB00_DATA1() bfin_read16(CAN1_MB00_DATA1)
-#define bfin_write_CAN1_MB00_DATA1(val) bfin_write16(CAN1_MB00_DATA1, val)
-#define bfin_read_CAN1_MB00_DATA2() bfin_read16(CAN1_MB00_DATA2)
-#define bfin_write_CAN1_MB00_DATA2(val) bfin_write16(CAN1_MB00_DATA2, val)
-#define bfin_read_CAN1_MB00_DATA3() bfin_read16(CAN1_MB00_DATA3)
-#define bfin_write_CAN1_MB00_DATA3(val) bfin_write16(CAN1_MB00_DATA3, val)
-#define bfin_read_CAN1_MB00_LENGTH() bfin_read16(CAN1_MB00_LENGTH)
-#define bfin_write_CAN1_MB00_LENGTH(val) bfin_write16(CAN1_MB00_LENGTH, val)
-#define bfin_read_CAN1_MB00_TIMESTAMP() bfin_read16(CAN1_MB00_TIMESTAMP)
-#define bfin_write_CAN1_MB00_TIMESTAMP(val) bfin_write16(CAN1_MB00_TIMESTAMP, val)
-#define bfin_read_CAN1_MB00_ID0() bfin_read16(CAN1_MB00_ID0)
-#define bfin_write_CAN1_MB00_ID0(val) bfin_write16(CAN1_MB00_ID0, val)
-#define bfin_read_CAN1_MB00_ID1() bfin_read16(CAN1_MB00_ID1)
-#define bfin_write_CAN1_MB00_ID1(val) bfin_write16(CAN1_MB00_ID1, val)
-#define bfin_read_CAN1_MB01_DATA0() bfin_read16(CAN1_MB01_DATA0)
-#define bfin_write_CAN1_MB01_DATA0(val) bfin_write16(CAN1_MB01_DATA0, val)
-#define bfin_read_CAN1_MB01_DATA1() bfin_read16(CAN1_MB01_DATA1)
-#define bfin_write_CAN1_MB01_DATA1(val) bfin_write16(CAN1_MB01_DATA1, val)
-#define bfin_read_CAN1_MB01_DATA2() bfin_read16(CAN1_MB01_DATA2)
-#define bfin_write_CAN1_MB01_DATA2(val) bfin_write16(CAN1_MB01_DATA2, val)
-#define bfin_read_CAN1_MB01_DATA3() bfin_read16(CAN1_MB01_DATA3)
-#define bfin_write_CAN1_MB01_DATA3(val) bfin_write16(CAN1_MB01_DATA3, val)
-#define bfin_read_CAN1_MB01_LENGTH() bfin_read16(CAN1_MB01_LENGTH)
-#define bfin_write_CAN1_MB01_LENGTH(val) bfin_write16(CAN1_MB01_LENGTH, val)
-#define bfin_read_CAN1_MB01_TIMESTAMP() bfin_read16(CAN1_MB01_TIMESTAMP)
-#define bfin_write_CAN1_MB01_TIMESTAMP(val) bfin_write16(CAN1_MB01_TIMESTAMP, val)
-#define bfin_read_CAN1_MB01_ID0() bfin_read16(CAN1_MB01_ID0)
-#define bfin_write_CAN1_MB01_ID0(val) bfin_write16(CAN1_MB01_ID0, val)
-#define bfin_read_CAN1_MB01_ID1() bfin_read16(CAN1_MB01_ID1)
-#define bfin_write_CAN1_MB01_ID1(val) bfin_write16(CAN1_MB01_ID1, val)
-#define bfin_read_CAN1_MB02_DATA0() bfin_read16(CAN1_MB02_DATA0)
-#define bfin_write_CAN1_MB02_DATA0(val) bfin_write16(CAN1_MB02_DATA0, val)
-#define bfin_read_CAN1_MB02_DATA1() bfin_read16(CAN1_MB02_DATA1)
-#define bfin_write_CAN1_MB02_DATA1(val) bfin_write16(CAN1_MB02_DATA1, val)
-#define bfin_read_CAN1_MB02_DATA2() bfin_read16(CAN1_MB02_DATA2)
-#define bfin_write_CAN1_MB02_DATA2(val) bfin_write16(CAN1_MB02_DATA2, val)
-#define bfin_read_CAN1_MB02_DATA3() bfin_read16(CAN1_MB02_DATA3)
-#define bfin_write_CAN1_MB02_DATA3(val) bfin_write16(CAN1_MB02_DATA3, val)
-#define bfin_read_CAN1_MB02_LENGTH() bfin_read16(CAN1_MB02_LENGTH)
-#define bfin_write_CAN1_MB02_LENGTH(val) bfin_write16(CAN1_MB02_LENGTH, val)
-#define bfin_read_CAN1_MB02_TIMESTAMP() bfin_read16(CAN1_MB02_TIMESTAMP)
-#define bfin_write_CAN1_MB02_TIMESTAMP(val) bfin_write16(CAN1_MB02_TIMESTAMP, val)
-#define bfin_read_CAN1_MB02_ID0() bfin_read16(CAN1_MB02_ID0)
-#define bfin_write_CAN1_MB02_ID0(val) bfin_write16(CAN1_MB02_ID0, val)
-#define bfin_read_CAN1_MB02_ID1() bfin_read16(CAN1_MB02_ID1)
-#define bfin_write_CAN1_MB02_ID1(val) bfin_write16(CAN1_MB02_ID1, val)
-#define bfin_read_CAN1_MB03_DATA0() bfin_read16(CAN1_MB03_DATA0)
-#define bfin_write_CAN1_MB03_DATA0(val) bfin_write16(CAN1_MB03_DATA0, val)
-#define bfin_read_CAN1_MB03_DATA1() bfin_read16(CAN1_MB03_DATA1)
-#define bfin_write_CAN1_MB03_DATA1(val) bfin_write16(CAN1_MB03_DATA1, val)
-#define bfin_read_CAN1_MB03_DATA2() bfin_read16(CAN1_MB03_DATA2)
-#define bfin_write_CAN1_MB03_DATA2(val) bfin_write16(CAN1_MB03_DATA2, val)
-#define bfin_read_CAN1_MB03_DATA3() bfin_read16(CAN1_MB03_DATA3)
-#define bfin_write_CAN1_MB03_DATA3(val) bfin_write16(CAN1_MB03_DATA3, val)
-#define bfin_read_CAN1_MB03_LENGTH() bfin_read16(CAN1_MB03_LENGTH)
-#define bfin_write_CAN1_MB03_LENGTH(val) bfin_write16(CAN1_MB03_LENGTH, val)
-#define bfin_read_CAN1_MB03_TIMESTAMP() bfin_read16(CAN1_MB03_TIMESTAMP)
-#define bfin_write_CAN1_MB03_TIMESTAMP(val) bfin_write16(CAN1_MB03_TIMESTAMP, val)
-#define bfin_read_CAN1_MB03_ID0() bfin_read16(CAN1_MB03_ID0)
-#define bfin_write_CAN1_MB03_ID0(val) bfin_write16(CAN1_MB03_ID0, val)
-#define bfin_read_CAN1_MB03_ID1() bfin_read16(CAN1_MB03_ID1)
-#define bfin_write_CAN1_MB03_ID1(val) bfin_write16(CAN1_MB03_ID1, val)
-#define bfin_read_CAN1_MB04_DATA0() bfin_read16(CAN1_MB04_DATA0)
-#define bfin_write_CAN1_MB04_DATA0(val) bfin_write16(CAN1_MB04_DATA0, val)
-#define bfin_read_CAN1_MB04_DATA1() bfin_read16(CAN1_MB04_DATA1)
-#define bfin_write_CAN1_MB04_DATA1(val) bfin_write16(CAN1_MB04_DATA1, val)
-#define bfin_read_CAN1_MB04_DATA2() bfin_read16(CAN1_MB04_DATA2)
-#define bfin_write_CAN1_MB04_DATA2(val) bfin_write16(CAN1_MB04_DATA2, val)
-#define bfin_read_CAN1_MB04_DATA3() bfin_read16(CAN1_MB04_DATA3)
-#define bfin_write_CAN1_MB04_DATA3(val) bfin_write16(CAN1_MB04_DATA3, val)
-#define bfin_read_CAN1_MB04_LENGTH() bfin_read16(CAN1_MB04_LENGTH)
-#define bfin_write_CAN1_MB04_LENGTH(val) bfin_write16(CAN1_MB04_LENGTH, val)
-#define bfin_read_CAN1_MB04_TIMESTAMP() bfin_read16(CAN1_MB04_TIMESTAMP)
-#define bfin_write_CAN1_MB04_TIMESTAMP(val) bfin_write16(CAN1_MB04_TIMESTAMP, val)
-#define bfin_read_CAN1_MB04_ID0() bfin_read16(CAN1_MB04_ID0)
-#define bfin_write_CAN1_MB04_ID0(val) bfin_write16(CAN1_MB04_ID0, val)
-#define bfin_read_CAN1_MB04_ID1() bfin_read16(CAN1_MB04_ID1)
-#define bfin_write_CAN1_MB04_ID1(val) bfin_write16(CAN1_MB04_ID1, val)
-#define bfin_read_CAN1_MB05_DATA0() bfin_read16(CAN1_MB05_DATA0)
-#define bfin_write_CAN1_MB05_DATA0(val) bfin_write16(CAN1_MB05_DATA0, val)
-#define bfin_read_CAN1_MB05_DATA1() bfin_read16(CAN1_MB05_DATA1)
-#define bfin_write_CAN1_MB05_DATA1(val) bfin_write16(CAN1_MB05_DATA1, val)
-#define bfin_read_CAN1_MB05_DATA2() bfin_read16(CAN1_MB05_DATA2)
-#define bfin_write_CAN1_MB05_DATA2(val) bfin_write16(CAN1_MB05_DATA2, val)
-#define bfin_read_CAN1_MB05_DATA3() bfin_read16(CAN1_MB05_DATA3)
-#define bfin_write_CAN1_MB05_DATA3(val) bfin_write16(CAN1_MB05_DATA3, val)
-#define bfin_read_CAN1_MB05_LENGTH() bfin_read16(CAN1_MB05_LENGTH)
-#define bfin_write_CAN1_MB05_LENGTH(val) bfin_write16(CAN1_MB05_LENGTH, val)
-#define bfin_read_CAN1_MB05_TIMESTAMP() bfin_read16(CAN1_MB05_TIMESTAMP)
-#define bfin_write_CAN1_MB05_TIMESTAMP(val) bfin_write16(CAN1_MB05_TIMESTAMP, val)
-#define bfin_read_CAN1_MB05_ID0() bfin_read16(CAN1_MB05_ID0)
-#define bfin_write_CAN1_MB05_ID0(val) bfin_write16(CAN1_MB05_ID0, val)
-#define bfin_read_CAN1_MB05_ID1() bfin_read16(CAN1_MB05_ID1)
-#define bfin_write_CAN1_MB05_ID1(val) bfin_write16(CAN1_MB05_ID1, val)
-#define bfin_read_CAN1_MB06_DATA0() bfin_read16(CAN1_MB06_DATA0)
-#define bfin_write_CAN1_MB06_DATA0(val) bfin_write16(CAN1_MB06_DATA0, val)
-#define bfin_read_CAN1_MB06_DATA1() bfin_read16(CAN1_MB06_DATA1)
-#define bfin_write_CAN1_MB06_DATA1(val) bfin_write16(CAN1_MB06_DATA1, val)
-#define bfin_read_CAN1_MB06_DATA2() bfin_read16(CAN1_MB06_DATA2)
-#define bfin_write_CAN1_MB06_DATA2(val) bfin_write16(CAN1_MB06_DATA2, val)
-#define bfin_read_CAN1_MB06_DATA3() bfin_read16(CAN1_MB06_DATA3)
-#define bfin_write_CAN1_MB06_DATA3(val) bfin_write16(CAN1_MB06_DATA3, val)
-#define bfin_read_CAN1_MB06_LENGTH() bfin_read16(CAN1_MB06_LENGTH)
-#define bfin_write_CAN1_MB06_LENGTH(val) bfin_write16(CAN1_MB06_LENGTH, val)
-#define bfin_read_CAN1_MB06_TIMESTAMP() bfin_read16(CAN1_MB06_TIMESTAMP)
-#define bfin_write_CAN1_MB06_TIMESTAMP(val) bfin_write16(CAN1_MB06_TIMESTAMP, val)
-#define bfin_read_CAN1_MB06_ID0() bfin_read16(CAN1_MB06_ID0)
-#define bfin_write_CAN1_MB06_ID0(val) bfin_write16(CAN1_MB06_ID0, val)
-#define bfin_read_CAN1_MB06_ID1() bfin_read16(CAN1_MB06_ID1)
-#define bfin_write_CAN1_MB06_ID1(val) bfin_write16(CAN1_MB06_ID1, val)
-#define bfin_read_CAN1_MB07_DATA0() bfin_read16(CAN1_MB07_DATA0)
-#define bfin_write_CAN1_MB07_DATA0(val) bfin_write16(CAN1_MB07_DATA0, val)
-#define bfin_read_CAN1_MB07_DATA1() bfin_read16(CAN1_MB07_DATA1)
-#define bfin_write_CAN1_MB07_DATA1(val) bfin_write16(CAN1_MB07_DATA1, val)
-#define bfin_read_CAN1_MB07_DATA2() bfin_read16(CAN1_MB07_DATA2)
-#define bfin_write_CAN1_MB07_DATA2(val) bfin_write16(CAN1_MB07_DATA2, val)
-#define bfin_read_CAN1_MB07_DATA3() bfin_read16(CAN1_MB07_DATA3)
-#define bfin_write_CAN1_MB07_DATA3(val) bfin_write16(CAN1_MB07_DATA3, val)
-#define bfin_read_CAN1_MB07_LENGTH() bfin_read16(CAN1_MB07_LENGTH)
-#define bfin_write_CAN1_MB07_LENGTH(val) bfin_write16(CAN1_MB07_LENGTH, val)
-#define bfin_read_CAN1_MB07_TIMESTAMP() bfin_read16(CAN1_MB07_TIMESTAMP)
-#define bfin_write_CAN1_MB07_TIMESTAMP(val) bfin_write16(CAN1_MB07_TIMESTAMP, val)
-#define bfin_read_CAN1_MB07_ID0() bfin_read16(CAN1_MB07_ID0)
-#define bfin_write_CAN1_MB07_ID0(val) bfin_write16(CAN1_MB07_ID0, val)
-#define bfin_read_CAN1_MB07_ID1() bfin_read16(CAN1_MB07_ID1)
-#define bfin_write_CAN1_MB07_ID1(val) bfin_write16(CAN1_MB07_ID1, val)
-#define bfin_read_CAN1_MB08_DATA0() bfin_read16(CAN1_MB08_DATA0)
-#define bfin_write_CAN1_MB08_DATA0(val) bfin_write16(CAN1_MB08_DATA0, val)
-#define bfin_read_CAN1_MB08_DATA1() bfin_read16(CAN1_MB08_DATA1)
-#define bfin_write_CAN1_MB08_DATA1(val) bfin_write16(CAN1_MB08_DATA1, val)
-#define bfin_read_CAN1_MB08_DATA2() bfin_read16(CAN1_MB08_DATA2)
-#define bfin_write_CAN1_MB08_DATA2(val) bfin_write16(CAN1_MB08_DATA2, val)
-#define bfin_read_CAN1_MB08_DATA3() bfin_read16(CAN1_MB08_DATA3)
-#define bfin_write_CAN1_MB08_DATA3(val) bfin_write16(CAN1_MB08_DATA3, val)
-#define bfin_read_CAN1_MB08_LENGTH() bfin_read16(CAN1_MB08_LENGTH)
-#define bfin_write_CAN1_MB08_LENGTH(val) bfin_write16(CAN1_MB08_LENGTH, val)
-#define bfin_read_CAN1_MB08_TIMESTAMP() bfin_read16(CAN1_MB08_TIMESTAMP)
-#define bfin_write_CAN1_MB08_TIMESTAMP(val) bfin_write16(CAN1_MB08_TIMESTAMP, val)
-#define bfin_read_CAN1_MB08_ID0() bfin_read16(CAN1_MB08_ID0)
-#define bfin_write_CAN1_MB08_ID0(val) bfin_write16(CAN1_MB08_ID0, val)
-#define bfin_read_CAN1_MB08_ID1() bfin_read16(CAN1_MB08_ID1)
-#define bfin_write_CAN1_MB08_ID1(val) bfin_write16(CAN1_MB08_ID1, val)
-#define bfin_read_CAN1_MB09_DATA0() bfin_read16(CAN1_MB09_DATA0)
-#define bfin_write_CAN1_MB09_DATA0(val) bfin_write16(CAN1_MB09_DATA0, val)
-#define bfin_read_CAN1_MB09_DATA1() bfin_read16(CAN1_MB09_DATA1)
-#define bfin_write_CAN1_MB09_DATA1(val) bfin_write16(CAN1_MB09_DATA1, val)
-#define bfin_read_CAN1_MB09_DATA2() bfin_read16(CAN1_MB09_DATA2)
-#define bfin_write_CAN1_MB09_DATA2(val) bfin_write16(CAN1_MB09_DATA2, val)
-#define bfin_read_CAN1_MB09_DATA3() bfin_read16(CAN1_MB09_DATA3)
-#define bfin_write_CAN1_MB09_DATA3(val) bfin_write16(CAN1_MB09_DATA3, val)
-#define bfin_read_CAN1_MB09_LENGTH() bfin_read16(CAN1_MB09_LENGTH)
-#define bfin_write_CAN1_MB09_LENGTH(val) bfin_write16(CAN1_MB09_LENGTH, val)
-#define bfin_read_CAN1_MB09_TIMESTAMP() bfin_read16(CAN1_MB09_TIMESTAMP)
-#define bfin_write_CAN1_MB09_TIMESTAMP(val) bfin_write16(CAN1_MB09_TIMESTAMP, val)
-#define bfin_read_CAN1_MB09_ID0() bfin_read16(CAN1_MB09_ID0)
-#define bfin_write_CAN1_MB09_ID0(val) bfin_write16(CAN1_MB09_ID0, val)
-#define bfin_read_CAN1_MB09_ID1() bfin_read16(CAN1_MB09_ID1)
-#define bfin_write_CAN1_MB09_ID1(val) bfin_write16(CAN1_MB09_ID1, val)
-#define bfin_read_CAN1_MB10_DATA0() bfin_read16(CAN1_MB10_DATA0)
-#define bfin_write_CAN1_MB10_DATA0(val) bfin_write16(CAN1_MB10_DATA0, val)
-#define bfin_read_CAN1_MB10_DATA1() bfin_read16(CAN1_MB10_DATA1)
-#define bfin_write_CAN1_MB10_DATA1(val) bfin_write16(CAN1_MB10_DATA1, val)
-#define bfin_read_CAN1_MB10_DATA2() bfin_read16(CAN1_MB10_DATA2)
-#define bfin_write_CAN1_MB10_DATA2(val) bfin_write16(CAN1_MB10_DATA2, val)
-#define bfin_read_CAN1_MB10_DATA3() bfin_read16(CAN1_MB10_DATA3)
-#define bfin_write_CAN1_MB10_DATA3(val) bfin_write16(CAN1_MB10_DATA3, val)
-#define bfin_read_CAN1_MB10_LENGTH() bfin_read16(CAN1_MB10_LENGTH)
-#define bfin_write_CAN1_MB10_LENGTH(val) bfin_write16(CAN1_MB10_LENGTH, val)
-#define bfin_read_CAN1_MB10_TIMESTAMP() bfin_read16(CAN1_MB10_TIMESTAMP)
-#define bfin_write_CAN1_MB10_TIMESTAMP(val) bfin_write16(CAN1_MB10_TIMESTAMP, val)
-#define bfin_read_CAN1_MB10_ID0() bfin_read16(CAN1_MB10_ID0)
-#define bfin_write_CAN1_MB10_ID0(val) bfin_write16(CAN1_MB10_ID0, val)
-#define bfin_read_CAN1_MB10_ID1() bfin_read16(CAN1_MB10_ID1)
-#define bfin_write_CAN1_MB10_ID1(val) bfin_write16(CAN1_MB10_ID1, val)
-#define bfin_read_CAN1_MB11_DATA0() bfin_read16(CAN1_MB11_DATA0)
-#define bfin_write_CAN1_MB11_DATA0(val) bfin_write16(CAN1_MB11_DATA0, val)
-#define bfin_read_CAN1_MB11_DATA1() bfin_read16(CAN1_MB11_DATA1)
-#define bfin_write_CAN1_MB11_DATA1(val) bfin_write16(CAN1_MB11_DATA1, val)
-#define bfin_read_CAN1_MB11_DATA2() bfin_read16(CAN1_MB11_DATA2)
-#define bfin_write_CAN1_MB11_DATA2(val) bfin_write16(CAN1_MB11_DATA2, val)
-#define bfin_read_CAN1_MB11_DATA3() bfin_read16(CAN1_MB11_DATA3)
-#define bfin_write_CAN1_MB11_DATA3(val) bfin_write16(CAN1_MB11_DATA3, val)
-#define bfin_read_CAN1_MB11_LENGTH() bfin_read16(CAN1_MB11_LENGTH)
-#define bfin_write_CAN1_MB11_LENGTH(val) bfin_write16(CAN1_MB11_LENGTH, val)
-#define bfin_read_CAN1_MB11_TIMESTAMP() bfin_read16(CAN1_MB11_TIMESTAMP)
-#define bfin_write_CAN1_MB11_TIMESTAMP(val) bfin_write16(CAN1_MB11_TIMESTAMP, val)
-#define bfin_read_CAN1_MB11_ID0() bfin_read16(CAN1_MB11_ID0)
-#define bfin_write_CAN1_MB11_ID0(val) bfin_write16(CAN1_MB11_ID0, val)
-#define bfin_read_CAN1_MB11_ID1() bfin_read16(CAN1_MB11_ID1)
-#define bfin_write_CAN1_MB11_ID1(val) bfin_write16(CAN1_MB11_ID1, val)
-#define bfin_read_CAN1_MB12_DATA0() bfin_read16(CAN1_MB12_DATA0)
-#define bfin_write_CAN1_MB12_DATA0(val) bfin_write16(CAN1_MB12_DATA0, val)
-#define bfin_read_CAN1_MB12_DATA1() bfin_read16(CAN1_MB12_DATA1)
-#define bfin_write_CAN1_MB12_DATA1(val) bfin_write16(CAN1_MB12_DATA1, val)
-#define bfin_read_CAN1_MB12_DATA2() bfin_read16(CAN1_MB12_DATA2)
-#define bfin_write_CAN1_MB12_DATA2(val) bfin_write16(CAN1_MB12_DATA2, val)
-#define bfin_read_CAN1_MB12_DATA3() bfin_read16(CAN1_MB12_DATA3)
-#define bfin_write_CAN1_MB12_DATA3(val) bfin_write16(CAN1_MB12_DATA3, val)
-#define bfin_read_CAN1_MB12_LENGTH() bfin_read16(CAN1_MB12_LENGTH)
-#define bfin_write_CAN1_MB12_LENGTH(val) bfin_write16(CAN1_MB12_LENGTH, val)
-#define bfin_read_CAN1_MB12_TIMESTAMP() bfin_read16(CAN1_MB12_TIMESTAMP)
-#define bfin_write_CAN1_MB12_TIMESTAMP(val) bfin_write16(CAN1_MB12_TIMESTAMP, val)
-#define bfin_read_CAN1_MB12_ID0() bfin_read16(CAN1_MB12_ID0)
-#define bfin_write_CAN1_MB12_ID0(val) bfin_write16(CAN1_MB12_ID0, val)
-#define bfin_read_CAN1_MB12_ID1() bfin_read16(CAN1_MB12_ID1)
-#define bfin_write_CAN1_MB12_ID1(val) bfin_write16(CAN1_MB12_ID1, val)
-#define bfin_read_CAN1_MB13_DATA0() bfin_read16(CAN1_MB13_DATA0)
-#define bfin_write_CAN1_MB13_DATA0(val) bfin_write16(CAN1_MB13_DATA0, val)
-#define bfin_read_CAN1_MB13_DATA1() bfin_read16(CAN1_MB13_DATA1)
-#define bfin_write_CAN1_MB13_DATA1(val) bfin_write16(CAN1_MB13_DATA1, val)
-#define bfin_read_CAN1_MB13_DATA2() bfin_read16(CAN1_MB13_DATA2)
-#define bfin_write_CAN1_MB13_DATA2(val) bfin_write16(CAN1_MB13_DATA2, val)
-#define bfin_read_CAN1_MB13_DATA3() bfin_read16(CAN1_MB13_DATA3)
-#define bfin_write_CAN1_MB13_DATA3(val) bfin_write16(CAN1_MB13_DATA3, val)
-#define bfin_read_CAN1_MB13_LENGTH() bfin_read16(CAN1_MB13_LENGTH)
-#define bfin_write_CAN1_MB13_LENGTH(val) bfin_write16(CAN1_MB13_LENGTH, val)
-#define bfin_read_CAN1_MB13_TIMESTAMP() bfin_read16(CAN1_MB13_TIMESTAMP)
-#define bfin_write_CAN1_MB13_TIMESTAMP(val) bfin_write16(CAN1_MB13_TIMESTAMP, val)
-#define bfin_read_CAN1_MB13_ID0() bfin_read16(CAN1_MB13_ID0)
-#define bfin_write_CAN1_MB13_ID0(val) bfin_write16(CAN1_MB13_ID0, val)
-#define bfin_read_CAN1_MB13_ID1() bfin_read16(CAN1_MB13_ID1)
-#define bfin_write_CAN1_MB13_ID1(val) bfin_write16(CAN1_MB13_ID1, val)
-#define bfin_read_CAN1_MB14_DATA0() bfin_read16(CAN1_MB14_DATA0)
-#define bfin_write_CAN1_MB14_DATA0(val) bfin_write16(CAN1_MB14_DATA0, val)
-#define bfin_read_CAN1_MB14_DATA1() bfin_read16(CAN1_MB14_DATA1)
-#define bfin_write_CAN1_MB14_DATA1(val) bfin_write16(CAN1_MB14_DATA1, val)
-#define bfin_read_CAN1_MB14_DATA2() bfin_read16(CAN1_MB14_DATA2)
-#define bfin_write_CAN1_MB14_DATA2(val) bfin_write16(CAN1_MB14_DATA2, val)
-#define bfin_read_CAN1_MB14_DATA3() bfin_read16(CAN1_MB14_DATA3)
-#define bfin_write_CAN1_MB14_DATA3(val) bfin_write16(CAN1_MB14_DATA3, val)
-#define bfin_read_CAN1_MB14_LENGTH() bfin_read16(CAN1_MB14_LENGTH)
-#define bfin_write_CAN1_MB14_LENGTH(val) bfin_write16(CAN1_MB14_LENGTH, val)
-#define bfin_read_CAN1_MB14_TIMESTAMP() bfin_read16(CAN1_MB14_TIMESTAMP)
-#define bfin_write_CAN1_MB14_TIMESTAMP(val) bfin_write16(CAN1_MB14_TIMESTAMP, val)
-#define bfin_read_CAN1_MB14_ID0() bfin_read16(CAN1_MB14_ID0)
-#define bfin_write_CAN1_MB14_ID0(val) bfin_write16(CAN1_MB14_ID0, val)
-#define bfin_read_CAN1_MB14_ID1() bfin_read16(CAN1_MB14_ID1)
-#define bfin_write_CAN1_MB14_ID1(val) bfin_write16(CAN1_MB14_ID1, val)
-#define bfin_read_CAN1_MB15_DATA0() bfin_read16(CAN1_MB15_DATA0)
-#define bfin_write_CAN1_MB15_DATA0(val) bfin_write16(CAN1_MB15_DATA0, val)
-#define bfin_read_CAN1_MB15_DATA1() bfin_read16(CAN1_MB15_DATA1)
-#define bfin_write_CAN1_MB15_DATA1(val) bfin_write16(CAN1_MB15_DATA1, val)
-#define bfin_read_CAN1_MB15_DATA2() bfin_read16(CAN1_MB15_DATA2)
-#define bfin_write_CAN1_MB15_DATA2(val) bfin_write16(CAN1_MB15_DATA2, val)
-#define bfin_read_CAN1_MB15_DATA3() bfin_read16(CAN1_MB15_DATA3)
-#define bfin_write_CAN1_MB15_DATA3(val) bfin_write16(CAN1_MB15_DATA3, val)
-#define bfin_read_CAN1_MB15_LENGTH() bfin_read16(CAN1_MB15_LENGTH)
-#define bfin_write_CAN1_MB15_LENGTH(val) bfin_write16(CAN1_MB15_LENGTH, val)
-#define bfin_read_CAN1_MB15_TIMESTAMP() bfin_read16(CAN1_MB15_TIMESTAMP)
-#define bfin_write_CAN1_MB15_TIMESTAMP(val) bfin_write16(CAN1_MB15_TIMESTAMP, val)
-#define bfin_read_CAN1_MB15_ID0() bfin_read16(CAN1_MB15_ID0)
-#define bfin_write_CAN1_MB15_ID0(val) bfin_write16(CAN1_MB15_ID0, val)
-#define bfin_read_CAN1_MB15_ID1() bfin_read16(CAN1_MB15_ID1)
-#define bfin_write_CAN1_MB15_ID1(val) bfin_write16(CAN1_MB15_ID1, val)
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define bfin_read_CAN1_MB16_DATA0() bfin_read16(CAN1_MB16_DATA0)
-#define bfin_write_CAN1_MB16_DATA0(val) bfin_write16(CAN1_MB16_DATA0, val)
-#define bfin_read_CAN1_MB16_DATA1() bfin_read16(CAN1_MB16_DATA1)
-#define bfin_write_CAN1_MB16_DATA1(val) bfin_write16(CAN1_MB16_DATA1, val)
-#define bfin_read_CAN1_MB16_DATA2() bfin_read16(CAN1_MB16_DATA2)
-#define bfin_write_CAN1_MB16_DATA2(val) bfin_write16(CAN1_MB16_DATA2, val)
-#define bfin_read_CAN1_MB16_DATA3() bfin_read16(CAN1_MB16_DATA3)
-#define bfin_write_CAN1_MB16_DATA3(val) bfin_write16(CAN1_MB16_DATA3, val)
-#define bfin_read_CAN1_MB16_LENGTH() bfin_read16(CAN1_MB16_LENGTH)
-#define bfin_write_CAN1_MB16_LENGTH(val) bfin_write16(CAN1_MB16_LENGTH, val)
-#define bfin_read_CAN1_MB16_TIMESTAMP() bfin_read16(CAN1_MB16_TIMESTAMP)
-#define bfin_write_CAN1_MB16_TIMESTAMP(val) bfin_write16(CAN1_MB16_TIMESTAMP, val)
-#define bfin_read_CAN1_MB16_ID0() bfin_read16(CAN1_MB16_ID0)
-#define bfin_write_CAN1_MB16_ID0(val) bfin_write16(CAN1_MB16_ID0, val)
-#define bfin_read_CAN1_MB16_ID1() bfin_read16(CAN1_MB16_ID1)
-#define bfin_write_CAN1_MB16_ID1(val) bfin_write16(CAN1_MB16_ID1, val)
-#define bfin_read_CAN1_MB17_DATA0() bfin_read16(CAN1_MB17_DATA0)
-#define bfin_write_CAN1_MB17_DATA0(val) bfin_write16(CAN1_MB17_DATA0, val)
-#define bfin_read_CAN1_MB17_DATA1() bfin_read16(CAN1_MB17_DATA1)
-#define bfin_write_CAN1_MB17_DATA1(val) bfin_write16(CAN1_MB17_DATA1, val)
-#define bfin_read_CAN1_MB17_DATA2() bfin_read16(CAN1_MB17_DATA2)
-#define bfin_write_CAN1_MB17_DATA2(val) bfin_write16(CAN1_MB17_DATA2, val)
-#define bfin_read_CAN1_MB17_DATA3() bfin_read16(CAN1_MB17_DATA3)
-#define bfin_write_CAN1_MB17_DATA3(val) bfin_write16(CAN1_MB17_DATA3, val)
-#define bfin_read_CAN1_MB17_LENGTH() bfin_read16(CAN1_MB17_LENGTH)
-#define bfin_write_CAN1_MB17_LENGTH(val) bfin_write16(CAN1_MB17_LENGTH, val)
-#define bfin_read_CAN1_MB17_TIMESTAMP() bfin_read16(CAN1_MB17_TIMESTAMP)
-#define bfin_write_CAN1_MB17_TIMESTAMP(val) bfin_write16(CAN1_MB17_TIMESTAMP, val)
-#define bfin_read_CAN1_MB17_ID0() bfin_read16(CAN1_MB17_ID0)
-#define bfin_write_CAN1_MB17_ID0(val) bfin_write16(CAN1_MB17_ID0, val)
-#define bfin_read_CAN1_MB17_ID1() bfin_read16(CAN1_MB17_ID1)
-#define bfin_write_CAN1_MB17_ID1(val) bfin_write16(CAN1_MB17_ID1, val)
-#define bfin_read_CAN1_MB18_DATA0() bfin_read16(CAN1_MB18_DATA0)
-#define bfin_write_CAN1_MB18_DATA0(val) bfin_write16(CAN1_MB18_DATA0, val)
-#define bfin_read_CAN1_MB18_DATA1() bfin_read16(CAN1_MB18_DATA1)
-#define bfin_write_CAN1_MB18_DATA1(val) bfin_write16(CAN1_MB18_DATA1, val)
-#define bfin_read_CAN1_MB18_DATA2() bfin_read16(CAN1_MB18_DATA2)
-#define bfin_write_CAN1_MB18_DATA2(val) bfin_write16(CAN1_MB18_DATA2, val)
-#define bfin_read_CAN1_MB18_DATA3() bfin_read16(CAN1_MB18_DATA3)
-#define bfin_write_CAN1_MB18_DATA3(val) bfin_write16(CAN1_MB18_DATA3, val)
-#define bfin_read_CAN1_MB18_LENGTH() bfin_read16(CAN1_MB18_LENGTH)
-#define bfin_write_CAN1_MB18_LENGTH(val) bfin_write16(CAN1_MB18_LENGTH, val)
-#define bfin_read_CAN1_MB18_TIMESTAMP() bfin_read16(CAN1_MB18_TIMESTAMP)
-#define bfin_write_CAN1_MB18_TIMESTAMP(val) bfin_write16(CAN1_MB18_TIMESTAMP, val)
-#define bfin_read_CAN1_MB18_ID0() bfin_read16(CAN1_MB18_ID0)
-#define bfin_write_CAN1_MB18_ID0(val) bfin_write16(CAN1_MB18_ID0, val)
-#define bfin_read_CAN1_MB18_ID1() bfin_read16(CAN1_MB18_ID1)
-#define bfin_write_CAN1_MB18_ID1(val) bfin_write16(CAN1_MB18_ID1, val)
-#define bfin_read_CAN1_MB19_DATA0() bfin_read16(CAN1_MB19_DATA0)
-#define bfin_write_CAN1_MB19_DATA0(val) bfin_write16(CAN1_MB19_DATA0, val)
-#define bfin_read_CAN1_MB19_DATA1() bfin_read16(CAN1_MB19_DATA1)
-#define bfin_write_CAN1_MB19_DATA1(val) bfin_write16(CAN1_MB19_DATA1, val)
-#define bfin_read_CAN1_MB19_DATA2() bfin_read16(CAN1_MB19_DATA2)
-#define bfin_write_CAN1_MB19_DATA2(val) bfin_write16(CAN1_MB19_DATA2, val)
-#define bfin_read_CAN1_MB19_DATA3() bfin_read16(CAN1_MB19_DATA3)
-#define bfin_write_CAN1_MB19_DATA3(val) bfin_write16(CAN1_MB19_DATA3, val)
-#define bfin_read_CAN1_MB19_LENGTH() bfin_read16(CAN1_MB19_LENGTH)
-#define bfin_write_CAN1_MB19_LENGTH(val) bfin_write16(CAN1_MB19_LENGTH, val)
-#define bfin_read_CAN1_MB19_TIMESTAMP() bfin_read16(CAN1_MB19_TIMESTAMP)
-#define bfin_write_CAN1_MB19_TIMESTAMP(val) bfin_write16(CAN1_MB19_TIMESTAMP, val)
-#define bfin_read_CAN1_MB19_ID0() bfin_read16(CAN1_MB19_ID0)
-#define bfin_write_CAN1_MB19_ID0(val) bfin_write16(CAN1_MB19_ID0, val)
-#define bfin_read_CAN1_MB19_ID1() bfin_read16(CAN1_MB19_ID1)
-#define bfin_write_CAN1_MB19_ID1(val) bfin_write16(CAN1_MB19_ID1, val)
-#define bfin_read_CAN1_MB20_DATA0() bfin_read16(CAN1_MB20_DATA0)
-#define bfin_write_CAN1_MB20_DATA0(val) bfin_write16(CAN1_MB20_DATA0, val)
-#define bfin_read_CAN1_MB20_DATA1() bfin_read16(CAN1_MB20_DATA1)
-#define bfin_write_CAN1_MB20_DATA1(val) bfin_write16(CAN1_MB20_DATA1, val)
-#define bfin_read_CAN1_MB20_DATA2() bfin_read16(CAN1_MB20_DATA2)
-#define bfin_write_CAN1_MB20_DATA2(val) bfin_write16(CAN1_MB20_DATA2, val)
-#define bfin_read_CAN1_MB20_DATA3() bfin_read16(CAN1_MB20_DATA3)
-#define bfin_write_CAN1_MB20_DATA3(val) bfin_write16(CAN1_MB20_DATA3, val)
-#define bfin_read_CAN1_MB20_LENGTH() bfin_read16(CAN1_MB20_LENGTH)
-#define bfin_write_CAN1_MB20_LENGTH(val) bfin_write16(CAN1_MB20_LENGTH, val)
-#define bfin_read_CAN1_MB20_TIMESTAMP() bfin_read16(CAN1_MB20_TIMESTAMP)
-#define bfin_write_CAN1_MB20_TIMESTAMP(val) bfin_write16(CAN1_MB20_TIMESTAMP, val)
-#define bfin_read_CAN1_MB20_ID0() bfin_read16(CAN1_MB20_ID0)
-#define bfin_write_CAN1_MB20_ID0(val) bfin_write16(CAN1_MB20_ID0, val)
-#define bfin_read_CAN1_MB20_ID1() bfin_read16(CAN1_MB20_ID1)
-#define bfin_write_CAN1_MB20_ID1(val) bfin_write16(CAN1_MB20_ID1, val)
-#define bfin_read_CAN1_MB21_DATA0() bfin_read16(CAN1_MB21_DATA0)
-#define bfin_write_CAN1_MB21_DATA0(val) bfin_write16(CAN1_MB21_DATA0, val)
-#define bfin_read_CAN1_MB21_DATA1() bfin_read16(CAN1_MB21_DATA1)
-#define bfin_write_CAN1_MB21_DATA1(val) bfin_write16(CAN1_MB21_DATA1, val)
-#define bfin_read_CAN1_MB21_DATA2() bfin_read16(CAN1_MB21_DATA2)
-#define bfin_write_CAN1_MB21_DATA2(val) bfin_write16(CAN1_MB21_DATA2, val)
-#define bfin_read_CAN1_MB21_DATA3() bfin_read16(CAN1_MB21_DATA3)
-#define bfin_write_CAN1_MB21_DATA3(val) bfin_write16(CAN1_MB21_DATA3, val)
-#define bfin_read_CAN1_MB21_LENGTH() bfin_read16(CAN1_MB21_LENGTH)
-#define bfin_write_CAN1_MB21_LENGTH(val) bfin_write16(CAN1_MB21_LENGTH, val)
-#define bfin_read_CAN1_MB21_TIMESTAMP() bfin_read16(CAN1_MB21_TIMESTAMP)
-#define bfin_write_CAN1_MB21_TIMESTAMP(val) bfin_write16(CAN1_MB21_TIMESTAMP, val)
-#define bfin_read_CAN1_MB21_ID0() bfin_read16(CAN1_MB21_ID0)
-#define bfin_write_CAN1_MB21_ID0(val) bfin_write16(CAN1_MB21_ID0, val)
-#define bfin_read_CAN1_MB21_ID1() bfin_read16(CAN1_MB21_ID1)
-#define bfin_write_CAN1_MB21_ID1(val) bfin_write16(CAN1_MB21_ID1, val)
-#define bfin_read_CAN1_MB22_DATA0() bfin_read16(CAN1_MB22_DATA0)
-#define bfin_write_CAN1_MB22_DATA0(val) bfin_write16(CAN1_MB22_DATA0, val)
-#define bfin_read_CAN1_MB22_DATA1() bfin_read16(CAN1_MB22_DATA1)
-#define bfin_write_CAN1_MB22_DATA1(val) bfin_write16(CAN1_MB22_DATA1, val)
-#define bfin_read_CAN1_MB22_DATA2() bfin_read16(CAN1_MB22_DATA2)
-#define bfin_write_CAN1_MB22_DATA2(val) bfin_write16(CAN1_MB22_DATA2, val)
-#define bfin_read_CAN1_MB22_DATA3() bfin_read16(CAN1_MB22_DATA3)
-#define bfin_write_CAN1_MB22_DATA3(val) bfin_write16(CAN1_MB22_DATA3, val)
-#define bfin_read_CAN1_MB22_LENGTH() bfin_read16(CAN1_MB22_LENGTH)
-#define bfin_write_CAN1_MB22_LENGTH(val) bfin_write16(CAN1_MB22_LENGTH, val)
-#define bfin_read_CAN1_MB22_TIMESTAMP() bfin_read16(CAN1_MB22_TIMESTAMP)
-#define bfin_write_CAN1_MB22_TIMESTAMP(val) bfin_write16(CAN1_MB22_TIMESTAMP, val)
-#define bfin_read_CAN1_MB22_ID0() bfin_read16(CAN1_MB22_ID0)
-#define bfin_write_CAN1_MB22_ID0(val) bfin_write16(CAN1_MB22_ID0, val)
-#define bfin_read_CAN1_MB22_ID1() bfin_read16(CAN1_MB22_ID1)
-#define bfin_write_CAN1_MB22_ID1(val) bfin_write16(CAN1_MB22_ID1, val)
-#define bfin_read_CAN1_MB23_DATA0() bfin_read16(CAN1_MB23_DATA0)
-#define bfin_write_CAN1_MB23_DATA0(val) bfin_write16(CAN1_MB23_DATA0, val)
-#define bfin_read_CAN1_MB23_DATA1() bfin_read16(CAN1_MB23_DATA1)
-#define bfin_write_CAN1_MB23_DATA1(val) bfin_write16(CAN1_MB23_DATA1, val)
-#define bfin_read_CAN1_MB23_DATA2() bfin_read16(CAN1_MB23_DATA2)
-#define bfin_write_CAN1_MB23_DATA2(val) bfin_write16(CAN1_MB23_DATA2, val)
-#define bfin_read_CAN1_MB23_DATA3() bfin_read16(CAN1_MB23_DATA3)
-#define bfin_write_CAN1_MB23_DATA3(val) bfin_write16(CAN1_MB23_DATA3, val)
-#define bfin_read_CAN1_MB23_LENGTH() bfin_read16(CAN1_MB23_LENGTH)
-#define bfin_write_CAN1_MB23_LENGTH(val) bfin_write16(CAN1_MB23_LENGTH, val)
-#define bfin_read_CAN1_MB23_TIMESTAMP() bfin_read16(CAN1_MB23_TIMESTAMP)
-#define bfin_write_CAN1_MB23_TIMESTAMP(val) bfin_write16(CAN1_MB23_TIMESTAMP, val)
-#define bfin_read_CAN1_MB23_ID0() bfin_read16(CAN1_MB23_ID0)
-#define bfin_write_CAN1_MB23_ID0(val) bfin_write16(CAN1_MB23_ID0, val)
-#define bfin_read_CAN1_MB23_ID1() bfin_read16(CAN1_MB23_ID1)
-#define bfin_write_CAN1_MB23_ID1(val) bfin_write16(CAN1_MB23_ID1, val)
-#define bfin_read_CAN1_MB24_DATA0() bfin_read16(CAN1_MB24_DATA0)
-#define bfin_write_CAN1_MB24_DATA0(val) bfin_write16(CAN1_MB24_DATA0, val)
-#define bfin_read_CAN1_MB24_DATA1() bfin_read16(CAN1_MB24_DATA1)
-#define bfin_write_CAN1_MB24_DATA1(val) bfin_write16(CAN1_MB24_DATA1, val)
-#define bfin_read_CAN1_MB24_DATA2() bfin_read16(CAN1_MB24_DATA2)
-#define bfin_write_CAN1_MB24_DATA2(val) bfin_write16(CAN1_MB24_DATA2, val)
-#define bfin_read_CAN1_MB24_DATA3() bfin_read16(CAN1_MB24_DATA3)
-#define bfin_write_CAN1_MB24_DATA3(val) bfin_write16(CAN1_MB24_DATA3, val)
-#define bfin_read_CAN1_MB24_LENGTH() bfin_read16(CAN1_MB24_LENGTH)
-#define bfin_write_CAN1_MB24_LENGTH(val) bfin_write16(CAN1_MB24_LENGTH, val)
-#define bfin_read_CAN1_MB24_TIMESTAMP() bfin_read16(CAN1_MB24_TIMESTAMP)
-#define bfin_write_CAN1_MB24_TIMESTAMP(val) bfin_write16(CAN1_MB24_TIMESTAMP, val)
-#define bfin_read_CAN1_MB24_ID0() bfin_read16(CAN1_MB24_ID0)
-#define bfin_write_CAN1_MB24_ID0(val) bfin_write16(CAN1_MB24_ID0, val)
-#define bfin_read_CAN1_MB24_ID1() bfin_read16(CAN1_MB24_ID1)
-#define bfin_write_CAN1_MB24_ID1(val) bfin_write16(CAN1_MB24_ID1, val)
-#define bfin_read_CAN1_MB25_DATA0() bfin_read16(CAN1_MB25_DATA0)
-#define bfin_write_CAN1_MB25_DATA0(val) bfin_write16(CAN1_MB25_DATA0, val)
-#define bfin_read_CAN1_MB25_DATA1() bfin_read16(CAN1_MB25_DATA1)
-#define bfin_write_CAN1_MB25_DATA1(val) bfin_write16(CAN1_MB25_DATA1, val)
-#define bfin_read_CAN1_MB25_DATA2() bfin_read16(CAN1_MB25_DATA2)
-#define bfin_write_CAN1_MB25_DATA2(val) bfin_write16(CAN1_MB25_DATA2, val)
-#define bfin_read_CAN1_MB25_DATA3() bfin_read16(CAN1_MB25_DATA3)
-#define bfin_write_CAN1_MB25_DATA3(val) bfin_write16(CAN1_MB25_DATA3, val)
-#define bfin_read_CAN1_MB25_LENGTH() bfin_read16(CAN1_MB25_LENGTH)
-#define bfin_write_CAN1_MB25_LENGTH(val) bfin_write16(CAN1_MB25_LENGTH, val)
-#define bfin_read_CAN1_MB25_TIMESTAMP() bfin_read16(CAN1_MB25_TIMESTAMP)
-#define bfin_write_CAN1_MB25_TIMESTAMP(val) bfin_write16(CAN1_MB25_TIMESTAMP, val)
-#define bfin_read_CAN1_MB25_ID0() bfin_read16(CAN1_MB25_ID0)
-#define bfin_write_CAN1_MB25_ID0(val) bfin_write16(CAN1_MB25_ID0, val)
-#define bfin_read_CAN1_MB25_ID1() bfin_read16(CAN1_MB25_ID1)
-#define bfin_write_CAN1_MB25_ID1(val) bfin_write16(CAN1_MB25_ID1, val)
-#define bfin_read_CAN1_MB26_DATA0() bfin_read16(CAN1_MB26_DATA0)
-#define bfin_write_CAN1_MB26_DATA0(val) bfin_write16(CAN1_MB26_DATA0, val)
-#define bfin_read_CAN1_MB26_DATA1() bfin_read16(CAN1_MB26_DATA1)
-#define bfin_write_CAN1_MB26_DATA1(val) bfin_write16(CAN1_MB26_DATA1, val)
-#define bfin_read_CAN1_MB26_DATA2() bfin_read16(CAN1_MB26_DATA2)
-#define bfin_write_CAN1_MB26_DATA2(val) bfin_write16(CAN1_MB26_DATA2, val)
-#define bfin_read_CAN1_MB26_DATA3() bfin_read16(CAN1_MB26_DATA3)
-#define bfin_write_CAN1_MB26_DATA3(val) bfin_write16(CAN1_MB26_DATA3, val)
-#define bfin_read_CAN1_MB26_LENGTH() bfin_read16(CAN1_MB26_LENGTH)
-#define bfin_write_CAN1_MB26_LENGTH(val) bfin_write16(CAN1_MB26_LENGTH, val)
-#define bfin_read_CAN1_MB26_TIMESTAMP() bfin_read16(CAN1_MB26_TIMESTAMP)
-#define bfin_write_CAN1_MB26_TIMESTAMP(val) bfin_write16(CAN1_MB26_TIMESTAMP, val)
-#define bfin_read_CAN1_MB26_ID0() bfin_read16(CAN1_MB26_ID0)
-#define bfin_write_CAN1_MB26_ID0(val) bfin_write16(CAN1_MB26_ID0, val)
-#define bfin_read_CAN1_MB26_ID1() bfin_read16(CAN1_MB26_ID1)
-#define bfin_write_CAN1_MB26_ID1(val) bfin_write16(CAN1_MB26_ID1, val)
-#define bfin_read_CAN1_MB27_DATA0() bfin_read16(CAN1_MB27_DATA0)
-#define bfin_write_CAN1_MB27_DATA0(val) bfin_write16(CAN1_MB27_DATA0, val)
-#define bfin_read_CAN1_MB27_DATA1() bfin_read16(CAN1_MB27_DATA1)
-#define bfin_write_CAN1_MB27_DATA1(val) bfin_write16(CAN1_MB27_DATA1, val)
-#define bfin_read_CAN1_MB27_DATA2() bfin_read16(CAN1_MB27_DATA2)
-#define bfin_write_CAN1_MB27_DATA2(val) bfin_write16(CAN1_MB27_DATA2, val)
-#define bfin_read_CAN1_MB27_DATA3() bfin_read16(CAN1_MB27_DATA3)
-#define bfin_write_CAN1_MB27_DATA3(val) bfin_write16(CAN1_MB27_DATA3, val)
-#define bfin_read_CAN1_MB27_LENGTH() bfin_read16(CAN1_MB27_LENGTH)
-#define bfin_write_CAN1_MB27_LENGTH(val) bfin_write16(CAN1_MB27_LENGTH, val)
-#define bfin_read_CAN1_MB27_TIMESTAMP() bfin_read16(CAN1_MB27_TIMESTAMP)
-#define bfin_write_CAN1_MB27_TIMESTAMP(val) bfin_write16(CAN1_MB27_TIMESTAMP, val)
-#define bfin_read_CAN1_MB27_ID0() bfin_read16(CAN1_MB27_ID0)
-#define bfin_write_CAN1_MB27_ID0(val) bfin_write16(CAN1_MB27_ID0, val)
-#define bfin_read_CAN1_MB27_ID1() bfin_read16(CAN1_MB27_ID1)
-#define bfin_write_CAN1_MB27_ID1(val) bfin_write16(CAN1_MB27_ID1, val)
-#define bfin_read_CAN1_MB28_DATA0() bfin_read16(CAN1_MB28_DATA0)
-#define bfin_write_CAN1_MB28_DATA0(val) bfin_write16(CAN1_MB28_DATA0, val)
-#define bfin_read_CAN1_MB28_DATA1() bfin_read16(CAN1_MB28_DATA1)
-#define bfin_write_CAN1_MB28_DATA1(val) bfin_write16(CAN1_MB28_DATA1, val)
-#define bfin_read_CAN1_MB28_DATA2() bfin_read16(CAN1_MB28_DATA2)
-#define bfin_write_CAN1_MB28_DATA2(val) bfin_write16(CAN1_MB28_DATA2, val)
-#define bfin_read_CAN1_MB28_DATA3() bfin_read16(CAN1_MB28_DATA3)
-#define bfin_write_CAN1_MB28_DATA3(val) bfin_write16(CAN1_MB28_DATA3, val)
-#define bfin_read_CAN1_MB28_LENGTH() bfin_read16(CAN1_MB28_LENGTH)
-#define bfin_write_CAN1_MB28_LENGTH(val) bfin_write16(CAN1_MB28_LENGTH, val)
-#define bfin_read_CAN1_MB28_TIMESTAMP() bfin_read16(CAN1_MB28_TIMESTAMP)
-#define bfin_write_CAN1_MB28_TIMESTAMP(val) bfin_write16(CAN1_MB28_TIMESTAMP, val)
-#define bfin_read_CAN1_MB28_ID0() bfin_read16(CAN1_MB28_ID0)
-#define bfin_write_CAN1_MB28_ID0(val) bfin_write16(CAN1_MB28_ID0, val)
-#define bfin_read_CAN1_MB28_ID1() bfin_read16(CAN1_MB28_ID1)
-#define bfin_write_CAN1_MB28_ID1(val) bfin_write16(CAN1_MB28_ID1, val)
-#define bfin_read_CAN1_MB29_DATA0() bfin_read16(CAN1_MB29_DATA0)
-#define bfin_write_CAN1_MB29_DATA0(val) bfin_write16(CAN1_MB29_DATA0, val)
-#define bfin_read_CAN1_MB29_DATA1() bfin_read16(CAN1_MB29_DATA1)
-#define bfin_write_CAN1_MB29_DATA1(val) bfin_write16(CAN1_MB29_DATA1, val)
-#define bfin_read_CAN1_MB29_DATA2() bfin_read16(CAN1_MB29_DATA2)
-#define bfin_write_CAN1_MB29_DATA2(val) bfin_write16(CAN1_MB29_DATA2, val)
-#define bfin_read_CAN1_MB29_DATA3() bfin_read16(CAN1_MB29_DATA3)
-#define bfin_write_CAN1_MB29_DATA3(val) bfin_write16(CAN1_MB29_DATA3, val)
-#define bfin_read_CAN1_MB29_LENGTH() bfin_read16(CAN1_MB29_LENGTH)
-#define bfin_write_CAN1_MB29_LENGTH(val) bfin_write16(CAN1_MB29_LENGTH, val)
-#define bfin_read_CAN1_MB29_TIMESTAMP() bfin_read16(CAN1_MB29_TIMESTAMP)
-#define bfin_write_CAN1_MB29_TIMESTAMP(val) bfin_write16(CAN1_MB29_TIMESTAMP, val)
-#define bfin_read_CAN1_MB29_ID0() bfin_read16(CAN1_MB29_ID0)
-#define bfin_write_CAN1_MB29_ID0(val) bfin_write16(CAN1_MB29_ID0, val)
-#define bfin_read_CAN1_MB29_ID1() bfin_read16(CAN1_MB29_ID1)
-#define bfin_write_CAN1_MB29_ID1(val) bfin_write16(CAN1_MB29_ID1, val)
-#define bfin_read_CAN1_MB30_DATA0() bfin_read16(CAN1_MB30_DATA0)
-#define bfin_write_CAN1_MB30_DATA0(val) bfin_write16(CAN1_MB30_DATA0, val)
-#define bfin_read_CAN1_MB30_DATA1() bfin_read16(CAN1_MB30_DATA1)
-#define bfin_write_CAN1_MB30_DATA1(val) bfin_write16(CAN1_MB30_DATA1, val)
-#define bfin_read_CAN1_MB30_DATA2() bfin_read16(CAN1_MB30_DATA2)
-#define bfin_write_CAN1_MB30_DATA2(val) bfin_write16(CAN1_MB30_DATA2, val)
-#define bfin_read_CAN1_MB30_DATA3() bfin_read16(CAN1_MB30_DATA3)
-#define bfin_write_CAN1_MB30_DATA3(val) bfin_write16(CAN1_MB30_DATA3, val)
-#define bfin_read_CAN1_MB30_LENGTH() bfin_read16(CAN1_MB30_LENGTH)
-#define bfin_write_CAN1_MB30_LENGTH(val) bfin_write16(CAN1_MB30_LENGTH, val)
-#define bfin_read_CAN1_MB30_TIMESTAMP() bfin_read16(CAN1_MB30_TIMESTAMP)
-#define bfin_write_CAN1_MB30_TIMESTAMP(val) bfin_write16(CAN1_MB30_TIMESTAMP, val)
-#define bfin_read_CAN1_MB30_ID0() bfin_read16(CAN1_MB30_ID0)
-#define bfin_write_CAN1_MB30_ID0(val) bfin_write16(CAN1_MB30_ID0, val)
-#define bfin_read_CAN1_MB30_ID1() bfin_read16(CAN1_MB30_ID1)
-#define bfin_write_CAN1_MB30_ID1(val) bfin_write16(CAN1_MB30_ID1, val)
-#define bfin_read_CAN1_MB31_DATA0() bfin_read16(CAN1_MB31_DATA0)
-#define bfin_write_CAN1_MB31_DATA0(val) bfin_write16(CAN1_MB31_DATA0, val)
-#define bfin_read_CAN1_MB31_DATA1() bfin_read16(CAN1_MB31_DATA1)
-#define bfin_write_CAN1_MB31_DATA1(val) bfin_write16(CAN1_MB31_DATA1, val)
-#define bfin_read_CAN1_MB31_DATA2() bfin_read16(CAN1_MB31_DATA2)
-#define bfin_write_CAN1_MB31_DATA2(val) bfin_write16(CAN1_MB31_DATA2, val)
-#define bfin_read_CAN1_MB31_DATA3() bfin_read16(CAN1_MB31_DATA3)
-#define bfin_write_CAN1_MB31_DATA3(val) bfin_write16(CAN1_MB31_DATA3, val)
-#define bfin_read_CAN1_MB31_LENGTH() bfin_read16(CAN1_MB31_LENGTH)
-#define bfin_write_CAN1_MB31_LENGTH(val) bfin_write16(CAN1_MB31_LENGTH, val)
-#define bfin_read_CAN1_MB31_TIMESTAMP() bfin_read16(CAN1_MB31_TIMESTAMP)
-#define bfin_write_CAN1_MB31_TIMESTAMP(val) bfin_write16(CAN1_MB31_TIMESTAMP, val)
-#define bfin_read_CAN1_MB31_ID0() bfin_read16(CAN1_MB31_ID0)
-#define bfin_write_CAN1_MB31_ID0(val) bfin_write16(CAN1_MB31_ID0, val)
-#define bfin_read_CAN1_MB31_ID1() bfin_read16(CAN1_MB31_ID1)
-#define bfin_write_CAN1_MB31_ID1(val) bfin_write16(CAN1_MB31_ID1, val)
-
-#endif /* _CDEF_BF548_H */
+++ /dev/null
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CDEF_BF549_H
-#define _CDEF_BF549_H
-
-/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
-#include "cdefBF54x_base.h"
-
-/* The BF549 is like the BF544, but has MXVR */
-#include "cdefBF547.h"
-
-/* MXVR Registers */
-
-#define bfin_read_MXVR_CONFIG() bfin_read16(MXVR_CONFIG)
-#define bfin_write_MXVR_CONFIG(val) bfin_write16(MXVR_CONFIG, val)
-#define bfin_read_MXVR_STATE_0() bfin_read32(MXVR_STATE_0)
-#define bfin_write_MXVR_STATE_0(val) bfin_write32(MXVR_STATE_0, val)
-#define bfin_read_MXVR_STATE_1() bfin_read32(MXVR_STATE_1)
-#define bfin_write_MXVR_STATE_1(val) bfin_write32(MXVR_STATE_1, val)
-#define bfin_read_MXVR_INT_STAT_0() bfin_read32(MXVR_INT_STAT_0)
-#define bfin_write_MXVR_INT_STAT_0(val) bfin_write32(MXVR_INT_STAT_0, val)
-#define bfin_read_MXVR_INT_STAT_1() bfin_read32(MXVR_INT_STAT_1)
-#define bfin_write_MXVR_INT_STAT_1(val) bfin_write32(MXVR_INT_STAT_1, val)
-#define bfin_read_MXVR_INT_EN_0() bfin_read32(MXVR_INT_EN_0)
-#define bfin_write_MXVR_INT_EN_0(val) bfin_write32(MXVR_INT_EN_0, val)
-#define bfin_read_MXVR_INT_EN_1() bfin_read32(MXVR_INT_EN_1)
-#define bfin_write_MXVR_INT_EN_1(val) bfin_write32(MXVR_INT_EN_1, val)
-#define bfin_read_MXVR_POSITION() bfin_read16(MXVR_POSITION)
-#define bfin_write_MXVR_POSITION(val) bfin_write16(MXVR_POSITION, val)
-#define bfin_read_MXVR_MAX_POSITION() bfin_read16(MXVR_MAX_POSITION)
-#define bfin_write_MXVR_MAX_POSITION(val) bfin_write16(MXVR_MAX_POSITION, val)
-#define bfin_read_MXVR_DELAY() bfin_read16(MXVR_DELAY)
-#define bfin_write_MXVR_DELAY(val) bfin_write16(MXVR_DELAY, val)
-#define bfin_read_MXVR_MAX_DELAY() bfin_read16(MXVR_MAX_DELAY)
-#define bfin_write_MXVR_MAX_DELAY(val) bfin_write16(MXVR_MAX_DELAY, val)
-#define bfin_read_MXVR_LADDR() bfin_read32(MXVR_LADDR)
-#define bfin_write_MXVR_LADDR(val) bfin_write32(MXVR_LADDR, val)
-#define bfin_read_MXVR_GADDR() bfin_read16(MXVR_GADDR)
-#define bfin_write_MXVR_GADDR(val) bfin_write16(MXVR_GADDR, val)
-#define bfin_read_MXVR_AADDR() bfin_read32(MXVR_AADDR)
-#define bfin_write_MXVR_AADDR(val) bfin_write32(MXVR_AADDR, val)
-
-/* MXVR Allocation Table Registers */
-
-#define bfin_read_MXVR_ALLOC_0() bfin_read32(MXVR_ALLOC_0)
-#define bfin_write_MXVR_ALLOC_0(val) bfin_write32(MXVR_ALLOC_0, val)
-#define bfin_read_MXVR_ALLOC_1() bfin_read32(MXVR_ALLOC_1)
-#define bfin_write_MXVR_ALLOC_1(val) bfin_write32(MXVR_ALLOC_1, val)
-#define bfin_read_MXVR_ALLOC_2() bfin_read32(MXVR_ALLOC_2)
-#define bfin_write_MXVR_ALLOC_2(val) bfin_write32(MXVR_ALLOC_2, val)
-#define bfin_read_MXVR_ALLOC_3() bfin_read32(MXVR_ALLOC_3)
-#define bfin_write_MXVR_ALLOC_3(val) bfin_write32(MXVR_ALLOC_3, val)
-#define bfin_read_MXVR_ALLOC_4() bfin_read32(MXVR_ALLOC_4)
-#define bfin_write_MXVR_ALLOC_4(val) bfin_write32(MXVR_ALLOC_4, val)
-#define bfin_read_MXVR_ALLOC_5() bfin_read32(MXVR_ALLOC_5)
-#define bfin_write_MXVR_ALLOC_5(val) bfin_write32(MXVR_ALLOC_5, val)
-#define bfin_read_MXVR_ALLOC_6() bfin_read32(MXVR_ALLOC_6)
-#define bfin_write_MXVR_ALLOC_6(val) bfin_write32(MXVR_ALLOC_6, val)
-#define bfin_read_MXVR_ALLOC_7() bfin_read32(MXVR_ALLOC_7)
-#define bfin_write_MXVR_ALLOC_7(val) bfin_write32(MXVR_ALLOC_7, val)
-#define bfin_read_MXVR_ALLOC_8() bfin_read32(MXVR_ALLOC_8)
-#define bfin_write_MXVR_ALLOC_8(val) bfin_write32(MXVR_ALLOC_8, val)
-#define bfin_read_MXVR_ALLOC_9() bfin_read32(MXVR_ALLOC_9)
-#define bfin_write_MXVR_ALLOC_9(val) bfin_write32(MXVR_ALLOC_9, val)
-#define bfin_read_MXVR_ALLOC_10() bfin_read32(MXVR_ALLOC_10)
-#define bfin_write_MXVR_ALLOC_10(val) bfin_write32(MXVR_ALLOC_10, val)
-#define bfin_read_MXVR_ALLOC_11() bfin_read32(MXVR_ALLOC_11)
-#define bfin_write_MXVR_ALLOC_11(val) bfin_write32(MXVR_ALLOC_11, val)
-#define bfin_read_MXVR_ALLOC_12() bfin_read32(MXVR_ALLOC_12)
-#define bfin_write_MXVR_ALLOC_12(val) bfin_write32(MXVR_ALLOC_12, val)
-#define bfin_read_MXVR_ALLOC_13() bfin_read32(MXVR_ALLOC_13)
-#define bfin_write_MXVR_ALLOC_13(val) bfin_write32(MXVR_ALLOC_13, val)
-#define bfin_read_MXVR_ALLOC_14() bfin_read32(MXVR_ALLOC_14)
-#define bfin_write_MXVR_ALLOC_14(val) bfin_write32(MXVR_ALLOC_14, val)
-
-/* MXVR Channel Assign Registers */
-
-#define bfin_read_MXVR_SYNC_LCHAN_0() bfin_read32(MXVR_SYNC_LCHAN_0)
-#define bfin_write_MXVR_SYNC_LCHAN_0(val) bfin_write32(MXVR_SYNC_LCHAN_0, val)
-#define bfin_read_MXVR_SYNC_LCHAN_1() bfin_read32(MXVR_SYNC_LCHAN_1)
-#define bfin_write_MXVR_SYNC_LCHAN_1(val) bfin_write32(MXVR_SYNC_LCHAN_1, val)
-#define bfin_read_MXVR_SYNC_LCHAN_2() bfin_read32(MXVR_SYNC_LCHAN_2)
-#define bfin_write_MXVR_SYNC_LCHAN_2(val) bfin_write32(MXVR_SYNC_LCHAN_2, val)
-#define bfin_read_MXVR_SYNC_LCHAN_3() bfin_read32(MXVR_SYNC_LCHAN_3)
-#define bfin_write_MXVR_SYNC_LCHAN_3(val) bfin_write32(MXVR_SYNC_LCHAN_3, val)
-#define bfin_read_MXVR_SYNC_LCHAN_4() bfin_read32(MXVR_SYNC_LCHAN_4)
-#define bfin_write_MXVR_SYNC_LCHAN_4(val) bfin_write32(MXVR_SYNC_LCHAN_4, val)
-#define bfin_read_MXVR_SYNC_LCHAN_5() bfin_read32(MXVR_SYNC_LCHAN_5)
-#define bfin_write_MXVR_SYNC_LCHAN_5(val) bfin_write32(MXVR_SYNC_LCHAN_5, val)
-#define bfin_read_MXVR_SYNC_LCHAN_6() bfin_read32(MXVR_SYNC_LCHAN_6)
-#define bfin_write_MXVR_SYNC_LCHAN_6(val) bfin_write32(MXVR_SYNC_LCHAN_6, val)
-#define bfin_read_MXVR_SYNC_LCHAN_7() bfin_read32(MXVR_SYNC_LCHAN_7)
-#define bfin_write_MXVR_SYNC_LCHAN_7(val) bfin_write32(MXVR_SYNC_LCHAN_7, val)
-
-/* MXVR DMA0 Registers */
-
-#define bfin_read_MXVR_DMA0_CONFIG() bfin_read32(MXVR_DMA0_CONFIG)
-#define bfin_write_MXVR_DMA0_CONFIG(val) bfin_write32(MXVR_DMA0_CONFIG, val)
-#define bfin_read_MXVR_DMA0_START_ADDR() bfin_read32(MXVR_DMA0_START_ADDR)
-#define bfin_write_MXVR_DMA0_START_ADDR(val) bfin_write32(MXVR_DMA0_START_ADDR)
-#define bfin_read_MXVR_DMA0_COUNT() bfin_read16(MXVR_DMA0_COUNT)
-#define bfin_write_MXVR_DMA0_COUNT(val) bfin_write16(MXVR_DMA0_COUNT, val)
-#define bfin_read_MXVR_DMA0_CURR_ADDR() bfin_read32(MXVR_DMA0_CURR_ADDR)
-#define bfin_write_MXVR_DMA0_CURR_ADDR(val) bfin_write32(MXVR_DMA0_CURR_ADDR)
-#define bfin_read_MXVR_DMA0_CURR_COUNT() bfin_read16(MXVR_DMA0_CURR_COUNT)
-#define bfin_write_MXVR_DMA0_CURR_COUNT(val) bfin_write16(MXVR_DMA0_CURR_COUNT, val)
-
-/* MXVR DMA1 Registers */
-
-#define bfin_read_MXVR_DMA1_CONFIG() bfin_read32(MXVR_DMA1_CONFIG)
-#define bfin_write_MXVR_DMA1_CONFIG(val) bfin_write32(MXVR_DMA1_CONFIG, val)
-#define bfin_read_MXVR_DMA1_START_ADDR() bfin_read32(MXVR_DMA1_START_ADDR)
-#define bfin_write_MXVR_DMA1_START_ADDR(val) bfin_write32(MXVR_DMA1_START_ADDR)
-#define bfin_read_MXVR_DMA1_COUNT() bfin_read16(MXVR_DMA1_COUNT)
-#define bfin_write_MXVR_DMA1_COUNT(val) bfin_write16(MXVR_DMA1_COUNT, val)
-#define bfin_read_MXVR_DMA1_CURR_ADDR() bfin_read32(MXVR_DMA1_CURR_ADDR)
-#define bfin_write_MXVR_DMA1_CURR_ADDR(val) bfin_write32(MXVR_DMA1_CURR_ADDR)
-#define bfin_read_MXVR_DMA1_CURR_COUNT() bfin_read16(MXVR_DMA1_CURR_COUNT)
-#define bfin_write_MXVR_DMA1_CURR_COUNT(val) bfin_write16(MXVR_DMA1_CURR_COUNT, val)
-
-/* MXVR DMA2 Registers */
-
-#define bfin_read_MXVR_DMA2_CONFIG() bfin_read32(MXVR_DMA2_CONFIG)
-#define bfin_write_MXVR_DMA2_CONFIG(val) bfin_write32(MXVR_DMA2_CONFIG, val)
-#define bfin_read_MXVR_DMA2_START_ADDR() bfin_read32(MXVR_DMA2_START_ADDR)
-#define bfin_write_MXVR_DMA2_START_ADDR(val) bfin_write32(MXVR_DMA2_START_ADDR)
-#define bfin_read_MXVR_DMA2_COUNT() bfin_read16(MXVR_DMA2_COUNT)
-#define bfin_write_MXVR_DMA2_COUNT(val) bfin_write16(MXVR_DMA2_COUNT, val)
-#define bfin_read_MXVR_DMA2_CURR_ADDR() bfin_read32(MXVR_DMA2_CURR_ADDR)
-#define bfin_write_MXVR_DMA2_CURR_ADDR(val) bfin_write32(MXVR_DMA2_CURR_ADDR)
-#define bfin_read_MXVR_DMA2_CURR_COUNT() bfin_read16(MXVR_DMA2_CURR_COUNT)
-#define bfin_write_MXVR_DMA2_CURR_COUNT(val) bfin_write16(MXVR_DMA2_CURR_COUNT, val)
-
-/* MXVR DMA3 Registers */
-
-#define bfin_read_MXVR_DMA3_CONFIG() bfin_read32(MXVR_DMA3_CONFIG)
-#define bfin_write_MXVR_DMA3_CONFIG(val) bfin_write32(MXVR_DMA3_CONFIG, val)
-#define bfin_read_MXVR_DMA3_START_ADDR() bfin_read32(MXVR_DMA3_START_ADDR)
-#define bfin_write_MXVR_DMA3_START_ADDR(val) bfin_write32(MXVR_DMA3_START_ADDR)
-#define bfin_read_MXVR_DMA3_COUNT() bfin_read16(MXVR_DMA3_COUNT)
-#define bfin_write_MXVR_DMA3_COUNT(val) bfin_write16(MXVR_DMA3_COUNT, val)
-#define bfin_read_MXVR_DMA3_CURR_ADDR() bfin_read32(MXVR_DMA3_CURR_ADDR)
-#define bfin_write_MXVR_DMA3_CURR_ADDR(val) bfin_write32(MXVR_DMA3_CURR_ADDR)
-#define bfin_read_MXVR_DMA3_CURR_COUNT() bfin_read16(MXVR_DMA3_CURR_COUNT)
-#define bfin_write_MXVR_DMA3_CURR_COUNT(val) bfin_write16(MXVR_DMA3_CURR_COUNT, val)
-
-/* MXVR DMA4 Registers */
-
-#define bfin_read_MXVR_DMA4_CONFIG() bfin_read32(MXVR_DMA4_CONFIG)
-#define bfin_write_MXVR_DMA4_CONFIG(val) bfin_write32(MXVR_DMA4_CONFIG, val)
-#define bfin_read_MXVR_DMA4_START_ADDR() bfin_read32(MXVR_DMA4_START_ADDR)
-#define bfin_write_MXVR_DMA4_START_ADDR(val) bfin_write32(MXVR_DMA4_START_ADDR)
-#define bfin_read_MXVR_DMA4_COUNT() bfin_read16(MXVR_DMA4_COUNT)
-#define bfin_write_MXVR_DMA4_COUNT(val) bfin_write16(MXVR_DMA4_COUNT, val)
-#define bfin_read_MXVR_DMA4_CURR_ADDR() bfin_read32(MXVR_DMA4_CURR_ADDR)
-#define bfin_write_MXVR_DMA4_CURR_ADDR(val) bfin_write32(MXVR_DMA4_CURR_ADDR)
-#define bfin_read_MXVR_DMA4_CURR_COUNT() bfin_read16(MXVR_DMA4_CURR_COUNT)
-#define bfin_write_MXVR_DMA4_CURR_COUNT(val) bfin_write16(MXVR_DMA4_CURR_COUNT, val)
-
-/* MXVR DMA5 Registers */
-
-#define bfin_read_MXVR_DMA5_CONFIG() bfin_read32(MXVR_DMA5_CONFIG)
-#define bfin_write_MXVR_DMA5_CONFIG(val) bfin_write32(MXVR_DMA5_CONFIG, val)
-#define bfin_read_MXVR_DMA5_START_ADDR() bfin_read32(MXVR_DMA5_START_ADDR)
-#define bfin_write_MXVR_DMA5_START_ADDR(val) bfin_write32(MXVR_DMA5_START_ADDR)
-#define bfin_read_MXVR_DMA5_COUNT() bfin_read16(MXVR_DMA5_COUNT)
-#define bfin_write_MXVR_DMA5_COUNT(val) bfin_write16(MXVR_DMA5_COUNT, val)
-#define bfin_read_MXVR_DMA5_CURR_ADDR() bfin_read32(MXVR_DMA5_CURR_ADDR)
-#define bfin_write_MXVR_DMA5_CURR_ADDR(val) bfin_write32(MXVR_DMA5_CURR_ADDR)
-#define bfin_read_MXVR_DMA5_CURR_COUNT() bfin_read16(MXVR_DMA5_CURR_COUNT)
-#define bfin_write_MXVR_DMA5_CURR_COUNT(val) bfin_write16(MXVR_DMA5_CURR_COUNT, val)
-
-/* MXVR DMA6 Registers */
-
-#define bfin_read_MXVR_DMA6_CONFIG() bfin_read32(MXVR_DMA6_CONFIG)
-#define bfin_write_MXVR_DMA6_CONFIG(val) bfin_write32(MXVR_DMA6_CONFIG, val)
-#define bfin_read_MXVR_DMA6_START_ADDR() bfin_read32(MXVR_DMA6_START_ADDR)
-#define bfin_write_MXVR_DMA6_START_ADDR(val) bfin_write32(MXVR_DMA6_START_ADDR)
-#define bfin_read_MXVR_DMA6_COUNT() bfin_read16(MXVR_DMA6_COUNT)
-#define bfin_write_MXVR_DMA6_COUNT(val) bfin_write16(MXVR_DMA6_COUNT, val)
-#define bfin_read_MXVR_DMA6_CURR_ADDR() bfin_read32(MXVR_DMA6_CURR_ADDR)
-#define bfin_write_MXVR_DMA6_CURR_ADDR(val) bfin_write32(MXVR_DMA6_CURR_ADDR)
-#define bfin_read_MXVR_DMA6_CURR_COUNT() bfin_read16(MXVR_DMA6_CURR_COUNT)
-#define bfin_write_MXVR_DMA6_CURR_COUNT(val) bfin_write16(MXVR_DMA6_CURR_COUNT, val)
-
-/* MXVR DMA7 Registers */
-
-#define bfin_read_MXVR_DMA7_CONFIG() bfin_read32(MXVR_DMA7_CONFIG)
-#define bfin_write_MXVR_DMA7_CONFIG(val) bfin_write32(MXVR_DMA7_CONFIG, val)
-#define bfin_read_MXVR_DMA7_START_ADDR() bfin_read32(MXVR_DMA7_START_ADDR)
-#define bfin_write_MXVR_DMA7_START_ADDR(val) bfin_write32(MXVR_DMA7_START_ADDR)
-#define bfin_read_MXVR_DMA7_COUNT() bfin_read16(MXVR_DMA7_COUNT)
-#define bfin_write_MXVR_DMA7_COUNT(val) bfin_write16(MXVR_DMA7_COUNT, val)
-#define bfin_read_MXVR_DMA7_CURR_ADDR() bfin_read32(MXVR_DMA7_CURR_ADDR)
-#define bfin_write_MXVR_DMA7_CURR_ADDR(val) bfin_write32(MXVR_DMA7_CURR_ADDR)
-#define bfin_read_MXVR_DMA7_CURR_COUNT() bfin_read16(MXVR_DMA7_CURR_COUNT)
-#define bfin_write_MXVR_DMA7_CURR_COUNT(val) bfin_write16(MXVR_DMA7_CURR_COUNT, val)
-
-/* MXVR Asynch Packet Registers */
-
-#define bfin_read_MXVR_AP_CTL() bfin_read16(MXVR_AP_CTL)
-#define bfin_write_MXVR_AP_CTL(val) bfin_write16(MXVR_AP_CTL, val)
-#define bfin_read_MXVR_APRB_START_ADDR() bfin_read32(MXVR_APRB_START_ADDR)
-#define bfin_write_MXVR_APRB_START_ADDR(val) bfin_write32(MXVR_APRB_START_ADDR)
-#define bfin_read_MXVR_APRB_CURR_ADDR() bfin_read32(MXVR_APRB_CURR_ADDR)
-#define bfin_write_MXVR_APRB_CURR_ADDR(val) bfin_write32(MXVR_APRB_CURR_ADDR)
-#define bfin_read_MXVR_APTB_START_ADDR() bfin_read32(MXVR_APTB_START_ADDR)
-#define bfin_write_MXVR_APTB_START_ADDR(val) bfin_write32(MXVR_APTB_START_ADDR)
-#define bfin_read_MXVR_APTB_CURR_ADDR() bfin_read32(MXVR_APTB_CURR_ADDR)
-#define bfin_write_MXVR_APTB_CURR_ADDR(val) bfin_write32(MXVR_APTB_CURR_ADDR)
-
-/* MXVR Control Message Registers */
-
-#define bfin_read_MXVR_CM_CTL() bfin_read32(MXVR_CM_CTL)
-#define bfin_write_MXVR_CM_CTL(val) bfin_write32(MXVR_CM_CTL, val)
-#define bfin_read_MXVR_CMRB_START_ADDR() bfin_read32(MXVR_CMRB_START_ADDR)
-#define bfin_write_MXVR_CMRB_START_ADDR(val) bfin_write32(MXVR_CMRB_START_ADDR)
-#define bfin_read_MXVR_CMRB_CURR_ADDR() bfin_read32(MXVR_CMRB_CURR_ADDR)
-#define bfin_write_MXVR_CMRB_CURR_ADDR(val) bfin_write32(MXVR_CMRB_CURR_ADDR)
-#define bfin_read_MXVR_CMTB_START_ADDR() bfin_read32(MXVR_CMTB_START_ADDR)
-#define bfin_write_MXVR_CMTB_START_ADDR(val) bfin_write32(MXVR_CMTB_START_ADDR)
-#define bfin_read_MXVR_CMTB_CURR_ADDR() bfin_read32(MXVR_CMTB_CURR_ADDR)
-#define bfin_write_MXVR_CMTB_CURR_ADDR(val) bfin_write32(MXVR_CMTB_CURR_ADDR)
-
-/* MXVR Remote Read Registers */
-
-#define bfin_read_MXVR_RRDB_START_ADDR() bfin_read32(MXVR_RRDB_START_ADDR)
-#define bfin_write_MXVR_RRDB_START_ADDR(val) bfin_write32(MXVR_RRDB_START_ADDR)
-#define bfin_read_MXVR_RRDB_CURR_ADDR() bfin_read32(MXVR_RRDB_CURR_ADDR)
-#define bfin_write_MXVR_RRDB_CURR_ADDR(val) bfin_write32(MXVR_RRDB_CURR_ADDR)
-
-/* MXVR Pattern Data Registers */
-
-#define bfin_read_MXVR_PAT_DATA_0() bfin_read32(MXVR_PAT_DATA_0)
-#define bfin_write_MXVR_PAT_DATA_0(val) bfin_write32(MXVR_PAT_DATA_0, val)
-#define bfin_read_MXVR_PAT_EN_0() bfin_read32(MXVR_PAT_EN_0)
-#define bfin_write_MXVR_PAT_EN_0(val) bfin_write32(MXVR_PAT_EN_0, val)
-#define bfin_read_MXVR_PAT_DATA_1() bfin_read32(MXVR_PAT_DATA_1)
-#define bfin_write_MXVR_PAT_DATA_1(val) bfin_write32(MXVR_PAT_DATA_1, val)
-#define bfin_read_MXVR_PAT_EN_1() bfin_read32(MXVR_PAT_EN_1)
-#define bfin_write_MXVR_PAT_EN_1(val) bfin_write32(MXVR_PAT_EN_1, val)
-
-/* MXVR Frame Counter Registers */
-
-#define bfin_read_MXVR_FRAME_CNT_0() bfin_read16(MXVR_FRAME_CNT_0)
-#define bfin_write_MXVR_FRAME_CNT_0(val) bfin_write16(MXVR_FRAME_CNT_0, val)
-#define bfin_read_MXVR_FRAME_CNT_1() bfin_read16(MXVR_FRAME_CNT_1)
-#define bfin_write_MXVR_FRAME_CNT_1(val) bfin_write16(MXVR_FRAME_CNT_1, val)
-
-/* MXVR Routing Table Registers */
-
-#define bfin_read_MXVR_ROUTING_0() bfin_read32(MXVR_ROUTING_0)
-#define bfin_write_MXVR_ROUTING_0(val) bfin_write32(MXVR_ROUTING_0, val)
-#define bfin_read_MXVR_ROUTING_1() bfin_read32(MXVR_ROUTING_1)
-#define bfin_write_MXVR_ROUTING_1(val) bfin_write32(MXVR_ROUTING_1, val)
-#define bfin_read_MXVR_ROUTING_2() bfin_read32(MXVR_ROUTING_2)
-#define bfin_write_MXVR_ROUTING_2(val) bfin_write32(MXVR_ROUTING_2, val)
-#define bfin_read_MXVR_ROUTING_3() bfin_read32(MXVR_ROUTING_3)
-#define bfin_write_MXVR_ROUTING_3(val) bfin_write32(MXVR_ROUTING_3, val)
-#define bfin_read_MXVR_ROUTING_4() bfin_read32(MXVR_ROUTING_4)
-#define bfin_write_MXVR_ROUTING_4(val) bfin_write32(MXVR_ROUTING_4, val)
-#define bfin_read_MXVR_ROUTING_5() bfin_read32(MXVR_ROUTING_5)
-#define bfin_write_MXVR_ROUTING_5(val) bfin_write32(MXVR_ROUTING_5, val)
-#define bfin_read_MXVR_ROUTING_6() bfin_read32(MXVR_ROUTING_6)
-#define bfin_write_MXVR_ROUTING_6(val) bfin_write32(MXVR_ROUTING_6, val)
-#define bfin_read_MXVR_ROUTING_7() bfin_read32(MXVR_ROUTING_7)
-#define bfin_write_MXVR_ROUTING_7(val) bfin_write32(MXVR_ROUTING_7, val)
-#define bfin_read_MXVR_ROUTING_8() bfin_read32(MXVR_ROUTING_8)
-#define bfin_write_MXVR_ROUTING_8(val) bfin_write32(MXVR_ROUTING_8, val)
-#define bfin_read_MXVR_ROUTING_9() bfin_read32(MXVR_ROUTING_9)
-#define bfin_write_MXVR_ROUTING_9(val) bfin_write32(MXVR_ROUTING_9, val)
-#define bfin_read_MXVR_ROUTING_10() bfin_read32(MXVR_ROUTING_10)
-#define bfin_write_MXVR_ROUTING_10(val) bfin_write32(MXVR_ROUTING_10, val)
-#define bfin_read_MXVR_ROUTING_11() bfin_read32(MXVR_ROUTING_11)
-#define bfin_write_MXVR_ROUTING_11(val) bfin_write32(MXVR_ROUTING_11, val)
-#define bfin_read_MXVR_ROUTING_12() bfin_read32(MXVR_ROUTING_12)
-#define bfin_write_MXVR_ROUTING_12(val) bfin_write32(MXVR_ROUTING_12, val)
-#define bfin_read_MXVR_ROUTING_13() bfin_read32(MXVR_ROUTING_13)
-#define bfin_write_MXVR_ROUTING_13(val) bfin_write32(MXVR_ROUTING_13, val)
-#define bfin_read_MXVR_ROUTING_14() bfin_read32(MXVR_ROUTING_14)
-#define bfin_write_MXVR_ROUTING_14(val) bfin_write32(MXVR_ROUTING_14, val)
-
-/* MXVR Counter-Clock-Control Registers */
-
-#define bfin_read_MXVR_BLOCK_CNT() bfin_read16(MXVR_BLOCK_CNT)
-#define bfin_write_MXVR_BLOCK_CNT(val) bfin_write16(MXVR_BLOCK_CNT, val)
-#define bfin_read_MXVR_CLK_CTL() bfin_read32(MXVR_CLK_CTL)
-#define bfin_write_MXVR_CLK_CTL(val) bfin_write32(MXVR_CLK_CTL, val)
-#define bfin_read_MXVR_CDRPLL_CTL() bfin_read32(MXVR_CDRPLL_CTL)
-#define bfin_write_MXVR_CDRPLL_CTL(val) bfin_write32(MXVR_CDRPLL_CTL, val)
-#define bfin_read_MXVR_FMPLL_CTL() bfin_read32(MXVR_FMPLL_CTL)
-#define bfin_write_MXVR_FMPLL_CTL(val) bfin_write32(MXVR_FMPLL_CTL, val)
-#define bfin_read_MXVR_PIN_CTL() bfin_read16(MXVR_PIN_CTL)
-#define bfin_write_MXVR_PIN_CTL(val) bfin_write16(MXVR_PIN_CTL, val)
-#define bfin_read_MXVR_SCLK_CNT() bfin_read16(MXVR_SCLK_CNT)
-#define bfin_write_MXVR_SCLK_CNT(val) bfin_write16(MXVR_SCLK_CNT, val)
-
-#endif /* _CDEF_BF549_H */
+++ /dev/null
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CDEF_BF54X_H
-#define _CDEF_BF54X_H
-
-/* ************************************************************** */
-/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x */
-/* ************************************************************** */
-
-/* PLL Registers */
-
-#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
-#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
-#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
-#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
-#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
-
-/* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */
-
-#define bfin_read_CHIPID() bfin_read32(CHIPID)
-#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
-
-/* System Reset and Interrubfin_read_()t Controller (0xFFC00100 - 0xFFC00104) */
-
-#define bfin_read_SWRST() bfin_read16(SWRST)
-#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
-#define bfin_read_SYSCR() bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
-
-/* SIC Registers */
-
-#define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT)
-#define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val)
-#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
-#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
-#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)
-#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val)
-#define bfin_read_SIC_IMASK2() bfin_read32(SIC_IMASK2)
-#define bfin_write_SIC_IMASK2(val) bfin_write32(SIC_IMASK2, val)
-#define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + (x << 2))
-#define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 2)), val)
-
-#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
-#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
-#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
-#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
-#define bfin_read_SIC_ISR2() bfin_read32(SIC_ISR2)
-#define bfin_write_SIC_ISR2(val) bfin_write32(SIC_ISR2, val)
-#define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + (x << 2))
-#define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 2)), val)
-
-#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
-#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
-#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
-#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val)
-#define bfin_read_SIC_IWR2() bfin_read32(SIC_IWR2)
-#define bfin_write_SIC_IWR2(val) bfin_write32(SIC_IWR2, val)
-#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
-#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
-#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
-#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val)
-#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
-#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val)
-#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
-#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val)
-#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4)
-#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val)
-#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5)
-#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val)
-#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6)
-#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val)
-#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7)
-#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val)
-#define bfin_read_SIC_IAR8() bfin_read32(SIC_IAR8)
-#define bfin_write_SIC_IAR8(val) bfin_write32(SIC_IAR8, val)
-#define bfin_read_SIC_IAR9() bfin_read32(SIC_IAR9)
-#define bfin_write_SIC_IAR9(val) bfin_write32(SIC_IAR9, val)
-#define bfin_read_SIC_IAR10() bfin_read32(SIC_IAR10)
-#define bfin_write_SIC_IAR10(val) bfin_write32(SIC_IAR10, val)
-#define bfin_read_SIC_IAR11() bfin_read32(SIC_IAR11)
-#define bfin_write_SIC_IAR11(val) bfin_write32(SIC_IAR11, val)
-
-/* Watchdog Timer Registers */
-
-#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
-#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
-#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
-
-/* RTC Registers */
-
-#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
-#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val)
-#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
-#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val)
-#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
-#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val)
-#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
-#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val)
-#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
-#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val)
-#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
-#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val)
-
-/* UART0 Registers */
-
-#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL)
-#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val)
-#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH)
-#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val)
-#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL)
-#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val)
-#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR)
-#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val)
-#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR)
-#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val)
-#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR)
-#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val)
-#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR)
-#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val)
-#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR)
-#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val)
-#define bfin_read_UART0_IER_SET() bfin_read16(UART0_IER_SET)
-#define bfin_write_UART0_IER_SET(val) bfin_write16(UART0_IER_SET, val)
-#define bfin_read_UART0_IER_CLEAR() bfin_read16(UART0_IER_CLEAR)
-#define bfin_write_UART0_IER_CLEAR(val) bfin_write16(UART0_IER_CLEAR, val)
-#define bfin_read_UART0_THR() bfin_read16(UART0_THR)
-#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val)
-#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR)
-#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val)
-
-/* SPI0 Registers */
-
-#define bfin_read_SPI0_CTL() bfin_read16(SPI0_CTL)
-#define bfin_write_SPI0_CTL(val) bfin_write16(SPI0_CTL, val)
-#define bfin_read_SPI0_FLG() bfin_read16(SPI0_FLG)
-#define bfin_write_SPI0_FLG(val) bfin_write16(SPI0_FLG, val)
-#define bfin_read_SPI0_STAT() bfin_read16(SPI0_STAT)
-#define bfin_write_SPI0_STAT(val) bfin_write16(SPI0_STAT, val)
-#define bfin_read_SPI0_TDBR() bfin_read16(SPI0_TDBR)
-#define bfin_write_SPI0_TDBR(val) bfin_write16(SPI0_TDBR, val)
-#define bfin_read_SPI0_RDBR() bfin_read16(SPI0_RDBR)
-#define bfin_write_SPI0_RDBR(val) bfin_write16(SPI0_RDBR, val)
-#define bfin_read_SPI0_BAUD() bfin_read16(SPI0_BAUD)
-#define bfin_write_SPI0_BAUD(val) bfin_write16(SPI0_BAUD, val)
-#define bfin_read_SPI0_SHADOW() bfin_read16(SPI0_SHADOW)
-#define bfin_write_SPI0_SHADOW(val) bfin_write16(SPI0_SHADOW, val)
-
-/* Timer Groubfin_read_() of 3 registers are not defined in the shared file because they are not available on the ADSP-BF542 processor */
-
-/* Two Wire Interface Registers (TWI0) */
-
-/* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 bfin_read_()rocessors */
-
-/* SPORT1 Registers */
-
-#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val)
-#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val)
-#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
-#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
-#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
-#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
-#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
-#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val)
-#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
-#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val)
-#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val)
-#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val)
-#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val)
-#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val)
-#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
-#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val)
-#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
-#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val)
-#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
-#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val)
-#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
-#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val)
-#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
-#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val)
-#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
-#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val)
-#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
-#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val)
-#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
-#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val)
-
-/* Asynchronous Memory Control Registers */
-
-#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val)
-#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
-#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
-#define bfin_read_EBIU_MBSCTL() bfin_read16(EBIU_MBSCTL)
-#define bfin_write_EBIU_MBSCTL(val) bfin_write16(EBIU_MBSCTL, val)
-#define bfin_read_EBIU_ARBSTAT() bfin_read32(EBIU_ARBSTAT)
-#define bfin_write_EBIU_ARBSTAT(val) bfin_write32(EBIU_ARBSTAT, val)
-#define bfin_read_EBIU_MODE() bfin_read32(EBIU_MODE)
-#define bfin_write_EBIU_MODE(val) bfin_write32(EBIU_MODE, val)
-#define bfin_read_EBIU_FCTL() bfin_read16(EBIU_FCTL)
-#define bfin_write_EBIU_FCTL(val) bfin_write16(EBIU_FCTL, val)
-
-/* DDR Memory Control Registers */
-
-#define bfin_read_EBIU_DDRCTL0() bfin_read32(EBIU_DDRCTL0)
-#define bfin_write_EBIU_DDRCTL0(val) bfin_write32(EBIU_DDRCTL0, val)
-#define bfin_read_EBIU_DDRCTL1() bfin_read32(EBIU_DDRCTL1)
-#define bfin_write_EBIU_DDRCTL1(val) bfin_write32(EBIU_DDRCTL1, val)
-#define bfin_read_EBIU_DDRCTL2() bfin_read32(EBIU_DDRCTL2)
-#define bfin_write_EBIU_DDRCTL2(val) bfin_write32(EBIU_DDRCTL2, val)
-#define bfin_read_EBIU_DDRCTL3() bfin_read32(EBIU_DDRCTL3)
-#define bfin_write_EBIU_DDRCTL3(val) bfin_write32(EBIU_DDRCTL3, val)
-#define bfin_read_EBIU_DDRQUE() bfin_read32(EBIU_DDRQUE)
-#define bfin_write_EBIU_DDRQUE(val) bfin_write32(EBIU_DDRQUE, val)
-#define bfin_read_EBIU_ERRADD() bfin_read32(EBIU_ERRADD)
-#define bfin_write_EBIU_ERRADD(val) bfin_write32(EBIU_ERRADD, val)
-#define bfin_read_EBIU_ERRMST() bfin_read16(EBIU_ERRMST)
-#define bfin_write_EBIU_ERRMST(val) bfin_write16(EBIU_ERRMST, val)
-#define bfin_read_EBIU_RSTCTL() bfin_read16(EBIU_RSTCTL)
-#define bfin_write_EBIU_RSTCTL(val) bfin_write16(EBIU_RSTCTL, val)
-
-/* DDR BankRead and Write Count Registers */
-
-#define bfin_read_EBIU_DDRBRC0() bfin_read32(EBIU_DDRBRC0)
-#define bfin_write_EBIU_DDRBRC0(val) bfin_write32(EBIU_DDRBRC0, val)
-#define bfin_read_EBIU_DDRBRC1() bfin_read32(EBIU_DDRBRC1)
-#define bfin_write_EBIU_DDRBRC1(val) bfin_write32(EBIU_DDRBRC1, val)
-#define bfin_read_EBIU_DDRBRC2() bfin_read32(EBIU_DDRBRC2)
-#define bfin_write_EBIU_DDRBRC2(val) bfin_write32(EBIU_DDRBRC2, val)
-#define bfin_read_EBIU_DDRBRC3() bfin_read32(EBIU_DDRBRC3)
-#define bfin_write_EBIU_DDRBRC3(val) bfin_write32(EBIU_DDRBRC3, val)
-#define bfin_read_EBIU_DDRBRC4() bfin_read32(EBIU_DDRBRC4)
-#define bfin_write_EBIU_DDRBRC4(val) bfin_write32(EBIU_DDRBRC4, val)
-#define bfin_read_EBIU_DDRBRC5() bfin_read32(EBIU_DDRBRC5)
-#define bfin_write_EBIU_DDRBRC5(val) bfin_write32(EBIU_DDRBRC5, val)
-#define bfin_read_EBIU_DDRBRC6() bfin_read32(EBIU_DDRBRC6)
-#define bfin_write_EBIU_DDRBRC6(val) bfin_write32(EBIU_DDRBRC6, val)
-#define bfin_read_EBIU_DDRBRC7() bfin_read32(EBIU_DDRBRC7)
-#define bfin_write_EBIU_DDRBRC7(val) bfin_write32(EBIU_DDRBRC7, val)
-#define bfin_read_EBIU_DDRBWC0() bfin_read32(EBIU_DDRBWC0)
-#define bfin_write_EBIU_DDRBWC0(val) bfin_write32(EBIU_DDRBWC0, val)
-#define bfin_read_EBIU_DDRBWC1() bfin_read32(EBIU_DDRBWC1)
-#define bfin_write_EBIU_DDRBWC1(val) bfin_write32(EBIU_DDRBWC1, val)
-#define bfin_read_EBIU_DDRBWC2() bfin_read32(EBIU_DDRBWC2)
-#define bfin_write_EBIU_DDRBWC2(val) bfin_write32(EBIU_DDRBWC2, val)
-#define bfin_read_EBIU_DDRBWC3() bfin_read32(EBIU_DDRBWC3)
-#define bfin_write_EBIU_DDRBWC3(val) bfin_write32(EBIU_DDRBWC3, val)
-#define bfin_read_EBIU_DDRBWC4() bfin_read32(EBIU_DDRBWC4)
-#define bfin_write_EBIU_DDRBWC4(val) bfin_write32(EBIU_DDRBWC4, val)
-#define bfin_read_EBIU_DDRBWC5() bfin_read32(EBIU_DDRBWC5)
-#define bfin_write_EBIU_DDRBWC5(val) bfin_write32(EBIU_DDRBWC5, val)
-#define bfin_read_EBIU_DDRBWC6() bfin_read32(EBIU_DDRBWC6)
-#define bfin_write_EBIU_DDRBWC6(val) bfin_write32(EBIU_DDRBWC6, val)
-#define bfin_read_EBIU_DDRBWC7() bfin_read32(EBIU_DDRBWC7)
-#define bfin_write_EBIU_DDRBWC7(val) bfin_write32(EBIU_DDRBWC7, val)
-#define bfin_read_EBIU_DDRACCT() bfin_read32(EBIU_DDRACCT)
-#define bfin_write_EBIU_DDRACCT(val) bfin_write32(EBIU_DDRACCT, val)
-#define bfin_read_EBIU_DDRTACT() bfin_read32(EBIU_DDRTACT)
-#define bfin_write_EBIU_DDRTACT(val) bfin_write32(EBIU_DDRTACT, val)
-#define bfin_read_EBIU_DDRARCT() bfin_read32(EBIU_DDRARCT)
-#define bfin_write_EBIU_DDRARCT(val) bfin_write32(EBIU_DDRARCT, val)
-#define bfin_read_EBIU_DDRGC0() bfin_read32(EBIU_DDRGC0)
-#define bfin_write_EBIU_DDRGC0(val) bfin_write32(EBIU_DDRGC0, val)
-#define bfin_read_EBIU_DDRGC1() bfin_read32(EBIU_DDRGC1)
-#define bfin_write_EBIU_DDRGC1(val) bfin_write32(EBIU_DDRGC1, val)
-#define bfin_read_EBIU_DDRGC2() bfin_read32(EBIU_DDRGC2)
-#define bfin_write_EBIU_DDRGC2(val) bfin_write32(EBIU_DDRGC2, val)
-#define bfin_read_EBIU_DDRGC3() bfin_read32(EBIU_DDRGC3)
-#define bfin_write_EBIU_DDRGC3(val) bfin_write32(EBIU_DDRGC3, val)
-#define bfin_read_EBIU_DDRMCEN() bfin_read32(EBIU_DDRMCEN)
-#define bfin_write_EBIU_DDRMCEN(val) bfin_write32(EBIU_DDRMCEN, val)
-#define bfin_read_EBIU_DDRMCCL() bfin_read32(EBIU_DDRMCCL)
-#define bfin_write_EBIU_DDRMCCL(val) bfin_write32(EBIU_DDRMCCL, val)
-
-/* DMAC0 Registers */
-
-#define bfin_read_DMAC0_TC_PER() bfin_read16(DMAC0_TC_PER)
-#define bfin_write_DMAC0_TC_PER(val) bfin_write16(DMAC0_TC_PER, val)
-#define bfin_read_DMAC0_TC_CNT() bfin_read16(DMAC0_TC_CNT)
-#define bfin_write_DMAC0_TC_CNT(val) bfin_write16(DMAC0_TC_CNT, val)
-
-/* DMA Channel 0 Registers */
-
-#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val)
-#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val)
-#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
-#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val)
-#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
-#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val)
-#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val)
-#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
-#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val)
-#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val)
-#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val)
-#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val)
-#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
-#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
-#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
-#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
-#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
-#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
-#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
-#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
-
-/* DMA Channel 1 Registers */
-
-#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val)
-#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
-#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val)
-#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
-#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val)
-#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val)
-#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
-#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val)
-#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val)
-#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val)
-#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
-#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
-#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
-#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
-#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
-#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
-#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
-
-/* DMA Channel 2 Registers */
-
-#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val)
-#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
-#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val)
-#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
-#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val)
-#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val)
-#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
-#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val)
-#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val)
-#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val)
-#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
-#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
-#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
-#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
-#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
-#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
-#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
-
-/* DMA Channel 3 Registers */
-
-#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val)
-#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val)
-#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
-#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val)
-#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
-#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val)
-#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val)
-#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
-#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val)
-#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val)
-#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val)
-#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val)
-#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
-#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
-#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
-#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
-#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
-#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
-#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
-#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
-
-/* DMA Channel 4 Registers */
-
-#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val)
-#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val)
-#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
-#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val)
-#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
-#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val)
-#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val)
-#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
-#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val)
-#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val)
-#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val)
-#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val)
-#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
-#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
-#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
-#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
-#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
-#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
-#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
-#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
-
-/* DMA Channel 5 Registers */
-
-#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val)
-#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val)
-#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
-#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
-#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
-#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val)
-#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val)
-#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
-#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
-#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val)
-#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val)
-#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val)
-#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
-#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
-#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
-#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
-#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
-#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
-#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
-#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
-
-/* DMA Channel 6 Registers */
-
-#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
-#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val)
-#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
-#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val)
-#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
-#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val)
-#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val)
-#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
-#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val)
-#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val)
-#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val)
-#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val)
-#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
-#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
-#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
-#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
-#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
-#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
-#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
-#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
-
-/* DMA Channel 7 Registers */
-
-#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val)
-#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val)
-#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
-#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val)
-#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
-#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val)
-#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val)
-#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
-#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val)
-#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val)
-#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val)
-#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val)
-#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
-#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
-#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
-#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
-#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
-#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
-#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
-#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
-
-/* DMA Channel 8 Registers */
-
-#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR)
-#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR, val)
-#define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR)
-#define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR, val)
-#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG)
-#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val)
-#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT)
-#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val)
-#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY)
-#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val)
-#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT)
-#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val)
-#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY)
-#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val)
-#define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR)
-#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR, val)
-#define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR)
-#define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR, val)
-#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
-#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
-#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
-#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
-#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT)
-#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
-#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT)
-#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
-
-/* DMA Channel 9 Registers */
-
-#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR)
-#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR, val)
-#define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR)
-#define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR, val)
-#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG)
-#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val)
-#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT)
-#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val)
-#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY)
-#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val)
-#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT)
-#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val)
-#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY)
-#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val)
-#define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR)
-#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR, val)
-#define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR)
-#define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR, val)
-#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS)
-#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
-#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
-#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
-#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT)
-#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
-#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT)
-#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
-
-/* DMA Channel 10 Registers */
-
-#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR)
-#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR, val)
-#define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR)
-#define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR, val)
-#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG)
-#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val)
-#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT)
-#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val)
-#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY)
-#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
-#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT)
-#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val)
-#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY)
-#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
-#define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR)
-#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR, val)
-#define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR)
-#define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR, val)
-#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS)
-#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
-#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
-#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
-#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
-#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
-#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
-#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
-
-/* DMA Channel 11 Registers */
-
-#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR)
-#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR, val)
-#define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR)
-#define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR, val)
-#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG)
-#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val)
-#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT)
-#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val)
-#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY)
-#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
-#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT)
-#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val)
-#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY)
-#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
-#define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR)
-#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR, val)
-#define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR)
-#define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR, val)
-#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS)
-#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
-#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
-#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
-#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
-#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
-#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
-#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
-
-/* MDMA Stream 0 Registers */
-
-#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR)
-#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val)
-#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
-#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
-#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
-#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
-#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
-#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
-#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
-#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
-#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
-#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
-#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR)
-#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR, val)
-#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
-#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
-#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
-#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR)
-#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR, val)
-#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
-#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
-#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
-#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
-#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
-#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
-#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
-#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
-#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
-#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
-#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR)
-#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR, val)
-#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
-#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
-#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
-#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
-
-/* MDMA Stream 1 Registers */
-
-#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR)
-#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR, val)
-#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
-#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
-#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
-#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
-#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
-#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
-#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
-#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
-#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
-#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
-#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR)
-#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR, val)
-#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
-#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
-#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
-#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR)
-#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR, val)
-#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
-#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
-#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
-#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
-#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
-#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
-#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
-#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
-#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
-#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
-#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR)
-#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR, val)
-#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
-#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
-#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
-#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
-
-/* EPPI1 Registers */
-
-#define bfin_read_EPPI1_STATUS() bfin_read16(EPPI1_STATUS)
-#define bfin_write_EPPI1_STATUS(val) bfin_write16(EPPI1_STATUS, val)
-#define bfin_read_EPPI1_HCOUNT() bfin_read16(EPPI1_HCOUNT)
-#define bfin_write_EPPI1_HCOUNT(val) bfin_write16(EPPI1_HCOUNT, val)
-#define bfin_read_EPPI1_HDELAY() bfin_read16(EPPI1_HDELAY)
-#define bfin_write_EPPI1_HDELAY(val) bfin_write16(EPPI1_HDELAY, val)
-#define bfin_read_EPPI1_VCOUNT() bfin_read16(EPPI1_VCOUNT)
-#define bfin_write_EPPI1_VCOUNT(val) bfin_write16(EPPI1_VCOUNT, val)
-#define bfin_read_EPPI1_VDELAY() bfin_read16(EPPI1_VDELAY)
-#define bfin_write_EPPI1_VDELAY(val) bfin_write16(EPPI1_VDELAY, val)
-#define bfin_read_EPPI1_FRAME() bfin_read16(EPPI1_FRAME)
-#define bfin_write_EPPI1_FRAME(val) bfin_write16(EPPI1_FRAME, val)
-#define bfin_read_EPPI1_LINE() bfin_read16(EPPI1_LINE)
-#define bfin_write_EPPI1_LINE(val) bfin_write16(EPPI1_LINE, val)
-#define bfin_read_EPPI1_CLKDIV() bfin_read16(EPPI1_CLKDIV)
-#define bfin_write_EPPI1_CLKDIV(val) bfin_write16(EPPI1_CLKDIV, val)
-#define bfin_read_EPPI1_CONTROL() bfin_read32(EPPI1_CONTROL)
-#define bfin_write_EPPI1_CONTROL(val) bfin_write32(EPPI1_CONTROL, val)
-#define bfin_read_EPPI1_FS1W_HBL() bfin_read32(EPPI1_FS1W_HBL)
-#define bfin_write_EPPI1_FS1W_HBL(val) bfin_write32(EPPI1_FS1W_HBL, val)
-#define bfin_read_EPPI1_FS1P_AVPL() bfin_read32(EPPI1_FS1P_AVPL)
-#define bfin_write_EPPI1_FS1P_AVPL(val) bfin_write32(EPPI1_FS1P_AVPL, val)
-#define bfin_read_EPPI1_FS2W_LVB() bfin_read32(EPPI1_FS2W_LVB)
-#define bfin_write_EPPI1_FS2W_LVB(val) bfin_write32(EPPI1_FS2W_LVB, val)
-#define bfin_read_EPPI1_FS2P_LAVF() bfin_read32(EPPI1_FS2P_LAVF)
-#define bfin_write_EPPI1_FS2P_LAVF(val) bfin_write32(EPPI1_FS2P_LAVF, val)
-#define bfin_read_EPPI1_CLIP() bfin_read32(EPPI1_CLIP)
-#define bfin_write_EPPI1_CLIP(val) bfin_write32(EPPI1_CLIP, val)
-
-/* Port Interrubfin_read_()t 0 Registers (32-bit) */
-
-#define bfin_read_PINT0_MASK_SET() bfin_read32(PINT0_MASK_SET)
-#define bfin_write_PINT0_MASK_SET(val) bfin_write32(PINT0_MASK_SET, val)
-#define bfin_read_PINT0_MASK_CLEAR() bfin_read32(PINT0_MASK_CLEAR)
-#define bfin_write_PINT0_MASK_CLEAR(val) bfin_write32(PINT0_MASK_CLEAR, val)
-#define bfin_read_PINT0_REQUEST() bfin_read32(PINT0_REQUEST)
-#define bfin_write_PINT0_REQUEST(val) bfin_write32(PINT0_REQUEST, val)
-#define bfin_read_PINT0_ASSIGN() bfin_read32(PINT0_ASSIGN)
-#define bfin_write_PINT0_ASSIGN(val) bfin_write32(PINT0_ASSIGN, val)
-#define bfin_read_PINT0_EDGE_SET() bfin_read32(PINT0_EDGE_SET)
-#define bfin_write_PINT0_EDGE_SET(val) bfin_write32(PINT0_EDGE_SET, val)
-#define bfin_read_PINT0_EDGE_CLEAR() bfin_read32(PINT0_EDGE_CLEAR)
-#define bfin_write_PINT0_EDGE_CLEAR(val) bfin_write32(PINT0_EDGE_CLEAR, val)
-#define bfin_read_PINT0_INVERT_SET() bfin_read32(PINT0_INVERT_SET)
-#define bfin_write_PINT0_INVERT_SET(val) bfin_write32(PINT0_INVERT_SET, val)
-#define bfin_read_PINT0_INVERT_CLEAR() bfin_read32(PINT0_INVERT_CLEAR)
-#define bfin_write_PINT0_INVERT_CLEAR(val) bfin_write32(PINT0_INVERT_CLEAR, val)
-#define bfin_read_PINT0_PINSTATE() bfin_read32(PINT0_PINSTATE)
-#define bfin_write_PINT0_PINSTATE(val) bfin_write32(PINT0_PINSTATE, val)
-#define bfin_read_PINT0_LATCH() bfin_read32(PINT0_LATCH)
-#define bfin_write_PINT0_LATCH(val) bfin_write32(PINT0_LATCH, val)
-
-/* Port Interrubfin_read_()t 1 Registers (32-bit) */
-
-#define bfin_read_PINT1_MASK_SET() bfin_read32(PINT1_MASK_SET)
-#define bfin_write_PINT1_MASK_SET(val) bfin_write32(PINT1_MASK_SET, val)
-#define bfin_read_PINT1_MASK_CLEAR() bfin_read32(PINT1_MASK_CLEAR)
-#define bfin_write_PINT1_MASK_CLEAR(val) bfin_write32(PINT1_MASK_CLEAR, val)
-#define bfin_read_PINT1_REQUEST() bfin_read32(PINT1_REQUEST)
-#define bfin_write_PINT1_REQUEST(val) bfin_write32(PINT1_REQUEST, val)
-#define bfin_read_PINT1_ASSIGN() bfin_read32(PINT1_ASSIGN)
-#define bfin_write_PINT1_ASSIGN(val) bfin_write32(PINT1_ASSIGN, val)
-#define bfin_read_PINT1_EDGE_SET() bfin_read32(PINT1_EDGE_SET)
-#define bfin_write_PINT1_EDGE_SET(val) bfin_write32(PINT1_EDGE_SET, val)
-#define bfin_read_PINT1_EDGE_CLEAR() bfin_read32(PINT1_EDGE_CLEAR)
-#define bfin_write_PINT1_EDGE_CLEAR(val) bfin_write32(PINT1_EDGE_CLEAR, val)
-#define bfin_read_PINT1_INVERT_SET() bfin_read32(PINT1_INVERT_SET)
-#define bfin_write_PINT1_INVERT_SET(val) bfin_write32(PINT1_INVERT_SET, val)
-#define bfin_read_PINT1_INVERT_CLEAR() bfin_read32(PINT1_INVERT_CLEAR)
-#define bfin_write_PINT1_INVERT_CLEAR(val) bfin_write32(PINT1_INVERT_CLEAR, val)
-#define bfin_read_PINT1_PINSTATE() bfin_read32(PINT1_PINSTATE)
-#define bfin_write_PINT1_PINSTATE(val) bfin_write32(PINT1_PINSTATE, val)
-#define bfin_read_PINT1_LATCH() bfin_read32(PINT1_LATCH)
-#define bfin_write_PINT1_LATCH(val) bfin_write32(PINT1_LATCH, val)
-
-/* Port Interrubfin_read_()t 2 Registers (32-bit) */
-
-#define bfin_read_PINT2_MASK_SET() bfin_read32(PINT2_MASK_SET)
-#define bfin_write_PINT2_MASK_SET(val) bfin_write32(PINT2_MASK_SET, val)
-#define bfin_read_PINT2_MASK_CLEAR() bfin_read32(PINT2_MASK_CLEAR)
-#define bfin_write_PINT2_MASK_CLEAR(val) bfin_write32(PINT2_MASK_CLEAR, val)
-#define bfin_read_PINT2_REQUEST() bfin_read32(PINT2_REQUEST)
-#define bfin_write_PINT2_REQUEST(val) bfin_write32(PINT2_REQUEST, val)
-#define bfin_read_PINT2_ASSIGN() bfin_read32(PINT2_ASSIGN)
-#define bfin_write_PINT2_ASSIGN(val) bfin_write32(PINT2_ASSIGN, val)
-#define bfin_read_PINT2_EDGE_SET() bfin_read32(PINT2_EDGE_SET)
-#define bfin_write_PINT2_EDGE_SET(val) bfin_write32(PINT2_EDGE_SET, val)
-#define bfin_read_PINT2_EDGE_CLEAR() bfin_read32(PINT2_EDGE_CLEAR)
-#define bfin_write_PINT2_EDGE_CLEAR(val) bfin_write32(PINT2_EDGE_CLEAR, val)
-#define bfin_read_PINT2_INVERT_SET() bfin_read32(PINT2_INVERT_SET)
-#define bfin_write_PINT2_INVERT_SET(val) bfin_write32(PINT2_INVERT_SET, val)
-#define bfin_read_PINT2_INVERT_CLEAR() bfin_read32(PINT2_INVERT_CLEAR)
-#define bfin_write_PINT2_INVERT_CLEAR(val) bfin_write32(PINT2_INVERT_CLEAR, val)
-#define bfin_read_PINT2_PINSTATE() bfin_read32(PINT2_PINSTATE)
-#define bfin_write_PINT2_PINSTATE(val) bfin_write32(PINT2_PINSTATE, val)
-#define bfin_read_PINT2_LATCH() bfin_read32(PINT2_LATCH)
-#define bfin_write_PINT2_LATCH(val) bfin_write32(PINT2_LATCH, val)
-
-/* Port Interrubfin_read_()t 3 Registers (32-bit) */
-
-#define bfin_read_PINT3_MASK_SET() bfin_read32(PINT3_MASK_SET)
-#define bfin_write_PINT3_MASK_SET(val) bfin_write32(PINT3_MASK_SET, val)
-#define bfin_read_PINT3_MASK_CLEAR() bfin_read32(PINT3_MASK_CLEAR)
-#define bfin_write_PINT3_MASK_CLEAR(val) bfin_write32(PINT3_MASK_CLEAR, val)
-#define bfin_read_PINT3_REQUEST() bfin_read32(PINT3_REQUEST)
-#define bfin_write_PINT3_REQUEST(val) bfin_write32(PINT3_REQUEST, val)
-#define bfin_read_PINT3_ASSIGN() bfin_read32(PINT3_ASSIGN)
-#define bfin_write_PINT3_ASSIGN(val) bfin_write32(PINT3_ASSIGN, val)
-#define bfin_read_PINT3_EDGE_SET() bfin_read32(PINT3_EDGE_SET)
-#define bfin_write_PINT3_EDGE_SET(val) bfin_write32(PINT3_EDGE_SET, val)
-#define bfin_read_PINT3_EDGE_CLEAR() bfin_read32(PINT3_EDGE_CLEAR)
-#define bfin_write_PINT3_EDGE_CLEAR(val) bfin_write32(PINT3_EDGE_CLEAR, val)
-#define bfin_read_PINT3_INVERT_SET() bfin_read32(PINT3_INVERT_SET)
-#define bfin_write_PINT3_INVERT_SET(val) bfin_write32(PINT3_INVERT_SET, val)
-#define bfin_read_PINT3_INVERT_CLEAR() bfin_read32(PINT3_INVERT_CLEAR)
-#define bfin_write_PINT3_INVERT_CLEAR(val) bfin_write32(PINT3_INVERT_CLEAR, val)
-#define bfin_read_PINT3_PINSTATE() bfin_read32(PINT3_PINSTATE)
-#define bfin_write_PINT3_PINSTATE(val) bfin_write32(PINT3_PINSTATE, val)
-#define bfin_read_PINT3_LATCH() bfin_read32(PINT3_LATCH)
-#define bfin_write_PINT3_LATCH(val) bfin_write32(PINT3_LATCH, val)
-
-/* Port A Registers */
-
-#define bfin_read_PORTA_FER() bfin_read16(PORTA_FER)
-#define bfin_write_PORTA_FER(val) bfin_write16(PORTA_FER, val)
-#define bfin_read_PORTA() bfin_read16(PORTA)
-#define bfin_write_PORTA(val) bfin_write16(PORTA, val)
-#define bfin_read_PORTA_SET() bfin_read16(PORTA_SET)
-#define bfin_write_PORTA_SET(val) bfin_write16(PORTA_SET, val)
-#define bfin_read_PORTA_CLEAR() bfin_read16(PORTA_CLEAR)
-#define bfin_write_PORTA_CLEAR(val) bfin_write16(PORTA_CLEAR, val)
-#define bfin_read_PORTA_DIR_SET() bfin_read16(PORTA_DIR_SET)
-#define bfin_write_PORTA_DIR_SET(val) bfin_write16(PORTA_DIR_SET, val)
-#define bfin_read_PORTA_DIR_CLEAR() bfin_read16(PORTA_DIR_CLEAR)
-#define bfin_write_PORTA_DIR_CLEAR(val) bfin_write16(PORTA_DIR_CLEAR, val)
-#define bfin_read_PORTA_INEN() bfin_read16(PORTA_INEN)
-#define bfin_write_PORTA_INEN(val) bfin_write16(PORTA_INEN, val)
-#define bfin_read_PORTA_MUX() bfin_read32(PORTA_MUX)
-#define bfin_write_PORTA_MUX(val) bfin_write32(PORTA_MUX, val)
-
-/* Port B Registers */
-
-#define bfin_read_PORTB_FER() bfin_read16(PORTB_FER)
-#define bfin_write_PORTB_FER(val) bfin_write16(PORTB_FER, val)
-#define bfin_read_PORTB() bfin_read16(PORTB)
-#define bfin_write_PORTB(val) bfin_write16(PORTB, val)
-#define bfin_read_PORTB_SET() bfin_read16(PORTB_SET)
-#define bfin_write_PORTB_SET(val) bfin_write16(PORTB_SET, val)
-#define bfin_read_PORTB_CLEAR() bfin_read16(PORTB_CLEAR)
-#define bfin_write_PORTB_CLEAR(val) bfin_write16(PORTB_CLEAR, val)
-#define bfin_read_PORTB_DIR_SET() bfin_read16(PORTB_DIR_SET)
-#define bfin_write_PORTB_DIR_SET(val) bfin_write16(PORTB_DIR_SET, val)
-#define bfin_read_PORTB_DIR_CLEAR() bfin_read16(PORTB_DIR_CLEAR)
-#define bfin_write_PORTB_DIR_CLEAR(val) bfin_write16(PORTB_DIR_CLEAR, val)
-#define bfin_read_PORTB_INEN() bfin_read16(PORTB_INEN)
-#define bfin_write_PORTB_INEN(val) bfin_write16(PORTB_INEN, val)
-#define bfin_read_PORTB_MUX() bfin_read32(PORTB_MUX)
-#define bfin_write_PORTB_MUX(val) bfin_write32(PORTB_MUX, val)
-
-/* Port C Registers */
-
-#define bfin_read_PORTC_FER() bfin_read16(PORTC_FER)
-#define bfin_write_PORTC_FER(val) bfin_write16(PORTC_FER, val)
-#define bfin_read_PORTC() bfin_read16(PORTC)
-#define bfin_write_PORTC(val) bfin_write16(PORTC, val)
-#define bfin_read_PORTC_SET() bfin_read16(PORTC_SET)
-#define bfin_write_PORTC_SET(val) bfin_write16(PORTC_SET, val)
-#define bfin_read_PORTC_CLEAR() bfin_read16(PORTC_CLEAR)
-#define bfin_write_PORTC_CLEAR(val) bfin_write16(PORTC_CLEAR, val)
-#define bfin_read_PORTC_DIR_SET() bfin_read16(PORTC_DIR_SET)
-#define bfin_write_PORTC_DIR_SET(val) bfin_write16(PORTC_DIR_SET, val)
-#define bfin_read_PORTC_DIR_CLEAR() bfin_read16(PORTC_DIR_CLEAR)
-#define bfin_write_PORTC_DIR_CLEAR(val) bfin_write16(PORTC_DIR_CLEAR, val)
-#define bfin_read_PORTC_INEN() bfin_read16(PORTC_INEN)
-#define bfin_write_PORTC_INEN(val) bfin_write16(PORTC_INEN, val)
-#define bfin_read_PORTC_MUX() bfin_read32(PORTC_MUX)
-#define bfin_write_PORTC_MUX(val) bfin_write32(PORTC_MUX, val)
-
-/* Port D Registers */
-
-#define bfin_read_PORTD_FER() bfin_read16(PORTD_FER)
-#define bfin_write_PORTD_FER(val) bfin_write16(PORTD_FER, val)
-#define bfin_read_PORTD() bfin_read16(PORTD)
-#define bfin_write_PORTD(val) bfin_write16(PORTD, val)
-#define bfin_read_PORTD_SET() bfin_read16(PORTD_SET)
-#define bfin_write_PORTD_SET(val) bfin_write16(PORTD_SET, val)
-#define bfin_read_PORTD_CLEAR() bfin_read16(PORTD_CLEAR)
-#define bfin_write_PORTD_CLEAR(val) bfin_write16(PORTD_CLEAR, val)
-#define bfin_read_PORTD_DIR_SET() bfin_read16(PORTD_DIR_SET)
-#define bfin_write_PORTD_DIR_SET(val) bfin_write16(PORTD_DIR_SET, val)
-#define bfin_read_PORTD_DIR_CLEAR() bfin_read16(PORTD_DIR_CLEAR)
-#define bfin_write_PORTD_DIR_CLEAR(val) bfin_write16(PORTD_DIR_CLEAR, val)
-#define bfin_read_PORTD_INEN() bfin_read16(PORTD_INEN)
-#define bfin_write_PORTD_INEN(val) bfin_write16(PORTD_INEN, val)
-#define bfin_read_PORTD_MUX() bfin_read32(PORTD_MUX)
-#define bfin_write_PORTD_MUX(val) bfin_write32(PORTD_MUX, val)
-
-/* Port E Registers */
-
-#define bfin_read_PORTE_FER() bfin_read16(PORTE_FER)
-#define bfin_write_PORTE_FER(val) bfin_write16(PORTE_FER, val)
-#define bfin_read_PORTE() bfin_read16(PORTE)
-#define bfin_write_PORTE(val) bfin_write16(PORTE, val)
-#define bfin_read_PORTE_SET() bfin_read16(PORTE_SET)
-#define bfin_write_PORTE_SET(val) bfin_write16(PORTE_SET, val)
-#define bfin_read_PORTE_CLEAR() bfin_read16(PORTE_CLEAR)
-#define bfin_write_PORTE_CLEAR(val) bfin_write16(PORTE_CLEAR, val)
-#define bfin_read_PORTE_DIR_SET() bfin_read16(PORTE_DIR_SET)
-#define bfin_write_PORTE_DIR_SET(val) bfin_write16(PORTE_DIR_SET, val)
-#define bfin_read_PORTE_DIR_CLEAR() bfin_read16(PORTE_DIR_CLEAR)
-#define bfin_write_PORTE_DIR_CLEAR(val) bfin_write16(PORTE_DIR_CLEAR, val)
-#define bfin_read_PORTE_INEN() bfin_read16(PORTE_INEN)
-#define bfin_write_PORTE_INEN(val) bfin_write16(PORTE_INEN, val)
-#define bfin_read_PORTE_MUX() bfin_read32(PORTE_MUX)
-#define bfin_write_PORTE_MUX(val) bfin_write32(PORTE_MUX, val)
-
-/* Port F Registers */
-
-#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER)
-#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val)
-#define bfin_read_PORTF() bfin_read16(PORTF)
-#define bfin_write_PORTF(val) bfin_write16(PORTF, val)
-#define bfin_read_PORTF_SET() bfin_read16(PORTF_SET)
-#define bfin_write_PORTF_SET(val) bfin_write16(PORTF_SET, val)
-#define bfin_read_PORTF_CLEAR() bfin_read16(PORTF_CLEAR)
-#define bfin_write_PORTF_CLEAR(val) bfin_write16(PORTF_CLEAR, val)
-#define bfin_read_PORTF_DIR_SET() bfin_read16(PORTF_DIR_SET)
-#define bfin_write_PORTF_DIR_SET(val) bfin_write16(PORTF_DIR_SET, val)
-#define bfin_read_PORTF_DIR_CLEAR() bfin_read16(PORTF_DIR_CLEAR)
-#define bfin_write_PORTF_DIR_CLEAR(val) bfin_write16(PORTF_DIR_CLEAR, val)
-#define bfin_read_PORTF_INEN() bfin_read16(PORTF_INEN)
-#define bfin_write_PORTF_INEN(val) bfin_write16(PORTF_INEN, val)
-#define bfin_read_PORTF_MUX() bfin_read32(PORTF_MUX)
-#define bfin_write_PORTF_MUX(val) bfin_write32(PORTF_MUX, val)
-
-/* Port G Registers */
-
-#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER)
-#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val)
-#define bfin_read_PORTG() bfin_read16(PORTG)
-#define bfin_write_PORTG(val) bfin_write16(PORTG, val)
-#define bfin_read_PORTG_SET() bfin_read16(PORTG_SET)
-#define bfin_write_PORTG_SET(val) bfin_write16(PORTG_SET, val)
-#define bfin_read_PORTG_CLEAR() bfin_read16(PORTG_CLEAR)
-#define bfin_write_PORTG_CLEAR(val) bfin_write16(PORTG_CLEAR, val)
-#define bfin_read_PORTG_DIR_SET() bfin_read16(PORTG_DIR_SET)
-#define bfin_write_PORTG_DIR_SET(val) bfin_write16(PORTG_DIR_SET, val)
-#define bfin_read_PORTG_DIR_CLEAR() bfin_read16(PORTG_DIR_CLEAR)
-#define bfin_write_PORTG_DIR_CLEAR(val) bfin_write16(PORTG_DIR_CLEAR, val)
-#define bfin_read_PORTG_INEN() bfin_read16(PORTG_INEN)
-#define bfin_write_PORTG_INEN(val) bfin_write16(PORTG_INEN, val)
-#define bfin_read_PORTG_MUX() bfin_read32(PORTG_MUX)
-#define bfin_write_PORTG_MUX(val) bfin_write32(PORTG_MUX, val)
-
-/* Port H Registers */
-
-#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER)
-#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val)
-#define bfin_read_PORTH() bfin_read16(PORTH)
-#define bfin_write_PORTH(val) bfin_write16(PORTH, val)
-#define bfin_read_PORTH_SET() bfin_read16(PORTH_SET)
-#define bfin_write_PORTH_SET(val) bfin_write16(PORTH_SET, val)
-#define bfin_read_PORTH_CLEAR() bfin_read16(PORTH_CLEAR)
-#define bfin_write_PORTH_CLEAR(val) bfin_write16(PORTH_CLEAR, val)
-#define bfin_read_PORTH_DIR_SET() bfin_read16(PORTH_DIR_SET)
-#define bfin_write_PORTH_DIR_SET(val) bfin_write16(PORTH_DIR_SET, val)
-#define bfin_read_PORTH_DIR_CLEAR() bfin_read16(PORTH_DIR_CLEAR)
-#define bfin_write_PORTH_DIR_CLEAR(val) bfin_write16(PORTH_DIR_CLEAR, val)
-#define bfin_read_PORTH_INEN() bfin_read16(PORTH_INEN)
-#define bfin_write_PORTH_INEN(val) bfin_write16(PORTH_INEN, val)
-#define bfin_read_PORTH_MUX() bfin_read32(PORTH_MUX)
-#define bfin_write_PORTH_MUX(val) bfin_write32(PORTH_MUX, val)
-
-/* Port I Registers */
-
-#define bfin_read_PORTI_FER() bfin_read16(PORTI_FER)
-#define bfin_write_PORTI_FER(val) bfin_write16(PORTI_FER, val)
-#define bfin_read_PORTI() bfin_read16(PORTI)
-#define bfin_write_PORTI(val) bfin_write16(PORTI, val)
-#define bfin_read_PORTI_SET() bfin_read16(PORTI_SET)
-#define bfin_write_PORTI_SET(val) bfin_write16(PORTI_SET, val)
-#define bfin_read_PORTI_CLEAR() bfin_read16(PORTI_CLEAR)
-#define bfin_write_PORTI_CLEAR(val) bfin_write16(PORTI_CLEAR, val)
-#define bfin_read_PORTI_DIR_SET() bfin_read16(PORTI_DIR_SET)
-#define bfin_write_PORTI_DIR_SET(val) bfin_write16(PORTI_DIR_SET, val)
-#define bfin_read_PORTI_DIR_CLEAR() bfin_read16(PORTI_DIR_CLEAR)
-#define bfin_write_PORTI_DIR_CLEAR(val) bfin_write16(PORTI_DIR_CLEAR, val)
-#define bfin_read_PORTI_INEN() bfin_read16(PORTI_INEN)
-#define bfin_write_PORTI_INEN(val) bfin_write16(PORTI_INEN, val)
-#define bfin_read_PORTI_MUX() bfin_read32(PORTI_MUX)
-#define bfin_write_PORTI_MUX(val) bfin_write32(PORTI_MUX, val)
-
-/* Port J Registers */
-
-#define bfin_read_PORTJ_FER() bfin_read16(PORTJ_FER)
-#define bfin_write_PORTJ_FER(val) bfin_write16(PORTJ_FER, val)
-#define bfin_read_PORTJ() bfin_read16(PORTJ)
-#define bfin_write_PORTJ(val) bfin_write16(PORTJ, val)
-#define bfin_read_PORTJ_SET() bfin_read16(PORTJ_SET)
-#define bfin_write_PORTJ_SET(val) bfin_write16(PORTJ_SET, val)
-#define bfin_read_PORTJ_CLEAR() bfin_read16(PORTJ_CLEAR)
-#define bfin_write_PORTJ_CLEAR(val) bfin_write16(PORTJ_CLEAR, val)
-#define bfin_read_PORTJ_DIR_SET() bfin_read16(PORTJ_DIR_SET)
-#define bfin_write_PORTJ_DIR_SET(val) bfin_write16(PORTJ_DIR_SET, val)
-#define bfin_read_PORTJ_DIR_CLEAR() bfin_read16(PORTJ_DIR_CLEAR)
-#define bfin_write_PORTJ_DIR_CLEAR(val) bfin_write16(PORTJ_DIR_CLEAR, val)
-#define bfin_read_PORTJ_INEN() bfin_read16(PORTJ_INEN)
-#define bfin_write_PORTJ_INEN(val) bfin_write16(PORTJ_INEN, val)
-#define bfin_read_PORTJ_MUX() bfin_read32(PORTJ_MUX)
-#define bfin_write_PORTJ_MUX(val) bfin_write32(PORTJ_MUX, val)
-
-/* PWM Timer Registers */
-
-#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
-#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
-#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
-#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
-#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
-#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
-#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
-#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
-#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
-#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
-#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val)
-#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
-#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
-#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
-#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val)
-#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
-#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val)
-#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
-#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val)
-#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
-#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
-#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
-#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val)
-#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
-#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val)
-#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
-#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val)
-#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
-#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
-#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
-#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val)
-#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
-#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val)
-#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
-#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val)
-#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
-#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
-#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
-#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val)
-#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
-#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val)
-#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
-#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val)
-#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
-#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
-#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
-#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val)
-#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
-#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val)
-
-/* Timer Groubfin_read_() of 8 */
-
-#define bfin_read_TIMER_ENABLE0() bfin_read16(TIMER_ENABLE0)
-#define bfin_write_TIMER_ENABLE0(val) bfin_write16(TIMER_ENABLE0, val)
-#define bfin_read_TIMER_DISABLE0() bfin_read16(TIMER_DISABLE0)
-#define bfin_write_TIMER_DISABLE0(val) bfin_write16(TIMER_DISABLE0, val)
-#define bfin_read_TIMER_STATUS0() bfin_read32(TIMER_STATUS0)
-#define bfin_write_TIMER_STATUS0(val) bfin_write32(TIMER_STATUS0, val)
-
-/* DMAC1 Registers */
-
-#define bfin_read_DMAC1_TC_PER() bfin_read16(DMAC1_TC_PER)
-#define bfin_write_DMAC1_TC_PER(val) bfin_write16(DMAC1_TC_PER, val)
-#define bfin_read_DMAC1_TC_CNT() bfin_read16(DMAC1_TC_CNT)
-#define bfin_write_DMAC1_TC_CNT(val) bfin_write16(DMAC1_TC_CNT, val)
-
-/* DMA Channel 12 Registers */
-
-#define bfin_read_DMA12_NEXT_DESC_PTR() bfin_read32(DMA12_NEXT_DESC_PTR)
-#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_write32(DMA12_NEXT_DESC_PTR, val)
-#define bfin_read_DMA12_START_ADDR() bfin_read32(DMA12_START_ADDR)
-#define bfin_write_DMA12_START_ADDR(val) bfin_write32(DMA12_START_ADDR, val)
-#define bfin_read_DMA12_CONFIG() bfin_read16(DMA12_CONFIG)
-#define bfin_write_DMA12_CONFIG(val) bfin_write16(DMA12_CONFIG, val)
-#define bfin_read_DMA12_X_COUNT() bfin_read16(DMA12_X_COUNT)
-#define bfin_write_DMA12_X_COUNT(val) bfin_write16(DMA12_X_COUNT, val)
-#define bfin_read_DMA12_X_MODIFY() bfin_read16(DMA12_X_MODIFY)
-#define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val)
-#define bfin_read_DMA12_Y_COUNT() bfin_read16(DMA12_Y_COUNT)
-#define bfin_write_DMA12_Y_COUNT(val) bfin_write16(DMA12_Y_COUNT, val)
-#define bfin_read_DMA12_Y_MODIFY() bfin_read16(DMA12_Y_MODIFY)
-#define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val)
-#define bfin_read_DMA12_CURR_DESC_PTR() bfin_read32(DMA12_CURR_DESC_PTR)
-#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_write32(DMA12_CURR_DESC_PTR, val)
-#define bfin_read_DMA12_CURR_ADDR() bfin_read32(DMA12_CURR_ADDR)
-#define bfin_write_DMA12_CURR_ADDR(val) bfin_write32(DMA12_CURR_ADDR, val)
-#define bfin_read_DMA12_IRQ_STATUS() bfin_read16(DMA12_IRQ_STATUS)
-#define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val)
-#define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP)
-#define bfin_write_DMA12_PERIPHERAL_MAP(val) bfin_write16(DMA12_PERIPHERAL_MAP, val)
-#define bfin_read_DMA12_CURR_X_COUNT() bfin_read16(DMA12_CURR_X_COUNT)
-#define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write16(DMA12_CURR_X_COUNT, val)
-#define bfin_read_DMA12_CURR_Y_COUNT() bfin_read16(DMA12_CURR_Y_COUNT)
-#define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write16(DMA12_CURR_Y_COUNT, val)
-
-/* DMA Channel 13 Registers */
-
-#define bfin_read_DMA13_NEXT_DESC_PTR() bfin_read32(DMA13_NEXT_DESC_PTR)
-#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_write32(DMA13_NEXT_DESC_PTR, val)
-#define bfin_read_DMA13_START_ADDR() bfin_read32(DMA13_START_ADDR)
-#define bfin_write_DMA13_START_ADDR(val) bfin_write32(DMA13_START_ADDR, val)
-#define bfin_read_DMA13_CONFIG() bfin_read16(DMA13_CONFIG)
-#define bfin_write_DMA13_CONFIG(val) bfin_write16(DMA13_CONFIG, val)
-#define bfin_read_DMA13_X_COUNT() bfin_read16(DMA13_X_COUNT)
-#define bfin_write_DMA13_X_COUNT(val) bfin_write16(DMA13_X_COUNT, val)
-#define bfin_read_DMA13_X_MODIFY() bfin_read16(DMA13_X_MODIFY)
-#define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val)
-#define bfin_read_DMA13_Y_COUNT() bfin_read16(DMA13_Y_COUNT)
-#define bfin_write_DMA13_Y_COUNT(val) bfin_write16(DMA13_Y_COUNT, val)
-#define bfin_read_DMA13_Y_MODIFY() bfin_read16(DMA13_Y_MODIFY)
-#define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val)
-#define bfin_read_DMA13_CURR_DESC_PTR() bfin_read32(DMA13_CURR_DESC_PTR)
-#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_write32(DMA13_CURR_DESC_PTR, val)
-#define bfin_read_DMA13_CURR_ADDR() bfin_read32(DMA13_CURR_ADDR)
-#define bfin_write_DMA13_CURR_ADDR(val) bfin_write32(DMA13_CURR_ADDR, val)
-#define bfin_read_DMA13_IRQ_STATUS() bfin_read16(DMA13_IRQ_STATUS)
-#define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val)
-#define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP)
-#define bfin_write_DMA13_PERIPHERAL_MAP(val) bfin_write16(DMA13_PERIPHERAL_MAP, val)
-#define bfin_read_DMA13_CURR_X_COUNT() bfin_read16(DMA13_CURR_X_COUNT)
-#define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write16(DMA13_CURR_X_COUNT, val)
-#define bfin_read_DMA13_CURR_Y_COUNT() bfin_read16(DMA13_CURR_Y_COUNT)
-#define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write16(DMA13_CURR_Y_COUNT, val)
-
-/* DMA Channel 14 Registers */
-
-#define bfin_read_DMA14_NEXT_DESC_PTR() bfin_read32(DMA14_NEXT_DESC_PTR)
-#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_write32(DMA14_NEXT_DESC_PTR, val)
-#define bfin_read_DMA14_START_ADDR() bfin_read32(DMA14_START_ADDR)
-#define bfin_write_DMA14_START_ADDR(val) bfin_write32(DMA14_START_ADDR, val)
-#define bfin_read_DMA14_CONFIG() bfin_read16(DMA14_CONFIG)
-#define bfin_write_DMA14_CONFIG(val) bfin_write16(DMA14_CONFIG, val)
-#define bfin_read_DMA14_X_COUNT() bfin_read16(DMA14_X_COUNT)
-#define bfin_write_DMA14_X_COUNT(val) bfin_write16(DMA14_X_COUNT, val)
-#define bfin_read_DMA14_X_MODIFY() bfin_read16(DMA14_X_MODIFY)
-#define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val)
-#define bfin_read_DMA14_Y_COUNT() bfin_read16(DMA14_Y_COUNT)
-#define bfin_write_DMA14_Y_COUNT(val) bfin_write16(DMA14_Y_COUNT, val)
-#define bfin_read_DMA14_Y_MODIFY() bfin_read16(DMA14_Y_MODIFY)
-#define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val)
-#define bfin_read_DMA14_CURR_DESC_PTR() bfin_read32(DMA14_CURR_DESC_PTR)
-#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_write32(DMA14_CURR_DESC_PTR, val)
-#define bfin_read_DMA14_CURR_ADDR() bfin_read32(DMA14_CURR_ADDR)
-#define bfin_write_DMA14_CURR_ADDR(val) bfin_write32(DMA14_CURR_ADDR, val)
-#define bfin_read_DMA14_IRQ_STATUS() bfin_read16(DMA14_IRQ_STATUS)
-#define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val)
-#define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP)
-#define bfin_write_DMA14_PERIPHERAL_MAP(val) bfin_write16(DMA14_PERIPHERAL_MAP, val)
-#define bfin_read_DMA14_CURR_X_COUNT() bfin_read16(DMA14_CURR_X_COUNT)
-#define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write16(DMA14_CURR_X_COUNT, val)
-#define bfin_read_DMA14_CURR_Y_COUNT() bfin_read16(DMA14_CURR_Y_COUNT)
-#define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write16(DMA14_CURR_Y_COUNT, val)
-
-/* DMA Channel 15 Registers */
-
-#define bfin_read_DMA15_NEXT_DESC_PTR() bfin_read32(DMA15_NEXT_DESC_PTR)
-#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_write32(DMA15_NEXT_DESC_PTR, val)
-#define bfin_read_DMA15_START_ADDR() bfin_read32(DMA15_START_ADDR)
-#define bfin_write_DMA15_START_ADDR(val) bfin_write32(DMA15_START_ADDR, val)
-#define bfin_read_DMA15_CONFIG() bfin_read16(DMA15_CONFIG)
-#define bfin_write_DMA15_CONFIG(val) bfin_write16(DMA15_CONFIG, val)
-#define bfin_read_DMA15_X_COUNT() bfin_read16(DMA15_X_COUNT)
-#define bfin_write_DMA15_X_COUNT(val) bfin_write16(DMA15_X_COUNT, val)
-#define bfin_read_DMA15_X_MODIFY() bfin_read16(DMA15_X_MODIFY)
-#define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val)
-#define bfin_read_DMA15_Y_COUNT() bfin_read16(DMA15_Y_COUNT)
-#define bfin_write_DMA15_Y_COUNT(val) bfin_write16(DMA15_Y_COUNT, val)
-#define bfin_read_DMA15_Y_MODIFY() bfin_read16(DMA15_Y_MODIFY)
-#define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val)
-#define bfin_read_DMA15_CURR_DESC_PTR() bfin_read32(DMA15_CURR_DESC_PTR)
-#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_write32(DMA15_CURR_DESC_PTR, val)
-#define bfin_read_DMA15_CURR_ADDR() bfin_read32(DMA15_CURR_ADDR)
-#define bfin_write_DMA15_CURR_ADDR(val) bfin_write32(DMA15_CURR_ADDR, val)
-#define bfin_read_DMA15_IRQ_STATUS() bfin_read16(DMA15_IRQ_STATUS)
-#define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val)
-#define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP)
-#define bfin_write_DMA15_PERIPHERAL_MAP(val) bfin_write16(DMA15_PERIPHERAL_MAP, val)
-#define bfin_read_DMA15_CURR_X_COUNT() bfin_read16(DMA15_CURR_X_COUNT)
-#define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write16(DMA15_CURR_X_COUNT, val)
-#define bfin_read_DMA15_CURR_Y_COUNT() bfin_read16(DMA15_CURR_Y_COUNT)
-#define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write16(DMA15_CURR_Y_COUNT, val)
-
-/* DMA Channel 16 Registers */
-
-#define bfin_read_DMA16_NEXT_DESC_PTR() bfin_read32(DMA16_NEXT_DESC_PTR)
-#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_write32(DMA16_NEXT_DESC_PTR, val)
-#define bfin_read_DMA16_START_ADDR() bfin_read32(DMA16_START_ADDR)
-#define bfin_write_DMA16_START_ADDR(val) bfin_write32(DMA16_START_ADDR, val)
-#define bfin_read_DMA16_CONFIG() bfin_read16(DMA16_CONFIG)
-#define bfin_write_DMA16_CONFIG(val) bfin_write16(DMA16_CONFIG, val)
-#define bfin_read_DMA16_X_COUNT() bfin_read16(DMA16_X_COUNT)
-#define bfin_write_DMA16_X_COUNT(val) bfin_write16(DMA16_X_COUNT, val)
-#define bfin_read_DMA16_X_MODIFY() bfin_read16(DMA16_X_MODIFY)
-#define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val)
-#define bfin_read_DMA16_Y_COUNT() bfin_read16(DMA16_Y_COUNT)
-#define bfin_write_DMA16_Y_COUNT(val) bfin_write16(DMA16_Y_COUNT, val)
-#define bfin_read_DMA16_Y_MODIFY() bfin_read16(DMA16_Y_MODIFY)
-#define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val)
-#define bfin_read_DMA16_CURR_DESC_PTR() bfin_read32(DMA16_CURR_DESC_PTR)
-#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_write32(DMA16_CURR_DESC_PTR, val)
-#define bfin_read_DMA16_CURR_ADDR() bfin_read32(DMA16_CURR_ADDR)
-#define bfin_write_DMA16_CURR_ADDR(val) bfin_write32(DMA16_CURR_ADDR, val)
-#define bfin_read_DMA16_IRQ_STATUS() bfin_read16(DMA16_IRQ_STATUS)
-#define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val)
-#define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP)
-#define bfin_write_DMA16_PERIPHERAL_MAP(val) bfin_write16(DMA16_PERIPHERAL_MAP, val)
-#define bfin_read_DMA16_CURR_X_COUNT() bfin_read16(DMA16_CURR_X_COUNT)
-#define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write16(DMA16_CURR_X_COUNT, val)
-#define bfin_read_DMA16_CURR_Y_COUNT() bfin_read16(DMA16_CURR_Y_COUNT)
-#define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write16(DMA16_CURR_Y_COUNT, val)
-
-/* DMA Channel 17 Registers */
-
-#define bfin_read_DMA17_NEXT_DESC_PTR() bfin_read32(DMA17_NEXT_DESC_PTR)
-#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_write32(DMA17_NEXT_DESC_PTR, val)
-#define bfin_read_DMA17_START_ADDR() bfin_read32(DMA17_START_ADDR)
-#define bfin_write_DMA17_START_ADDR(val) bfin_write32(DMA17_START_ADDR, val)
-#define bfin_read_DMA17_CONFIG() bfin_read16(DMA17_CONFIG)
-#define bfin_write_DMA17_CONFIG(val) bfin_write16(DMA17_CONFIG, val)
-#define bfin_read_DMA17_X_COUNT() bfin_read16(DMA17_X_COUNT)
-#define bfin_write_DMA17_X_COUNT(val) bfin_write16(DMA17_X_COUNT, val)
-#define bfin_read_DMA17_X_MODIFY() bfin_read16(DMA17_X_MODIFY)
-#define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val)
-#define bfin_read_DMA17_Y_COUNT() bfin_read16(DMA17_Y_COUNT)
-#define bfin_write_DMA17_Y_COUNT(val) bfin_write16(DMA17_Y_COUNT, val)
-#define bfin_read_DMA17_Y_MODIFY() bfin_read16(DMA17_Y_MODIFY)
-#define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val)
-#define bfin_read_DMA17_CURR_DESC_PTR() bfin_read32(DMA17_CURR_DESC_PTR)
-#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_write32(DMA17_CURR_DESC_PTR, val)
-#define bfin_read_DMA17_CURR_ADDR() bfin_read32(DMA17_CURR_ADDR)
-#define bfin_write_DMA17_CURR_ADDR(val) bfin_write32(DMA17_CURR_ADDR, val)
-#define bfin_read_DMA17_IRQ_STATUS() bfin_read16(DMA17_IRQ_STATUS)
-#define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val)
-#define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP)
-#define bfin_write_DMA17_PERIPHERAL_MAP(val) bfin_write16(DMA17_PERIPHERAL_MAP, val)
-#define bfin_read_DMA17_CURR_X_COUNT() bfin_read16(DMA17_CURR_X_COUNT)
-#define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write16(DMA17_CURR_X_COUNT, val)
-#define bfin_read_DMA17_CURR_Y_COUNT() bfin_read16(DMA17_CURR_Y_COUNT)
-#define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write16(DMA17_CURR_Y_COUNT, val)
-
-/* DMA Channel 18 Registers */
-
-#define bfin_read_DMA18_NEXT_DESC_PTR() bfin_read32(DMA18_NEXT_DESC_PTR)
-#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_write32(DMA18_NEXT_DESC_PTR, val)
-#define bfin_read_DMA18_START_ADDR() bfin_read32(DMA18_START_ADDR)
-#define bfin_write_DMA18_START_ADDR(val) bfin_write32(DMA18_START_ADDR, val)
-#define bfin_read_DMA18_CONFIG() bfin_read16(DMA18_CONFIG)
-#define bfin_write_DMA18_CONFIG(val) bfin_write16(DMA18_CONFIG, val)
-#define bfin_read_DMA18_X_COUNT() bfin_read16(DMA18_X_COUNT)
-#define bfin_write_DMA18_X_COUNT(val) bfin_write16(DMA18_X_COUNT, val)
-#define bfin_read_DMA18_X_MODIFY() bfin_read16(DMA18_X_MODIFY)
-#define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val)
-#define bfin_read_DMA18_Y_COUNT() bfin_read16(DMA18_Y_COUNT)
-#define bfin_write_DMA18_Y_COUNT(val) bfin_write16(DMA18_Y_COUNT, val)
-#define bfin_read_DMA18_Y_MODIFY() bfin_read16(DMA18_Y_MODIFY)
-#define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val)
-#define bfin_read_DMA18_CURR_DESC_PTR() bfin_read32(DMA18_CURR_DESC_PTR)
-#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_write32(DMA18_CURR_DESC_PTR, val)
-#define bfin_read_DMA18_CURR_ADDR() bfin_read32(DMA18_CURR_ADDR)
-#define bfin_write_DMA18_CURR_ADDR(val) bfin_write32(DMA18_CURR_ADDR, val)
-#define bfin_read_DMA18_IRQ_STATUS() bfin_read16(DMA18_IRQ_STATUS)
-#define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val)
-#define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP)
-#define bfin_write_DMA18_PERIPHERAL_MAP(val) bfin_write16(DMA18_PERIPHERAL_MAP, val)
-#define bfin_read_DMA18_CURR_X_COUNT() bfin_read16(DMA18_CURR_X_COUNT)
-#define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write16(DMA18_CURR_X_COUNT, val)
-#define bfin_read_DMA18_CURR_Y_COUNT() bfin_read16(DMA18_CURR_Y_COUNT)
-#define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write16(DMA18_CURR_Y_COUNT, val)
-
-/* DMA Channel 19 Registers */
-
-#define bfin_read_DMA19_NEXT_DESC_PTR() bfin_read32(DMA19_NEXT_DESC_PTR)
-#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_write32(DMA19_NEXT_DESC_PTR, val)
-#define bfin_read_DMA19_START_ADDR() bfin_read32(DMA19_START_ADDR)
-#define bfin_write_DMA19_START_ADDR(val) bfin_write32(DMA19_START_ADDR, val)
-#define bfin_read_DMA19_CONFIG() bfin_read16(DMA19_CONFIG)
-#define bfin_write_DMA19_CONFIG(val) bfin_write16(DMA19_CONFIG, val)
-#define bfin_read_DMA19_X_COUNT() bfin_read16(DMA19_X_COUNT)
-#define bfin_write_DMA19_X_COUNT(val) bfin_write16(DMA19_X_COUNT, val)
-#define bfin_read_DMA19_X_MODIFY() bfin_read16(DMA19_X_MODIFY)
-#define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val)
-#define bfin_read_DMA19_Y_COUNT() bfin_read16(DMA19_Y_COUNT)
-#define bfin_write_DMA19_Y_COUNT(val) bfin_write16(DMA19_Y_COUNT, val)
-#define bfin_read_DMA19_Y_MODIFY() bfin_read16(DMA19_Y_MODIFY)
-#define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val)
-#define bfin_read_DMA19_CURR_DESC_PTR() bfin_read32(DMA19_CURR_DESC_PTR)
-#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_write32(DMA19_CURR_DESC_PTR, val)
-#define bfin_read_DMA19_CURR_ADDR() bfin_read32(DMA19_CURR_ADDR)
-#define bfin_write_DMA19_CURR_ADDR(val) bfin_write32(DMA19_CURR_ADDR, val)
-#define bfin_read_DMA19_IRQ_STATUS() bfin_read16(DMA19_IRQ_STATUS)
-#define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val)
-#define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP)
-#define bfin_write_DMA19_PERIPHERAL_MAP(val) bfin_write16(DMA19_PERIPHERAL_MAP, val)
-#define bfin_read_DMA19_CURR_X_COUNT() bfin_read16(DMA19_CURR_X_COUNT)
-#define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val)
-#define bfin_read_DMA19_CURR_Y_COUNT() bfin_read16(DMA19_CURR_Y_COUNT)
-#define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val)
-
-/* DMA Channel 20 Registers */
-
-#define bfin_read_DMA20_NEXT_DESC_PTR() bfin_read32(DMA20_NEXT_DESC_PTR)
-#define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_write32(DMA20_NEXT_DESC_PTR, val)
-#define bfin_read_DMA20_START_ADDR() bfin_read32(DMA20_START_ADDR)
-#define bfin_write_DMA20_START_ADDR(val) bfin_write32(DMA20_START_ADDR, val)
-#define bfin_read_DMA20_CONFIG() bfin_read16(DMA20_CONFIG)
-#define bfin_write_DMA20_CONFIG(val) bfin_write16(DMA20_CONFIG, val)
-#define bfin_read_DMA20_X_COUNT() bfin_read16(DMA20_X_COUNT)
-#define bfin_write_DMA20_X_COUNT(val) bfin_write16(DMA20_X_COUNT, val)
-#define bfin_read_DMA20_X_MODIFY() bfin_read16(DMA20_X_MODIFY)
-#define bfin_write_DMA20_X_MODIFY(val) bfin_write16(DMA20_X_MODIFY, val)
-#define bfin_read_DMA20_Y_COUNT() bfin_read16(DMA20_Y_COUNT)
-#define bfin_write_DMA20_Y_COUNT(val) bfin_write16(DMA20_Y_COUNT, val)
-#define bfin_read_DMA20_Y_MODIFY() bfin_read16(DMA20_Y_MODIFY)
-#define bfin_write_DMA20_Y_MODIFY(val) bfin_write16(DMA20_Y_MODIFY, val)
-#define bfin_read_DMA20_CURR_DESC_PTR() bfin_read32(DMA20_CURR_DESC_PTR)
-#define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_write32(DMA20_CURR_DESC_PTR, val)
-#define bfin_read_DMA20_CURR_ADDR() bfin_read32(DMA20_CURR_ADDR)
-#define bfin_write_DMA20_CURR_ADDR(val) bfin_write32(DMA20_CURR_ADDR, val)
-#define bfin_read_DMA20_IRQ_STATUS() bfin_read16(DMA20_IRQ_STATUS)
-#define bfin_write_DMA20_IRQ_STATUS(val) bfin_write16(DMA20_IRQ_STATUS, val)
-#define bfin_read_DMA20_PERIPHERAL_MAP() bfin_read16(DMA20_PERIPHERAL_MAP)
-#define bfin_write_DMA20_PERIPHERAL_MAP(val) bfin_write16(DMA20_PERIPHERAL_MAP, val)
-#define bfin_read_DMA20_CURR_X_COUNT() bfin_read16(DMA20_CURR_X_COUNT)
-#define bfin_write_DMA20_CURR_X_COUNT(val) bfin_write16(DMA20_CURR_X_COUNT, val)
-#define bfin_read_DMA20_CURR_Y_COUNT() bfin_read16(DMA20_CURR_Y_COUNT)
-#define bfin_write_DMA20_CURR_Y_COUNT(val) bfin_write16(DMA20_CURR_Y_COUNT, val)
-
-/* DMA Channel 21 Registers */
-
-#define bfin_read_DMA21_NEXT_DESC_PTR() bfin_read32(DMA21_NEXT_DESC_PTR)
-#define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_write32(DMA21_NEXT_DESC_PTR, val)
-#define bfin_read_DMA21_START_ADDR() bfin_read32(DMA21_START_ADDR)
-#define bfin_write_DMA21_START_ADDR(val) bfin_write32(DMA21_START_ADDR, val)
-#define bfin_read_DMA21_CONFIG() bfin_read16(DMA21_CONFIG)
-#define bfin_write_DMA21_CONFIG(val) bfin_write16(DMA21_CONFIG, val)
-#define bfin_read_DMA21_X_COUNT() bfin_read16(DMA21_X_COUNT)
-#define bfin_write_DMA21_X_COUNT(val) bfin_write16(DMA21_X_COUNT, val)
-#define bfin_read_DMA21_X_MODIFY() bfin_read16(DMA21_X_MODIFY)
-#define bfin_write_DMA21_X_MODIFY(val) bfin_write16(DMA21_X_MODIFY, val)
-#define bfin_read_DMA21_Y_COUNT() bfin_read16(DMA21_Y_COUNT)
-#define bfin_write_DMA21_Y_COUNT(val) bfin_write16(DMA21_Y_COUNT, val)
-#define bfin_read_DMA21_Y_MODIFY() bfin_read16(DMA21_Y_MODIFY)
-#define bfin_write_DMA21_Y_MODIFY(val) bfin_write16(DMA21_Y_MODIFY, val)
-#define bfin_read_DMA21_CURR_DESC_PTR() bfin_read32(DMA21_CURR_DESC_PTR)
-#define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_write32(DMA21_CURR_DESC_PTR, val)
-#define bfin_read_DMA21_CURR_ADDR() bfin_read32(DMA21_CURR_ADDR)
-#define bfin_write_DMA21_CURR_ADDR(val) bfin_write32(DMA21_CURR_ADDR, val)
-#define bfin_read_DMA21_IRQ_STATUS() bfin_read16(DMA21_IRQ_STATUS)
-#define bfin_write_DMA21_IRQ_STATUS(val) bfin_write16(DMA21_IRQ_STATUS, val)
-#define bfin_read_DMA21_PERIPHERAL_MAP() bfin_read16(DMA21_PERIPHERAL_MAP)
-#define bfin_write_DMA21_PERIPHERAL_MAP(val) bfin_write16(DMA21_PERIPHERAL_MAP, val)
-#define bfin_read_DMA21_CURR_X_COUNT() bfin_read16(DMA21_CURR_X_COUNT)
-#define bfin_write_DMA21_CURR_X_COUNT(val) bfin_write16(DMA21_CURR_X_COUNT, val)
-#define bfin_read_DMA21_CURR_Y_COUNT() bfin_read16(DMA21_CURR_Y_COUNT)
-#define bfin_write_DMA21_CURR_Y_COUNT(val) bfin_write16(DMA21_CURR_Y_COUNT, val)
-
-/* DMA Channel 22 Registers */
-
-#define bfin_read_DMA22_NEXT_DESC_PTR() bfin_read32(DMA22_NEXT_DESC_PTR)
-#define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_write32(DMA22_NEXT_DESC_PTR, val)
-#define bfin_read_DMA22_START_ADDR() bfin_read32(DMA22_START_ADDR)
-#define bfin_write_DMA22_START_ADDR(val) bfin_write32(DMA22_START_ADDR, val)
-#define bfin_read_DMA22_CONFIG() bfin_read16(DMA22_CONFIG)
-#define bfin_write_DMA22_CONFIG(val) bfin_write16(DMA22_CONFIG, val)
-#define bfin_read_DMA22_X_COUNT() bfin_read16(DMA22_X_COUNT)
-#define bfin_write_DMA22_X_COUNT(val) bfin_write16(DMA22_X_COUNT, val)
-#define bfin_read_DMA22_X_MODIFY() bfin_read16(DMA22_X_MODIFY)
-#define bfin_write_DMA22_X_MODIFY(val) bfin_write16(DMA22_X_MODIFY, val)
-#define bfin_read_DMA22_Y_COUNT() bfin_read16(DMA22_Y_COUNT)
-#define bfin_write_DMA22_Y_COUNT(val) bfin_write16(DMA22_Y_COUNT, val)
-#define bfin_read_DMA22_Y_MODIFY() bfin_read16(DMA22_Y_MODIFY)
-#define bfin_write_DMA22_Y_MODIFY(val) bfin_write16(DMA22_Y_MODIFY, val)
-#define bfin_read_DMA22_CURR_DESC_PTR() bfin_read32(DMA22_CURR_DESC_PTR)
-#define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_write32(DMA22_CURR_DESC_PTR, val)
-#define bfin_read_DMA22_CURR_ADDR() bfin_read32(DMA22_CURR_ADDR)
-#define bfin_write_DMA22_CURR_ADDR(val) bfin_write32(DMA22_CURR_ADDR, val)
-#define bfin_read_DMA22_IRQ_STATUS() bfin_read16(DMA22_IRQ_STATUS)
-#define bfin_write_DMA22_IRQ_STATUS(val) bfin_write16(DMA22_IRQ_STATUS, val)
-#define bfin_read_DMA22_PERIPHERAL_MAP() bfin_read16(DMA22_PERIPHERAL_MAP)
-#define bfin_write_DMA22_PERIPHERAL_MAP(val) bfin_write16(DMA22_PERIPHERAL_MAP, val)
-#define bfin_read_DMA22_CURR_X_COUNT() bfin_read16(DMA22_CURR_X_COUNT)
-#define bfin_write_DMA22_CURR_X_COUNT(val) bfin_write16(DMA22_CURR_X_COUNT, val)
-#define bfin_read_DMA22_CURR_Y_COUNT() bfin_read16(DMA22_CURR_Y_COUNT)
-#define bfin_write_DMA22_CURR_Y_COUNT(val) bfin_write16(DMA22_CURR_Y_COUNT, val)
-
-/* DMA Channel 23 Registers */
-
-#define bfin_read_DMA23_NEXT_DESC_PTR() bfin_read32(DMA23_NEXT_DESC_PTR)
-#define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_write32(DMA23_NEXT_DESC_PTR, val)
-#define bfin_read_DMA23_START_ADDR() bfin_read32(DMA23_START_ADDR)
-#define bfin_write_DMA23_START_ADDR(val) bfin_write32(DMA23_START_ADDR, val)
-#define bfin_read_DMA23_CONFIG() bfin_read16(DMA23_CONFIG)
-#define bfin_write_DMA23_CONFIG(val) bfin_write16(DMA23_CONFIG, val)
-#define bfin_read_DMA23_X_COUNT() bfin_read16(DMA23_X_COUNT)
-#define bfin_write_DMA23_X_COUNT(val) bfin_write16(DMA23_X_COUNT, val)
-#define bfin_read_DMA23_X_MODIFY() bfin_read16(DMA23_X_MODIFY)
-#define bfin_write_DMA23_X_MODIFY(val) bfin_write16(DMA23_X_MODIFY, val)
-#define bfin_read_DMA23_Y_COUNT() bfin_read16(DMA23_Y_COUNT)
-#define bfin_write_DMA23_Y_COUNT(val) bfin_write16(DMA23_Y_COUNT, val)
-#define bfin_read_DMA23_Y_MODIFY() bfin_read16(DMA23_Y_MODIFY)
-#define bfin_write_DMA23_Y_MODIFY(val) bfin_write16(DMA23_Y_MODIFY, val)
-#define bfin_read_DMA23_CURR_DESC_PTR() bfin_read32(DMA23_CURR_DESC_PTR)
-#define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_write32(DMA23_CURR_DESC_PTR, val)
-#define bfin_read_DMA23_CURR_ADDR() bfin_read32(DMA23_CURR_ADDR)
-#define bfin_write_DMA23_CURR_ADDR(val) bfin_write32(DMA23_CURR_ADDR, val)
-#define bfin_read_DMA23_IRQ_STATUS() bfin_read16(DMA23_IRQ_STATUS)
-#define bfin_write_DMA23_IRQ_STATUS(val) bfin_write16(DMA23_IRQ_STATUS, val)
-#define bfin_read_DMA23_PERIPHERAL_MAP() bfin_read16(DMA23_PERIPHERAL_MAP)
-#define bfin_write_DMA23_PERIPHERAL_MAP(val) bfin_write16(DMA23_PERIPHERAL_MAP, val)
-#define bfin_read_DMA23_CURR_X_COUNT() bfin_read16(DMA23_CURR_X_COUNT)
-#define bfin_write_DMA23_CURR_X_COUNT(val) bfin_write16(DMA23_CURR_X_COUNT, val)
-#define bfin_read_DMA23_CURR_Y_COUNT() bfin_read16(DMA23_CURR_Y_COUNT)
-#define bfin_write_DMA23_CURR_Y_COUNT(val) bfin_write16(DMA23_CURR_Y_COUNT, val)
-
-/* MDMA Stream 2 Registers */
-
-#define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_read32(MDMA_D2_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_write32(MDMA_D2_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D2_START_ADDR() bfin_read32(MDMA_D2_START_ADDR)
-#define bfin_write_MDMA_D2_START_ADDR(val) bfin_write32(MDMA_D2_START_ADDR, val)
-#define bfin_read_MDMA_D2_CONFIG() bfin_read16(MDMA_D2_CONFIG)
-#define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val)
-#define bfin_read_MDMA_D2_X_COUNT() bfin_read16(MDMA_D2_X_COUNT)
-#define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val)
-#define bfin_read_MDMA_D2_X_MODIFY() bfin_read16(MDMA_D2_X_MODIFY)
-#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY, val)
-#define bfin_read_MDMA_D2_Y_COUNT() bfin_read16(MDMA_D2_Y_COUNT)
-#define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val)
-#define bfin_read_MDMA_D2_Y_MODIFY() bfin_read16(MDMA_D2_Y_MODIFY)
-#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY, val)
-#define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_read32(MDMA_D2_CURR_DESC_PTR)
-#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_write32(MDMA_D2_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D2_CURR_ADDR() bfin_read32(MDMA_D2_CURR_ADDR)
-#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_write32(MDMA_D2_CURR_ADDR, val)
-#define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS)
-#define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val)
-#define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT)
-#define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT)
-#define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_read32(MDMA_S2_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_write32(MDMA_S2_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S2_START_ADDR() bfin_read32(MDMA_S2_START_ADDR)
-#define bfin_write_MDMA_S2_START_ADDR(val) bfin_write32(MDMA_S2_START_ADDR, val)
-#define bfin_read_MDMA_S2_CONFIG() bfin_read16(MDMA_S2_CONFIG)
-#define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val)
-#define bfin_read_MDMA_S2_X_COUNT() bfin_read16(MDMA_S2_X_COUNT)
-#define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val)
-#define bfin_read_MDMA_S2_X_MODIFY() bfin_read16(MDMA_S2_X_MODIFY)
-#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY, val)
-#define bfin_read_MDMA_S2_Y_COUNT() bfin_read16(MDMA_S2_Y_COUNT)
-#define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val)
-#define bfin_read_MDMA_S2_Y_MODIFY() bfin_read16(MDMA_S2_Y_MODIFY)
-#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY, val)
-#define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_read32(MDMA_S2_CURR_DESC_PTR)
-#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_write32(MDMA_S2_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S2_CURR_ADDR() bfin_read32(MDMA_S2_CURR_ADDR)
-#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_write32(MDMA_S2_CURR_ADDR, val)
-#define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS)
-#define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val)
-#define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT)
-#define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT)
-#define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT, val)
-
-/* MDMA Stream 3 Registers */
-
-#define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_read32(MDMA_D3_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_write32(MDMA_D3_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D3_START_ADDR() bfin_read32(MDMA_D3_START_ADDR)
-#define bfin_write_MDMA_D3_START_ADDR(val) bfin_write32(MDMA_D3_START_ADDR, val)
-#define bfin_read_MDMA_D3_CONFIG() bfin_read16(MDMA_D3_CONFIG)
-#define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val)
-#define bfin_read_MDMA_D3_X_COUNT() bfin_read16(MDMA_D3_X_COUNT)
-#define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val)
-#define bfin_read_MDMA_D3_X_MODIFY() bfin_read16(MDMA_D3_X_MODIFY)
-#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY, val)
-#define bfin_read_MDMA_D3_Y_COUNT() bfin_read16(MDMA_D3_Y_COUNT)
-#define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val)
-#define bfin_read_MDMA_D3_Y_MODIFY() bfin_read16(MDMA_D3_Y_MODIFY)
-#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY, val)
-#define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_read32(MDMA_D3_CURR_DESC_PTR)
-#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_write32(MDMA_D3_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D3_CURR_ADDR() bfin_read32(MDMA_D3_CURR_ADDR)
-#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_write32(MDMA_D3_CURR_ADDR, val)
-#define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS)
-#define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val)
-#define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT)
-#define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT)
-#define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_read32(MDMA_S3_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_write32(MDMA_S3_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S3_START_ADDR() bfin_read32(MDMA_S3_START_ADDR)
-#define bfin_write_MDMA_S3_START_ADDR(val) bfin_write32(MDMA_S3_START_ADDR, val)
-#define bfin_read_MDMA_S3_CONFIG() bfin_read16(MDMA_S3_CONFIG)
-#define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val)
-#define bfin_read_MDMA_S3_X_COUNT() bfin_read16(MDMA_S3_X_COUNT)
-#define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val)
-#define bfin_read_MDMA_S3_X_MODIFY() bfin_read16(MDMA_S3_X_MODIFY)
-#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY, val)
-#define bfin_read_MDMA_S3_Y_COUNT() bfin_read16(MDMA_S3_Y_COUNT)
-#define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val)
-#define bfin_read_MDMA_S3_Y_MODIFY() bfin_read16(MDMA_S3_Y_MODIFY)
-#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY, val)
-#define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_read32(MDMA_S3_CURR_DESC_PTR)
-#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_write32(MDMA_S3_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S3_CURR_ADDR() bfin_read32(MDMA_S3_CURR_ADDR)
-#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_write32(MDMA_S3_CURR_ADDR, val)
-#define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS)
-#define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val)
-#define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT)
-#define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT)
-#define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT, val)
-
-/* UART1 Registers */
-
-#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL)
-#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val)
-#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH)
-#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val)
-#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL)
-#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val)
-#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR)
-#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val)
-#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR)
-#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val)
-#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR)
-#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val)
-#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR)
-#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val)
-#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR)
-#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val)
-#define bfin_read_UART1_IER_SET() bfin_read16(UART1_IER_SET)
-#define bfin_write_UART1_IER_SET(val) bfin_write16(UART1_IER_SET, val)
-#define bfin_read_UART1_IER_CLEAR() bfin_read16(UART1_IER_CLEAR)
-#define bfin_write_UART1_IER_CLEAR(val) bfin_write16(UART1_IER_CLEAR, val)
-#define bfin_read_UART1_THR() bfin_read16(UART1_THR)
-#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val)
-#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR)
-#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val)
-
-/* UART2 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 bfin_read_()rocessors */
-
-/* SPI1 Registers */
-
-#define bfin_read_SPI1_CTL() bfin_read16(SPI1_CTL)
-#define bfin_write_SPI1_CTL(val) bfin_write16(SPI1_CTL, val)
-#define bfin_read_SPI1_FLG() bfin_read16(SPI1_FLG)
-#define bfin_write_SPI1_FLG(val) bfin_write16(SPI1_FLG, val)
-#define bfin_read_SPI1_STAT() bfin_read16(SPI1_STAT)
-#define bfin_write_SPI1_STAT(val) bfin_write16(SPI1_STAT, val)
-#define bfin_read_SPI1_TDBR() bfin_read16(SPI1_TDBR)
-#define bfin_write_SPI1_TDBR(val) bfin_write16(SPI1_TDBR, val)
-#define bfin_read_SPI1_RDBR() bfin_read16(SPI1_RDBR)
-#define bfin_write_SPI1_RDBR(val) bfin_write16(SPI1_RDBR, val)
-#define bfin_read_SPI1_BAUD() bfin_read16(SPI1_BAUD)
-#define bfin_write_SPI1_BAUD(val) bfin_write16(SPI1_BAUD, val)
-#define bfin_read_SPI1_SHADOW() bfin_read16(SPI1_SHADOW)
-#define bfin_write_SPI1_SHADOW(val) bfin_write16(SPI1_SHADOW, val)
-
-/* SPORT2 Registers */
-
-#define bfin_read_SPORT2_TCR1() bfin_read16(SPORT2_TCR1)
-#define bfin_write_SPORT2_TCR1(val) bfin_write16(SPORT2_TCR1, val)
-#define bfin_read_SPORT2_TCR2() bfin_read16(SPORT2_TCR2)
-#define bfin_write_SPORT2_TCR2(val) bfin_write16(SPORT2_TCR2, val)
-#define bfin_read_SPORT2_TCLKDIV() bfin_read16(SPORT2_TCLKDIV)
-#define bfin_write_SPORT2_TCLKDIV(val) bfin_write16(SPORT2_TCLKDIV, val)
-#define bfin_read_SPORT2_TFSDIV() bfin_read16(SPORT2_TFSDIV)
-#define bfin_write_SPORT2_TFSDIV(val) bfin_write16(SPORT2_TFSDIV, val)
-#define bfin_read_SPORT2_TX() bfin_read32(SPORT2_TX)
-#define bfin_write_SPORT2_TX(val) bfin_write32(SPORT2_TX, val)
-#define bfin_read_SPORT2_RX() bfin_read32(SPORT2_RX)
-#define bfin_write_SPORT2_RX(val) bfin_write32(SPORT2_RX, val)
-#define bfin_read_SPORT2_RCR1() bfin_read16(SPORT2_RCR1)
-#define bfin_write_SPORT2_RCR1(val) bfin_write16(SPORT2_RCR1, val)
-#define bfin_read_SPORT2_RCR2() bfin_read16(SPORT2_RCR2)
-#define bfin_write_SPORT2_RCR2(val) bfin_write16(SPORT2_RCR2, val)
-#define bfin_read_SPORT2_RCLKDIV() bfin_read16(SPORT2_RCLKDIV)
-#define bfin_write_SPORT2_RCLKDIV(val) bfin_write16(SPORT2_RCLKDIV, val)
-#define bfin_read_SPORT2_RFSDIV() bfin_read16(SPORT2_RFSDIV)
-#define bfin_write_SPORT2_RFSDIV(val) bfin_write16(SPORT2_RFSDIV, val)
-#define bfin_read_SPORT2_STAT() bfin_read16(SPORT2_STAT)
-#define bfin_write_SPORT2_STAT(val) bfin_write16(SPORT2_STAT, val)
-#define bfin_read_SPORT2_CHNL() bfin_read16(SPORT2_CHNL)
-#define bfin_write_SPORT2_CHNL(val) bfin_write16(SPORT2_CHNL, val)
-#define bfin_read_SPORT2_MCMC1() bfin_read16(SPORT2_MCMC1)
-#define bfin_write_SPORT2_MCMC1(val) bfin_write16(SPORT2_MCMC1, val)
-#define bfin_read_SPORT2_MCMC2() bfin_read16(SPORT2_MCMC2)
-#define bfin_write_SPORT2_MCMC2(val) bfin_write16(SPORT2_MCMC2, val)
-#define bfin_read_SPORT2_MTCS0() bfin_read32(SPORT2_MTCS0)
-#define bfin_write_SPORT2_MTCS0(val) bfin_write32(SPORT2_MTCS0, val)
-#define bfin_read_SPORT2_MTCS1() bfin_read32(SPORT2_MTCS1)
-#define bfin_write_SPORT2_MTCS1(val) bfin_write32(SPORT2_MTCS1, val)
-#define bfin_read_SPORT2_MTCS2() bfin_read32(SPORT2_MTCS2)
-#define bfin_write_SPORT2_MTCS2(val) bfin_write32(SPORT2_MTCS2, val)
-#define bfin_read_SPORT2_MTCS3() bfin_read32(SPORT2_MTCS3)
-#define bfin_write_SPORT2_MTCS3(val) bfin_write32(SPORT2_MTCS3, val)
-#define bfin_read_SPORT2_MRCS0() bfin_read32(SPORT2_MRCS0)
-#define bfin_write_SPORT2_MRCS0(val) bfin_write32(SPORT2_MRCS0, val)
-#define bfin_read_SPORT2_MRCS1() bfin_read32(SPORT2_MRCS1)
-#define bfin_write_SPORT2_MRCS1(val) bfin_write32(SPORT2_MRCS1, val)
-#define bfin_read_SPORT2_MRCS2() bfin_read32(SPORT2_MRCS2)
-#define bfin_write_SPORT2_MRCS2(val) bfin_write32(SPORT2_MRCS2, val)
-#define bfin_read_SPORT2_MRCS3() bfin_read32(SPORT2_MRCS3)
-#define bfin_write_SPORT2_MRCS3(val) bfin_write32(SPORT2_MRCS3, val)
-
-/* SPORT3 Registers */
-
-#define bfin_read_SPORT3_TCR1() bfin_read16(SPORT3_TCR1)
-#define bfin_write_SPORT3_TCR1(val) bfin_write16(SPORT3_TCR1, val)
-#define bfin_read_SPORT3_TCR2() bfin_read16(SPORT3_TCR2)
-#define bfin_write_SPORT3_TCR2(val) bfin_write16(SPORT3_TCR2, val)
-#define bfin_read_SPORT3_TCLKDIV() bfin_read16(SPORT3_TCLKDIV)
-#define bfin_write_SPORT3_TCLKDIV(val) bfin_write16(SPORT3_TCLKDIV, val)
-#define bfin_read_SPORT3_TFSDIV() bfin_read16(SPORT3_TFSDIV)
-#define bfin_write_SPORT3_TFSDIV(val) bfin_write16(SPORT3_TFSDIV, val)
-#define bfin_read_SPORT3_TX() bfin_read32(SPORT3_TX)
-#define bfin_write_SPORT3_TX(val) bfin_write32(SPORT3_TX, val)
-#define bfin_read_SPORT3_RX() bfin_read32(SPORT3_RX)
-#define bfin_write_SPORT3_RX(val) bfin_write32(SPORT3_RX, val)
-#define bfin_read_SPORT3_RCR1() bfin_read16(SPORT3_RCR1)
-#define bfin_write_SPORT3_RCR1(val) bfin_write16(SPORT3_RCR1, val)
-#define bfin_read_SPORT3_RCR2() bfin_read16(SPORT3_RCR2)
-#define bfin_write_SPORT3_RCR2(val) bfin_write16(SPORT3_RCR2, val)
-#define bfin_read_SPORT3_RCLKDIV() bfin_read16(SPORT3_RCLKDIV)
-#define bfin_write_SPORT3_RCLKDIV(val) bfin_write16(SPORT3_RCLKDIV, val)
-#define bfin_read_SPORT3_RFSDIV() bfin_read16(SPORT3_RFSDIV)
-#define bfin_write_SPORT3_RFSDIV(val) bfin_write16(SPORT3_RFSDIV, val)
-#define bfin_read_SPORT3_STAT() bfin_read16(SPORT3_STAT)
-#define bfin_write_SPORT3_STAT(val) bfin_write16(SPORT3_STAT, val)
-#define bfin_read_SPORT3_CHNL() bfin_read16(SPORT3_CHNL)
-#define bfin_write_SPORT3_CHNL(val) bfin_write16(SPORT3_CHNL, val)
-#define bfin_read_SPORT3_MCMC1() bfin_read16(SPORT3_MCMC1)
-#define bfin_write_SPORT3_MCMC1(val) bfin_write16(SPORT3_MCMC1, val)
-#define bfin_read_SPORT3_MCMC2() bfin_read16(SPORT3_MCMC2)
-#define bfin_write_SPORT3_MCMC2(val) bfin_write16(SPORT3_MCMC2, val)
-#define bfin_read_SPORT3_MTCS0() bfin_read32(SPORT3_MTCS0)
-#define bfin_write_SPORT3_MTCS0(val) bfin_write32(SPORT3_MTCS0, val)
-#define bfin_read_SPORT3_MTCS1() bfin_read32(SPORT3_MTCS1)
-#define bfin_write_SPORT3_MTCS1(val) bfin_write32(SPORT3_MTCS1, val)
-#define bfin_read_SPORT3_MTCS2() bfin_read32(SPORT3_MTCS2)
-#define bfin_write_SPORT3_MTCS2(val) bfin_write32(SPORT3_MTCS2, val)
-#define bfin_read_SPORT3_MTCS3() bfin_read32(SPORT3_MTCS3)
-#define bfin_write_SPORT3_MTCS3(val) bfin_write32(SPORT3_MTCS3, val)
-#define bfin_read_SPORT3_MRCS0() bfin_read32(SPORT3_MRCS0)
-#define bfin_write_SPORT3_MRCS0(val) bfin_write32(SPORT3_MRCS0, val)
-#define bfin_read_SPORT3_MRCS1() bfin_read32(SPORT3_MRCS1)
-#define bfin_write_SPORT3_MRCS1(val) bfin_write32(SPORT3_MRCS1, val)
-#define bfin_read_SPORT3_MRCS2() bfin_read32(SPORT3_MRCS2)
-#define bfin_write_SPORT3_MRCS2(val) bfin_write32(SPORT3_MRCS2, val)
-#define bfin_read_SPORT3_MRCS3() bfin_read32(SPORT3_MRCS3)
-#define bfin_write_SPORT3_MRCS3(val) bfin_write32(SPORT3_MRCS3, val)
-
-/* EPPI2 Registers */
-
-#define bfin_read_EPPI2_STATUS() bfin_read16(EPPI2_STATUS)
-#define bfin_write_EPPI2_STATUS(val) bfin_write16(EPPI2_STATUS, val)
-#define bfin_read_EPPI2_HCOUNT() bfin_read16(EPPI2_HCOUNT)
-#define bfin_write_EPPI2_HCOUNT(val) bfin_write16(EPPI2_HCOUNT, val)
-#define bfin_read_EPPI2_HDELAY() bfin_read16(EPPI2_HDELAY)
-#define bfin_write_EPPI2_HDELAY(val) bfin_write16(EPPI2_HDELAY, val)
-#define bfin_read_EPPI2_VCOUNT() bfin_read16(EPPI2_VCOUNT)
-#define bfin_write_EPPI2_VCOUNT(val) bfin_write16(EPPI2_VCOUNT, val)
-#define bfin_read_EPPI2_VDELAY() bfin_read16(EPPI2_VDELAY)
-#define bfin_write_EPPI2_VDELAY(val) bfin_write16(EPPI2_VDELAY, val)
-#define bfin_read_EPPI2_FRAME() bfin_read16(EPPI2_FRAME)
-#define bfin_write_EPPI2_FRAME(val) bfin_write16(EPPI2_FRAME, val)
-#define bfin_read_EPPI2_LINE() bfin_read16(EPPI2_LINE)
-#define bfin_write_EPPI2_LINE(val) bfin_write16(EPPI2_LINE, val)
-#define bfin_read_EPPI2_CLKDIV() bfin_read16(EPPI2_CLKDIV)
-#define bfin_write_EPPI2_CLKDIV(val) bfin_write16(EPPI2_CLKDIV, val)
-#define bfin_read_EPPI2_CONTROL() bfin_read32(EPPI2_CONTROL)
-#define bfin_write_EPPI2_CONTROL(val) bfin_write32(EPPI2_CONTROL, val)
-#define bfin_read_EPPI2_FS1W_HBL() bfin_read32(EPPI2_FS1W_HBL)
-#define bfin_write_EPPI2_FS1W_HBL(val) bfin_write32(EPPI2_FS1W_HBL, val)
-#define bfin_read_EPPI2_FS1P_AVPL() bfin_read32(EPPI2_FS1P_AVPL)
-#define bfin_write_EPPI2_FS1P_AVPL(val) bfin_write32(EPPI2_FS1P_AVPL, val)
-#define bfin_read_EPPI2_FS2W_LVB() bfin_read32(EPPI2_FS2W_LVB)
-#define bfin_write_EPPI2_FS2W_LVB(val) bfin_write32(EPPI2_FS2W_LVB, val)
-#define bfin_read_EPPI2_FS2P_LAVF() bfin_read32(EPPI2_FS2P_LAVF)
-#define bfin_write_EPPI2_FS2P_LAVF(val) bfin_write32(EPPI2_FS2P_LAVF, val)
-#define bfin_read_EPPI2_CLIP() bfin_read32(EPPI2_CLIP)
-#define bfin_write_EPPI2_CLIP(val) bfin_write32(EPPI2_CLIP, val)
-
-/* CAN Controller 0 Config 1 Registers */
-
-#define bfin_read_CAN0_MC1() bfin_read16(CAN0_MC1)
-#define bfin_write_CAN0_MC1(val) bfin_write16(CAN0_MC1, val)
-#define bfin_read_CAN0_MD1() bfin_read16(CAN0_MD1)
-#define bfin_write_CAN0_MD1(val) bfin_write16(CAN0_MD1, val)
-#define bfin_read_CAN0_TRS1() bfin_read16(CAN0_TRS1)
-#define bfin_write_CAN0_TRS1(val) bfin_write16(CAN0_TRS1, val)
-#define bfin_read_CAN0_TRR1() bfin_read16(CAN0_TRR1)
-#define bfin_write_CAN0_TRR1(val) bfin_write16(CAN0_TRR1, val)
-#define bfin_read_CAN0_TA1() bfin_read16(CAN0_TA1)
-#define bfin_write_CAN0_TA1(val) bfin_write16(CAN0_TA1, val)
-#define bfin_read_CAN0_AA1() bfin_read16(CAN0_AA1)
-#define bfin_write_CAN0_AA1(val) bfin_write16(CAN0_AA1, val)
-#define bfin_read_CAN0_RMP1() bfin_read16(CAN0_RMP1)
-#define bfin_write_CAN0_RMP1(val) bfin_write16(CAN0_RMP1, val)
-#define bfin_read_CAN0_RML1() bfin_read16(CAN0_RML1)
-#define bfin_write_CAN0_RML1(val) bfin_write16(CAN0_RML1, val)
-#define bfin_read_CAN0_MBTIF1() bfin_read16(CAN0_MBTIF1)
-#define bfin_write_CAN0_MBTIF1(val) bfin_write16(CAN0_MBTIF1, val)
-#define bfin_read_CAN0_MBRIF1() bfin_read16(CAN0_MBRIF1)
-#define bfin_write_CAN0_MBRIF1(val) bfin_write16(CAN0_MBRIF1, val)
-#define bfin_read_CAN0_MBIM1() bfin_read16(CAN0_MBIM1)
-#define bfin_write_CAN0_MBIM1(val) bfin_write16(CAN0_MBIM1, val)
-#define bfin_read_CAN0_RFH1() bfin_read16(CAN0_RFH1)
-#define bfin_write_CAN0_RFH1(val) bfin_write16(CAN0_RFH1, val)
-#define bfin_read_CAN0_OPSS1() bfin_read16(CAN0_OPSS1)
-#define bfin_write_CAN0_OPSS1(val) bfin_write16(CAN0_OPSS1, val)
-
-/* CAN Controller 0 Config 2 Registers */
-
-#define bfin_read_CAN0_MC2() bfin_read16(CAN0_MC2)
-#define bfin_write_CAN0_MC2(val) bfin_write16(CAN0_MC2, val)
-#define bfin_read_CAN0_MD2() bfin_read16(CAN0_MD2)
-#define bfin_write_CAN0_MD2(val) bfin_write16(CAN0_MD2, val)
-#define bfin_read_CAN0_TRS2() bfin_read16(CAN0_TRS2)
-#define bfin_write_CAN0_TRS2(val) bfin_write16(CAN0_TRS2, val)
-#define bfin_read_CAN0_TRR2() bfin_read16(CAN0_TRR2)
-#define bfin_write_CAN0_TRR2(val) bfin_write16(CAN0_TRR2, val)
-#define bfin_read_CAN0_TA2() bfin_read16(CAN0_TA2)
-#define bfin_write_CAN0_TA2(val) bfin_write16(CAN0_TA2, val)
-#define bfin_read_CAN0_AA2() bfin_read16(CAN0_AA2)
-#define bfin_write_CAN0_AA2(val) bfin_write16(CAN0_AA2, val)
-#define bfin_read_CAN0_RMP2() bfin_read16(CAN0_RMP2)
-#define bfin_write_CAN0_RMP2(val) bfin_write16(CAN0_RMP2, val)
-#define bfin_read_CAN0_RML2() bfin_read16(CAN0_RML2)
-#define bfin_write_CAN0_RML2(val) bfin_write16(CAN0_RML2, val)
-#define bfin_read_CAN0_MBTIF2() bfin_read16(CAN0_MBTIF2)
-#define bfin_write_CAN0_MBTIF2(val) bfin_write16(CAN0_MBTIF2, val)
-#define bfin_read_CAN0_MBRIF2() bfin_read16(CAN0_MBRIF2)
-#define bfin_write_CAN0_MBRIF2(val) bfin_write16(CAN0_MBRIF2, val)
-#define bfin_read_CAN0_MBIM2() bfin_read16(CAN0_MBIM2)
-#define bfin_write_CAN0_MBIM2(val) bfin_write16(CAN0_MBIM2, val)
-#define bfin_read_CAN0_RFH2() bfin_read16(CAN0_RFH2)
-#define bfin_write_CAN0_RFH2(val) bfin_write16(CAN0_RFH2, val)
-#define bfin_read_CAN0_OPSS2() bfin_read16(CAN0_OPSS2)
-#define bfin_write_CAN0_OPSS2(val) bfin_write16(CAN0_OPSS2, val)
-
-/* CAN Controller 0 Clock/Interrubfin_read_()t/Counter Registers */
-
-#define bfin_read_CAN0_CLOCK() bfin_read16(CAN0_CLOCK)
-#define bfin_write_CAN0_CLOCK(val) bfin_write16(CAN0_CLOCK, val)
-#define bfin_read_CAN0_TIMING() bfin_read16(CAN0_TIMING)
-#define bfin_write_CAN0_TIMING(val) bfin_write16(CAN0_TIMING, val)
-#define bfin_read_CAN0_DEBUG() bfin_read16(CAN0_DEBUG)
-#define bfin_write_CAN0_DEBUG(val) bfin_write16(CAN0_DEBUG, val)
-#define bfin_read_CAN0_STATUS() bfin_read16(CAN0_STATUS)
-#define bfin_write_CAN0_STATUS(val) bfin_write16(CAN0_STATUS, val)
-#define bfin_read_CAN0_CEC() bfin_read16(CAN0_CEC)
-#define bfin_write_CAN0_CEC(val) bfin_write16(CAN0_CEC, val)
-#define bfin_read_CAN0_GIS() bfin_read16(CAN0_GIS)
-#define bfin_write_CAN0_GIS(val) bfin_write16(CAN0_GIS, val)
-#define bfin_read_CAN0_GIM() bfin_read16(CAN0_GIM)
-#define bfin_write_CAN0_GIM(val) bfin_write16(CAN0_GIM, val)
-#define bfin_read_CAN0_GIF() bfin_read16(CAN0_GIF)
-#define bfin_write_CAN0_GIF(val) bfin_write16(CAN0_GIF, val)
-#define bfin_read_CAN0_CONTROL() bfin_read16(CAN0_CONTROL)
-#define bfin_write_CAN0_CONTROL(val) bfin_write16(CAN0_CONTROL, val)
-#define bfin_read_CAN0_INTR() bfin_read16(CAN0_INTR)
-#define bfin_write_CAN0_INTR(val) bfin_write16(CAN0_INTR, val)
-#define bfin_read_CAN0_MBTD() bfin_read16(CAN0_MBTD)
-#define bfin_write_CAN0_MBTD(val) bfin_write16(CAN0_MBTD, val)
-#define bfin_read_CAN0_EWR() bfin_read16(CAN0_EWR)
-#define bfin_write_CAN0_EWR(val) bfin_write16(CAN0_EWR, val)
-#define bfin_read_CAN0_ESR() bfin_read16(CAN0_ESR)
-#define bfin_write_CAN0_ESR(val) bfin_write16(CAN0_ESR, val)
-#define bfin_read_CAN0_UCCNT() bfin_read16(CAN0_UCCNT)
-#define bfin_write_CAN0_UCCNT(val) bfin_write16(CAN0_UCCNT, val)
-#define bfin_read_CAN0_UCRC() bfin_read16(CAN0_UCRC)
-#define bfin_write_CAN0_UCRC(val) bfin_write16(CAN0_UCRC, val)
-#define bfin_read_CAN0_UCCNF() bfin_read16(CAN0_UCCNF)
-#define bfin_write_CAN0_UCCNF(val) bfin_write16(CAN0_UCCNF, val)
-
-/* CAN Controller 0 Accebfin_read_()tance Registers */
-
-#define bfin_read_CAN0_AM00L() bfin_read16(CAN0_AM00L)
-#define bfin_write_CAN0_AM00L(val) bfin_write16(CAN0_AM00L, val)
-#define bfin_read_CAN0_AM00H() bfin_read16(CAN0_AM00H)
-#define bfin_write_CAN0_AM00H(val) bfin_write16(CAN0_AM00H, val)
-#define bfin_read_CAN0_AM01L() bfin_read16(CAN0_AM01L)
-#define bfin_write_CAN0_AM01L(val) bfin_write16(CAN0_AM01L, val)
-#define bfin_read_CAN0_AM01H() bfin_read16(CAN0_AM01H)
-#define bfin_write_CAN0_AM01H(val) bfin_write16(CAN0_AM01H, val)
-#define bfin_read_CAN0_AM02L() bfin_read16(CAN0_AM02L)
-#define bfin_write_CAN0_AM02L(val) bfin_write16(CAN0_AM02L, val)
-#define bfin_read_CAN0_AM02H() bfin_read16(CAN0_AM02H)
-#define bfin_write_CAN0_AM02H(val) bfin_write16(CAN0_AM02H, val)
-#define bfin_read_CAN0_AM03L() bfin_read16(CAN0_AM03L)
-#define bfin_write_CAN0_AM03L(val) bfin_write16(CAN0_AM03L, val)
-#define bfin_read_CAN0_AM03H() bfin_read16(CAN0_AM03H)
-#define bfin_write_CAN0_AM03H(val) bfin_write16(CAN0_AM03H, val)
-#define bfin_read_CAN0_AM04L() bfin_read16(CAN0_AM04L)
-#define bfin_write_CAN0_AM04L(val) bfin_write16(CAN0_AM04L, val)
-#define bfin_read_CAN0_AM04H() bfin_read16(CAN0_AM04H)
-#define bfin_write_CAN0_AM04H(val) bfin_write16(CAN0_AM04H, val)
-#define bfin_read_CAN0_AM05L() bfin_read16(CAN0_AM05L)
-#define bfin_write_CAN0_AM05L(val) bfin_write16(CAN0_AM05L, val)
-#define bfin_read_CAN0_AM05H() bfin_read16(CAN0_AM05H)
-#define bfin_write_CAN0_AM05H(val) bfin_write16(CAN0_AM05H, val)
-#define bfin_read_CAN0_AM06L() bfin_read16(CAN0_AM06L)
-#define bfin_write_CAN0_AM06L(val) bfin_write16(CAN0_AM06L, val)
-#define bfin_read_CAN0_AM06H() bfin_read16(CAN0_AM06H)
-#define bfin_write_CAN0_AM06H(val) bfin_write16(CAN0_AM06H, val)
-#define bfin_read_CAN0_AM07L() bfin_read16(CAN0_AM07L)
-#define bfin_write_CAN0_AM07L(val) bfin_write16(CAN0_AM07L, val)
-#define bfin_read_CAN0_AM07H() bfin_read16(CAN0_AM07H)
-#define bfin_write_CAN0_AM07H(val) bfin_write16(CAN0_AM07H, val)
-#define bfin_read_CAN0_AM08L() bfin_read16(CAN0_AM08L)
-#define bfin_write_CAN0_AM08L(val) bfin_write16(CAN0_AM08L, val)
-#define bfin_read_CAN0_AM08H() bfin_read16(CAN0_AM08H)
-#define bfin_write_CAN0_AM08H(val) bfin_write16(CAN0_AM08H, val)
-#define bfin_read_CAN0_AM09L() bfin_read16(CAN0_AM09L)
-#define bfin_write_CAN0_AM09L(val) bfin_write16(CAN0_AM09L, val)
-#define bfin_read_CAN0_AM09H() bfin_read16(CAN0_AM09H)
-#define bfin_write_CAN0_AM09H(val) bfin_write16(CAN0_AM09H, val)
-#define bfin_read_CAN0_AM10L() bfin_read16(CAN0_AM10L)
-#define bfin_write_CAN0_AM10L(val) bfin_write16(CAN0_AM10L, val)
-#define bfin_read_CAN0_AM10H() bfin_read16(CAN0_AM10H)
-#define bfin_write_CAN0_AM10H(val) bfin_write16(CAN0_AM10H, val)
-#define bfin_read_CAN0_AM11L() bfin_read16(CAN0_AM11L)
-#define bfin_write_CAN0_AM11L(val) bfin_write16(CAN0_AM11L, val)
-#define bfin_read_CAN0_AM11H() bfin_read16(CAN0_AM11H)
-#define bfin_write_CAN0_AM11H(val) bfin_write16(CAN0_AM11H, val)
-#define bfin_read_CAN0_AM12L() bfin_read16(CAN0_AM12L)
-#define bfin_write_CAN0_AM12L(val) bfin_write16(CAN0_AM12L, val)
-#define bfin_read_CAN0_AM12H() bfin_read16(CAN0_AM12H)
-#define bfin_write_CAN0_AM12H(val) bfin_write16(CAN0_AM12H, val)
-#define bfin_read_CAN0_AM13L() bfin_read16(CAN0_AM13L)
-#define bfin_write_CAN0_AM13L(val) bfin_write16(CAN0_AM13L, val)
-#define bfin_read_CAN0_AM13H() bfin_read16(CAN0_AM13H)
-#define bfin_write_CAN0_AM13H(val) bfin_write16(CAN0_AM13H, val)
-#define bfin_read_CAN0_AM14L() bfin_read16(CAN0_AM14L)
-#define bfin_write_CAN0_AM14L(val) bfin_write16(CAN0_AM14L, val)
-#define bfin_read_CAN0_AM14H() bfin_read16(CAN0_AM14H)
-#define bfin_write_CAN0_AM14H(val) bfin_write16(CAN0_AM14H, val)
-#define bfin_read_CAN0_AM15L() bfin_read16(CAN0_AM15L)
-#define bfin_write_CAN0_AM15L(val) bfin_write16(CAN0_AM15L, val)
-#define bfin_read_CAN0_AM15H() bfin_read16(CAN0_AM15H)
-#define bfin_write_CAN0_AM15H(val) bfin_write16(CAN0_AM15H, val)
-
-/* CAN Controller 0 Accebfin_read_()tance Registers */
-
-#define bfin_read_CAN0_AM16L() bfin_read16(CAN0_AM16L)
-#define bfin_write_CAN0_AM16L(val) bfin_write16(CAN0_AM16L, val)
-#define bfin_read_CAN0_AM16H() bfin_read16(CAN0_AM16H)
-#define bfin_write_CAN0_AM16H(val) bfin_write16(CAN0_AM16H, val)
-#define bfin_read_CAN0_AM17L() bfin_read16(CAN0_AM17L)
-#define bfin_write_CAN0_AM17L(val) bfin_write16(CAN0_AM17L, val)
-#define bfin_read_CAN0_AM17H() bfin_read16(CAN0_AM17H)
-#define bfin_write_CAN0_AM17H(val) bfin_write16(CAN0_AM17H, val)
-#define bfin_read_CAN0_AM18L() bfin_read16(CAN0_AM18L)
-#define bfin_write_CAN0_AM18L(val) bfin_write16(CAN0_AM18L, val)
-#define bfin_read_CAN0_AM18H() bfin_read16(CAN0_AM18H)
-#define bfin_write_CAN0_AM18H(val) bfin_write16(CAN0_AM18H, val)
-#define bfin_read_CAN0_AM19L() bfin_read16(CAN0_AM19L)
-#define bfin_write_CAN0_AM19L(val) bfin_write16(CAN0_AM19L, val)
-#define bfin_read_CAN0_AM19H() bfin_read16(CAN0_AM19H)
-#define bfin_write_CAN0_AM19H(val) bfin_write16(CAN0_AM19H, val)
-#define bfin_read_CAN0_AM20L() bfin_read16(CAN0_AM20L)
-#define bfin_write_CAN0_AM20L(val) bfin_write16(CAN0_AM20L, val)
-#define bfin_read_CAN0_AM20H() bfin_read16(CAN0_AM20H)
-#define bfin_write_CAN0_AM20H(val) bfin_write16(CAN0_AM20H, val)
-#define bfin_read_CAN0_AM21L() bfin_read16(CAN0_AM21L)
-#define bfin_write_CAN0_AM21L(val) bfin_write16(CAN0_AM21L, val)
-#define bfin_read_CAN0_AM21H() bfin_read16(CAN0_AM21H)
-#define bfin_write_CAN0_AM21H(val) bfin_write16(CAN0_AM21H, val)
-#define bfin_read_CAN0_AM22L() bfin_read16(CAN0_AM22L)
-#define bfin_write_CAN0_AM22L(val) bfin_write16(CAN0_AM22L, val)
-#define bfin_read_CAN0_AM22H() bfin_read16(CAN0_AM22H)
-#define bfin_write_CAN0_AM22H(val) bfin_write16(CAN0_AM22H, val)
-#define bfin_read_CAN0_AM23L() bfin_read16(CAN0_AM23L)
-#define bfin_write_CAN0_AM23L(val) bfin_write16(CAN0_AM23L, val)
-#define bfin_read_CAN0_AM23H() bfin_read16(CAN0_AM23H)
-#define bfin_write_CAN0_AM23H(val) bfin_write16(CAN0_AM23H, val)
-#define bfin_read_CAN0_AM24L() bfin_read16(CAN0_AM24L)
-#define bfin_write_CAN0_AM24L(val) bfin_write16(CAN0_AM24L, val)
-#define bfin_read_CAN0_AM24H() bfin_read16(CAN0_AM24H)
-#define bfin_write_CAN0_AM24H(val) bfin_write16(CAN0_AM24H, val)
-#define bfin_read_CAN0_AM25L() bfin_read16(CAN0_AM25L)
-#define bfin_write_CAN0_AM25L(val) bfin_write16(CAN0_AM25L, val)
-#define bfin_read_CAN0_AM25H() bfin_read16(CAN0_AM25H)
-#define bfin_write_CAN0_AM25H(val) bfin_write16(CAN0_AM25H, val)
-#define bfin_read_CAN0_AM26L() bfin_read16(CAN0_AM26L)
-#define bfin_write_CAN0_AM26L(val) bfin_write16(CAN0_AM26L, val)
-#define bfin_read_CAN0_AM26H() bfin_read16(CAN0_AM26H)
-#define bfin_write_CAN0_AM26H(val) bfin_write16(CAN0_AM26H, val)
-#define bfin_read_CAN0_AM27L() bfin_read16(CAN0_AM27L)
-#define bfin_write_CAN0_AM27L(val) bfin_write16(CAN0_AM27L, val)
-#define bfin_read_CAN0_AM27H() bfin_read16(CAN0_AM27H)
-#define bfin_write_CAN0_AM27H(val) bfin_write16(CAN0_AM27H, val)
-#define bfin_read_CAN0_AM28L() bfin_read16(CAN0_AM28L)
-#define bfin_write_CAN0_AM28L(val) bfin_write16(CAN0_AM28L, val)
-#define bfin_read_CAN0_AM28H() bfin_read16(CAN0_AM28H)
-#define bfin_write_CAN0_AM28H(val) bfin_write16(CAN0_AM28H, val)
-#define bfin_read_CAN0_AM29L() bfin_read16(CAN0_AM29L)
-#define bfin_write_CAN0_AM29L(val) bfin_write16(CAN0_AM29L, val)
-#define bfin_read_CAN0_AM29H() bfin_read16(CAN0_AM29H)
-#define bfin_write_CAN0_AM29H(val) bfin_write16(CAN0_AM29H, val)
-#define bfin_read_CAN0_AM30L() bfin_read16(CAN0_AM30L)
-#define bfin_write_CAN0_AM30L(val) bfin_write16(CAN0_AM30L, val)
-#define bfin_read_CAN0_AM30H() bfin_read16(CAN0_AM30H)
-#define bfin_write_CAN0_AM30H(val) bfin_write16(CAN0_AM30H, val)
-#define bfin_read_CAN0_AM31L() bfin_read16(CAN0_AM31L)
-#define bfin_write_CAN0_AM31L(val) bfin_write16(CAN0_AM31L, val)
-#define bfin_read_CAN0_AM31H() bfin_read16(CAN0_AM31H)
-#define bfin_write_CAN0_AM31H(val) bfin_write16(CAN0_AM31H, val)
-
-/* CAN Controller 0 Mailbox Data Registers */
-
-#define bfin_read_CAN0_MB00_DATA0() bfin_read16(CAN0_MB00_DATA0)
-#define bfin_write_CAN0_MB00_DATA0(val) bfin_write16(CAN0_MB00_DATA0, val)
-#define bfin_read_CAN0_MB00_DATA1() bfin_read16(CAN0_MB00_DATA1)
-#define bfin_write_CAN0_MB00_DATA1(val) bfin_write16(CAN0_MB00_DATA1, val)
-#define bfin_read_CAN0_MB00_DATA2() bfin_read16(CAN0_MB00_DATA2)
-#define bfin_write_CAN0_MB00_DATA2(val) bfin_write16(CAN0_MB00_DATA2, val)
-#define bfin_read_CAN0_MB00_DATA3() bfin_read16(CAN0_MB00_DATA3)
-#define bfin_write_CAN0_MB00_DATA3(val) bfin_write16(CAN0_MB00_DATA3, val)
-#define bfin_read_CAN0_MB00_LENGTH() bfin_read16(CAN0_MB00_LENGTH)
-#define bfin_write_CAN0_MB00_LENGTH(val) bfin_write16(CAN0_MB00_LENGTH, val)
-#define bfin_read_CAN0_MB00_TIMESTAMP() bfin_read16(CAN0_MB00_TIMESTAMP)
-#define bfin_write_CAN0_MB00_TIMESTAMP(val) bfin_write16(CAN0_MB00_TIMESTAMP, val)
-#define bfin_read_CAN0_MB00_ID0() bfin_read16(CAN0_MB00_ID0)
-#define bfin_write_CAN0_MB00_ID0(val) bfin_write16(CAN0_MB00_ID0, val)
-#define bfin_read_CAN0_MB00_ID1() bfin_read16(CAN0_MB00_ID1)
-#define bfin_write_CAN0_MB00_ID1(val) bfin_write16(CAN0_MB00_ID1, val)
-#define bfin_read_CAN0_MB01_DATA0() bfin_read16(CAN0_MB01_DATA0)
-#define bfin_write_CAN0_MB01_DATA0(val) bfin_write16(CAN0_MB01_DATA0, val)
-#define bfin_read_CAN0_MB01_DATA1() bfin_read16(CAN0_MB01_DATA1)
-#define bfin_write_CAN0_MB01_DATA1(val) bfin_write16(CAN0_MB01_DATA1, val)
-#define bfin_read_CAN0_MB01_DATA2() bfin_read16(CAN0_MB01_DATA2)
-#define bfin_write_CAN0_MB01_DATA2(val) bfin_write16(CAN0_MB01_DATA2, val)
-#define bfin_read_CAN0_MB01_DATA3() bfin_read16(CAN0_MB01_DATA3)
-#define bfin_write_CAN0_MB01_DATA3(val) bfin_write16(CAN0_MB01_DATA3, val)
-#define bfin_read_CAN0_MB01_LENGTH() bfin_read16(CAN0_MB01_LENGTH)
-#define bfin_write_CAN0_MB01_LENGTH(val) bfin_write16(CAN0_MB01_LENGTH, val)
-#define bfin_read_CAN0_MB01_TIMESTAMP() bfin_read16(CAN0_MB01_TIMESTAMP)
-#define bfin_write_CAN0_MB01_TIMESTAMP(val) bfin_write16(CAN0_MB01_TIMESTAMP, val)
-#define bfin_read_CAN0_MB01_ID0() bfin_read16(CAN0_MB01_ID0)
-#define bfin_write_CAN0_MB01_ID0(val) bfin_write16(CAN0_MB01_ID0, val)
-#define bfin_read_CAN0_MB01_ID1() bfin_read16(CAN0_MB01_ID1)
-#define bfin_write_CAN0_MB01_ID1(val) bfin_write16(CAN0_MB01_ID1, val)
-#define bfin_read_CAN0_MB02_DATA0() bfin_read16(CAN0_MB02_DATA0)
-#define bfin_write_CAN0_MB02_DATA0(val) bfin_write16(CAN0_MB02_DATA0, val)
-#define bfin_read_CAN0_MB02_DATA1() bfin_read16(CAN0_MB02_DATA1)
-#define bfin_write_CAN0_MB02_DATA1(val) bfin_write16(CAN0_MB02_DATA1, val)
-#define bfin_read_CAN0_MB02_DATA2() bfin_read16(CAN0_MB02_DATA2)
-#define bfin_write_CAN0_MB02_DATA2(val) bfin_write16(CAN0_MB02_DATA2, val)
-#define bfin_read_CAN0_MB02_DATA3() bfin_read16(CAN0_MB02_DATA3)
-#define bfin_write_CAN0_MB02_DATA3(val) bfin_write16(CAN0_MB02_DATA3, val)
-#define bfin_read_CAN0_MB02_LENGTH() bfin_read16(CAN0_MB02_LENGTH)
-#define bfin_write_CAN0_MB02_LENGTH(val) bfin_write16(CAN0_MB02_LENGTH, val)
-#define bfin_read_CAN0_MB02_TIMESTAMP() bfin_read16(CAN0_MB02_TIMESTAMP)
-#define bfin_write_CAN0_MB02_TIMESTAMP(val) bfin_write16(CAN0_MB02_TIMESTAMP, val)
-#define bfin_read_CAN0_MB02_ID0() bfin_read16(CAN0_MB02_ID0)
-#define bfin_write_CAN0_MB02_ID0(val) bfin_write16(CAN0_MB02_ID0, val)
-#define bfin_read_CAN0_MB02_ID1() bfin_read16(CAN0_MB02_ID1)
-#define bfin_write_CAN0_MB02_ID1(val) bfin_write16(CAN0_MB02_ID1, val)
-#define bfin_read_CAN0_MB03_DATA0() bfin_read16(CAN0_MB03_DATA0)
-#define bfin_write_CAN0_MB03_DATA0(val) bfin_write16(CAN0_MB03_DATA0, val)
-#define bfin_read_CAN0_MB03_DATA1() bfin_read16(CAN0_MB03_DATA1)
-#define bfin_write_CAN0_MB03_DATA1(val) bfin_write16(CAN0_MB03_DATA1, val)
-#define bfin_read_CAN0_MB03_DATA2() bfin_read16(CAN0_MB03_DATA2)
-#define bfin_write_CAN0_MB03_DATA2(val) bfin_write16(CAN0_MB03_DATA2, val)
-#define bfin_read_CAN0_MB03_DATA3() bfin_read16(CAN0_MB03_DATA3)
-#define bfin_write_CAN0_MB03_DATA3(val) bfin_write16(CAN0_MB03_DATA3, val)
-#define bfin_read_CAN0_MB03_LENGTH() bfin_read16(CAN0_MB03_LENGTH)
-#define bfin_write_CAN0_MB03_LENGTH(val) bfin_write16(CAN0_MB03_LENGTH, val)
-#define bfin_read_CAN0_MB03_TIMESTAMP() bfin_read16(CAN0_MB03_TIMESTAMP)
-#define bfin_write_CAN0_MB03_TIMESTAMP(val) bfin_write16(CAN0_MB03_TIMESTAMP, val)
-#define bfin_read_CAN0_MB03_ID0() bfin_read16(CAN0_MB03_ID0)
-#define bfin_write_CAN0_MB03_ID0(val) bfin_write16(CAN0_MB03_ID0, val)
-#define bfin_read_CAN0_MB03_ID1() bfin_read16(CAN0_MB03_ID1)
-#define bfin_write_CAN0_MB03_ID1(val) bfin_write16(CAN0_MB03_ID1, val)
-#define bfin_read_CAN0_MB04_DATA0() bfin_read16(CAN0_MB04_DATA0)
-#define bfin_write_CAN0_MB04_DATA0(val) bfin_write16(CAN0_MB04_DATA0, val)
-#define bfin_read_CAN0_MB04_DATA1() bfin_read16(CAN0_MB04_DATA1)
-#define bfin_write_CAN0_MB04_DATA1(val) bfin_write16(CAN0_MB04_DATA1, val)
-#define bfin_read_CAN0_MB04_DATA2() bfin_read16(CAN0_MB04_DATA2)
-#define bfin_write_CAN0_MB04_DATA2(val) bfin_write16(CAN0_MB04_DATA2, val)
-#define bfin_read_CAN0_MB04_DATA3() bfin_read16(CAN0_MB04_DATA3)
-#define bfin_write_CAN0_MB04_DATA3(val) bfin_write16(CAN0_MB04_DATA3, val)
-#define bfin_read_CAN0_MB04_LENGTH() bfin_read16(CAN0_MB04_LENGTH)
-#define bfin_write_CAN0_MB04_LENGTH(val) bfin_write16(CAN0_MB04_LENGTH, val)
-#define bfin_read_CAN0_MB04_TIMESTAMP() bfin_read16(CAN0_MB04_TIMESTAMP)
-#define bfin_write_CAN0_MB04_TIMESTAMP(val) bfin_write16(CAN0_MB04_TIMESTAMP, val)
-#define bfin_read_CAN0_MB04_ID0() bfin_read16(CAN0_MB04_ID0)
-#define bfin_write_CAN0_MB04_ID0(val) bfin_write16(CAN0_MB04_ID0, val)
-#define bfin_read_CAN0_MB04_ID1() bfin_read16(CAN0_MB04_ID1)
-#define bfin_write_CAN0_MB04_ID1(val) bfin_write16(CAN0_MB04_ID1, val)
-#define bfin_read_CAN0_MB05_DATA0() bfin_read16(CAN0_MB05_DATA0)
-#define bfin_write_CAN0_MB05_DATA0(val) bfin_write16(CAN0_MB05_DATA0, val)
-#define bfin_read_CAN0_MB05_DATA1() bfin_read16(CAN0_MB05_DATA1)
-#define bfin_write_CAN0_MB05_DATA1(val) bfin_write16(CAN0_MB05_DATA1, val)
-#define bfin_read_CAN0_MB05_DATA2() bfin_read16(CAN0_MB05_DATA2)
-#define bfin_write_CAN0_MB05_DATA2(val) bfin_write16(CAN0_MB05_DATA2, val)
-#define bfin_read_CAN0_MB05_DATA3() bfin_read16(CAN0_MB05_DATA3)
-#define bfin_write_CAN0_MB05_DATA3(val) bfin_write16(CAN0_MB05_DATA3, val)
-#define bfin_read_CAN0_MB05_LENGTH() bfin_read16(CAN0_MB05_LENGTH)
-#define bfin_write_CAN0_MB05_LENGTH(val) bfin_write16(CAN0_MB05_LENGTH, val)
-#define bfin_read_CAN0_MB05_TIMESTAMP() bfin_read16(CAN0_MB05_TIMESTAMP)
-#define bfin_write_CAN0_MB05_TIMESTAMP(val) bfin_write16(CAN0_MB05_TIMESTAMP, val)
-#define bfin_read_CAN0_MB05_ID0() bfin_read16(CAN0_MB05_ID0)
-#define bfin_write_CAN0_MB05_ID0(val) bfin_write16(CAN0_MB05_ID0, val)
-#define bfin_read_CAN0_MB05_ID1() bfin_read16(CAN0_MB05_ID1)
-#define bfin_write_CAN0_MB05_ID1(val) bfin_write16(CAN0_MB05_ID1, val)
-#define bfin_read_CAN0_MB06_DATA0() bfin_read16(CAN0_MB06_DATA0)
-#define bfin_write_CAN0_MB06_DATA0(val) bfin_write16(CAN0_MB06_DATA0, val)
-#define bfin_read_CAN0_MB06_DATA1() bfin_read16(CAN0_MB06_DATA1)
-#define bfin_write_CAN0_MB06_DATA1(val) bfin_write16(CAN0_MB06_DATA1, val)
-#define bfin_read_CAN0_MB06_DATA2() bfin_read16(CAN0_MB06_DATA2)
-#define bfin_write_CAN0_MB06_DATA2(val) bfin_write16(CAN0_MB06_DATA2, val)
-#define bfin_read_CAN0_MB06_DATA3() bfin_read16(CAN0_MB06_DATA3)
-#define bfin_write_CAN0_MB06_DATA3(val) bfin_write16(CAN0_MB06_DATA3, val)
-#define bfin_read_CAN0_MB06_LENGTH() bfin_read16(CAN0_MB06_LENGTH)
-#define bfin_write_CAN0_MB06_LENGTH(val) bfin_write16(CAN0_MB06_LENGTH, val)
-#define bfin_read_CAN0_MB06_TIMESTAMP() bfin_read16(CAN0_MB06_TIMESTAMP)
-#define bfin_write_CAN0_MB06_TIMESTAMP(val) bfin_write16(CAN0_MB06_TIMESTAMP, val)
-#define bfin_read_CAN0_MB06_ID0() bfin_read16(CAN0_MB06_ID0)
-#define bfin_write_CAN0_MB06_ID0(val) bfin_write16(CAN0_MB06_ID0, val)
-#define bfin_read_CAN0_MB06_ID1() bfin_read16(CAN0_MB06_ID1)
-#define bfin_write_CAN0_MB06_ID1(val) bfin_write16(CAN0_MB06_ID1, val)
-#define bfin_read_CAN0_MB07_DATA0() bfin_read16(CAN0_MB07_DATA0)
-#define bfin_write_CAN0_MB07_DATA0(val) bfin_write16(CAN0_MB07_DATA0, val)
-#define bfin_read_CAN0_MB07_DATA1() bfin_read16(CAN0_MB07_DATA1)
-#define bfin_write_CAN0_MB07_DATA1(val) bfin_write16(CAN0_MB07_DATA1, val)
-#define bfin_read_CAN0_MB07_DATA2() bfin_read16(CAN0_MB07_DATA2)
-#define bfin_write_CAN0_MB07_DATA2(val) bfin_write16(CAN0_MB07_DATA2, val)
-#define bfin_read_CAN0_MB07_DATA3() bfin_read16(CAN0_MB07_DATA3)
-#define bfin_write_CAN0_MB07_DATA3(val) bfin_write16(CAN0_MB07_DATA3, val)
-#define bfin_read_CAN0_MB07_LENGTH() bfin_read16(CAN0_MB07_LENGTH)
-#define bfin_write_CAN0_MB07_LENGTH(val) bfin_write16(CAN0_MB07_LENGTH, val)
-#define bfin_read_CAN0_MB07_TIMESTAMP() bfin_read16(CAN0_MB07_TIMESTAMP)
-#define bfin_write_CAN0_MB07_TIMESTAMP(val) bfin_write16(CAN0_MB07_TIMESTAMP, val)
-#define bfin_read_CAN0_MB07_ID0() bfin_read16(CAN0_MB07_ID0)
-#define bfin_write_CAN0_MB07_ID0(val) bfin_write16(CAN0_MB07_ID0, val)
-#define bfin_read_CAN0_MB07_ID1() bfin_read16(CAN0_MB07_ID1)
-#define bfin_write_CAN0_MB07_ID1(val) bfin_write16(CAN0_MB07_ID1, val)
-#define bfin_read_CAN0_MB08_DATA0() bfin_read16(CAN0_MB08_DATA0)
-#define bfin_write_CAN0_MB08_DATA0(val) bfin_write16(CAN0_MB08_DATA0, val)
-#define bfin_read_CAN0_MB08_DATA1() bfin_read16(CAN0_MB08_DATA1)
-#define bfin_write_CAN0_MB08_DATA1(val) bfin_write16(CAN0_MB08_DATA1, val)
-#define bfin_read_CAN0_MB08_DATA2() bfin_read16(CAN0_MB08_DATA2)
-#define bfin_write_CAN0_MB08_DATA2(val) bfin_write16(CAN0_MB08_DATA2, val)
-#define bfin_read_CAN0_MB08_DATA3() bfin_read16(CAN0_MB08_DATA3)
-#define bfin_write_CAN0_MB08_DATA3(val) bfin_write16(CAN0_MB08_DATA3, val)
-#define bfin_read_CAN0_MB08_LENGTH() bfin_read16(CAN0_MB08_LENGTH)
-#define bfin_write_CAN0_MB08_LENGTH(val) bfin_write16(CAN0_MB08_LENGTH, val)
-#define bfin_read_CAN0_MB08_TIMESTAMP() bfin_read16(CAN0_MB08_TIMESTAMP)
-#define bfin_write_CAN0_MB08_TIMESTAMP(val) bfin_write16(CAN0_MB08_TIMESTAMP, val)
-#define bfin_read_CAN0_MB08_ID0() bfin_read16(CAN0_MB08_ID0)
-#define bfin_write_CAN0_MB08_ID0(val) bfin_write16(CAN0_MB08_ID0, val)
-#define bfin_read_CAN0_MB08_ID1() bfin_read16(CAN0_MB08_ID1)
-#define bfin_write_CAN0_MB08_ID1(val) bfin_write16(CAN0_MB08_ID1, val)
-#define bfin_read_CAN0_MB09_DATA0() bfin_read16(CAN0_MB09_DATA0)
-#define bfin_write_CAN0_MB09_DATA0(val) bfin_write16(CAN0_MB09_DATA0, val)
-#define bfin_read_CAN0_MB09_DATA1() bfin_read16(CAN0_MB09_DATA1)
-#define bfin_write_CAN0_MB09_DATA1(val) bfin_write16(CAN0_MB09_DATA1, val)
-#define bfin_read_CAN0_MB09_DATA2() bfin_read16(CAN0_MB09_DATA2)
-#define bfin_write_CAN0_MB09_DATA2(val) bfin_write16(CAN0_MB09_DATA2, val)
-#define bfin_read_CAN0_MB09_DATA3() bfin_read16(CAN0_MB09_DATA3)
-#define bfin_write_CAN0_MB09_DATA3(val) bfin_write16(CAN0_MB09_DATA3, val)
-#define bfin_read_CAN0_MB09_LENGTH() bfin_read16(CAN0_MB09_LENGTH)
-#define bfin_write_CAN0_MB09_LENGTH(val) bfin_write16(CAN0_MB09_LENGTH, val)
-#define bfin_read_CAN0_MB09_TIMESTAMP() bfin_read16(CAN0_MB09_TIMESTAMP)
-#define bfin_write_CAN0_MB09_TIMESTAMP(val) bfin_write16(CAN0_MB09_TIMESTAMP, val)
-#define bfin_read_CAN0_MB09_ID0() bfin_read16(CAN0_MB09_ID0)
-#define bfin_write_CAN0_MB09_ID0(val) bfin_write16(CAN0_MB09_ID0, val)
-#define bfin_read_CAN0_MB09_ID1() bfin_read16(CAN0_MB09_ID1)
-#define bfin_write_CAN0_MB09_ID1(val) bfin_write16(CAN0_MB09_ID1, val)
-#define bfin_read_CAN0_MB10_DATA0() bfin_read16(CAN0_MB10_DATA0)
-#define bfin_write_CAN0_MB10_DATA0(val) bfin_write16(CAN0_MB10_DATA0, val)
-#define bfin_read_CAN0_MB10_DATA1() bfin_read16(CAN0_MB10_DATA1)
-#define bfin_write_CAN0_MB10_DATA1(val) bfin_write16(CAN0_MB10_DATA1, val)
-#define bfin_read_CAN0_MB10_DATA2() bfin_read16(CAN0_MB10_DATA2)
-#define bfin_write_CAN0_MB10_DATA2(val) bfin_write16(CAN0_MB10_DATA2, val)
-#define bfin_read_CAN0_MB10_DATA3() bfin_read16(CAN0_MB10_DATA3)
-#define bfin_write_CAN0_MB10_DATA3(val) bfin_write16(CAN0_MB10_DATA3, val)
-#define bfin_read_CAN0_MB10_LENGTH() bfin_read16(CAN0_MB10_LENGTH)
-#define bfin_write_CAN0_MB10_LENGTH(val) bfin_write16(CAN0_MB10_LENGTH, val)
-#define bfin_read_CAN0_MB10_TIMESTAMP() bfin_read16(CAN0_MB10_TIMESTAMP)
-#define bfin_write_CAN0_MB10_TIMESTAMP(val) bfin_write16(CAN0_MB10_TIMESTAMP, val)
-#define bfin_read_CAN0_MB10_ID0() bfin_read16(CAN0_MB10_ID0)
-#define bfin_write_CAN0_MB10_ID0(val) bfin_write16(CAN0_MB10_ID0, val)
-#define bfin_read_CAN0_MB10_ID1() bfin_read16(CAN0_MB10_ID1)
-#define bfin_write_CAN0_MB10_ID1(val) bfin_write16(CAN0_MB10_ID1, val)
-#define bfin_read_CAN0_MB11_DATA0() bfin_read16(CAN0_MB11_DATA0)
-#define bfin_write_CAN0_MB11_DATA0(val) bfin_write16(CAN0_MB11_DATA0, val)
-#define bfin_read_CAN0_MB11_DATA1() bfin_read16(CAN0_MB11_DATA1)
-#define bfin_write_CAN0_MB11_DATA1(val) bfin_write16(CAN0_MB11_DATA1, val)
-#define bfin_read_CAN0_MB11_DATA2() bfin_read16(CAN0_MB11_DATA2)
-#define bfin_write_CAN0_MB11_DATA2(val) bfin_write16(CAN0_MB11_DATA2, val)
-#define bfin_read_CAN0_MB11_DATA3() bfin_read16(CAN0_MB11_DATA3)
-#define bfin_write_CAN0_MB11_DATA3(val) bfin_write16(CAN0_MB11_DATA3, val)
-#define bfin_read_CAN0_MB11_LENGTH() bfin_read16(CAN0_MB11_LENGTH)
-#define bfin_write_CAN0_MB11_LENGTH(val) bfin_write16(CAN0_MB11_LENGTH, val)
-#define bfin_read_CAN0_MB11_TIMESTAMP() bfin_read16(CAN0_MB11_TIMESTAMP)
-#define bfin_write_CAN0_MB11_TIMESTAMP(val) bfin_write16(CAN0_MB11_TIMESTAMP, val)
-#define bfin_read_CAN0_MB11_ID0() bfin_read16(CAN0_MB11_ID0)
-#define bfin_write_CAN0_MB11_ID0(val) bfin_write16(CAN0_MB11_ID0, val)
-#define bfin_read_CAN0_MB11_ID1() bfin_read16(CAN0_MB11_ID1)
-#define bfin_write_CAN0_MB11_ID1(val) bfin_write16(CAN0_MB11_ID1, val)
-#define bfin_read_CAN0_MB12_DATA0() bfin_read16(CAN0_MB12_DATA0)
-#define bfin_write_CAN0_MB12_DATA0(val) bfin_write16(CAN0_MB12_DATA0, val)
-#define bfin_read_CAN0_MB12_DATA1() bfin_read16(CAN0_MB12_DATA1)
-#define bfin_write_CAN0_MB12_DATA1(val) bfin_write16(CAN0_MB12_DATA1, val)
-#define bfin_read_CAN0_MB12_DATA2() bfin_read16(CAN0_MB12_DATA2)
-#define bfin_write_CAN0_MB12_DATA2(val) bfin_write16(CAN0_MB12_DATA2, val)
-#define bfin_read_CAN0_MB12_DATA3() bfin_read16(CAN0_MB12_DATA3)
-#define bfin_write_CAN0_MB12_DATA3(val) bfin_write16(CAN0_MB12_DATA3, val)
-#define bfin_read_CAN0_MB12_LENGTH() bfin_read16(CAN0_MB12_LENGTH)
-#define bfin_write_CAN0_MB12_LENGTH(val) bfin_write16(CAN0_MB12_LENGTH, val)
-#define bfin_read_CAN0_MB12_TIMESTAMP() bfin_read16(CAN0_MB12_TIMESTAMP)
-#define bfin_write_CAN0_MB12_TIMESTAMP(val) bfin_write16(CAN0_MB12_TIMESTAMP, val)
-#define bfin_read_CAN0_MB12_ID0() bfin_read16(CAN0_MB12_ID0)
-#define bfin_write_CAN0_MB12_ID0(val) bfin_write16(CAN0_MB12_ID0, val)
-#define bfin_read_CAN0_MB12_ID1() bfin_read16(CAN0_MB12_ID1)
-#define bfin_write_CAN0_MB12_ID1(val) bfin_write16(CAN0_MB12_ID1, val)
-#define bfin_read_CAN0_MB13_DATA0() bfin_read16(CAN0_MB13_DATA0)
-#define bfin_write_CAN0_MB13_DATA0(val) bfin_write16(CAN0_MB13_DATA0, val)
-#define bfin_read_CAN0_MB13_DATA1() bfin_read16(CAN0_MB13_DATA1)
-#define bfin_write_CAN0_MB13_DATA1(val) bfin_write16(CAN0_MB13_DATA1, val)
-#define bfin_read_CAN0_MB13_DATA2() bfin_read16(CAN0_MB13_DATA2)
-#define bfin_write_CAN0_MB13_DATA2(val) bfin_write16(CAN0_MB13_DATA2, val)
-#define bfin_read_CAN0_MB13_DATA3() bfin_read16(CAN0_MB13_DATA3)
-#define bfin_write_CAN0_MB13_DATA3(val) bfin_write16(CAN0_MB13_DATA3, val)
-#define bfin_read_CAN0_MB13_LENGTH() bfin_read16(CAN0_MB13_LENGTH)
-#define bfin_write_CAN0_MB13_LENGTH(val) bfin_write16(CAN0_MB13_LENGTH, val)
-#define bfin_read_CAN0_MB13_TIMESTAMP() bfin_read16(CAN0_MB13_TIMESTAMP)
-#define bfin_write_CAN0_MB13_TIMESTAMP(val) bfin_write16(CAN0_MB13_TIMESTAMP, val)
-#define bfin_read_CAN0_MB13_ID0() bfin_read16(CAN0_MB13_ID0)
-#define bfin_write_CAN0_MB13_ID0(val) bfin_write16(CAN0_MB13_ID0, val)
-#define bfin_read_CAN0_MB13_ID1() bfin_read16(CAN0_MB13_ID1)
-#define bfin_write_CAN0_MB13_ID1(val) bfin_write16(CAN0_MB13_ID1, val)
-#define bfin_read_CAN0_MB14_DATA0() bfin_read16(CAN0_MB14_DATA0)
-#define bfin_write_CAN0_MB14_DATA0(val) bfin_write16(CAN0_MB14_DATA0, val)
-#define bfin_read_CAN0_MB14_DATA1() bfin_read16(CAN0_MB14_DATA1)
-#define bfin_write_CAN0_MB14_DATA1(val) bfin_write16(CAN0_MB14_DATA1, val)
-#define bfin_read_CAN0_MB14_DATA2() bfin_read16(CAN0_MB14_DATA2)
-#define bfin_write_CAN0_MB14_DATA2(val) bfin_write16(CAN0_MB14_DATA2, val)
-#define bfin_read_CAN0_MB14_DATA3() bfin_read16(CAN0_MB14_DATA3)
-#define bfin_write_CAN0_MB14_DATA3(val) bfin_write16(CAN0_MB14_DATA3, val)
-#define bfin_read_CAN0_MB14_LENGTH() bfin_read16(CAN0_MB14_LENGTH)
-#define bfin_write_CAN0_MB14_LENGTH(val) bfin_write16(CAN0_MB14_LENGTH, val)
-#define bfin_read_CAN0_MB14_TIMESTAMP() bfin_read16(CAN0_MB14_TIMESTAMP)
-#define bfin_write_CAN0_MB14_TIMESTAMP(val) bfin_write16(CAN0_MB14_TIMESTAMP, val)
-#define bfin_read_CAN0_MB14_ID0() bfin_read16(CAN0_MB14_ID0)
-#define bfin_write_CAN0_MB14_ID0(val) bfin_write16(CAN0_MB14_ID0, val)
-#define bfin_read_CAN0_MB14_ID1() bfin_read16(CAN0_MB14_ID1)
-#define bfin_write_CAN0_MB14_ID1(val) bfin_write16(CAN0_MB14_ID1, val)
-#define bfin_read_CAN0_MB15_DATA0() bfin_read16(CAN0_MB15_DATA0)
-#define bfin_write_CAN0_MB15_DATA0(val) bfin_write16(CAN0_MB15_DATA0, val)
-#define bfin_read_CAN0_MB15_DATA1() bfin_read16(CAN0_MB15_DATA1)
-#define bfin_write_CAN0_MB15_DATA1(val) bfin_write16(CAN0_MB15_DATA1, val)
-#define bfin_read_CAN0_MB15_DATA2() bfin_read16(CAN0_MB15_DATA2)
-#define bfin_write_CAN0_MB15_DATA2(val) bfin_write16(CAN0_MB15_DATA2, val)
-#define bfin_read_CAN0_MB15_DATA3() bfin_read16(CAN0_MB15_DATA3)
-#define bfin_write_CAN0_MB15_DATA3(val) bfin_write16(CAN0_MB15_DATA3, val)
-#define bfin_read_CAN0_MB15_LENGTH() bfin_read16(CAN0_MB15_LENGTH)
-#define bfin_write_CAN0_MB15_LENGTH(val) bfin_write16(CAN0_MB15_LENGTH, val)
-#define bfin_read_CAN0_MB15_TIMESTAMP() bfin_read16(CAN0_MB15_TIMESTAMP)
-#define bfin_write_CAN0_MB15_TIMESTAMP(val) bfin_write16(CAN0_MB15_TIMESTAMP, val)
-#define bfin_read_CAN0_MB15_ID0() bfin_read16(CAN0_MB15_ID0)
-#define bfin_write_CAN0_MB15_ID0(val) bfin_write16(CAN0_MB15_ID0, val)
-#define bfin_read_CAN0_MB15_ID1() bfin_read16(CAN0_MB15_ID1)
-#define bfin_write_CAN0_MB15_ID1(val) bfin_write16(CAN0_MB15_ID1, val)
-
-/* CAN Controller 0 Mailbox Data Registers */
-
-#define bfin_read_CAN0_MB16_DATA0() bfin_read16(CAN0_MB16_DATA0)
-#define bfin_write_CAN0_MB16_DATA0(val) bfin_write16(CAN0_MB16_DATA0, val)
-#define bfin_read_CAN0_MB16_DATA1() bfin_read16(CAN0_MB16_DATA1)
-#define bfin_write_CAN0_MB16_DATA1(val) bfin_write16(CAN0_MB16_DATA1, val)
-#define bfin_read_CAN0_MB16_DATA2() bfin_read16(CAN0_MB16_DATA2)
-#define bfin_write_CAN0_MB16_DATA2(val) bfin_write16(CAN0_MB16_DATA2, val)
-#define bfin_read_CAN0_MB16_DATA3() bfin_read16(CAN0_MB16_DATA3)
-#define bfin_write_CAN0_MB16_DATA3(val) bfin_write16(CAN0_MB16_DATA3, val)
-#define bfin_read_CAN0_MB16_LENGTH() bfin_read16(CAN0_MB16_LENGTH)
-#define bfin_write_CAN0_MB16_LENGTH(val) bfin_write16(CAN0_MB16_LENGTH, val)
-#define bfin_read_CAN0_MB16_TIMESTAMP() bfin_read16(CAN0_MB16_TIMESTAMP)
-#define bfin_write_CAN0_MB16_TIMESTAMP(val) bfin_write16(CAN0_MB16_TIMESTAMP, val)
-#define bfin_read_CAN0_MB16_ID0() bfin_read16(CAN0_MB16_ID0)
-#define bfin_write_CAN0_MB16_ID0(val) bfin_write16(CAN0_MB16_ID0, val)
-#define bfin_read_CAN0_MB16_ID1() bfin_read16(CAN0_MB16_ID1)
-#define bfin_write_CAN0_MB16_ID1(val) bfin_write16(CAN0_MB16_ID1, val)
-#define bfin_read_CAN0_MB17_DATA0() bfin_read16(CAN0_MB17_DATA0)
-#define bfin_write_CAN0_MB17_DATA0(val) bfin_write16(CAN0_MB17_DATA0, val)
-#define bfin_read_CAN0_MB17_DATA1() bfin_read16(CAN0_MB17_DATA1)
-#define bfin_write_CAN0_MB17_DATA1(val) bfin_write16(CAN0_MB17_DATA1, val)
-#define bfin_read_CAN0_MB17_DATA2() bfin_read16(CAN0_MB17_DATA2)
-#define bfin_write_CAN0_MB17_DATA2(val) bfin_write16(CAN0_MB17_DATA2, val)
-#define bfin_read_CAN0_MB17_DATA3() bfin_read16(CAN0_MB17_DATA3)
-#define bfin_write_CAN0_MB17_DATA3(val) bfin_write16(CAN0_MB17_DATA3, val)
-#define bfin_read_CAN0_MB17_LENGTH() bfin_read16(CAN0_MB17_LENGTH)
-#define bfin_write_CAN0_MB17_LENGTH(val) bfin_write16(CAN0_MB17_LENGTH, val)
-#define bfin_read_CAN0_MB17_TIMESTAMP() bfin_read16(CAN0_MB17_TIMESTAMP)
-#define bfin_write_CAN0_MB17_TIMESTAMP(val) bfin_write16(CAN0_MB17_TIMESTAMP, val)
-#define bfin_read_CAN0_MB17_ID0() bfin_read16(CAN0_MB17_ID0)
-#define bfin_write_CAN0_MB17_ID0(val) bfin_write16(CAN0_MB17_ID0, val)
-#define bfin_read_CAN0_MB17_ID1() bfin_read16(CAN0_MB17_ID1)
-#define bfin_write_CAN0_MB17_ID1(val) bfin_write16(CAN0_MB17_ID1, val)
-#define bfin_read_CAN0_MB18_DATA0() bfin_read16(CAN0_MB18_DATA0)
-#define bfin_write_CAN0_MB18_DATA0(val) bfin_write16(CAN0_MB18_DATA0, val)
-#define bfin_read_CAN0_MB18_DATA1() bfin_read16(CAN0_MB18_DATA1)
-#define bfin_write_CAN0_MB18_DATA1(val) bfin_write16(CAN0_MB18_DATA1, val)
-#define bfin_read_CAN0_MB18_DATA2() bfin_read16(CAN0_MB18_DATA2)
-#define bfin_write_CAN0_MB18_DATA2(val) bfin_write16(CAN0_MB18_DATA2, val)
-#define bfin_read_CAN0_MB18_DATA3() bfin_read16(CAN0_MB18_DATA3)
-#define bfin_write_CAN0_MB18_DATA3(val) bfin_write16(CAN0_MB18_DATA3, val)
-#define bfin_read_CAN0_MB18_LENGTH() bfin_read16(CAN0_MB18_LENGTH)
-#define bfin_write_CAN0_MB18_LENGTH(val) bfin_write16(CAN0_MB18_LENGTH, val)
-#define bfin_read_CAN0_MB18_TIMESTAMP() bfin_read16(CAN0_MB18_TIMESTAMP)
-#define bfin_write_CAN0_MB18_TIMESTAMP(val) bfin_write16(CAN0_MB18_TIMESTAMP, val)
-#define bfin_read_CAN0_MB18_ID0() bfin_read16(CAN0_MB18_ID0)
-#define bfin_write_CAN0_MB18_ID0(val) bfin_write16(CAN0_MB18_ID0, val)
-#define bfin_read_CAN0_MB18_ID1() bfin_read16(CAN0_MB18_ID1)
-#define bfin_write_CAN0_MB18_ID1(val) bfin_write16(CAN0_MB18_ID1, val)
-#define bfin_read_CAN0_MB19_DATA0() bfin_read16(CAN0_MB19_DATA0)
-#define bfin_write_CAN0_MB19_DATA0(val) bfin_write16(CAN0_MB19_DATA0, val)
-#define bfin_read_CAN0_MB19_DATA1() bfin_read16(CAN0_MB19_DATA1)
-#define bfin_write_CAN0_MB19_DATA1(val) bfin_write16(CAN0_MB19_DATA1, val)
-#define bfin_read_CAN0_MB19_DATA2() bfin_read16(CAN0_MB19_DATA2)
-#define bfin_write_CAN0_MB19_DATA2(val) bfin_write16(CAN0_MB19_DATA2, val)
-#define bfin_read_CAN0_MB19_DATA3() bfin_read16(CAN0_MB19_DATA3)
-#define bfin_write_CAN0_MB19_DATA3(val) bfin_write16(CAN0_MB19_DATA3, val)
-#define bfin_read_CAN0_MB19_LENGTH() bfin_read16(CAN0_MB19_LENGTH)
-#define bfin_write_CAN0_MB19_LENGTH(val) bfin_write16(CAN0_MB19_LENGTH, val)
-#define bfin_read_CAN0_MB19_TIMESTAMP() bfin_read16(CAN0_MB19_TIMESTAMP)
-#define bfin_write_CAN0_MB19_TIMESTAMP(val) bfin_write16(CAN0_MB19_TIMESTAMP, val)
-#define bfin_read_CAN0_MB19_ID0() bfin_read16(CAN0_MB19_ID0)
-#define bfin_write_CAN0_MB19_ID0(val) bfin_write16(CAN0_MB19_ID0, val)
-#define bfin_read_CAN0_MB19_ID1() bfin_read16(CAN0_MB19_ID1)
-#define bfin_write_CAN0_MB19_ID1(val) bfin_write16(CAN0_MB19_ID1, val)
-#define bfin_read_CAN0_MB20_DATA0() bfin_read16(CAN0_MB20_DATA0)
-#define bfin_write_CAN0_MB20_DATA0(val) bfin_write16(CAN0_MB20_DATA0, val)
-#define bfin_read_CAN0_MB20_DATA1() bfin_read16(CAN0_MB20_DATA1)
-#define bfin_write_CAN0_MB20_DATA1(val) bfin_write16(CAN0_MB20_DATA1, val)
-#define bfin_read_CAN0_MB20_DATA2() bfin_read16(CAN0_MB20_DATA2)
-#define bfin_write_CAN0_MB20_DATA2(val) bfin_write16(CAN0_MB20_DATA2, val)
-#define bfin_read_CAN0_MB20_DATA3() bfin_read16(CAN0_MB20_DATA3)
-#define bfin_write_CAN0_MB20_DATA3(val) bfin_write16(CAN0_MB20_DATA3, val)
-#define bfin_read_CAN0_MB20_LENGTH() bfin_read16(CAN0_MB20_LENGTH)
-#define bfin_write_CAN0_MB20_LENGTH(val) bfin_write16(CAN0_MB20_LENGTH, val)
-#define bfin_read_CAN0_MB20_TIMESTAMP() bfin_read16(CAN0_MB20_TIMESTAMP)
-#define bfin_write_CAN0_MB20_TIMESTAMP(val) bfin_write16(CAN0_MB20_TIMESTAMP, val)
-#define bfin_read_CAN0_MB20_ID0() bfin_read16(CAN0_MB20_ID0)
-#define bfin_write_CAN0_MB20_ID0(val) bfin_write16(CAN0_MB20_ID0, val)
-#define bfin_read_CAN0_MB20_ID1() bfin_read16(CAN0_MB20_ID1)
-#define bfin_write_CAN0_MB20_ID1(val) bfin_write16(CAN0_MB20_ID1, val)
-#define bfin_read_CAN0_MB21_DATA0() bfin_read16(CAN0_MB21_DATA0)
-#define bfin_write_CAN0_MB21_DATA0(val) bfin_write16(CAN0_MB21_DATA0, val)
-#define bfin_read_CAN0_MB21_DATA1() bfin_read16(CAN0_MB21_DATA1)
-#define bfin_write_CAN0_MB21_DATA1(val) bfin_write16(CAN0_MB21_DATA1, val)
-#define bfin_read_CAN0_MB21_DATA2() bfin_read16(CAN0_MB21_DATA2)
-#define bfin_write_CAN0_MB21_DATA2(val) bfin_write16(CAN0_MB21_DATA2, val)
-#define bfin_read_CAN0_MB21_DATA3() bfin_read16(CAN0_MB21_DATA3)
-#define bfin_write_CAN0_MB21_DATA3(val) bfin_write16(CAN0_MB21_DATA3, val)
-#define bfin_read_CAN0_MB21_LENGTH() bfin_read16(CAN0_MB21_LENGTH)
-#define bfin_write_CAN0_MB21_LENGTH(val) bfin_write16(CAN0_MB21_LENGTH, val)
-#define bfin_read_CAN0_MB21_TIMESTAMP() bfin_read16(CAN0_MB21_TIMESTAMP)
-#define bfin_write_CAN0_MB21_TIMESTAMP(val) bfin_write16(CAN0_MB21_TIMESTAMP, val)
-#define bfin_read_CAN0_MB21_ID0() bfin_read16(CAN0_MB21_ID0)
-#define bfin_write_CAN0_MB21_ID0(val) bfin_write16(CAN0_MB21_ID0, val)
-#define bfin_read_CAN0_MB21_ID1() bfin_read16(CAN0_MB21_ID1)
-#define bfin_write_CAN0_MB21_ID1(val) bfin_write16(CAN0_MB21_ID1, val)
-#define bfin_read_CAN0_MB22_DATA0() bfin_read16(CAN0_MB22_DATA0)
-#define bfin_write_CAN0_MB22_DATA0(val) bfin_write16(CAN0_MB22_DATA0, val)
-#define bfin_read_CAN0_MB22_DATA1() bfin_read16(CAN0_MB22_DATA1)
-#define bfin_write_CAN0_MB22_DATA1(val) bfin_write16(CAN0_MB22_DATA1, val)
-#define bfin_read_CAN0_MB22_DATA2() bfin_read16(CAN0_MB22_DATA2)
-#define bfin_write_CAN0_MB22_DATA2(val) bfin_write16(CAN0_MB22_DATA2, val)
-#define bfin_read_CAN0_MB22_DATA3() bfin_read16(CAN0_MB22_DATA3)
-#define bfin_write_CAN0_MB22_DATA3(val) bfin_write16(CAN0_MB22_DATA3, val)
-#define bfin_read_CAN0_MB22_LENGTH() bfin_read16(CAN0_MB22_LENGTH)
-#define bfin_write_CAN0_MB22_LENGTH(val) bfin_write16(CAN0_MB22_LENGTH, val)
-#define bfin_read_CAN0_MB22_TIMESTAMP() bfin_read16(CAN0_MB22_TIMESTAMP)
-#define bfin_write_CAN0_MB22_TIMESTAMP(val) bfin_write16(CAN0_MB22_TIMESTAMP, val)
-#define bfin_read_CAN0_MB22_ID0() bfin_read16(CAN0_MB22_ID0)
-#define bfin_write_CAN0_MB22_ID0(val) bfin_write16(CAN0_MB22_ID0, val)
-#define bfin_read_CAN0_MB22_ID1() bfin_read16(CAN0_MB22_ID1)
-#define bfin_write_CAN0_MB22_ID1(val) bfin_write16(CAN0_MB22_ID1, val)
-#define bfin_read_CAN0_MB23_DATA0() bfin_read16(CAN0_MB23_DATA0)
-#define bfin_write_CAN0_MB23_DATA0(val) bfin_write16(CAN0_MB23_DATA0, val)
-#define bfin_read_CAN0_MB23_DATA1() bfin_read16(CAN0_MB23_DATA1)
-#define bfin_write_CAN0_MB23_DATA1(val) bfin_write16(CAN0_MB23_DATA1, val)
-#define bfin_read_CAN0_MB23_DATA2() bfin_read16(CAN0_MB23_DATA2)
-#define bfin_write_CAN0_MB23_DATA2(val) bfin_write16(CAN0_MB23_DATA2, val)
-#define bfin_read_CAN0_MB23_DATA3() bfin_read16(CAN0_MB23_DATA3)
-#define bfin_write_CAN0_MB23_DATA3(val) bfin_write16(CAN0_MB23_DATA3, val)
-#define bfin_read_CAN0_MB23_LENGTH() bfin_read16(CAN0_MB23_LENGTH)
-#define bfin_write_CAN0_MB23_LENGTH(val) bfin_write16(CAN0_MB23_LENGTH, val)
-#define bfin_read_CAN0_MB23_TIMESTAMP() bfin_read16(CAN0_MB23_TIMESTAMP)
-#define bfin_write_CAN0_MB23_TIMESTAMP(val) bfin_write16(CAN0_MB23_TIMESTAMP, val)
-#define bfin_read_CAN0_MB23_ID0() bfin_read16(CAN0_MB23_ID0)
-#define bfin_write_CAN0_MB23_ID0(val) bfin_write16(CAN0_MB23_ID0, val)
-#define bfin_read_CAN0_MB23_ID1() bfin_read16(CAN0_MB23_ID1)
-#define bfin_write_CAN0_MB23_ID1(val) bfin_write16(CAN0_MB23_ID1, val)
-#define bfin_read_CAN0_MB24_DATA0() bfin_read16(CAN0_MB24_DATA0)
-#define bfin_write_CAN0_MB24_DATA0(val) bfin_write16(CAN0_MB24_DATA0, val)
-#define bfin_read_CAN0_MB24_DATA1() bfin_read16(CAN0_MB24_DATA1)
-#define bfin_write_CAN0_MB24_DATA1(val) bfin_write16(CAN0_MB24_DATA1, val)
-#define bfin_read_CAN0_MB24_DATA2() bfin_read16(CAN0_MB24_DATA2)
-#define bfin_write_CAN0_MB24_DATA2(val) bfin_write16(CAN0_MB24_DATA2, val)
-#define bfin_read_CAN0_MB24_DATA3() bfin_read16(CAN0_MB24_DATA3)
-#define bfin_write_CAN0_MB24_DATA3(val) bfin_write16(CAN0_MB24_DATA3, val)
-#define bfin_read_CAN0_MB24_LENGTH() bfin_read16(CAN0_MB24_LENGTH)
-#define bfin_write_CAN0_MB24_LENGTH(val) bfin_write16(CAN0_MB24_LENGTH, val)
-#define bfin_read_CAN0_MB24_TIMESTAMP() bfin_read16(CAN0_MB24_TIMESTAMP)
-#define bfin_write_CAN0_MB24_TIMESTAMP(val) bfin_write16(CAN0_MB24_TIMESTAMP, val)
-#define bfin_read_CAN0_MB24_ID0() bfin_read16(CAN0_MB24_ID0)
-#define bfin_write_CAN0_MB24_ID0(val) bfin_write16(CAN0_MB24_ID0, val)
-#define bfin_read_CAN0_MB24_ID1() bfin_read16(CAN0_MB24_ID1)
-#define bfin_write_CAN0_MB24_ID1(val) bfin_write16(CAN0_MB24_ID1, val)
-#define bfin_read_CAN0_MB25_DATA0() bfin_read16(CAN0_MB25_DATA0)
-#define bfin_write_CAN0_MB25_DATA0(val) bfin_write16(CAN0_MB25_DATA0, val)
-#define bfin_read_CAN0_MB25_DATA1() bfin_read16(CAN0_MB25_DATA1)
-#define bfin_write_CAN0_MB25_DATA1(val) bfin_write16(CAN0_MB25_DATA1, val)
-#define bfin_read_CAN0_MB25_DATA2() bfin_read16(CAN0_MB25_DATA2)
-#define bfin_write_CAN0_MB25_DATA2(val) bfin_write16(CAN0_MB25_DATA2, val)
-#define bfin_read_CAN0_MB25_DATA3() bfin_read16(CAN0_MB25_DATA3)
-#define bfin_write_CAN0_MB25_DATA3(val) bfin_write16(CAN0_MB25_DATA3, val)
-#define bfin_read_CAN0_MB25_LENGTH() bfin_read16(CAN0_MB25_LENGTH)
-#define bfin_write_CAN0_MB25_LENGTH(val) bfin_write16(CAN0_MB25_LENGTH, val)
-#define bfin_read_CAN0_MB25_TIMESTAMP() bfin_read16(CAN0_MB25_TIMESTAMP)
-#define bfin_write_CAN0_MB25_TIMESTAMP(val) bfin_write16(CAN0_MB25_TIMESTAMP, val)
-#define bfin_read_CAN0_MB25_ID0() bfin_read16(CAN0_MB25_ID0)
-#define bfin_write_CAN0_MB25_ID0(val) bfin_write16(CAN0_MB25_ID0, val)
-#define bfin_read_CAN0_MB25_ID1() bfin_read16(CAN0_MB25_ID1)
-#define bfin_write_CAN0_MB25_ID1(val) bfin_write16(CAN0_MB25_ID1, val)
-#define bfin_read_CAN0_MB26_DATA0() bfin_read16(CAN0_MB26_DATA0)
-#define bfin_write_CAN0_MB26_DATA0(val) bfin_write16(CAN0_MB26_DATA0, val)
-#define bfin_read_CAN0_MB26_DATA1() bfin_read16(CAN0_MB26_DATA1)
-#define bfin_write_CAN0_MB26_DATA1(val) bfin_write16(CAN0_MB26_DATA1, val)
-#define bfin_read_CAN0_MB26_DATA2() bfin_read16(CAN0_MB26_DATA2)
-#define bfin_write_CAN0_MB26_DATA2(val) bfin_write16(CAN0_MB26_DATA2, val)
-#define bfin_read_CAN0_MB26_DATA3() bfin_read16(CAN0_MB26_DATA3)
-#define bfin_write_CAN0_MB26_DATA3(val) bfin_write16(CAN0_MB26_DATA3, val)
-#define bfin_read_CAN0_MB26_LENGTH() bfin_read16(CAN0_MB26_LENGTH)
-#define bfin_write_CAN0_MB26_LENGTH(val) bfin_write16(CAN0_MB26_LENGTH, val)
-#define bfin_read_CAN0_MB26_TIMESTAMP() bfin_read16(CAN0_MB26_TIMESTAMP)
-#define bfin_write_CAN0_MB26_TIMESTAMP(val) bfin_write16(CAN0_MB26_TIMESTAMP, val)
-#define bfin_read_CAN0_MB26_ID0() bfin_read16(CAN0_MB26_ID0)
-#define bfin_write_CAN0_MB26_ID0(val) bfin_write16(CAN0_MB26_ID0, val)
-#define bfin_read_CAN0_MB26_ID1() bfin_read16(CAN0_MB26_ID1)
-#define bfin_write_CAN0_MB26_ID1(val) bfin_write16(CAN0_MB26_ID1, val)
-#define bfin_read_CAN0_MB27_DATA0() bfin_read16(CAN0_MB27_DATA0)
-#define bfin_write_CAN0_MB27_DATA0(val) bfin_write16(CAN0_MB27_DATA0, val)
-#define bfin_read_CAN0_MB27_DATA1() bfin_read16(CAN0_MB27_DATA1)
-#define bfin_write_CAN0_MB27_DATA1(val) bfin_write16(CAN0_MB27_DATA1, val)
-#define bfin_read_CAN0_MB27_DATA2() bfin_read16(CAN0_MB27_DATA2)
-#define bfin_write_CAN0_MB27_DATA2(val) bfin_write16(CAN0_MB27_DATA2, val)
-#define bfin_read_CAN0_MB27_DATA3() bfin_read16(CAN0_MB27_DATA3)
-#define bfin_write_CAN0_MB27_DATA3(val) bfin_write16(CAN0_MB27_DATA3, val)
-#define bfin_read_CAN0_MB27_LENGTH() bfin_read16(CAN0_MB27_LENGTH)
-#define bfin_write_CAN0_MB27_LENGTH(val) bfin_write16(CAN0_MB27_LENGTH, val)
-#define bfin_read_CAN0_MB27_TIMESTAMP() bfin_read16(CAN0_MB27_TIMESTAMP)
-#define bfin_write_CAN0_MB27_TIMESTAMP(val) bfin_write16(CAN0_MB27_TIMESTAMP, val)
-#define bfin_read_CAN0_MB27_ID0() bfin_read16(CAN0_MB27_ID0)
-#define bfin_write_CAN0_MB27_ID0(val) bfin_write16(CAN0_MB27_ID0, val)
-#define bfin_read_CAN0_MB27_ID1() bfin_read16(CAN0_MB27_ID1)
-#define bfin_write_CAN0_MB27_ID1(val) bfin_write16(CAN0_MB27_ID1, val)
-#define bfin_read_CAN0_MB28_DATA0() bfin_read16(CAN0_MB28_DATA0)
-#define bfin_write_CAN0_MB28_DATA0(val) bfin_write16(CAN0_MB28_DATA0, val)
-#define bfin_read_CAN0_MB28_DATA1() bfin_read16(CAN0_MB28_DATA1)
-#define bfin_write_CAN0_MB28_DATA1(val) bfin_write16(CAN0_MB28_DATA1, val)
-#define bfin_read_CAN0_MB28_DATA2() bfin_read16(CAN0_MB28_DATA2)
-#define bfin_write_CAN0_MB28_DATA2(val) bfin_write16(CAN0_MB28_DATA2, val)
-#define bfin_read_CAN0_MB28_DATA3() bfin_read16(CAN0_MB28_DATA3)
-#define bfin_write_CAN0_MB28_DATA3(val) bfin_write16(CAN0_MB28_DATA3, val)
-#define bfin_read_CAN0_MB28_LENGTH() bfin_read16(CAN0_MB28_LENGTH)
-#define bfin_write_CAN0_MB28_LENGTH(val) bfin_write16(CAN0_MB28_LENGTH, val)
-#define bfin_read_CAN0_MB28_TIMESTAMP() bfin_read16(CAN0_MB28_TIMESTAMP)
-#define bfin_write_CAN0_MB28_TIMESTAMP(val) bfin_write16(CAN0_MB28_TIMESTAMP, val)
-#define bfin_read_CAN0_MB28_ID0() bfin_read16(CAN0_MB28_ID0)
-#define bfin_write_CAN0_MB28_ID0(val) bfin_write16(CAN0_MB28_ID0, val)
-#define bfin_read_CAN0_MB28_ID1() bfin_read16(CAN0_MB28_ID1)
-#define bfin_write_CAN0_MB28_ID1(val) bfin_write16(CAN0_MB28_ID1, val)
-#define bfin_read_CAN0_MB29_DATA0() bfin_read16(CAN0_MB29_DATA0)
-#define bfin_write_CAN0_MB29_DATA0(val) bfin_write16(CAN0_MB29_DATA0, val)
-#define bfin_read_CAN0_MB29_DATA1() bfin_read16(CAN0_MB29_DATA1)
-#define bfin_write_CAN0_MB29_DATA1(val) bfin_write16(CAN0_MB29_DATA1, val)
-#define bfin_read_CAN0_MB29_DATA2() bfin_read16(CAN0_MB29_DATA2)
-#define bfin_write_CAN0_MB29_DATA2(val) bfin_write16(CAN0_MB29_DATA2, val)
-#define bfin_read_CAN0_MB29_DATA3() bfin_read16(CAN0_MB29_DATA3)
-#define bfin_write_CAN0_MB29_DATA3(val) bfin_write16(CAN0_MB29_DATA3, val)
-#define bfin_read_CAN0_MB29_LENGTH() bfin_read16(CAN0_MB29_LENGTH)
-#define bfin_write_CAN0_MB29_LENGTH(val) bfin_write16(CAN0_MB29_LENGTH, val)
-#define bfin_read_CAN0_MB29_TIMESTAMP() bfin_read16(CAN0_MB29_TIMESTAMP)
-#define bfin_write_CAN0_MB29_TIMESTAMP(val) bfin_write16(CAN0_MB29_TIMESTAMP, val)
-#define bfin_read_CAN0_MB29_ID0() bfin_read16(CAN0_MB29_ID0)
-#define bfin_write_CAN0_MB29_ID0(val) bfin_write16(CAN0_MB29_ID0, val)
-#define bfin_read_CAN0_MB29_ID1() bfin_read16(CAN0_MB29_ID1)
-#define bfin_write_CAN0_MB29_ID1(val) bfin_write16(CAN0_MB29_ID1, val)
-#define bfin_read_CAN0_MB30_DATA0() bfin_read16(CAN0_MB30_DATA0)
-#define bfin_write_CAN0_MB30_DATA0(val) bfin_write16(CAN0_MB30_DATA0, val)
-#define bfin_read_CAN0_MB30_DATA1() bfin_read16(CAN0_MB30_DATA1)
-#define bfin_write_CAN0_MB30_DATA1(val) bfin_write16(CAN0_MB30_DATA1, val)
-#define bfin_read_CAN0_MB30_DATA2() bfin_read16(CAN0_MB30_DATA2)
-#define bfin_write_CAN0_MB30_DATA2(val) bfin_write16(CAN0_MB30_DATA2, val)
-#define bfin_read_CAN0_MB30_DATA3() bfin_read16(CAN0_MB30_DATA3)
-#define bfin_write_CAN0_MB30_DATA3(val) bfin_write16(CAN0_MB30_DATA3, val)
-#define bfin_read_CAN0_MB30_LENGTH() bfin_read16(CAN0_MB30_LENGTH)
-#define bfin_write_CAN0_MB30_LENGTH(val) bfin_write16(CAN0_MB30_LENGTH, val)
-#define bfin_read_CAN0_MB30_TIMESTAMP() bfin_read16(CAN0_MB30_TIMESTAMP)
-#define bfin_write_CAN0_MB30_TIMESTAMP(val) bfin_write16(CAN0_MB30_TIMESTAMP, val)
-#define bfin_read_CAN0_MB30_ID0() bfin_read16(CAN0_MB30_ID0)
-#define bfin_write_CAN0_MB30_ID0(val) bfin_write16(CAN0_MB30_ID0, val)
-#define bfin_read_CAN0_MB30_ID1() bfin_read16(CAN0_MB30_ID1)
-#define bfin_write_CAN0_MB30_ID1(val) bfin_write16(CAN0_MB30_ID1, val)
-#define bfin_read_CAN0_MB31_DATA0() bfin_read16(CAN0_MB31_DATA0)
-#define bfin_write_CAN0_MB31_DATA0(val) bfin_write16(CAN0_MB31_DATA0, val)
-#define bfin_read_CAN0_MB31_DATA1() bfin_read16(CAN0_MB31_DATA1)
-#define bfin_write_CAN0_MB31_DATA1(val) bfin_write16(CAN0_MB31_DATA1, val)
-#define bfin_read_CAN0_MB31_DATA2() bfin_read16(CAN0_MB31_DATA2)
-#define bfin_write_CAN0_MB31_DATA2(val) bfin_write16(CAN0_MB31_DATA2, val)
-#define bfin_read_CAN0_MB31_DATA3() bfin_read16(CAN0_MB31_DATA3)
-#define bfin_write_CAN0_MB31_DATA3(val) bfin_write16(CAN0_MB31_DATA3, val)
-#define bfin_read_CAN0_MB31_LENGTH() bfin_read16(CAN0_MB31_LENGTH)
-#define bfin_write_CAN0_MB31_LENGTH(val) bfin_write16(CAN0_MB31_LENGTH, val)
-#define bfin_read_CAN0_MB31_TIMESTAMP() bfin_read16(CAN0_MB31_TIMESTAMP)
-#define bfin_write_CAN0_MB31_TIMESTAMP(val) bfin_write16(CAN0_MB31_TIMESTAMP, val)
-#define bfin_read_CAN0_MB31_ID0() bfin_read16(CAN0_MB31_ID0)
-#define bfin_write_CAN0_MB31_ID0(val) bfin_write16(CAN0_MB31_ID0, val)
-#define bfin_read_CAN0_MB31_ID1() bfin_read16(CAN0_MB31_ID1)
-#define bfin_write_CAN0_MB31_ID1(val) bfin_write16(CAN0_MB31_ID1, val)
-
-/* UART3 Registers */
-
-#define bfin_read_UART3_DLL() bfin_read16(UART3_DLL)
-#define bfin_write_UART3_DLL(val) bfin_write16(UART3_DLL, val)
-#define bfin_read_UART3_DLH() bfin_read16(UART3_DLH)
-#define bfin_write_UART3_DLH(val) bfin_write16(UART3_DLH, val)
-#define bfin_read_UART3_GCTL() bfin_read16(UART3_GCTL)
-#define bfin_write_UART3_GCTL(val) bfin_write16(UART3_GCTL, val)
-#define bfin_read_UART3_LCR() bfin_read16(UART3_LCR)
-#define bfin_write_UART3_LCR(val) bfin_write16(UART3_LCR, val)
-#define bfin_read_UART3_MCR() bfin_read16(UART3_MCR)
-#define bfin_write_UART3_MCR(val) bfin_write16(UART3_MCR, val)
-#define bfin_read_UART3_LSR() bfin_read16(UART3_LSR)
-#define bfin_write_UART3_LSR(val) bfin_write16(UART3_LSR, val)
-#define bfin_read_UART3_MSR() bfin_read16(UART3_MSR)
-#define bfin_write_UART3_MSR(val) bfin_write16(UART3_MSR, val)
-#define bfin_read_UART3_SCR() bfin_read16(UART3_SCR)
-#define bfin_write_UART3_SCR(val) bfin_write16(UART3_SCR, val)
-#define bfin_read_UART3_IER_SET() bfin_read16(UART3_IER_SET)
-#define bfin_write_UART3_IER_SET(val) bfin_write16(UART3_IER_SET, val)
-#define bfin_read_UART3_IER_CLEAR() bfin_read16(UART3_IER_CLEAR)
-#define bfin_write_UART3_IER_CLEAR(val) bfin_write16(UART3_IER_CLEAR, val)
-#define bfin_read_UART3_THR() bfin_read16(UART3_THR)
-#define bfin_write_UART3_THR(val) bfin_write16(UART3_THR, val)
-#define bfin_read_UART3_RBR() bfin_read16(UART3_RBR)
-#define bfin_write_UART3_RBR(val) bfin_write16(UART3_RBR, val)
-
-/* NFC Registers */
-
-#define bfin_read_NFC_CTL() bfin_read16(NFC_CTL)
-#define bfin_write_NFC_CTL(val) bfin_write16(NFC_CTL, val)
-#define bfin_read_NFC_STAT() bfin_read16(NFC_STAT)
-#define bfin_write_NFC_STAT(val) bfin_write16(NFC_STAT, val)
-#define bfin_read_NFC_IRQSTAT() bfin_read16(NFC_IRQSTAT)
-#define bfin_write_NFC_IRQSTAT(val) bfin_write16(NFC_IRQSTAT, val)
-#define bfin_read_NFC_IRQMASK() bfin_read16(NFC_IRQMASK)
-#define bfin_write_NFC_IRQMASK(val) bfin_write16(NFC_IRQMASK, val)
-#define bfin_read_NFC_ECC0() bfin_read16(NFC_ECC0)
-#define bfin_write_NFC_ECC0(val) bfin_write16(NFC_ECC0, val)
-#define bfin_read_NFC_ECC1() bfin_read16(NFC_ECC1)
-#define bfin_write_NFC_ECC1(val) bfin_write16(NFC_ECC1, val)
-#define bfin_read_NFC_ECC2() bfin_read16(NFC_ECC2)
-#define bfin_write_NFC_ECC2(val) bfin_write16(NFC_ECC2, val)
-#define bfin_read_NFC_ECC3() bfin_read16(NFC_ECC3)
-#define bfin_write_NFC_ECC3(val) bfin_write16(NFC_ECC3, val)
-#define bfin_read_NFC_COUNT() bfin_read16(NFC_COUNT)
-#define bfin_write_NFC_COUNT(val) bfin_write16(NFC_COUNT, val)
-#define bfin_read_NFC_RST() bfin_read16(NFC_RST)
-#define bfin_write_NFC_RST(val) bfin_write16(NFC_RST, val)
-#define bfin_read_NFC_PGCTL() bfin_read16(NFC_PGCTL)
-#define bfin_write_NFC_PGCTL(val) bfin_write16(NFC_PGCTL, val)
-#define bfin_read_NFC_READ() bfin_read16(NFC_READ)
-#define bfin_write_NFC_READ(val) bfin_write16(NFC_READ, val)
-#define bfin_read_NFC_ADDR() bfin_read16(NFC_ADDR)
-#define bfin_write_NFC_ADDR(val) bfin_write16(NFC_ADDR, val)
-#define bfin_read_NFC_CMD() bfin_read16(NFC_CMD)
-#define bfin_write_NFC_CMD(val) bfin_write16(NFC_CMD, val)
-#define bfin_read_NFC_DATA_WR() bfin_read16(NFC_DATA_WR)
-#define bfin_write_NFC_DATA_WR(val) bfin_write16(NFC_DATA_WR, val)
-#define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD)
-#define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val)
-
-/* Counter Registers */
-
-#define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG)
-#define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val)
-#define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK)
-#define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val)
-#define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS)
-#define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val)
-#define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND)
-#define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val)
-#define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE)
-#define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val)
-#define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER)
-#define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val)
-#define bfin_read_CNT_MAX() bfin_read32(CNT_MAX)
-#define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val)
-#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN)
-#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val)
-
-/* Security Registers */
-
-#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT)
-#define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val)
-#define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL)
-#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
-#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS)
-#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val)
-
-/* DMA Peribfin_read_()heral Mux Register */
-
-#define bfin_read_DMAC1_PERIMUX() bfin_read16(DMAC1_PERIMUX)
-#define bfin_write_DMAC1_PERIMUX(val) bfin_write16(DMAC1_PERIMUX, val)
-
-/* Handshake MDMA is not defined in the shared file because it is not available on the ADSP-BF542 bfin_read_()rocessor */
-
-#endif /* _CDEF_BF54X_H */
-
+++ /dev/null
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF542_H
-#define _DEF_BF542_H
-
-/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
-#include "defBF54x_base.h"
-
-/* The following are the #defines needed by ADSP-BF542 that are not in the common header */
-
-/* ATAPI Registers */
-
-#define ATAPI_CONTROL 0xffc03800 /* ATAPI Control Register */
-#define ATAPI_STATUS 0xffc03804 /* ATAPI Status Register */
-#define ATAPI_DEV_ADDR 0xffc03808 /* ATAPI Device Register Address */
-#define ATAPI_DEV_TXBUF 0xffc0380c /* ATAPI Device Register Write Data */
-#define ATAPI_DEV_RXBUF 0xffc03810 /* ATAPI Device Register Read Data */
-#define ATAPI_INT_MASK 0xffc03814 /* ATAPI Interrupt Mask Register */
-#define ATAPI_INT_STATUS 0xffc03818 /* ATAPI Interrupt Status Register */
-#define ATAPI_XFER_LEN 0xffc0381c /* ATAPI Length of Transfer */
-#define ATAPI_LINE_STATUS 0xffc03820 /* ATAPI Line Status */
-#define ATAPI_SM_STATE 0xffc03824 /* ATAPI State Machine Status */
-#define ATAPI_TERMINATE 0xffc03828 /* ATAPI Host Terminate */
-#define ATAPI_PIO_TFRCNT 0xffc0382c /* ATAPI PIO mode transfer count */
-#define ATAPI_DMA_TFRCNT 0xffc03830 /* ATAPI DMA mode transfer count */
-#define ATAPI_UMAIN_TFRCNT 0xffc03834 /* ATAPI UDMAIN transfer count */
-#define ATAPI_UDMAOUT_TFRCNT 0xffc03838 /* ATAPI UDMAOUT transfer count */
-#define ATAPI_REG_TIM_0 0xffc03840 /* ATAPI Register Transfer Timing 0 */
-#define ATAPI_PIO_TIM_0 0xffc03844 /* ATAPI PIO Timing 0 Register */
-#define ATAPI_PIO_TIM_1 0xffc03848 /* ATAPI PIO Timing 1 Register */
-#define ATAPI_MULTI_TIM_0 0xffc03850 /* ATAPI Multi-DMA Timing 0 Register */
-#define ATAPI_MULTI_TIM_1 0xffc03854 /* ATAPI Multi-DMA Timing 1 Register */
-#define ATAPI_MULTI_TIM_2 0xffc03858 /* ATAPI Multi-DMA Timing 2 Register */
-#define ATAPI_ULTRA_TIM_0 0xffc03860 /* ATAPI Ultra-DMA Timing 0 Register */
-#define ATAPI_ULTRA_TIM_1 0xffc03864 /* ATAPI Ultra-DMA Timing 1 Register */
-#define ATAPI_ULTRA_TIM_2 0xffc03868 /* ATAPI Ultra-DMA Timing 2 Register */
-#define ATAPI_ULTRA_TIM_3 0xffc0386c /* ATAPI Ultra-DMA Timing 3 Register */
-
-/* SDH Registers */
-
-#define SDH_PWR_CTL 0xffc03900 /* SDH Power Control */
-#define SDH_CLK_CTL 0xffc03904 /* SDH Clock Control */
-#define SDH_ARGUMENT 0xffc03908 /* SDH Argument */
-#define SDH_COMMAND 0xffc0390c /* SDH Command */
-#define SDH_RESP_CMD 0xffc03910 /* SDH Response Command */
-#define SDH_RESPONSE0 0xffc03914 /* SDH Response0 */
-#define SDH_RESPONSE1 0xffc03918 /* SDH Response1 */
-#define SDH_RESPONSE2 0xffc0391c /* SDH Response2 */
-#define SDH_RESPONSE3 0xffc03920 /* SDH Response3 */
-#define SDH_DATA_TIMER 0xffc03924 /* SDH Data Timer */
-#define SDH_DATA_LGTH 0xffc03928 /* SDH Data Length */
-#define SDH_DATA_CTL 0xffc0392c /* SDH Data Control */
-#define SDH_DATA_CNT 0xffc03930 /* SDH Data Counter */
-#define SDH_STATUS 0xffc03934 /* SDH Status */
-#define SDH_STATUS_CLR 0xffc03938 /* SDH Status Clear */
-#define SDH_MASK0 0xffc0393c /* SDH Interrupt0 Mask */
-#define SDH_MASK1 0xffc03940 /* SDH Interrupt1 Mask */
-#define SDH_FIFO_CNT 0xffc03948 /* SDH FIFO Counter */
-#define SDH_FIFO 0xffc03980 /* SDH Data FIFO */
-#define SDH_E_STATUS 0xffc039c0 /* SDH Exception Status */
-#define SDH_E_MASK 0xffc039c4 /* SDH Exception Mask */
-#define SDH_CFG 0xffc039c8 /* SDH Configuration */
-#define SDH_RD_WAIT_EN 0xffc039cc /* SDH Read Wait Enable */
-#define SDH_PID0 0xffc039d0 /* SDH Peripheral Identification0 */
-#define SDH_PID1 0xffc039d4 /* SDH Peripheral Identification1 */
-#define SDH_PID2 0xffc039d8 /* SDH Peripheral Identification2 */
-#define SDH_PID3 0xffc039dc /* SDH Peripheral Identification3 */
-#define SDH_PID4 0xffc039e0 /* SDH Peripheral Identification4 */
-#define SDH_PID5 0xffc039e4 /* SDH Peripheral Identification5 */
-#define SDH_PID6 0xffc039e8 /* SDH Peripheral Identification6 */
-#define SDH_PID7 0xffc039ec /* SDH Peripheral Identification7 */
-
-/* USB Control Registers */
-
-#define USB_FADDR 0xffc03c00 /* Function address register */
-#define USB_POWER 0xffc03c04 /* Power management register */
-#define USB_INTRTX 0xffc03c08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
-#define USB_INTRRX 0xffc03c0c /* Interrupt register for Rx endpoints 1 to 7 */
-#define USB_INTRTXE 0xffc03c10 /* Interrupt enable register for IntrTx */
-#define USB_INTRRXE 0xffc03c14 /* Interrupt enable register for IntrRx */
-#define USB_INTRUSB 0xffc03c18 /* Interrupt register for common USB interrupts */
-#define USB_INTRUSBE 0xffc03c1c /* Interrupt enable register for IntrUSB */
-#define USB_FRAME 0xffc03c20 /* USB frame number */
-#define USB_INDEX 0xffc03c24 /* Index register for selecting the indexed endpoint registers */
-#define USB_TESTMODE 0xffc03c28 /* Enabled USB 20 test modes */
-#define USB_GLOBINTR 0xffc03c2c /* Global Interrupt Mask register and Wakeup Exception Interrupt */
-#define USB_GLOBAL_CTL 0xffc03c30 /* Global Clock Control for the core */
-
-/* USB Packet Control Registers */
-
-#define USB_TX_MAX_PACKET 0xffc03c40 /* Maximum packet size for Host Tx endpoint */
-#define USB_CSR0 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define USB_TXCSR 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define USB_RX_MAX_PACKET 0xffc03c48 /* Maximum packet size for Host Rx endpoint */
-#define USB_RXCSR 0xffc03c4c /* Control Status register for Host Rx endpoint */
-#define USB_COUNT0 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define USB_RXCOUNT 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define USB_TXTYPE 0xffc03c54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
-#define USB_NAKLIMIT0 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define USB_TXINTERVAL 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define USB_RXTYPE 0xffc03c5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
-#define USB_RXINTERVAL 0xffc03c60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
-#define USB_TXCOUNT 0xffc03c68 /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* USB Endpoint FIFO Registers */
-
-#define USB_EP0_FIFO 0xffc03c80 /* Endpoint 0 FIFO */
-#define USB_EP1_FIFO 0xffc03c88 /* Endpoint 1 FIFO */
-#define USB_EP2_FIFO 0xffc03c90 /* Endpoint 2 FIFO */
-#define USB_EP3_FIFO 0xffc03c98 /* Endpoint 3 FIFO */
-#define USB_EP4_FIFO 0xffc03ca0 /* Endpoint 4 FIFO */
-#define USB_EP5_FIFO 0xffc03ca8 /* Endpoint 5 FIFO */
-#define USB_EP6_FIFO 0xffc03cb0 /* Endpoint 6 FIFO */
-#define USB_EP7_FIFO 0xffc03cb8 /* Endpoint 7 FIFO */
-
-/* USB OTG Control Registers */
-
-#define USB_OTG_DEV_CTL 0xffc03d00 /* OTG Device Control Register */
-#define USB_OTG_VBUS_IRQ 0xffc03d04 /* OTG VBUS Control Interrupts */
-#define USB_OTG_VBUS_MASK 0xffc03d08 /* VBUS Control Interrupt Enable */
-
-/* USB Phy Control Registers */
-
-#define USB_LINKINFO 0xffc03d48 /* Enables programming of some PHY-side delays */
-#define USB_VPLEN 0xffc03d4c /* Determines duration of VBUS pulse for VBUS charging */
-#define USB_HS_EOF1 0xffc03d50 /* Time buffer for High-Speed transactions */
-#define USB_FS_EOF1 0xffc03d54 /* Time buffer for Full-Speed transactions */
-#define USB_LS_EOF1 0xffc03d58 /* Time buffer for Low-Speed transactions */
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define USB_APHY_CNTRL 0xffc03de0 /* Register that increases visibility of Analog PHY */
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define USB_APHY_CALIB 0xffc03de4 /* Register used to set some calibration values */
-#define USB_APHY_CNTRL2 0xffc03de8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
-
-#define USB_PLLOSC_CTRL 0xffc03df0 /* Used to program different parameters for USB PLL and Oscillator */
-#define USB_SRP_CLKDIV 0xffc03df4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
-
-/* USB Endpoint 0 Control Registers */
-
-#define USB_EP_NI0_TXMAXP 0xffc03e00 /* Maximum packet size for Host Tx endpoint0 */
-#define USB_EP_NI0_TXCSR 0xffc03e04 /* Control Status register for endpoint 0 */
-#define USB_EP_NI0_RXMAXP 0xffc03e08 /* Maximum packet size for Host Rx endpoint0 */
-#define USB_EP_NI0_RXCSR 0xffc03e0c /* Control Status register for Host Rx endpoint0 */
-#define USB_EP_NI0_RXCOUNT 0xffc03e10 /* Number of bytes received in endpoint 0 FIFO */
-#define USB_EP_NI0_TXTYPE 0xffc03e14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
-#define USB_EP_NI0_TXINTERVAL 0xffc03e18 /* Sets the NAK response timeout on Endpoint 0 */
-#define USB_EP_NI0_RXTYPE 0xffc03e1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
-#define USB_EP_NI0_RXINTERVAL 0xffc03e20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
-
-/* USB Endpoint 1 Control Registers */
-
-#define USB_EP_NI0_TXCOUNT 0xffc03e28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
-#define USB_EP_NI1_TXMAXP 0xffc03e40 /* Maximum packet size for Host Tx endpoint1 */
-#define USB_EP_NI1_TXCSR 0xffc03e44 /* Control Status register for endpoint1 */
-#define USB_EP_NI1_RXMAXP 0xffc03e48 /* Maximum packet size for Host Rx endpoint1 */
-#define USB_EP_NI1_RXCSR 0xffc03e4c /* Control Status register for Host Rx endpoint1 */
-#define USB_EP_NI1_RXCOUNT 0xffc03e50 /* Number of bytes received in endpoint1 FIFO */
-#define USB_EP_NI1_TXTYPE 0xffc03e54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
-#define USB_EP_NI1_TXINTERVAL 0xffc03e58 /* Sets the NAK response timeout on Endpoint1 */
-#define USB_EP_NI1_RXTYPE 0xffc03e5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
-#define USB_EP_NI1_RXINTERVAL 0xffc03e60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
-
-/* USB Endpoint 2 Control Registers */
-
-#define USB_EP_NI1_TXCOUNT 0xffc03e68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
-#define USB_EP_NI2_TXMAXP 0xffc03e80 /* Maximum packet size for Host Tx endpoint2 */
-#define USB_EP_NI2_TXCSR 0xffc03e84 /* Control Status register for endpoint2 */
-#define USB_EP_NI2_RXMAXP 0xffc03e88 /* Maximum packet size for Host Rx endpoint2 */
-#define USB_EP_NI2_RXCSR 0xffc03e8c /* Control Status register for Host Rx endpoint2 */
-#define USB_EP_NI2_RXCOUNT 0xffc03e90 /* Number of bytes received in endpoint2 FIFO */
-#define USB_EP_NI2_TXTYPE 0xffc03e94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
-#define USB_EP_NI2_TXINTERVAL 0xffc03e98 /* Sets the NAK response timeout on Endpoint2 */
-#define USB_EP_NI2_RXTYPE 0xffc03e9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
-#define USB_EP_NI2_RXINTERVAL 0xffc03ea0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
-
-/* USB Endpoint 3 Control Registers */
-
-#define USB_EP_NI2_TXCOUNT 0xffc03ea8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
-#define USB_EP_NI3_TXMAXP 0xffc03ec0 /* Maximum packet size for Host Tx endpoint3 */
-#define USB_EP_NI3_TXCSR 0xffc03ec4 /* Control Status register for endpoint3 */
-#define USB_EP_NI3_RXMAXP 0xffc03ec8 /* Maximum packet size for Host Rx endpoint3 */
-#define USB_EP_NI3_RXCSR 0xffc03ecc /* Control Status register for Host Rx endpoint3 */
-#define USB_EP_NI3_RXCOUNT 0xffc03ed0 /* Number of bytes received in endpoint3 FIFO */
-#define USB_EP_NI3_TXTYPE 0xffc03ed4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
-#define USB_EP_NI3_TXINTERVAL 0xffc03ed8 /* Sets the NAK response timeout on Endpoint3 */
-#define USB_EP_NI3_RXTYPE 0xffc03edc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
-#define USB_EP_NI3_RXINTERVAL 0xffc03ee0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
-
-/* USB Endpoint 4 Control Registers */
-
-#define USB_EP_NI3_TXCOUNT 0xffc03ee8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
-#define USB_EP_NI4_TXMAXP 0xffc03f00 /* Maximum packet size for Host Tx endpoint4 */
-#define USB_EP_NI4_TXCSR 0xffc03f04 /* Control Status register for endpoint4 */
-#define USB_EP_NI4_RXMAXP 0xffc03f08 /* Maximum packet size for Host Rx endpoint4 */
-#define USB_EP_NI4_RXCSR 0xffc03f0c /* Control Status register for Host Rx endpoint4 */
-#define USB_EP_NI4_RXCOUNT 0xffc03f10 /* Number of bytes received in endpoint4 FIFO */
-#define USB_EP_NI4_TXTYPE 0xffc03f14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
-#define USB_EP_NI4_TXINTERVAL 0xffc03f18 /* Sets the NAK response timeout on Endpoint4 */
-#define USB_EP_NI4_RXTYPE 0xffc03f1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
-#define USB_EP_NI4_RXINTERVAL 0xffc03f20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
-
-/* USB Endpoint 5 Control Registers */
-
-#define USB_EP_NI4_TXCOUNT 0xffc03f28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
-#define USB_EP_NI5_TXMAXP 0xffc03f40 /* Maximum packet size for Host Tx endpoint5 */
-#define USB_EP_NI5_TXCSR 0xffc03f44 /* Control Status register for endpoint5 */
-#define USB_EP_NI5_RXMAXP 0xffc03f48 /* Maximum packet size for Host Rx endpoint5 */
-#define USB_EP_NI5_RXCSR 0xffc03f4c /* Control Status register for Host Rx endpoint5 */
-#define USB_EP_NI5_RXCOUNT 0xffc03f50 /* Number of bytes received in endpoint5 FIFO */
-#define USB_EP_NI5_TXTYPE 0xffc03f54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
-#define USB_EP_NI5_TXINTERVAL 0xffc03f58 /* Sets the NAK response timeout on Endpoint5 */
-#define USB_EP_NI5_RXTYPE 0xffc03f5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
-#define USB_EP_NI5_RXINTERVAL 0xffc03f60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
-
-/* USB Endpoint 6 Control Registers */
-
-#define USB_EP_NI5_TXCOUNT 0xffc03f68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
-#define USB_EP_NI6_TXMAXP 0xffc03f80 /* Maximum packet size for Host Tx endpoint6 */
-#define USB_EP_NI6_TXCSR 0xffc03f84 /* Control Status register for endpoint6 */
-#define USB_EP_NI6_RXMAXP 0xffc03f88 /* Maximum packet size for Host Rx endpoint6 */
-#define USB_EP_NI6_RXCSR 0xffc03f8c /* Control Status register for Host Rx endpoint6 */
-#define USB_EP_NI6_RXCOUNT 0xffc03f90 /* Number of bytes received in endpoint6 FIFO */
-#define USB_EP_NI6_TXTYPE 0xffc03f94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
-#define USB_EP_NI6_TXINTERVAL 0xffc03f98 /* Sets the NAK response timeout on Endpoint6 */
-#define USB_EP_NI6_RXTYPE 0xffc03f9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
-#define USB_EP_NI6_RXINTERVAL 0xffc03fa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
-
-/* USB Endpoint 7 Control Registers */
-
-#define USB_EP_NI6_TXCOUNT 0xffc03fa8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
-#define USB_EP_NI7_TXMAXP 0xffc03fc0 /* Maximum packet size for Host Tx endpoint7 */
-#define USB_EP_NI7_TXCSR 0xffc03fc4 /* Control Status register for endpoint7 */
-#define USB_EP_NI7_RXMAXP 0xffc03fc8 /* Maximum packet size for Host Rx endpoint7 */
-#define USB_EP_NI7_RXCSR 0xffc03fcc /* Control Status register for Host Rx endpoint7 */
-#define USB_EP_NI7_RXCOUNT 0xffc03fd0 /* Number of bytes received in endpoint7 FIFO */
-#define USB_EP_NI7_TXTYPE 0xffc03fd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
-#define USB_EP_NI7_TXINTERVAL 0xffc03fd8 /* Sets the NAK response timeout on Endpoint7 */
-#define USB_EP_NI7_RXTYPE 0xffc03fdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
-#define USB_EP_NI7_RXINTERVAL 0xffc03ff0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
-#define USB_EP_NI7_TXCOUNT 0xffc03ff8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
-#define USB_DMA_INTERRUPT 0xffc04000 /* Indicates pending interrupts for the DMA channels */
-
-/* USB Channel 0 Config Registers */
-
-#define USB_DMA0CONTROL 0xffc04004 /* DMA master channel 0 configuration */
-#define USB_DMA0ADDRLOW 0xffc04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
-#define USB_DMA0ADDRHIGH 0xffc0400c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
-#define USB_DMA0COUNTLOW 0xffc04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define USB_DMA0COUNTHIGH 0xffc04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
-
-/* USB Channel 1 Config Registers */
-
-#define USB_DMA1CONTROL 0xffc04024 /* DMA master channel 1 configuration */
-#define USB_DMA1ADDRLOW 0xffc04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
-#define USB_DMA1ADDRHIGH 0xffc0402c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
-#define USB_DMA1COUNTLOW 0xffc04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define USB_DMA1COUNTHIGH 0xffc04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
-
-/* USB Channel 2 Config Registers */
-
-#define USB_DMA2CONTROL 0xffc04044 /* DMA master channel 2 configuration */
-#define USB_DMA2ADDRLOW 0xffc04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
-#define USB_DMA2ADDRHIGH 0xffc0404c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
-#define USB_DMA2COUNTLOW 0xffc04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define USB_DMA2COUNTHIGH 0xffc04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
-
-/* USB Channel 3 Config Registers */
-
-#define USB_DMA3CONTROL 0xffc04064 /* DMA master channel 3 configuration */
-#define USB_DMA3ADDRLOW 0xffc04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
-#define USB_DMA3ADDRHIGH 0xffc0406c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
-#define USB_DMA3COUNTLOW 0xffc04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define USB_DMA3COUNTHIGH 0xffc04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
-
-/* USB Channel 4 Config Registers */
-
-#define USB_DMA4CONTROL 0xffc04084 /* DMA master channel 4 configuration */
-#define USB_DMA4ADDRLOW 0xffc04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
-#define USB_DMA4ADDRHIGH 0xffc0408c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
-#define USB_DMA4COUNTLOW 0xffc04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define USB_DMA4COUNTHIGH 0xffc04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
-
-/* USB Channel 5 Config Registers */
-
-#define USB_DMA5CONTROL 0xffc040a4 /* DMA master channel 5 configuration */
-#define USB_DMA5ADDRLOW 0xffc040a8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
-#define USB_DMA5ADDRHIGH 0xffc040ac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
-#define USB_DMA5COUNTLOW 0xffc040b0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define USB_DMA5COUNTHIGH 0xffc040b4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
-
-/* USB Channel 6 Config Registers */
-
-#define USB_DMA6CONTROL 0xffc040c4 /* DMA master channel 6 configuration */
-#define USB_DMA6ADDRLOW 0xffc040c8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
-#define USB_DMA6ADDRHIGH 0xffc040cc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
-#define USB_DMA6COUNTLOW 0xffc040d0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define USB_DMA6COUNTHIGH 0xffc040d4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
-
-/* USB Channel 7 Config Registers */
-
-#define USB_DMA7CONTROL 0xffc040e4 /* DMA master channel 7 configuration */
-#define USB_DMA7ADDRLOW 0xffc040e8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
-#define USB_DMA7ADDRHIGH 0xffc040ec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
-#define USB_DMA7COUNTLOW 0xffc040f0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
-#define USB_DMA7COUNTHIGH 0xffc040f4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
-
-/* Keypad Registers */
-
-#define KPAD_CTL 0xffc04100 /* Controls keypad module enable and disable */
-#define KPAD_PRESCALE 0xffc04104 /* Establish a time base for programing the KPAD_MSEL register */
-#define KPAD_MSEL 0xffc04108 /* Selects delay parameters for keypad interface sensitivity */
-#define KPAD_ROWCOL 0xffc0410c /* Captures the row and column output values of the keys pressed */
-#define KPAD_STAT 0xffc04110 /* Holds and clears the status of the keypad interface interrupt */
-#define KPAD_SOFTEVAL 0xffc04114 /* Lets software force keypad interface to check for keys being pressed */
-
-
-/* ********************************************************** */
-/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
-/* and MULTI BIT READ MACROS */
-/* ********************************************************** */
-
-/* Bit masks for KPAD_CTL */
-
-#define KPAD_EN 0x1 /* Keypad Enable */
-#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */
-#define KPAD_ROWEN 0x1c00 /* Row Enable Width */
-#define KPAD_COLEN 0xe000 /* Column Enable Width */
-
-/* Bit masks for KPAD_PRESCALE */
-
-#define KPAD_PRESCALE_VAL 0x3f /* Key Prescale Value */
-
-/* Bit masks for KPAD_MSEL */
-
-#define DBON_SCALE 0xff /* Debounce Scale Value */
-#define COLDRV_SCALE 0xff00 /* Column Driver Scale Value */
-
-/* Bit masks for KPAD_ROWCOL */
-
-#define KPAD_ROW 0xff /* Rows Pressed */
-#define KPAD_COL 0xff00 /* Columns Pressed */
-
-/* Bit masks for KPAD_STAT */
-
-#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */
-#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */
-#define KPAD_PRESSED 0x8 /* Key press current status */
-
-/* Bit masks for KPAD_SOFTEVAL */
-
-#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */
-
-/* Bit masks for ATAPI_CONTROL */
-
-#define PIO_START 0x1 /* Start PIO/Reg Op */
-#define MULTI_START 0x2 /* Start Multi-DMA Op */
-#define ULTRA_START 0x4 /* Start Ultra-DMA Op */
-#define XFER_DIR 0x8 /* Transfer Direction */
-#define IORDY_EN 0x10 /* IORDY Enable */
-#define FIFO_FLUSH 0x20 /* Flush FIFOs */
-#define SOFT_RST 0x40 /* Soft Reset */
-#define DEV_RST 0x80 /* Device Reset */
-#define TFRCNT_RST 0x100 /* Trans Count Reset */
-#define END_ON_TERM 0x200 /* End/Terminate Select */
-#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */
-#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */
-
-/* Bit masks for ATAPI_STATUS */
-
-#define PIO_XFER_ON 0x1 /* PIO transfer in progress */
-#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */
-#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */
-#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */
-
-/* Bit masks for ATAPI_DEV_ADDR */
-
-#define DEV_ADDR 0x1f /* Device Address */
-
-/* Bit masks for ATAPI_INT_MASK */
-
-#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */
-#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */
-#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */
-#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */
-#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */
-#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */
-#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */
-#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */
-#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */
-
-/* Bit masks for ATAPI_INT_STATUS */
-
-#define ATAPI_DEV_INT 0x1 /* Device interrupt status */
-#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */
-#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */
-#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */
-#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */
-#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */
-#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */
-#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */
-#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */
-
-/* Bit masks for ATAPI_LINE_STATUS */
-
-#define ATAPI_INTR 0x1 /* Device interrupt to host line status */
-#define ATAPI_DASP 0x2 /* Device dasp to host line status */
-#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */
-#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */
-#define ATAPI_ADDR 0x70 /* ATAPI address line status */
-#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */
-#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */
-#define ATAPI_DIOWN 0x200 /* ATAPI write line status */
-#define ATAPI_DIORN 0x400 /* ATAPI read line status */
-#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */
-
-/* Bit masks for ATAPI_SM_STATE */
-
-#define PIO_CSTATE 0xf /* PIO mode state machine current state */
-#define DMA_CSTATE 0xf0 /* DMA mode state machine current state */
-#define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */
-#define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */
-
-/* Bit masks for ATAPI_TERMINATE */
-
-#define ATAPI_HOST_TERM 0x1 /* Host terminationation */
-
-/* Bit masks for ATAPI_REG_TIM_0 */
-
-#define T2_REG 0xff /* End of cycle time for register access transfers */
-#define TEOC_REG 0xff00 /* Selects DIOR/DIOW pulsewidth */
-
-/* Bit masks for ATAPI_PIO_TIM_0 */
-
-#define T1_REG 0xf /* Time from address valid to DIOR/DIOW */
-#define T2_REG_PIO 0xff0 /* DIOR/DIOW pulsewidth */
-#define T4_REG 0xf000 /* DIOW data hold */
-
-/* Bit masks for ATAPI_PIO_TIM_1 */
-
-#define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */
-
-/* Bit masks for ATAPI_MULTI_TIM_0 */
-
-#define TD 0xff /* DIOR/DIOW asserted pulsewidth */
-#define TM 0xff00 /* Time from address valid to DIOR/DIOW */
-
-/* Bit masks for ATAPI_MULTI_TIM_1 */
-
-#define TKW 0xff /* Selects DIOW negated pulsewidth */
-#define TKR 0xff00 /* Selects DIOR negated pulsewidth */
-
-/* Bit masks for ATAPI_MULTI_TIM_2 */
-
-#define TH 0xff /* Selects DIOW data hold */
-#define TEOC 0xff00 /* Selects end of cycle for DMA */
-
-/* Bit masks for ATAPI_ULTRA_TIM_0 */
-
-#define TACK 0xff /* Selects setup and hold times for TACK */
-#define TENV 0xff00 /* Selects envelope time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_1 */
-
-#define TDVS 0xff /* Selects data valid setup time */
-#define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_2 */
-
-#define TSS 0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */
-#define TMLI 0xff00 /* Selects interlock time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_3 */
-
-#define TZAH 0xff /* Selects minimum delay required for output */
-#define READY_PAUSE 0xff00 /* Selects ready to pause */
-
-/* Bit masks for USB_FADDR */
-
-#define FUNCTION_ADDRESS 0x7f /* Function address */
-
-/* Bit masks for USB_POWER */
-
-#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
-#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
-#define RESUME_MODE 0x4 /* DMA Mode */
-#define RESET 0x8 /* Reset indicator */
-#define HS_MODE 0x10 /* High Speed mode indicator */
-#define HS_ENABLE 0x20 /* high Speed Enable */
-#define SOFT_CONN 0x40 /* Soft connect */
-#define ISO_UPDATE 0x80 /* Isochronous update */
-
-/* Bit masks for USB_INTRTX */
-
-#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
-#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
-#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
-#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
-#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
-#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
-#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
-#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
-
-/* Bit masks for USB_INTRRX */
-
-#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
-#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
-#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
-#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
-#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
-#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
-#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
-
-/* Bit masks for USB_INTRTXE */
-
-#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
-#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
-#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
-#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
-#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
-#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
-#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
-#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
-
-/* Bit masks for USB_INTRRXE */
-
-#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
-#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
-#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
-#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
-#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
-#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
-#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
-
-/* Bit masks for USB_INTRUSB */
-
-#define SUSPEND_B 0x1 /* Suspend indicator */
-#define RESUME_B 0x2 /* Resume indicator */
-#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
-#define SOF_B 0x8 /* Start of frame */
-#define CONN_B 0x10 /* Connection indicator */
-#define DISCON_B 0x20 /* Disconnect indicator */
-#define SESSION_REQ_B 0x40 /* Session Request */
-#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
-
-/* Bit masks for USB_INTRUSBE */
-
-#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
-#define RESUME_BE 0x2 /* Resume indicator int enable */
-#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
-#define SOF_BE 0x8 /* Start of frame int enable */
-#define CONN_BE 0x10 /* Connection indicator int enable */
-#define DISCON_BE 0x20 /* Disconnect indicator int enable */
-#define SESSION_REQ_BE 0x40 /* Session Request int enable */
-#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
-
-/* Bit masks for USB_FRAME */
-
-#define FRAME_NUMBER 0x7ff /* Frame number */
-
-/* Bit masks for USB_INDEX */
-
-#define SELECTED_ENDPOINT 0xf /* selected endpoint */
-
-/* Bit masks for USB_GLOBAL_CTL */
-
-#define GLOBAL_ENA 0x1 /* enables USB module */
-#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
-#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
-#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
-#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
-#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
-#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
-#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
-#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
-#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
-#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
-#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
-#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
-#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
-#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
-
-/* Bit masks for USB_OTG_DEV_CTL */
-
-#define SESSION 0x1 /* session indicator */
-#define HOST_REQ 0x2 /* Host negotiation request */
-#define HOST_MODE 0x4 /* indicates USBDRC is a host */
-#define VBUS0 0x8 /* Vbus level indicator[0] */
-#define VBUS1 0x10 /* Vbus level indicator[1] */
-#define LSDEV 0x20 /* Low-speed indicator */
-#define FSDEV 0x40 /* Full or High-speed indicator */
-#define B_DEVICE 0x80 /* A' or 'B' device indicator */
-
-/* Bit masks for USB_OTG_VBUS_IRQ */
-
-#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
-#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
-#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
-#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
-#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
-#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
-
-/* Bit masks for USB_OTG_VBUS_MASK */
-
-#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
-#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
-#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
-#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
-#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
-#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
-
-/* Bit masks for USB_CSR0 */
-
-#define RXPKTRDY 0x1 /* data packet receive indicator */
-#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
-#define STALL_SENT 0x4 /* STALL handshake sent */
-#define DATAEND 0x8 /* Data end indicator */
-#define SETUPEND 0x10 /* Setup end */
-#define SENDSTALL 0x20 /* Send STALL handshake */
-#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
-#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
-#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
-#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
-#define SETUPPKT_H 0x8 /* send Setup token host mode */
-#define ERROR_H 0x10 /* timeout error indicator host mode */
-#define REQPKT_H 0x20 /* Request an IN transaction host mode */
-#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
-#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
-
-/* Bit masks for USB_COUNT0 */
-
-#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */
-
-/* Bit masks for USB_NAKLIMIT0 */
-
-#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */
-
-/* Bit masks for USB_TX_MAX_PACKET */
-
-#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */
-
-/* Bit masks for USB_RX_MAX_PACKET */
-
-#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */
-
-/* Bit masks for USB_TXCSR */
-
-#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
-#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
-#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
-#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
-#define STALL_SEND_T 0x10 /* issue a Stall handshake */
-#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
-#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
-#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
-#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
-#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
-#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
-#define ISO_T 0x4000 /* enable Isochronous transfers */
-#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
-#define ERROR_TH 0x4 /* error condition host mode */
-#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
-#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
-
-/* Bit masks for USB_TXCOUNT */
-
-#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* Bit masks for USB_RXCSR */
-
-#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
-#define FIFO_FULL_R 0x2 /* FIFO not empty */
-#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
-#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
-#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
-#define STALL_SEND_R 0x20 /* issue a Stall handshake */
-#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
-#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
-#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
-#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
-#define DISNYET_R 0x1000 /* disable Nyet handshakes */
-#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
-#define ISO_R 0x4000 /* enable Isochronous transfers */
-#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
-#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
-#define REQPKT_RH 0x20 /* request an IN transaction host mode */
-#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
-#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
-#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
-#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
-
-/* Bit masks for USB_RXCOUNT */
-
-#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */
-
-/* Bit masks for USB_TXTYPE */
-
-#define TARGET_EP_NO_T 0xf /* EP number */
-#define PROTOCOL_T 0xc /* transfer type */
-
-/* Bit masks for USB_TXINTERVAL */
-
-#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
-
-/* Bit masks for USB_RXTYPE */
-
-#define TARGET_EP_NO_R 0xf /* EP number */
-#define PROTOCOL_R 0xc /* transfer type */
-
-/* Bit masks for USB_RXINTERVAL */
-
-#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
-
-/* Bit masks for USB_DMA_INTERRUPT */
-
-#define DMA0_INT 0x1 /* DMA0 pending interrupt */
-#define DMA1_INT 0x2 /* DMA1 pending interrupt */
-#define DMA2_INT 0x4 /* DMA2 pending interrupt */
-#define DMA3_INT 0x8 /* DMA3 pending interrupt */
-#define DMA4_INT 0x10 /* DMA4 pending interrupt */
-#define DMA5_INT 0x20 /* DMA5 pending interrupt */
-#define DMA6_INT 0x40 /* DMA6 pending interrupt */
-#define DMA7_INT 0x80 /* DMA7 pending interrupt */
-
-/* Bit masks for USB_DMAxCONTROL */
-
-#define DMA_ENA 0x1 /* DMA enable */
-#define DIRECTION 0x2 /* direction of DMA transfer */
-#define MODE 0x4 /* DMA Bus error */
-#define INT_ENA 0x8 /* Interrupt enable */
-#define EPNUM 0xf0 /* EP number */
-#define BUSERROR 0x100 /* DMA Bus error */
-
-/* Bit masks for USB_DMAxADDRHIGH */
-
-#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxADDRLOW */
-
-#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTHIGH */
-
-#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTLOW */
-
-#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
-
-
-/* ******************************************* */
-/* MULTI BIT MACRO ENUMERATIONS */
-/* ******************************************* */
-
-
-#endif /* _DEF_BF542_H */
+++ /dev/null
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF544_H
-#define _DEF_BF544_H
-
-/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
-#include "defBF54x_base.h"
-
-/* The following are the #defines needed by ADSP-BF544 that are not in the common header */
-
-/* Timer Registers */
-
-#define TIMER8_CONFIG 0xffc00600 /* Timer 8 Configuration Register */
-#define TIMER8_COUNTER 0xffc00604 /* Timer 8 Counter Register */
-#define TIMER8_PERIOD 0xffc00608 /* Timer 8 Period Register */
-#define TIMER8_WIDTH 0xffc0060c /* Timer 8 Width Register */
-#define TIMER9_CONFIG 0xffc00610 /* Timer 9 Configuration Register */
-#define TIMER9_COUNTER 0xffc00614 /* Timer 9 Counter Register */
-#define TIMER9_PERIOD 0xffc00618 /* Timer 9 Period Register */
-#define TIMER9_WIDTH 0xffc0061c /* Timer 9 Width Register */
-#define TIMER10_CONFIG 0xffc00620 /* Timer 10 Configuration Register */
-#define TIMER10_COUNTER 0xffc00624 /* Timer 10 Counter Register */
-#define TIMER10_PERIOD 0xffc00628 /* Timer 10 Period Register */
-#define TIMER10_WIDTH 0xffc0062c /* Timer 10 Width Register */
-
-/* Timer Group of 3 Registers */
-
-#define TIMER_ENABLE1 0xffc00640 /* Timer Group of 3 Enable Register */
-#define TIMER_DISABLE1 0xffc00644 /* Timer Group of 3 Disable Register */
-#define TIMER_STATUS1 0xffc00648 /* Timer Group of 3 Status Register */
-
-/* EPPI0 Registers */
-
-#define EPPI0_STATUS 0xffc01000 /* EPPI0 Status Register */
-#define EPPI0_HCOUNT 0xffc01004 /* EPPI0 Horizontal Transfer Count Register */
-#define EPPI0_HDELAY 0xffc01008 /* EPPI0 Horizontal Delay Count Register */
-#define EPPI0_VCOUNT 0xffc0100c /* EPPI0 Vertical Transfer Count Register */
-#define EPPI0_VDELAY 0xffc01010 /* EPPI0 Vertical Delay Count Register */
-#define EPPI0_FRAME 0xffc01014 /* EPPI0 Lines per Frame Register */
-#define EPPI0_LINE 0xffc01018 /* EPPI0 Samples per Line Register */
-#define EPPI0_CLKDIV 0xffc0101c /* EPPI0 Clock Divide Register */
-#define EPPI0_CONTROL 0xffc01020 /* EPPI0 Control Register */
-#define EPPI0_FS1W_HBL 0xffc01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
-#define EPPI0_FS1P_AVPL 0xffc01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
-#define EPPI0_FS2W_LVB 0xffc0102c /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
-#define EPPI0_FS2P_LAVF 0xffc01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
-#define EPPI0_CLIP 0xffc01034 /* EPPI0 Clipping Register */
-
-/* Two Wire Interface Registers (TWI1) */
-
-#define TWI1_REGBASE 0xffc02200
-#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */
-#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */
-#define TWI1_SLAVE_CTL 0xffc02208 /* TWI Slave Mode Control Register */
-#define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */
-#define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */
-#define TWI1_MASTER_CTL 0xffc02214 /* TWI Master Mode Control Register */
-#define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */
-#define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */
-#define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */
-#define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */
-#define TWI1_FIFO_CTL 0xffc02228 /* TWI FIFO Control Register */
-#define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */
-#define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */
-#define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */
-#define TWI1_RCV_DATA8 0xffc02288 /* TWI FIFO Receive Data Single Byte Register */
-#define TWI1_RCV_DATA16 0xffc0228c /* TWI FIFO Receive Data Double Byte Register */
-
-/* CAN Controller 1 Config 1 Registers */
-
-#define CAN1_MC1 0xffc03200 /* CAN Controller 1 Mailbox Configuration Register 1 */
-#define CAN1_MD1 0xffc03204 /* CAN Controller 1 Mailbox Direction Register 1 */
-#define CAN1_TRS1 0xffc03208 /* CAN Controller 1 Transmit Request Set Register 1 */
-#define CAN1_TRR1 0xffc0320c /* CAN Controller 1 Transmit Request Reset Register 1 */
-#define CAN1_TA1 0xffc03210 /* CAN Controller 1 Transmit Acknowledge Register 1 */
-#define CAN1_AA1 0xffc03214 /* CAN Controller 1 Abort Acknowledge Register 1 */
-#define CAN1_RMP1 0xffc03218 /* CAN Controller 1 Receive Message Pending Register 1 */
-#define CAN1_RML1 0xffc0321c /* CAN Controller 1 Receive Message Lost Register 1 */
-#define CAN1_MBTIF1 0xffc03220 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
-#define CAN1_MBRIF1 0xffc03224 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
-#define CAN1_MBIM1 0xffc03228 /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
-#define CAN1_RFH1 0xffc0322c /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
-#define CAN1_OPSS1 0xffc03230 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
-
-/* CAN Controller 1 Config 2 Registers */
-
-#define CAN1_MC2 0xffc03240 /* CAN Controller 1 Mailbox Configuration Register 2 */
-#define CAN1_MD2 0xffc03244 /* CAN Controller 1 Mailbox Direction Register 2 */
-#define CAN1_TRS2 0xffc03248 /* CAN Controller 1 Transmit Request Set Register 2 */
-#define CAN1_TRR2 0xffc0324c /* CAN Controller 1 Transmit Request Reset Register 2 */
-#define CAN1_TA2 0xffc03250 /* CAN Controller 1 Transmit Acknowledge Register 2 */
-#define CAN1_AA2 0xffc03254 /* CAN Controller 1 Abort Acknowledge Register 2 */
-#define CAN1_RMP2 0xffc03258 /* CAN Controller 1 Receive Message Pending Register 2 */
-#define CAN1_RML2 0xffc0325c /* CAN Controller 1 Receive Message Lost Register 2 */
-#define CAN1_MBTIF2 0xffc03260 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
-#define CAN1_MBRIF2 0xffc03264 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
-#define CAN1_MBIM2 0xffc03268 /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
-#define CAN1_RFH2 0xffc0326c /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
-#define CAN1_OPSS2 0xffc03270 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
-
-/* CAN Controller 1 Clock/Interrupt/Counter Registers */
-
-#define CAN1_CLOCK 0xffc03280 /* CAN Controller 1 Clock Register */
-#define CAN1_TIMING 0xffc03284 /* CAN Controller 1 Timing Register */
-#define CAN1_DEBUG 0xffc03288 /* CAN Controller 1 Debug Register */
-#define CAN1_STATUS 0xffc0328c /* CAN Controller 1 Global Status Register */
-#define CAN1_CEC 0xffc03290 /* CAN Controller 1 Error Counter Register */
-#define CAN1_GIS 0xffc03294 /* CAN Controller 1 Global Interrupt Status Register */
-#define CAN1_GIM 0xffc03298 /* CAN Controller 1 Global Interrupt Mask Register */
-#define CAN1_GIF 0xffc0329c /* CAN Controller 1 Global Interrupt Flag Register */
-#define CAN1_CONTROL 0xffc032a0 /* CAN Controller 1 Master Control Register */
-#define CAN1_INTR 0xffc032a4 /* CAN Controller 1 Interrupt Pending Register */
-#define CAN1_MBTD 0xffc032ac /* CAN Controller 1 Mailbox Temporary Disable Register */
-#define CAN1_EWR 0xffc032b0 /* CAN Controller 1 Programmable Warning Level Register */
-#define CAN1_ESR 0xffc032b4 /* CAN Controller 1 Error Status Register */
-#define CAN1_UCCNT 0xffc032c4 /* CAN Controller 1 Universal Counter Register */
-#define CAN1_UCRC 0xffc032c8 /* CAN Controller 1 Universal Counter Force Reload Register */
-#define CAN1_UCCNF 0xffc032cc /* CAN Controller 1 Universal Counter Configuration Register */
-
-/* CAN Controller 1 Mailbox Acceptance Registers */
-
-#define CAN1_AM00L 0xffc03300 /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
-#define CAN1_AM00H 0xffc03304 /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
-#define CAN1_AM01L 0xffc03308 /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
-#define CAN1_AM01H 0xffc0330c /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
-#define CAN1_AM02L 0xffc03310 /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
-#define CAN1_AM02H 0xffc03314 /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
-#define CAN1_AM03L 0xffc03318 /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
-#define CAN1_AM03H 0xffc0331c /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
-#define CAN1_AM04L 0xffc03320 /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
-#define CAN1_AM04H 0xffc03324 /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
-#define CAN1_AM05L 0xffc03328 /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
-#define CAN1_AM05H 0xffc0332c /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
-#define CAN1_AM06L 0xffc03330 /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
-#define CAN1_AM06H 0xffc03334 /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
-#define CAN1_AM07L 0xffc03338 /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
-#define CAN1_AM07H 0xffc0333c /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
-#define CAN1_AM08L 0xffc03340 /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
-#define CAN1_AM08H 0xffc03344 /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
-#define CAN1_AM09L 0xffc03348 /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
-#define CAN1_AM09H 0xffc0334c /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
-#define CAN1_AM10L 0xffc03350 /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
-#define CAN1_AM10H 0xffc03354 /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
-#define CAN1_AM11L 0xffc03358 /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
-#define CAN1_AM11H 0xffc0335c /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
-#define CAN1_AM12L 0xffc03360 /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
-#define CAN1_AM12H 0xffc03364 /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
-#define CAN1_AM13L 0xffc03368 /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
-#define CAN1_AM13H 0xffc0336c /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
-#define CAN1_AM14L 0xffc03370 /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
-#define CAN1_AM14H 0xffc03374 /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
-#define CAN1_AM15L 0xffc03378 /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
-#define CAN1_AM15H 0xffc0337c /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
-
-/* CAN Controller 1 Mailbox Acceptance Registers */
-
-#define CAN1_AM16L 0xffc03380 /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
-#define CAN1_AM16H 0xffc03384 /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
-#define CAN1_AM17L 0xffc03388 /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
-#define CAN1_AM17H 0xffc0338c /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
-#define CAN1_AM18L 0xffc03390 /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
-#define CAN1_AM18H 0xffc03394 /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
-#define CAN1_AM19L 0xffc03398 /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
-#define CAN1_AM19H 0xffc0339c /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
-#define CAN1_AM20L 0xffc033a0 /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
-#define CAN1_AM20H 0xffc033a4 /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
-#define CAN1_AM21L 0xffc033a8 /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
-#define CAN1_AM21H 0xffc033ac /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
-#define CAN1_AM22L 0xffc033b0 /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
-#define CAN1_AM22H 0xffc033b4 /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
-#define CAN1_AM23L 0xffc033b8 /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
-#define CAN1_AM23H 0xffc033bc /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
-#define CAN1_AM24L 0xffc033c0 /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
-#define CAN1_AM24H 0xffc033c4 /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
-#define CAN1_AM25L 0xffc033c8 /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
-#define CAN1_AM25H 0xffc033cc /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
-#define CAN1_AM26L 0xffc033d0 /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
-#define CAN1_AM26H 0xffc033d4 /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
-#define CAN1_AM27L 0xffc033d8 /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
-#define CAN1_AM27H 0xffc033dc /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
-#define CAN1_AM28L 0xffc033e0 /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
-#define CAN1_AM28H 0xffc033e4 /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
-#define CAN1_AM29L 0xffc033e8 /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
-#define CAN1_AM29H 0xffc033ec /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
-#define CAN1_AM30L 0xffc033f0 /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
-#define CAN1_AM30H 0xffc033f4 /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
-#define CAN1_AM31L 0xffc033f8 /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
-#define CAN1_AM31H 0xffc033fc /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define CAN1_MB00_DATA0 0xffc03400 /* CAN Controller 1 Mailbox 0 Data 0 Register */
-#define CAN1_MB00_DATA1 0xffc03404 /* CAN Controller 1 Mailbox 0 Data 1 Register */
-#define CAN1_MB00_DATA2 0xffc03408 /* CAN Controller 1 Mailbox 0 Data 2 Register */
-#define CAN1_MB00_DATA3 0xffc0340c /* CAN Controller 1 Mailbox 0 Data 3 Register */
-#define CAN1_MB00_LENGTH 0xffc03410 /* CAN Controller 1 Mailbox 0 Length Register */
-#define CAN1_MB00_TIMESTAMP 0xffc03414 /* CAN Controller 1 Mailbox 0 Timestamp Register */
-#define CAN1_MB00_ID0 0xffc03418 /* CAN Controller 1 Mailbox 0 ID0 Register */
-#define CAN1_MB00_ID1 0xffc0341c /* CAN Controller 1 Mailbox 0 ID1 Register */
-#define CAN1_MB01_DATA0 0xffc03420 /* CAN Controller 1 Mailbox 1 Data 0 Register */
-#define CAN1_MB01_DATA1 0xffc03424 /* CAN Controller 1 Mailbox 1 Data 1 Register */
-#define CAN1_MB01_DATA2 0xffc03428 /* CAN Controller 1 Mailbox 1 Data 2 Register */
-#define CAN1_MB01_DATA3 0xffc0342c /* CAN Controller 1 Mailbox 1 Data 3 Register */
-#define CAN1_MB01_LENGTH 0xffc03430 /* CAN Controller 1 Mailbox 1 Length Register */
-#define CAN1_MB01_TIMESTAMP 0xffc03434 /* CAN Controller 1 Mailbox 1 Timestamp Register */
-#define CAN1_MB01_ID0 0xffc03438 /* CAN Controller 1 Mailbox 1 ID0 Register */
-#define CAN1_MB01_ID1 0xffc0343c /* CAN Controller 1 Mailbox 1 ID1 Register */
-#define CAN1_MB02_DATA0 0xffc03440 /* CAN Controller 1 Mailbox 2 Data 0 Register */
-#define CAN1_MB02_DATA1 0xffc03444 /* CAN Controller 1 Mailbox 2 Data 1 Register */
-#define CAN1_MB02_DATA2 0xffc03448 /* CAN Controller 1 Mailbox 2 Data 2 Register */
-#define CAN1_MB02_DATA3 0xffc0344c /* CAN Controller 1 Mailbox 2 Data 3 Register */
-#define CAN1_MB02_LENGTH 0xffc03450 /* CAN Controller 1 Mailbox 2 Length Register */
-#define CAN1_MB02_TIMESTAMP 0xffc03454 /* CAN Controller 1 Mailbox 2 Timestamp Register */
-#define CAN1_MB02_ID0 0xffc03458 /* CAN Controller 1 Mailbox 2 ID0 Register */
-#define CAN1_MB02_ID1 0xffc0345c /* CAN Controller 1 Mailbox 2 ID1 Register */
-#define CAN1_MB03_DATA0 0xffc03460 /* CAN Controller 1 Mailbox 3 Data 0 Register */
-#define CAN1_MB03_DATA1 0xffc03464 /* CAN Controller 1 Mailbox 3 Data 1 Register */
-#define CAN1_MB03_DATA2 0xffc03468 /* CAN Controller 1 Mailbox 3 Data 2 Register */
-#define CAN1_MB03_DATA3 0xffc0346c /* CAN Controller 1 Mailbox 3 Data 3 Register */
-#define CAN1_MB03_LENGTH 0xffc03470 /* CAN Controller 1 Mailbox 3 Length Register */
-#define CAN1_MB03_TIMESTAMP 0xffc03474 /* CAN Controller 1 Mailbox 3 Timestamp Register */
-#define CAN1_MB03_ID0 0xffc03478 /* CAN Controller 1 Mailbox 3 ID0 Register */
-#define CAN1_MB03_ID1 0xffc0347c /* CAN Controller 1 Mailbox 3 ID1 Register */
-#define CAN1_MB04_DATA0 0xffc03480 /* CAN Controller 1 Mailbox 4 Data 0 Register */
-#define CAN1_MB04_DATA1 0xffc03484 /* CAN Controller 1 Mailbox 4 Data 1 Register */
-#define CAN1_MB04_DATA2 0xffc03488 /* CAN Controller 1 Mailbox 4 Data 2 Register */
-#define CAN1_MB04_DATA3 0xffc0348c /* CAN Controller 1 Mailbox 4 Data 3 Register */
-#define CAN1_MB04_LENGTH 0xffc03490 /* CAN Controller 1 Mailbox 4 Length Register */
-#define CAN1_MB04_TIMESTAMP 0xffc03494 /* CAN Controller 1 Mailbox 4 Timestamp Register */
-#define CAN1_MB04_ID0 0xffc03498 /* CAN Controller 1 Mailbox 4 ID0 Register */
-#define CAN1_MB04_ID1 0xffc0349c /* CAN Controller 1 Mailbox 4 ID1 Register */
-#define CAN1_MB05_DATA0 0xffc034a0 /* CAN Controller 1 Mailbox 5 Data 0 Register */
-#define CAN1_MB05_DATA1 0xffc034a4 /* CAN Controller 1 Mailbox 5 Data 1 Register */
-#define CAN1_MB05_DATA2 0xffc034a8 /* CAN Controller 1 Mailbox 5 Data 2 Register */
-#define CAN1_MB05_DATA3 0xffc034ac /* CAN Controller 1 Mailbox 5 Data 3 Register */
-#define CAN1_MB05_LENGTH 0xffc034b0 /* CAN Controller 1 Mailbox 5 Length Register */
-#define CAN1_MB05_TIMESTAMP 0xffc034b4 /* CAN Controller 1 Mailbox 5 Timestamp Register */
-#define CAN1_MB05_ID0 0xffc034b8 /* CAN Controller 1 Mailbox 5 ID0 Register */
-#define CAN1_MB05_ID1 0xffc034bc /* CAN Controller 1 Mailbox 5 ID1 Register */
-#define CAN1_MB06_DATA0 0xffc034c0 /* CAN Controller 1 Mailbox 6 Data 0 Register */
-#define CAN1_MB06_DATA1 0xffc034c4 /* CAN Controller 1 Mailbox 6 Data 1 Register */
-#define CAN1_MB06_DATA2 0xffc034c8 /* CAN Controller 1 Mailbox 6 Data 2 Register */
-#define CAN1_MB06_DATA3 0xffc034cc /* CAN Controller 1 Mailbox 6 Data 3 Register */
-#define CAN1_MB06_LENGTH 0xffc034d0 /* CAN Controller 1 Mailbox 6 Length Register */
-#define CAN1_MB06_TIMESTAMP 0xffc034d4 /* CAN Controller 1 Mailbox 6 Timestamp Register */
-#define CAN1_MB06_ID0 0xffc034d8 /* CAN Controller 1 Mailbox 6 ID0 Register */
-#define CAN1_MB06_ID1 0xffc034dc /* CAN Controller 1 Mailbox 6 ID1 Register */
-#define CAN1_MB07_DATA0 0xffc034e0 /* CAN Controller 1 Mailbox 7 Data 0 Register */
-#define CAN1_MB07_DATA1 0xffc034e4 /* CAN Controller 1 Mailbox 7 Data 1 Register */
-#define CAN1_MB07_DATA2 0xffc034e8 /* CAN Controller 1 Mailbox 7 Data 2 Register */
-#define CAN1_MB07_DATA3 0xffc034ec /* CAN Controller 1 Mailbox 7 Data 3 Register */
-#define CAN1_MB07_LENGTH 0xffc034f0 /* CAN Controller 1 Mailbox 7 Length Register */
-#define CAN1_MB07_TIMESTAMP 0xffc034f4 /* CAN Controller 1 Mailbox 7 Timestamp Register */
-#define CAN1_MB07_ID0 0xffc034f8 /* CAN Controller 1 Mailbox 7 ID0 Register */
-#define CAN1_MB07_ID1 0xffc034fc /* CAN Controller 1 Mailbox 7 ID1 Register */
-#define CAN1_MB08_DATA0 0xffc03500 /* CAN Controller 1 Mailbox 8 Data 0 Register */
-#define CAN1_MB08_DATA1 0xffc03504 /* CAN Controller 1 Mailbox 8 Data 1 Register */
-#define CAN1_MB08_DATA2 0xffc03508 /* CAN Controller 1 Mailbox 8 Data 2 Register */
-#define CAN1_MB08_DATA3 0xffc0350c /* CAN Controller 1 Mailbox 8 Data 3 Register */
-#define CAN1_MB08_LENGTH 0xffc03510 /* CAN Controller 1 Mailbox 8 Length Register */
-#define CAN1_MB08_TIMESTAMP 0xffc03514 /* CAN Controller 1 Mailbox 8 Timestamp Register */
-#define CAN1_MB08_ID0 0xffc03518 /* CAN Controller 1 Mailbox 8 ID0 Register */
-#define CAN1_MB08_ID1 0xffc0351c /* CAN Controller 1 Mailbox 8 ID1 Register */
-#define CAN1_MB09_DATA0 0xffc03520 /* CAN Controller 1 Mailbox 9 Data 0 Register */
-#define CAN1_MB09_DATA1 0xffc03524 /* CAN Controller 1 Mailbox 9 Data 1 Register */
-#define CAN1_MB09_DATA2 0xffc03528 /* CAN Controller 1 Mailbox 9 Data 2 Register */
-#define CAN1_MB09_DATA3 0xffc0352c /* CAN Controller 1 Mailbox 9 Data 3 Register */
-#define CAN1_MB09_LENGTH 0xffc03530 /* CAN Controller 1 Mailbox 9 Length Register */
-#define CAN1_MB09_TIMESTAMP 0xffc03534 /* CAN Controller 1 Mailbox 9 Timestamp Register */
-#define CAN1_MB09_ID0 0xffc03538 /* CAN Controller 1 Mailbox 9 ID0 Register */
-#define CAN1_MB09_ID1 0xffc0353c /* CAN Controller 1 Mailbox 9 ID1 Register */
-#define CAN1_MB10_DATA0 0xffc03540 /* CAN Controller 1 Mailbox 10 Data 0 Register */
-#define CAN1_MB10_DATA1 0xffc03544 /* CAN Controller 1 Mailbox 10 Data 1 Register */
-#define CAN1_MB10_DATA2 0xffc03548 /* CAN Controller 1 Mailbox 10 Data 2 Register */
-#define CAN1_MB10_DATA3 0xffc0354c /* CAN Controller 1 Mailbox 10 Data 3 Register */
-#define CAN1_MB10_LENGTH 0xffc03550 /* CAN Controller 1 Mailbox 10 Length Register */
-#define CAN1_MB10_TIMESTAMP 0xffc03554 /* CAN Controller 1 Mailbox 10 Timestamp Register */
-#define CAN1_MB10_ID0 0xffc03558 /* CAN Controller 1 Mailbox 10 ID0 Register */
-#define CAN1_MB10_ID1 0xffc0355c /* CAN Controller 1 Mailbox 10 ID1 Register */
-#define CAN1_MB11_DATA0 0xffc03560 /* CAN Controller 1 Mailbox 11 Data 0 Register */
-#define CAN1_MB11_DATA1 0xffc03564 /* CAN Controller 1 Mailbox 11 Data 1 Register */
-#define CAN1_MB11_DATA2 0xffc03568 /* CAN Controller 1 Mailbox 11 Data 2 Register */
-#define CAN1_MB11_DATA3 0xffc0356c /* CAN Controller 1 Mailbox 11 Data 3 Register */
-#define CAN1_MB11_LENGTH 0xffc03570 /* CAN Controller 1 Mailbox 11 Length Register */
-#define CAN1_MB11_TIMESTAMP 0xffc03574 /* CAN Controller 1 Mailbox 11 Timestamp Register */
-#define CAN1_MB11_ID0 0xffc03578 /* CAN Controller 1 Mailbox 11 ID0 Register */
-#define CAN1_MB11_ID1 0xffc0357c /* CAN Controller 1 Mailbox 11 ID1 Register */
-#define CAN1_MB12_DATA0 0xffc03580 /* CAN Controller 1 Mailbox 12 Data 0 Register */
-#define CAN1_MB12_DATA1 0xffc03584 /* CAN Controller 1 Mailbox 12 Data 1 Register */
-#define CAN1_MB12_DATA2 0xffc03588 /* CAN Controller 1 Mailbox 12 Data 2 Register */
-#define CAN1_MB12_DATA3 0xffc0358c /* CAN Controller 1 Mailbox 12 Data 3 Register */
-#define CAN1_MB12_LENGTH 0xffc03590 /* CAN Controller 1 Mailbox 12 Length Register */
-#define CAN1_MB12_TIMESTAMP 0xffc03594 /* CAN Controller 1 Mailbox 12 Timestamp Register */
-#define CAN1_MB12_ID0 0xffc03598 /* CAN Controller 1 Mailbox 12 ID0 Register */
-#define CAN1_MB12_ID1 0xffc0359c /* CAN Controller 1 Mailbox 12 ID1 Register */
-#define CAN1_MB13_DATA0 0xffc035a0 /* CAN Controller 1 Mailbox 13 Data 0 Register */
-#define CAN1_MB13_DATA1 0xffc035a4 /* CAN Controller 1 Mailbox 13 Data 1 Register */
-#define CAN1_MB13_DATA2 0xffc035a8 /* CAN Controller 1 Mailbox 13 Data 2 Register */
-#define CAN1_MB13_DATA3 0xffc035ac /* CAN Controller 1 Mailbox 13 Data 3 Register */
-#define CAN1_MB13_LENGTH 0xffc035b0 /* CAN Controller 1 Mailbox 13 Length Register */
-#define CAN1_MB13_TIMESTAMP 0xffc035b4 /* CAN Controller 1 Mailbox 13 Timestamp Register */
-#define CAN1_MB13_ID0 0xffc035b8 /* CAN Controller 1 Mailbox 13 ID0 Register */
-#define CAN1_MB13_ID1 0xffc035bc /* CAN Controller 1 Mailbox 13 ID1 Register */
-#define CAN1_MB14_DATA0 0xffc035c0 /* CAN Controller 1 Mailbox 14 Data 0 Register */
-#define CAN1_MB14_DATA1 0xffc035c4 /* CAN Controller 1 Mailbox 14 Data 1 Register */
-#define CAN1_MB14_DATA2 0xffc035c8 /* CAN Controller 1 Mailbox 14 Data 2 Register */
-#define CAN1_MB14_DATA3 0xffc035cc /* CAN Controller 1 Mailbox 14 Data 3 Register */
-#define CAN1_MB14_LENGTH 0xffc035d0 /* CAN Controller 1 Mailbox 14 Length Register */
-#define CAN1_MB14_TIMESTAMP 0xffc035d4 /* CAN Controller 1 Mailbox 14 Timestamp Register */
-#define CAN1_MB14_ID0 0xffc035d8 /* CAN Controller 1 Mailbox 14 ID0 Register */
-#define CAN1_MB14_ID1 0xffc035dc /* CAN Controller 1 Mailbox 14 ID1 Register */
-#define CAN1_MB15_DATA0 0xffc035e0 /* CAN Controller 1 Mailbox 15 Data 0 Register */
-#define CAN1_MB15_DATA1 0xffc035e4 /* CAN Controller 1 Mailbox 15 Data 1 Register */
-#define CAN1_MB15_DATA2 0xffc035e8 /* CAN Controller 1 Mailbox 15 Data 2 Register */
-#define CAN1_MB15_DATA3 0xffc035ec /* CAN Controller 1 Mailbox 15 Data 3 Register */
-#define CAN1_MB15_LENGTH 0xffc035f0 /* CAN Controller 1 Mailbox 15 Length Register */
-#define CAN1_MB15_TIMESTAMP 0xffc035f4 /* CAN Controller 1 Mailbox 15 Timestamp Register */
-#define CAN1_MB15_ID0 0xffc035f8 /* CAN Controller 1 Mailbox 15 ID0 Register */
-#define CAN1_MB15_ID1 0xffc035fc /* CAN Controller 1 Mailbox 15 ID1 Register */
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define CAN1_MB16_DATA0 0xffc03600 /* CAN Controller 1 Mailbox 16 Data 0 Register */
-#define CAN1_MB16_DATA1 0xffc03604 /* CAN Controller 1 Mailbox 16 Data 1 Register */
-#define CAN1_MB16_DATA2 0xffc03608 /* CAN Controller 1 Mailbox 16 Data 2 Register */
-#define CAN1_MB16_DATA3 0xffc0360c /* CAN Controller 1 Mailbox 16 Data 3 Register */
-#define CAN1_MB16_LENGTH 0xffc03610 /* CAN Controller 1 Mailbox 16 Length Register */
-#define CAN1_MB16_TIMESTAMP 0xffc03614 /* CAN Controller 1 Mailbox 16 Timestamp Register */
-#define CAN1_MB16_ID0 0xffc03618 /* CAN Controller 1 Mailbox 16 ID0 Register */
-#define CAN1_MB16_ID1 0xffc0361c /* CAN Controller 1 Mailbox 16 ID1 Register */
-#define CAN1_MB17_DATA0 0xffc03620 /* CAN Controller 1 Mailbox 17 Data 0 Register */
-#define CAN1_MB17_DATA1 0xffc03624 /* CAN Controller 1 Mailbox 17 Data 1 Register */
-#define CAN1_MB17_DATA2 0xffc03628 /* CAN Controller 1 Mailbox 17 Data 2 Register */
-#define CAN1_MB17_DATA3 0xffc0362c /* CAN Controller 1 Mailbox 17 Data 3 Register */
-#define CAN1_MB17_LENGTH 0xffc03630 /* CAN Controller 1 Mailbox 17 Length Register */
-#define CAN1_MB17_TIMESTAMP 0xffc03634 /* CAN Controller 1 Mailbox 17 Timestamp Register */
-#define CAN1_MB17_ID0 0xffc03638 /* CAN Controller 1 Mailbox 17 ID0 Register */
-#define CAN1_MB17_ID1 0xffc0363c /* CAN Controller 1 Mailbox 17 ID1 Register */
-#define CAN1_MB18_DATA0 0xffc03640 /* CAN Controller 1 Mailbox 18 Data 0 Register */
-#define CAN1_MB18_DATA1 0xffc03644 /* CAN Controller 1 Mailbox 18 Data 1 Register */
-#define CAN1_MB18_DATA2 0xffc03648 /* CAN Controller 1 Mailbox 18 Data 2 Register */
-#define CAN1_MB18_DATA3 0xffc0364c /* CAN Controller 1 Mailbox 18 Data 3 Register */
-#define CAN1_MB18_LENGTH 0xffc03650 /* CAN Controller 1 Mailbox 18 Length Register */
-#define CAN1_MB18_TIMESTAMP 0xffc03654 /* CAN Controller 1 Mailbox 18 Timestamp Register */
-#define CAN1_MB18_ID0 0xffc03658 /* CAN Controller 1 Mailbox 18 ID0 Register */
-#define CAN1_MB18_ID1 0xffc0365c /* CAN Controller 1 Mailbox 18 ID1 Register */
-#define CAN1_MB19_DATA0 0xffc03660 /* CAN Controller 1 Mailbox 19 Data 0 Register */
-#define CAN1_MB19_DATA1 0xffc03664 /* CAN Controller 1 Mailbox 19 Data 1 Register */
-#define CAN1_MB19_DATA2 0xffc03668 /* CAN Controller 1 Mailbox 19 Data 2 Register */
-#define CAN1_MB19_DATA3 0xffc0366c /* CAN Controller 1 Mailbox 19 Data 3 Register */
-#define CAN1_MB19_LENGTH 0xffc03670 /* CAN Controller 1 Mailbox 19 Length Register */
-#define CAN1_MB19_TIMESTAMP 0xffc03674 /* CAN Controller 1 Mailbox 19 Timestamp Register */
-#define CAN1_MB19_ID0 0xffc03678 /* CAN Controller 1 Mailbox 19 ID0 Register */
-#define CAN1_MB19_ID1 0xffc0367c /* CAN Controller 1 Mailbox 19 ID1 Register */
-#define CAN1_MB20_DATA0 0xffc03680 /* CAN Controller 1 Mailbox 20 Data 0 Register */
-#define CAN1_MB20_DATA1 0xffc03684 /* CAN Controller 1 Mailbox 20 Data 1 Register */
-#define CAN1_MB20_DATA2 0xffc03688 /* CAN Controller 1 Mailbox 20 Data 2 Register */
-#define CAN1_MB20_DATA3 0xffc0368c /* CAN Controller 1 Mailbox 20 Data 3 Register */
-#define CAN1_MB20_LENGTH 0xffc03690 /* CAN Controller 1 Mailbox 20 Length Register */
-#define CAN1_MB20_TIMESTAMP 0xffc03694 /* CAN Controller 1 Mailbox 20 Timestamp Register */
-#define CAN1_MB20_ID0 0xffc03698 /* CAN Controller 1 Mailbox 20 ID0 Register */
-#define CAN1_MB20_ID1 0xffc0369c /* CAN Controller 1 Mailbox 20 ID1 Register */
-#define CAN1_MB21_DATA0 0xffc036a0 /* CAN Controller 1 Mailbox 21 Data 0 Register */
-#define CAN1_MB21_DATA1 0xffc036a4 /* CAN Controller 1 Mailbox 21 Data 1 Register */
-#define CAN1_MB21_DATA2 0xffc036a8 /* CAN Controller 1 Mailbox 21 Data 2 Register */
-#define CAN1_MB21_DATA3 0xffc036ac /* CAN Controller 1 Mailbox 21 Data 3 Register */
-#define CAN1_MB21_LENGTH 0xffc036b0 /* CAN Controller 1 Mailbox 21 Length Register */
-#define CAN1_MB21_TIMESTAMP 0xffc036b4 /* CAN Controller 1 Mailbox 21 Timestamp Register */
-#define CAN1_MB21_ID0 0xffc036b8 /* CAN Controller 1 Mailbox 21 ID0 Register */
-#define CAN1_MB21_ID1 0xffc036bc /* CAN Controller 1 Mailbox 21 ID1 Register */
-#define CAN1_MB22_DATA0 0xffc036c0 /* CAN Controller 1 Mailbox 22 Data 0 Register */
-#define CAN1_MB22_DATA1 0xffc036c4 /* CAN Controller 1 Mailbox 22 Data 1 Register */
-#define CAN1_MB22_DATA2 0xffc036c8 /* CAN Controller 1 Mailbox 22 Data 2 Register */
-#define CAN1_MB22_DATA3 0xffc036cc /* CAN Controller 1 Mailbox 22 Data 3 Register */
-#define CAN1_MB22_LENGTH 0xffc036d0 /* CAN Controller 1 Mailbox 22 Length Register */
-#define CAN1_MB22_TIMESTAMP 0xffc036d4 /* CAN Controller 1 Mailbox 22 Timestamp Register */
-#define CAN1_MB22_ID0 0xffc036d8 /* CAN Controller 1 Mailbox 22 ID0 Register */
-#define CAN1_MB22_ID1 0xffc036dc /* CAN Controller 1 Mailbox 22 ID1 Register */
-#define CAN1_MB23_DATA0 0xffc036e0 /* CAN Controller 1 Mailbox 23 Data 0 Register */
-#define CAN1_MB23_DATA1 0xffc036e4 /* CAN Controller 1 Mailbox 23 Data 1 Register */
-#define CAN1_MB23_DATA2 0xffc036e8 /* CAN Controller 1 Mailbox 23 Data 2 Register */
-#define CAN1_MB23_DATA3 0xffc036ec /* CAN Controller 1 Mailbox 23 Data 3 Register */
-#define CAN1_MB23_LENGTH 0xffc036f0 /* CAN Controller 1 Mailbox 23 Length Register */
-#define CAN1_MB23_TIMESTAMP 0xffc036f4 /* CAN Controller 1 Mailbox 23 Timestamp Register */
-#define CAN1_MB23_ID0 0xffc036f8 /* CAN Controller 1 Mailbox 23 ID0 Register */
-#define CAN1_MB23_ID1 0xffc036fc /* CAN Controller 1 Mailbox 23 ID1 Register */
-#define CAN1_MB24_DATA0 0xffc03700 /* CAN Controller 1 Mailbox 24 Data 0 Register */
-#define CAN1_MB24_DATA1 0xffc03704 /* CAN Controller 1 Mailbox 24 Data 1 Register */
-#define CAN1_MB24_DATA2 0xffc03708 /* CAN Controller 1 Mailbox 24 Data 2 Register */
-#define CAN1_MB24_DATA3 0xffc0370c /* CAN Controller 1 Mailbox 24 Data 3 Register */
-#define CAN1_MB24_LENGTH 0xffc03710 /* CAN Controller 1 Mailbox 24 Length Register */
-#define CAN1_MB24_TIMESTAMP 0xffc03714 /* CAN Controller 1 Mailbox 24 Timestamp Register */
-#define CAN1_MB24_ID0 0xffc03718 /* CAN Controller 1 Mailbox 24 ID0 Register */
-#define CAN1_MB24_ID1 0xffc0371c /* CAN Controller 1 Mailbox 24 ID1 Register */
-#define CAN1_MB25_DATA0 0xffc03720 /* CAN Controller 1 Mailbox 25 Data 0 Register */
-#define CAN1_MB25_DATA1 0xffc03724 /* CAN Controller 1 Mailbox 25 Data 1 Register */
-#define CAN1_MB25_DATA2 0xffc03728 /* CAN Controller 1 Mailbox 25 Data 2 Register */
-#define CAN1_MB25_DATA3 0xffc0372c /* CAN Controller 1 Mailbox 25 Data 3 Register */
-#define CAN1_MB25_LENGTH 0xffc03730 /* CAN Controller 1 Mailbox 25 Length Register */
-#define CAN1_MB25_TIMESTAMP 0xffc03734 /* CAN Controller 1 Mailbox 25 Timestamp Register */
-#define CAN1_MB25_ID0 0xffc03738 /* CAN Controller 1 Mailbox 25 ID0 Register */
-#define CAN1_MB25_ID1 0xffc0373c /* CAN Controller 1 Mailbox 25 ID1 Register */
-#define CAN1_MB26_DATA0 0xffc03740 /* CAN Controller 1 Mailbox 26 Data 0 Register */
-#define CAN1_MB26_DATA1 0xffc03744 /* CAN Controller 1 Mailbox 26 Data 1 Register */
-#define CAN1_MB26_DATA2 0xffc03748 /* CAN Controller 1 Mailbox 26 Data 2 Register */
-#define CAN1_MB26_DATA3 0xffc0374c /* CAN Controller 1 Mailbox 26 Data 3 Register */
-#define CAN1_MB26_LENGTH 0xffc03750 /* CAN Controller 1 Mailbox 26 Length Register */
-#define CAN1_MB26_TIMESTAMP 0xffc03754 /* CAN Controller 1 Mailbox 26 Timestamp Register */
-#define CAN1_MB26_ID0 0xffc03758 /* CAN Controller 1 Mailbox 26 ID0 Register */
-#define CAN1_MB26_ID1 0xffc0375c /* CAN Controller 1 Mailbox 26 ID1 Register */
-#define CAN1_MB27_DATA0 0xffc03760 /* CAN Controller 1 Mailbox 27 Data 0 Register */
-#define CAN1_MB27_DATA1 0xffc03764 /* CAN Controller 1 Mailbox 27 Data 1 Register */
-#define CAN1_MB27_DATA2 0xffc03768 /* CAN Controller 1 Mailbox 27 Data 2 Register */
-#define CAN1_MB27_DATA3 0xffc0376c /* CAN Controller 1 Mailbox 27 Data 3 Register */
-#define CAN1_MB27_LENGTH 0xffc03770 /* CAN Controller 1 Mailbox 27 Length Register */
-#define CAN1_MB27_TIMESTAMP 0xffc03774 /* CAN Controller 1 Mailbox 27 Timestamp Register */
-#define CAN1_MB27_ID0 0xffc03778 /* CAN Controller 1 Mailbox 27 ID0 Register */
-#define CAN1_MB27_ID1 0xffc0377c /* CAN Controller 1 Mailbox 27 ID1 Register */
-#define CAN1_MB28_DATA0 0xffc03780 /* CAN Controller 1 Mailbox 28 Data 0 Register */
-#define CAN1_MB28_DATA1 0xffc03784 /* CAN Controller 1 Mailbox 28 Data 1 Register */
-#define CAN1_MB28_DATA2 0xffc03788 /* CAN Controller 1 Mailbox 28 Data 2 Register */
-#define CAN1_MB28_DATA3 0xffc0378c /* CAN Controller 1 Mailbox 28 Data 3 Register */
-#define CAN1_MB28_LENGTH 0xffc03790 /* CAN Controller 1 Mailbox 28 Length Register */
-#define CAN1_MB28_TIMESTAMP 0xffc03794 /* CAN Controller 1 Mailbox 28 Timestamp Register */
-#define CAN1_MB28_ID0 0xffc03798 /* CAN Controller 1 Mailbox 28 ID0 Register */
-#define CAN1_MB28_ID1 0xffc0379c /* CAN Controller 1 Mailbox 28 ID1 Register */
-#define CAN1_MB29_DATA0 0xffc037a0 /* CAN Controller 1 Mailbox 29 Data 0 Register */
-#define CAN1_MB29_DATA1 0xffc037a4 /* CAN Controller 1 Mailbox 29 Data 1 Register */
-#define CAN1_MB29_DATA2 0xffc037a8 /* CAN Controller 1 Mailbox 29 Data 2 Register */
-#define CAN1_MB29_DATA3 0xffc037ac /* CAN Controller 1 Mailbox 29 Data 3 Register */
-#define CAN1_MB29_LENGTH 0xffc037b0 /* CAN Controller 1 Mailbox 29 Length Register */
-#define CAN1_MB29_TIMESTAMP 0xffc037b4 /* CAN Controller 1 Mailbox 29 Timestamp Register */
-#define CAN1_MB29_ID0 0xffc037b8 /* CAN Controller 1 Mailbox 29 ID0 Register */
-#define CAN1_MB29_ID1 0xffc037bc /* CAN Controller 1 Mailbox 29 ID1 Register */
-#define CAN1_MB30_DATA0 0xffc037c0 /* CAN Controller 1 Mailbox 30 Data 0 Register */
-#define CAN1_MB30_DATA1 0xffc037c4 /* CAN Controller 1 Mailbox 30 Data 1 Register */
-#define CAN1_MB30_DATA2 0xffc037c8 /* CAN Controller 1 Mailbox 30 Data 2 Register */
-#define CAN1_MB30_DATA3 0xffc037cc /* CAN Controller 1 Mailbox 30 Data 3 Register */
-#define CAN1_MB30_LENGTH 0xffc037d0 /* CAN Controller 1 Mailbox 30 Length Register */
-#define CAN1_MB30_TIMESTAMP 0xffc037d4 /* CAN Controller 1 Mailbox 30 Timestamp Register */
-#define CAN1_MB30_ID0 0xffc037d8 /* CAN Controller 1 Mailbox 30 ID0 Register */
-#define CAN1_MB30_ID1 0xffc037dc /* CAN Controller 1 Mailbox 30 ID1 Register */
-#define CAN1_MB31_DATA0 0xffc037e0 /* CAN Controller 1 Mailbox 31 Data 0 Register */
-#define CAN1_MB31_DATA1 0xffc037e4 /* CAN Controller 1 Mailbox 31 Data 1 Register */
-#define CAN1_MB31_DATA2 0xffc037e8 /* CAN Controller 1 Mailbox 31 Data 2 Register */
-#define CAN1_MB31_DATA3 0xffc037ec /* CAN Controller 1 Mailbox 31 Data 3 Register */
-#define CAN1_MB31_LENGTH 0xffc037f0 /* CAN Controller 1 Mailbox 31 Length Register */
-#define CAN1_MB31_TIMESTAMP 0xffc037f4 /* CAN Controller 1 Mailbox 31 Timestamp Register */
-#define CAN1_MB31_ID0 0xffc037f8 /* CAN Controller 1 Mailbox 31 ID0 Register */
-#define CAN1_MB31_ID1 0xffc037fc /* CAN Controller 1 Mailbox 31 ID1 Register */
-
-/* HOST Port Registers */
-
-#define HOST_CONTROL 0xffc03a00 /* HOST Control Register */
-#define HOST_STATUS 0xffc03a04 /* HOST Status Register */
-#define HOST_TIMEOUT 0xffc03a08 /* HOST Acknowledge Mode Timeout Register */
-
-/* Pixel Compositor (PIXC) Registers */
-
-#define PIXC_CTL 0xffc04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
-#define PIXC_PPL 0xffc04404 /* Holds the number of pixels per line of the display */
-#define PIXC_LPF 0xffc04408 /* Holds the number of lines per frame of the display */
-#define PIXC_AHSTART 0xffc0440c /* Contains horizontal start pixel information of the overlay data (set A) */
-#define PIXC_AHEND 0xffc04410 /* Contains horizontal end pixel information of the overlay data (set A) */
-#define PIXC_AVSTART 0xffc04414 /* Contains vertical start pixel information of the overlay data (set A) */
-#define PIXC_AVEND 0xffc04418 /* Contains vertical end pixel information of the overlay data (set A) */
-#define PIXC_ATRANSP 0xffc0441c /* Contains the transparency ratio (set A) */
-#define PIXC_BHSTART 0xffc04420 /* Contains horizontal start pixel information of the overlay data (set B) */
-#define PIXC_BHEND 0xffc04424 /* Contains horizontal end pixel information of the overlay data (set B) */
-#define PIXC_BVSTART 0xffc04428 /* Contains vertical start pixel information of the overlay data (set B) */
-#define PIXC_BVEND 0xffc0442c /* Contains vertical end pixel information of the overlay data (set B) */
-#define PIXC_BTRANSP 0xffc04430 /* Contains the transparency ratio (set B) */
-#define PIXC_INTRSTAT 0xffc0443c /* Overlay interrupt configuration/status */
-#define PIXC_RYCON 0xffc04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
-#define PIXC_GUCON 0xffc04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */
-#define PIXC_BVCON 0xffc04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */
-#define PIXC_CCBIAS 0xffc0444c /* Bias values for the color space conversion matrix */
-#define PIXC_TC 0xffc04450 /* Holds the transparent color value */
-
-/* Handshake MDMA 0 Registers */
-
-#define HMDMA0_CONTROL 0xffc04500 /* Handshake MDMA0 Control Register */
-#define HMDMA0_ECINIT 0xffc04504 /* Handshake MDMA0 Initial Edge Count Register */
-#define HMDMA0_BCINIT 0xffc04508 /* Handshake MDMA0 Initial Block Count Register */
-#define HMDMA0_ECURGENT 0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshold Register */
-#define HMDMA0_ECOVERFLOW 0xffc04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
-#define HMDMA0_ECOUNT 0xffc04514 /* Handshake MDMA0 Current Edge Count Register */
-#define HMDMA0_BCOUNT 0xffc04518 /* Handshake MDMA0 Current Block Count Register */
-
-/* Handshake MDMA 1 Registers */
-
-#define HMDMA1_CONTROL 0xffc04540 /* Handshake MDMA1 Control Register */
-#define HMDMA1_ECINIT 0xffc04544 /* Handshake MDMA1 Initial Edge Count Register */
-#define HMDMA1_BCINIT 0xffc04548 /* Handshake MDMA1 Initial Block Count Register */
-#define HMDMA1_ECURGENT 0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshold Register */
-#define HMDMA1_ECOVERFLOW 0xffc04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
-#define HMDMA1_ECOUNT 0xffc04554 /* Handshake MDMA1 Current Edge Count Register */
-#define HMDMA1_BCOUNT 0xffc04558 /* Handshake MDMA1 Current Block Count Register */
-
-
-/* ********************************************************** */
-/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
-/* and MULTI BIT READ MACROS */
-/* ********************************************************** */
-
-/* Bit masks for PIXC_CTL */
-
-#define PIXC_EN 0x1 /* Pixel Compositor Enable */
-#define OVR_A_EN 0x2 /* Overlay A Enable */
-#define OVR_B_EN 0x4 /* Overlay B Enable */
-#define IMG_FORM 0x8 /* Image Data Format */
-#define OVR_FORM 0x10 /* Overlay Data Format */
-#define OUT_FORM 0x20 /* Output Data Format */
-#define UDS_MOD 0x40 /* Resampling Mode */
-#define TC_EN 0x80 /* Transparent Color Enable */
-#define IMG_STAT 0x300 /* Image FIFO Status */
-#define OVR_STAT 0xc00 /* Overlay FIFO Status */
-#define WM_LVL 0x3000 /* FIFO Watermark Level */
-
-/* Bit masks for PIXC_AHSTART */
-
-#define A_HSTART 0xfff /* Horizontal Start Coordinates */
-
-/* Bit masks for PIXC_AHEND */
-
-#define A_HEND 0xfff /* Horizontal End Coordinates */
-
-/* Bit masks for PIXC_AVSTART */
-
-#define A_VSTART 0x3ff /* Vertical Start Coordinates */
-
-/* Bit masks for PIXC_AVEND */
-
-#define A_VEND 0x3ff /* Vertical End Coordinates */
-
-/* Bit masks for PIXC_ATRANSP */
-
-#define A_TRANSP 0xf /* Transparency Value */
-
-/* Bit masks for PIXC_BHSTART */
-
-#define B_HSTART 0xfff /* Horizontal Start Coordinates */
-
-/* Bit masks for PIXC_BHEND */
-
-#define B_HEND 0xfff /* Horizontal End Coordinates */
-
-/* Bit masks for PIXC_BVSTART */
-
-#define B_VSTART 0x3ff /* Vertical Start Coordinates */
-
-/* Bit masks for PIXC_BVEND */
-
-#define B_VEND 0x3ff /* Vertical End Coordinates */
-
-/* Bit masks for PIXC_BTRANSP */
-
-#define B_TRANSP 0xf /* Transparency Value */
-
-/* Bit masks for PIXC_INTRSTAT */
-
-#define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */
-#define FRM_INT_EN 0x2 /* Interrupt at End of Frame */
-#define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */
-#define FRM_INT_STAT 0x8 /* Frame Interrupt Status */
-
-/* Bit masks for PIXC_RYCON */
-
-#define A11 0x3ff /* A11 in the Coefficient Matrix */
-#define A12 0xffc00 /* A12 in the Coefficient Matrix */
-#define A13 0x3ff00000 /* A13 in the Coefficient Matrix */
-#define RY_MULT4 0x40000000 /* Multiply Row by 4 */
-
-/* Bit masks for PIXC_GUCON */
-
-#define A21 0x3ff /* A21 in the Coefficient Matrix */
-#define A22 0xffc00 /* A22 in the Coefficient Matrix */
-#define A23 0x3ff00000 /* A23 in the Coefficient Matrix */
-#define GU_MULT4 0x40000000 /* Multiply Row by 4 */
-
-/* Bit masks for PIXC_BVCON */
-
-#define A31 0x3ff /* A31 in the Coefficient Matrix */
-#define A32 0xffc00 /* A32 in the Coefficient Matrix */
-#define A33 0x3ff00000 /* A33 in the Coefficient Matrix */
-#define BV_MULT4 0x40000000 /* Multiply Row by 4 */
-
-/* Bit masks for PIXC_CCBIAS */
-
-#define A14 0x3ff /* A14 in the Bias Vector */
-#define A24 0xffc00 /* A24 in the Bias Vector */
-#define A34 0x3ff00000 /* A34 in the Bias Vector */
-
-/* Bit masks for PIXC_TC */
-
-#define RY_TRANS 0xff /* Transparent Color - R/Y Component */
-#define GU_TRANS 0xff00 /* Transparent Color - G/U Component */
-#define BV_TRANS 0xff0000 /* Transparent Color - B/V Component */
-
-/* Bit masks for TIMER_ENABLE1 */
-
-#define TIMEN8 0x1 /* Timer 8 Enable */
-#define TIMEN9 0x2 /* Timer 9 Enable */
-#define TIMEN10 0x4 /* Timer 10 Enable */
-
-/* Bit masks for TIMER_DISABLE1 */
-
-#define TIMDIS8 0x1 /* Timer 8 Disable */
-#define TIMDIS9 0x2 /* Timer 9 Disable */
-#define TIMDIS10 0x4 /* Timer 10 Disable */
-
-/* Bit masks for TIMER_STATUS1 */
-
-#define TIMIL8 0x1 /* Timer 8 Interrupt */
-#define TIMIL9 0x2 /* Timer 9 Interrupt */
-#define TIMIL10 0x4 /* Timer 10 Interrupt */
-#define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */
-#define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */
-#define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */
-#define TRUN8 0x1000 /* Timer 8 Slave Enable Status */
-#define TRUN9 0x2000 /* Timer 9 Slave Enable Status */
-#define TRUN10 0x4000 /* Timer 10 Slave Enable Status */
-
-/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
-
-#endif /* _DEF_BF544_H */
+++ /dev/null
-/*
- * Copyright 2008-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF547_H
-#define _DEF_BF547_H
-
-/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
-#include "defBF54x_base.h"
-
-/* The following are the #defines needed by ADSP-BF547 that are not in the common header */
-
-/* Timer Registers */
-
-#define TIMER8_CONFIG 0xffc00600 /* Timer 8 Configuration Register */
-#define TIMER8_COUNTER 0xffc00604 /* Timer 8 Counter Register */
-#define TIMER8_PERIOD 0xffc00608 /* Timer 8 Period Register */
-#define TIMER8_WIDTH 0xffc0060c /* Timer 8 Width Register */
-#define TIMER9_CONFIG 0xffc00610 /* Timer 9 Configuration Register */
-#define TIMER9_COUNTER 0xffc00614 /* Timer 9 Counter Register */
-#define TIMER9_PERIOD 0xffc00618 /* Timer 9 Period Register */
-#define TIMER9_WIDTH 0xffc0061c /* Timer 9 Width Register */
-#define TIMER10_CONFIG 0xffc00620 /* Timer 10 Configuration Register */
-#define TIMER10_COUNTER 0xffc00624 /* Timer 10 Counter Register */
-#define TIMER10_PERIOD 0xffc00628 /* Timer 10 Period Register */
-#define TIMER10_WIDTH 0xffc0062c /* Timer 10 Width Register */
-
-/* Timer Group of 3 Registers */
-
-#define TIMER_ENABLE1 0xffc00640 /* Timer Group of 3 Enable Register */
-#define TIMER_DISABLE1 0xffc00644 /* Timer Group of 3 Disable Register */
-#define TIMER_STATUS1 0xffc00648 /* Timer Group of 3 Status Register */
-
-/* SPORT0 Registers */
-
-#define SPORT0_TCR1 0xffc00800 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_TCR2 0xffc00804 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_TCLKDIV 0xffc00808 /* SPORT0 Transmit Serial Clock Divider Register */
-#define SPORT0_TFSDIV 0xffc0080c /* SPORT0 Transmit Frame Sync Divider Register */
-#define SPORT0_TX 0xffc00810 /* SPORT0 Transmit Data Register */
-#define SPORT0_RX 0xffc00818 /* SPORT0 Receive Data Register */
-#define SPORT0_RCR1 0xffc00820 /* SPORT0 Receive Configuration 1 Register */
-#define SPORT0_RCR2 0xffc00824 /* SPORT0 Receive Configuration 2 Register */
-#define SPORT0_RCLKDIV 0xffc00828 /* SPORT0 Receive Serial Clock Divider Register */
-#define SPORT0_RFSDIV 0xffc0082c /* SPORT0 Receive Frame Sync Divider Register */
-#define SPORT0_STAT 0xffc00830 /* SPORT0 Status Register */
-#define SPORT0_CHNL 0xffc00834 /* SPORT0 Current Channel Register */
-#define SPORT0_MCMC1 0xffc00838 /* SPORT0 Multi channel Configuration Register 1 */
-#define SPORT0_MCMC2 0xffc0083c /* SPORT0 Multi channel Configuration Register 2 */
-#define SPORT0_MTCS0 0xffc00840 /* SPORT0 Multi channel Transmit Select Register 0 */
-#define SPORT0_MTCS1 0xffc00844 /* SPORT0 Multi channel Transmit Select Register 1 */
-#define SPORT0_MTCS2 0xffc00848 /* SPORT0 Multi channel Transmit Select Register 2 */
-#define SPORT0_MTCS3 0xffc0084c /* SPORT0 Multi channel Transmit Select Register 3 */
-#define SPORT0_MRCS0 0xffc00850 /* SPORT0 Multi channel Receive Select Register 0 */
-#define SPORT0_MRCS1 0xffc00854 /* SPORT0 Multi channel Receive Select Register 1 */
-#define SPORT0_MRCS2 0xffc00858 /* SPORT0 Multi channel Receive Select Register 2 */
-#define SPORT0_MRCS3 0xffc0085c /* SPORT0 Multi channel Receive Select Register 3 */
-
-/* EPPI0 Registers */
-
-#define EPPI0_STATUS 0xffc01000 /* EPPI0 Status Register */
-#define EPPI0_HCOUNT 0xffc01004 /* EPPI0 Horizontal Transfer Count Register */
-#define EPPI0_HDELAY 0xffc01008 /* EPPI0 Horizontal Delay Count Register */
-#define EPPI0_VCOUNT 0xffc0100c /* EPPI0 Vertical Transfer Count Register */
-#define EPPI0_VDELAY 0xffc01010 /* EPPI0 Vertical Delay Count Register */
-#define EPPI0_FRAME 0xffc01014 /* EPPI0 Lines per Frame Register */
-#define EPPI0_LINE 0xffc01018 /* EPPI0 Samples per Line Register */
-#define EPPI0_CLKDIV 0xffc0101c /* EPPI0 Clock Divide Register */
-#define EPPI0_CONTROL 0xffc01020 /* EPPI0 Control Register */
-#define EPPI0_FS1W_HBL 0xffc01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
-#define EPPI0_FS1P_AVPL 0xffc01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
-#define EPPI0_FS2W_LVB 0xffc0102c /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
-#define EPPI0_FS2P_LAVF 0xffc01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
-#define EPPI0_CLIP 0xffc01034 /* EPPI0 Clipping Register */
-
-/* UART2 Registers */
-
-#define UART2_DLL 0xffc02100 /* Divisor Latch Low Byte */
-#define UART2_DLH 0xffc02104 /* Divisor Latch High Byte */
-#define UART2_GCTL 0xffc02108 /* Global Control Register */
-#define UART2_LCR 0xffc0210c /* Line Control Register */
-#define UART2_MCR 0xffc02110 /* Modem Control Register */
-#define UART2_LSR 0xffc02114 /* Line Status Register */
-#define UART2_MSR 0xffc02118 /* Modem Status Register */
-#define UART2_SCR 0xffc0211c /* Scratch Register */
-#define UART2_IER_SET 0xffc02120 /* Interrupt Enable Register Set */
-#define UART2_IER_CLEAR 0xffc02124 /* Interrupt Enable Register Clear */
-#define UART2_RBR 0xffc0212c /* Receive Buffer Register */
-
-/* Two Wire Interface Registers (TWI1) */
-
-#define TWI1_REGBASE 0xffc02200
-#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */
-#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */
-#define TWI1_SLAVE_CTL 0xffc02208 /* TWI Slave Mode Control Register */
-#define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */
-#define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */
-#define TWI1_MASTER_CTL 0xffc02214 /* TWI Master Mode Control Register */
-#define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */
-#define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */
-#define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */
-#define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */
-#define TWI1_FIFO_CTL 0xffc02228 /* TWI FIFO Control Register */
-#define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */
-#define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */
-#define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */
-#define TWI1_RCV_DATA8 0xffc02288 /* TWI FIFO Receive Data Single Byte Register */
-#define TWI1_RCV_DATA16 0xffc0228c /* TWI FIFO Receive Data Double Byte Register */
-
-/* SPI2 Registers */
-
-#define SPI2_REGBASE 0xffc02400
-#define SPI2_CTL 0xffc02400 /* SPI2 Control Register */
-#define SPI2_FLG 0xffc02404 /* SPI2 Flag Register */
-#define SPI2_STAT 0xffc02408 /* SPI2 Status Register */
-#define SPI2_TDBR 0xffc0240c /* SPI2 Transmit Data Buffer Register */
-#define SPI2_RDBR 0xffc02410 /* SPI2 Receive Data Buffer Register */
-#define SPI2_BAUD 0xffc02414 /* SPI2 Baud Rate Register */
-#define SPI2_SHADOW 0xffc02418 /* SPI2 Receive Data Buffer Shadow Register */
-
-/* ATAPI Registers */
-
-#define ATAPI_CONTROL 0xffc03800 /* ATAPI Control Register */
-#define ATAPI_STATUS 0xffc03804 /* ATAPI Status Register */
-#define ATAPI_DEV_ADDR 0xffc03808 /* ATAPI Device Register Address */
-#define ATAPI_DEV_TXBUF 0xffc0380c /* ATAPI Device Register Write Data */
-#define ATAPI_DEV_RXBUF 0xffc03810 /* ATAPI Device Register Read Data */
-#define ATAPI_INT_MASK 0xffc03814 /* ATAPI Interrupt Mask Register */
-#define ATAPI_INT_STATUS 0xffc03818 /* ATAPI Interrupt Status Register */
-#define ATAPI_XFER_LEN 0xffc0381c /* ATAPI Length of Transfer */
-#define ATAPI_LINE_STATUS 0xffc03820 /* ATAPI Line Status */
-#define ATAPI_SM_STATE 0xffc03824 /* ATAPI State Machine Status */
-#define ATAPI_TERMINATE 0xffc03828 /* ATAPI Host Terminate */
-#define ATAPI_PIO_TFRCNT 0xffc0382c /* ATAPI PIO mode transfer count */
-#define ATAPI_DMA_TFRCNT 0xffc03830 /* ATAPI DMA mode transfer count */
-#define ATAPI_UMAIN_TFRCNT 0xffc03834 /* ATAPI UDMAIN transfer count */
-#define ATAPI_UDMAOUT_TFRCNT 0xffc03838 /* ATAPI UDMAOUT transfer count */
-#define ATAPI_REG_TIM_0 0xffc03840 /* ATAPI Register Transfer Timing 0 */
-#define ATAPI_PIO_TIM_0 0xffc03844 /* ATAPI PIO Timing 0 Register */
-#define ATAPI_PIO_TIM_1 0xffc03848 /* ATAPI PIO Timing 1 Register */
-#define ATAPI_MULTI_TIM_0 0xffc03850 /* ATAPI Multi-DMA Timing 0 Register */
-#define ATAPI_MULTI_TIM_1 0xffc03854 /* ATAPI Multi-DMA Timing 1 Register */
-#define ATAPI_MULTI_TIM_2 0xffc03858 /* ATAPI Multi-DMA Timing 2 Register */
-#define ATAPI_ULTRA_TIM_0 0xffc03860 /* ATAPI Ultra-DMA Timing 0 Register */
-#define ATAPI_ULTRA_TIM_1 0xffc03864 /* ATAPI Ultra-DMA Timing 1 Register */
-#define ATAPI_ULTRA_TIM_2 0xffc03868 /* ATAPI Ultra-DMA Timing 2 Register */
-#define ATAPI_ULTRA_TIM_3 0xffc0386c /* ATAPI Ultra-DMA Timing 3 Register */
-
-/* SDH Registers */
-
-#define SDH_PWR_CTL 0xffc03900 /* SDH Power Control */
-#define SDH_CLK_CTL 0xffc03904 /* SDH Clock Control */
-#define SDH_ARGUMENT 0xffc03908 /* SDH Argument */
-#define SDH_COMMAND 0xffc0390c /* SDH Command */
-#define SDH_RESP_CMD 0xffc03910 /* SDH Response Command */
-#define SDH_RESPONSE0 0xffc03914 /* SDH Response0 */
-#define SDH_RESPONSE1 0xffc03918 /* SDH Response1 */
-#define SDH_RESPONSE2 0xffc0391c /* SDH Response2 */
-#define SDH_RESPONSE3 0xffc03920 /* SDH Response3 */
-#define SDH_DATA_TIMER 0xffc03924 /* SDH Data Timer */
-#define SDH_DATA_LGTH 0xffc03928 /* SDH Data Length */
-#define SDH_DATA_CTL 0xffc0392c /* SDH Data Control */
-#define SDH_DATA_CNT 0xffc03930 /* SDH Data Counter */
-#define SDH_STATUS 0xffc03934 /* SDH Status */
-#define SDH_STATUS_CLR 0xffc03938 /* SDH Status Clear */
-#define SDH_MASK0 0xffc0393c /* SDH Interrupt0 Mask */
-#define SDH_MASK1 0xffc03940 /* SDH Interrupt1 Mask */
-#define SDH_FIFO_CNT 0xffc03948 /* SDH FIFO Counter */
-#define SDH_FIFO 0xffc03980 /* SDH Data FIFO */
-#define SDH_E_STATUS 0xffc039c0 /* SDH Exception Status */
-#define SDH_E_MASK 0xffc039c4 /* SDH Exception Mask */
-#define SDH_CFG 0xffc039c8 /* SDH Configuration */
-#define SDH_RD_WAIT_EN 0xffc039cc /* SDH Read Wait Enable */
-#define SDH_PID0 0xffc039d0 /* SDH Peripheral Identification0 */
-#define SDH_PID1 0xffc039d4 /* SDH Peripheral Identification1 */
-#define SDH_PID2 0xffc039d8 /* SDH Peripheral Identification2 */
-#define SDH_PID3 0xffc039dc /* SDH Peripheral Identification3 */
-#define SDH_PID4 0xffc039e0 /* SDH Peripheral Identification4 */
-#define SDH_PID5 0xffc039e4 /* SDH Peripheral Identification5 */
-#define SDH_PID6 0xffc039e8 /* SDH Peripheral Identification6 */
-#define SDH_PID7 0xffc039ec /* SDH Peripheral Identification7 */
-
-/* HOST Port Registers */
-
-#define HOST_CONTROL 0xffc03a00 /* HOST Control Register */
-#define HOST_STATUS 0xffc03a04 /* HOST Status Register */
-#define HOST_TIMEOUT 0xffc03a08 /* HOST Acknowledge Mode Timeout Register */
-
-/* USB Control Registers */
-
-#define USB_FADDR 0xffc03c00 /* Function address register */
-#define USB_POWER 0xffc03c04 /* Power management register */
-#define USB_INTRTX 0xffc03c08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
-#define USB_INTRRX 0xffc03c0c /* Interrupt register for Rx endpoints 1 to 7 */
-#define USB_INTRTXE 0xffc03c10 /* Interrupt enable register for IntrTx */
-#define USB_INTRRXE 0xffc03c14 /* Interrupt enable register for IntrRx */
-#define USB_INTRUSB 0xffc03c18 /* Interrupt register for common USB interrupts */
-#define USB_INTRUSBE 0xffc03c1c /* Interrupt enable register for IntrUSB */
-#define USB_FRAME 0xffc03c20 /* USB frame number */
-#define USB_INDEX 0xffc03c24 /* Index register for selecting the indexed endpoint registers */
-#define USB_TESTMODE 0xffc03c28 /* Enabled USB 20 test modes */
-#define USB_GLOBINTR 0xffc03c2c /* Global Interrupt Mask register and Wakeup Exception Interrupt */
-#define USB_GLOBAL_CTL 0xffc03c30 /* Global Clock Control for the core */
-
-/* USB Packet Control Registers */
-
-#define USB_TX_MAX_PACKET 0xffc03c40 /* Maximum packet size for Host Tx endpoint */
-#define USB_CSR0 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define USB_TXCSR 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define USB_RX_MAX_PACKET 0xffc03c48 /* Maximum packet size for Host Rx endpoint */
-#define USB_RXCSR 0xffc03c4c /* Control Status register for Host Rx endpoint */
-#define USB_COUNT0 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define USB_RXCOUNT 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define USB_TXTYPE 0xffc03c54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
-#define USB_NAKLIMIT0 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define USB_TXINTERVAL 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define USB_RXTYPE 0xffc03c5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
-#define USB_RXINTERVAL 0xffc03c60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
-#define USB_TXCOUNT 0xffc03c68 /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* USB Endpoint FIFO Registers */
-
-#define USB_EP0_FIFO 0xffc03c80 /* Endpoint 0 FIFO */
-#define USB_EP1_FIFO 0xffc03c88 /* Endpoint 1 FIFO */
-#define USB_EP2_FIFO 0xffc03c90 /* Endpoint 2 FIFO */
-#define USB_EP3_FIFO 0xffc03c98 /* Endpoint 3 FIFO */
-#define USB_EP4_FIFO 0xffc03ca0 /* Endpoint 4 FIFO */
-#define USB_EP5_FIFO 0xffc03ca8 /* Endpoint 5 FIFO */
-#define USB_EP6_FIFO 0xffc03cb0 /* Endpoint 6 FIFO */
-#define USB_EP7_FIFO 0xffc03cb8 /* Endpoint 7 FIFO */
-
-/* USB OTG Control Registers */
-
-#define USB_OTG_DEV_CTL 0xffc03d00 /* OTG Device Control Register */
-#define USB_OTG_VBUS_IRQ 0xffc03d04 /* OTG VBUS Control Interrupts */
-#define USB_OTG_VBUS_MASK 0xffc03d08 /* VBUS Control Interrupt Enable */
-
-/* USB Phy Control Registers */
-
-#define USB_LINKINFO 0xffc03d48 /* Enables programming of some PHY-side delays */
-#define USB_VPLEN 0xffc03d4c /* Determines duration of VBUS pulse for VBUS charging */
-#define USB_HS_EOF1 0xffc03d50 /* Time buffer for High-Speed transactions */
-#define USB_FS_EOF1 0xffc03d54 /* Time buffer for Full-Speed transactions */
-#define USB_LS_EOF1 0xffc03d58 /* Time buffer for Low-Speed transactions */
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define USB_APHY_CNTRL 0xffc03de0 /* Register that increases visibility of Analog PHY */
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define USB_APHY_CALIB 0xffc03de4 /* Register used to set some calibration values */
-#define USB_APHY_CNTRL2 0xffc03de8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
-
-#define USB_PLLOSC_CTRL 0xffc03df0 /* Used to program different parameters for USB PLL and Oscillator */
-#define USB_SRP_CLKDIV 0xffc03df4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
-
-/* USB Endpoint 0 Control Registers */
-
-#define USB_EP_NI0_TXMAXP 0xffc03e00 /* Maximum packet size for Host Tx endpoint0 */
-#define USB_EP_NI0_TXCSR 0xffc03e04 /* Control Status register for endpoint 0 */
-#define USB_EP_NI0_RXMAXP 0xffc03e08 /* Maximum packet size for Host Rx endpoint0 */
-#define USB_EP_NI0_RXCSR 0xffc03e0c /* Control Status register for Host Rx endpoint0 */
-#define USB_EP_NI0_RXCOUNT 0xffc03e10 /* Number of bytes received in endpoint 0 FIFO */
-#define USB_EP_NI0_TXTYPE 0xffc03e14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
-#define USB_EP_NI0_TXINTERVAL 0xffc03e18 /* Sets the NAK response timeout on Endpoint 0 */
-#define USB_EP_NI0_RXTYPE 0xffc03e1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
-#define USB_EP_NI0_RXINTERVAL 0xffc03e20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
-#define USB_EP_NI0_TXCOUNT 0xffc03e28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
-
-/* USB Endpoint 1 Control Registers */
-
-#define USB_EP_NI1_TXMAXP 0xffc03e40 /* Maximum packet size for Host Tx endpoint1 */
-#define USB_EP_NI1_TXCSR 0xffc03e44 /* Control Status register for endpoint1 */
-#define USB_EP_NI1_RXMAXP 0xffc03e48 /* Maximum packet size for Host Rx endpoint1 */
-#define USB_EP_NI1_RXCSR 0xffc03e4c /* Control Status register for Host Rx endpoint1 */
-#define USB_EP_NI1_RXCOUNT 0xffc03e50 /* Number of bytes received in endpoint1 FIFO */
-#define USB_EP_NI1_TXTYPE 0xffc03e54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
-#define USB_EP_NI1_TXINTERVAL 0xffc03e58 /* Sets the NAK response timeout on Endpoint1 */
-#define USB_EP_NI1_RXTYPE 0xffc03e5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
-#define USB_EP_NI1_RXINTERVAL 0xffc03e60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
-#define USB_EP_NI1_TXCOUNT 0xffc03e68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
-
-/* USB Endpoint 2 Control Registers */
-
-#define USB_EP_NI2_TXMAXP 0xffc03e80 /* Maximum packet size for Host Tx endpoint2 */
-#define USB_EP_NI2_TXCSR 0xffc03e84 /* Control Status register for endpoint2 */
-#define USB_EP_NI2_RXMAXP 0xffc03e88 /* Maximum packet size for Host Rx endpoint2 */
-#define USB_EP_NI2_RXCSR 0xffc03e8c /* Control Status register for Host Rx endpoint2 */
-#define USB_EP_NI2_RXCOUNT 0xffc03e90 /* Number of bytes received in endpoint2 FIFO */
-#define USB_EP_NI2_TXTYPE 0xffc03e94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
-#define USB_EP_NI2_TXINTERVAL 0xffc03e98 /* Sets the NAK response timeout on Endpoint2 */
-#define USB_EP_NI2_RXTYPE 0xffc03e9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
-#define USB_EP_NI2_RXINTERVAL 0xffc03ea0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
-#define USB_EP_NI2_TXCOUNT 0xffc03ea8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
-
-/* USB Endpoint 3 Control Registers */
-
-#define USB_EP_NI3_TXMAXP 0xffc03ec0 /* Maximum packet size for Host Tx endpoint3 */
-#define USB_EP_NI3_TXCSR 0xffc03ec4 /* Control Status register for endpoint3 */
-#define USB_EP_NI3_RXMAXP 0xffc03ec8 /* Maximum packet size for Host Rx endpoint3 */
-#define USB_EP_NI3_RXCSR 0xffc03ecc /* Control Status register for Host Rx endpoint3 */
-#define USB_EP_NI3_RXCOUNT 0xffc03ed0 /* Number of bytes received in endpoint3 FIFO */
-#define USB_EP_NI3_TXTYPE 0xffc03ed4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
-#define USB_EP_NI3_TXINTERVAL 0xffc03ed8 /* Sets the NAK response timeout on Endpoint3 */
-#define USB_EP_NI3_RXTYPE 0xffc03edc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
-#define USB_EP_NI3_RXINTERVAL 0xffc03ee0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
-#define USB_EP_NI3_TXCOUNT 0xffc03ee8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
-
-/* USB Endpoint 4 Control Registers */
-
-#define USB_EP_NI4_TXMAXP 0xffc03f00 /* Maximum packet size for Host Tx endpoint4 */
-#define USB_EP_NI4_TXCSR 0xffc03f04 /* Control Status register for endpoint4 */
-#define USB_EP_NI4_RXMAXP 0xffc03f08 /* Maximum packet size for Host Rx endpoint4 */
-#define USB_EP_NI4_RXCSR 0xffc03f0c /* Control Status register for Host Rx endpoint4 */
-#define USB_EP_NI4_RXCOUNT 0xffc03f10 /* Number of bytes received in endpoint4 FIFO */
-#define USB_EP_NI4_TXTYPE 0xffc03f14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
-#define USB_EP_NI4_TXINTERVAL 0xffc03f18 /* Sets the NAK response timeout on Endpoint4 */
-#define USB_EP_NI4_RXTYPE 0xffc03f1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
-#define USB_EP_NI4_RXINTERVAL 0xffc03f20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
-#define USB_EP_NI4_TXCOUNT 0xffc03f28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
-
-/* USB Endpoint 5 Control Registers */
-
-#define USB_EP_NI5_TXMAXP 0xffc03f40 /* Maximum packet size for Host Tx endpoint5 */
-#define USB_EP_NI5_TXCSR 0xffc03f44 /* Control Status register for endpoint5 */
-#define USB_EP_NI5_RXMAXP 0xffc03f48 /* Maximum packet size for Host Rx endpoint5 */
-#define USB_EP_NI5_RXCSR 0xffc03f4c /* Control Status register for Host Rx endpoint5 */
-#define USB_EP_NI5_RXCOUNT 0xffc03f50 /* Number of bytes received in endpoint5 FIFO */
-#define USB_EP_NI5_TXTYPE 0xffc03f54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
-#define USB_EP_NI5_TXINTERVAL 0xffc03f58 /* Sets the NAK response timeout on Endpoint5 */
-#define USB_EP_NI5_RXTYPE 0xffc03f5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
-#define USB_EP_NI5_RXINTERVAL 0xffc03f60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
-#define USB_EP_NI5_TXCOUNT 0xffc03f68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
-
-/* USB Endpoint 6 Control Registers */
-
-#define USB_EP_NI6_TXMAXP 0xffc03f80 /* Maximum packet size for Host Tx endpoint6 */
-#define USB_EP_NI6_TXCSR 0xffc03f84 /* Control Status register for endpoint6 */
-#define USB_EP_NI6_RXMAXP 0xffc03f88 /* Maximum packet size for Host Rx endpoint6 */
-#define USB_EP_NI6_RXCSR 0xffc03f8c /* Control Status register for Host Rx endpoint6 */
-#define USB_EP_NI6_RXCOUNT 0xffc03f90 /* Number of bytes received in endpoint6 FIFO */
-#define USB_EP_NI6_TXTYPE 0xffc03f94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
-#define USB_EP_NI6_TXINTERVAL 0xffc03f98 /* Sets the NAK response timeout on Endpoint6 */
-#define USB_EP_NI6_RXTYPE 0xffc03f9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
-#define USB_EP_NI6_RXINTERVAL 0xffc03fa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
-#define USB_EP_NI6_TXCOUNT 0xffc03fa8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
-
-/* USB Endpoint 7 Control Registers */
-
-#define USB_EP_NI7_TXMAXP 0xffc03fc0 /* Maximum packet size for Host Tx endpoint7 */
-#define USB_EP_NI7_TXCSR 0xffc03fc4 /* Control Status register for endpoint7 */
-#define USB_EP_NI7_RXMAXP 0xffc03fc8 /* Maximum packet size for Host Rx endpoint7 */
-#define USB_EP_NI7_RXCSR 0xffc03fcc /* Control Status register for Host Rx endpoint7 */
-#define USB_EP_NI7_RXCOUNT 0xffc03fd0 /* Number of bytes received in endpoint7 FIFO */
-#define USB_EP_NI7_TXTYPE 0xffc03fd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
-#define USB_EP_NI7_TXINTERVAL 0xffc03fd8 /* Sets the NAK response timeout on Endpoint7 */
-#define USB_EP_NI7_RXTYPE 0xffc03fdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
-#define USB_EP_NI7_RXINTERVAL 0xffc03fe0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
-#define USB_EP_NI7_TXCOUNT 0xffc03fe8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
-
-#define USB_DMA_INTERRUPT 0xffc04000 /* Indicates pending interrupts for the DMA channels */
-
-/* USB Channel 0 Config Registers */
-
-#define USB_DMA0CONTROL 0xffc04004 /* DMA master channel 0 configuration */
-#define USB_DMA0ADDRLOW 0xffc04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
-#define USB_DMA0ADDRHIGH 0xffc0400c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
-#define USB_DMA0COUNTLOW 0xffc04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define USB_DMA0COUNTHIGH 0xffc04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
-
-/* USB Channel 1 Config Registers */
-
-#define USB_DMA1CONTROL 0xffc04024 /* DMA master channel 1 configuration */
-#define USB_DMA1ADDRLOW 0xffc04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
-#define USB_DMA1ADDRHIGH 0xffc0402c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
-#define USB_DMA1COUNTLOW 0xffc04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define USB_DMA1COUNTHIGH 0xffc04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
-
-/* USB Channel 2 Config Registers */
-
-#define USB_DMA2CONTROL 0xffc04044 /* DMA master channel 2 configuration */
-#define USB_DMA2ADDRLOW 0xffc04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
-#define USB_DMA2ADDRHIGH 0xffc0404c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
-#define USB_DMA2COUNTLOW 0xffc04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define USB_DMA2COUNTHIGH 0xffc04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
-
-/* USB Channel 3 Config Registers */
-
-#define USB_DMA3CONTROL 0xffc04064 /* DMA master channel 3 configuration */
-#define USB_DMA3ADDRLOW 0xffc04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
-#define USB_DMA3ADDRHIGH 0xffc0406c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
-#define USB_DMA3COUNTLOW 0xffc04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define USB_DMA3COUNTHIGH 0xffc04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
-
-/* USB Channel 4 Config Registers */
-
-#define USB_DMA4CONTROL 0xffc04084 /* DMA master channel 4 configuration */
-#define USB_DMA4ADDRLOW 0xffc04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
-#define USB_DMA4ADDRHIGH 0xffc0408c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
-#define USB_DMA4COUNTLOW 0xffc04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define USB_DMA4COUNTHIGH 0xffc04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
-
-/* USB Channel 5 Config Registers */
-
-#define USB_DMA5CONTROL 0xffc040a4 /* DMA master channel 5 configuration */
-#define USB_DMA5ADDRLOW 0xffc040a8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
-#define USB_DMA5ADDRHIGH 0xffc040ac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
-#define USB_DMA5COUNTLOW 0xffc040b0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define USB_DMA5COUNTHIGH 0xffc040b4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
-
-/* USB Channel 6 Config Registers */
-
-#define USB_DMA6CONTROL 0xffc040c4 /* DMA master channel 6 configuration */
-#define USB_DMA6ADDRLOW 0xffc040c8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
-#define USB_DMA6ADDRHIGH 0xffc040cc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
-#define USB_DMA6COUNTLOW 0xffc040d0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define USB_DMA6COUNTHIGH 0xffc040d4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
-
-/* USB Channel 7 Config Registers */
-
-#define USB_DMA7CONTROL 0xffc040e4 /* DMA master channel 7 configuration */
-#define USB_DMA7ADDRLOW 0xffc040e8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
-#define USB_DMA7ADDRHIGH 0xffc040ec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
-#define USB_DMA7COUNTLOW 0xffc040f0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
-#define USB_DMA7COUNTHIGH 0xffc040f4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
-
-/* Keypad Registers */
-
-#define KPAD_CTL 0xffc04100 /* Controls keypad module enable and disable */
-#define KPAD_PRESCALE 0xffc04104 /* Establish a time base for programing the KPAD_MSEL register */
-#define KPAD_MSEL 0xffc04108 /* Selects delay parameters for keypad interface sensitivity */
-#define KPAD_ROWCOL 0xffc0410c /* Captures the row and column output values of the keys pressed */
-#define KPAD_STAT 0xffc04110 /* Holds and clears the status of the keypad interface interrupt */
-#define KPAD_SOFTEVAL 0xffc04114 /* Lets software force keypad interface to check for keys being pressed */
-
-/* Pixel Compositor (PIXC) Registers */
-
-#define PIXC_CTL 0xffc04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
-#define PIXC_PPL 0xffc04404 /* Holds the number of pixels per line of the display */
-#define PIXC_LPF 0xffc04408 /* Holds the number of lines per frame of the display */
-#define PIXC_AHSTART 0xffc0440c /* Contains horizontal start pixel information of the overlay data (set A) */
-#define PIXC_AHEND 0xffc04410 /* Contains horizontal end pixel information of the overlay data (set A) */
-#define PIXC_AVSTART 0xffc04414 /* Contains vertical start pixel information of the overlay data (set A) */
-#define PIXC_AVEND 0xffc04418 /* Contains vertical end pixel information of the overlay data (set A) */
-#define PIXC_ATRANSP 0xffc0441c /* Contains the transparency ratio (set A) */
-#define PIXC_BHSTART 0xffc04420 /* Contains horizontal start pixel information of the overlay data (set B) */
-#define PIXC_BHEND 0xffc04424 /* Contains horizontal end pixel information of the overlay data (set B) */
-#define PIXC_BVSTART 0xffc04428 /* Contains vertical start pixel information of the overlay data (set B) */
-#define PIXC_BVEND 0xffc0442c /* Contains vertical end pixel information of the overlay data (set B) */
-#define PIXC_BTRANSP 0xffc04430 /* Contains the transparency ratio (set B) */
-#define PIXC_INTRSTAT 0xffc0443c /* Overlay interrupt configuration/status */
-#define PIXC_RYCON 0xffc04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
-#define PIXC_GUCON 0xffc04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */
-#define PIXC_BVCON 0xffc04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */
-#define PIXC_CCBIAS 0xffc0444c /* Bias values for the color space conversion matrix */
-#define PIXC_TC 0xffc04450 /* Holds the transparent color value */
-
-/* Handshake MDMA 0 Registers */
-
-#define HMDMA0_CONTROL 0xffc04500 /* Handshake MDMA0 Control Register */
-#define HMDMA0_ECINIT 0xffc04504 /* Handshake MDMA0 Initial Edge Count Register */
-#define HMDMA0_BCINIT 0xffc04508 /* Handshake MDMA0 Initial Block Count Register */
-#define HMDMA0_ECURGENT 0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshold Register */
-#define HMDMA0_ECOVERFLOW 0xffc04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
-#define HMDMA0_ECOUNT 0xffc04514 /* Handshake MDMA0 Current Edge Count Register */
-#define HMDMA0_BCOUNT 0xffc04518 /* Handshake MDMA0 Current Block Count Register */
-
-/* Handshake MDMA 1 Registers */
-
-#define HMDMA1_CONTROL 0xffc04540 /* Handshake MDMA1 Control Register */
-#define HMDMA1_ECINIT 0xffc04544 /* Handshake MDMA1 Initial Edge Count Register */
-#define HMDMA1_BCINIT 0xffc04548 /* Handshake MDMA1 Initial Block Count Register */
-#define HMDMA1_ECURGENT 0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshold Register */
-#define HMDMA1_ECOVERFLOW 0xffc04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
-#define HMDMA1_ECOUNT 0xffc04554 /* Handshake MDMA1 Current Edge Count Register */
-#define HMDMA1_BCOUNT 0xffc04558 /* Handshake MDMA1 Current Block Count Register */
-
-
-/* ********************************************************** */
-/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
-/* and MULTI BIT READ MACROS */
-/* ********************************************************** */
-
-/* Bit masks for PIXC_CTL */
-
-#define PIXC_EN 0x1 /* Pixel Compositor Enable */
-#define OVR_A_EN 0x2 /* Overlay A Enable */
-#define OVR_B_EN 0x4 /* Overlay B Enable */
-#define IMG_FORM 0x8 /* Image Data Format */
-#define OVR_FORM 0x10 /* Overlay Data Format */
-#define OUT_FORM 0x20 /* Output Data Format */
-#define UDS_MOD 0x40 /* Resampling Mode */
-#define TC_EN 0x80 /* Transparent Color Enable */
-#define IMG_STAT 0x300 /* Image FIFO Status */
-#define OVR_STAT 0xc00 /* Overlay FIFO Status */
-#define WM_LVL 0x3000 /* FIFO Watermark Level */
-
-/* Bit masks for PIXC_AHSTART */
-
-#define A_HSTART 0xfff /* Horizontal Start Coordinates */
-
-/* Bit masks for PIXC_AHEND */
-
-#define A_HEND 0xfff /* Horizontal End Coordinates */
-
-/* Bit masks for PIXC_AVSTART */
-
-#define A_VSTART 0x3ff /* Vertical Start Coordinates */
-
-/* Bit masks for PIXC_AVEND */
-
-#define A_VEND 0x3ff /* Vertical End Coordinates */
-
-/* Bit masks for PIXC_ATRANSP */
-
-#define A_TRANSP 0xf /* Transparency Value */
-
-/* Bit masks for PIXC_BHSTART */
-
-#define B_HSTART 0xfff /* Horizontal Start Coordinates */
-
-/* Bit masks for PIXC_BHEND */
-
-#define B_HEND 0xfff /* Horizontal End Coordinates */
-
-/* Bit masks for PIXC_BVSTART */
-
-#define B_VSTART 0x3ff /* Vertical Start Coordinates */
-
-/* Bit masks for PIXC_BVEND */
-
-#define B_VEND 0x3ff /* Vertical End Coordinates */
-
-/* Bit masks for PIXC_BTRANSP */
-
-#define B_TRANSP 0xf /* Transparency Value */
-
-/* Bit masks for PIXC_INTRSTAT */
-
-#define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */
-#define FRM_INT_EN 0x2 /* Interrupt at End of Frame */
-#define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */
-#define FRM_INT_STAT 0x8 /* Frame Interrupt Status */
-
-/* Bit masks for PIXC_RYCON */
-
-#define A11 0x3ff /* A11 in the Coefficient Matrix */
-#define A12 0xffc00 /* A12 in the Coefficient Matrix */
-#define A13 0x3ff00000 /* A13 in the Coefficient Matrix */
-#define RY_MULT4 0x40000000 /* Multiply Row by 4 */
-
-/* Bit masks for PIXC_GUCON */
-
-#define A21 0x3ff /* A21 in the Coefficient Matrix */
-#define A22 0xffc00 /* A22 in the Coefficient Matrix */
-#define A23 0x3ff00000 /* A23 in the Coefficient Matrix */
-#define GU_MULT4 0x40000000 /* Multiply Row by 4 */
-
-/* Bit masks for PIXC_BVCON */
-
-#define A31 0x3ff /* A31 in the Coefficient Matrix */
-#define A32 0xffc00 /* A32 in the Coefficient Matrix */
-#define A33 0x3ff00000 /* A33 in the Coefficient Matrix */
-#define BV_MULT4 0x40000000 /* Multiply Row by 4 */
-
-/* Bit masks for PIXC_CCBIAS */
-
-#define A14 0x3ff /* A14 in the Bias Vector */
-#define A24 0xffc00 /* A24 in the Bias Vector */
-#define A34 0x3ff00000 /* A34 in the Bias Vector */
-
-/* Bit masks for PIXC_TC */
-
-#define RY_TRANS 0xff /* Transparent Color - R/Y Component */
-#define GU_TRANS 0xff00 /* Transparent Color - G/U Component */
-#define BV_TRANS 0xff0000 /* Transparent Color - B/V Component */
-
-/* Bit masks for KPAD_CTL */
-
-#define KPAD_EN 0x1 /* Keypad Enable */
-#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */
-#define KPAD_ROWEN 0x1c00 /* Row Enable Width */
-#define KPAD_COLEN 0xe000 /* Column Enable Width */
-
-/* Bit masks for KPAD_PRESCALE */
-
-#define KPAD_PRESCALE_VAL 0x3f /* Key Prescale Value */
-
-/* Bit masks for KPAD_MSEL */
-
-#define DBON_SCALE 0xff /* Debounce Scale Value */
-#define COLDRV_SCALE 0xff00 /* Column Driver Scale Value */
-
-/* Bit masks for KPAD_ROWCOL */
-
-#define KPAD_ROW 0xff /* Rows Pressed */
-#define KPAD_COL 0xff00 /* Columns Pressed */
-
-/* Bit masks for KPAD_STAT */
-
-#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */
-#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */
-#define KPAD_PRESSED 0x8 /* Key press current status */
-
-/* Bit masks for KPAD_SOFTEVAL */
-
-#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */
-
-/* Bit masks for ATAPI_CONTROL */
-
-#define PIO_START 0x1 /* Start PIO/Reg Op */
-#define MULTI_START 0x2 /* Start Multi-DMA Op */
-#define ULTRA_START 0x4 /* Start Ultra-DMA Op */
-#define XFER_DIR 0x8 /* Transfer Direction */
-#define IORDY_EN 0x10 /* IORDY Enable */
-#define FIFO_FLUSH 0x20 /* Flush FIFOs */
-#define SOFT_RST 0x40 /* Soft Reset */
-#define DEV_RST 0x80 /* Device Reset */
-#define TFRCNT_RST 0x100 /* Trans Count Reset */
-#define END_ON_TERM 0x200 /* End/Terminate Select */
-#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */
-#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */
-
-/* Bit masks for ATAPI_STATUS */
-
-#define PIO_XFER_ON 0x1 /* PIO transfer in progress */
-#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */
-#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */
-#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */
-
-/* Bit masks for ATAPI_DEV_ADDR */
-
-#define DEV_ADDR 0x1f /* Device Address */
-
-/* Bit masks for ATAPI_INT_MASK */
-
-#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */
-#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */
-#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */
-#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */
-#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */
-#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */
-#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */
-#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */
-#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */
-
-/* Bit masks for ATAPI_INT_STATUS */
-
-#define ATAPI_DEV_INT 0x1 /* Device interrupt status */
-#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */
-#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */
-#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */
-#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */
-#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */
-#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */
-#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */
-#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */
-
-/* Bit masks for ATAPI_LINE_STATUS */
-
-#define ATAPI_INTR 0x1 /* Device interrupt to host line status */
-#define ATAPI_DASP 0x2 /* Device dasp to host line status */
-#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */
-#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */
-#define ATAPI_ADDR 0x70 /* ATAPI address line status */
-#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */
-#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */
-#define ATAPI_DIOWN 0x200 /* ATAPI write line status */
-#define ATAPI_DIORN 0x400 /* ATAPI read line status */
-#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */
-
-/* Bit masks for ATAPI_SM_STATE */
-
-#define PIO_CSTATE 0xf /* PIO mode state machine current state */
-#define DMA_CSTATE 0xf0 /* DMA mode state machine current state */
-#define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */
-#define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */
-
-/* Bit masks for ATAPI_TERMINATE */
-
-#define ATAPI_HOST_TERM 0x1 /* Host terminationation */
-
-/* Bit masks for ATAPI_REG_TIM_0 */
-
-#define T2_REG 0xff /* End of cycle time for register access transfers */
-#define TEOC_REG 0xff00 /* Selects DIOR/DIOW pulsewidth */
-
-/* Bit masks for ATAPI_PIO_TIM_0 */
-
-#define T1_REG 0xf /* Time from address valid to DIOR/DIOW */
-#define T2_REG_PIO 0xff0 /* DIOR/DIOW pulsewidth */
-#define T4_REG 0xf000 /* DIOW data hold */
-
-/* Bit masks for ATAPI_PIO_TIM_1 */
-
-#define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */
-
-/* Bit masks for ATAPI_MULTI_TIM_0 */
-
-#define TD 0xff /* DIOR/DIOW asserted pulsewidth */
-#define TM 0xff00 /* Time from address valid to DIOR/DIOW */
-
-/* Bit masks for ATAPI_MULTI_TIM_1 */
-
-#define TKW 0xff /* Selects DIOW negated pulsewidth */
-#define TKR 0xff00 /* Selects DIOR negated pulsewidth */
-
-/* Bit masks for ATAPI_MULTI_TIM_2 */
-
-#define TH 0xff /* Selects DIOW data hold */
-#define TEOC 0xff00 /* Selects end of cycle for DMA */
-
-/* Bit masks for ATAPI_ULTRA_TIM_0 */
-
-#define TACK 0xff /* Selects setup and hold times for TACK */
-#define TENV 0xff00 /* Selects envelope time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_1 */
-
-#define TDVS 0xff /* Selects data valid setup time */
-#define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_2 */
-
-#define TSS 0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */
-#define TMLI 0xff00 /* Selects interlock time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_3 */
-
-#define TZAH 0xff /* Selects minimum delay required for output */
-#define READY_PAUSE 0xff00 /* Selects ready to pause */
-
-/* Bit masks for TIMER_ENABLE1 */
-
-#define TIMEN8 0x1 /* Timer 8 Enable */
-#define TIMEN9 0x2 /* Timer 9 Enable */
-#define TIMEN10 0x4 /* Timer 10 Enable */
-
-/* Bit masks for TIMER_DISABLE1 */
-
-#define TIMDIS8 0x1 /* Timer 8 Disable */
-#define TIMDIS9 0x2 /* Timer 9 Disable */
-#define TIMDIS10 0x4 /* Timer 10 Disable */
-
-/* Bit masks for TIMER_STATUS1 */
-
-#define TIMIL8 0x1 /* Timer 8 Interrupt */
-#define TIMIL9 0x2 /* Timer 9 Interrupt */
-#define TIMIL10 0x4 /* Timer 10 Interrupt */
-#define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */
-#define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */
-#define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */
-#define TRUN8 0x1000 /* Timer 8 Slave Enable Status */
-#define TRUN9 0x2000 /* Timer 9 Slave Enable Status */
-#define TRUN10 0x4000 /* Timer 10 Slave Enable Status */
-
-/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
-
-/* Bit masks for USB_FADDR */
-
-#define FUNCTION_ADDRESS 0x7f /* Function address */
-
-/* Bit masks for USB_POWER */
-
-#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
-#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
-#define RESUME_MODE 0x4 /* DMA Mode */
-#define RESET 0x8 /* Reset indicator */
-#define HS_MODE 0x10 /* High Speed mode indicator */
-#define HS_ENABLE 0x20 /* high Speed Enable */
-#define SOFT_CONN 0x40 /* Soft connect */
-#define ISO_UPDATE 0x80 /* Isochronous update */
-
-/* Bit masks for USB_INTRTX */
-
-#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
-#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
-#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
-#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
-#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
-#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
-#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
-#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
-
-/* Bit masks for USB_INTRRX */
-
-#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
-#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
-#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
-#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
-#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
-#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
-#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
-
-/* Bit masks for USB_INTRTXE */
-
-#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
-#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
-#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
-#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
-#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
-#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
-#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
-#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
-
-/* Bit masks for USB_INTRRXE */
-
-#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
-#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
-#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
-#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
-#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
-#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
-#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
-
-/* Bit masks for USB_INTRUSB */
-
-#define SUSPEND_B 0x1 /* Suspend indicator */
-#define RESUME_B 0x2 /* Resume indicator */
-#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
-#define SOF_B 0x8 /* Start of frame */
-#define CONN_B 0x10 /* Connection indicator */
-#define DISCON_B 0x20 /* Disconnect indicator */
-#define SESSION_REQ_B 0x40 /* Session Request */
-#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
-
-/* Bit masks for USB_INTRUSBE */
-
-#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
-#define RESUME_BE 0x2 /* Resume indicator int enable */
-#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
-#define SOF_BE 0x8 /* Start of frame int enable */
-#define CONN_BE 0x10 /* Connection indicator int enable */
-#define DISCON_BE 0x20 /* Disconnect indicator int enable */
-#define SESSION_REQ_BE 0x40 /* Session Request int enable */
-#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
-
-/* Bit masks for USB_FRAME */
-
-#define FRAME_NUMBER 0x7ff /* Frame number */
-
-/* Bit masks for USB_INDEX */
-
-#define SELECTED_ENDPOINT 0xf /* selected endpoint */
-
-/* Bit masks for USB_GLOBAL_CTL */
-
-#define GLOBAL_ENA 0x1 /* enables USB module */
-#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
-#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
-#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
-#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
-#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
-#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
-#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
-#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
-#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
-#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
-#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
-#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
-#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
-#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
-
-/* Bit masks for USB_OTG_DEV_CTL */
-
-#define SESSION 0x1 /* session indicator */
-#define HOST_REQ 0x2 /* Host negotiation request */
-#define HOST_MODE 0x4 /* indicates USBDRC is a host */
-#define VBUS0 0x8 /* Vbus level indicator[0] */
-#define VBUS1 0x10 /* Vbus level indicator[1] */
-#define LSDEV 0x20 /* Low-speed indicator */
-#define FSDEV 0x40 /* Full or High-speed indicator */
-#define B_DEVICE 0x80 /* A' or 'B' device indicator */
-
-/* Bit masks for USB_OTG_VBUS_IRQ */
-
-#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
-#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
-#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
-#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
-#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
-#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
-
-/* Bit masks for USB_OTG_VBUS_MASK */
-
-#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
-#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
-#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
-#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
-#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
-#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
-
-/* Bit masks for USB_CSR0 */
-
-#define RXPKTRDY 0x1 /* data packet receive indicator */
-#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
-#define STALL_SENT 0x4 /* STALL handshake sent */
-#define DATAEND 0x8 /* Data end indicator */
-#define SETUPEND 0x10 /* Setup end */
-#define SENDSTALL 0x20 /* Send STALL handshake */
-#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
-#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
-#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
-#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
-#define SETUPPKT_H 0x8 /* send Setup token host mode */
-#define ERROR_H 0x10 /* timeout error indicator host mode */
-#define REQPKT_H 0x20 /* Request an IN transaction host mode */
-#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
-#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
-
-/* Bit masks for USB_COUNT0 */
-
-#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */
-
-/* Bit masks for USB_NAKLIMIT0 */
-
-#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */
-
-/* Bit masks for USB_TX_MAX_PACKET */
-
-#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */
-
-/* Bit masks for USB_RX_MAX_PACKET */
-
-#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */
-
-/* Bit masks for USB_TXCSR */
-
-#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
-#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
-#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
-#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
-#define STALL_SEND_T 0x10 /* issue a Stall handshake */
-#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
-#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
-#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
-#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
-#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
-#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
-#define ISO_T 0x4000 /* enable Isochronous transfers */
-#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
-#define ERROR_TH 0x4 /* error condition host mode */
-#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
-#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
-
-/* Bit masks for USB_TXCOUNT */
-
-#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* Bit masks for USB_RXCSR */
-
-#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
-#define FIFO_FULL_R 0x2 /* FIFO not empty */
-#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
-#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
-#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
-#define STALL_SEND_R 0x20 /* issue a Stall handshake */
-#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
-#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
-#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
-#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
-#define DISNYET_R 0x1000 /* disable Nyet handshakes */
-#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
-#define ISO_R 0x4000 /* enable Isochronous transfers */
-#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
-#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
-#define REQPKT_RH 0x20 /* request an IN transaction host mode */
-#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
-#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
-#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
-#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
-
-/* Bit masks for USB_RXCOUNT */
-
-#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */
-
-/* Bit masks for USB_TXTYPE */
-
-#define TARGET_EP_NO_T 0xf /* EP number */
-#define PROTOCOL_T 0xc /* transfer type */
-
-/* Bit masks for USB_TXINTERVAL */
-
-#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
-
-/* Bit masks for USB_RXTYPE */
-
-#define TARGET_EP_NO_R 0xf /* EP number */
-#define PROTOCOL_R 0xc /* transfer type */
-
-/* Bit masks for USB_RXINTERVAL */
-
-#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
-
-/* Bit masks for USB_DMA_INTERRUPT */
-
-#define DMA0_INT 0x1 /* DMA0 pending interrupt */
-#define DMA1_INT 0x2 /* DMA1 pending interrupt */
-#define DMA2_INT 0x4 /* DMA2 pending interrupt */
-#define DMA3_INT 0x8 /* DMA3 pending interrupt */
-#define DMA4_INT 0x10 /* DMA4 pending interrupt */
-#define DMA5_INT 0x20 /* DMA5 pending interrupt */
-#define DMA6_INT 0x40 /* DMA6 pending interrupt */
-#define DMA7_INT 0x80 /* DMA7 pending interrupt */
-
-/* Bit masks for USB_DMAxCONTROL */
-
-#define DMA_ENA 0x1 /* DMA enable */
-#define DIRECTION 0x2 /* direction of DMA transfer */
-#define MODE 0x4 /* DMA Bus error */
-#define INT_ENA 0x8 /* Interrupt enable */
-#define EPNUM 0xf0 /* EP number */
-#define BUSERROR 0x100 /* DMA Bus error */
-
-/* Bit masks for USB_DMAxADDRHIGH */
-
-#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxADDRLOW */
-
-#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTHIGH */
-
-#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTLOW */
-
-#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
-
-#endif /* _DEF_BF547_H */
+++ /dev/null
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF548_H
-#define _DEF_BF548_H
-
-/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
-#include "defBF54x_base.h"
-
-/* The BF548 is like the BF547, but has additional CANs */
-#include "defBF547.h"
-
-/* CAN Controller 1 Config 1 Registers */
-
-#define CAN1_MC1 0xffc03200 /* CAN Controller 1 Mailbox Configuration Register 1 */
-#define CAN1_MD1 0xffc03204 /* CAN Controller 1 Mailbox Direction Register 1 */
-#define CAN1_TRS1 0xffc03208 /* CAN Controller 1 Transmit Request Set Register 1 */
-#define CAN1_TRR1 0xffc0320c /* CAN Controller 1 Transmit Request Reset Register 1 */
-#define CAN1_TA1 0xffc03210 /* CAN Controller 1 Transmit Acknowledge Register 1 */
-#define CAN1_AA1 0xffc03214 /* CAN Controller 1 Abort Acknowledge Register 1 */
-#define CAN1_RMP1 0xffc03218 /* CAN Controller 1 Receive Message Pending Register 1 */
-#define CAN1_RML1 0xffc0321c /* CAN Controller 1 Receive Message Lost Register 1 */
-#define CAN1_MBTIF1 0xffc03220 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
-#define CAN1_MBRIF1 0xffc03224 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
-#define CAN1_MBIM1 0xffc03228 /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
-#define CAN1_RFH1 0xffc0322c /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
-#define CAN1_OPSS1 0xffc03230 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
-
-/* CAN Controller 1 Config 2 Registers */
-
-#define CAN1_MC2 0xffc03240 /* CAN Controller 1 Mailbox Configuration Register 2 */
-#define CAN1_MD2 0xffc03244 /* CAN Controller 1 Mailbox Direction Register 2 */
-#define CAN1_TRS2 0xffc03248 /* CAN Controller 1 Transmit Request Set Register 2 */
-#define CAN1_TRR2 0xffc0324c /* CAN Controller 1 Transmit Request Reset Register 2 */
-#define CAN1_TA2 0xffc03250 /* CAN Controller 1 Transmit Acknowledge Register 2 */
-#define CAN1_AA2 0xffc03254 /* CAN Controller 1 Abort Acknowledge Register 2 */
-#define CAN1_RMP2 0xffc03258 /* CAN Controller 1 Receive Message Pending Register 2 */
-#define CAN1_RML2 0xffc0325c /* CAN Controller 1 Receive Message Lost Register 2 */
-#define CAN1_MBTIF2 0xffc03260 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
-#define CAN1_MBRIF2 0xffc03264 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
-#define CAN1_MBIM2 0xffc03268 /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
-#define CAN1_RFH2 0xffc0326c /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
-#define CAN1_OPSS2 0xffc03270 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
-
-/* CAN Controller 1 Clock/Interrupt/Counter Registers */
-
-#define CAN1_CLOCK 0xffc03280 /* CAN Controller 1 Clock Register */
-#define CAN1_TIMING 0xffc03284 /* CAN Controller 1 Timing Register */
-#define CAN1_DEBUG 0xffc03288 /* CAN Controller 1 Debug Register */
-#define CAN1_STATUS 0xffc0328c /* CAN Controller 1 Global Status Register */
-#define CAN1_CEC 0xffc03290 /* CAN Controller 1 Error Counter Register */
-#define CAN1_GIS 0xffc03294 /* CAN Controller 1 Global Interrupt Status Register */
-#define CAN1_GIM 0xffc03298 /* CAN Controller 1 Global Interrupt Mask Register */
-#define CAN1_GIF 0xffc0329c /* CAN Controller 1 Global Interrupt Flag Register */
-#define CAN1_CONTROL 0xffc032a0 /* CAN Controller 1 Master Control Register */
-#define CAN1_INTR 0xffc032a4 /* CAN Controller 1 Interrupt Pending Register */
-#define CAN1_MBTD 0xffc032ac /* CAN Controller 1 Mailbox Temporary Disable Register */
-#define CAN1_EWR 0xffc032b0 /* CAN Controller 1 Programmable Warning Level Register */
-#define CAN1_ESR 0xffc032b4 /* CAN Controller 1 Error Status Register */
-#define CAN1_UCCNT 0xffc032c4 /* CAN Controller 1 Universal Counter Register */
-#define CAN1_UCRC 0xffc032c8 /* CAN Controller 1 Universal Counter Force Reload Register */
-#define CAN1_UCCNF 0xffc032cc /* CAN Controller 1 Universal Counter Configuration Register */
-
-/* CAN Controller 1 Mailbox Acceptance Registers */
-
-#define CAN1_AM00L 0xffc03300 /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
-#define CAN1_AM00H 0xffc03304 /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
-#define CAN1_AM01L 0xffc03308 /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
-#define CAN1_AM01H 0xffc0330c /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
-#define CAN1_AM02L 0xffc03310 /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
-#define CAN1_AM02H 0xffc03314 /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
-#define CAN1_AM03L 0xffc03318 /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
-#define CAN1_AM03H 0xffc0331c /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
-#define CAN1_AM04L 0xffc03320 /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
-#define CAN1_AM04H 0xffc03324 /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
-#define CAN1_AM05L 0xffc03328 /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
-#define CAN1_AM05H 0xffc0332c /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
-#define CAN1_AM06L 0xffc03330 /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
-#define CAN1_AM06H 0xffc03334 /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
-#define CAN1_AM07L 0xffc03338 /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
-#define CAN1_AM07H 0xffc0333c /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
-#define CAN1_AM08L 0xffc03340 /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
-#define CAN1_AM08H 0xffc03344 /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
-#define CAN1_AM09L 0xffc03348 /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
-#define CAN1_AM09H 0xffc0334c /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
-#define CAN1_AM10L 0xffc03350 /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
-#define CAN1_AM10H 0xffc03354 /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
-#define CAN1_AM11L 0xffc03358 /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
-#define CAN1_AM11H 0xffc0335c /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
-#define CAN1_AM12L 0xffc03360 /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
-#define CAN1_AM12H 0xffc03364 /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
-#define CAN1_AM13L 0xffc03368 /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
-#define CAN1_AM13H 0xffc0336c /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
-#define CAN1_AM14L 0xffc03370 /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
-#define CAN1_AM14H 0xffc03374 /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
-#define CAN1_AM15L 0xffc03378 /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
-#define CAN1_AM15H 0xffc0337c /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
-
-/* CAN Controller 1 Mailbox Acceptance Registers */
-
-#define CAN1_AM16L 0xffc03380 /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
-#define CAN1_AM16H 0xffc03384 /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
-#define CAN1_AM17L 0xffc03388 /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
-#define CAN1_AM17H 0xffc0338c /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
-#define CAN1_AM18L 0xffc03390 /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
-#define CAN1_AM18H 0xffc03394 /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
-#define CAN1_AM19L 0xffc03398 /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
-#define CAN1_AM19H 0xffc0339c /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
-#define CAN1_AM20L 0xffc033a0 /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
-#define CAN1_AM20H 0xffc033a4 /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
-#define CAN1_AM21L 0xffc033a8 /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
-#define CAN1_AM21H 0xffc033ac /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
-#define CAN1_AM22L 0xffc033b0 /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
-#define CAN1_AM22H 0xffc033b4 /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
-#define CAN1_AM23L 0xffc033b8 /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
-#define CAN1_AM23H 0xffc033bc /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
-#define CAN1_AM24L 0xffc033c0 /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
-#define CAN1_AM24H 0xffc033c4 /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
-#define CAN1_AM25L 0xffc033c8 /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
-#define CAN1_AM25H 0xffc033cc /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
-#define CAN1_AM26L 0xffc033d0 /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
-#define CAN1_AM26H 0xffc033d4 /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
-#define CAN1_AM27L 0xffc033d8 /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
-#define CAN1_AM27H 0xffc033dc /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
-#define CAN1_AM28L 0xffc033e0 /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
-#define CAN1_AM28H 0xffc033e4 /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
-#define CAN1_AM29L 0xffc033e8 /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
-#define CAN1_AM29H 0xffc033ec /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
-#define CAN1_AM30L 0xffc033f0 /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
-#define CAN1_AM30H 0xffc033f4 /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
-#define CAN1_AM31L 0xffc033f8 /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
-#define CAN1_AM31H 0xffc033fc /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define CAN1_MB00_DATA0 0xffc03400 /* CAN Controller 1 Mailbox 0 Data 0 Register */
-#define CAN1_MB00_DATA1 0xffc03404 /* CAN Controller 1 Mailbox 0 Data 1 Register */
-#define CAN1_MB00_DATA2 0xffc03408 /* CAN Controller 1 Mailbox 0 Data 2 Register */
-#define CAN1_MB00_DATA3 0xffc0340c /* CAN Controller 1 Mailbox 0 Data 3 Register */
-#define CAN1_MB00_LENGTH 0xffc03410 /* CAN Controller 1 Mailbox 0 Length Register */
-#define CAN1_MB00_TIMESTAMP 0xffc03414 /* CAN Controller 1 Mailbox 0 Timestamp Register */
-#define CAN1_MB00_ID0 0xffc03418 /* CAN Controller 1 Mailbox 0 ID0 Register */
-#define CAN1_MB00_ID1 0xffc0341c /* CAN Controller 1 Mailbox 0 ID1 Register */
-#define CAN1_MB01_DATA0 0xffc03420 /* CAN Controller 1 Mailbox 1 Data 0 Register */
-#define CAN1_MB01_DATA1 0xffc03424 /* CAN Controller 1 Mailbox 1 Data 1 Register */
-#define CAN1_MB01_DATA2 0xffc03428 /* CAN Controller 1 Mailbox 1 Data 2 Register */
-#define CAN1_MB01_DATA3 0xffc0342c /* CAN Controller 1 Mailbox 1 Data 3 Register */
-#define CAN1_MB01_LENGTH 0xffc03430 /* CAN Controller 1 Mailbox 1 Length Register */
-#define CAN1_MB01_TIMESTAMP 0xffc03434 /* CAN Controller 1 Mailbox 1 Timestamp Register */
-#define CAN1_MB01_ID0 0xffc03438 /* CAN Controller 1 Mailbox 1 ID0 Register */
-#define CAN1_MB01_ID1 0xffc0343c /* CAN Controller 1 Mailbox 1 ID1 Register */
-#define CAN1_MB02_DATA0 0xffc03440 /* CAN Controller 1 Mailbox 2 Data 0 Register */
-#define CAN1_MB02_DATA1 0xffc03444 /* CAN Controller 1 Mailbox 2 Data 1 Register */
-#define CAN1_MB02_DATA2 0xffc03448 /* CAN Controller 1 Mailbox 2 Data 2 Register */
-#define CAN1_MB02_DATA3 0xffc0344c /* CAN Controller 1 Mailbox 2 Data 3 Register */
-#define CAN1_MB02_LENGTH 0xffc03450 /* CAN Controller 1 Mailbox 2 Length Register */
-#define CAN1_MB02_TIMESTAMP 0xffc03454 /* CAN Controller 1 Mailbox 2 Timestamp Register */
-#define CAN1_MB02_ID0 0xffc03458 /* CAN Controller 1 Mailbox 2 ID0 Register */
-#define CAN1_MB02_ID1 0xffc0345c /* CAN Controller 1 Mailbox 2 ID1 Register */
-#define CAN1_MB03_DATA0 0xffc03460 /* CAN Controller 1 Mailbox 3 Data 0 Register */
-#define CAN1_MB03_DATA1 0xffc03464 /* CAN Controller 1 Mailbox 3 Data 1 Register */
-#define CAN1_MB03_DATA2 0xffc03468 /* CAN Controller 1 Mailbox 3 Data 2 Register */
-#define CAN1_MB03_DATA3 0xffc0346c /* CAN Controller 1 Mailbox 3 Data 3 Register */
-#define CAN1_MB03_LENGTH 0xffc03470 /* CAN Controller 1 Mailbox 3 Length Register */
-#define CAN1_MB03_TIMESTAMP 0xffc03474 /* CAN Controller 1 Mailbox 3 Timestamp Register */
-#define CAN1_MB03_ID0 0xffc03478 /* CAN Controller 1 Mailbox 3 ID0 Register */
-#define CAN1_MB03_ID1 0xffc0347c /* CAN Controller 1 Mailbox 3 ID1 Register */
-#define CAN1_MB04_DATA0 0xffc03480 /* CAN Controller 1 Mailbox 4 Data 0 Register */
-#define CAN1_MB04_DATA1 0xffc03484 /* CAN Controller 1 Mailbox 4 Data 1 Register */
-#define CAN1_MB04_DATA2 0xffc03488 /* CAN Controller 1 Mailbox 4 Data 2 Register */
-#define CAN1_MB04_DATA3 0xffc0348c /* CAN Controller 1 Mailbox 4 Data 3 Register */
-#define CAN1_MB04_LENGTH 0xffc03490 /* CAN Controller 1 Mailbox 4 Length Register */
-#define CAN1_MB04_TIMESTAMP 0xffc03494 /* CAN Controller 1 Mailbox 4 Timestamp Register */
-#define CAN1_MB04_ID0 0xffc03498 /* CAN Controller 1 Mailbox 4 ID0 Register */
-#define CAN1_MB04_ID1 0xffc0349c /* CAN Controller 1 Mailbox 4 ID1 Register */
-#define CAN1_MB05_DATA0 0xffc034a0 /* CAN Controller 1 Mailbox 5 Data 0 Register */
-#define CAN1_MB05_DATA1 0xffc034a4 /* CAN Controller 1 Mailbox 5 Data 1 Register */
-#define CAN1_MB05_DATA2 0xffc034a8 /* CAN Controller 1 Mailbox 5 Data 2 Register */
-#define CAN1_MB05_DATA3 0xffc034ac /* CAN Controller 1 Mailbox 5 Data 3 Register */
-#define CAN1_MB05_LENGTH 0xffc034b0 /* CAN Controller 1 Mailbox 5 Length Register */
-#define CAN1_MB05_TIMESTAMP 0xffc034b4 /* CAN Controller 1 Mailbox 5 Timestamp Register */
-#define CAN1_MB05_ID0 0xffc034b8 /* CAN Controller 1 Mailbox 5 ID0 Register */
-#define CAN1_MB05_ID1 0xffc034bc /* CAN Controller 1 Mailbox 5 ID1 Register */
-#define CAN1_MB06_DATA0 0xffc034c0 /* CAN Controller 1 Mailbox 6 Data 0 Register */
-#define CAN1_MB06_DATA1 0xffc034c4 /* CAN Controller 1 Mailbox 6 Data 1 Register */
-#define CAN1_MB06_DATA2 0xffc034c8 /* CAN Controller 1 Mailbox 6 Data 2 Register */
-#define CAN1_MB06_DATA3 0xffc034cc /* CAN Controller 1 Mailbox 6 Data 3 Register */
-#define CAN1_MB06_LENGTH 0xffc034d0 /* CAN Controller 1 Mailbox 6 Length Register */
-#define CAN1_MB06_TIMESTAMP 0xffc034d4 /* CAN Controller 1 Mailbox 6 Timestamp Register */
-#define CAN1_MB06_ID0 0xffc034d8 /* CAN Controller 1 Mailbox 6 ID0 Register */
-#define CAN1_MB06_ID1 0xffc034dc /* CAN Controller 1 Mailbox 6 ID1 Register */
-#define CAN1_MB07_DATA0 0xffc034e0 /* CAN Controller 1 Mailbox 7 Data 0 Register */
-#define CAN1_MB07_DATA1 0xffc034e4 /* CAN Controller 1 Mailbox 7 Data 1 Register */
-#define CAN1_MB07_DATA2 0xffc034e8 /* CAN Controller 1 Mailbox 7 Data 2 Register */
-#define CAN1_MB07_DATA3 0xffc034ec /* CAN Controller 1 Mailbox 7 Data 3 Register */
-#define CAN1_MB07_LENGTH 0xffc034f0 /* CAN Controller 1 Mailbox 7 Length Register */
-#define CAN1_MB07_TIMESTAMP 0xffc034f4 /* CAN Controller 1 Mailbox 7 Timestamp Register */
-#define CAN1_MB07_ID0 0xffc034f8 /* CAN Controller 1 Mailbox 7 ID0 Register */
-#define CAN1_MB07_ID1 0xffc034fc /* CAN Controller 1 Mailbox 7 ID1 Register */
-#define CAN1_MB08_DATA0 0xffc03500 /* CAN Controller 1 Mailbox 8 Data 0 Register */
-#define CAN1_MB08_DATA1 0xffc03504 /* CAN Controller 1 Mailbox 8 Data 1 Register */
-#define CAN1_MB08_DATA2 0xffc03508 /* CAN Controller 1 Mailbox 8 Data 2 Register */
-#define CAN1_MB08_DATA3 0xffc0350c /* CAN Controller 1 Mailbox 8 Data 3 Register */
-#define CAN1_MB08_LENGTH 0xffc03510 /* CAN Controller 1 Mailbox 8 Length Register */
-#define CAN1_MB08_TIMESTAMP 0xffc03514 /* CAN Controller 1 Mailbox 8 Timestamp Register */
-#define CAN1_MB08_ID0 0xffc03518 /* CAN Controller 1 Mailbox 8 ID0 Register */
-#define CAN1_MB08_ID1 0xffc0351c /* CAN Controller 1 Mailbox 8 ID1 Register */
-#define CAN1_MB09_DATA0 0xffc03520 /* CAN Controller 1 Mailbox 9 Data 0 Register */
-#define CAN1_MB09_DATA1 0xffc03524 /* CAN Controller 1 Mailbox 9 Data 1 Register */
-#define CAN1_MB09_DATA2 0xffc03528 /* CAN Controller 1 Mailbox 9 Data 2 Register */
-#define CAN1_MB09_DATA3 0xffc0352c /* CAN Controller 1 Mailbox 9 Data 3 Register */
-#define CAN1_MB09_LENGTH 0xffc03530 /* CAN Controller 1 Mailbox 9 Length Register */
-#define CAN1_MB09_TIMESTAMP 0xffc03534 /* CAN Controller 1 Mailbox 9 Timestamp Register */
-#define CAN1_MB09_ID0 0xffc03538 /* CAN Controller 1 Mailbox 9 ID0 Register */
-#define CAN1_MB09_ID1 0xffc0353c /* CAN Controller 1 Mailbox 9 ID1 Register */
-#define CAN1_MB10_DATA0 0xffc03540 /* CAN Controller 1 Mailbox 10 Data 0 Register */
-#define CAN1_MB10_DATA1 0xffc03544 /* CAN Controller 1 Mailbox 10 Data 1 Register */
-#define CAN1_MB10_DATA2 0xffc03548 /* CAN Controller 1 Mailbox 10 Data 2 Register */
-#define CAN1_MB10_DATA3 0xffc0354c /* CAN Controller 1 Mailbox 10 Data 3 Register */
-#define CAN1_MB10_LENGTH 0xffc03550 /* CAN Controller 1 Mailbox 10 Length Register */
-#define CAN1_MB10_TIMESTAMP 0xffc03554 /* CAN Controller 1 Mailbox 10 Timestamp Register */
-#define CAN1_MB10_ID0 0xffc03558 /* CAN Controller 1 Mailbox 10 ID0 Register */
-#define CAN1_MB10_ID1 0xffc0355c /* CAN Controller 1 Mailbox 10 ID1 Register */
-#define CAN1_MB11_DATA0 0xffc03560 /* CAN Controller 1 Mailbox 11 Data 0 Register */
-#define CAN1_MB11_DATA1 0xffc03564 /* CAN Controller 1 Mailbox 11 Data 1 Register */
-#define CAN1_MB11_DATA2 0xffc03568 /* CAN Controller 1 Mailbox 11 Data 2 Register */
-#define CAN1_MB11_DATA3 0xffc0356c /* CAN Controller 1 Mailbox 11 Data 3 Register */
-#define CAN1_MB11_LENGTH 0xffc03570 /* CAN Controller 1 Mailbox 11 Length Register */
-#define CAN1_MB11_TIMESTAMP 0xffc03574 /* CAN Controller 1 Mailbox 11 Timestamp Register */
-#define CAN1_MB11_ID0 0xffc03578 /* CAN Controller 1 Mailbox 11 ID0 Register */
-#define CAN1_MB11_ID1 0xffc0357c /* CAN Controller 1 Mailbox 11 ID1 Register */
-#define CAN1_MB12_DATA0 0xffc03580 /* CAN Controller 1 Mailbox 12 Data 0 Register */
-#define CAN1_MB12_DATA1 0xffc03584 /* CAN Controller 1 Mailbox 12 Data 1 Register */
-#define CAN1_MB12_DATA2 0xffc03588 /* CAN Controller 1 Mailbox 12 Data 2 Register */
-#define CAN1_MB12_DATA3 0xffc0358c /* CAN Controller 1 Mailbox 12 Data 3 Register */
-#define CAN1_MB12_LENGTH 0xffc03590 /* CAN Controller 1 Mailbox 12 Length Register */
-#define CAN1_MB12_TIMESTAMP 0xffc03594 /* CAN Controller 1 Mailbox 12 Timestamp Register */
-#define CAN1_MB12_ID0 0xffc03598 /* CAN Controller 1 Mailbox 12 ID0 Register */
-#define CAN1_MB12_ID1 0xffc0359c /* CAN Controller 1 Mailbox 12 ID1 Register */
-#define CAN1_MB13_DATA0 0xffc035a0 /* CAN Controller 1 Mailbox 13 Data 0 Register */
-#define CAN1_MB13_DATA1 0xffc035a4 /* CAN Controller 1 Mailbox 13 Data 1 Register */
-#define CAN1_MB13_DATA2 0xffc035a8 /* CAN Controller 1 Mailbox 13 Data 2 Register */
-#define CAN1_MB13_DATA3 0xffc035ac /* CAN Controller 1 Mailbox 13 Data 3 Register */
-#define CAN1_MB13_LENGTH 0xffc035b0 /* CAN Controller 1 Mailbox 13 Length Register */
-#define CAN1_MB13_TIMESTAMP 0xffc035b4 /* CAN Controller 1 Mailbox 13 Timestamp Register */
-#define CAN1_MB13_ID0 0xffc035b8 /* CAN Controller 1 Mailbox 13 ID0 Register */
-#define CAN1_MB13_ID1 0xffc035bc /* CAN Controller 1 Mailbox 13 ID1 Register */
-#define CAN1_MB14_DATA0 0xffc035c0 /* CAN Controller 1 Mailbox 14 Data 0 Register */
-#define CAN1_MB14_DATA1 0xffc035c4 /* CAN Controller 1 Mailbox 14 Data 1 Register */
-#define CAN1_MB14_DATA2 0xffc035c8 /* CAN Controller 1 Mailbox 14 Data 2 Register */
-#define CAN1_MB14_DATA3 0xffc035cc /* CAN Controller 1 Mailbox 14 Data 3 Register */
-#define CAN1_MB14_LENGTH 0xffc035d0 /* CAN Controller 1 Mailbox 14 Length Register */
-#define CAN1_MB14_TIMESTAMP 0xffc035d4 /* CAN Controller 1 Mailbox 14 Timestamp Register */
-#define CAN1_MB14_ID0 0xffc035d8 /* CAN Controller 1 Mailbox 14 ID0 Register */
-#define CAN1_MB14_ID1 0xffc035dc /* CAN Controller 1 Mailbox 14 ID1 Register */
-#define CAN1_MB15_DATA0 0xffc035e0 /* CAN Controller 1 Mailbox 15 Data 0 Register */
-#define CAN1_MB15_DATA1 0xffc035e4 /* CAN Controller 1 Mailbox 15 Data 1 Register */
-#define CAN1_MB15_DATA2 0xffc035e8 /* CAN Controller 1 Mailbox 15 Data 2 Register */
-#define CAN1_MB15_DATA3 0xffc035ec /* CAN Controller 1 Mailbox 15 Data 3 Register */
-#define CAN1_MB15_LENGTH 0xffc035f0 /* CAN Controller 1 Mailbox 15 Length Register */
-#define CAN1_MB15_TIMESTAMP 0xffc035f4 /* CAN Controller 1 Mailbox 15 Timestamp Register */
-#define CAN1_MB15_ID0 0xffc035f8 /* CAN Controller 1 Mailbox 15 ID0 Register */
-#define CAN1_MB15_ID1 0xffc035fc /* CAN Controller 1 Mailbox 15 ID1 Register */
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define CAN1_MB16_DATA0 0xffc03600 /* CAN Controller 1 Mailbox 16 Data 0 Register */
-#define CAN1_MB16_DATA1 0xffc03604 /* CAN Controller 1 Mailbox 16 Data 1 Register */
-#define CAN1_MB16_DATA2 0xffc03608 /* CAN Controller 1 Mailbox 16 Data 2 Register */
-#define CAN1_MB16_DATA3 0xffc0360c /* CAN Controller 1 Mailbox 16 Data 3 Register */
-#define CAN1_MB16_LENGTH 0xffc03610 /* CAN Controller 1 Mailbox 16 Length Register */
-#define CAN1_MB16_TIMESTAMP 0xffc03614 /* CAN Controller 1 Mailbox 16 Timestamp Register */
-#define CAN1_MB16_ID0 0xffc03618 /* CAN Controller 1 Mailbox 16 ID0 Register */
-#define CAN1_MB16_ID1 0xffc0361c /* CAN Controller 1 Mailbox 16 ID1 Register */
-#define CAN1_MB17_DATA0 0xffc03620 /* CAN Controller 1 Mailbox 17 Data 0 Register */
-#define CAN1_MB17_DATA1 0xffc03624 /* CAN Controller 1 Mailbox 17 Data 1 Register */
-#define CAN1_MB17_DATA2 0xffc03628 /* CAN Controller 1 Mailbox 17 Data 2 Register */
-#define CAN1_MB17_DATA3 0xffc0362c /* CAN Controller 1 Mailbox 17 Data 3 Register */
-#define CAN1_MB17_LENGTH 0xffc03630 /* CAN Controller 1 Mailbox 17 Length Register */
-#define CAN1_MB17_TIMESTAMP 0xffc03634 /* CAN Controller 1 Mailbox 17 Timestamp Register */
-#define CAN1_MB17_ID0 0xffc03638 /* CAN Controller 1 Mailbox 17 ID0 Register */
-#define CAN1_MB17_ID1 0xffc0363c /* CAN Controller 1 Mailbox 17 ID1 Register */
-#define CAN1_MB18_DATA0 0xffc03640 /* CAN Controller 1 Mailbox 18 Data 0 Register */
-#define CAN1_MB18_DATA1 0xffc03644 /* CAN Controller 1 Mailbox 18 Data 1 Register */
-#define CAN1_MB18_DATA2 0xffc03648 /* CAN Controller 1 Mailbox 18 Data 2 Register */
-#define CAN1_MB18_DATA3 0xffc0364c /* CAN Controller 1 Mailbox 18 Data 3 Register */
-#define CAN1_MB18_LENGTH 0xffc03650 /* CAN Controller 1 Mailbox 18 Length Register */
-#define CAN1_MB18_TIMESTAMP 0xffc03654 /* CAN Controller 1 Mailbox 18 Timestamp Register */
-#define CAN1_MB18_ID0 0xffc03658 /* CAN Controller 1 Mailbox 18 ID0 Register */
-#define CAN1_MB18_ID1 0xffc0365c /* CAN Controller 1 Mailbox 18 ID1 Register */
-#define CAN1_MB19_DATA0 0xffc03660 /* CAN Controller 1 Mailbox 19 Data 0 Register */
-#define CAN1_MB19_DATA1 0xffc03664 /* CAN Controller 1 Mailbox 19 Data 1 Register */
-#define CAN1_MB19_DATA2 0xffc03668 /* CAN Controller 1 Mailbox 19 Data 2 Register */
-#define CAN1_MB19_DATA3 0xffc0366c /* CAN Controller 1 Mailbox 19 Data 3 Register */
-#define CAN1_MB19_LENGTH 0xffc03670 /* CAN Controller 1 Mailbox 19 Length Register */
-#define CAN1_MB19_TIMESTAMP 0xffc03674 /* CAN Controller 1 Mailbox 19 Timestamp Register */
-#define CAN1_MB19_ID0 0xffc03678 /* CAN Controller 1 Mailbox 19 ID0 Register */
-#define CAN1_MB19_ID1 0xffc0367c /* CAN Controller 1 Mailbox 19 ID1 Register */
-#define CAN1_MB20_DATA0 0xffc03680 /* CAN Controller 1 Mailbox 20 Data 0 Register */
-#define CAN1_MB20_DATA1 0xffc03684 /* CAN Controller 1 Mailbox 20 Data 1 Register */
-#define CAN1_MB20_DATA2 0xffc03688 /* CAN Controller 1 Mailbox 20 Data 2 Register */
-#define CAN1_MB20_DATA3 0xffc0368c /* CAN Controller 1 Mailbox 20 Data 3 Register */
-#define CAN1_MB20_LENGTH 0xffc03690 /* CAN Controller 1 Mailbox 20 Length Register */
-#define CAN1_MB20_TIMESTAMP 0xffc03694 /* CAN Controller 1 Mailbox 20 Timestamp Register */
-#define CAN1_MB20_ID0 0xffc03698 /* CAN Controller 1 Mailbox 20 ID0 Register */
-#define CAN1_MB20_ID1 0xffc0369c /* CAN Controller 1 Mailbox 20 ID1 Register */
-#define CAN1_MB21_DATA0 0xffc036a0 /* CAN Controller 1 Mailbox 21 Data 0 Register */
-#define CAN1_MB21_DATA1 0xffc036a4 /* CAN Controller 1 Mailbox 21 Data 1 Register */
-#define CAN1_MB21_DATA2 0xffc036a8 /* CAN Controller 1 Mailbox 21 Data 2 Register */
-#define CAN1_MB21_DATA3 0xffc036ac /* CAN Controller 1 Mailbox 21 Data 3 Register */
-#define CAN1_MB21_LENGTH 0xffc036b0 /* CAN Controller 1 Mailbox 21 Length Register */
-#define CAN1_MB21_TIMESTAMP 0xffc036b4 /* CAN Controller 1 Mailbox 21 Timestamp Register */
-#define CAN1_MB21_ID0 0xffc036b8 /* CAN Controller 1 Mailbox 21 ID0 Register */
-#define CAN1_MB21_ID1 0xffc036bc /* CAN Controller 1 Mailbox 21 ID1 Register */
-#define CAN1_MB22_DATA0 0xffc036c0 /* CAN Controller 1 Mailbox 22 Data 0 Register */
-#define CAN1_MB22_DATA1 0xffc036c4 /* CAN Controller 1 Mailbox 22 Data 1 Register */
-#define CAN1_MB22_DATA2 0xffc036c8 /* CAN Controller 1 Mailbox 22 Data 2 Register */
-#define CAN1_MB22_DATA3 0xffc036cc /* CAN Controller 1 Mailbox 22 Data 3 Register */
-#define CAN1_MB22_LENGTH 0xffc036d0 /* CAN Controller 1 Mailbox 22 Length Register */
-#define CAN1_MB22_TIMESTAMP 0xffc036d4 /* CAN Controller 1 Mailbox 22 Timestamp Register */
-#define CAN1_MB22_ID0 0xffc036d8 /* CAN Controller 1 Mailbox 22 ID0 Register */
-#define CAN1_MB22_ID1 0xffc036dc /* CAN Controller 1 Mailbox 22 ID1 Register */
-#define CAN1_MB23_DATA0 0xffc036e0 /* CAN Controller 1 Mailbox 23 Data 0 Register */
-#define CAN1_MB23_DATA1 0xffc036e4 /* CAN Controller 1 Mailbox 23 Data 1 Register */
-#define CAN1_MB23_DATA2 0xffc036e8 /* CAN Controller 1 Mailbox 23 Data 2 Register */
-#define CAN1_MB23_DATA3 0xffc036ec /* CAN Controller 1 Mailbox 23 Data 3 Register */
-#define CAN1_MB23_LENGTH 0xffc036f0 /* CAN Controller 1 Mailbox 23 Length Register */
-#define CAN1_MB23_TIMESTAMP 0xffc036f4 /* CAN Controller 1 Mailbox 23 Timestamp Register */
-#define CAN1_MB23_ID0 0xffc036f8 /* CAN Controller 1 Mailbox 23 ID0 Register */
-#define CAN1_MB23_ID1 0xffc036fc /* CAN Controller 1 Mailbox 23 ID1 Register */
-#define CAN1_MB24_DATA0 0xffc03700 /* CAN Controller 1 Mailbox 24 Data 0 Register */
-#define CAN1_MB24_DATA1 0xffc03704 /* CAN Controller 1 Mailbox 24 Data 1 Register */
-#define CAN1_MB24_DATA2 0xffc03708 /* CAN Controller 1 Mailbox 24 Data 2 Register */
-#define CAN1_MB24_DATA3 0xffc0370c /* CAN Controller 1 Mailbox 24 Data 3 Register */
-#define CAN1_MB24_LENGTH 0xffc03710 /* CAN Controller 1 Mailbox 24 Length Register */
-#define CAN1_MB24_TIMESTAMP 0xffc03714 /* CAN Controller 1 Mailbox 24 Timestamp Register */
-#define CAN1_MB24_ID0 0xffc03718 /* CAN Controller 1 Mailbox 24 ID0 Register */
-#define CAN1_MB24_ID1 0xffc0371c /* CAN Controller 1 Mailbox 24 ID1 Register */
-#define CAN1_MB25_DATA0 0xffc03720 /* CAN Controller 1 Mailbox 25 Data 0 Register */
-#define CAN1_MB25_DATA1 0xffc03724 /* CAN Controller 1 Mailbox 25 Data 1 Register */
-#define CAN1_MB25_DATA2 0xffc03728 /* CAN Controller 1 Mailbox 25 Data 2 Register */
-#define CAN1_MB25_DATA3 0xffc0372c /* CAN Controller 1 Mailbox 25 Data 3 Register */
-#define CAN1_MB25_LENGTH 0xffc03730 /* CAN Controller 1 Mailbox 25 Length Register */
-#define CAN1_MB25_TIMESTAMP 0xffc03734 /* CAN Controller 1 Mailbox 25 Timestamp Register */
-#define CAN1_MB25_ID0 0xffc03738 /* CAN Controller 1 Mailbox 25 ID0 Register */
-#define CAN1_MB25_ID1 0xffc0373c /* CAN Controller 1 Mailbox 25 ID1 Register */
-#define CAN1_MB26_DATA0 0xffc03740 /* CAN Controller 1 Mailbox 26 Data 0 Register */
-#define CAN1_MB26_DATA1 0xffc03744 /* CAN Controller 1 Mailbox 26 Data 1 Register */
-#define CAN1_MB26_DATA2 0xffc03748 /* CAN Controller 1 Mailbox 26 Data 2 Register */
-#define CAN1_MB26_DATA3 0xffc0374c /* CAN Controller 1 Mailbox 26 Data 3 Register */
-#define CAN1_MB26_LENGTH 0xffc03750 /* CAN Controller 1 Mailbox 26 Length Register */
-#define CAN1_MB26_TIMESTAMP 0xffc03754 /* CAN Controller 1 Mailbox 26 Timestamp Register */
-#define CAN1_MB26_ID0 0xffc03758 /* CAN Controller 1 Mailbox 26 ID0 Register */
-#define CAN1_MB26_ID1 0xffc0375c /* CAN Controller 1 Mailbox 26 ID1 Register */
-#define CAN1_MB27_DATA0 0xffc03760 /* CAN Controller 1 Mailbox 27 Data 0 Register */
-#define CAN1_MB27_DATA1 0xffc03764 /* CAN Controller 1 Mailbox 27 Data 1 Register */
-#define CAN1_MB27_DATA2 0xffc03768 /* CAN Controller 1 Mailbox 27 Data 2 Register */
-#define CAN1_MB27_DATA3 0xffc0376c /* CAN Controller 1 Mailbox 27 Data 3 Register */
-#define CAN1_MB27_LENGTH 0xffc03770 /* CAN Controller 1 Mailbox 27 Length Register */
-#define CAN1_MB27_TIMESTAMP 0xffc03774 /* CAN Controller 1 Mailbox 27 Timestamp Register */
-#define CAN1_MB27_ID0 0xffc03778 /* CAN Controller 1 Mailbox 27 ID0 Register */
-#define CAN1_MB27_ID1 0xffc0377c /* CAN Controller 1 Mailbox 27 ID1 Register */
-#define CAN1_MB28_DATA0 0xffc03780 /* CAN Controller 1 Mailbox 28 Data 0 Register */
-#define CAN1_MB28_DATA1 0xffc03784 /* CAN Controller 1 Mailbox 28 Data 1 Register */
-#define CAN1_MB28_DATA2 0xffc03788 /* CAN Controller 1 Mailbox 28 Data 2 Register */
-#define CAN1_MB28_DATA3 0xffc0378c /* CAN Controller 1 Mailbox 28 Data 3 Register */
-#define CAN1_MB28_LENGTH 0xffc03790 /* CAN Controller 1 Mailbox 28 Length Register */
-#define CAN1_MB28_TIMESTAMP 0xffc03794 /* CAN Controller 1 Mailbox 28 Timestamp Register */
-#define CAN1_MB28_ID0 0xffc03798 /* CAN Controller 1 Mailbox 28 ID0 Register */
-#define CAN1_MB28_ID1 0xffc0379c /* CAN Controller 1 Mailbox 28 ID1 Register */
-#define CAN1_MB29_DATA0 0xffc037a0 /* CAN Controller 1 Mailbox 29 Data 0 Register */
-#define CAN1_MB29_DATA1 0xffc037a4 /* CAN Controller 1 Mailbox 29 Data 1 Register */
-#define CAN1_MB29_DATA2 0xffc037a8 /* CAN Controller 1 Mailbox 29 Data 2 Register */
-#define CAN1_MB29_DATA3 0xffc037ac /* CAN Controller 1 Mailbox 29 Data 3 Register */
-#define CAN1_MB29_LENGTH 0xffc037b0 /* CAN Controller 1 Mailbox 29 Length Register */
-#define CAN1_MB29_TIMESTAMP 0xffc037b4 /* CAN Controller 1 Mailbox 29 Timestamp Register */
-#define CAN1_MB29_ID0 0xffc037b8 /* CAN Controller 1 Mailbox 29 ID0 Register */
-#define CAN1_MB29_ID1 0xffc037bc /* CAN Controller 1 Mailbox 29 ID1 Register */
-#define CAN1_MB30_DATA0 0xffc037c0 /* CAN Controller 1 Mailbox 30 Data 0 Register */
-#define CAN1_MB30_DATA1 0xffc037c4 /* CAN Controller 1 Mailbox 30 Data 1 Register */
-#define CAN1_MB30_DATA2 0xffc037c8 /* CAN Controller 1 Mailbox 30 Data 2 Register */
-#define CAN1_MB30_DATA3 0xffc037cc /* CAN Controller 1 Mailbox 30 Data 3 Register */
-#define CAN1_MB30_LENGTH 0xffc037d0 /* CAN Controller 1 Mailbox 30 Length Register */
-#define CAN1_MB30_TIMESTAMP 0xffc037d4 /* CAN Controller 1 Mailbox 30 Timestamp Register */
-#define CAN1_MB30_ID0 0xffc037d8 /* CAN Controller 1 Mailbox 30 ID0 Register */
-#define CAN1_MB30_ID1 0xffc037dc /* CAN Controller 1 Mailbox 30 ID1 Register */
-#define CAN1_MB31_DATA0 0xffc037e0 /* CAN Controller 1 Mailbox 31 Data 0 Register */
-#define CAN1_MB31_DATA1 0xffc037e4 /* CAN Controller 1 Mailbox 31 Data 1 Register */
-#define CAN1_MB31_DATA2 0xffc037e8 /* CAN Controller 1 Mailbox 31 Data 2 Register */
-#define CAN1_MB31_DATA3 0xffc037ec /* CAN Controller 1 Mailbox 31 Data 3 Register */
-#define CAN1_MB31_LENGTH 0xffc037f0 /* CAN Controller 1 Mailbox 31 Length Register */
-#define CAN1_MB31_TIMESTAMP 0xffc037f4 /* CAN Controller 1 Mailbox 31 Timestamp Register */
-#define CAN1_MB31_ID0 0xffc037f8 /* CAN Controller 1 Mailbox 31 ID0 Register */
-#define CAN1_MB31_ID1 0xffc037fc /* CAN Controller 1 Mailbox 31 ID1 Register */
-
-#endif /* _DEF_BF548_H */
+++ /dev/null
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF549_H
-#define _DEF_BF549_H
-
-/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
-#include "defBF54x_base.h"
-
-/* The BF549 is like the BF544, but has MXVR */
-#include "defBF547.h"
-
-/* MXVR Registers */
-
-#define MXVR_CONFIG 0xffc02700 /* MXVR Configuration Register */
-#define MXVR_STATE_0 0xffc02708 /* MXVR State Register 0 */
-#define MXVR_STATE_1 0xffc0270c /* MXVR State Register 1 */
-#define MXVR_INT_STAT_0 0xffc02710 /* MXVR Interrupt Status Register 0 */
-#define MXVR_INT_STAT_1 0xffc02714 /* MXVR Interrupt Status Register 1 */
-#define MXVR_INT_EN_0 0xffc02718 /* MXVR Interrupt Enable Register 0 */
-#define MXVR_INT_EN_1 0xffc0271c /* MXVR Interrupt Enable Register 1 */
-#define MXVR_POSITION 0xffc02720 /* MXVR Node Position Register */
-#define MXVR_MAX_POSITION 0xffc02724 /* MXVR Maximum Node Position Register */
-#define MXVR_DELAY 0xffc02728 /* MXVR Node Frame Delay Register */
-#define MXVR_MAX_DELAY 0xffc0272c /* MXVR Maximum Node Frame Delay Register */
-#define MXVR_LADDR 0xffc02730 /* MXVR Logical Address Register */
-#define MXVR_GADDR 0xffc02734 /* MXVR Group Address Register */
-#define MXVR_AADDR 0xffc02738 /* MXVR Alternate Address Register */
-
-/* MXVR Allocation Table Registers */
-
-#define MXVR_ALLOC_0 0xffc0273c /* MXVR Allocation Table Register 0 */
-#define MXVR_ALLOC_1 0xffc02740 /* MXVR Allocation Table Register 1 */
-#define MXVR_ALLOC_2 0xffc02744 /* MXVR Allocation Table Register 2 */
-#define MXVR_ALLOC_3 0xffc02748 /* MXVR Allocation Table Register 3 */
-#define MXVR_ALLOC_4 0xffc0274c /* MXVR Allocation Table Register 4 */
-#define MXVR_ALLOC_5 0xffc02750 /* MXVR Allocation Table Register 5 */
-#define MXVR_ALLOC_6 0xffc02754 /* MXVR Allocation Table Register 6 */
-#define MXVR_ALLOC_7 0xffc02758 /* MXVR Allocation Table Register 7 */
-#define MXVR_ALLOC_8 0xffc0275c /* MXVR Allocation Table Register 8 */
-#define MXVR_ALLOC_9 0xffc02760 /* MXVR Allocation Table Register 9 */
-#define MXVR_ALLOC_10 0xffc02764 /* MXVR Allocation Table Register 10 */
-#define MXVR_ALLOC_11 0xffc02768 /* MXVR Allocation Table Register 11 */
-#define MXVR_ALLOC_12 0xffc0276c /* MXVR Allocation Table Register 12 */
-#define MXVR_ALLOC_13 0xffc02770 /* MXVR Allocation Table Register 13 */
-#define MXVR_ALLOC_14 0xffc02774 /* MXVR Allocation Table Register 14 */
-
-/* MXVR Channel Assign Registers */
-
-#define MXVR_SYNC_LCHAN_0 0xffc02778 /* MXVR Sync Data Logical Channel Assign Register 0 */
-#define MXVR_SYNC_LCHAN_1 0xffc0277c /* MXVR Sync Data Logical Channel Assign Register 1 */
-#define MXVR_SYNC_LCHAN_2 0xffc02780 /* MXVR Sync Data Logical Channel Assign Register 2 */
-#define MXVR_SYNC_LCHAN_3 0xffc02784 /* MXVR Sync Data Logical Channel Assign Register 3 */
-#define MXVR_SYNC_LCHAN_4 0xffc02788 /* MXVR Sync Data Logical Channel Assign Register 4 */
-#define MXVR_SYNC_LCHAN_5 0xffc0278c /* MXVR Sync Data Logical Channel Assign Register 5 */
-#define MXVR_SYNC_LCHAN_6 0xffc02790 /* MXVR Sync Data Logical Channel Assign Register 6 */
-#define MXVR_SYNC_LCHAN_7 0xffc02794 /* MXVR Sync Data Logical Channel Assign Register 7 */
-
-/* MXVR DMA0 Registers */
-
-#define MXVR_DMA0_CONFIG 0xffc02798 /* MXVR Sync Data DMA0 Config Register */
-#define MXVR_DMA0_START_ADDR 0xffc0279c /* MXVR Sync Data DMA0 Start Address */
-#define MXVR_DMA0_COUNT 0xffc027a0 /* MXVR Sync Data DMA0 Loop Count Register */
-#define MXVR_DMA0_CURR_ADDR 0xffc027a4 /* MXVR Sync Data DMA0 Current Address */
-#define MXVR_DMA0_CURR_COUNT 0xffc027a8 /* MXVR Sync Data DMA0 Current Loop Count */
-
-/* MXVR DMA1 Registers */
-
-#define MXVR_DMA1_CONFIG 0xffc027ac /* MXVR Sync Data DMA1 Config Register */
-#define MXVR_DMA1_START_ADDR 0xffc027b0 /* MXVR Sync Data DMA1 Start Address */
-#define MXVR_DMA1_COUNT 0xffc027b4 /* MXVR Sync Data DMA1 Loop Count Register */
-#define MXVR_DMA1_CURR_ADDR 0xffc027b8 /* MXVR Sync Data DMA1 Current Address */
-#define MXVR_DMA1_CURR_COUNT 0xffc027bc /* MXVR Sync Data DMA1 Current Loop Count */
-
-/* MXVR DMA2 Registers */
-
-#define MXVR_DMA2_CONFIG 0xffc027c0 /* MXVR Sync Data DMA2 Config Register */
-#define MXVR_DMA2_START_ADDR 0xffc027c4 /* MXVR Sync Data DMA2 Start Address */
-#define MXVR_DMA2_COUNT 0xffc027c8 /* MXVR Sync Data DMA2 Loop Count Register */
-#define MXVR_DMA2_CURR_ADDR 0xffc027cc /* MXVR Sync Data DMA2 Current Address */
-#define MXVR_DMA2_CURR_COUNT 0xffc027d0 /* MXVR Sync Data DMA2 Current Loop Count */
-
-/* MXVR DMA3 Registers */
-
-#define MXVR_DMA3_CONFIG 0xffc027d4 /* MXVR Sync Data DMA3 Config Register */
-#define MXVR_DMA3_START_ADDR 0xffc027d8 /* MXVR Sync Data DMA3 Start Address */
-#define MXVR_DMA3_COUNT 0xffc027dc /* MXVR Sync Data DMA3 Loop Count Register */
-#define MXVR_DMA3_CURR_ADDR 0xffc027e0 /* MXVR Sync Data DMA3 Current Address */
-#define MXVR_DMA3_CURR_COUNT 0xffc027e4 /* MXVR Sync Data DMA3 Current Loop Count */
-
-/* MXVR DMA4 Registers */
-
-#define MXVR_DMA4_CONFIG 0xffc027e8 /* MXVR Sync Data DMA4 Config Register */
-#define MXVR_DMA4_START_ADDR 0xffc027ec /* MXVR Sync Data DMA4 Start Address */
-#define MXVR_DMA4_COUNT 0xffc027f0 /* MXVR Sync Data DMA4 Loop Count Register */
-#define MXVR_DMA4_CURR_ADDR 0xffc027f4 /* MXVR Sync Data DMA4 Current Address */
-#define MXVR_DMA4_CURR_COUNT 0xffc027f8 /* MXVR Sync Data DMA4 Current Loop Count */
-
-/* MXVR DMA5 Registers */
-
-#define MXVR_DMA5_CONFIG 0xffc027fc /* MXVR Sync Data DMA5 Config Register */
-#define MXVR_DMA5_START_ADDR 0xffc02800 /* MXVR Sync Data DMA5 Start Address */
-#define MXVR_DMA5_COUNT 0xffc02804 /* MXVR Sync Data DMA5 Loop Count Register */
-#define MXVR_DMA5_CURR_ADDR 0xffc02808 /* MXVR Sync Data DMA5 Current Address */
-#define MXVR_DMA5_CURR_COUNT 0xffc0280c /* MXVR Sync Data DMA5 Current Loop Count */
-
-/* MXVR DMA6 Registers */
-
-#define MXVR_DMA6_CONFIG 0xffc02810 /* MXVR Sync Data DMA6 Config Register */
-#define MXVR_DMA6_START_ADDR 0xffc02814 /* MXVR Sync Data DMA6 Start Address */
-#define MXVR_DMA6_COUNT 0xffc02818 /* MXVR Sync Data DMA6 Loop Count Register */
-#define MXVR_DMA6_CURR_ADDR 0xffc0281c /* MXVR Sync Data DMA6 Current Address */
-#define MXVR_DMA6_CURR_COUNT 0xffc02820 /* MXVR Sync Data DMA6 Current Loop Count */
-
-/* MXVR DMA7 Registers */
-
-#define MXVR_DMA7_CONFIG 0xffc02824 /* MXVR Sync Data DMA7 Config Register */
-#define MXVR_DMA7_START_ADDR 0xffc02828 /* MXVR Sync Data DMA7 Start Address */
-#define MXVR_DMA7_COUNT 0xffc0282c /* MXVR Sync Data DMA7 Loop Count Register */
-#define MXVR_DMA7_CURR_ADDR 0xffc02830 /* MXVR Sync Data DMA7 Current Address */
-#define MXVR_DMA7_CURR_COUNT 0xffc02834 /* MXVR Sync Data DMA7 Current Loop Count */
-
-/* MXVR Asynch Packet Registers */
-
-#define MXVR_AP_CTL 0xffc02838 /* MXVR Async Packet Control Register */
-#define MXVR_APRB_START_ADDR 0xffc0283c /* MXVR Async Packet RX Buffer Start Addr Register */
-#define MXVR_APRB_CURR_ADDR 0xffc02840 /* MXVR Async Packet RX Buffer Current Addr Register */
-#define MXVR_APTB_START_ADDR 0xffc02844 /* MXVR Async Packet TX Buffer Start Addr Register */
-#define MXVR_APTB_CURR_ADDR 0xffc02848 /* MXVR Async Packet TX Buffer Current Addr Register */
-
-/* MXVR Control Message Registers */
-
-#define MXVR_CM_CTL 0xffc0284c /* MXVR Control Message Control Register */
-#define MXVR_CMRB_START_ADDR 0xffc02850 /* MXVR Control Message RX Buffer Start Addr Register */
-#define MXVR_CMRB_CURR_ADDR 0xffc02854 /* MXVR Control Message RX Buffer Current Address */
-#define MXVR_CMTB_START_ADDR 0xffc02858 /* MXVR Control Message TX Buffer Start Addr Register */
-#define MXVR_CMTB_CURR_ADDR 0xffc0285c /* MXVR Control Message TX Buffer Current Address */
-
-/* MXVR Remote Read Registers */
-
-#define MXVR_RRDB_START_ADDR 0xffc02860 /* MXVR Remote Read Buffer Start Addr Register */
-#define MXVR_RRDB_CURR_ADDR 0xffc02864 /* MXVR Remote Read Buffer Current Addr Register */
-
-/* MXVR Pattern Data Registers */
-
-#define MXVR_PAT_DATA_0 0xffc02868 /* MXVR Pattern Data Register 0 */
-#define MXVR_PAT_EN_0 0xffc0286c /* MXVR Pattern Enable Register 0 */
-#define MXVR_PAT_DATA_1 0xffc02870 /* MXVR Pattern Data Register 1 */
-#define MXVR_PAT_EN_1 0xffc02874 /* MXVR Pattern Enable Register 1 */
-
-/* MXVR Frame Counter Registers */
-
-#define MXVR_FRAME_CNT_0 0xffc02878 /* MXVR Frame Counter 0 */
-#define MXVR_FRAME_CNT_1 0xffc0287c /* MXVR Frame Counter 1 */
-
-/* MXVR Routing Table Registers */
-
-#define MXVR_ROUTING_0 0xffc02880 /* MXVR Routing Table Register 0 */
-#define MXVR_ROUTING_1 0xffc02884 /* MXVR Routing Table Register 1 */
-#define MXVR_ROUTING_2 0xffc02888 /* MXVR Routing Table Register 2 */
-#define MXVR_ROUTING_3 0xffc0288c /* MXVR Routing Table Register 3 */
-#define MXVR_ROUTING_4 0xffc02890 /* MXVR Routing Table Register 4 */
-#define MXVR_ROUTING_5 0xffc02894 /* MXVR Routing Table Register 5 */
-#define MXVR_ROUTING_6 0xffc02898 /* MXVR Routing Table Register 6 */
-#define MXVR_ROUTING_7 0xffc0289c /* MXVR Routing Table Register 7 */
-#define MXVR_ROUTING_8 0xffc028a0 /* MXVR Routing Table Register 8 */
-#define MXVR_ROUTING_9 0xffc028a4 /* MXVR Routing Table Register 9 */
-#define MXVR_ROUTING_10 0xffc028a8 /* MXVR Routing Table Register 10 */
-#define MXVR_ROUTING_11 0xffc028ac /* MXVR Routing Table Register 11 */
-#define MXVR_ROUTING_12 0xffc028b0 /* MXVR Routing Table Register 12 */
-#define MXVR_ROUTING_13 0xffc028b4 /* MXVR Routing Table Register 13 */
-#define MXVR_ROUTING_14 0xffc028b8 /* MXVR Routing Table Register 14 */
-
-/* MXVR Counter-Clock-Control Registers */
-
-#define MXVR_BLOCK_CNT 0xffc028c0 /* MXVR Block Counter */
-#define MXVR_CLK_CTL 0xffc028d0 /* MXVR Clock Control Register */
-#define MXVR_CDRPLL_CTL 0xffc028d4 /* MXVR Clock/Data Recovery PLL Control Register */
-#define MXVR_FMPLL_CTL 0xffc028d8 /* MXVR Frequency Multiply PLL Control Register */
-#define MXVR_PIN_CTL 0xffc028dc /* MXVR Pin Control Register */
-#define MXVR_SCLK_CNT 0xffc028e0 /* MXVR System Clock Counter Register */
-
-#endif /* _DEF_BF549_H */
+++ /dev/null
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF54X_H
-#define _DEF_BF54X_H
-
-
-/* ************************************************************** */
-/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x */
-/* ************************************************************** */
-
-/* PLL Registers */
-
-#define PLL_CTL 0xffc00000 /* PLL Control Register */
-#define PLL_DIV 0xffc00004 /* PLL Divisor Register */
-#define VR_CTL 0xffc00008 /* Voltage Regulator Control Register */
-#define PLL_STAT 0xffc0000c /* PLL Status Register */
-#define PLL_LOCKCNT 0xffc00010 /* PLL Lock Count Register */
-
-/* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */
-
-#define CHIPID 0xffc00014
-/* CHIPID Masks */
-#define CHIPID_VERSION 0xF0000000
-#define CHIPID_FAMILY 0x0FFFF000
-#define CHIPID_MANUFACTURE 0x00000FFE
-
-/* System Reset and Interrupt Controller (0xFFC00100 - 0xFFC00104) */
-
-#define SWRST 0xffc00100 /* Software Reset Register */
-#define SYSCR 0xffc00104 /* System Configuration register */
-
-/* SIC Registers */
-
-#define SIC_RVECT 0xffc00108
-#define SIC_IMASK0 0xffc0010c /* System Interrupt Mask Register 0 */
-#define SIC_IMASK1 0xffc00110 /* System Interrupt Mask Register 1 */
-#define SIC_IMASK2 0xffc00114 /* System Interrupt Mask Register 2 */
-#define SIC_ISR0 0xffc00118 /* System Interrupt Status Register 0 */
-#define SIC_ISR1 0xffc0011c /* System Interrupt Status Register 1 */
-#define SIC_ISR2 0xffc00120 /* System Interrupt Status Register 2 */
-#define SIC_IWR0 0xffc00124 /* System Interrupt Wakeup Register 0 */
-#define SIC_IWR1 0xffc00128 /* System Interrupt Wakeup Register 1 */
-#define SIC_IWR2 0xffc0012c /* System Interrupt Wakeup Register 2 */
-#define SIC_IAR0 0xffc00130 /* System Interrupt Assignment Register 0 */
-#define SIC_IAR1 0xffc00134 /* System Interrupt Assignment Register 1 */
-#define SIC_IAR2 0xffc00138 /* System Interrupt Assignment Register 2 */
-#define SIC_IAR3 0xffc0013c /* System Interrupt Assignment Register 3 */
-#define SIC_IAR4 0xffc00140 /* System Interrupt Assignment Register 4 */
-#define SIC_IAR5 0xffc00144 /* System Interrupt Assignment Register 5 */
-#define SIC_IAR6 0xffc00148 /* System Interrupt Assignment Register 6 */
-#define SIC_IAR7 0xffc0014c /* System Interrupt Assignment Register 7 */
-#define SIC_IAR8 0xffc00150 /* System Interrupt Assignment Register 8 */
-#define SIC_IAR9 0xffc00154 /* System Interrupt Assignment Register 9 */
-#define SIC_IAR10 0xffc00158 /* System Interrupt Assignment Register 10 */
-#define SIC_IAR11 0xffc0015c /* System Interrupt Assignment Register 11 */
-
-/* Watchdog Timer Registers */
-
-#define WDOG_CTL 0xffc00200 /* Watchdog Control Register */
-#define WDOG_CNT 0xffc00204 /* Watchdog Count Register */
-#define WDOG_STAT 0xffc00208 /* Watchdog Status Register */
-
-/* RTC Registers */
-
-#define RTC_STAT 0xffc00300 /* RTC Status Register */
-#define RTC_ICTL 0xffc00304 /* RTC Interrupt Control Register */
-#define RTC_ISTAT 0xffc00308 /* RTC Interrupt Status Register */
-#define RTC_SWCNT 0xffc0030c /* RTC Stopwatch Count Register */
-#define RTC_ALARM 0xffc00310 /* RTC Alarm Register */
-#define RTC_PREN 0xffc00314 /* RTC Prescaler Enable Register */
-
-/* UART0 Registers */
-
-#define UART0_DLL 0xffc00400 /* Divisor Latch Low Byte */
-#define UART0_DLH 0xffc00404 /* Divisor Latch High Byte */
-#define UART0_GCTL 0xffc00408 /* Global Control Register */
-#define UART0_LCR 0xffc0040c /* Line Control Register */
-#define UART0_MCR 0xffc00410 /* Modem Control Register */
-#define UART0_LSR 0xffc00414 /* Line Status Register */
-#define UART0_MSR 0xffc00418 /* Modem Status Register */
-#define UART0_SCR 0xffc0041c /* Scratch Register */
-#define UART0_IER_SET 0xffc00420 /* Interrupt Enable Register Set */
-#define UART0_IER_CLEAR 0xffc00424 /* Interrupt Enable Register Clear */
-#define UART0_THR 0xffc00428 /* Transmit Hold Register */
-#define UART0_RBR 0xffc0042c /* Receive Buffer Register */
-
-/* SPI0 Registers */
-
-#define SPI0_REGBASE 0xffc00500
-#define SPI0_CTL 0xffc00500 /* SPI0 Control Register */
-#define SPI0_FLG 0xffc00504 /* SPI0 Flag Register */
-#define SPI0_STAT 0xffc00508 /* SPI0 Status Register */
-#define SPI0_TDBR 0xffc0050c /* SPI0 Transmit Data Buffer Register */
-#define SPI0_RDBR 0xffc00510 /* SPI0 Receive Data Buffer Register */
-#define SPI0_BAUD 0xffc00514 /* SPI0 Baud Rate Register */
-#define SPI0_SHADOW 0xffc00518 /* SPI0 Receive Data Buffer Shadow Register */
-
-/* Timer Group of 3 registers are not defined in the shared file because they are not available on the ADSP-BF542 processor */
-
-/* Two Wire Interface Registers (TWI0) */
-
-#define TWI0_REGBASE 0xffc00700
-#define TWI0_CLKDIV 0xffc00700 /* Clock Divider Register */
-#define TWI0_CONTROL 0xffc00704 /* TWI Control Register */
-#define TWI0_SLAVE_CTL 0xffc00708 /* TWI Slave Mode Control Register */
-#define TWI0_SLAVE_STAT 0xffc0070c /* TWI Slave Mode Status Register */
-#define TWI0_SLAVE_ADDR 0xffc00710 /* TWI Slave Mode Address Register */
-#define TWI0_MASTER_CTL 0xffc00714 /* TWI Master Mode Control Register */
-#define TWI0_MASTER_STAT 0xffc00718 /* TWI Master Mode Status Register */
-#define TWI0_MASTER_ADDR 0xffc0071c /* TWI Master Mode Address Register */
-#define TWI0_INT_STAT 0xffc00720 /* TWI Interrupt Status Register */
-#define TWI0_INT_MASK 0xffc00724 /* TWI Interrupt Mask Register */
-#define TWI0_FIFO_CTL 0xffc00728 /* TWI FIFO Control Register */
-#define TWI0_FIFO_STAT 0xffc0072c /* TWI FIFO Status Register */
-#define TWI0_XMT_DATA8 0xffc00780 /* TWI FIFO Transmit Data Single Byte Register */
-#define TWI0_XMT_DATA16 0xffc00784 /* TWI FIFO Transmit Data Double Byte Register */
-#define TWI0_RCV_DATA8 0xffc00788 /* TWI FIFO Receive Data Single Byte Register */
-#define TWI0_RCV_DATA16 0xffc0078c /* TWI FIFO Receive Data Double Byte Register */
-
-/* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 processors */
-
-/* SPORT1 Registers */
-
-#define SPORT1_TCR1 0xffc00900 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_TCR2 0xffc00904 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_TCLKDIV 0xffc00908 /* SPORT1 Transmit Serial Clock Divider Register */
-#define SPORT1_TFSDIV 0xffc0090c /* SPORT1 Transmit Frame Sync Divider Register */
-#define SPORT1_TX 0xffc00910 /* SPORT1 Transmit Data Register */
-#define SPORT1_RX 0xffc00918 /* SPORT1 Receive Data Register */
-#define SPORT1_RCR1 0xffc00920 /* SPORT1 Receive Configuration 1 Register */
-#define SPORT1_RCR2 0xffc00924 /* SPORT1 Receive Configuration 2 Register */
-#define SPORT1_RCLKDIV 0xffc00928 /* SPORT1 Receive Serial Clock Divider Register */
-#define SPORT1_RFSDIV 0xffc0092c /* SPORT1 Receive Frame Sync Divider Register */
-#define SPORT1_STAT 0xffc00930 /* SPORT1 Status Register */
-#define SPORT1_CHNL 0xffc00934 /* SPORT1 Current Channel Register */
-#define SPORT1_MCMC1 0xffc00938 /* SPORT1 Multi channel Configuration Register 1 */
-#define SPORT1_MCMC2 0xffc0093c /* SPORT1 Multi channel Configuration Register 2 */
-#define SPORT1_MTCS0 0xffc00940 /* SPORT1 Multi channel Transmit Select Register 0 */
-#define SPORT1_MTCS1 0xffc00944 /* SPORT1 Multi channel Transmit Select Register 1 */
-#define SPORT1_MTCS2 0xffc00948 /* SPORT1 Multi channel Transmit Select Register 2 */
-#define SPORT1_MTCS3 0xffc0094c /* SPORT1 Multi channel Transmit Select Register 3 */
-#define SPORT1_MRCS0 0xffc00950 /* SPORT1 Multi channel Receive Select Register 0 */
-#define SPORT1_MRCS1 0xffc00954 /* SPORT1 Multi channel Receive Select Register 1 */
-#define SPORT1_MRCS2 0xffc00958 /* SPORT1 Multi channel Receive Select Register 2 */
-#define SPORT1_MRCS3 0xffc0095c /* SPORT1 Multi channel Receive Select Register 3 */
-
-/* Asynchronous Memory Control Registers */
-
-#define EBIU_AMGCTL 0xffc00a00 /* Asynchronous Memory Global Control Register */
-#define EBIU_AMBCTL0 0xffc00a04 /* Asynchronous Memory Bank Control Register */
-#define EBIU_AMBCTL1 0xffc00a08 /* Asynchronous Memory Bank Control Register */
-#define EBIU_MBSCTL 0xffc00a0c /* Asynchronous Memory Bank Select Control Register */
-#define EBIU_ARBSTAT 0xffc00a10 /* Asynchronous Memory Arbiter Status Register */
-#define EBIU_MODE 0xffc00a14 /* Asynchronous Mode Control Register */
-#define EBIU_FCTL 0xffc00a18 /* Asynchronous Memory Flash Control Register */
-
-/* DDR Memory Control Registers */
-
-#define EBIU_DDRCTL0 0xffc00a20 /* DDR Memory Control 0 Register */
-#define EBIU_DDRCTL1 0xffc00a24 /* DDR Memory Control 1 Register */
-#define EBIU_DDRCTL2 0xffc00a28 /* DDR Memory Control 2 Register */
-#define EBIU_DDRCTL3 0xffc00a2c /* DDR Memory Control 3 Register */
-#define EBIU_DDRQUE 0xffc00a30 /* DDR Queue Configuration Register */
-#define EBIU_ERRADD 0xffc00a34 /* DDR Error Address Register */
-#define EBIU_ERRMST 0xffc00a38 /* DDR Error Master Register */
-#define EBIU_RSTCTL 0xffc00a3c /* DDR Reset Control Register */
-
-/* DDR BankRead and Write Count Registers */
-
-#define EBIU_DDRBRC0 0xffc00a60 /* DDR Bank0 Read Count Register */
-#define EBIU_DDRBRC1 0xffc00a64 /* DDR Bank1 Read Count Register */
-#define EBIU_DDRBRC2 0xffc00a68 /* DDR Bank2 Read Count Register */
-#define EBIU_DDRBRC3 0xffc00a6c /* DDR Bank3 Read Count Register */
-#define EBIU_DDRBRC4 0xffc00a70 /* DDR Bank4 Read Count Register */
-#define EBIU_DDRBRC5 0xffc00a74 /* DDR Bank5 Read Count Register */
-#define EBIU_DDRBRC6 0xffc00a78 /* DDR Bank6 Read Count Register */
-#define EBIU_DDRBRC7 0xffc00a7c /* DDR Bank7 Read Count Register */
-#define EBIU_DDRBWC0 0xffc00a80 /* DDR Bank0 Write Count Register */
-#define EBIU_DDRBWC1 0xffc00a84 /* DDR Bank1 Write Count Register */
-#define EBIU_DDRBWC2 0xffc00a88 /* DDR Bank2 Write Count Register */
-#define EBIU_DDRBWC3 0xffc00a8c /* DDR Bank3 Write Count Register */
-#define EBIU_DDRBWC4 0xffc00a90 /* DDR Bank4 Write Count Register */
-#define EBIU_DDRBWC5 0xffc00a94 /* DDR Bank5 Write Count Register */
-#define EBIU_DDRBWC6 0xffc00a98 /* DDR Bank6 Write Count Register */
-#define EBIU_DDRBWC7 0xffc00a9c /* DDR Bank7 Write Count Register */
-#define EBIU_DDRACCT 0xffc00aa0 /* DDR Activation Count Register */
-#define EBIU_DDRTACT 0xffc00aa8 /* DDR Turn Around Count Register */
-#define EBIU_DDRARCT 0xffc00aac /* DDR Auto-refresh Count Register */
-#define EBIU_DDRGC0 0xffc00ab0 /* DDR Grant Count 0 Register */
-#define EBIU_DDRGC1 0xffc00ab4 /* DDR Grant Count 1 Register */
-#define EBIU_DDRGC2 0xffc00ab8 /* DDR Grant Count 2 Register */
-#define EBIU_DDRGC3 0xffc00abc /* DDR Grant Count 3 Register */
-#define EBIU_DDRMCEN 0xffc00ac0 /* DDR Metrics Counter Enable Register */
-#define EBIU_DDRMCCL 0xffc00ac4 /* DDR Metrics Counter Clear Register */
-
-/* DMAC0 Registers */
-
-#define DMAC0_TC_PER 0xffc00b0c /* DMA Controller 0 Traffic Control Periods Register */
-#define DMAC0_TC_CNT 0xffc00b10 /* DMA Controller 0 Current Counts Register */
-
-/* DMA Channel 0 Registers */
-
-#define DMA0_NEXT_DESC_PTR 0xffc00c00 /* DMA Channel 0 Next Descriptor Pointer Register */
-#define DMA0_START_ADDR 0xffc00c04 /* DMA Channel 0 Start Address Register */
-#define DMA0_CONFIG 0xffc00c08 /* DMA Channel 0 Configuration Register */
-#define DMA0_X_COUNT 0xffc00c10 /* DMA Channel 0 X Count Register */
-#define DMA0_X_MODIFY 0xffc00c14 /* DMA Channel 0 X Modify Register */
-#define DMA0_Y_COUNT 0xffc00c18 /* DMA Channel 0 Y Count Register */
-#define DMA0_Y_MODIFY 0xffc00c1c /* DMA Channel 0 Y Modify Register */
-#define DMA0_CURR_DESC_PTR 0xffc00c20 /* DMA Channel 0 Current Descriptor Pointer Register */
-#define DMA0_CURR_ADDR 0xffc00c24 /* DMA Channel 0 Current Address Register */
-#define DMA0_IRQ_STATUS 0xffc00c28 /* DMA Channel 0 Interrupt/Status Register */
-#define DMA0_PERIPHERAL_MAP 0xffc00c2c /* DMA Channel 0 Peripheral Map Register */
-#define DMA0_CURR_X_COUNT 0xffc00c30 /* DMA Channel 0 Current X Count Register */
-#define DMA0_CURR_Y_COUNT 0xffc00c38 /* DMA Channel 0 Current Y Count Register */
-
-/* DMA Channel 1 Registers */
-
-#define DMA1_NEXT_DESC_PTR 0xffc00c40 /* DMA Channel 1 Next Descriptor Pointer Register */
-#define DMA1_START_ADDR 0xffc00c44 /* DMA Channel 1 Start Address Register */
-#define DMA1_CONFIG 0xffc00c48 /* DMA Channel 1 Configuration Register */
-#define DMA1_X_COUNT 0xffc00c50 /* DMA Channel 1 X Count Register */
-#define DMA1_X_MODIFY 0xffc00c54 /* DMA Channel 1 X Modify Register */
-#define DMA1_Y_COUNT 0xffc00c58 /* DMA Channel 1 Y Count Register */
-#define DMA1_Y_MODIFY 0xffc00c5c /* DMA Channel 1 Y Modify Register */
-#define DMA1_CURR_DESC_PTR 0xffc00c60 /* DMA Channel 1 Current Descriptor Pointer Register */
-#define DMA1_CURR_ADDR 0xffc00c64 /* DMA Channel 1 Current Address Register */
-#define DMA1_IRQ_STATUS 0xffc00c68 /* DMA Channel 1 Interrupt/Status Register */
-#define DMA1_PERIPHERAL_MAP 0xffc00c6c /* DMA Channel 1 Peripheral Map Register */
-#define DMA1_CURR_X_COUNT 0xffc00c70 /* DMA Channel 1 Current X Count Register */
-#define DMA1_CURR_Y_COUNT 0xffc00c78 /* DMA Channel 1 Current Y Count Register */
-
-/* DMA Channel 2 Registers */
-
-#define DMA2_NEXT_DESC_PTR 0xffc00c80 /* DMA Channel 2 Next Descriptor Pointer Register */
-#define DMA2_START_ADDR 0xffc00c84 /* DMA Channel 2 Start Address Register */
-#define DMA2_CONFIG 0xffc00c88 /* DMA Channel 2 Configuration Register */
-#define DMA2_X_COUNT 0xffc00c90 /* DMA Channel 2 X Count Register */
-#define DMA2_X_MODIFY 0xffc00c94 /* DMA Channel 2 X Modify Register */
-#define DMA2_Y_COUNT 0xffc00c98 /* DMA Channel 2 Y Count Register */
-#define DMA2_Y_MODIFY 0xffc00c9c /* DMA Channel 2 Y Modify Register */
-#define DMA2_CURR_DESC_PTR 0xffc00ca0 /* DMA Channel 2 Current Descriptor Pointer Register */
-#define DMA2_CURR_ADDR 0xffc00ca4 /* DMA Channel 2 Current Address Register */
-#define DMA2_IRQ_STATUS 0xffc00ca8 /* DMA Channel 2 Interrupt/Status Register */
-#define DMA2_PERIPHERAL_MAP 0xffc00cac /* DMA Channel 2 Peripheral Map Register */
-#define DMA2_CURR_X_COUNT 0xffc00cb0 /* DMA Channel 2 Current X Count Register */
-#define DMA2_CURR_Y_COUNT 0xffc00cb8 /* DMA Channel 2 Current Y Count Register */
-
-/* DMA Channel 3 Registers */
-
-#define DMA3_NEXT_DESC_PTR 0xffc00cc0 /* DMA Channel 3 Next Descriptor Pointer Register */
-#define DMA3_START_ADDR 0xffc00cc4 /* DMA Channel 3 Start Address Register */
-#define DMA3_CONFIG 0xffc00cc8 /* DMA Channel 3 Configuration Register */
-#define DMA3_X_COUNT 0xffc00cd0 /* DMA Channel 3 X Count Register */
-#define DMA3_X_MODIFY 0xffc00cd4 /* DMA Channel 3 X Modify Register */
-#define DMA3_Y_COUNT 0xffc00cd8 /* DMA Channel 3 Y Count Register */
-#define DMA3_Y_MODIFY 0xffc00cdc /* DMA Channel 3 Y Modify Register */
-#define DMA3_CURR_DESC_PTR 0xffc00ce0 /* DMA Channel 3 Current Descriptor Pointer Register */
-#define DMA3_CURR_ADDR 0xffc00ce4 /* DMA Channel 3 Current Address Register */
-#define DMA3_IRQ_STATUS 0xffc00ce8 /* DMA Channel 3 Interrupt/Status Register */
-#define DMA3_PERIPHERAL_MAP 0xffc00cec /* DMA Channel 3 Peripheral Map Register */
-#define DMA3_CURR_X_COUNT 0xffc00cf0 /* DMA Channel 3 Current X Count Register */
-#define DMA3_CURR_Y_COUNT 0xffc00cf8 /* DMA Channel 3 Current Y Count Register */
-
-/* DMA Channel 4 Registers */
-
-#define DMA4_NEXT_DESC_PTR 0xffc00d00 /* DMA Channel 4 Next Descriptor Pointer Register */
-#define DMA4_START_ADDR 0xffc00d04 /* DMA Channel 4 Start Address Register */
-#define DMA4_CONFIG 0xffc00d08 /* DMA Channel 4 Configuration Register */
-#define DMA4_X_COUNT 0xffc00d10 /* DMA Channel 4 X Count Register */
-#define DMA4_X_MODIFY 0xffc00d14 /* DMA Channel 4 X Modify Register */
-#define DMA4_Y_COUNT 0xffc00d18 /* DMA Channel 4 Y Count Register */
-#define DMA4_Y_MODIFY 0xffc00d1c /* DMA Channel 4 Y Modify Register */
-#define DMA4_CURR_DESC_PTR 0xffc00d20 /* DMA Channel 4 Current Descriptor Pointer Register */
-#define DMA4_CURR_ADDR 0xffc00d24 /* DMA Channel 4 Current Address Register */
-#define DMA4_IRQ_STATUS 0xffc00d28 /* DMA Channel 4 Interrupt/Status Register */
-#define DMA4_PERIPHERAL_MAP 0xffc00d2c /* DMA Channel 4 Peripheral Map Register */
-#define DMA4_CURR_X_COUNT 0xffc00d30 /* DMA Channel 4 Current X Count Register */
-#define DMA4_CURR_Y_COUNT 0xffc00d38 /* DMA Channel 4 Current Y Count Register */
-
-/* DMA Channel 5 Registers */
-
-#define DMA5_NEXT_DESC_PTR 0xffc00d40 /* DMA Channel 5 Next Descriptor Pointer Register */
-#define DMA5_START_ADDR 0xffc00d44 /* DMA Channel 5 Start Address Register */
-#define DMA5_CONFIG 0xffc00d48 /* DMA Channel 5 Configuration Register */
-#define DMA5_X_COUNT 0xffc00d50 /* DMA Channel 5 X Count Register */
-#define DMA5_X_MODIFY 0xffc00d54 /* DMA Channel 5 X Modify Register */
-#define DMA5_Y_COUNT 0xffc00d58 /* DMA Channel 5 Y Count Register */
-#define DMA5_Y_MODIFY 0xffc00d5c /* DMA Channel 5 Y Modify Register */
-#define DMA5_CURR_DESC_PTR 0xffc00d60 /* DMA Channel 5 Current Descriptor Pointer Register */
-#define DMA5_CURR_ADDR 0xffc00d64 /* DMA Channel 5 Current Address Register */
-#define DMA5_IRQ_STATUS 0xffc00d68 /* DMA Channel 5 Interrupt/Status Register */
-#define DMA5_PERIPHERAL_MAP 0xffc00d6c /* DMA Channel 5 Peripheral Map Register */
-#define DMA5_CURR_X_COUNT 0xffc00d70 /* DMA Channel 5 Current X Count Register */
-#define DMA5_CURR_Y_COUNT 0xffc00d78 /* DMA Channel 5 Current Y Count Register */
-
-/* DMA Channel 6 Registers */
-
-#define DMA6_NEXT_DESC_PTR 0xffc00d80 /* DMA Channel 6 Next Descriptor Pointer Register */
-#define DMA6_START_ADDR 0xffc00d84 /* DMA Channel 6 Start Address Register */
-#define DMA6_CONFIG 0xffc00d88 /* DMA Channel 6 Configuration Register */
-#define DMA6_X_COUNT 0xffc00d90 /* DMA Channel 6 X Count Register */
-#define DMA6_X_MODIFY 0xffc00d94 /* DMA Channel 6 X Modify Register */
-#define DMA6_Y_COUNT 0xffc00d98 /* DMA Channel 6 Y Count Register */
-#define DMA6_Y_MODIFY 0xffc00d9c /* DMA Channel 6 Y Modify Register */
-#define DMA6_CURR_DESC_PTR 0xffc00da0 /* DMA Channel 6 Current Descriptor Pointer Register */
-#define DMA6_CURR_ADDR 0xffc00da4 /* DMA Channel 6 Current Address Register */
-#define DMA6_IRQ_STATUS 0xffc00da8 /* DMA Channel 6 Interrupt/Status Register */
-#define DMA6_PERIPHERAL_MAP 0xffc00dac /* DMA Channel 6 Peripheral Map Register */
-#define DMA6_CURR_X_COUNT 0xffc00db0 /* DMA Channel 6 Current X Count Register */
-#define DMA6_CURR_Y_COUNT 0xffc00db8 /* DMA Channel 6 Current Y Count Register */
-
-/* DMA Channel 7 Registers */
-
-#define DMA7_NEXT_DESC_PTR 0xffc00dc0 /* DMA Channel 7 Next Descriptor Pointer Register */
-#define DMA7_START_ADDR 0xffc00dc4 /* DMA Channel 7 Start Address Register */
-#define DMA7_CONFIG 0xffc00dc8 /* DMA Channel 7 Configuration Register */
-#define DMA7_X_COUNT 0xffc00dd0 /* DMA Channel 7 X Count Register */
-#define DMA7_X_MODIFY 0xffc00dd4 /* DMA Channel 7 X Modify Register */
-#define DMA7_Y_COUNT 0xffc00dd8 /* DMA Channel 7 Y Count Register */
-#define DMA7_Y_MODIFY 0xffc00ddc /* DMA Channel 7 Y Modify Register */
-#define DMA7_CURR_DESC_PTR 0xffc00de0 /* DMA Channel 7 Current Descriptor Pointer Register */
-#define DMA7_CURR_ADDR 0xffc00de4 /* DMA Channel 7 Current Address Register */
-#define DMA7_IRQ_STATUS 0xffc00de8 /* DMA Channel 7 Interrupt/Status Register */
-#define DMA7_PERIPHERAL_MAP 0xffc00dec /* DMA Channel 7 Peripheral Map Register */
-#define DMA7_CURR_X_COUNT 0xffc00df0 /* DMA Channel 7 Current X Count Register */
-#define DMA7_CURR_Y_COUNT 0xffc00df8 /* DMA Channel 7 Current Y Count Register */
-
-/* DMA Channel 8 Registers */
-
-#define DMA8_NEXT_DESC_PTR 0xffc00e00 /* DMA Channel 8 Next Descriptor Pointer Register */
-#define DMA8_START_ADDR 0xffc00e04 /* DMA Channel 8 Start Address Register */
-#define DMA8_CONFIG 0xffc00e08 /* DMA Channel 8 Configuration Register */
-#define DMA8_X_COUNT 0xffc00e10 /* DMA Channel 8 X Count Register */
-#define DMA8_X_MODIFY 0xffc00e14 /* DMA Channel 8 X Modify Register */
-#define DMA8_Y_COUNT 0xffc00e18 /* DMA Channel 8 Y Count Register */
-#define DMA8_Y_MODIFY 0xffc00e1c /* DMA Channel 8 Y Modify Register */
-#define DMA8_CURR_DESC_PTR 0xffc00e20 /* DMA Channel 8 Current Descriptor Pointer Register */
-#define DMA8_CURR_ADDR 0xffc00e24 /* DMA Channel 8 Current Address Register */
-#define DMA8_IRQ_STATUS 0xffc00e28 /* DMA Channel 8 Interrupt/Status Register */
-#define DMA8_PERIPHERAL_MAP 0xffc00e2c /* DMA Channel 8 Peripheral Map Register */
-#define DMA8_CURR_X_COUNT 0xffc00e30 /* DMA Channel 8 Current X Count Register */
-#define DMA8_CURR_Y_COUNT 0xffc00e38 /* DMA Channel 8 Current Y Count Register */
-
-/* DMA Channel 9 Registers */
-
-#define DMA9_NEXT_DESC_PTR 0xffc00e40 /* DMA Channel 9 Next Descriptor Pointer Register */
-#define DMA9_START_ADDR 0xffc00e44 /* DMA Channel 9 Start Address Register */
-#define DMA9_CONFIG 0xffc00e48 /* DMA Channel 9 Configuration Register */
-#define DMA9_X_COUNT 0xffc00e50 /* DMA Channel 9 X Count Register */
-#define DMA9_X_MODIFY 0xffc00e54 /* DMA Channel 9 X Modify Register */
-#define DMA9_Y_COUNT 0xffc00e58 /* DMA Channel 9 Y Count Register */
-#define DMA9_Y_MODIFY 0xffc00e5c /* DMA Channel 9 Y Modify Register */
-#define DMA9_CURR_DESC_PTR 0xffc00e60 /* DMA Channel 9 Current Descriptor Pointer Register */
-#define DMA9_CURR_ADDR 0xffc00e64 /* DMA Channel 9 Current Address Register */
-#define DMA9_IRQ_STATUS 0xffc00e68 /* DMA Channel 9 Interrupt/Status Register */
-#define DMA9_PERIPHERAL_MAP 0xffc00e6c /* DMA Channel 9 Peripheral Map Register */
-#define DMA9_CURR_X_COUNT 0xffc00e70 /* DMA Channel 9 Current X Count Register */
-#define DMA9_CURR_Y_COUNT 0xffc00e78 /* DMA Channel 9 Current Y Count Register */
-
-/* DMA Channel 10 Registers */
-
-#define DMA10_NEXT_DESC_PTR 0xffc00e80 /* DMA Channel 10 Next Descriptor Pointer Register */
-#define DMA10_START_ADDR 0xffc00e84 /* DMA Channel 10 Start Address Register */
-#define DMA10_CONFIG 0xffc00e88 /* DMA Channel 10 Configuration Register */
-#define DMA10_X_COUNT 0xffc00e90 /* DMA Channel 10 X Count Register */
-#define DMA10_X_MODIFY 0xffc00e94 /* DMA Channel 10 X Modify Register */
-#define DMA10_Y_COUNT 0xffc00e98 /* DMA Channel 10 Y Count Register */
-#define DMA10_Y_MODIFY 0xffc00e9c /* DMA Channel 10 Y Modify Register */
-#define DMA10_CURR_DESC_PTR 0xffc00ea0 /* DMA Channel 10 Current Descriptor Pointer Register */
-#define DMA10_CURR_ADDR 0xffc00ea4 /* DMA Channel 10 Current Address Register */
-#define DMA10_IRQ_STATUS 0xffc00ea8 /* DMA Channel 10 Interrupt/Status Register */
-#define DMA10_PERIPHERAL_MAP 0xffc00eac /* DMA Channel 10 Peripheral Map Register */
-#define DMA10_CURR_X_COUNT 0xffc00eb0 /* DMA Channel 10 Current X Count Register */
-#define DMA10_CURR_Y_COUNT 0xffc00eb8 /* DMA Channel 10 Current Y Count Register */
-
-/* DMA Channel 11 Registers */
-
-#define DMA11_NEXT_DESC_PTR 0xffc00ec0 /* DMA Channel 11 Next Descriptor Pointer Register */
-#define DMA11_START_ADDR 0xffc00ec4 /* DMA Channel 11 Start Address Register */
-#define DMA11_CONFIG 0xffc00ec8 /* DMA Channel 11 Configuration Register */
-#define DMA11_X_COUNT 0xffc00ed0 /* DMA Channel 11 X Count Register */
-#define DMA11_X_MODIFY 0xffc00ed4 /* DMA Channel 11 X Modify Register */
-#define DMA11_Y_COUNT 0xffc00ed8 /* DMA Channel 11 Y Count Register */
-#define DMA11_Y_MODIFY 0xffc00edc /* DMA Channel 11 Y Modify Register */
-#define DMA11_CURR_DESC_PTR 0xffc00ee0 /* DMA Channel 11 Current Descriptor Pointer Register */
-#define DMA11_CURR_ADDR 0xffc00ee4 /* DMA Channel 11 Current Address Register */
-#define DMA11_IRQ_STATUS 0xffc00ee8 /* DMA Channel 11 Interrupt/Status Register */
-#define DMA11_PERIPHERAL_MAP 0xffc00eec /* DMA Channel 11 Peripheral Map Register */
-#define DMA11_CURR_X_COUNT 0xffc00ef0 /* DMA Channel 11 Current X Count Register */
-#define DMA11_CURR_Y_COUNT 0xffc00ef8 /* DMA Channel 11 Current Y Count Register */
-
-/* MDMA Stream 0 Registers */
-
-#define MDMA_D0_NEXT_DESC_PTR 0xffc00f00 /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */
-#define MDMA_D0_START_ADDR 0xffc00f04 /* Memory DMA Stream 0 Destination Start Address Register */
-#define MDMA_D0_CONFIG 0xffc00f08 /* Memory DMA Stream 0 Destination Configuration Register */
-#define MDMA_D0_X_COUNT 0xffc00f10 /* Memory DMA Stream 0 Destination X Count Register */
-#define MDMA_D0_X_MODIFY 0xffc00f14 /* Memory DMA Stream 0 Destination X Modify Register */
-#define MDMA_D0_Y_COUNT 0xffc00f18 /* Memory DMA Stream 0 Destination Y Count Register */
-#define MDMA_D0_Y_MODIFY 0xffc00f1c /* Memory DMA Stream 0 Destination Y Modify Register */
-#define MDMA_D0_CURR_DESC_PTR 0xffc00f20 /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */
-#define MDMA_D0_CURR_ADDR 0xffc00f24 /* Memory DMA Stream 0 Destination Current Address Register */
-#define MDMA_D0_IRQ_STATUS 0xffc00f28 /* Memory DMA Stream 0 Destination Interrupt/Status Register */
-#define MDMA_D0_PERIPHERAL_MAP 0xffc00f2c /* Memory DMA Stream 0 Destination Peripheral Map Register */
-#define MDMA_D0_CURR_X_COUNT 0xffc00f30 /* Memory DMA Stream 0 Destination Current X Count Register */
-#define MDMA_D0_CURR_Y_COUNT 0xffc00f38 /* Memory DMA Stream 0 Destination Current Y Count Register */
-#define MDMA_S0_NEXT_DESC_PTR 0xffc00f40 /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */
-#define MDMA_S0_START_ADDR 0xffc00f44 /* Memory DMA Stream 0 Source Start Address Register */
-#define MDMA_S0_CONFIG 0xffc00f48 /* Memory DMA Stream 0 Source Configuration Register */
-#define MDMA_S0_X_COUNT 0xffc00f50 /* Memory DMA Stream 0 Source X Count Register */
-#define MDMA_S0_X_MODIFY 0xffc00f54 /* Memory DMA Stream 0 Source X Modify Register */
-#define MDMA_S0_Y_COUNT 0xffc00f58 /* Memory DMA Stream 0 Source Y Count Register */
-#define MDMA_S0_Y_MODIFY 0xffc00f5c /* Memory DMA Stream 0 Source Y Modify Register */
-#define MDMA_S0_CURR_DESC_PTR 0xffc00f60 /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */
-#define MDMA_S0_CURR_ADDR 0xffc00f64 /* Memory DMA Stream 0 Source Current Address Register */
-#define MDMA_S0_IRQ_STATUS 0xffc00f68 /* Memory DMA Stream 0 Source Interrupt/Status Register */
-#define MDMA_S0_PERIPHERAL_MAP 0xffc00f6c /* Memory DMA Stream 0 Source Peripheral Map Register */
-#define MDMA_S0_CURR_X_COUNT 0xffc00f70 /* Memory DMA Stream 0 Source Current X Count Register */
-#define MDMA_S0_CURR_Y_COUNT 0xffc00f78 /* Memory DMA Stream 0 Source Current Y Count Register */
-
-/* MDMA Stream 1 Registers */
-
-#define MDMA_D1_NEXT_DESC_PTR 0xffc00f80 /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */
-#define MDMA_D1_START_ADDR 0xffc00f84 /* Memory DMA Stream 1 Destination Start Address Register */
-#define MDMA_D1_CONFIG 0xffc00f88 /* Memory DMA Stream 1 Destination Configuration Register */
-#define MDMA_D1_X_COUNT 0xffc00f90 /* Memory DMA Stream 1 Destination X Count Register */
-#define MDMA_D1_X_MODIFY 0xffc00f94 /* Memory DMA Stream 1 Destination X Modify Register */
-#define MDMA_D1_Y_COUNT 0xffc00f98 /* Memory DMA Stream 1 Destination Y Count Register */
-#define MDMA_D1_Y_MODIFY 0xffc00f9c /* Memory DMA Stream 1 Destination Y Modify Register */
-#define MDMA_D1_CURR_DESC_PTR 0xffc00fa0 /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */
-#define MDMA_D1_CURR_ADDR 0xffc00fa4 /* Memory DMA Stream 1 Destination Current Address Register */
-#define MDMA_D1_IRQ_STATUS 0xffc00fa8 /* Memory DMA Stream 1 Destination Interrupt/Status Register */
-#define MDMA_D1_PERIPHERAL_MAP 0xffc00fac /* Memory DMA Stream 1 Destination Peripheral Map Register */
-#define MDMA_D1_CURR_X_COUNT 0xffc00fb0 /* Memory DMA Stream 1 Destination Current X Count Register */
-#define MDMA_D1_CURR_Y_COUNT 0xffc00fb8 /* Memory DMA Stream 1 Destination Current Y Count Register */
-#define MDMA_S1_NEXT_DESC_PTR 0xffc00fc0 /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */
-#define MDMA_S1_START_ADDR 0xffc00fc4 /* Memory DMA Stream 1 Source Start Address Register */
-#define MDMA_S1_CONFIG 0xffc00fc8 /* Memory DMA Stream 1 Source Configuration Register */
-#define MDMA_S1_X_COUNT 0xffc00fd0 /* Memory DMA Stream 1 Source X Count Register */
-#define MDMA_S1_X_MODIFY 0xffc00fd4 /* Memory DMA Stream 1 Source X Modify Register */
-#define MDMA_S1_Y_COUNT 0xffc00fd8 /* Memory DMA Stream 1 Source Y Count Register */
-#define MDMA_S1_Y_MODIFY 0xffc00fdc /* Memory DMA Stream 1 Source Y Modify Register */
-#define MDMA_S1_CURR_DESC_PTR 0xffc00fe0 /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */
-#define MDMA_S1_CURR_ADDR 0xffc00fe4 /* Memory DMA Stream 1 Source Current Address Register */
-#define MDMA_S1_IRQ_STATUS 0xffc00fe8 /* Memory DMA Stream 1 Source Interrupt/Status Register */
-#define MDMA_S1_PERIPHERAL_MAP 0xffc00fec /* Memory DMA Stream 1 Source Peripheral Map Register */
-#define MDMA_S1_CURR_X_COUNT 0xffc00ff0 /* Memory DMA Stream 1 Source Current X Count Register */
-#define MDMA_S1_CURR_Y_COUNT 0xffc00ff8 /* Memory DMA Stream 1 Source Current Y Count Register */
-
-/* UART3 Registers */
-
-#define UART3_DLL 0xffc03100 /* Divisor Latch Low Byte */
-#define UART3_DLH 0xffc03104 /* Divisor Latch High Byte */
-#define UART3_GCTL 0xffc03108 /* Global Control Register */
-#define UART3_LCR 0xffc0310c /* Line Control Register */
-#define UART3_MCR 0xffc03110 /* Modem Control Register */
-#define UART3_LSR 0xffc03114 /* Line Status Register */
-#define UART3_MSR 0xffc03118 /* Modem Status Register */
-#define UART3_SCR 0xffc0311c /* Scratch Register */
-#define UART3_IER_SET 0xffc03120 /* Interrupt Enable Register Set */
-#define UART3_IER_CLEAR 0xffc03124 /* Interrupt Enable Register Clear */
-#define UART3_THR 0xffc03128 /* Transmit Hold Register */
-#define UART3_RBR 0xffc0312c /* Receive Buffer Register */
-
-/* EPPI1 Registers */
-
-#define EPPI1_STATUS 0xffc01300 /* EPPI1 Status Register */
-#define EPPI1_HCOUNT 0xffc01304 /* EPPI1 Horizontal Transfer Count Register */
-#define EPPI1_HDELAY 0xffc01308 /* EPPI1 Horizontal Delay Count Register */
-#define EPPI1_VCOUNT 0xffc0130c /* EPPI1 Vertical Transfer Count Register */
-#define EPPI1_VDELAY 0xffc01310 /* EPPI1 Vertical Delay Count Register */
-#define EPPI1_FRAME 0xffc01314 /* EPPI1 Lines per Frame Register */
-#define EPPI1_LINE 0xffc01318 /* EPPI1 Samples per Line Register */
-#define EPPI1_CLKDIV 0xffc0131c /* EPPI1 Clock Divide Register */
-#define EPPI1_CONTROL 0xffc01320 /* EPPI1 Control Register */
-#define EPPI1_FS1W_HBL 0xffc01324 /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */
-#define EPPI1_FS1P_AVPL 0xffc01328 /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */
-#define EPPI1_FS2W_LVB 0xffc0132c /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */
-#define EPPI1_FS2P_LAVF 0xffc01330 /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */
-#define EPPI1_CLIP 0xffc01334 /* EPPI1 Clipping Register */
-
-/* Port Interrupt 0 Registers (32-bit) */
-
-#define PINT0_MASK_SET 0xffc01400 /* Pin Interrupt 0 Mask Set Register */
-#define PINT0_MASK_CLEAR 0xffc01404 /* Pin Interrupt 0 Mask Clear Register */
-#define PINT0_REQUEST 0xffc01408 /* Pin Interrupt 0 Interrupt Request Register */
-#define PINT0_ASSIGN 0xffc0140c /* Pin Interrupt 0 Port Assign Register */
-#define PINT0_EDGE_SET 0xffc01410 /* Pin Interrupt 0 Edge-sensitivity Set Register */
-#define PINT0_EDGE_CLEAR 0xffc01414 /* Pin Interrupt 0 Edge-sensitivity Clear Register */
-#define PINT0_INVERT_SET 0xffc01418 /* Pin Interrupt 0 Inversion Set Register */
-#define PINT0_INVERT_CLEAR 0xffc0141c /* Pin Interrupt 0 Inversion Clear Register */
-#define PINT0_PINSTATE 0xffc01420 /* Pin Interrupt 0 Pin Status Register */
-#define PINT0_LATCH 0xffc01424 /* Pin Interrupt 0 Latch Register */
-
-/* Port Interrupt 1 Registers (32-bit) */
-
-#define PINT1_MASK_SET 0xffc01430 /* Pin Interrupt 1 Mask Set Register */
-#define PINT1_MASK_CLEAR 0xffc01434 /* Pin Interrupt 1 Mask Clear Register */
-#define PINT1_REQUEST 0xffc01438 /* Pin Interrupt 1 Interrupt Request Register */
-#define PINT1_ASSIGN 0xffc0143c /* Pin Interrupt 1 Port Assign Register */
-#define PINT1_EDGE_SET 0xffc01440 /* Pin Interrupt 1 Edge-sensitivity Set Register */
-#define PINT1_EDGE_CLEAR 0xffc01444 /* Pin Interrupt 1 Edge-sensitivity Clear Register */
-#define PINT1_INVERT_SET 0xffc01448 /* Pin Interrupt 1 Inversion Set Register */
-#define PINT1_INVERT_CLEAR 0xffc0144c /* Pin Interrupt 1 Inversion Clear Register */
-#define PINT1_PINSTATE 0xffc01450 /* Pin Interrupt 1 Pin Status Register */
-#define PINT1_LATCH 0xffc01454 /* Pin Interrupt 1 Latch Register */
-
-/* Port Interrupt 2 Registers (32-bit) */
-
-#define PINT2_MASK_SET 0xffc01460 /* Pin Interrupt 2 Mask Set Register */
-#define PINT2_MASK_CLEAR 0xffc01464 /* Pin Interrupt 2 Mask Clear Register */
-#define PINT2_REQUEST 0xffc01468 /* Pin Interrupt 2 Interrupt Request Register */
-#define PINT2_ASSIGN 0xffc0146c /* Pin Interrupt 2 Port Assign Register */
-#define PINT2_EDGE_SET 0xffc01470 /* Pin Interrupt 2 Edge-sensitivity Set Register */
-#define PINT2_EDGE_CLEAR 0xffc01474 /* Pin Interrupt 2 Edge-sensitivity Clear Register */
-#define PINT2_INVERT_SET 0xffc01478 /* Pin Interrupt 2 Inversion Set Register */
-#define PINT2_INVERT_CLEAR 0xffc0147c /* Pin Interrupt 2 Inversion Clear Register */
-#define PINT2_PINSTATE 0xffc01480 /* Pin Interrupt 2 Pin Status Register */
-#define PINT2_LATCH 0xffc01484 /* Pin Interrupt 2 Latch Register */
-
-/* Port Interrupt 3 Registers (32-bit) */
-
-#define PINT3_MASK_SET 0xffc01490 /* Pin Interrupt 3 Mask Set Register */
-#define PINT3_MASK_CLEAR 0xffc01494 /* Pin Interrupt 3 Mask Clear Register */
-#define PINT3_REQUEST 0xffc01498 /* Pin Interrupt 3 Interrupt Request Register */
-#define PINT3_ASSIGN 0xffc0149c /* Pin Interrupt 3 Port Assign Register */
-#define PINT3_EDGE_SET 0xffc014a0 /* Pin Interrupt 3 Edge-sensitivity Set Register */
-#define PINT3_EDGE_CLEAR 0xffc014a4 /* Pin Interrupt 3 Edge-sensitivity Clear Register */
-#define PINT3_INVERT_SET 0xffc014a8 /* Pin Interrupt 3 Inversion Set Register */
-#define PINT3_INVERT_CLEAR 0xffc014ac /* Pin Interrupt 3 Inversion Clear Register */
-#define PINT3_PINSTATE 0xffc014b0 /* Pin Interrupt 3 Pin Status Register */
-#define PINT3_LATCH 0xffc014b4 /* Pin Interrupt 3 Latch Register */
-
-/* Port A Registers */
-
-#define PORTA_FER 0xffc014c0 /* Function Enable Register */
-#define PORTA 0xffc014c4 /* GPIO Data Register */
-#define PORTA_SET 0xffc014c8 /* GPIO Data Set Register */
-#define PORTA_CLEAR 0xffc014cc /* GPIO Data Clear Register */
-#define PORTA_DIR_SET 0xffc014d0 /* GPIO Direction Set Register */
-#define PORTA_DIR_CLEAR 0xffc014d4 /* GPIO Direction Clear Register */
-#define PORTA_INEN 0xffc014d8 /* GPIO Input Enable Register */
-#define PORTA_MUX 0xffc014dc /* Multiplexer Control Register */
-
-/* Port B Registers */
-
-#define PORTB_FER 0xffc014e0 /* Function Enable Register */
-#define PORTB 0xffc014e4 /* GPIO Data Register */
-#define PORTB_SET 0xffc014e8 /* GPIO Data Set Register */
-#define PORTB_CLEAR 0xffc014ec /* GPIO Data Clear Register */
-#define PORTB_DIR_SET 0xffc014f0 /* GPIO Direction Set Register */
-#define PORTB_DIR_CLEAR 0xffc014f4 /* GPIO Direction Clear Register */
-#define PORTB_INEN 0xffc014f8 /* GPIO Input Enable Register */
-#define PORTB_MUX 0xffc014fc /* Multiplexer Control Register */
-
-/* Port C Registers */
-
-#define PORTC_FER 0xffc01500 /* Function Enable Register */
-#define PORTC 0xffc01504 /* GPIO Data Register */
-#define PORTC_SET 0xffc01508 /* GPIO Data Set Register */
-#define PORTC_CLEAR 0xffc0150c /* GPIO Data Clear Register */
-#define PORTC_DIR_SET 0xffc01510 /* GPIO Direction Set Register */
-#define PORTC_DIR_CLEAR 0xffc01514 /* GPIO Direction Clear Register */
-#define PORTC_INEN 0xffc01518 /* GPIO Input Enable Register */
-#define PORTC_MUX 0xffc0151c /* Multiplexer Control Register */
-
-/* Port D Registers */
-
-#define PORTD_FER 0xffc01520 /* Function Enable Register */
-#define PORTD 0xffc01524 /* GPIO Data Register */
-#define PORTD_SET 0xffc01528 /* GPIO Data Set Register */
-#define PORTD_CLEAR 0xffc0152c /* GPIO Data Clear Register */
-#define PORTD_DIR_SET 0xffc01530 /* GPIO Direction Set Register */
-#define PORTD_DIR_CLEAR 0xffc01534 /* GPIO Direction Clear Register */
-#define PORTD_INEN 0xffc01538 /* GPIO Input Enable Register */
-#define PORTD_MUX 0xffc0153c /* Multiplexer Control Register */
-
-/* Port E Registers */
-
-#define PORTE_FER 0xffc01540 /* Function Enable Register */
-#define PORTE 0xffc01544 /* GPIO Data Register */
-#define PORTE_SET 0xffc01548 /* GPIO Data Set Register */
-#define PORTE_CLEAR 0xffc0154c /* GPIO Data Clear Register */
-#define PORTE_DIR_SET 0xffc01550 /* GPIO Direction Set Register */
-#define PORTE_DIR_CLEAR 0xffc01554 /* GPIO Direction Clear Register */
-#define PORTE_INEN 0xffc01558 /* GPIO Input Enable Register */
-#define PORTE_MUX 0xffc0155c /* Multiplexer Control Register */
-
-/* Port F Registers */
-
-#define PORTF_FER 0xffc01560 /* Function Enable Register */
-#define PORTF 0xffc01564 /* GPIO Data Register */
-#define PORTF_SET 0xffc01568 /* GPIO Data Set Register */
-#define PORTF_CLEAR 0xffc0156c /* GPIO Data Clear Register */
-#define PORTF_DIR_SET 0xffc01570 /* GPIO Direction Set Register */
-#define PORTF_DIR_CLEAR 0xffc01574 /* GPIO Direction Clear Register */
-#define PORTF_INEN 0xffc01578 /* GPIO Input Enable Register */
-#define PORTF_MUX 0xffc0157c /* Multiplexer Control Register */
-
-/* Port G Registers */
-
-#define PORTG_FER 0xffc01580 /* Function Enable Register */
-#define PORTG 0xffc01584 /* GPIO Data Register */
-#define PORTG_SET 0xffc01588 /* GPIO Data Set Register */
-#define PORTG_CLEAR 0xffc0158c /* GPIO Data Clear Register */
-#define PORTG_DIR_SET 0xffc01590 /* GPIO Direction Set Register */
-#define PORTG_DIR_CLEAR 0xffc01594 /* GPIO Direction Clear Register */
-#define PORTG_INEN 0xffc01598 /* GPIO Input Enable Register */
-#define PORTG_MUX 0xffc0159c /* Multiplexer Control Register */
-
-/* Port H Registers */
-
-#define PORTH_FER 0xffc015a0 /* Function Enable Register */
-#define PORTH 0xffc015a4 /* GPIO Data Register */
-#define PORTH_SET 0xffc015a8 /* GPIO Data Set Register */
-#define PORTH_CLEAR 0xffc015ac /* GPIO Data Clear Register */
-#define PORTH_DIR_SET 0xffc015b0 /* GPIO Direction Set Register */
-#define PORTH_DIR_CLEAR 0xffc015b4 /* GPIO Direction Clear Register */
-#define PORTH_INEN 0xffc015b8 /* GPIO Input Enable Register */
-#define PORTH_MUX 0xffc015bc /* Multiplexer Control Register */
-
-/* Port I Registers */
-
-#define PORTI_FER 0xffc015c0 /* Function Enable Register */
-#define PORTI 0xffc015c4 /* GPIO Data Register */
-#define PORTI_SET 0xffc015c8 /* GPIO Data Set Register */
-#define PORTI_CLEAR 0xffc015cc /* GPIO Data Clear Register */
-#define PORTI_DIR_SET 0xffc015d0 /* GPIO Direction Set Register */
-#define PORTI_DIR_CLEAR 0xffc015d4 /* GPIO Direction Clear Register */
-#define PORTI_INEN 0xffc015d8 /* GPIO Input Enable Register */
-#define PORTI_MUX 0xffc015dc /* Multiplexer Control Register */
-
-/* Port J Registers */
-
-#define PORTJ_FER 0xffc015e0 /* Function Enable Register */
-#define PORTJ 0xffc015e4 /* GPIO Data Register */
-#define PORTJ_SET 0xffc015e8 /* GPIO Data Set Register */
-#define PORTJ_CLEAR 0xffc015ec /* GPIO Data Clear Register */
-#define PORTJ_DIR_SET 0xffc015f0 /* GPIO Direction Set Register */
-#define PORTJ_DIR_CLEAR 0xffc015f4 /* GPIO Direction Clear Register */
-#define PORTJ_INEN 0xffc015f8 /* GPIO Input Enable Register */
-#define PORTJ_MUX 0xffc015fc /* Multiplexer Control Register */
-
-/* PWM Timer Registers */
-
-#define TIMER0_CONFIG 0xffc01600 /* Timer 0 Configuration Register */
-#define TIMER0_COUNTER 0xffc01604 /* Timer 0 Counter Register */
-#define TIMER0_PERIOD 0xffc01608 /* Timer 0 Period Register */
-#define TIMER0_WIDTH 0xffc0160c /* Timer 0 Width Register */
-#define TIMER1_CONFIG 0xffc01610 /* Timer 1 Configuration Register */
-#define TIMER1_COUNTER 0xffc01614 /* Timer 1 Counter Register */
-#define TIMER1_PERIOD 0xffc01618 /* Timer 1 Period Register */
-#define TIMER1_WIDTH 0xffc0161c /* Timer 1 Width Register */
-#define TIMER2_CONFIG 0xffc01620 /* Timer 2 Configuration Register */
-#define TIMER2_COUNTER 0xffc01624 /* Timer 2 Counter Register */
-#define TIMER2_PERIOD 0xffc01628 /* Timer 2 Period Register */
-#define TIMER2_WIDTH 0xffc0162c /* Timer 2 Width Register */
-#define TIMER3_CONFIG 0xffc01630 /* Timer 3 Configuration Register */
-#define TIMER3_COUNTER 0xffc01634 /* Timer 3 Counter Register */
-#define TIMER3_PERIOD 0xffc01638 /* Timer 3 Period Register */
-#define TIMER3_WIDTH 0xffc0163c /* Timer 3 Width Register */
-#define TIMER4_CONFIG 0xffc01640 /* Timer 4 Configuration Register */
-#define TIMER4_COUNTER 0xffc01644 /* Timer 4 Counter Register */
-#define TIMER4_PERIOD 0xffc01648 /* Timer 4 Period Register */
-#define TIMER4_WIDTH 0xffc0164c /* Timer 4 Width Register */
-#define TIMER5_CONFIG 0xffc01650 /* Timer 5 Configuration Register */
-#define TIMER5_COUNTER 0xffc01654 /* Timer 5 Counter Register */
-#define TIMER5_PERIOD 0xffc01658 /* Timer 5 Period Register */
-#define TIMER5_WIDTH 0xffc0165c /* Timer 5 Width Register */
-#define TIMER6_CONFIG 0xffc01660 /* Timer 6 Configuration Register */
-#define TIMER6_COUNTER 0xffc01664 /* Timer 6 Counter Register */
-#define TIMER6_PERIOD 0xffc01668 /* Timer 6 Period Register */
-#define TIMER6_WIDTH 0xffc0166c /* Timer 6 Width Register */
-#define TIMER7_CONFIG 0xffc01670 /* Timer 7 Configuration Register */
-#define TIMER7_COUNTER 0xffc01674 /* Timer 7 Counter Register */
-#define TIMER7_PERIOD 0xffc01678 /* Timer 7 Period Register */
-#define TIMER7_WIDTH 0xffc0167c /* Timer 7 Width Register */
-
-/* Timer Group of 8 */
-
-#define TIMER_ENABLE0 0xffc01680 /* Timer Group of 8 Enable Register */
-#define TIMER_DISABLE0 0xffc01684 /* Timer Group of 8 Disable Register */
-#define TIMER_STATUS0 0xffc01688 /* Timer Group of 8 Status Register */
-
-/* DMAC1 Registers */
-
-#define DMAC1_TC_PER 0xffc01b0c /* DMA Controller 1 Traffic Control Periods Register */
-#define DMAC1_TC_CNT 0xffc01b10 /* DMA Controller 1 Current Counts Register */
-
-/* DMA Channel 12 Registers */
-
-#define DMA12_NEXT_DESC_PTR 0xffc01c00 /* DMA Channel 12 Next Descriptor Pointer Register */
-#define DMA12_START_ADDR 0xffc01c04 /* DMA Channel 12 Start Address Register */
-#define DMA12_CONFIG 0xffc01c08 /* DMA Channel 12 Configuration Register */
-#define DMA12_X_COUNT 0xffc01c10 /* DMA Channel 12 X Count Register */
-#define DMA12_X_MODIFY 0xffc01c14 /* DMA Channel 12 X Modify Register */
-#define DMA12_Y_COUNT 0xffc01c18 /* DMA Channel 12 Y Count Register */
-#define DMA12_Y_MODIFY 0xffc01c1c /* DMA Channel 12 Y Modify Register */
-#define DMA12_CURR_DESC_PTR 0xffc01c20 /* DMA Channel 12 Current Descriptor Pointer Register */
-#define DMA12_CURR_ADDR 0xffc01c24 /* DMA Channel 12 Current Address Register */
-#define DMA12_IRQ_STATUS 0xffc01c28 /* DMA Channel 12 Interrupt/Status Register */
-#define DMA12_PERIPHERAL_MAP 0xffc01c2c /* DMA Channel 12 Peripheral Map Register */
-#define DMA12_CURR_X_COUNT 0xffc01c30 /* DMA Channel 12 Current X Count Register */
-#define DMA12_CURR_Y_COUNT 0xffc01c38 /* DMA Channel 12 Current Y Count Register */
-
-/* DMA Channel 13 Registers */
-
-#define DMA13_NEXT_DESC_PTR 0xffc01c40 /* DMA Channel 13 Next Descriptor Pointer Register */
-#define DMA13_START_ADDR 0xffc01c44 /* DMA Channel 13 Start Address Register */
-#define DMA13_CONFIG 0xffc01c48 /* DMA Channel 13 Configuration Register */
-#define DMA13_X_COUNT 0xffc01c50 /* DMA Channel 13 X Count Register */
-#define DMA13_X_MODIFY 0xffc01c54 /* DMA Channel 13 X Modify Register */
-#define DMA13_Y_COUNT 0xffc01c58 /* DMA Channel 13 Y Count Register */
-#define DMA13_Y_MODIFY 0xffc01c5c /* DMA Channel 13 Y Modify Register */
-#define DMA13_CURR_DESC_PTR 0xffc01c60 /* DMA Channel 13 Current Descriptor Pointer Register */
-#define DMA13_CURR_ADDR 0xffc01c64 /* DMA Channel 13 Current Address Register */
-#define DMA13_IRQ_STATUS 0xffc01c68 /* DMA Channel 13 Interrupt/Status Register */
-#define DMA13_PERIPHERAL_MAP 0xffc01c6c /* DMA Channel 13 Peripheral Map Register */
-#define DMA13_CURR_X_COUNT 0xffc01c70 /* DMA Channel 13 Current X Count Register */
-#define DMA13_CURR_Y_COUNT 0xffc01c78 /* DMA Channel 13 Current Y Count Register */
-
-/* DMA Channel 14 Registers */
-
-#define DMA14_NEXT_DESC_PTR 0xffc01c80 /* DMA Channel 14 Next Descriptor Pointer Register */
-#define DMA14_START_ADDR 0xffc01c84 /* DMA Channel 14 Start Address Register */
-#define DMA14_CONFIG 0xffc01c88 /* DMA Channel 14 Configuration Register */
-#define DMA14_X_COUNT 0xffc01c90 /* DMA Channel 14 X Count Register */
-#define DMA14_X_MODIFY 0xffc01c94 /* DMA Channel 14 X Modify Register */
-#define DMA14_Y_COUNT 0xffc01c98 /* DMA Channel 14 Y Count Register */
-#define DMA14_Y_MODIFY 0xffc01c9c /* DMA Channel 14 Y Modify Register */
-#define DMA14_CURR_DESC_PTR 0xffc01ca0 /* DMA Channel 14 Current Descriptor Pointer Register */
-#define DMA14_CURR_ADDR 0xffc01ca4 /* DMA Channel 14 Current Address Register */
-#define DMA14_IRQ_STATUS 0xffc01ca8 /* DMA Channel 14 Interrupt/Status Register */
-#define DMA14_PERIPHERAL_MAP 0xffc01cac /* DMA Channel 14 Peripheral Map Register */
-#define DMA14_CURR_X_COUNT 0xffc01cb0 /* DMA Channel 14 Current X Count Register */
-#define DMA14_CURR_Y_COUNT 0xffc01cb8 /* DMA Channel 14 Current Y Count Register */
-
-/* DMA Channel 15 Registers */
-
-#define DMA15_NEXT_DESC_PTR 0xffc01cc0 /* DMA Channel 15 Next Descriptor Pointer Register */
-#define DMA15_START_ADDR 0xffc01cc4 /* DMA Channel 15 Start Address Register */
-#define DMA15_CONFIG 0xffc01cc8 /* DMA Channel 15 Configuration Register */
-#define DMA15_X_COUNT 0xffc01cd0 /* DMA Channel 15 X Count Register */
-#define DMA15_X_MODIFY 0xffc01cd4 /* DMA Channel 15 X Modify Register */
-#define DMA15_Y_COUNT 0xffc01cd8 /* DMA Channel 15 Y Count Register */
-#define DMA15_Y_MODIFY 0xffc01cdc /* DMA Channel 15 Y Modify Register */
-#define DMA15_CURR_DESC_PTR 0xffc01ce0 /* DMA Channel 15 Current Descriptor Pointer Register */
-#define DMA15_CURR_ADDR 0xffc01ce4 /* DMA Channel 15 Current Address Register */
-#define DMA15_IRQ_STATUS 0xffc01ce8 /* DMA Channel 15 Interrupt/Status Register */
-#define DMA15_PERIPHERAL_MAP 0xffc01cec /* DMA Channel 15 Peripheral Map Register */
-#define DMA15_CURR_X_COUNT 0xffc01cf0 /* DMA Channel 15 Current X Count Register */
-#define DMA15_CURR_Y_COUNT 0xffc01cf8 /* DMA Channel 15 Current Y Count Register */
-
-/* DMA Channel 16 Registers */
-
-#define DMA16_NEXT_DESC_PTR 0xffc01d00 /* DMA Channel 16 Next Descriptor Pointer Register */
-#define DMA16_START_ADDR 0xffc01d04 /* DMA Channel 16 Start Address Register */
-#define DMA16_CONFIG 0xffc01d08 /* DMA Channel 16 Configuration Register */
-#define DMA16_X_COUNT 0xffc01d10 /* DMA Channel 16 X Count Register */
-#define DMA16_X_MODIFY 0xffc01d14 /* DMA Channel 16 X Modify Register */
-#define DMA16_Y_COUNT 0xffc01d18 /* DMA Channel 16 Y Count Register */
-#define DMA16_Y_MODIFY 0xffc01d1c /* DMA Channel 16 Y Modify Register */
-#define DMA16_CURR_DESC_PTR 0xffc01d20 /* DMA Channel 16 Current Descriptor Pointer Register */
-#define DMA16_CURR_ADDR 0xffc01d24 /* DMA Channel 16 Current Address Register */
-#define DMA16_IRQ_STATUS 0xffc01d28 /* DMA Channel 16 Interrupt/Status Register */
-#define DMA16_PERIPHERAL_MAP 0xffc01d2c /* DMA Channel 16 Peripheral Map Register */
-#define DMA16_CURR_X_COUNT 0xffc01d30 /* DMA Channel 16 Current X Count Register */
-#define DMA16_CURR_Y_COUNT 0xffc01d38 /* DMA Channel 16 Current Y Count Register */
-
-/* DMA Channel 17 Registers */
-
-#define DMA17_NEXT_DESC_PTR 0xffc01d40 /* DMA Channel 17 Next Descriptor Pointer Register */
-#define DMA17_START_ADDR 0xffc01d44 /* DMA Channel 17 Start Address Register */
-#define DMA17_CONFIG 0xffc01d48 /* DMA Channel 17 Configuration Register */
-#define DMA17_X_COUNT 0xffc01d50 /* DMA Channel 17 X Count Register */
-#define DMA17_X_MODIFY 0xffc01d54 /* DMA Channel 17 X Modify Register */
-#define DMA17_Y_COUNT 0xffc01d58 /* DMA Channel 17 Y Count Register */
-#define DMA17_Y_MODIFY 0xffc01d5c /* DMA Channel 17 Y Modify Register */
-#define DMA17_CURR_DESC_PTR 0xffc01d60 /* DMA Channel 17 Current Descriptor Pointer Register */
-#define DMA17_CURR_ADDR 0xffc01d64 /* DMA Channel 17 Current Address Register */
-#define DMA17_IRQ_STATUS 0xffc01d68 /* DMA Channel 17 Interrupt/Status Register */
-#define DMA17_PERIPHERAL_MAP 0xffc01d6c /* DMA Channel 17 Peripheral Map Register */
-#define DMA17_CURR_X_COUNT 0xffc01d70 /* DMA Channel 17 Current X Count Register */
-#define DMA17_CURR_Y_COUNT 0xffc01d78 /* DMA Channel 17 Current Y Count Register */
-
-/* DMA Channel 18 Registers */
-
-#define DMA18_NEXT_DESC_PTR 0xffc01d80 /* DMA Channel 18 Next Descriptor Pointer Register */
-#define DMA18_START_ADDR 0xffc01d84 /* DMA Channel 18 Start Address Register */
-#define DMA18_CONFIG 0xffc01d88 /* DMA Channel 18 Configuration Register */
-#define DMA18_X_COUNT 0xffc01d90 /* DMA Channel 18 X Count Register */
-#define DMA18_X_MODIFY 0xffc01d94 /* DMA Channel 18 X Modify Register */
-#define DMA18_Y_COUNT 0xffc01d98 /* DMA Channel 18 Y Count Register */
-#define DMA18_Y_MODIFY 0xffc01d9c /* DMA Channel 18 Y Modify Register */
-#define DMA18_CURR_DESC_PTR 0xffc01da0 /* DMA Channel 18 Current Descriptor Pointer Register */
-#define DMA18_CURR_ADDR 0xffc01da4 /* DMA Channel 18 Current Address Register */
-#define DMA18_IRQ_STATUS 0xffc01da8 /* DMA Channel 18 Interrupt/Status Register */
-#define DMA18_PERIPHERAL_MAP 0xffc01dac /* DMA Channel 18 Peripheral Map Register */
-#define DMA18_CURR_X_COUNT 0xffc01db0 /* DMA Channel 18 Current X Count Register */
-#define DMA18_CURR_Y_COUNT 0xffc01db8 /* DMA Channel 18 Current Y Count Register */
-
-/* DMA Channel 19 Registers */
-
-#define DMA19_NEXT_DESC_PTR 0xffc01dc0 /* DMA Channel 19 Next Descriptor Pointer Register */
-#define DMA19_START_ADDR 0xffc01dc4 /* DMA Channel 19 Start Address Register */
-#define DMA19_CONFIG 0xffc01dc8 /* DMA Channel 19 Configuration Register */
-#define DMA19_X_COUNT 0xffc01dd0 /* DMA Channel 19 X Count Register */
-#define DMA19_X_MODIFY 0xffc01dd4 /* DMA Channel 19 X Modify Register */
-#define DMA19_Y_COUNT 0xffc01dd8 /* DMA Channel 19 Y Count Register */
-#define DMA19_Y_MODIFY 0xffc01ddc /* DMA Channel 19 Y Modify Register */
-#define DMA19_CURR_DESC_PTR 0xffc01de0 /* DMA Channel 19 Current Descriptor Pointer Register */
-#define DMA19_CURR_ADDR 0xffc01de4 /* DMA Channel 19 Current Address Register */
-#define DMA19_IRQ_STATUS 0xffc01de8 /* DMA Channel 19 Interrupt/Status Register */
-#define DMA19_PERIPHERAL_MAP 0xffc01dec /* DMA Channel 19 Peripheral Map Register */
-#define DMA19_CURR_X_COUNT 0xffc01df0 /* DMA Channel 19 Current X Count Register */
-#define DMA19_CURR_Y_COUNT 0xffc01df8 /* DMA Channel 19 Current Y Count Register */
-
-/* DMA Channel 20 Registers */
-
-#define DMA20_NEXT_DESC_PTR 0xffc01e00 /* DMA Channel 20 Next Descriptor Pointer Register */
-#define DMA20_START_ADDR 0xffc01e04 /* DMA Channel 20 Start Address Register */
-#define DMA20_CONFIG 0xffc01e08 /* DMA Channel 20 Configuration Register */
-#define DMA20_X_COUNT 0xffc01e10 /* DMA Channel 20 X Count Register */
-#define DMA20_X_MODIFY 0xffc01e14 /* DMA Channel 20 X Modify Register */
-#define DMA20_Y_COUNT 0xffc01e18 /* DMA Channel 20 Y Count Register */
-#define DMA20_Y_MODIFY 0xffc01e1c /* DMA Channel 20 Y Modify Register */
-#define DMA20_CURR_DESC_PTR 0xffc01e20 /* DMA Channel 20 Current Descriptor Pointer Register */
-#define DMA20_CURR_ADDR 0xffc01e24 /* DMA Channel 20 Current Address Register */
-#define DMA20_IRQ_STATUS 0xffc01e28 /* DMA Channel 20 Interrupt/Status Register */
-#define DMA20_PERIPHERAL_MAP 0xffc01e2c /* DMA Channel 20 Peripheral Map Register */
-#define DMA20_CURR_X_COUNT 0xffc01e30 /* DMA Channel 20 Current X Count Register */
-#define DMA20_CURR_Y_COUNT 0xffc01e38 /* DMA Channel 20 Current Y Count Register */
-
-/* DMA Channel 21 Registers */
-
-#define DMA21_NEXT_DESC_PTR 0xffc01e40 /* DMA Channel 21 Next Descriptor Pointer Register */
-#define DMA21_START_ADDR 0xffc01e44 /* DMA Channel 21 Start Address Register */
-#define DMA21_CONFIG 0xffc01e48 /* DMA Channel 21 Configuration Register */
-#define DMA21_X_COUNT 0xffc01e50 /* DMA Channel 21 X Count Register */
-#define DMA21_X_MODIFY 0xffc01e54 /* DMA Channel 21 X Modify Register */
-#define DMA21_Y_COUNT 0xffc01e58 /* DMA Channel 21 Y Count Register */
-#define DMA21_Y_MODIFY 0xffc01e5c /* DMA Channel 21 Y Modify Register */
-#define DMA21_CURR_DESC_PTR 0xffc01e60 /* DMA Channel 21 Current Descriptor Pointer Register */
-#define DMA21_CURR_ADDR 0xffc01e64 /* DMA Channel 21 Current Address Register */
-#define DMA21_IRQ_STATUS 0xffc01e68 /* DMA Channel 21 Interrupt/Status Register */
-#define DMA21_PERIPHERAL_MAP 0xffc01e6c /* DMA Channel 21 Peripheral Map Register */
-#define DMA21_CURR_X_COUNT 0xffc01e70 /* DMA Channel 21 Current X Count Register */
-#define DMA21_CURR_Y_COUNT 0xffc01e78 /* DMA Channel 21 Current Y Count Register */
-
-/* DMA Channel 22 Registers */
-
-#define DMA22_NEXT_DESC_PTR 0xffc01e80 /* DMA Channel 22 Next Descriptor Pointer Register */
-#define DMA22_START_ADDR 0xffc01e84 /* DMA Channel 22 Start Address Register */
-#define DMA22_CONFIG 0xffc01e88 /* DMA Channel 22 Configuration Register */
-#define DMA22_X_COUNT 0xffc01e90 /* DMA Channel 22 X Count Register */
-#define DMA22_X_MODIFY 0xffc01e94 /* DMA Channel 22 X Modify Register */
-#define DMA22_Y_COUNT 0xffc01e98 /* DMA Channel 22 Y Count Register */
-#define DMA22_Y_MODIFY 0xffc01e9c /* DMA Channel 22 Y Modify Register */
-#define DMA22_CURR_DESC_PTR 0xffc01ea0 /* DMA Channel 22 Current Descriptor Pointer Register */
-#define DMA22_CURR_ADDR 0xffc01ea4 /* DMA Channel 22 Current Address Register */
-#define DMA22_IRQ_STATUS 0xffc01ea8 /* DMA Channel 22 Interrupt/Status Register */
-#define DMA22_PERIPHERAL_MAP 0xffc01eac /* DMA Channel 22 Peripheral Map Register */
-#define DMA22_CURR_X_COUNT 0xffc01eb0 /* DMA Channel 22 Current X Count Register */
-#define DMA22_CURR_Y_COUNT 0xffc01eb8 /* DMA Channel 22 Current Y Count Register */
-
-/* DMA Channel 23 Registers */
-
-#define DMA23_NEXT_DESC_PTR 0xffc01ec0 /* DMA Channel 23 Next Descriptor Pointer Register */
-#define DMA23_START_ADDR 0xffc01ec4 /* DMA Channel 23 Start Address Register */
-#define DMA23_CONFIG 0xffc01ec8 /* DMA Channel 23 Configuration Register */
-#define DMA23_X_COUNT 0xffc01ed0 /* DMA Channel 23 X Count Register */
-#define DMA23_X_MODIFY 0xffc01ed4 /* DMA Channel 23 X Modify Register */
-#define DMA23_Y_COUNT 0xffc01ed8 /* DMA Channel 23 Y Count Register */
-#define DMA23_Y_MODIFY 0xffc01edc /* DMA Channel 23 Y Modify Register */
-#define DMA23_CURR_DESC_PTR 0xffc01ee0 /* DMA Channel 23 Current Descriptor Pointer Register */
-#define DMA23_CURR_ADDR 0xffc01ee4 /* DMA Channel 23 Current Address Register */
-#define DMA23_IRQ_STATUS 0xffc01ee8 /* DMA Channel 23 Interrupt/Status Register */
-#define DMA23_PERIPHERAL_MAP 0xffc01eec /* DMA Channel 23 Peripheral Map Register */
-#define DMA23_CURR_X_COUNT 0xffc01ef0 /* DMA Channel 23 Current X Count Register */
-#define DMA23_CURR_Y_COUNT 0xffc01ef8 /* DMA Channel 23 Current Y Count Register */
-
-/* MDMA Stream 2 Registers */
-
-#define MDMA_D2_NEXT_DESC_PTR 0xffc01f00 /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */
-#define MDMA_D2_START_ADDR 0xffc01f04 /* Memory DMA Stream 2 Destination Start Address Register */
-#define MDMA_D2_CONFIG 0xffc01f08 /* Memory DMA Stream 2 Destination Configuration Register */
-#define MDMA_D2_X_COUNT 0xffc01f10 /* Memory DMA Stream 2 Destination X Count Register */
-#define MDMA_D2_X_MODIFY 0xffc01f14 /* Memory DMA Stream 2 Destination X Modify Register */
-#define MDMA_D2_Y_COUNT 0xffc01f18 /* Memory DMA Stream 2 Destination Y Count Register */
-#define MDMA_D2_Y_MODIFY 0xffc01f1c /* Memory DMA Stream 2 Destination Y Modify Register */
-#define MDMA_D2_CURR_DESC_PTR 0xffc01f20 /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */
-#define MDMA_D2_CURR_ADDR 0xffc01f24 /* Memory DMA Stream 2 Destination Current Address Register */
-#define MDMA_D2_IRQ_STATUS 0xffc01f28 /* Memory DMA Stream 2 Destination Interrupt/Status Register */
-#define MDMA_D2_PERIPHERAL_MAP 0xffc01f2c /* Memory DMA Stream 2 Destination Peripheral Map Register */
-#define MDMA_D2_CURR_X_COUNT 0xffc01f30 /* Memory DMA Stream 2 Destination Current X Count Register */
-#define MDMA_D2_CURR_Y_COUNT 0xffc01f38 /* Memory DMA Stream 2 Destination Current Y Count Register */
-#define MDMA_S2_NEXT_DESC_PTR 0xffc01f40 /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */
-#define MDMA_S2_START_ADDR 0xffc01f44 /* Memory DMA Stream 2 Source Start Address Register */
-#define MDMA_S2_CONFIG 0xffc01f48 /* Memory DMA Stream 2 Source Configuration Register */
-#define MDMA_S2_X_COUNT 0xffc01f50 /* Memory DMA Stream 2 Source X Count Register */
-#define MDMA_S2_X_MODIFY 0xffc01f54 /* Memory DMA Stream 2 Source X Modify Register */
-#define MDMA_S2_Y_COUNT 0xffc01f58 /* Memory DMA Stream 2 Source Y Count Register */
-#define MDMA_S2_Y_MODIFY 0xffc01f5c /* Memory DMA Stream 2 Source Y Modify Register */
-#define MDMA_S2_CURR_DESC_PTR 0xffc01f60 /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */
-#define MDMA_S2_CURR_ADDR 0xffc01f64 /* Memory DMA Stream 2 Source Current Address Register */
-#define MDMA_S2_IRQ_STATUS 0xffc01f68 /* Memory DMA Stream 2 Source Interrupt/Status Register */
-#define MDMA_S2_PERIPHERAL_MAP 0xffc01f6c /* Memory DMA Stream 2 Source Peripheral Map Register */
-#define MDMA_S2_CURR_X_COUNT 0xffc01f70 /* Memory DMA Stream 2 Source Current X Count Register */
-#define MDMA_S2_CURR_Y_COUNT 0xffc01f78 /* Memory DMA Stream 2 Source Current Y Count Register */
-
-/* MDMA Stream 3 Registers */
-
-#define MDMA_D3_NEXT_DESC_PTR 0xffc01f80 /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */
-#define MDMA_D3_START_ADDR 0xffc01f84 /* Memory DMA Stream 3 Destination Start Address Register */
-#define MDMA_D3_CONFIG 0xffc01f88 /* Memory DMA Stream 3 Destination Configuration Register */
-#define MDMA_D3_X_COUNT 0xffc01f90 /* Memory DMA Stream 3 Destination X Count Register */
-#define MDMA_D3_X_MODIFY 0xffc01f94 /* Memory DMA Stream 3 Destination X Modify Register */
-#define MDMA_D3_Y_COUNT 0xffc01f98 /* Memory DMA Stream 3 Destination Y Count Register */
-#define MDMA_D3_Y_MODIFY 0xffc01f9c /* Memory DMA Stream 3 Destination Y Modify Register */
-#define MDMA_D3_CURR_DESC_PTR 0xffc01fa0 /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */
-#define MDMA_D3_CURR_ADDR 0xffc01fa4 /* Memory DMA Stream 3 Destination Current Address Register */
-#define MDMA_D3_IRQ_STATUS 0xffc01fa8 /* Memory DMA Stream 3 Destination Interrupt/Status Register */
-#define MDMA_D3_PERIPHERAL_MAP 0xffc01fac /* Memory DMA Stream 3 Destination Peripheral Map Register */
-#define MDMA_D3_CURR_X_COUNT 0xffc01fb0 /* Memory DMA Stream 3 Destination Current X Count Register */
-#define MDMA_D3_CURR_Y_COUNT 0xffc01fb8 /* Memory DMA Stream 3 Destination Current Y Count Register */
-#define MDMA_S3_NEXT_DESC_PTR 0xffc01fc0 /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */
-#define MDMA_S3_START_ADDR 0xffc01fc4 /* Memory DMA Stream 3 Source Start Address Register */
-#define MDMA_S3_CONFIG 0xffc01fc8 /* Memory DMA Stream 3 Source Configuration Register */
-#define MDMA_S3_X_COUNT 0xffc01fd0 /* Memory DMA Stream 3 Source X Count Register */
-#define MDMA_S3_X_MODIFY 0xffc01fd4 /* Memory DMA Stream 3 Source X Modify Register */
-#define MDMA_S3_Y_COUNT 0xffc01fd8 /* Memory DMA Stream 3 Source Y Count Register */
-#define MDMA_S3_Y_MODIFY 0xffc01fdc /* Memory DMA Stream 3 Source Y Modify Register */
-#define MDMA_S3_CURR_DESC_PTR 0xffc01fe0 /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */
-#define MDMA_S3_CURR_ADDR 0xffc01fe4 /* Memory DMA Stream 3 Source Current Address Register */
-#define MDMA_S3_IRQ_STATUS 0xffc01fe8 /* Memory DMA Stream 3 Source Interrupt/Status Register */
-#define MDMA_S3_PERIPHERAL_MAP 0xffc01fec /* Memory DMA Stream 3 Source Peripheral Map Register */
-#define MDMA_S3_CURR_X_COUNT 0xffc01ff0 /* Memory DMA Stream 3 Source Current X Count Register */
-#define MDMA_S3_CURR_Y_COUNT 0xffc01ff8 /* Memory DMA Stream 3 Source Current Y Count Register */
-
-/* UART1 Registers */
-
-#define UART1_DLL 0xffc02000 /* Divisor Latch Low Byte */
-#define UART1_DLH 0xffc02004 /* Divisor Latch High Byte */
-#define UART1_GCTL 0xffc02008 /* Global Control Register */
-#define UART1_LCR 0xffc0200c /* Line Control Register */
-#define UART1_MCR 0xffc02010 /* Modem Control Register */
-#define UART1_LSR 0xffc02014 /* Line Status Register */
-#define UART1_MSR 0xffc02018 /* Modem Status Register */
-#define UART1_SCR 0xffc0201c /* Scratch Register */
-#define UART1_IER_SET 0xffc02020 /* Interrupt Enable Register Set */
-#define UART1_IER_CLEAR 0xffc02024 /* Interrupt Enable Register Clear */
-#define UART1_THR 0xffc02028 /* Transmit Hold Register */
-#define UART1_RBR 0xffc0202c /* Receive Buffer Register */
-
-/* UART2 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 processors */
-
-/* SPI1 Registers */
-
-#define SPI1_REGBASE 0xffc02300
-#define SPI1_CTL 0xffc02300 /* SPI1 Control Register */
-#define SPI1_FLG 0xffc02304 /* SPI1 Flag Register */
-#define SPI1_STAT 0xffc02308 /* SPI1 Status Register */
-#define SPI1_TDBR 0xffc0230c /* SPI1 Transmit Data Buffer Register */
-#define SPI1_RDBR 0xffc02310 /* SPI1 Receive Data Buffer Register */
-#define SPI1_BAUD 0xffc02314 /* SPI1 Baud Rate Register */
-#define SPI1_SHADOW 0xffc02318 /* SPI1 Receive Data Buffer Shadow Register */
-
-/* SPORT2 Registers */
-
-#define SPORT2_TCR1 0xffc02500 /* SPORT2 Transmit Configuration 1 Register */
-#define SPORT2_TCR2 0xffc02504 /* SPORT2 Transmit Configuration 2 Register */
-#define SPORT2_TCLKDIV 0xffc02508 /* SPORT2 Transmit Serial Clock Divider Register */
-#define SPORT2_TFSDIV 0xffc0250c /* SPORT2 Transmit Frame Sync Divider Register */
-#define SPORT2_TX 0xffc02510 /* SPORT2 Transmit Data Register */
-#define SPORT2_RX 0xffc02518 /* SPORT2 Receive Data Register */
-#define SPORT2_RCR1 0xffc02520 /* SPORT2 Receive Configuration 1 Register */
-#define SPORT2_RCR2 0xffc02524 /* SPORT2 Receive Configuration 2 Register */
-#define SPORT2_RCLKDIV 0xffc02528 /* SPORT2 Receive Serial Clock Divider Register */
-#define SPORT2_RFSDIV 0xffc0252c /* SPORT2 Receive Frame Sync Divider Register */
-#define SPORT2_STAT 0xffc02530 /* SPORT2 Status Register */
-#define SPORT2_CHNL 0xffc02534 /* SPORT2 Current Channel Register */
-#define SPORT2_MCMC1 0xffc02538 /* SPORT2 Multi channel Configuration Register 1 */
-#define SPORT2_MCMC2 0xffc0253c /* SPORT2 Multi channel Configuration Register 2 */
-#define SPORT2_MTCS0 0xffc02540 /* SPORT2 Multi channel Transmit Select Register 0 */
-#define SPORT2_MTCS1 0xffc02544 /* SPORT2 Multi channel Transmit Select Register 1 */
-#define SPORT2_MTCS2 0xffc02548 /* SPORT2 Multi channel Transmit Select Register 2 */
-#define SPORT2_MTCS3 0xffc0254c /* SPORT2 Multi channel Transmit Select Register 3 */
-#define SPORT2_MRCS0 0xffc02550 /* SPORT2 Multi channel Receive Select Register 0 */
-#define SPORT2_MRCS1 0xffc02554 /* SPORT2 Multi channel Receive Select Register 1 */
-#define SPORT2_MRCS2 0xffc02558 /* SPORT2 Multi channel Receive Select Register 2 */
-#define SPORT2_MRCS3 0xffc0255c /* SPORT2 Multi channel Receive Select Register 3 */
-
-/* SPORT3 Registers */
-
-#define SPORT3_TCR1 0xffc02600 /* SPORT3 Transmit Configuration 1 Register */
-#define SPORT3_TCR2 0xffc02604 /* SPORT3 Transmit Configuration 2 Register */
-#define SPORT3_TCLKDIV 0xffc02608 /* SPORT3 Transmit Serial Clock Divider Register */
-#define SPORT3_TFSDIV 0xffc0260c /* SPORT3 Transmit Frame Sync Divider Register */
-#define SPORT3_TX 0xffc02610 /* SPORT3 Transmit Data Register */
-#define SPORT3_RX 0xffc02618 /* SPORT3 Receive Data Register */
-#define SPORT3_RCR1 0xffc02620 /* SPORT3 Receive Configuration 1 Register */
-#define SPORT3_RCR2 0xffc02624 /* SPORT3 Receive Configuration 2 Register */
-#define SPORT3_RCLKDIV 0xffc02628 /* SPORT3 Receive Serial Clock Divider Register */
-#define SPORT3_RFSDIV 0xffc0262c /* SPORT3 Receive Frame Sync Divider Register */
-#define SPORT3_STAT 0xffc02630 /* SPORT3 Status Register */
-#define SPORT3_CHNL 0xffc02634 /* SPORT3 Current Channel Register */
-#define SPORT3_MCMC1 0xffc02638 /* SPORT3 Multi channel Configuration Register 1 */
-#define SPORT3_MCMC2 0xffc0263c /* SPORT3 Multi channel Configuration Register 2 */
-#define SPORT3_MTCS0 0xffc02640 /* SPORT3 Multi channel Transmit Select Register 0 */
-#define SPORT3_MTCS1 0xffc02644 /* SPORT3 Multi channel Transmit Select Register 1 */
-#define SPORT3_MTCS2 0xffc02648 /* SPORT3 Multi channel Transmit Select Register 2 */
-#define SPORT3_MTCS3 0xffc0264c /* SPORT3 Multi channel Transmit Select Register 3 */
-#define SPORT3_MRCS0 0xffc02650 /* SPORT3 Multi channel Receive Select Register 0 */
-#define SPORT3_MRCS1 0xffc02654 /* SPORT3 Multi channel Receive Select Register 1 */
-#define SPORT3_MRCS2 0xffc02658 /* SPORT3 Multi channel Receive Select Register 2 */
-#define SPORT3_MRCS3 0xffc0265c /* SPORT3 Multi channel Receive Select Register 3 */
-
-/* EPPI2 Registers */
-
-#define EPPI2_STATUS 0xffc02900 /* EPPI2 Status Register */
-#define EPPI2_HCOUNT 0xffc02904 /* EPPI2 Horizontal Transfer Count Register */
-#define EPPI2_HDELAY 0xffc02908 /* EPPI2 Horizontal Delay Count Register */
-#define EPPI2_VCOUNT 0xffc0290c /* EPPI2 Vertical Transfer Count Register */
-#define EPPI2_VDELAY 0xffc02910 /* EPPI2 Vertical Delay Count Register */
-#define EPPI2_FRAME 0xffc02914 /* EPPI2 Lines per Frame Register */
-#define EPPI2_LINE 0xffc02918 /* EPPI2 Samples per Line Register */
-#define EPPI2_CLKDIV 0xffc0291c /* EPPI2 Clock Divide Register */
-#define EPPI2_CONTROL 0xffc02920 /* EPPI2 Control Register */
-#define EPPI2_FS1W_HBL 0xffc02924 /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */
-#define EPPI2_FS1P_AVPL 0xffc02928 /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */
-#define EPPI2_FS2W_LVB 0xffc0292c /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */
-#define EPPI2_FS2P_LAVF 0xffc02930 /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */
-#define EPPI2_CLIP 0xffc02934 /* EPPI2 Clipping Register */
-
-/* CAN Controller 0 Config 1 Registers */
-
-#define CAN0_MC1 0xffc02a00 /* CAN Controller 0 Mailbox Configuration Register 1 */
-#define CAN0_MD1 0xffc02a04 /* CAN Controller 0 Mailbox Direction Register 1 */
-#define CAN0_TRS1 0xffc02a08 /* CAN Controller 0 Transmit Request Set Register 1 */
-#define CAN0_TRR1 0xffc02a0c /* CAN Controller 0 Transmit Request Reset Register 1 */
-#define CAN0_TA1 0xffc02a10 /* CAN Controller 0 Transmit Acknowledge Register 1 */
-#define CAN0_AA1 0xffc02a14 /* CAN Controller 0 Abort Acknowledge Register 1 */
-#define CAN0_RMP1 0xffc02a18 /* CAN Controller 0 Receive Message Pending Register 1 */
-#define CAN0_RML1 0xffc02a1c /* CAN Controller 0 Receive Message Lost Register 1 */
-#define CAN0_MBTIF1 0xffc02a20 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */
-#define CAN0_MBRIF1 0xffc02a24 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */
-#define CAN0_MBIM1 0xffc02a28 /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */
-#define CAN0_RFH1 0xffc02a2c /* CAN Controller 0 Remote Frame Handling Enable Register 1 */
-#define CAN0_OPSS1 0xffc02a30 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */
-
-/* CAN Controller 0 Config 2 Registers */
-
-#define CAN0_MC2 0xffc02a40 /* CAN Controller 0 Mailbox Configuration Register 2 */
-#define CAN0_MD2 0xffc02a44 /* CAN Controller 0 Mailbox Direction Register 2 */
-#define CAN0_TRS2 0xffc02a48 /* CAN Controller 0 Transmit Request Set Register 2 */
-#define CAN0_TRR2 0xffc02a4c /* CAN Controller 0 Transmit Request Reset Register 2 */
-#define CAN0_TA2 0xffc02a50 /* CAN Controller 0 Transmit Acknowledge Register 2 */
-#define CAN0_AA2 0xffc02a54 /* CAN Controller 0 Abort Acknowledge Register 2 */
-#define CAN0_RMP2 0xffc02a58 /* CAN Controller 0 Receive Message Pending Register 2 */
-#define CAN0_RML2 0xffc02a5c /* CAN Controller 0 Receive Message Lost Register 2 */
-#define CAN0_MBTIF2 0xffc02a60 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */
-#define CAN0_MBRIF2 0xffc02a64 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */
-#define CAN0_MBIM2 0xffc02a68 /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */
-#define CAN0_RFH2 0xffc02a6c /* CAN Controller 0 Remote Frame Handling Enable Register 2 */
-#define CAN0_OPSS2 0xffc02a70 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */
-
-/* CAN Controller 0 Clock/Interrupt/Counter Registers */
-
-#define CAN0_CLOCK 0xffc02a80 /* CAN Controller 0 Clock Register */
-#define CAN0_TIMING 0xffc02a84 /* CAN Controller 0 Timing Register */
-#define CAN0_DEBUG 0xffc02a88 /* CAN Controller 0 Debug Register */
-#define CAN0_STATUS 0xffc02a8c /* CAN Controller 0 Global Status Register */
-#define CAN0_CEC 0xffc02a90 /* CAN Controller 0 Error Counter Register */
-#define CAN0_GIS 0xffc02a94 /* CAN Controller 0 Global Interrupt Status Register */
-#define CAN0_GIM 0xffc02a98 /* CAN Controller 0 Global Interrupt Mask Register */
-#define CAN0_GIF 0xffc02a9c /* CAN Controller 0 Global Interrupt Flag Register */
-#define CAN0_CONTROL 0xffc02aa0 /* CAN Controller 0 Master Control Register */
-#define CAN0_INTR 0xffc02aa4 /* CAN Controller 0 Interrupt Pending Register */
-#define CAN0_MBTD 0xffc02aac /* CAN Controller 0 Mailbox Temporary Disable Register */
-#define CAN0_EWR 0xffc02ab0 /* CAN Controller 0 Programmable Warning Level Register */
-#define CAN0_ESR 0xffc02ab4 /* CAN Controller 0 Error Status Register */
-#define CAN0_UCCNT 0xffc02ac4 /* CAN Controller 0 Universal Counter Register */
-#define CAN0_UCRC 0xffc02ac8 /* CAN Controller 0 Universal Counter Force Reload Register */
-#define CAN0_UCCNF 0xffc02acc /* CAN Controller 0 Universal Counter Configuration Register */
-
-/* CAN Controller 0 Acceptance Registers */
-
-#define CAN0_AM00L 0xffc02b00 /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */
-#define CAN0_AM00H 0xffc02b04 /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */
-#define CAN0_AM01L 0xffc02b08 /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */
-#define CAN0_AM01H 0xffc02b0c /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */
-#define CAN0_AM02L 0xffc02b10 /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */
-#define CAN0_AM02H 0xffc02b14 /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */
-#define CAN0_AM03L 0xffc02b18 /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */
-#define CAN0_AM03H 0xffc02b1c /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */
-#define CAN0_AM04L 0xffc02b20 /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */
-#define CAN0_AM04H 0xffc02b24 /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */
-#define CAN0_AM05L 0xffc02b28 /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */
-#define CAN0_AM05H 0xffc02b2c /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */
-#define CAN0_AM06L 0xffc02b30 /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */
-#define CAN0_AM06H 0xffc02b34 /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */
-#define CAN0_AM07L 0xffc02b38 /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */
-#define CAN0_AM07H 0xffc02b3c /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */
-#define CAN0_AM08L 0xffc02b40 /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */
-#define CAN0_AM08H 0xffc02b44 /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */
-#define CAN0_AM09L 0xffc02b48 /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */
-#define CAN0_AM09H 0xffc02b4c /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */
-#define CAN0_AM10L 0xffc02b50 /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */
-#define CAN0_AM10H 0xffc02b54 /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */
-#define CAN0_AM11L 0xffc02b58 /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */
-#define CAN0_AM11H 0xffc02b5c /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */
-#define CAN0_AM12L 0xffc02b60 /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */
-#define CAN0_AM12H 0xffc02b64 /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */
-#define CAN0_AM13L 0xffc02b68 /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */
-#define CAN0_AM13H 0xffc02b6c /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */
-#define CAN0_AM14L 0xffc02b70 /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */
-#define CAN0_AM14H 0xffc02b74 /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */
-#define CAN0_AM15L 0xffc02b78 /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */
-#define CAN0_AM15H 0xffc02b7c /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */
-
-/* CAN Controller 0 Acceptance Registers */
-
-#define CAN0_AM16L 0xffc02b80 /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */
-#define CAN0_AM16H 0xffc02b84 /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */
-#define CAN0_AM17L 0xffc02b88 /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */
-#define CAN0_AM17H 0xffc02b8c /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */
-#define CAN0_AM18L 0xffc02b90 /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */
-#define CAN0_AM18H 0xffc02b94 /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */
-#define CAN0_AM19L 0xffc02b98 /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */
-#define CAN0_AM19H 0xffc02b9c /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */
-#define CAN0_AM20L 0xffc02ba0 /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */
-#define CAN0_AM20H 0xffc02ba4 /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */
-#define CAN0_AM21L 0xffc02ba8 /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */
-#define CAN0_AM21H 0xffc02bac /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */
-#define CAN0_AM22L 0xffc02bb0 /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */
-#define CAN0_AM22H 0xffc02bb4 /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */
-#define CAN0_AM23L 0xffc02bb8 /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */
-#define CAN0_AM23H 0xffc02bbc /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */
-#define CAN0_AM24L 0xffc02bc0 /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */
-#define CAN0_AM24H 0xffc02bc4 /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */
-#define CAN0_AM25L 0xffc02bc8 /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */
-#define CAN0_AM25H 0xffc02bcc /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */
-#define CAN0_AM26L 0xffc02bd0 /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */
-#define CAN0_AM26H 0xffc02bd4 /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */
-#define CAN0_AM27L 0xffc02bd8 /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */
-#define CAN0_AM27H 0xffc02bdc /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */
-#define CAN0_AM28L 0xffc02be0 /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */
-#define CAN0_AM28H 0xffc02be4 /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */
-#define CAN0_AM29L 0xffc02be8 /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */
-#define CAN0_AM29H 0xffc02bec /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */
-#define CAN0_AM30L 0xffc02bf0 /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */
-#define CAN0_AM30H 0xffc02bf4 /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */
-#define CAN0_AM31L 0xffc02bf8 /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */
-#define CAN0_AM31H 0xffc02bfc /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */
-
-/* CAN Controller 0 Mailbox Data Registers */
-
-#define CAN0_MB00_DATA0 0xffc02c00 /* CAN Controller 0 Mailbox 0 Data 0 Register */
-#define CAN0_MB00_DATA1 0xffc02c04 /* CAN Controller 0 Mailbox 0 Data 1 Register */
-#define CAN0_MB00_DATA2 0xffc02c08 /* CAN Controller 0 Mailbox 0 Data 2 Register */
-#define CAN0_MB00_DATA3 0xffc02c0c /* CAN Controller 0 Mailbox 0 Data 3 Register */
-#define CAN0_MB00_LENGTH 0xffc02c10 /* CAN Controller 0 Mailbox 0 Length Register */
-#define CAN0_MB00_TIMESTAMP 0xffc02c14 /* CAN Controller 0 Mailbox 0 Timestamp Register */
-#define CAN0_MB00_ID0 0xffc02c18 /* CAN Controller 0 Mailbox 0 ID0 Register */
-#define CAN0_MB00_ID1 0xffc02c1c /* CAN Controller 0 Mailbox 0 ID1 Register */
-#define CAN0_MB01_DATA0 0xffc02c20 /* CAN Controller 0 Mailbox 1 Data 0 Register */
-#define CAN0_MB01_DATA1 0xffc02c24 /* CAN Controller 0 Mailbox 1 Data 1 Register */
-#define CAN0_MB01_DATA2 0xffc02c28 /* CAN Controller 0 Mailbox 1 Data 2 Register */
-#define CAN0_MB01_DATA3 0xffc02c2c /* CAN Controller 0 Mailbox 1 Data 3 Register */
-#define CAN0_MB01_LENGTH 0xffc02c30 /* CAN Controller 0 Mailbox 1 Length Register */
-#define CAN0_MB01_TIMESTAMP 0xffc02c34 /* CAN Controller 0 Mailbox 1 Timestamp Register */
-#define CAN0_MB01_ID0 0xffc02c38 /* CAN Controller 0 Mailbox 1 ID0 Register */
-#define CAN0_MB01_ID1 0xffc02c3c /* CAN Controller 0 Mailbox 1 ID1 Register */
-#define CAN0_MB02_DATA0 0xffc02c40 /* CAN Controller 0 Mailbox 2 Data 0 Register */
-#define CAN0_MB02_DATA1 0xffc02c44 /* CAN Controller 0 Mailbox 2 Data 1 Register */
-#define CAN0_MB02_DATA2 0xffc02c48 /* CAN Controller 0 Mailbox 2 Data 2 Register */
-#define CAN0_MB02_DATA3 0xffc02c4c /* CAN Controller 0 Mailbox 2 Data 3 Register */
-#define CAN0_MB02_LENGTH 0xffc02c50 /* CAN Controller 0 Mailbox 2 Length Register */
-#define CAN0_MB02_TIMESTAMP 0xffc02c54 /* CAN Controller 0 Mailbox 2 Timestamp Register */
-#define CAN0_MB02_ID0 0xffc02c58 /* CAN Controller 0 Mailbox 2 ID0 Register */
-#define CAN0_MB02_ID1 0xffc02c5c /* CAN Controller 0 Mailbox 2 ID1 Register */
-#define CAN0_MB03_DATA0 0xffc02c60 /* CAN Controller 0 Mailbox 3 Data 0 Register */
-#define CAN0_MB03_DATA1 0xffc02c64 /* CAN Controller 0 Mailbox 3 Data 1 Register */
-#define CAN0_MB03_DATA2 0xffc02c68 /* CAN Controller 0 Mailbox 3 Data 2 Register */
-#define CAN0_MB03_DATA3 0xffc02c6c /* CAN Controller 0 Mailbox 3 Data 3 Register */
-#define CAN0_MB03_LENGTH 0xffc02c70 /* CAN Controller 0 Mailbox 3 Length Register */
-#define CAN0_MB03_TIMESTAMP 0xffc02c74 /* CAN Controller 0 Mailbox 3 Timestamp Register */
-#define CAN0_MB03_ID0 0xffc02c78 /* CAN Controller 0 Mailbox 3 ID0 Register */
-#define CAN0_MB03_ID1 0xffc02c7c /* CAN Controller 0 Mailbox 3 ID1 Register */
-#define CAN0_MB04_DATA0 0xffc02c80 /* CAN Controller 0 Mailbox 4 Data 0 Register */
-#define CAN0_MB04_DATA1 0xffc02c84 /* CAN Controller 0 Mailbox 4 Data 1 Register */
-#define CAN0_MB04_DATA2 0xffc02c88 /* CAN Controller 0 Mailbox 4 Data 2 Register */
-#define CAN0_MB04_DATA3 0xffc02c8c /* CAN Controller 0 Mailbox 4 Data 3 Register */
-#define CAN0_MB04_LENGTH 0xffc02c90 /* CAN Controller 0 Mailbox 4 Length Register */
-#define CAN0_MB04_TIMESTAMP 0xffc02c94 /* CAN Controller 0 Mailbox 4 Timestamp Register */
-#define CAN0_MB04_ID0 0xffc02c98 /* CAN Controller 0 Mailbox 4 ID0 Register */
-#define CAN0_MB04_ID1 0xffc02c9c /* CAN Controller 0 Mailbox 4 ID1 Register */
-#define CAN0_MB05_DATA0 0xffc02ca0 /* CAN Controller 0 Mailbox 5 Data 0 Register */
-#define CAN0_MB05_DATA1 0xffc02ca4 /* CAN Controller 0 Mailbox 5 Data 1 Register */
-#define CAN0_MB05_DATA2 0xffc02ca8 /* CAN Controller 0 Mailbox 5 Data 2 Register */
-#define CAN0_MB05_DATA3 0xffc02cac /* CAN Controller 0 Mailbox 5 Data 3 Register */
-#define CAN0_MB05_LENGTH 0xffc02cb0 /* CAN Controller 0 Mailbox 5 Length Register */
-#define CAN0_MB05_TIMESTAMP 0xffc02cb4 /* CAN Controller 0 Mailbox 5 Timestamp Register */
-#define CAN0_MB05_ID0 0xffc02cb8 /* CAN Controller 0 Mailbox 5 ID0 Register */
-#define CAN0_MB05_ID1 0xffc02cbc /* CAN Controller 0 Mailbox 5 ID1 Register */
-#define CAN0_MB06_DATA0 0xffc02cc0 /* CAN Controller 0 Mailbox 6 Data 0 Register */
-#define CAN0_MB06_DATA1 0xffc02cc4 /* CAN Controller 0 Mailbox 6 Data 1 Register */
-#define CAN0_MB06_DATA2 0xffc02cc8 /* CAN Controller 0 Mailbox 6 Data 2 Register */
-#define CAN0_MB06_DATA3 0xffc02ccc /* CAN Controller 0 Mailbox 6 Data 3 Register */
-#define CAN0_MB06_LENGTH 0xffc02cd0 /* CAN Controller 0 Mailbox 6 Length Register */
-#define CAN0_MB06_TIMESTAMP 0xffc02cd4 /* CAN Controller 0 Mailbox 6 Timestamp Register */
-#define CAN0_MB06_ID0 0xffc02cd8 /* CAN Controller 0 Mailbox 6 ID0 Register */
-#define CAN0_MB06_ID1 0xffc02cdc /* CAN Controller 0 Mailbox 6 ID1 Register */
-#define CAN0_MB07_DATA0 0xffc02ce0 /* CAN Controller 0 Mailbox 7 Data 0 Register */
-#define CAN0_MB07_DATA1 0xffc02ce4 /* CAN Controller 0 Mailbox 7 Data 1 Register */
-#define CAN0_MB07_DATA2 0xffc02ce8 /* CAN Controller 0 Mailbox 7 Data 2 Register */
-#define CAN0_MB07_DATA3 0xffc02cec /* CAN Controller 0 Mailbox 7 Data 3 Register */
-#define CAN0_MB07_LENGTH 0xffc02cf0 /* CAN Controller 0 Mailbox 7 Length Register */
-#define CAN0_MB07_TIMESTAMP 0xffc02cf4 /* CAN Controller 0 Mailbox 7 Timestamp Register */
-#define CAN0_MB07_ID0 0xffc02cf8 /* CAN Controller 0 Mailbox 7 ID0 Register */
-#define CAN0_MB07_ID1 0xffc02cfc /* CAN Controller 0 Mailbox 7 ID1 Register */
-#define CAN0_MB08_DATA0 0xffc02d00 /* CAN Controller 0 Mailbox 8 Data 0 Register */
-#define CAN0_MB08_DATA1 0xffc02d04 /* CAN Controller 0 Mailbox 8 Data 1 Register */
-#define CAN0_MB08_DATA2 0xffc02d08 /* CAN Controller 0 Mailbox 8 Data 2 Register */
-#define CAN0_MB08_DATA3 0xffc02d0c /* CAN Controller 0 Mailbox 8 Data 3 Register */
-#define CAN0_MB08_LENGTH 0xffc02d10 /* CAN Controller 0 Mailbox 8 Length Register */
-#define CAN0_MB08_TIMESTAMP 0xffc02d14 /* CAN Controller 0 Mailbox 8 Timestamp Register */
-#define CAN0_MB08_ID0 0xffc02d18 /* CAN Controller 0 Mailbox 8 ID0 Register */
-#define CAN0_MB08_ID1 0xffc02d1c /* CAN Controller 0 Mailbox 8 ID1 Register */
-#define CAN0_MB09_DATA0 0xffc02d20 /* CAN Controller 0 Mailbox 9 Data 0 Register */
-#define CAN0_MB09_DATA1 0xffc02d24 /* CAN Controller 0 Mailbox 9 Data 1 Register */
-#define CAN0_MB09_DATA2 0xffc02d28 /* CAN Controller 0 Mailbox 9 Data 2 Register */
-#define CAN0_MB09_DATA3 0xffc02d2c /* CAN Controller 0 Mailbox 9 Data 3 Register */
-#define CAN0_MB09_LENGTH 0xffc02d30 /* CAN Controller 0 Mailbox 9 Length Register */
-#define CAN0_MB09_TIMESTAMP 0xffc02d34 /* CAN Controller 0 Mailbox 9 Timestamp Register */
-#define CAN0_MB09_ID0 0xffc02d38 /* CAN Controller 0 Mailbox 9 ID0 Register */
-#define CAN0_MB09_ID1 0xffc02d3c /* CAN Controller 0 Mailbox 9 ID1 Register */
-#define CAN0_MB10_DATA0 0xffc02d40 /* CAN Controller 0 Mailbox 10 Data 0 Register */
-#define CAN0_MB10_DATA1 0xffc02d44 /* CAN Controller 0 Mailbox 10 Data 1 Register */
-#define CAN0_MB10_DATA2 0xffc02d48 /* CAN Controller 0 Mailbox 10 Data 2 Register */
-#define CAN0_MB10_DATA3 0xffc02d4c /* CAN Controller 0 Mailbox 10 Data 3 Register */
-#define CAN0_MB10_LENGTH 0xffc02d50 /* CAN Controller 0 Mailbox 10 Length Register */
-#define CAN0_MB10_TIMESTAMP 0xffc02d54 /* CAN Controller 0 Mailbox 10 Timestamp Register */
-#define CAN0_MB10_ID0 0xffc02d58 /* CAN Controller 0 Mailbox 10 ID0 Register */
-#define CAN0_MB10_ID1 0xffc02d5c /* CAN Controller 0 Mailbox 10 ID1 Register */
-#define CAN0_MB11_DATA0 0xffc02d60 /* CAN Controller 0 Mailbox 11 Data 0 Register */
-#define CAN0_MB11_DATA1 0xffc02d64 /* CAN Controller 0 Mailbox 11 Data 1 Register */
-#define CAN0_MB11_DATA2 0xffc02d68 /* CAN Controller 0 Mailbox 11 Data 2 Register */
-#define CAN0_MB11_DATA3 0xffc02d6c /* CAN Controller 0 Mailbox 11 Data 3 Register */
-#define CAN0_MB11_LENGTH 0xffc02d70 /* CAN Controller 0 Mailbox 11 Length Register */
-#define CAN0_MB11_TIMESTAMP 0xffc02d74 /* CAN Controller 0 Mailbox 11 Timestamp Register */
-#define CAN0_MB11_ID0 0xffc02d78 /* CAN Controller 0 Mailbox 11 ID0 Register */
-#define CAN0_MB11_ID1 0xffc02d7c /* CAN Controller 0 Mailbox 11 ID1 Register */
-#define CAN0_MB12_DATA0 0xffc02d80 /* CAN Controller 0 Mailbox 12 Data 0 Register */
-#define CAN0_MB12_DATA1 0xffc02d84 /* CAN Controller 0 Mailbox 12 Data 1 Register */
-#define CAN0_MB12_DATA2 0xffc02d88 /* CAN Controller 0 Mailbox 12 Data 2 Register */
-#define CAN0_MB12_DATA3 0xffc02d8c /* CAN Controller 0 Mailbox 12 Data 3 Register */
-#define CAN0_MB12_LENGTH 0xffc02d90 /* CAN Controller 0 Mailbox 12 Length Register */
-#define CAN0_MB12_TIMESTAMP 0xffc02d94 /* CAN Controller 0 Mailbox 12 Timestamp Register */
-#define CAN0_MB12_ID0 0xffc02d98 /* CAN Controller 0 Mailbox 12 ID0 Register */
-#define CAN0_MB12_ID1 0xffc02d9c /* CAN Controller 0 Mailbox 12 ID1 Register */
-#define CAN0_MB13_DATA0 0xffc02da0 /* CAN Controller 0 Mailbox 13 Data 0 Register */
-#define CAN0_MB13_DATA1 0xffc02da4 /* CAN Controller 0 Mailbox 13 Data 1 Register */
-#define CAN0_MB13_DATA2 0xffc02da8 /* CAN Controller 0 Mailbox 13 Data 2 Register */
-#define CAN0_MB13_DATA3 0xffc02dac /* CAN Controller 0 Mailbox 13 Data 3 Register */
-#define CAN0_MB13_LENGTH 0xffc02db0 /* CAN Controller 0 Mailbox 13 Length Register */
-#define CAN0_MB13_TIMESTAMP 0xffc02db4 /* CAN Controller 0 Mailbox 13 Timestamp Register */
-#define CAN0_MB13_ID0 0xffc02db8 /* CAN Controller 0 Mailbox 13 ID0 Register */
-#define CAN0_MB13_ID1 0xffc02dbc /* CAN Controller 0 Mailbox 13 ID1 Register */
-#define CAN0_MB14_DATA0 0xffc02dc0 /* CAN Controller 0 Mailbox 14 Data 0 Register */
-#define CAN0_MB14_DATA1 0xffc02dc4 /* CAN Controller 0 Mailbox 14 Data 1 Register */
-#define CAN0_MB14_DATA2 0xffc02dc8 /* CAN Controller 0 Mailbox 14 Data 2 Register */
-#define CAN0_MB14_DATA3 0xffc02dcc /* CAN Controller 0 Mailbox 14 Data 3 Register */
-#define CAN0_MB14_LENGTH 0xffc02dd0 /* CAN Controller 0 Mailbox 14 Length Register */
-#define CAN0_MB14_TIMESTAMP 0xffc02dd4 /* CAN Controller 0 Mailbox 14 Timestamp Register */
-#define CAN0_MB14_ID0 0xffc02dd8 /* CAN Controller 0 Mailbox 14 ID0 Register */
-#define CAN0_MB14_ID1 0xffc02ddc /* CAN Controller 0 Mailbox 14 ID1 Register */
-#define CAN0_MB15_DATA0 0xffc02de0 /* CAN Controller 0 Mailbox 15 Data 0 Register */
-#define CAN0_MB15_DATA1 0xffc02de4 /* CAN Controller 0 Mailbox 15 Data 1 Register */
-#define CAN0_MB15_DATA2 0xffc02de8 /* CAN Controller 0 Mailbox 15 Data 2 Register */
-#define CAN0_MB15_DATA3 0xffc02dec /* CAN Controller 0 Mailbox 15 Data 3 Register */
-#define CAN0_MB15_LENGTH 0xffc02df0 /* CAN Controller 0 Mailbox 15 Length Register */
-#define CAN0_MB15_TIMESTAMP 0xffc02df4 /* CAN Controller 0 Mailbox 15 Timestamp Register */
-#define CAN0_MB15_ID0 0xffc02df8 /* CAN Controller 0 Mailbox 15 ID0 Register */
-#define CAN0_MB15_ID1 0xffc02dfc /* CAN Controller 0 Mailbox 15 ID1 Register */
-
-/* CAN Controller 0 Mailbox Data Registers */
-
-#define CAN0_MB16_DATA0 0xffc02e00 /* CAN Controller 0 Mailbox 16 Data 0 Register */
-#define CAN0_MB16_DATA1 0xffc02e04 /* CAN Controller 0 Mailbox 16 Data 1 Register */
-#define CAN0_MB16_DATA2 0xffc02e08 /* CAN Controller 0 Mailbox 16 Data 2 Register */
-#define CAN0_MB16_DATA3 0xffc02e0c /* CAN Controller 0 Mailbox 16 Data 3 Register */
-#define CAN0_MB16_LENGTH 0xffc02e10 /* CAN Controller 0 Mailbox 16 Length Register */
-#define CAN0_MB16_TIMESTAMP 0xffc02e14 /* CAN Controller 0 Mailbox 16 Timestamp Register */
-#define CAN0_MB16_ID0 0xffc02e18 /* CAN Controller 0 Mailbox 16 ID0 Register */
-#define CAN0_MB16_ID1 0xffc02e1c /* CAN Controller 0 Mailbox 16 ID1 Register */
-#define CAN0_MB17_DATA0 0xffc02e20 /* CAN Controller 0 Mailbox 17 Data 0 Register */
-#define CAN0_MB17_DATA1 0xffc02e24 /* CAN Controller 0 Mailbox 17 Data 1 Register */
-#define CAN0_MB17_DATA2 0xffc02e28 /* CAN Controller 0 Mailbox 17 Data 2 Register */
-#define CAN0_MB17_DATA3 0xffc02e2c /* CAN Controller 0 Mailbox 17 Data 3 Register */
-#define CAN0_MB17_LENGTH 0xffc02e30 /* CAN Controller 0 Mailbox 17 Length Register */
-#define CAN0_MB17_TIMESTAMP 0xffc02e34 /* CAN Controller 0 Mailbox 17 Timestamp Register */
-#define CAN0_MB17_ID0 0xffc02e38 /* CAN Controller 0 Mailbox 17 ID0 Register */
-#define CAN0_MB17_ID1 0xffc02e3c /* CAN Controller 0 Mailbox 17 ID1 Register */
-#define CAN0_MB18_DATA0 0xffc02e40 /* CAN Controller 0 Mailbox 18 Data 0 Register */
-#define CAN0_MB18_DATA1 0xffc02e44 /* CAN Controller 0 Mailbox 18 Data 1 Register */
-#define CAN0_MB18_DATA2 0xffc02e48 /* CAN Controller 0 Mailbox 18 Data 2 Register */
-#define CAN0_MB18_DATA3 0xffc02e4c /* CAN Controller 0 Mailbox 18 Data 3 Register */
-#define CAN0_MB18_LENGTH 0xffc02e50 /* CAN Controller 0 Mailbox 18 Length Register */
-#define CAN0_MB18_TIMESTAMP 0xffc02e54 /* CAN Controller 0 Mailbox 18 Timestamp Register */
-#define CAN0_MB18_ID0 0xffc02e58 /* CAN Controller 0 Mailbox 18 ID0 Register */
-#define CAN0_MB18_ID1 0xffc02e5c /* CAN Controller 0 Mailbox 18 ID1 Register */
-#define CAN0_MB19_DATA0 0xffc02e60 /* CAN Controller 0 Mailbox 19 Data 0 Register */
-#define CAN0_MB19_DATA1 0xffc02e64 /* CAN Controller 0 Mailbox 19 Data 1 Register */
-#define CAN0_MB19_DATA2 0xffc02e68 /* CAN Controller 0 Mailbox 19 Data 2 Register */
-#define CAN0_MB19_DATA3 0xffc02e6c /* CAN Controller 0 Mailbox 19 Data 3 Register */
-#define CAN0_MB19_LENGTH 0xffc02e70 /* CAN Controller 0 Mailbox 19 Length Register */
-#define CAN0_MB19_TIMESTAMP 0xffc02e74 /* CAN Controller 0 Mailbox 19 Timestamp Register */
-#define CAN0_MB19_ID0 0xffc02e78 /* CAN Controller 0 Mailbox 19 ID0 Register */
-#define CAN0_MB19_ID1 0xffc02e7c /* CAN Controller 0 Mailbox 19 ID1 Register */
-#define CAN0_MB20_DATA0 0xffc02e80 /* CAN Controller 0 Mailbox 20 Data 0 Register */
-#define CAN0_MB20_DATA1 0xffc02e84 /* CAN Controller 0 Mailbox 20 Data 1 Register */
-#define CAN0_MB20_DATA2 0xffc02e88 /* CAN Controller 0 Mailbox 20 Data 2 Register */
-#define CAN0_MB20_DATA3 0xffc02e8c /* CAN Controller 0 Mailbox 20 Data 3 Register */
-#define CAN0_MB20_LENGTH 0xffc02e90 /* CAN Controller 0 Mailbox 20 Length Register */
-#define CAN0_MB20_TIMESTAMP 0xffc02e94 /* CAN Controller 0 Mailbox 20 Timestamp Register */
-#define CAN0_MB20_ID0 0xffc02e98 /* CAN Controller 0 Mailbox 20 ID0 Register */
-#define CAN0_MB20_ID1 0xffc02e9c /* CAN Controller 0 Mailbox 20 ID1 Register */
-#define CAN0_MB21_DATA0 0xffc02ea0 /* CAN Controller 0 Mailbox 21 Data 0 Register */
-#define CAN0_MB21_DATA1 0xffc02ea4 /* CAN Controller 0 Mailbox 21 Data 1 Register */
-#define CAN0_MB21_DATA2 0xffc02ea8 /* CAN Controller 0 Mailbox 21 Data 2 Register */
-#define CAN0_MB21_DATA3 0xffc02eac /* CAN Controller 0 Mailbox 21 Data 3 Register */
-#define CAN0_MB21_LENGTH 0xffc02eb0 /* CAN Controller 0 Mailbox 21 Length Register */
-#define CAN0_MB21_TIMESTAMP 0xffc02eb4 /* CAN Controller 0 Mailbox 21 Timestamp Register */
-#define CAN0_MB21_ID0 0xffc02eb8 /* CAN Controller 0 Mailbox 21 ID0 Register */
-#define CAN0_MB21_ID1 0xffc02ebc /* CAN Controller 0 Mailbox 21 ID1 Register */
-#define CAN0_MB22_DATA0 0xffc02ec0 /* CAN Controller 0 Mailbox 22 Data 0 Register */
-#define CAN0_MB22_DATA1 0xffc02ec4 /* CAN Controller 0 Mailbox 22 Data 1 Register */
-#define CAN0_MB22_DATA2 0xffc02ec8 /* CAN Controller 0 Mailbox 22 Data 2 Register */
-#define CAN0_MB22_DATA3 0xffc02ecc /* CAN Controller 0 Mailbox 22 Data 3 Register */
-#define CAN0_MB22_LENGTH 0xffc02ed0 /* CAN Controller 0 Mailbox 22 Length Register */
-#define CAN0_MB22_TIMESTAMP 0xffc02ed4 /* CAN Controller 0 Mailbox 22 Timestamp Register */
-#define CAN0_MB22_ID0 0xffc02ed8 /* CAN Controller 0 Mailbox 22 ID0 Register */
-#define CAN0_MB22_ID1 0xffc02edc /* CAN Controller 0 Mailbox 22 ID1 Register */
-#define CAN0_MB23_DATA0 0xffc02ee0 /* CAN Controller 0 Mailbox 23 Data 0 Register */
-#define CAN0_MB23_DATA1 0xffc02ee4 /* CAN Controller 0 Mailbox 23 Data 1 Register */
-#define CAN0_MB23_DATA2 0xffc02ee8 /* CAN Controller 0 Mailbox 23 Data 2 Register */
-#define CAN0_MB23_DATA3 0xffc02eec /* CAN Controller 0 Mailbox 23 Data 3 Register */
-#define CAN0_MB23_LENGTH 0xffc02ef0 /* CAN Controller 0 Mailbox 23 Length Register */
-#define CAN0_MB23_TIMESTAMP 0xffc02ef4 /* CAN Controller 0 Mailbox 23 Timestamp Register */
-#define CAN0_MB23_ID0 0xffc02ef8 /* CAN Controller 0 Mailbox 23 ID0 Register */
-#define CAN0_MB23_ID1 0xffc02efc /* CAN Controller 0 Mailbox 23 ID1 Register */
-#define CAN0_MB24_DATA0 0xffc02f00 /* CAN Controller 0 Mailbox 24 Data 0 Register */
-#define CAN0_MB24_DATA1 0xffc02f04 /* CAN Controller 0 Mailbox 24 Data 1 Register */
-#define CAN0_MB24_DATA2 0xffc02f08 /* CAN Controller 0 Mailbox 24 Data 2 Register */
-#define CAN0_MB24_DATA3 0xffc02f0c /* CAN Controller 0 Mailbox 24 Data 3 Register */
-#define CAN0_MB24_LENGTH 0xffc02f10 /* CAN Controller 0 Mailbox 24 Length Register */
-#define CAN0_MB24_TIMESTAMP 0xffc02f14 /* CAN Controller 0 Mailbox 24 Timestamp Register */
-#define CAN0_MB24_ID0 0xffc02f18 /* CAN Controller 0 Mailbox 24 ID0 Register */
-#define CAN0_MB24_ID1 0xffc02f1c /* CAN Controller 0 Mailbox 24 ID1 Register */
-#define CAN0_MB25_DATA0 0xffc02f20 /* CAN Controller 0 Mailbox 25 Data 0 Register */
-#define CAN0_MB25_DATA1 0xffc02f24 /* CAN Controller 0 Mailbox 25 Data 1 Register */
-#define CAN0_MB25_DATA2 0xffc02f28 /* CAN Controller 0 Mailbox 25 Data 2 Register */
-#define CAN0_MB25_DATA3 0xffc02f2c /* CAN Controller 0 Mailbox 25 Data 3 Register */
-#define CAN0_MB25_LENGTH 0xffc02f30 /* CAN Controller 0 Mailbox 25 Length Register */
-#define CAN0_MB25_TIMESTAMP 0xffc02f34 /* CAN Controller 0 Mailbox 25 Timestamp Register */
-#define CAN0_MB25_ID0 0xffc02f38 /* CAN Controller 0 Mailbox 25 ID0 Register */
-#define CAN0_MB25_ID1 0xffc02f3c /* CAN Controller 0 Mailbox 25 ID1 Register */
-#define CAN0_MB26_DATA0 0xffc02f40 /* CAN Controller 0 Mailbox 26 Data 0 Register */
-#define CAN0_MB26_DATA1 0xffc02f44 /* CAN Controller 0 Mailbox 26 Data 1 Register */
-#define CAN0_MB26_DATA2 0xffc02f48 /* CAN Controller 0 Mailbox 26 Data 2 Register */
-#define CAN0_MB26_DATA3 0xffc02f4c /* CAN Controller 0 Mailbox 26 Data 3 Register */
-#define CAN0_MB26_LENGTH 0xffc02f50 /* CAN Controller 0 Mailbox 26 Length Register */
-#define CAN0_MB26_TIMESTAMP 0xffc02f54 /* CAN Controller 0 Mailbox 26 Timestamp Register */
-#define CAN0_MB26_ID0 0xffc02f58 /* CAN Controller 0 Mailbox 26 ID0 Register */
-#define CAN0_MB26_ID1 0xffc02f5c /* CAN Controller 0 Mailbox 26 ID1 Register */
-#define CAN0_MB27_DATA0 0xffc02f60 /* CAN Controller 0 Mailbox 27 Data 0 Register */
-#define CAN0_MB27_DATA1 0xffc02f64 /* CAN Controller 0 Mailbox 27 Data 1 Register */
-#define CAN0_MB27_DATA2 0xffc02f68 /* CAN Controller 0 Mailbox 27 Data 2 Register */
-#define CAN0_MB27_DATA3 0xffc02f6c /* CAN Controller 0 Mailbox 27 Data 3 Register */
-#define CAN0_MB27_LENGTH 0xffc02f70 /* CAN Controller 0 Mailbox 27 Length Register */
-#define CAN0_MB27_TIMESTAMP 0xffc02f74 /* CAN Controller 0 Mailbox 27 Timestamp Register */
-#define CAN0_MB27_ID0 0xffc02f78 /* CAN Controller 0 Mailbox 27 ID0 Register */
-#define CAN0_MB27_ID1 0xffc02f7c /* CAN Controller 0 Mailbox 27 ID1 Register */
-#define CAN0_MB28_DATA0 0xffc02f80 /* CAN Controller 0 Mailbox 28 Data 0 Register */
-#define CAN0_MB28_DATA1 0xffc02f84 /* CAN Controller 0 Mailbox 28 Data 1 Register */
-#define CAN0_MB28_DATA2 0xffc02f88 /* CAN Controller 0 Mailbox 28 Data 2 Register */
-#define CAN0_MB28_DATA3 0xffc02f8c /* CAN Controller 0 Mailbox 28 Data 3 Register */
-#define CAN0_MB28_LENGTH 0xffc02f90 /* CAN Controller 0 Mailbox 28 Length Register */
-#define CAN0_MB28_TIMESTAMP 0xffc02f94 /* CAN Controller 0 Mailbox 28 Timestamp Register */
-#define CAN0_MB28_ID0 0xffc02f98 /* CAN Controller 0 Mailbox 28 ID0 Register */
-#define CAN0_MB28_ID1 0xffc02f9c /* CAN Controller 0 Mailbox 28 ID1 Register */
-#define CAN0_MB29_DATA0 0xffc02fa0 /* CAN Controller 0 Mailbox 29 Data 0 Register */
-#define CAN0_MB29_DATA1 0xffc02fa4 /* CAN Controller 0 Mailbox 29 Data 1 Register */
-#define CAN0_MB29_DATA2 0xffc02fa8 /* CAN Controller 0 Mailbox 29 Data 2 Register */
-#define CAN0_MB29_DATA3 0xffc02fac /* CAN Controller 0 Mailbox 29 Data 3 Register */
-#define CAN0_MB29_LENGTH 0xffc02fb0 /* CAN Controller 0 Mailbox 29 Length Register */
-#define CAN0_MB29_TIMESTAMP 0xffc02fb4 /* CAN Controller 0 Mailbox 29 Timestamp Register */
-#define CAN0_MB29_ID0 0xffc02fb8 /* CAN Controller 0 Mailbox 29 ID0 Register */
-#define CAN0_MB29_ID1 0xffc02fbc /* CAN Controller 0 Mailbox 29 ID1 Register */
-#define CAN0_MB30_DATA0 0xffc02fc0 /* CAN Controller 0 Mailbox 30 Data 0 Register */
-#define CAN0_MB30_DATA1 0xffc02fc4 /* CAN Controller 0 Mailbox 30 Data 1 Register */
-#define CAN0_MB30_DATA2 0xffc02fc8 /* CAN Controller 0 Mailbox 30 Data 2 Register */
-#define CAN0_MB30_DATA3 0xffc02fcc /* CAN Controller 0 Mailbox 30 Data 3 Register */
-#define CAN0_MB30_LENGTH 0xffc02fd0 /* CAN Controller 0 Mailbox 30 Length Register */
-#define CAN0_MB30_TIMESTAMP 0xffc02fd4 /* CAN Controller 0 Mailbox 30 Timestamp Register */
-#define CAN0_MB30_ID0 0xffc02fd8 /* CAN Controller 0 Mailbox 30 ID0 Register */
-#define CAN0_MB30_ID1 0xffc02fdc /* CAN Controller 0 Mailbox 30 ID1 Register */
-#define CAN0_MB31_DATA0 0xffc02fe0 /* CAN Controller 0 Mailbox 31 Data 0 Register */
-#define CAN0_MB31_DATA1 0xffc02fe4 /* CAN Controller 0 Mailbox 31 Data 1 Register */
-#define CAN0_MB31_DATA2 0xffc02fe8 /* CAN Controller 0 Mailbox 31 Data 2 Register */
-#define CAN0_MB31_DATA3 0xffc02fec /* CAN Controller 0 Mailbox 31 Data 3 Register */
-#define CAN0_MB31_LENGTH 0xffc02ff0 /* CAN Controller 0 Mailbox 31 Length Register */
-#define CAN0_MB31_TIMESTAMP 0xffc02ff4 /* CAN Controller 0 Mailbox 31 Timestamp Register */
-#define CAN0_MB31_ID0 0xffc02ff8 /* CAN Controller 0 Mailbox 31 ID0 Register */
-#define CAN0_MB31_ID1 0xffc02ffc /* CAN Controller 0 Mailbox 31 ID1 Register */
-
-/* UART3 Registers */
-
-#define UART3_DLL 0xffc03100 /* Divisor Latch Low Byte */
-#define UART3_DLH 0xffc03104 /* Divisor Latch High Byte */
-#define UART3_GCTL 0xffc03108 /* Global Control Register */
-#define UART3_LCR 0xffc0310c /* Line Control Register */
-#define UART3_MCR 0xffc03110 /* Modem Control Register */
-#define UART3_LSR 0xffc03114 /* Line Status Register */
-#define UART3_MSR 0xffc03118 /* Modem Status Register */
-#define UART3_SCR 0xffc0311c /* Scratch Register */
-#define UART3_IER_SET 0xffc03120 /* Interrupt Enable Register Set */
-#define UART3_IER_CLEAR 0xffc03124 /* Interrupt Enable Register Clear */
-#define UART3_THR 0xffc03128 /* Transmit Hold Register */
-#define UART3_RBR 0xffc0312c /* Receive Buffer Register */
-
-/* NFC Registers */
-
-#define NFC_CTL 0xffc03b00 /* NAND Control Register */
-#define NFC_STAT 0xffc03b04 /* NAND Status Register */
-#define NFC_IRQSTAT 0xffc03b08 /* NAND Interrupt Status Register */
-#define NFC_IRQMASK 0xffc03b0c /* NAND Interrupt Mask Register */
-#define NFC_ECC0 0xffc03b10 /* NAND ECC Register 0 */
-#define NFC_ECC1 0xffc03b14 /* NAND ECC Register 1 */
-#define NFC_ECC2 0xffc03b18 /* NAND ECC Register 2 */
-#define NFC_ECC3 0xffc03b1c /* NAND ECC Register 3 */
-#define NFC_COUNT 0xffc03b20 /* NAND ECC Count Register */
-#define NFC_RST 0xffc03b24 /* NAND ECC Reset Register */
-#define NFC_PGCTL 0xffc03b28 /* NAND Page Control Register */
-#define NFC_READ 0xffc03b2c /* NAND Read Data Register */
-#define NFC_ADDR 0xffc03b40 /* NAND Address Register */
-#define NFC_CMD 0xffc03b44 /* NAND Command Register */
-#define NFC_DATA_WR 0xffc03b48 /* NAND Data Write Register */
-#define NFC_DATA_RD 0xffc03b4c /* NAND Data Read Register */
-
-/* Counter Registers */
-
-#define CNT_CONFIG 0xffc04200 /* Configuration Register */
-#define CNT_IMASK 0xffc04204 /* Interrupt Mask Register */
-#define CNT_STATUS 0xffc04208 /* Status Register */
-#define CNT_COMMAND 0xffc0420c /* Command Register */
-#define CNT_DEBOUNCE 0xffc04210 /* Debounce Register */
-#define CNT_COUNTER 0xffc04214 /* Counter Register */
-#define CNT_MAX 0xffc04218 /* Maximal Count Register */
-#define CNT_MIN 0xffc0421c /* Minimal Count Register */
-
-/* OTP/FUSE Registers */
-
-#define OTP_CONTROL 0xffc04300 /* OTP/Fuse Control Register */
-#define OTP_BEN 0xffc04304 /* OTP/Fuse Byte Enable */
-#define OTP_STATUS 0xffc04308 /* OTP/Fuse Status */
-#define OTP_TIMING 0xffc0430c /* OTP/Fuse Access Timing */
-
-/* Security Registers */
-
-#define SECURE_SYSSWT 0xffc04320 /* Secure System Switches */
-#define SECURE_CONTROL 0xffc04324 /* Secure Control */
-#define SECURE_STATUS 0xffc04328 /* Secure Status */
-
-/* DMA Peripheral Mux Register */
-
-#define DMAC1_PERIMUX 0xffc04340 /* DMA Controller 1 Peripheral Multiplexer Register */
-
-/* OTP Read/Write Data Buffer Registers */
-
-#define OTP_DATA0 0xffc04380 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA1 0xffc04384 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA2 0xffc04388 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA3 0xffc0438c /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-
-/* Handshake MDMA is not defined in the shared file because it is not available on the ADSP-BF542 processor */
-
-/* ********************************************************** */
-/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
-/* and MULTI BIT READ MACROS */
-/* ********************************************************** */
-
-/* SIC_IMASK Masks */
-#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
-#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
-#define SIC_MASK(x) (1 << (x)) /* Mask Peripheral #x interrupt */
-#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */
-
-/* SIC_IWR Masks */
-#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
-#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
-#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */
-#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */
-
-/* Bit masks for SIC_IAR0 */
-
-#define PLL_WAKEUP 0x1 /* PLL Wakeup */
-
-/* Bit masks for SIC_IWR0, SIC_IMASK0, SIC_ISR0 */
-
-#define DMA0_ERR 0x2 /* DMA Controller 0 Error */
-#define EPPI0_ERR 0x4 /* EPPI0 Error */
-#define SPORT0_ERR 0x8 /* SPORT0 Error */
-#define SPORT1_ERR 0x10 /* SPORT1 Error */
-#define SPI0_ERR 0x20 /* SPI0 Error */
-#define UART0_ERR 0x40 /* UART0 Error */
-#define RTC 0x80 /* Real-Time Clock */
-#define DMA12 0x100 /* DMA Channel 12 */
-#define DMA0 0x200 /* DMA Channel 0 */
-#define DMA1 0x400 /* DMA Channel 1 */
-#define DMA2 0x800 /* DMA Channel 2 */
-#define DMA3 0x1000 /* DMA Channel 3 */
-#define DMA4 0x2000 /* DMA Channel 4 */
-#define DMA6 0x4000 /* DMA Channel 6 */
-#define DMA7 0x8000 /* DMA Channel 7 */
-#define PINT0 0x80000 /* Pin Interrupt 0 */
-#define PINT1 0x100000 /* Pin Interrupt 1 */
-#define MDMA0 0x200000 /* Memory DMA Stream 0 */
-#define MDMA1 0x400000 /* Memory DMA Stream 1 */
-#define WDOG 0x800000 /* Watchdog Timer */
-#define DMA1_ERR 0x1000000 /* DMA Controller 1 Error */
-#define SPORT2_ERR 0x2000000 /* SPORT2 Error */
-#define SPORT3_ERR 0x4000000 /* SPORT3 Error */
-#define MXVR_SD 0x8000000 /* MXVR Synchronous Data */
-#define SPI1_ERR 0x10000000 /* SPI1 Error */
-#define SPI2_ERR 0x20000000 /* SPI2 Error */
-#define UART1_ERR 0x40000000 /* UART1 Error */
-#define UART2_ERR 0x80000000 /* UART2 Error */
-
-/* Bit masks for SIC_IWR1, SIC_IMASK1, SIC_ISR1 */
-
-#define CAN0_ERR 0x1 /* CAN0 Error */
-#define DMA18 0x2 /* DMA Channel 18 */
-#define DMA19 0x4 /* DMA Channel 19 */
-#define DMA20 0x8 /* DMA Channel 20 */
-#define DMA21 0x10 /* DMA Channel 21 */
-#define DMA13 0x20 /* DMA Channel 13 */
-#define DMA14 0x40 /* DMA Channel 14 */
-#define DMA5 0x80 /* DMA Channel 5 */
-#define DMA23 0x100 /* DMA Channel 23 */
-#define DMA8 0x200 /* DMA Channel 8 */
-#define DMA9 0x400 /* DMA Channel 9 */
-#define DMA10 0x800 /* DMA Channel 10 */
-#define DMA11 0x1000 /* DMA Channel 11 */
-#define TWI0 0x2000 /* TWI0 */
-#define TWI1 0x4000 /* TWI1 */
-#define CAN0_RX 0x8000 /* CAN0 Receive */
-#define CAN0_TX 0x10000 /* CAN0 Transmit */
-#define MDMA2 0x20000 /* Memory DMA Stream 0 */
-#define MDMA3 0x40000 /* Memory DMA Stream 1 */
-#define MXVR_STAT 0x80000 /* MXVR Status */
-#define MXVR_CM 0x100000 /* MXVR Control Message */
-#define MXVR_AP 0x200000 /* MXVR Asynchronous Packet */
-#define EPPI1_ERR 0x400000 /* EPPI1 Error */
-#define EPPI2_ERR 0x800000 /* EPPI2 Error */
-#define UART3_ERR 0x1000000 /* UART3 Error */
-#define HOST_ERR 0x2000000 /* Host DMA Port Error */
-#define USB_ERR 0x4000000 /* USB Error */
-#define PIXC_ERR 0x8000000 /* Pixel Compositor Error */
-#define NFC_ERR 0x10000000 /* Nand Flash Controller Error */
-#define ATAPI_ERR 0x20000000 /* ATAPI Error */
-#define CAN1_ERR 0x40000000 /* CAN1 Error */
-#define DMAR0_ERR 0x80000000 /* DMAR0 Overflow Error */
-#define DMAR1_ERR 0x80000000 /* DMAR1 Overflow Error */
-#define DMAR0 0x80000000 /* DMAR0 Block */
-#define DMAR1 0x80000000 /* DMAR1 Block */
-
-/* Bit masks for SIC_IWR2, SIC_IMASK2, SIC_ISR2 */
-
-#define DMA15 0x1 /* DMA Channel 15 */
-#define DMA16 0x2 /* DMA Channel 16 */
-#define DMA17 0x4 /* DMA Channel 17 */
-#define DMA22 0x8 /* DMA Channel 22 */
-#define CNT 0x10 /* Counter */
-#define KEY 0x20 /* Keypad */
-#define CAN1_RX 0x40 /* CAN1 Receive */
-#define CAN1_TX 0x80 /* CAN1 Transmit */
-#define SDH_INT_MASK0 0x100 /* SDH Mask 0 */
-#define SDH_INT_MASK1 0x200 /* SDH Mask 1 */
-#define USB_EINT 0x400 /* USB Exception */
-#define USB_INT0 0x800 /* USB Interrupt 0 */
-#define USB_INT1 0x1000 /* USB Interrupt 1 */
-#define USB_INT2 0x2000 /* USB Interrupt 2 */
-#define USB_DMAINT 0x4000 /* USB DMA */
-#define OTPSEC 0x8000 /* OTP Access Complete */
-#define TIMER0 0x400000 /* Timer 0 */
-#define TIMER1 0x800000 /* Timer 1 */
-#define TIMER2 0x1000000 /* Timer 2 */
-#define TIMER3 0x2000000 /* Timer 3 */
-#define TIMER4 0x4000000 /* Timer 4 */
-#define TIMER5 0x8000000 /* Timer 5 */
-#define TIMER6 0x10000000 /* Timer 6 */
-#define TIMER7 0x20000000 /* Timer 7 */
-#define PINT2 0x40000000 /* Pin Interrupt 2 */
-#define PINT3 0x80000000 /* Pin Interrupt 3 */
-
-/* Bit masks for DMAx_PERIPHERAL_MAP, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */
-
-#define CTYPE 0x40 /* DMA Channel Type */
-#define PMAP 0xf000 /* Peripheral Mapped To This Channel */
-
-/* Bit masks for DMACx_TC_PER */
-
-#define DCB_TRAFFIC_PERIOD 0xf /* DCB Traffic Control Period */
-#define DEB_TRAFFIC_PERIOD 0xf0 /* DEB Traffic Control Period */
-#define DAB_TRAFFIC_PERIOD 0x700 /* DAB Traffic Control Period */
-#define MDMA_ROUND_ROBIN_PERIOD 0xf800 /* MDMA Round Robin Period */
-
-/* Bit masks for DMACx_TC_CNT */
-
-#define DCB_TRAFFIC_COUNT 0xf /* DCB Traffic Control Count */
-#define DEB_TRAFFIC_COUNT 0xf0 /* DEB Traffic Control Count */
-#define DAB_TRAFFIC_COUNT 0x700 /* DAB Traffic Control Count */
-#define MDMA_ROUND_ROBIN_COUNT 0xf800 /* MDMA Round Robin Count */
-
-/* Bit masks for DMAC1_PERIMUX */
-
-#define PMUXSDH 0x1 /* Peripheral Select for DMA22 channel */
-
-/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/
-/* EBIU_AMGCTL Masks */
-#define AMCKEN 0x0001 /* Enable CLKOUT */
-#define AMBEN_NONE 0x0000 /* All Banks Disabled */
-#define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */
-#define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */
-#define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */
-#define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */
-
-
-/* Bit masks for EBIU_AMBCTL0 */
-
-#define B0RDYEN 0x1 /* Bank 0 ARDY Enable */
-#define B0RDYPOL 0x2 /* Bank 0 ARDY Polarity */
-#define B0TT 0xc /* Bank 0 transition time */
-#define B0ST 0x30 /* Bank 0 Setup time */
-#define B0HT 0xc0 /* Bank 0 Hold time */
-#define B0RAT 0xf00 /* Bank 0 Read access time */
-#define B0WAT 0xf000 /* Bank 0 write access time */
-#define B1RDYEN 0x10000 /* Bank 1 ARDY Enable */
-#define B1RDYPOL 0x20000 /* Bank 1 ARDY Polarity */
-#define B1TT 0xc0000 /* Bank 1 transition time */
-#define B1ST 0x300000 /* Bank 1 Setup time */
-#define B1HT 0xc00000 /* Bank 1 Hold time */
-#define B1RAT 0xf000000 /* Bank 1 Read access time */
-#define B1WAT 0xf0000000 /* Bank 1 write access time */
-
-/* Bit masks for EBIU_AMBCTL1 */
-
-#define B2RDYEN 0x1 /* Bank 2 ARDY Enable */
-#define B2RDYPOL 0x2 /* Bank 2 ARDY Polarity */
-#define B2TT 0xc /* Bank 2 transition time */
-#define B2ST 0x30 /* Bank 2 Setup time */
-#define B2HT 0xc0 /* Bank 2 Hold time */
-#define B2RAT 0xf00 /* Bank 2 Read access time */
-#define B2WAT 0xf000 /* Bank 2 write access time */
-#define B3RDYEN 0x10000 /* Bank 3 ARDY Enable */
-#define B3RDYPOL 0x20000 /* Bank 3 ARDY Polarity */
-#define B3TT 0xc0000 /* Bank 3 transition time */
-#define B3ST 0x300000 /* Bank 3 Setup time */
-#define B3HT 0xc00000 /* Bank 3 Hold time */
-#define B3RAT 0xf000000 /* Bank 3 Read access time */
-#define B3WAT 0xf0000000 /* Bank 3 write access time */
-
-/* Bit masks for EBIU_MBSCTL */
-
-#define AMSB0CTL 0x3 /* Async Memory Bank 0 select */
-#define AMSB1CTL 0xc /* Async Memory Bank 1 select */
-#define AMSB2CTL 0x30 /* Async Memory Bank 2 select */
-#define AMSB3CTL 0xc0 /* Async Memory Bank 3 select */
-
-/* Bit masks for EBIU_MODE */
-
-#define B0MODE 0x3 /* Async Memory Bank 0 Access Mode */
-#define B1MODE 0xc /* Async Memory Bank 1 Access Mode */
-#define B2MODE 0x30 /* Async Memory Bank 2 Access Mode */
-#define B3MODE 0xc0 /* Async Memory Bank 3 Access Mode */
-
-/* Bit masks for EBIU_FCTL */
-
-#define TESTSETLOCK 0x1 /* Test set lock */
-#define BCLK 0x6 /* Burst clock frequency */
-#define PGWS 0x38 /* Page wait states */
-#define PGSZ 0x40 /* Page size */
-#define RDDL 0x380 /* Read data delay */
-
-/* Bit masks for EBIU_ARBSTAT */
-
-#define ARBSTAT 0x1 /* Arbitration status */
-#define BGSTAT 0x2 /* Bus grant status */
-
-/* Bit masks for EBIU_DDRCTL0 */
-
-#define TREFI 0x3fff /* Refresh Interval */
-#define TRFC 0x3c000 /* Auto-refresh command period */
-#define TRP 0x3c0000 /* Pre charge-to-active command period */
-#define TRAS 0x3c00000 /* Min Active-to-pre charge time */
-#define TRC 0x3c000000 /* Active-to-active time */
-#define DDR_TRAS(x) ((x<<22)&TRAS) /* DDR tRAS = (1~15) cycles */
-#define DDR_TRP(x) ((x<<18)&TRP) /* DDR tRP = (1~15) cycles */
-#define DDR_TRC(x) ((x<<26)&TRC) /* DDR tRC = (1~15) cycles */
-#define DDR_TRFC(x) ((x<<14)&TRFC) /* DDR tRFC = (1~15) cycles */
-#define DDR_TREFI(x) (x&TREFI) /* DDR tRFC = (1~15) cycles */
-
-/* Bit masks for EBIU_DDRCTL1 */
-
-#define TRCD 0xf /* Active-to-Read/write delay */
-#define TMRD 0xf0 /* Mode register set to active */
-#define TWR 0x300 /* Write Recovery time */
-#define DDRDATWIDTH 0x3000 /* DDR data width */
-#define EXTBANKS 0xc000 /* External banks */
-#define DDRDEVWIDTH 0x30000 /* DDR device width */
-#define DDRDEVSIZE 0xc0000 /* DDR device size */
-#define TWTR 0xf0000000 /* Write-to-read delay */
-#define DDR_TWTR(x) ((x<<28)&TWTR) /* DDR tWTR = (1~15) cycles */
-#define DDR_TMRD(x) ((x<<4)&TMRD) /* DDR tMRD = (1~15) cycles */
-#define DDR_TWR(x) ((x<<8)&TWR) /* DDR tWR = (1~15) cycles */
-#define DDR_TRCD(x) (x&TRCD) /* DDR tRCD = (1~15) cycles */
-#define DDR_DATWIDTH 0x2000 /* DDR data width */
-#define EXTBANK_1 0 /* 1 external bank */
-#define EXTBANK_2 0x4000 /* 2 external banks */
-#define DEVSZ_64 0x40000 /* DDR External Bank Size = 64MB */
-#define DEVSZ_128 0x80000 /* DDR External Bank Size = 128MB */
-#define DEVSZ_256 0xc0000 /* DDR External Bank Size = 256MB */
-#define DEVSZ_512 0 /* DDR External Bank Size = 512MB */
-#define DEVWD_4 0 /* DDR Device Width = 4 Bits */
-#define DEVWD_8 0x10000 /* DDR Device Width = 8 Bits */
-#define DEVWD_16 0x20000 /* DDR Device Width = 16 Bits */
-
-/* Bit masks for EBIU_DDRCTL2 */
-
-#define BURSTLENGTH 0x7 /* Burst length */
-#define CASLATENCY 0x70 /* CAS latency */
-#define DLLRESET 0x100 /* DLL Reset */
-#define REGE 0x1000 /* Register mode enable */
-#define CL_1_5 0x50 /* DDR CAS Latency = 1.5 cycles */
-#define CL_2 0x20 /* DDR CAS Latency = 2 cycles */
-#define CL_2_5 0x60 /* DDR CAS Latency = 2.5 cycles */
-#define CL_3 0x30 /* DDR CAS Latency = 3 cycles */
-
-/* Bit masks for EBIU_DDRCTL3 */
-
-#define PASR 0x7 /* Partial array self-refresh */
-
-/* Bit masks for EBIU_DDRQUE */
-
-#define DEB1_PFLEN 0x3 /* Pre fetch length for DEB1 accesses */
-#define DEB2_PFLEN 0xc /* Pre fetch length for DEB2 accesses */
-#define DEB3_PFLEN 0x30 /* Pre fetch length for DEB3 accesses */
-#define DEB_ARB_PRIORITY 0x700 /* Arbitration between DEB busses */
-#define DEB1_URGENT 0x1000 /* DEB1 Urgent */
-#define DEB2_URGENT 0x2000 /* DEB2 Urgent */
-#define DEB3_URGENT 0x4000 /* DEB3 Urgent */
-
-/* Bit masks for EBIU_ERRMST */
-
-#define DEB1_ERROR 0x1 /* DEB1 Error */
-#define DEB2_ERROR 0x2 /* DEB2 Error */
-#define DEB3_ERROR 0x4 /* DEB3 Error */
-#define CORE_ERROR 0x8 /* Core error */
-#define DEB_MERROR 0x10 /* DEB1 Error (2nd) */
-#define DEB2_MERROR 0x20 /* DEB2 Error (2nd) */
-#define DEB3_MERROR 0x40 /* DEB3 Error (2nd) */
-#define CORE_MERROR 0x80 /* Core Error (2nd) */
-
-/* Bit masks for EBIU_RSTCTL */
-
-#define DDRSRESET 0x1 /* DDR soft reset */
-#define PFTCHSRESET 0x4 /* DDR prefetch reset */
-#define SRREQ 0x8 /* Self-refresh request */
-#define SRACK 0x10 /* Self-refresh acknowledge */
-#define MDDRENABLE 0x20 /* Mobile DDR enable */
-
-/* Bit masks for EBIU_DDRMCEN */
-
-#define B0WCENABLE 0x1 /* Bank 0 write count enable */
-#define B1WCENABLE 0x2 /* Bank 1 write count enable */
-#define B2WCENABLE 0x4 /* Bank 2 write count enable */
-#define B3WCENABLE 0x8 /* Bank 3 write count enable */
-#define B4WCENABLE 0x10 /* Bank 4 write count enable */
-#define B5WCENABLE 0x20 /* Bank 5 write count enable */
-#define B6WCENABLE 0x40 /* Bank 6 write count enable */
-#define B7WCENABLE 0x80 /* Bank 7 write count enable */
-#define B0RCENABLE 0x100 /* Bank 0 read count enable */
-#define B1RCENABLE 0x200 /* Bank 1 read count enable */
-#define B2RCENABLE 0x400 /* Bank 2 read count enable */
-#define B3RCENABLE 0x800 /* Bank 3 read count enable */
-#define B4RCENABLE 0x1000 /* Bank 4 read count enable */
-#define B5RCENABLE 0x2000 /* Bank 5 read count enable */
-#define B6RCENABLE 0x4000 /* Bank 6 read count enable */
-#define B7RCENABLE 0x8000 /* Bank 7 read count enable */
-#define ROWACTCENABLE 0x10000 /* DDR Row activate count enable */
-#define RWTCENABLE 0x20000 /* DDR R/W Turn around count enable */
-#define ARCENABLE 0x40000 /* DDR Auto-refresh count enable */
-#define GC0ENABLE 0x100000 /* DDR Grant count 0 enable */
-#define GC1ENABLE 0x200000 /* DDR Grant count 1 enable */
-#define GC2ENABLE 0x400000 /* DDR Grant count 2 enable */
-#define GC3ENABLE 0x800000 /* DDR Grant count 3 enable */
-#define GCCONTROL 0x3000000 /* DDR Grant Count Control */
-
-/* Bit masks for EBIU_DDRMCCL */
-
-#define CB0WCOUNT 0x1 /* Clear write count 0 */
-#define CB1WCOUNT 0x2 /* Clear write count 1 */
-#define CB2WCOUNT 0x4 /* Clear write count 2 */
-#define CB3WCOUNT 0x8 /* Clear write count 3 */
-#define CB4WCOUNT 0x10 /* Clear write count 4 */
-#define CB5WCOUNT 0x20 /* Clear write count 5 */
-#define CB6WCOUNT 0x40 /* Clear write count 6 */
-#define CB7WCOUNT 0x80 /* Clear write count 7 */
-#define CBRCOUNT 0x100 /* Clear read count 0 */
-#define CB1RCOUNT 0x200 /* Clear read count 1 */
-#define CB2RCOUNT 0x400 /* Clear read count 2 */
-#define CB3RCOUNT 0x800 /* Clear read count 3 */
-#define CB4RCOUNT 0x1000 /* Clear read count 4 */
-#define CB5RCOUNT 0x2000 /* Clear read count 5 */
-#define CB6RCOUNT 0x4000 /* Clear read count 6 */
-#define CB7RCOUNT 0x8000 /* Clear read count 7 */
-#define CRACOUNT 0x10000 /* Clear row activation count */
-#define CRWTACOUNT 0x20000 /* Clear R/W turn-around count */
-#define CARCOUNT 0x40000 /* Clear auto-refresh count */
-#define CG0COUNT 0x100000 /* Clear grant count 0 */
-#define CG1COUNT 0x200000 /* Clear grant count 1 */
-#define CG2COUNT 0x400000 /* Clear grant count 2 */
-#define CG3COUNT 0x800000 /* Clear grant count 3 */
-
-/* Bit masks for (PORTx is PORTA - PORTJ) includes PORTx_FER, PORTx_SET, PORTx_CLEAR, PORTx_DIR_SET, PORTx_DIR_CLEAR, PORTx_INEN */
-
-#define Px0 0x1 /* GPIO 0 */
-#define Px1 0x2 /* GPIO 1 */
-#define Px2 0x4 /* GPIO 2 */
-#define Px3 0x8 /* GPIO 3 */
-#define Px4 0x10 /* GPIO 4 */
-#define Px5 0x20 /* GPIO 5 */
-#define Px6 0x40 /* GPIO 6 */
-#define Px7 0x80 /* GPIO 7 */
-#define Px8 0x100 /* GPIO 8 */
-#define Px9 0x200 /* GPIO 9 */
-#define Px10 0x400 /* GPIO 10 */
-#define Px11 0x800 /* GPIO 11 */
-#define Px12 0x1000 /* GPIO 12 */
-#define Px13 0x2000 /* GPIO 13 */
-#define Px14 0x4000 /* GPIO 14 */
-#define Px15 0x8000 /* GPIO 15 */
-
-/* Bit masks for PORTA_MUX - PORTJ_MUX */
-
-#define PxM0 0x3 /* GPIO Mux 0 */
-#define PxM1 0xc /* GPIO Mux 1 */
-#define PxM2 0x30 /* GPIO Mux 2 */
-#define PxM3 0xc0 /* GPIO Mux 3 */
-#define PxM4 0x300 /* GPIO Mux 4 */
-#define PxM5 0xc00 /* GPIO Mux 5 */
-#define PxM6 0x3000 /* GPIO Mux 6 */
-#define PxM7 0xc000 /* GPIO Mux 7 */
-#define PxM8 0x30000 /* GPIO Mux 8 */
-#define PxM9 0xc0000 /* GPIO Mux 9 */
-#define PxM10 0x300000 /* GPIO Mux 10 */
-#define PxM11 0xc00000 /* GPIO Mux 11 */
-#define PxM12 0x3000000 /* GPIO Mux 12 */
-#define PxM13 0xc000000 /* GPIO Mux 13 */
-#define PxM14 0x30000000 /* GPIO Mux 14 */
-#define PxM15 0xc0000000 /* GPIO Mux 15 */
-
-
-/* Bit masks for PINTx_MASK_SET/CLEAR, PINTx_REQUEST, PINTx_LATCH, PINTx_EDGE_SET/CLEAR, PINTx_INVERT_SET/CLEAR, PINTx_PINTSTATE */
-
-#define IB0 0x1 /* Interrupt Bit 0 */
-#define IB1 0x2 /* Interrupt Bit 1 */
-#define IB2 0x4 /* Interrupt Bit 2 */
-#define IB3 0x8 /* Interrupt Bit 3 */
-#define IB4 0x10 /* Interrupt Bit 4 */
-#define IB5 0x20 /* Interrupt Bit 5 */
-#define IB6 0x40 /* Interrupt Bit 6 */
-#define IB7 0x80 /* Interrupt Bit 7 */
-#define IB8 0x100 /* Interrupt Bit 8 */
-#define IB9 0x200 /* Interrupt Bit 9 */
-#define IB10 0x400 /* Interrupt Bit 10 */
-#define IB11 0x800 /* Interrupt Bit 11 */
-#define IB12 0x1000 /* Interrupt Bit 12 */
-#define IB13 0x2000 /* Interrupt Bit 13 */
-#define IB14 0x4000 /* Interrupt Bit 14 */
-#define IB15 0x8000 /* Interrupt Bit 15 */
-
-/* Bit masks for TIMERx_CONFIG */
-
-#define TMODE 0x3 /* Timer Mode */
-#define PULSE_HI 0x4 /* Pulse Polarity */
-#define PERIOD_CNT 0x8 /* Period Count */
-#define IRQ_ENA 0x10 /* Interrupt Request Enable */
-#define TIN_SEL 0x20 /* Timer Input Select */
-#define OUT_DIS 0x40 /* Output Pad Disable */
-#define CLK_SEL 0x80 /* Timer Clock Select */
-#define TOGGLE_HI 0x100 /* Toggle Mode */
-#define EMU_RUN 0x200 /* Emulation Behavior Select */
-#define ERR_TYP 0xc000 /* Error Type */
-
-/* Bit masks for TIMER_ENABLE0 */
-
-#define TIMEN0 0x1 /* Timer 0 Enable */
-#define TIMEN1 0x2 /* Timer 1 Enable */
-#define TIMEN2 0x4 /* Timer 2 Enable */
-#define TIMEN3 0x8 /* Timer 3 Enable */
-#define TIMEN4 0x10 /* Timer 4 Enable */
-#define TIMEN5 0x20 /* Timer 5 Enable */
-#define TIMEN6 0x40 /* Timer 6 Enable */
-#define TIMEN7 0x80 /* Timer 7 Enable */
-
-/* Bit masks for TIMER_DISABLE0 */
-
-#define TIMDIS0 0x1 /* Timer 0 Disable */
-#define TIMDIS1 0x2 /* Timer 1 Disable */
-#define TIMDIS2 0x4 /* Timer 2 Disable */
-#define TIMDIS3 0x8 /* Timer 3 Disable */
-#define TIMDIS4 0x10 /* Timer 4 Disable */
-#define TIMDIS5 0x20 /* Timer 5 Disable */
-#define TIMDIS6 0x40 /* Timer 6 Disable */
-#define TIMDIS7 0x80 /* Timer 7 Disable */
-
-/* Bit masks for TIMER_STATUS0 */
-
-#define TIMIL0 0x1 /* Timer 0 Interrupt */
-#define TIMIL1 0x2 /* Timer 1 Interrupt */
-#define TIMIL2 0x4 /* Timer 2 Interrupt */
-#define TIMIL3 0x8 /* Timer 3 Interrupt */
-#define TOVF_ERR0 0x10 /* Timer 0 Counter Overflow */
-#define TOVF_ERR1 0x20 /* Timer 1 Counter Overflow */
-#define TOVF_ERR2 0x40 /* Timer 2 Counter Overflow */
-#define TOVF_ERR3 0x80 /* Timer 3 Counter Overflow */
-#define TRUN0 0x1000 /* Timer 0 Slave Enable Status */
-#define TRUN1 0x2000 /* Timer 1 Slave Enable Status */
-#define TRUN2 0x4000 /* Timer 2 Slave Enable Status */
-#define TRUN3 0x8000 /* Timer 3 Slave Enable Status */
-#define TIMIL4 0x10000 /* Timer 4 Interrupt */
-#define TIMIL5 0x20000 /* Timer 5 Interrupt */
-#define TIMIL6 0x40000 /* Timer 6 Interrupt */
-#define TIMIL7 0x80000 /* Timer 7 Interrupt */
-#define TOVF_ERR4 0x100000 /* Timer 4 Counter Overflow */
-#define TOVF_ERR5 0x200000 /* Timer 5 Counter Overflow */
-#define TOVF_ERR6 0x400000 /* Timer 6 Counter Overflow */
-#define TOVF_ERR7 0x800000 /* Timer 7 Counter Overflow */
-#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */
-#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */
-#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */
-#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */
-
-/* Bit masks for SECURE_SYSSWT */
-
-#define EMUDABL 0x1 /* Emulation Disable. */
-#define RSTDABL 0x2 /* Reset Disable */
-#define L1IDABL 0x1c /* L1 Instruction Memory Disable. */
-#define L1DADABL 0xe0 /* L1 Data Bank A Memory Disable. */
-#define L1DBDABL 0x700 /* L1 Data Bank B Memory Disable. */
-#define DMA0OVR 0x800 /* DMA0 Memory Access Override */
-#define DMA1OVR 0x1000 /* DMA1 Memory Access Override */
-#define EMUOVR 0x4000 /* Emulation Override */
-#define OTPSEN 0x8000 /* OTP Secrets Enable. */
-#define L2DABL 0x70000 /* L2 Memory Disable. */
-
-/* Bit masks for SECURE_CONTROL */
-
-#define SECURE0 0x1 /* SECURE 0 */
-#define SECURE1 0x2 /* SECURE 1 */
-#define SECURE2 0x4 /* SECURE 2 */
-#define SECURE3 0x8 /* SECURE 3 */
-
-/* Bit masks for SECURE_STATUS */
-
-#define SECMODE 0x3 /* Secured Mode Control State */
-#define NMI 0x4 /* Non Maskable Interrupt */
-#define AFVALID 0x8 /* Authentication Firmware Valid */
-#define AFEXIT 0x10 /* Authentication Firmware Exit */
-#define SECSTAT 0xe0 /* Secure Status */
-
-/* SWRST Masks */
-#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
-#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
-#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
-#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
-#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
-
-/* Bit masks for EPPIx_STATUS */
-
-#define CFIFO_ERR 0x1 /* Chroma FIFO Error */
-#define YFIFO_ERR 0x2 /* Luma FIFO Error */
-#define LTERR_OVR 0x4 /* Line Track Overflow */
-#define LTERR_UNDR 0x8 /* Line Track Underflow */
-#define FTERR_OVR 0x10 /* Frame Track Overflow */
-#define FTERR_UNDR 0x20 /* Frame Track Underflow */
-#define ERR_NCOR 0x40 /* Preamble Error Not Corrected */
-#define DMA1URQ 0x80 /* DMA1 Urgent Request */
-#define DMA0URQ 0x100 /* DMA0 Urgent Request */
-#define ERR_DET 0x4000 /* Preamble Error Detected */
-#define FLD 0x8000 /* Field */
-
-/* Bit masks for EPPIx_CONTROL */
-
-#define EPPI_EN 0x1 /* Enable */
-#define EPPI_DIR 0x2 /* Direction */
-#define XFR_TYPE 0xc /* Operating Mode */
-#define FS_CFG 0x30 /* Frame Sync Configuration */
-#define FLD_SEL 0x40 /* Field Select/Trigger */
-#define ITU_TYPE 0x80 /* ITU Interlaced or Progressive */
-#define BLANKGEN 0x100 /* ITU Output Mode with Internal Blanking Generation */
-#define ICLKGEN 0x200 /* Internal Clock Generation */
-#define IFSGEN 0x400 /* Internal Frame Sync Generation */
-#define POLC 0x1800 /* Frame Sync and Data Driving/Sampling Edges */
-#define POLS 0x6000 /* Frame Sync Polarity */
-#define DLENGTH 0x38000 /* Data Length */
-#define SKIP_EN 0x40000 /* Skip Enable */
-#define SKIP_EO 0x80000 /* Skip Even or Odd */
-#define PACKEN 0x100000 /* Packing/Unpacking Enable */
-#define SWAPEN 0x200000 /* Swap Enable */
-#define SIGN_EXT 0x400000 /* Sign Extension or Zero-filled / Data Split Format */
-#define SPLT_EVEN_ODD 0x800000 /* Split Even and Odd Data Samples */
-#define SUBSPLT_ODD 0x1000000 /* Sub-split Odd Samples */
-#define DMACFG 0x2000000 /* One or Two DMA Channels Mode */
-#define RGB_FMT_EN 0x4000000 /* RGB Formatting Enable */
-#define FIFO_RWM 0x18000000 /* FIFO Regular Watermarks */
-#define FIFO_UWM 0x60000000 /* FIFO Urgent Watermarks */
-
-#define DLEN_8 (0 << 15) /* 000 - 8 bits */
-#define DLEN_10 (1 << 15) /* 001 - 10 bits */
-#define DLEN_12 (2 << 15) /* 010 - 12 bits */
-#define DLEN_14 (3 << 15) /* 011 - 14 bits */
-#define DLEN_16 (4 << 15) /* 100 - 16 bits */
-#define DLEN_18 (5 << 15) /* 101 - 18 bits */
-#define DLEN_24 (6 << 15) /* 110 - 24 bits */
-
-
-/* Bit masks for EPPIx_FS2W_LVB */
-
-#define F1VB_BD 0xff /* Vertical Blanking before Field 1 Active Data */
-#define F1VB_AD 0xff00 /* Vertical Blanking after Field 1 Active Data */
-#define F2VB_BD 0xff0000 /* Vertical Blanking before Field 2 Active Data */
-#define F2VB_AD 0xff000000 /* Vertical Blanking after Field 2 Active Data */
-
-/* Bit masks for EPPIx_FS2W_LAVF */
-
-#define F1_ACT 0xffff /* Number of Lines of Active Data in Field 1 */
-#define F2_ACT 0xffff0000 /* Number of Lines of Active Data in Field 2 */
-
-/* Bit masks for EPPIx_CLIP */
-
-#define LOW_ODD 0xff /* Lower Limit for Odd Bytes (Chroma) */
-#define HIGH_ODD 0xff00 /* Upper Limit for Odd Bytes (Chroma) */
-#define LOW_EVEN 0xff0000 /* Lower Limit for Even Bytes (Luma) */
-#define HIGH_EVEN 0xff000000 /* Upper Limit for Even Bytes (Luma) */
-
-
-/* ******************************************* */
-/* MULTI BIT MACRO ENUMERATIONS */
-/* ******************************************* */
-
-/* BCODE bit field options (SYSCFG register) */
-
-#define BCODE_WAKEUP 0x0000 /* boot according to wake-up condition */
-#define BCODE_FULLBOOT 0x0010 /* always perform full boot */
-#define BCODE_QUICKBOOT 0x0020 /* always perform quick boot */
-#define BCODE_NOBOOT 0x0030 /* always perform full boot */
-
-/* TMODE in TIMERx_CONFIG bit field options */
-
-#define PWM_OUT 0x0001
-#define WDTH_CAP 0x0002
-#define EXT_CLK 0x0003
-
-/* PINTx Register Bit Definitions */
-
-#define PIQ0 0x00000001
-#define PIQ1 0x00000002
-#define PIQ2 0x00000004
-#define PIQ3 0x00000008
-
-#define PIQ4 0x00000010
-#define PIQ5 0x00000020
-#define PIQ6 0x00000040
-#define PIQ7 0x00000080
-
-#define PIQ8 0x00000100
-#define PIQ9 0x00000200
-#define PIQ10 0x00000400
-#define PIQ11 0x00000800
-
-#define PIQ12 0x00001000
-#define PIQ13 0x00002000
-#define PIQ14 0x00004000
-#define PIQ15 0x00008000
-
-#define PIQ16 0x00010000
-#define PIQ17 0x00020000
-#define PIQ18 0x00040000
-#define PIQ19 0x00080000
-
-#define PIQ20 0x00100000
-#define PIQ21 0x00200000
-#define PIQ22 0x00400000
-#define PIQ23 0x00800000
-
-#define PIQ24 0x01000000
-#define PIQ25 0x02000000
-#define PIQ26 0x04000000
-#define PIQ27 0x08000000
-
-#define PIQ28 0x10000000
-#define PIQ29 0x20000000
-#define PIQ30 0x40000000
-#define PIQ31 0x80000000
-
-/* Port Muxing Bit Fields for PORTx_MUX Registers */
-
-#define MUX0 0x00000003
-#define MUX0_0 0x00000000
-#define MUX0_1 0x00000001
-#define MUX0_2 0x00000002
-#define MUX0_3 0x00000003
-
-#define MUX1 0x0000000C
-#define MUX1_0 0x00000000
-#define MUX1_1 0x00000004
-#define MUX1_2 0x00000008
-#define MUX1_3 0x0000000C
-
-#define MUX2 0x00000030
-#define MUX2_0 0x00000000
-#define MUX2_1 0x00000010
-#define MUX2_2 0x00000020
-#define MUX2_3 0x00000030
-
-#define MUX3 0x000000C0
-#define MUX3_0 0x00000000
-#define MUX3_1 0x00000040
-#define MUX3_2 0x00000080
-#define MUX3_3 0x000000C0
-
-#define MUX4 0x00000300
-#define MUX4_0 0x00000000
-#define MUX4_1 0x00000100
-#define MUX4_2 0x00000200
-#define MUX4_3 0x00000300
-
-#define MUX5 0x00000C00
-#define MUX5_0 0x00000000
-#define MUX5_1 0x00000400
-#define MUX5_2 0x00000800
-#define MUX5_3 0x00000C00
-
-#define MUX6 0x00003000
-#define MUX6_0 0x00000000
-#define MUX6_1 0x00001000
-#define MUX6_2 0x00002000
-#define MUX6_3 0x00003000
-
-#define MUX7 0x0000C000
-#define MUX7_0 0x00000000
-#define MUX7_1 0x00004000
-#define MUX7_2 0x00008000
-#define MUX7_3 0x0000C000
-
-#define MUX8 0x00030000
-#define MUX8_0 0x00000000
-#define MUX8_1 0x00010000
-#define MUX8_2 0x00020000
-#define MUX8_3 0x00030000
-
-#define MUX9 0x000C0000
-#define MUX9_0 0x00000000
-#define MUX9_1 0x00040000
-#define MUX9_2 0x00080000
-#define MUX9_3 0x000C0000
-
-#define MUX10 0x00300000
-#define MUX10_0 0x00000000
-#define MUX10_1 0x00100000
-#define MUX10_2 0x00200000
-#define MUX10_3 0x00300000
-
-#define MUX11 0x00C00000
-#define MUX11_0 0x00000000
-#define MUX11_1 0x00400000
-#define MUX11_2 0x00800000
-#define MUX11_3 0x00C00000
-
-#define MUX12 0x03000000
-#define MUX12_0 0x00000000
-#define MUX12_1 0x01000000
-#define MUX12_2 0x02000000
-#define MUX12_3 0x03000000
-
-#define MUX13 0x0C000000
-#define MUX13_0 0x00000000
-#define MUX13_1 0x04000000
-#define MUX13_2 0x08000000
-#define MUX13_3 0x0C000000
-
-#define MUX14 0x30000000
-#define MUX14_0 0x00000000
-#define MUX14_1 0x10000000
-#define MUX14_2 0x20000000
-#define MUX14_3 0x30000000
-
-#define MUX15 0xC0000000
-#define MUX15_0 0x00000000
-#define MUX15_1 0x40000000
-#define MUX15_2 0x80000000
-#define MUX15_3 0xC0000000
-
-#define MUX(b15,b14,b13,b12,b11,b10,b9,b8,b7,b6,b5,b4,b3,b2,b1,b0) \
- ((((b15)&3) << 30) | \
- (((b14)&3) << 28) | \
- (((b13)&3) << 26) | \
- (((b12)&3) << 24) | \
- (((b11)&3) << 22) | \
- (((b10)&3) << 20) | \
- (((b9) &3) << 18) | \
- (((b8) &3) << 16) | \
- (((b7) &3) << 14) | \
- (((b6) &3) << 12) | \
- (((b5) &3) << 10) | \
- (((b4) &3) << 8) | \
- (((b3) &3) << 6) | \
- (((b2) &3) << 4) | \
- (((b1) &3) << 2) | \
- (((b0) &3)))
-
-/* Bit fields for PINT0_ASSIGN and PINT1_ASSIGN registers */
-
-#define B0MAP 0x000000FF /* Byte 0 Lower Half Port Mapping */
-#define B0MAP_PAL 0x00000000 /* Map Port A Low to Byte 0 */
-#define B0MAP_PBL 0x00000001 /* Map Port B Low to Byte 0 */
-#define B1MAP 0x0000FF00 /* Byte 1 Upper Half Port Mapping */
-#define B1MAP_PAH 0x00000000 /* Map Port A High to Byte 1 */
-#define B1MAP_PBH 0x00000100 /* Map Port B High to Byte 1 */
-#define B2MAP 0x00FF0000 /* Byte 2 Lower Half Port Mapping */
-#define B2MAP_PAL 0x00000000 /* Map Port A Low to Byte 2 */
-#define B2MAP_PBL 0x00010000 /* Map Port B Low to Byte 2 */
-#define B3MAP 0xFF000000 /* Byte 3 Upper Half Port Mapping */
-#define B3MAP_PAH 0x00000000 /* Map Port A High to Byte 3 */
-#define B3MAP_PBH 0x01000000 /* Map Port B High to Byte 3 */
-
-/* Bit fields for PINT2_ASSIGN and PINT3_ASSIGN registers */
-
-#define B0MAP_PCL 0x00000000 /* Map Port C Low to Byte 0 */
-#define B0MAP_PDL 0x00000001 /* Map Port D Low to Byte 0 */
-#define B0MAP_PEL 0x00000002 /* Map Port E Low to Byte 0 */
-#define B0MAP_PFL 0x00000003 /* Map Port F Low to Byte 0 */
-#define B0MAP_PGL 0x00000004 /* Map Port G Low to Byte 0 */
-#define B0MAP_PHL 0x00000005 /* Map Port H Low to Byte 0 */
-#define B0MAP_PIL 0x00000006 /* Map Port I Low to Byte 0 */
-#define B0MAP_PJL 0x00000007 /* Map Port J Low to Byte 0 */
-
-#define B1MAP_PCH 0x00000000 /* Map Port C High to Byte 1 */
-#define B1MAP_PDH 0x00000100 /* Map Port D High to Byte 1 */
-#define B1MAP_PEH 0x00000200 /* Map Port E High to Byte 1 */
-#define B1MAP_PFH 0x00000300 /* Map Port F High to Byte 1 */
-#define B1MAP_PGH 0x00000400 /* Map Port G High to Byte 1 */
-#define B1MAP_PHH 0x00000500 /* Map Port H High to Byte 1 */
-#define B1MAP_PIH 0x00000600 /* Map Port I High to Byte 1 */
-#define B1MAP_PJH 0x00000700 /* Map Port J High to Byte 1 */
-
-#define B2MAP_PCL 0x00000000 /* Map Port C Low to Byte 2 */
-#define B2MAP_PDL 0x00010000 /* Map Port D Low to Byte 2 */
-#define B2MAP_PEL 0x00020000 /* Map Port E Low to Byte 2 */
-#define B2MAP_PFL 0x00030000 /* Map Port F Low to Byte 2 */
-#define B2MAP_PGL 0x00040000 /* Map Port G Low to Byte 2 */
-#define B2MAP_PHL 0x00050000 /* Map Port H Low to Byte 2 */
-#define B2MAP_PIL 0x00060000 /* Map Port I Low to Byte 2 */
-#define B2MAP_PJL 0x00070000 /* Map Port J Low to Byte 2 */
-
-#define B3MAP_PCH 0x00000000 /* Map Port C High to Byte 3 */
-#define B3MAP_PDH 0x01000000 /* Map Port D High to Byte 3 */
-#define B3MAP_PEH 0x02000000 /* Map Port E High to Byte 3 */
-#define B3MAP_PFH 0x03000000 /* Map Port F High to Byte 3 */
-#define B3MAP_PGH 0x04000000 /* Map Port G High to Byte 3 */
-#define B3MAP_PHH 0x05000000 /* Map Port H High to Byte 3 */
-#define B3MAP_PIH 0x06000000 /* Map Port I High to Byte 3 */
-#define B3MAP_PJH 0x07000000 /* Map Port J High to Byte 3 */
-
-#endif /* _DEF_BF54X_H */
+++ /dev/null
-/* mach/dma.h - arch-specific DMA defines
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_DMA_H_
-#define _MACH_DMA_H_
-
-#define CH_SPORT0_RX 0
-#define CH_SPORT0_TX 1
-#define CH_SPORT1_RX 2
-#define CH_SPORT1_TX 3
-#define CH_SPI0 4
-#define CH_SPI1 5
-#define CH_UART0_RX 6
-#define CH_UART0_TX 7
-#define CH_UART1_RX 8
-#define CH_UART1_TX 9
-#define CH_ATAPI_RX 10
-#define CH_ATAPI_TX 11
-#define CH_EPPI0 12
-#define CH_EPPI1 13
-#define CH_EPPI2 14
-#define CH_PIXC_IMAGE 15
-#define CH_PIXC_OVERLAY 16
-#define CH_PIXC_OUTPUT 17
-#define CH_SPORT2_RX 18
-#define CH_SPORT2_TX 19
-#define CH_SPORT3_RX 20
-#define CH_SPORT3_TX 21
-#define CH_SDH 22
-#define CH_NFC 22
-#define CH_SPI2 23
-
-#if defined(CONFIG_UART2_DMA_RX_ON_DMA13)
-#define CH_UART2_RX 13
-#define IRQ_UART2_RX BFIN_IRQ(37) /* UART2 RX USE EPP1 (DMA13) Interrupt */
-#define CH_UART2_TX 14
-#define IRQ_UART2_TX BFIN_IRQ(38) /* UART2 RX USE EPP1 (DMA14) Interrupt */
-#else /* Default USE SPORT2's DMA Channel */
-#define CH_UART2_RX 18
-#define IRQ_UART2_RX BFIN_IRQ(33) /* UART2 RX (DMA18) Interrupt */
-#define CH_UART2_TX 19
-#define IRQ_UART2_TX BFIN_IRQ(34) /* UART2 TX (DMA19) Interrupt */
-#endif
-
-#if defined(CONFIG_UART3_DMA_RX_ON_DMA15)
-#define CH_UART3_RX 15
-#define IRQ_UART3_RX BFIN_IRQ(64) /* UART3 RX USE PIXC IN0 (DMA15) Interrupt */
-#define CH_UART3_TX 16
-#define IRQ_UART3_TX BFIN_IRQ(65) /* UART3 TX USE PIXC IN1 (DMA16) Interrupt */
-#else /* Default USE SPORT3's DMA Channel */
-#define CH_UART3_RX 20
-#define IRQ_UART3_RX BFIN_IRQ(35) /* UART3 RX (DMA20) Interrupt */
-#define CH_UART3_TX 21
-#define IRQ_UART3_TX BFIN_IRQ(36) /* UART3 TX (DMA21) Interrupt */
-#endif
-
-#define CH_MEM_STREAM0_DEST 24
-#define CH_MEM_STREAM0_SRC 25
-#define CH_MEM_STREAM1_DEST 26
-#define CH_MEM_STREAM1_SRC 27
-#define CH_MEM_STREAM2_DEST 28
-#define CH_MEM_STREAM2_SRC 29
-#define CH_MEM_STREAM3_DEST 30
-#define CH_MEM_STREAM3_SRC 31
-
-#define MAX_DMA_CHANNELS 32
-
-#endif
+++ /dev/null
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-
-#ifndef _MACH_GPIO_H_
-#define _MACH_GPIO_H_
-
-#define GPIO_PA0 0
-#define GPIO_PA1 1
-#define GPIO_PA2 2
-#define GPIO_PA3 3
-#define GPIO_PA4 4
-#define GPIO_PA5 5
-#define GPIO_PA6 6
-#define GPIO_PA7 7
-#define GPIO_PA8 8
-#define GPIO_PA9 9
-#define GPIO_PA10 10
-#define GPIO_PA11 11
-#define GPIO_PA12 12
-#define GPIO_PA13 13
-#define GPIO_PA14 14
-#define GPIO_PA15 15
-#define GPIO_PB0 16
-#define GPIO_PB1 17
-#define GPIO_PB2 18
-#define GPIO_PB3 19
-#define GPIO_PB4 20
-#define GPIO_PB5 21
-#define GPIO_PB6 22
-#define GPIO_PB7 23
-#define GPIO_PB8 24
-#define GPIO_PB9 25
-#define GPIO_PB10 26
-#define GPIO_PB11 27
-#define GPIO_PB12 28
-#define GPIO_PB13 29
-#define GPIO_PB14 30
-#define GPIO_PB15 31 /* N/A */
-#define GPIO_PC0 32
-#define GPIO_PC1 33
-#define GPIO_PC2 34
-#define GPIO_PC3 35
-#define GPIO_PC4 36
-#define GPIO_PC5 37
-#define GPIO_PC6 38
-#define GPIO_PC7 39
-#define GPIO_PC8 40
-#define GPIO_PC9 41
-#define GPIO_PC10 42
-#define GPIO_PC11 43
-#define GPIO_PC12 44
-#define GPIO_PC13 45
-#define GPIO_PC14 46 /* N/A */
-#define GPIO_PC15 47 /* N/A */
-#define GPIO_PD0 48
-#define GPIO_PD1 49
-#define GPIO_PD2 50
-#define GPIO_PD3 51
-#define GPIO_PD4 52
-#define GPIO_PD5 53
-#define GPIO_PD6 54
-#define GPIO_PD7 55
-#define GPIO_PD8 56
-#define GPIO_PD9 57
-#define GPIO_PD10 58
-#define GPIO_PD11 59
-#define GPIO_PD12 60
-#define GPIO_PD13 61
-#define GPIO_PD14 62
-#define GPIO_PD15 63
-#define GPIO_PE0 64
-#define GPIO_PE1 65
-#define GPIO_PE2 66
-#define GPIO_PE3 67
-#define GPIO_PE4 68
-#define GPIO_PE5 69
-#define GPIO_PE6 70
-#define GPIO_PE7 71
-#define GPIO_PE8 72
-#define GPIO_PE9 73
-#define GPIO_PE10 74
-#define GPIO_PE11 75
-#define GPIO_PE12 76
-#define GPIO_PE13 77
-#define GPIO_PE14 78
-#define GPIO_PE15 79
-#define GPIO_PF0 80
-#define GPIO_PF1 81
-#define GPIO_PF2 82
-#define GPIO_PF3 83
-#define GPIO_PF4 84
-#define GPIO_PF5 85
-#define GPIO_PF6 86
-#define GPIO_PF7 87
-#define GPIO_PF8 88
-#define GPIO_PF9 89
-#define GPIO_PF10 90
-#define GPIO_PF11 91
-#define GPIO_PF12 92
-#define GPIO_PF13 93
-#define GPIO_PF14 94
-#define GPIO_PF15 95
-#define GPIO_PG0 96
-#define GPIO_PG1 97
-#define GPIO_PG2 98
-#define GPIO_PG3 99
-#define GPIO_PG4 100
-#define GPIO_PG5 101
-#define GPIO_PG6 102
-#define GPIO_PG7 103
-#define GPIO_PG8 104
-#define GPIO_PG9 105
-#define GPIO_PG10 106
-#define GPIO_PG11 107
-#define GPIO_PG12 108
-#define GPIO_PG13 109
-#define GPIO_PG14 110
-#define GPIO_PG15 111
-#define GPIO_PH0 112
-#define GPIO_PH1 113
-#define GPIO_PH2 114
-#define GPIO_PH3 115
-#define GPIO_PH4 116
-#define GPIO_PH5 117
-#define GPIO_PH6 118
-#define GPIO_PH7 119
-#define GPIO_PH8 120
-#define GPIO_PH9 121
-#define GPIO_PH10 122
-#define GPIO_PH11 123
-#define GPIO_PH12 124
-#define GPIO_PH13 125
-#define GPIO_PH14 126 /* N/A */
-#define GPIO_PH15 127 /* N/A */
-#define GPIO_PI0 128
-#define GPIO_PI1 129
-#define GPIO_PI2 130
-#define GPIO_PI3 131
-#define GPIO_PI4 132
-#define GPIO_PI5 133
-#define GPIO_PI6 134
-#define GPIO_PI7 135
-#define GPIO_PI8 136
-#define GPIO_PI9 137
-#define GPIO_PI10 138
-#define GPIO_PI11 139
-#define GPIO_PI12 140
-#define GPIO_PI13 141
-#define GPIO_PI14 142
-#define GPIO_PI15 143
-#define GPIO_PJ0 144
-#define GPIO_PJ1 145
-#define GPIO_PJ2 146
-#define GPIO_PJ3 147
-#define GPIO_PJ4 148
-#define GPIO_PJ5 149
-#define GPIO_PJ6 150
-#define GPIO_PJ7 151
-#define GPIO_PJ8 152
-#define GPIO_PJ9 153
-#define GPIO_PJ10 154
-#define GPIO_PJ11 155
-#define GPIO_PJ12 156
-#define GPIO_PJ13 157
-#define GPIO_PJ14 158 /* N/A */
-#define GPIO_PJ15 159 /* N/A */
-
-#define MAX_BLACKFIN_GPIOS 160
-
-#define BFIN_GPIO_PINT 1
-#define NR_PINT_SYS_IRQS 4
-#define NR_PINTS 160
-
-#ifndef __ASSEMBLY__
-
-struct gpio_port_t {
- unsigned short port_fer;
- unsigned short dummy1;
- unsigned short data;
- unsigned short dummy2;
- unsigned short data_set;
- unsigned short dummy3;
- unsigned short data_clear;
- unsigned short dummy4;
- unsigned short dir_set;
- unsigned short dummy5;
- unsigned short dir_clear;
- unsigned short dummy6;
- unsigned short inen;
- unsigned short dummy7;
- unsigned int port_mux;
-};
-
-#endif
-
-#include <mach-common/ports-a.h>
-#include <mach-common/ports-b.h>
-#include <mach-common/ports-c.h>
-#include <mach-common/ports-d.h>
-#include <mach-common/ports-e.h>
-#include <mach-common/ports-f.h>
-#include <mach-common/ports-g.h>
-#include <mach-common/ports-h.h>
-#include <mach-common/ports-i.h>
-#include <mach-common/ports-j.h>
-
-#endif /* _MACH_GPIO_H_ */
+++ /dev/null
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BF548_IRQ_H_
-#define _BF548_IRQ_H_
-
-#include <mach-common/irq.h>
-
-#define NR_PERI_INTS (3 * 32)
-
-#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
-#define IRQ_DMAC0_ERROR BFIN_IRQ(1) /* DMAC0 Status Interrupt */
-#define IRQ_EPPI0_ERROR BFIN_IRQ(2) /* EPPI0 Error Interrupt */
-#define IRQ_SPORT0_ERROR BFIN_IRQ(3) /* SPORT0 Error Interrupt */
-#define IRQ_SPORT1_ERROR BFIN_IRQ(4) /* SPORT1 Error Interrupt */
-#define IRQ_SPI0_ERROR BFIN_IRQ(5) /* SPI0 Status(Error) Interrupt */
-#define IRQ_UART0_ERROR BFIN_IRQ(6) /* UART0 Status(Error) Interrupt */
-#define IRQ_RTC BFIN_IRQ(7) /* RTC Interrupt */
-#define IRQ_EPPI0 BFIN_IRQ(8) /* EPPI0 Interrupt (DMA12) */
-#define IRQ_SPORT0_RX BFIN_IRQ(9) /* SPORT0 RX Interrupt (DMA0) */
-#define IRQ_SPORT0_TX BFIN_IRQ(10) /* SPORT0 TX Interrupt (DMA1) */
-#define IRQ_SPORT1_RX BFIN_IRQ(11) /* SPORT1 RX Interrupt (DMA2) */
-#define IRQ_SPORT1_TX BFIN_IRQ(12) /* SPORT1 TX Interrupt (DMA3) */
-#define IRQ_SPI0 BFIN_IRQ(13) /* SPI0 Interrupt (DMA4) */
-#define IRQ_UART0_RX BFIN_IRQ(14) /* UART0 RX Interrupt (DMA6) */
-#define IRQ_UART0_TX BFIN_IRQ(15) /* UART0 TX Interrupt (DMA7) */
-#define IRQ_TIMER8 BFIN_IRQ(16) /* TIMER 8 Interrupt */
-#define IRQ_TIMER9 BFIN_IRQ(17) /* TIMER 9 Interrupt */
-#define IRQ_TIMER10 BFIN_IRQ(18) /* TIMER 10 Interrupt */
-#define IRQ_PINT0 BFIN_IRQ(19) /* PINT0 Interrupt */
-#define IRQ_PINT1 BFIN_IRQ(20) /* PINT1 Interrupt */
-#define IRQ_MDMAS0 BFIN_IRQ(21) /* MDMA Stream 0 Interrupt */
-#define IRQ_MDMAS1 BFIN_IRQ(22) /* MDMA Stream 1 Interrupt */
-#define IRQ_WATCH BFIN_IRQ(23) /* Watchdog Interrupt */
-#define IRQ_DMAC1_ERROR BFIN_IRQ(24) /* DMAC1 Status (Error) Interrupt */
-#define IRQ_SPORT2_ERROR BFIN_IRQ(25) /* SPORT2 Error Interrupt */
-#define IRQ_SPORT3_ERROR BFIN_IRQ(26) /* SPORT3 Error Interrupt */
-#define IRQ_MXVR_DATA BFIN_IRQ(27) /* MXVR Data Interrupt */
-#define IRQ_SPI1_ERROR BFIN_IRQ(28) /* SPI1 Status (Error) Interrupt */
-#define IRQ_SPI2_ERROR BFIN_IRQ(29) /* SPI2 Status (Error) Interrupt */
-#define IRQ_UART1_ERROR BFIN_IRQ(30) /* UART1 Status (Error) Interrupt */
-#define IRQ_UART2_ERROR BFIN_IRQ(31) /* UART2 Status (Error) Interrupt */
-#define IRQ_CAN0_ERROR BFIN_IRQ(32) /* CAN0 Status (Error) Interrupt */
-#define IRQ_SPORT2_RX BFIN_IRQ(33) /* SPORT2 RX (DMA18) Interrupt */
-#define IRQ_SPORT2_TX BFIN_IRQ(34) /* SPORT2 TX (DMA19) Interrupt */
-#define IRQ_SPORT3_RX BFIN_IRQ(35) /* SPORT3 RX (DMA20) Interrupt */
-#define IRQ_SPORT3_TX BFIN_IRQ(36) /* SPORT3 TX (DMA21) Interrupt */
-#define IRQ_EPPI1 BFIN_IRQ(37) /* EPP1 (DMA13) Interrupt */
-#define IRQ_EPPI2 BFIN_IRQ(38) /* EPP2 (DMA14) Interrupt */
-#define IRQ_SPI1 BFIN_IRQ(39) /* SPI1 (DMA5) Interrupt */
-#define IRQ_SPI2 BFIN_IRQ(40) /* SPI2 (DMA23) Interrupt */
-#define IRQ_UART1_RX BFIN_IRQ(41) /* UART1 RX (DMA8) Interrupt */
-#define IRQ_UART1_TX BFIN_IRQ(42) /* UART1 TX (DMA9) Interrupt */
-#define IRQ_ATAPI_RX BFIN_IRQ(43) /* ATAPI RX (DMA10) Interrupt */
-#define IRQ_ATAPI_TX BFIN_IRQ(44) /* ATAPI TX (DMA11) Interrupt */
-#define IRQ_TWI0 BFIN_IRQ(45) /* TWI0 Interrupt */
-#define IRQ_TWI1 BFIN_IRQ(46) /* TWI1 Interrupt */
-#define IRQ_CAN0_RX BFIN_IRQ(47) /* CAN0 Receive Interrupt */
-#define IRQ_CAN0_TX BFIN_IRQ(48) /* CAN0 Transmit Interrupt */
-#define IRQ_MDMAS2 BFIN_IRQ(49) /* MDMA Stream 2 Interrupt */
-#define IRQ_MDMAS3 BFIN_IRQ(50) /* MDMA Stream 3 Interrupt */
-#define IRQ_MXVR_ERROR BFIN_IRQ(51) /* MXVR Status (Error) Interrupt */
-#define IRQ_MXVR_MSG BFIN_IRQ(52) /* MXVR Message Interrupt */
-#define IRQ_MXVR_PKT BFIN_IRQ(53) /* MXVR Packet Interrupt */
-#define IRQ_EPPI1_ERROR BFIN_IRQ(54) /* EPPI1 Error Interrupt */
-#define IRQ_EPPI2_ERROR BFIN_IRQ(55) /* EPPI2 Error Interrupt */
-#define IRQ_UART3_ERROR BFIN_IRQ(56) /* UART3 Status (Error) Interrupt */
-#define IRQ_HOST_ERROR BFIN_IRQ(57) /* HOST Status (Error) Interrupt */
-#define IRQ_PIXC_ERROR BFIN_IRQ(59) /* PIXC Status (Error) Interrupt */
-#define IRQ_NFC_ERROR BFIN_IRQ(60) /* NFC Error Interrupt */
-#define IRQ_ATAPI_ERROR BFIN_IRQ(61) /* ATAPI Error Interrupt */
-#define IRQ_CAN1_ERROR BFIN_IRQ(62) /* CAN1 Status (Error) Interrupt */
-#define IRQ_HS_DMA_ERROR BFIN_IRQ(63) /* Handshake DMA Status Interrupt */
-#define IRQ_PIXC_IN0 BFIN_IRQ(64) /* PIXC IN0 (DMA15) Interrupt */
-#define IRQ_PIXC_IN1 BFIN_IRQ(65) /* PIXC IN1 (DMA16) Interrupt */
-#define IRQ_PIXC_OUT BFIN_IRQ(66) /* PIXC OUT (DMA17) Interrupt */
-#define IRQ_SDH BFIN_IRQ(67) /* SDH/NFC (DMA22) Interrupt */
-#define IRQ_CNT BFIN_IRQ(68) /* CNT Interrupt */
-#define IRQ_KEY BFIN_IRQ(69) /* KEY Interrupt */
-#define IRQ_CAN1_RX BFIN_IRQ(70) /* CAN1 RX Interrupt */
-#define IRQ_CAN1_TX BFIN_IRQ(71) /* CAN1 TX Interrupt */
-#define IRQ_SDH_MASK0 BFIN_IRQ(72) /* SDH Mask 0 Interrupt */
-#define IRQ_SDH_MASK1 BFIN_IRQ(73) /* SDH Mask 1 Interrupt */
-#define IRQ_USB_INT0 BFIN_IRQ(75) /* USB INT0 Interrupt */
-#define IRQ_USB_INT1 BFIN_IRQ(76) /* USB INT1 Interrupt */
-#define IRQ_USB_INT2 BFIN_IRQ(77) /* USB INT2 Interrupt */
-#define IRQ_USB_DMA BFIN_IRQ(78) /* USB DMA Interrupt */
-#define IRQ_OPTSEC BFIN_IRQ(79) /* OTPSEC Interrupt */
-#define IRQ_TIMER0 BFIN_IRQ(86) /* Timer 0 Interrupt */
-#define IRQ_TIMER1 BFIN_IRQ(87) /* Timer 1 Interrupt */
-#define IRQ_TIMER2 BFIN_IRQ(88) /* Timer 2 Interrupt */
-#define IRQ_TIMER3 BFIN_IRQ(89) /* Timer 3 Interrupt */
-#define IRQ_TIMER4 BFIN_IRQ(90) /* Timer 4 Interrupt */
-#define IRQ_TIMER5 BFIN_IRQ(91) /* Timer 5 Interrupt */
-#define IRQ_TIMER6 BFIN_IRQ(92) /* Timer 6 Interrupt */
-#define IRQ_TIMER7 BFIN_IRQ(93) /* Timer 7 Interrupt */
-#define IRQ_PINT2 BFIN_IRQ(94) /* PINT2 Interrupt */
-#define IRQ_PINT3 BFIN_IRQ(95) /* PINT3 Interrupt */
-
-#define SYS_IRQS IRQ_PINT3
-
-#define BFIN_PA_IRQ(x) ((x) + SYS_IRQS + 1)
-#define IRQ_PA0 BFIN_PA_IRQ(0)
-#define IRQ_PA1 BFIN_PA_IRQ(1)
-#define IRQ_PA2 BFIN_PA_IRQ(2)
-#define IRQ_PA3 BFIN_PA_IRQ(3)
-#define IRQ_PA4 BFIN_PA_IRQ(4)
-#define IRQ_PA5 BFIN_PA_IRQ(5)
-#define IRQ_PA6 BFIN_PA_IRQ(6)
-#define IRQ_PA7 BFIN_PA_IRQ(7)
-#define IRQ_PA8 BFIN_PA_IRQ(8)
-#define IRQ_PA9 BFIN_PA_IRQ(9)
-#define IRQ_PA10 BFIN_PA_IRQ(10)
-#define IRQ_PA11 BFIN_PA_IRQ(11)
-#define IRQ_PA12 BFIN_PA_IRQ(12)
-#define IRQ_PA13 BFIN_PA_IRQ(13)
-#define IRQ_PA14 BFIN_PA_IRQ(14)
-#define IRQ_PA15 BFIN_PA_IRQ(15)
-
-#define BFIN_PB_IRQ(x) ((x) + IRQ_PA15 + 1)
-#define IRQ_PB0 BFIN_PB_IRQ(0)
-#define IRQ_PB1 BFIN_PB_IRQ(1)
-#define IRQ_PB2 BFIN_PB_IRQ(2)
-#define IRQ_PB3 BFIN_PB_IRQ(3)
-#define IRQ_PB4 BFIN_PB_IRQ(4)
-#define IRQ_PB5 BFIN_PB_IRQ(5)
-#define IRQ_PB6 BFIN_PB_IRQ(6)
-#define IRQ_PB7 BFIN_PB_IRQ(7)
-#define IRQ_PB8 BFIN_PB_IRQ(8)
-#define IRQ_PB9 BFIN_PB_IRQ(9)
-#define IRQ_PB10 BFIN_PB_IRQ(10)
-#define IRQ_PB11 BFIN_PB_IRQ(11)
-#define IRQ_PB12 BFIN_PB_IRQ(12)
-#define IRQ_PB13 BFIN_PB_IRQ(13)
-#define IRQ_PB14 BFIN_PB_IRQ(14)
-#define IRQ_PB15 BFIN_PB_IRQ(15) /* N/A */
-
-#define BFIN_PC_IRQ(x) ((x) + IRQ_PB15 + 1)
-#define IRQ_PC0 BFIN_PC_IRQ(0)
-#define IRQ_PC1 BFIN_PC_IRQ(1)
-#define IRQ_PC2 BFIN_PC_IRQ(2)
-#define IRQ_PC3 BFIN_PC_IRQ(3)
-#define IRQ_PC4 BFIN_PC_IRQ(4)
-#define IRQ_PC5 BFIN_PC_IRQ(5)
-#define IRQ_PC6 BFIN_PC_IRQ(6)
-#define IRQ_PC7 BFIN_PC_IRQ(7)
-#define IRQ_PC8 BFIN_PC_IRQ(8)
-#define IRQ_PC9 BFIN_PC_IRQ(9)
-#define IRQ_PC10 BFIN_PC_IRQ(10)
-#define IRQ_PC11 BFIN_PC_IRQ(11)
-#define IRQ_PC12 BFIN_PC_IRQ(12)
-#define IRQ_PC13 BFIN_PC_IRQ(13)
-#define IRQ_PC14 BFIN_PC_IRQ(14) /* N/A */
-#define IRQ_PC15 BFIN_PC_IRQ(15) /* N/A */
-
-#define BFIN_PD_IRQ(x) ((x) + IRQ_PC15 + 1)
-#define IRQ_PD0 BFIN_PD_IRQ(0)
-#define IRQ_PD1 BFIN_PD_IRQ(1)
-#define IRQ_PD2 BFIN_PD_IRQ(2)
-#define IRQ_PD3 BFIN_PD_IRQ(3)
-#define IRQ_PD4 BFIN_PD_IRQ(4)
-#define IRQ_PD5 BFIN_PD_IRQ(5)
-#define IRQ_PD6 BFIN_PD_IRQ(6)
-#define IRQ_PD7 BFIN_PD_IRQ(7)
-#define IRQ_PD8 BFIN_PD_IRQ(8)
-#define IRQ_PD9 BFIN_PD_IRQ(9)
-#define IRQ_PD10 BFIN_PD_IRQ(10)
-#define IRQ_PD11 BFIN_PD_IRQ(11)
-#define IRQ_PD12 BFIN_PD_IRQ(12)
-#define IRQ_PD13 BFIN_PD_IRQ(13)
-#define IRQ_PD14 BFIN_PD_IRQ(14)
-#define IRQ_PD15 BFIN_PD_IRQ(15)
-
-#define BFIN_PE_IRQ(x) ((x) + IRQ_PD15 + 1)
-#define IRQ_PE0 BFIN_PE_IRQ(0)
-#define IRQ_PE1 BFIN_PE_IRQ(1)
-#define IRQ_PE2 BFIN_PE_IRQ(2)
-#define IRQ_PE3 BFIN_PE_IRQ(3)
-#define IRQ_PE4 BFIN_PE_IRQ(4)
-#define IRQ_PE5 BFIN_PE_IRQ(5)
-#define IRQ_PE6 BFIN_PE_IRQ(6)
-#define IRQ_PE7 BFIN_PE_IRQ(7)
-#define IRQ_PE8 BFIN_PE_IRQ(8)
-#define IRQ_PE9 BFIN_PE_IRQ(9)
-#define IRQ_PE10 BFIN_PE_IRQ(10)
-#define IRQ_PE11 BFIN_PE_IRQ(11)
-#define IRQ_PE12 BFIN_PE_IRQ(12)
-#define IRQ_PE13 BFIN_PE_IRQ(13)
-#define IRQ_PE14 BFIN_PE_IRQ(14)
-#define IRQ_PE15 BFIN_PE_IRQ(15)
-
-#define BFIN_PF_IRQ(x) ((x) + IRQ_PE15 + 1)
-#define IRQ_PF0 BFIN_PF_IRQ(0)
-#define IRQ_PF1 BFIN_PF_IRQ(1)
-#define IRQ_PF2 BFIN_PF_IRQ(2)
-#define IRQ_PF3 BFIN_PF_IRQ(3)
-#define IRQ_PF4 BFIN_PF_IRQ(4)
-#define IRQ_PF5 BFIN_PF_IRQ(5)
-#define IRQ_PF6 BFIN_PF_IRQ(6)
-#define IRQ_PF7 BFIN_PF_IRQ(7)
-#define IRQ_PF8 BFIN_PF_IRQ(8)
-#define IRQ_PF9 BFIN_PF_IRQ(9)
-#define IRQ_PF10 BFIN_PF_IRQ(10)
-#define IRQ_PF11 BFIN_PF_IRQ(11)
-#define IRQ_PF12 BFIN_PF_IRQ(12)
-#define IRQ_PF13 BFIN_PF_IRQ(13)
-#define IRQ_PF14 BFIN_PF_IRQ(14)
-#define IRQ_PF15 BFIN_PF_IRQ(15)
-
-#define BFIN_PG_IRQ(x) ((x) + IRQ_PF15 + 1)
-#define IRQ_PG0 BFIN_PG_IRQ(0)
-#define IRQ_PG1 BFIN_PG_IRQ(1)
-#define IRQ_PG2 BFIN_PG_IRQ(2)
-#define IRQ_PG3 BFIN_PG_IRQ(3)
-#define IRQ_PG4 BFIN_PG_IRQ(4)
-#define IRQ_PG5 BFIN_PG_IRQ(5)
-#define IRQ_PG6 BFIN_PG_IRQ(6)
-#define IRQ_PG7 BFIN_PG_IRQ(7)
-#define IRQ_PG8 BFIN_PG_IRQ(8)
-#define IRQ_PG9 BFIN_PG_IRQ(9)
-#define IRQ_PG10 BFIN_PG_IRQ(10)
-#define IRQ_PG11 BFIN_PG_IRQ(11)
-#define IRQ_PG12 BFIN_PG_IRQ(12)
-#define IRQ_PG13 BFIN_PG_IRQ(13)
-#define IRQ_PG14 BFIN_PG_IRQ(14)
-#define IRQ_PG15 BFIN_PG_IRQ(15)
-
-#define BFIN_PH_IRQ(x) ((x) + IRQ_PG15 + 1)
-#define IRQ_PH0 BFIN_PH_IRQ(0)
-#define IRQ_PH1 BFIN_PH_IRQ(1)
-#define IRQ_PH2 BFIN_PH_IRQ(2)
-#define IRQ_PH3 BFIN_PH_IRQ(3)
-#define IRQ_PH4 BFIN_PH_IRQ(4)
-#define IRQ_PH5 BFIN_PH_IRQ(5)
-#define IRQ_PH6 BFIN_PH_IRQ(6)
-#define IRQ_PH7 BFIN_PH_IRQ(7)
-#define IRQ_PH8 BFIN_PH_IRQ(8)
-#define IRQ_PH9 BFIN_PH_IRQ(9)
-#define IRQ_PH10 BFIN_PH_IRQ(10)
-#define IRQ_PH11 BFIN_PH_IRQ(11)
-#define IRQ_PH12 BFIN_PH_IRQ(12)
-#define IRQ_PH13 BFIN_PH_IRQ(13)
-#define IRQ_PH14 BFIN_PH_IRQ(14) /* N/A */
-#define IRQ_PH15 BFIN_PH_IRQ(15) /* N/A */
-
-#define BFIN_PI_IRQ(x) ((x) + IRQ_PH15 + 1)
-#define IRQ_PI0 BFIN_PI_IRQ(0)
-#define IRQ_PI1 BFIN_PI_IRQ(1)
-#define IRQ_PI2 BFIN_PI_IRQ(2)
-#define IRQ_PI3 BFIN_PI_IRQ(3)
-#define IRQ_PI4 BFIN_PI_IRQ(4)
-#define IRQ_PI5 BFIN_PI_IRQ(5)
-#define IRQ_PI6 BFIN_PI_IRQ(6)
-#define IRQ_PI7 BFIN_PI_IRQ(7)
-#define IRQ_PI8 BFIN_PI_IRQ(8)
-#define IRQ_PI9 BFIN_PI_IRQ(9)
-#define IRQ_PI10 BFIN_PI_IRQ(10)
-#define IRQ_PI11 BFIN_PI_IRQ(11)
-#define IRQ_PI12 BFIN_PI_IRQ(12)
-#define IRQ_PI13 BFIN_PI_IRQ(13)
-#define IRQ_PI14 BFIN_PI_IRQ(14)
-#define IRQ_PI15 BFIN_PI_IRQ(15)
-
-#define BFIN_PJ_IRQ(x) ((x) + IRQ_PI15 + 1)
-#define IRQ_PJ0 BFIN_PJ_IRQ(0)
-#define IRQ_PJ1 BFIN_PJ_IRQ(1)
-#define IRQ_PJ2 BFIN_PJ_IRQ(2)
-#define IRQ_PJ3 BFIN_PJ_IRQ(3)
-#define IRQ_PJ4 BFIN_PJ_IRQ(4)
-#define IRQ_PJ5 BFIN_PJ_IRQ(5)
-#define IRQ_PJ6 BFIN_PJ_IRQ(6)
-#define IRQ_PJ7 BFIN_PJ_IRQ(7)
-#define IRQ_PJ8 BFIN_PJ_IRQ(8)
-#define IRQ_PJ9 BFIN_PJ_IRQ(9)
-#define IRQ_PJ10 BFIN_PJ_IRQ(10)
-#define IRQ_PJ11 BFIN_PJ_IRQ(11)
-#define IRQ_PJ12 BFIN_PJ_IRQ(12)
-#define IRQ_PJ13 BFIN_PJ_IRQ(13)
-#define IRQ_PJ14 BFIN_PJ_IRQ(14) /* N/A */
-#define IRQ_PJ15 BFIN_PJ_IRQ(15) /* N/A */
-
-#define GPIO_IRQ_BASE IRQ_PA0
-
-#define NR_MACH_IRQS (IRQ_PJ15 + 1)
-
-/* For compatibility reasons with existing code */
-
-#define IRQ_DMAC0_ERR IRQ_DMAC0_ERROR
-#define IRQ_EPPI0_ERR IRQ_EPPI0_ERROR
-#define IRQ_SPORT0_ERR IRQ_SPORT0_ERROR
-#define IRQ_SPORT1_ERR IRQ_SPORT1_ERROR
-#define IRQ_SPI0_ERR IRQ_SPI0_ERROR
-#define IRQ_UART0_ERR IRQ_UART0_ERROR
-#define IRQ_DMAC1_ERR IRQ_DMAC1_ERROR
-#define IRQ_SPORT2_ERR IRQ_SPORT2_ERROR
-#define IRQ_SPORT3_ERR IRQ_SPORT3_ERROR
-#define IRQ_SPI1_ERR IRQ_SPI1_ERROR
-#define IRQ_SPI2_ERR IRQ_SPI2_ERROR
-#define IRQ_UART1_ERR IRQ_UART1_ERROR
-#define IRQ_UART2_ERR IRQ_UART2_ERROR
-#define IRQ_CAN0_ERR IRQ_CAN0_ERROR
-#define IRQ_MXVR_ERR IRQ_MXVR_ERROR
-#define IRQ_EPPI1_ERR IRQ_EPPI1_ERROR
-#define IRQ_EPPI2_ERR IRQ_EPPI2_ERROR
-#define IRQ_UART3_ERR IRQ_UART3_ERROR
-#define IRQ_HOST_ERR IRQ_HOST_ERROR
-#define IRQ_PIXC_ERR IRQ_PIXC_ERROR
-#define IRQ_NFC_ERR IRQ_NFC_ERROR
-#define IRQ_ATAPI_ERR IRQ_ATAPI_ERROR
-#define IRQ_CAN1_ERR IRQ_CAN1_ERROR
-#define IRQ_HS_DMA_ERR IRQ_HS_DMA_ERROR
-
-/* IAR0 BIT FIELDS */
-#define IRQ_PLL_WAKEUP_POS 0
-#define IRQ_DMAC0_ERR_POS 4
-#define IRQ_EPPI0_ERR_POS 8
-#define IRQ_SPORT0_ERR_POS 12
-#define IRQ_SPORT1_ERR_POS 16
-#define IRQ_SPI0_ERR_POS 20
-#define IRQ_UART0_ERR_POS 24
-#define IRQ_RTC_POS 28
-
-/* IAR1 BIT FIELDS */
-#define IRQ_EPPI0_POS 0
-#define IRQ_SPORT0_RX_POS 4
-#define IRQ_SPORT0_TX_POS 8
-#define IRQ_SPORT1_RX_POS 12
-#define IRQ_SPORT1_TX_POS 16
-#define IRQ_SPI0_POS 20
-#define IRQ_UART0_RX_POS 24
-#define IRQ_UART0_TX_POS 28
-
-/* IAR2 BIT FIELDS */
-#define IRQ_TIMER8_POS 0
-#define IRQ_TIMER9_POS 4
-#define IRQ_TIMER10_POS 8
-#define IRQ_PINT0_POS 12
-#define IRQ_PINT1_POS 16
-#define IRQ_MDMAS0_POS 20
-#define IRQ_MDMAS1_POS 24
-#define IRQ_WATCH_POS 28
-
-/* IAR3 BIT FIELDS */
-#define IRQ_DMAC1_ERR_POS 0
-#define IRQ_SPORT2_ERR_POS 4
-#define IRQ_SPORT3_ERR_POS 8
-#define IRQ_MXVR_DATA_POS 12
-#define IRQ_SPI1_ERR_POS 16
-#define IRQ_SPI2_ERR_POS 20
-#define IRQ_UART1_ERR_POS 24
-#define IRQ_UART2_ERR_POS 28
-
-/* IAR4 BIT FILEDS */
-#define IRQ_CAN0_ERR_POS 0
-#define IRQ_SPORT2_RX_POS 4
-#define IRQ_UART2_RX_POS 4
-#define IRQ_SPORT2_TX_POS 8
-#define IRQ_UART2_TX_POS 8
-#define IRQ_SPORT3_RX_POS 12
-#define IRQ_UART3_RX_POS 12
-#define IRQ_SPORT3_TX_POS 16
-#define IRQ_UART3_TX_POS 16
-#define IRQ_EPPI1_POS 20
-#define IRQ_EPPI2_POS 24
-#define IRQ_SPI1_POS 28
-
-/* IAR5 BIT FIELDS */
-#define IRQ_SPI2_POS 0
-#define IRQ_UART1_RX_POS 4
-#define IRQ_UART1_TX_POS 8
-#define IRQ_ATAPI_RX_POS 12
-#define IRQ_ATAPI_TX_POS 16
-#define IRQ_TWI0_POS 20
-#define IRQ_TWI1_POS 24
-#define IRQ_CAN0_RX_POS 28
-
-/* IAR6 BIT FIELDS */
-#define IRQ_CAN0_TX_POS 0
-#define IRQ_MDMAS2_POS 4
-#define IRQ_MDMAS3_POS 8
-#define IRQ_MXVR_ERR_POS 12
-#define IRQ_MXVR_MSG_POS 16
-#define IRQ_MXVR_PKT_POS 20
-#define IRQ_EPPI1_ERR_POS 24
-#define IRQ_EPPI2_ERR_POS 28
-
-/* IAR7 BIT FIELDS */
-#define IRQ_UART3_ERR_POS 0
-#define IRQ_HOST_ERR_POS 4
-#define IRQ_PIXC_ERR_POS 12
-#define IRQ_NFC_ERR_POS 16
-#define IRQ_ATAPI_ERR_POS 20
-#define IRQ_CAN1_ERR_POS 24
-#define IRQ_HS_DMA_ERR_POS 28
-
-/* IAR8 BIT FIELDS */
-#define IRQ_PIXC_IN0_POS 0
-#define IRQ_PIXC_IN1_POS 4
-#define IRQ_PIXC_OUT_POS 8
-#define IRQ_SDH_POS 12
-#define IRQ_CNT_POS 16
-#define IRQ_KEY_POS 20
-#define IRQ_CAN1_RX_POS 24
-#define IRQ_CAN1_TX_POS 28
-
-/* IAR9 BIT FIELDS */
-#define IRQ_SDH_MASK0_POS 0
-#define IRQ_SDH_MASK1_POS 4
-#define IRQ_USB_INT0_POS 12
-#define IRQ_USB_INT1_POS 16
-#define IRQ_USB_INT2_POS 20
-#define IRQ_USB_DMA_POS 24
-#define IRQ_OTPSEC_POS 28
-
-/* IAR10 BIT FIELDS */
-#define IRQ_TIMER0_POS 24
-#define IRQ_TIMER1_POS 28
-
-/* IAR11 BIT FIELDS */
-#define IRQ_TIMER2_POS 0
-#define IRQ_TIMER3_POS 4
-#define IRQ_TIMER4_POS 8
-#define IRQ_TIMER5_POS 12
-#define IRQ_TIMER6_POS 16
-#define IRQ_TIMER7_POS 20
-#define IRQ_PINT2_POS 24
-#define IRQ_PINT3_POS 28
-
-#ifndef __ASSEMBLY__
-#include <linux/types.h>
-
-/*
- * gpio pint registers layout
- */
-struct bfin_pint_regs {
- u32 mask_set;
- u32 mask_clear;
- u32 request;
- u32 assign;
- u32 edge_set;
- u32 edge_clear;
- u32 invert_set;
- u32 invert_clear;
- u32 pinstate;
- u32 latch;
- u32 __pad0[2];
-};
-
-#endif
-
-#endif
+++ /dev/null
-/*
- * BF548 memory map
- *
- * Copyright 2004-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MACH_MEM_MAP_H__
-#define __BFIN_MACH_MEM_MAP_H__
-
-#ifndef __BFIN_MEM_MAP_H__
-# error "do not include mach/mem_map.h directly -- use asm/mem_map.h"
-#endif
-
-/* Async Memory Banks */
-#define ASYNC_BANK3_BASE 0x2C000000 /* Async Bank 3 */
-#define ASYNC_BANK3_SIZE 0x04000000 /* 64M */
-#define ASYNC_BANK2_BASE 0x28000000 /* Async Bank 2 */
-#define ASYNC_BANK2_SIZE 0x04000000 /* 64M */
-#define ASYNC_BANK1_BASE 0x24000000 /* Async Bank 1 */
-#define ASYNC_BANK1_SIZE 0x04000000 /* 64M */
-#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
-#define ASYNC_BANK0_SIZE 0x04000000 /* 64M */
-
-/* Boot ROM Memory */
-
-#define BOOT_ROM_START 0xEF000000
-#define BOOT_ROM_LENGTH 0x1000
-
-/* L1 Instruction ROM */
-
-#define L1_ROM_START 0xFFA14000
-#define L1_ROM_LENGTH 0x10000
-
-/* Level 1 Memory */
-
-/* Memory Map for ADSP-BF548 processors */
-#ifdef CONFIG_BFIN_ICACHE
-#define BFIN_ICACHESIZE (16*1024)
-#else
-#define BFIN_ICACHESIZE (0*1024)
-#endif
-
-#define L1_CODE_START 0xFFA00000
-#define L1_DATA_A_START 0xFF800000
-#define L1_DATA_B_START 0xFF900000
-
-#define L1_CODE_LENGTH 0xC000
-
-#ifdef CONFIG_BFIN_DCACHE
-
-#ifdef CONFIG_BFIN_DCACHE_BANKA
-#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE (16*1024)
-#define BFIN_DSUPBANKS 1
-#else
-#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
-#define BFIN_DCACHESIZE (32*1024)
-#define BFIN_DSUPBANKS 2
-#endif
-
-#else
-#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH 0x8000
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE (0*1024)
-#define BFIN_DSUPBANKS 0
-#endif /*CONFIG_BFIN_DCACHE*/
-
-/* Level 2 Memory */
-#define L2_START 0xFEB00000
-#if defined(CONFIG_BF542)
-# define L2_LENGTH 0
-#elif defined(CONFIG_BF544)
-# define L2_LENGTH 0x10000
-#else
-# define L2_LENGTH 0x20000
-#endif
-
-#endif
+++ /dev/null
-#include <mach-common/pll.h>
+++ /dev/null
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_PORTMUX_H_
-#define _MACH_PORTMUX_H_
-
-#define P_SPORT2_TFS (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(0))
-#define P_SPORT2_DTSEC (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(0))
-#define P_SPORT2_DTPRI (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(0))
-#define P_SPORT2_TSCLK (P_DEFINED | P_IDENT(GPIO_PA3) | P_FUNCT(0))
-#define P_SPORT2_RFS (P_DEFINED | P_IDENT(GPIO_PA4) | P_FUNCT(0))
-#define P_SPORT2_DRSEC (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(0))
-#define P_SPORT2_DRPRI (P_DEFINED | P_IDENT(GPIO_PA6) | P_FUNCT(0))
-#define P_SPORT2_RSCLK (P_DEFINED | P_IDENT(GPIO_PA7) | P_FUNCT(0))
-#define P_SPORT3_TFS (P_DEFINED | P_IDENT(GPIO_PA8) | P_FUNCT(0))
-#define P_SPORT3_DTSEC (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(0))
-#define P_SPORT3_DTPRI (P_DEFINED | P_IDENT(GPIO_PA10) | P_FUNCT(0))
-#define P_SPORT3_TSCLK (P_DEFINED | P_IDENT(GPIO_PA11) | P_FUNCT(0))
-#define P_SPORT3_RFS (P_DEFINED | P_IDENT(GPIO_PA12) | P_FUNCT(0))
-#define P_SPORT3_DRSEC (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(0))
-#define P_SPORT3_DRPRI (P_DEFINED | P_IDENT(GPIO_PA14) | P_FUNCT(0))
-#define P_SPORT3_RSCLK (P_DEFINED | P_IDENT(GPIO_PA15) | P_FUNCT(0))
-#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(1))
-#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(1))
-#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(1))
-#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(1))
-
-#define P_TWI1_SCL (P_DEFINED | P_IDENT(GPIO_PB0) | P_FUNCT(0))
-#define P_TWI1_SDA (P_DEFINED | P_IDENT(GPIO_PB1) | P_FUNCT(0))
-#define P_UART3_RTS (P_DEFINED | P_IDENT(GPIO_PB2) | P_FUNCT(0))
-#define P_UART3_CTS (P_DEFINED | P_IDENT(GPIO_PB3) | P_FUNCT(0))
-#define P_UART2_TX (P_DEFINED | P_IDENT(GPIO_PB4) | P_FUNCT(0))
-#define P_UART2_RX (P_DEFINED | P_IDENT(GPIO_PB5) | P_FUNCT(0))
-#define P_UART3_TX (P_DEFINED | P_IDENT(GPIO_PB6) | P_FUNCT(0))
-#define P_UART3_RX (P_DEFINED | P_IDENT(GPIO_PB7) | P_FUNCT(0))
-#define P_SPI2_SS (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(0))
-#define P_SPI2_SSEL1 (P_DEFINED | P_IDENT(GPIO_PB9) | P_FUNCT(0))
-#define P_SPI2_SSEL2 (P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(0))
-#define P_SPI2_SSEL3 (P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(0))
-#define P_SPI2_SCK (P_DEFINED | P_IDENT(GPIO_PB12) | P_FUNCT(0))
-#define P_SPI2_MOSI (P_DEFINED | P_IDENT(GPIO_PB13) | P_FUNCT(0))
-#define P_SPI2_MISO (P_DEFINED | P_IDENT(GPIO_PB14) | P_FUNCT(0))
-#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(1))
-#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PB9) | P_FUNCT(1))
-#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(1))
-#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(1))
-
-#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PC0) | P_FUNCT(0))
-#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(0))
-#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PC2) | P_FUNCT(0))
-#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PC3) | P_FUNCT(0))
-#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PC4) | P_FUNCT(0))
-#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(0))
-#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(GPIO_PC6) | P_FUNCT(0))
-#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PC7) | P_FUNCT(0))
-#define P_SD_D0 (P_DEFINED | P_IDENT(GPIO_PC8) | P_FUNCT(0))
-#define P_SD_D1 (P_DEFINED | P_IDENT(GPIO_PC9) | P_FUNCT(0))
-#define P_SD_D2 (P_DEFINED | P_IDENT(GPIO_PC10) | P_FUNCT(0))
-#define P_SD_D3 (P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(0))
-#define P_SD_CLK (P_DEFINED | P_IDENT(GPIO_PC12) | P_FUNCT(0))
-#define P_SD_CMD (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(0))
-#define P_MMCLK (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(1))
-#define P_MBCLK (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(1))
-
-#define P_PPI1_D0 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(0))
-#define P_PPI1_D1 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(0))
-#define P_PPI1_D2 (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(0))
-#define P_PPI1_D3 (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(0))
-#define P_PPI1_D4 (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(0))
-#define P_PPI1_D5 (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(0))
-#define P_PPI1_D6 (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(0))
-#define P_PPI1_D7 (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(0))
-#define P_PPI1_D8 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(0))
-#define P_PPI1_D9 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(0))
-#define P_PPI1_D10 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(0))
-#define P_PPI1_D11 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(0))
-#define P_PPI1_D12 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(0))
-#define P_PPI1_D13 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(0))
-#define P_PPI1_D14 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(0))
-#define P_PPI1_D15 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(0))
-
-#define P_HOST_D8 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(1))
-#define P_HOST_D9 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(1))
-#define P_HOST_D10 (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(1))
-#define P_HOST_D11 (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(1))
-#define P_HOST_D12 (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(1))
-#define P_HOST_D13 (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(1))
-#define P_HOST_D14 (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(1))
-#define P_HOST_D15 (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(1))
-#define P_HOST_D0 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(1))
-#define P_HOST_D1 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(1))
-#define P_HOST_D2 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(1))
-#define P_HOST_D3 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(1))
-#define P_HOST_D4 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(1))
-#define P_HOST_D5 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(1))
-#define P_HOST_D6 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(1))
-#define P_HOST_D7 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(1))
-#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(2))
-#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(2))
-#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(2))
-#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(2))
-#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(2))
-#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(2))
-#define P_SPORT1_DRPRI (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(2))
-#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(2))
-#define P_PPI2_D0 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(2))
-#define P_PPI2_D1 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(2))
-#define P_PPI2_D2 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(2))
-#define P_PPI2_D3 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(2))
-#define P_PPI2_D4 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(2))
-#define P_PPI2_D5 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(2))
-#define P_PPI2_D6 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(2))
-#define P_PPI2_D7 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(2))
-#define P_PPI0_D18 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(3))
-#define P_PPI0_D19 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(3))
-#define P_PPI0_D20 (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(3))
-#define P_PPI0_D21 (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(3))
-#define P_PPI0_D22 (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(3))
-#define P_PPI0_D23 (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(3))
-#define P_KEY_ROW0 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(3))
-#define P_KEY_ROW1 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(3))
-#define P_KEY_ROW2 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(3))
-#define P_KEY_ROW3 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(3))
-#define P_KEY_COL0 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(3))
-#define P_KEY_COL1 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(3))
-#define P_KEY_COL2 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(3))
-#define P_KEY_COL3 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(3))
-
-#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PE4
-#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL1
-#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(0))
-#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(0))
-#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(0))
-#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(0))
-#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(0))
-#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(0))
-#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(0))
-#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(0))
-#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PE8) | P_FUNCT(0))
-#define P_UART1_RTS (P_DEFINED | P_IDENT(GPIO_PE9) | P_FUNCT(0))
-#define P_UART1_CTS (P_DEFINED | P_IDENT(GPIO_PE10) | P_FUNCT(0))
-#define P_PPI1_CLK (P_DEFINED | P_IDENT(GPIO_PE11) | P_FUNCT(0))
-#define P_PPI1_FS1 (P_DEFINED | P_IDENT(GPIO_PE12) | P_FUNCT(0))
-#define P_PPI1_FS2 (P_DEFINED | P_IDENT(GPIO_PE13) | P_FUNCT(0))
-#define P_TWI0_SCL (P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(0))
-#define P_TWI0_SDA (P_DEFINED | P_IDENT(GPIO_PE15) | P_FUNCT(0))
-#define P_KEY_COL7 (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(1))
-#define P_KEY_ROW6 (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(1))
-#define P_KEY_COL6 (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(1))
-#define P_KEY_ROW5 (P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(1))
-#define P_KEY_COL5 (P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(1))
-#define P_KEY_ROW4 (P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(1))
-#define P_KEY_COL4 (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(1))
-#define P_KEY_ROW7 (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(1))
-
-#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
-#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
-#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
-#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
-#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
-#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
-#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))
-#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
-#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
-#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
-#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
-#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
-#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
-#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
-#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
-#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
-
-#ifdef CONFIG_BF548_ATAPI_ALTERNATIVE_PORT
-# define P_ATAPI_D0A (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
-# define P_ATAPI_D1A (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
-# define P_ATAPI_D2A (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
-# define P_ATAPI_D3A (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
-# define P_ATAPI_D4A (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
-# define P_ATAPI_D5A (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
-# define P_ATAPI_D6A (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
-# define P_ATAPI_D7A (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
-# define P_ATAPI_D8A (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
-# define P_ATAPI_D9A (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
-# define P_ATAPI_D10A (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1))
-# define P_ATAPI_D11A (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1))
-# define P_ATAPI_D12A (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1))
-# define P_ATAPI_D13A (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1))
-# define P_ATAPI_D14A (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
-# define P_ATAPI_D15A (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
-#else
-# define P_ATAPI_D0A (P_DONTCARE)
-# define P_ATAPI_D1A (P_DONTCARE)
-# define P_ATAPI_D2A (P_DONTCARE)
-# define P_ATAPI_D3A (P_DONTCARE)
-# define P_ATAPI_D4A (P_DONTCARE)
-# define P_ATAPI_D5A (P_DONTCARE)
-# define P_ATAPI_D6A (P_DONTCARE)
-# define P_ATAPI_D7A (P_DONTCARE)
-# define P_ATAPI_D8A (P_DONTCARE)
-# define P_ATAPI_D9A (P_DONTCARE)
-# define P_ATAPI_D10A (P_DONTCARE)
-# define P_ATAPI_D11A (P_DONTCARE)
-# define P_ATAPI_D12A (P_DONTCARE)
-# define P_ATAPI_D13A (P_DONTCARE)
-# define P_ATAPI_D14A (P_DONTCARE)
-# define P_ATAPI_D15A (P_DONTCARE)
-#endif
-
-#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
-#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
-#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0))
-#define P_PPI0_D16 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
-#define P_PPI0_D17 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0))
-#define P_SPI1_SSEL1 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
-#define P_SPI1_SSEL2 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
-#define P_SPI1_SSEL3 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
-#define P_SPI1_SCK (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
-#define P_SPI1_MISO (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
-#define P_SPI1_MOSI (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
-#define P_SPI1_SS (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0))
-#define P_CAN0_TX (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
-#define P_CAN0_RX (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
-#define P_CAN1_TX (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
-#define P_CAN1_RX (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
-#ifdef CONFIG_BF548_ATAPI_ALTERNATIVE_PORT
-# define P_ATAPI_A0A (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(1))
-# define P_ATAPI_A1A (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1))
-# define P_ATAPI_A2A (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1))
-#else
-# define P_ATAPI_A0A (P_DONTCARE)
-# define P_ATAPI_A1A (P_DONTCARE)
-# define P_ATAPI_A2A (P_DONTCARE)
-#endif
-#define P_HOST_CE (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1))
-#define P_HOST_RD (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
-#define P_HOST_WR (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
-#define P_MTXONB (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
-#define P_PPI2_FS2 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(2))
-#define P_PPI2_FS1 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2))
-#define P_PPI2_CLK (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2))
-#define P_CNT_CZM (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(3))
-
-#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
-#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
-#define P_ATAPI_RESET (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
-#define P_HOST_ADDR (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0))
-#define P_HOST_ACK (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0))
-#define P_MTX (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0))
-#define P_MRX (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0))
-#define P_MRXONB (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0))
-#define P_A4 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(0))
-#define P_A5 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(0))
-#define P_A6 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(0))
-#define P_A7 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(0))
-#define P_A8 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(0))
-#define P_A9 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(0))
-#define P_PPI1_FS3 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
-#define P_PPI2_FS3 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(1))
-#define P_TMR8 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(1))
-#define P_TMR9 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(1))
-#define P_TMR10 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(1))
-#define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(1))
-#define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1))
-#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(2))
-#define P_CNT_CDG (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(2))
-#define P_CNT_CUD (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2))
-
-#define P_A10 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI0) | P_FUNCT(0))
-#define P_A11 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI1) | P_FUNCT(0))
-#define P_A12 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI2) | P_FUNCT(0))
-#define P_A13 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI3) | P_FUNCT(0))
-#define P_A14 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI4) | P_FUNCT(0))
-#define P_A15 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI5) | P_FUNCT(0))
-#define P_A16 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI6) | P_FUNCT(0))
-#define P_A17 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI7) | P_FUNCT(0))
-#define P_A18 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI8) | P_FUNCT(0))
-#define P_A19 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI9) | P_FUNCT(0))
-#define P_A20 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI10) | P_FUNCT(0))
-#define P_A21 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI11) | P_FUNCT(0))
-#define P_A22 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI12) | P_FUNCT(0))
-#define P_A23 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI13) | P_FUNCT(0))
-#define P_A24 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI14) | P_FUNCT(0))
-#define P_A25 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI15) | P_FUNCT(0))
-#define P_NOR_CLK (P_DEFINED | P_IDENT(GPIO_PI15) | P_FUNCT(1))
-
-#define P_AMC_ARDY_NOR_WAIT (P_DEFINED | P_IDENT(GPIO_PJ0) | P_FUNCT(0))
-#define P_NAND_CE (P_DEFINED | P_IDENT(GPIO_PJ1) | P_FUNCT(0))
-#define P_NAND_RB (P_DEFINED | P_IDENT(GPIO_PJ2) | P_FUNCT(0))
-#define P_ATAPI_DIOR (P_DEFINED | P_IDENT(GPIO_PJ3) | P_FUNCT(0))
-#define P_ATAPI_DIOW (P_DEFINED | P_IDENT(GPIO_PJ4) | P_FUNCT(0))
-#define P_ATAPI_CS0 (P_DEFINED | P_IDENT(GPIO_PJ5) | P_FUNCT(0))
-#define P_ATAPI_CS1 (P_DEFINED | P_IDENT(GPIO_PJ6) | P_FUNCT(0))
-#define P_ATAPI_DMACK (P_DEFINED | P_IDENT(GPIO_PJ7) | P_FUNCT(0))
-#define P_ATAPI_DMARQ (P_DEFINED | P_IDENT(GPIO_PJ8) | P_FUNCT(0))
-#define P_ATAPI_INTRQ (P_DEFINED | P_IDENT(GPIO_PJ9) | P_FUNCT(0))
-#define P_ATAPI_IORDY (P_DEFINED | P_IDENT(GPIO_PJ10) | P_FUNCT(0))
-#define P_AMC_BR (P_DEFINED | P_IDENT(GPIO_PJ11) | P_FUNCT(0))
-#define P_AMC_BG (P_DEFINED | P_IDENT(GPIO_PJ12) | P_FUNCT(0))
-#define P_AMC_BGH (P_DEFINED | P_IDENT(GPIO_PJ13) | P_FUNCT(0))
-
-
-#define P_NAND_D0 (P_DONTCARE)
-#define P_NAND_D1 (P_DONTCARE)
-#define P_NAND_D2 (P_DONTCARE)
-#define P_NAND_D3 (P_DONTCARE)
-#define P_NAND_D4 (P_DONTCARE)
-#define P_NAND_D5 (P_DONTCARE)
-#define P_NAND_D6 (P_DONTCARE)
-#define P_NAND_D7 (P_DONTCARE)
-#define P_NAND_WE (P_DONTCARE)
-#define P_NAND_RE (P_DONTCARE)
-#define P_NAND_CLE (P_DONTCARE)
-#define P_NAND_ALE (P_DONTCARE)
-
-#endif /* _MACH_PORTMUX_H_ */
+++ /dev/null
-/*
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- *
- * Set up the interrupt priorities
- */
-
-#include <linux/module.h>
-#include <linux/irq.h>
-#include <asm/blackfin.h>
-
-void __init program_IAR(void)
-{
- /* Program the IAR0 Register with the configured priority */
- bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) |
- ((CONFIG_IRQ_DMAC0_ERR - 7) << IRQ_DMAC0_ERR_POS) |
- ((CONFIG_IRQ_EPPI0_ERR - 7) << IRQ_EPPI0_ERR_POS) |
- ((CONFIG_IRQ_SPORT0_ERR - 7) << IRQ_SPORT0_ERR_POS) |
- ((CONFIG_IRQ_SPORT1_ERR - 7) << IRQ_SPORT1_ERR_POS) |
- ((CONFIG_IRQ_SPI0_ERR - 7) << IRQ_SPI0_ERR_POS) |
- ((CONFIG_IRQ_UART0_ERR - 7) << IRQ_UART0_ERR_POS) |
- ((CONFIG_IRQ_RTC - 7) << IRQ_RTC_POS));
-
- bfin_write_SIC_IAR1(((CONFIG_IRQ_EPPI0 - 7) << IRQ_EPPI0_POS) |
- ((CONFIG_IRQ_SPORT0_RX - 7) << IRQ_SPORT0_RX_POS) |
- ((CONFIG_IRQ_SPORT0_TX - 7) << IRQ_SPORT0_TX_POS) |
- ((CONFIG_IRQ_SPORT1_RX - 7) << IRQ_SPORT1_RX_POS) |
- ((CONFIG_IRQ_SPORT1_TX - 7) << IRQ_SPORT1_TX_POS) |
- ((CONFIG_IRQ_SPI0 - 7) << IRQ_SPI0_POS) |
- ((CONFIG_IRQ_UART0_RX - 7) << IRQ_UART0_RX_POS) |
- ((CONFIG_IRQ_UART0_TX - 7) << IRQ_UART0_TX_POS));
-
- bfin_write_SIC_IAR2(((CONFIG_IRQ_TIMER8 - 7) << IRQ_TIMER8_POS) |
- ((CONFIG_IRQ_TIMER9 - 7) << IRQ_TIMER9_POS) |
- ((CONFIG_IRQ_PINT0 - 7) << IRQ_PINT0_POS) |
- ((CONFIG_IRQ_PINT1 - 7) << IRQ_PINT1_POS) |
- ((CONFIG_IRQ_MDMAS0 - 7) << IRQ_MDMAS0_POS) |
- ((CONFIG_IRQ_MDMAS1 - 7) << IRQ_MDMAS1_POS) |
- ((CONFIG_IRQ_WATCHDOG - 7) << IRQ_WATCH_POS));
-
- bfin_write_SIC_IAR3(((CONFIG_IRQ_DMAC1_ERR - 7) << IRQ_DMAC1_ERR_POS) |
- ((CONFIG_IRQ_SPORT2_ERR - 7) << IRQ_SPORT2_ERR_POS) |
- ((CONFIG_IRQ_SPORT3_ERR - 7) << IRQ_SPORT3_ERR_POS) |
- ((CONFIG_IRQ_MXVR_DATA - 7) << IRQ_MXVR_DATA_POS) |
- ((CONFIG_IRQ_SPI1_ERR - 7) << IRQ_SPI1_ERR_POS) |
- ((CONFIG_IRQ_SPI2_ERR - 7) << IRQ_SPI2_ERR_POS) |
- ((CONFIG_IRQ_UART1_ERR - 7) << IRQ_UART1_ERR_POS) |
- ((CONFIG_IRQ_UART2_ERR - 7) << IRQ_UART2_ERR_POS));
-
- bfin_write_SIC_IAR4(((CONFIG_IRQ_CAN0_ERR - 7) << IRQ_CAN0_ERR_POS) |
- ((CONFIG_IRQ_SPORT2_RX - 7) << IRQ_SPORT2_RX_POS) |
- ((CONFIG_IRQ_SPORT2_TX - 7) << IRQ_SPORT2_TX_POS) |
- ((CONFIG_IRQ_SPORT3_RX - 7) << IRQ_SPORT3_RX_POS) |
- ((CONFIG_IRQ_SPORT3_TX - 7) << IRQ_SPORT3_TX_POS) |
- ((CONFIG_IRQ_EPPI1 - 7) << IRQ_EPPI1_POS) |
- ((CONFIG_IRQ_EPPI2 - 7) << IRQ_EPPI2_POS) |
- ((CONFIG_IRQ_SPI1 - 7) << IRQ_SPI1_POS));
-
- bfin_write_SIC_IAR5(((CONFIG_IRQ_SPI2 - 7) << IRQ_SPI2_POS) |
- ((CONFIG_IRQ_UART1_RX - 7) << IRQ_UART1_RX_POS) |
- ((CONFIG_IRQ_UART1_TX - 7) << IRQ_UART1_TX_POS) |
- ((CONFIG_IRQ_ATAPI_RX - 7) << IRQ_ATAPI_RX_POS) |
- ((CONFIG_IRQ_ATAPI_TX - 7) << IRQ_ATAPI_TX_POS) |
- ((CONFIG_IRQ_TWI0 - 7) << IRQ_TWI0_POS) |
- ((CONFIG_IRQ_TWI1 - 7) << IRQ_TWI1_POS) |
- ((CONFIG_IRQ_CAN0_RX - 7) << IRQ_CAN0_RX_POS));
-
- bfin_write_SIC_IAR6(((CONFIG_IRQ_CAN0_TX - 7) << IRQ_CAN0_TX_POS) |
- ((CONFIG_IRQ_MDMAS2 - 7) << IRQ_MDMAS2_POS) |
- ((CONFIG_IRQ_MDMAS3 - 7) << IRQ_MDMAS3_POS) |
- ((CONFIG_IRQ_MXVR_ERR - 7) << IRQ_MXVR_ERR_POS) |
- ((CONFIG_IRQ_MXVR_MSG - 7) << IRQ_MXVR_MSG_POS) |
- ((CONFIG_IRQ_MXVR_PKT - 7) << IRQ_MXVR_PKT_POS) |
- ((CONFIG_IRQ_EPPI1_ERR - 7) << IRQ_EPPI1_ERR_POS) |
- ((CONFIG_IRQ_EPPI2_ERR - 7) << IRQ_EPPI2_ERR_POS));
-
- bfin_write_SIC_IAR7(((CONFIG_IRQ_UART3_ERR - 7) << IRQ_UART3_ERR_POS) |
- ((CONFIG_IRQ_HOST_ERR - 7) << IRQ_HOST_ERR_POS) |
- ((CONFIG_IRQ_PIXC_ERR - 7) << IRQ_PIXC_ERR_POS) |
- ((CONFIG_IRQ_NFC_ERR - 7) << IRQ_NFC_ERR_POS) |
- ((CONFIG_IRQ_ATAPI_ERR - 7) << IRQ_ATAPI_ERR_POS) |
- ((CONFIG_IRQ_CAN1_ERR - 7) << IRQ_CAN1_ERR_POS) |
- ((CONFIG_IRQ_HS_DMA_ERR - 7) << IRQ_HS_DMA_ERR_POS));
-
- bfin_write_SIC_IAR8(((CONFIG_IRQ_PIXC_IN0 - 7) << IRQ_PIXC_IN1_POS) |
- ((CONFIG_IRQ_PIXC_IN1 - 7) << IRQ_PIXC_IN1_POS) |
- ((CONFIG_IRQ_PIXC_OUT - 7) << IRQ_PIXC_OUT_POS) |
- ((CONFIG_IRQ_SDH - 7) << IRQ_SDH_POS) |
- ((CONFIG_IRQ_CNT - 7) << IRQ_CNT_POS) |
- ((CONFIG_IRQ_KEY - 7) << IRQ_KEY_POS) |
- ((CONFIG_IRQ_CAN1_RX - 7) << IRQ_CAN1_RX_POS) |
- ((CONFIG_IRQ_CAN1_TX - 7) << IRQ_CAN1_TX_POS));
-
- bfin_write_SIC_IAR9(((CONFIG_IRQ_SDH_MASK0 - 7) << IRQ_SDH_MASK0_POS) |
- ((CONFIG_IRQ_SDH_MASK1 - 7) << IRQ_SDH_MASK1_POS) |
- ((CONFIG_IRQ_USB_INT0 - 7) << IRQ_USB_INT0_POS) |
- ((CONFIG_IRQ_USB_INT1 - 7) << IRQ_USB_INT1_POS) |
- ((CONFIG_IRQ_USB_INT2 - 7) << IRQ_USB_INT2_POS) |
- ((CONFIG_IRQ_USB_DMA - 7) << IRQ_USB_DMA_POS) |
- ((CONFIG_IRQ_OTPSEC - 7) << IRQ_OTPSEC_POS));
-
- bfin_write_SIC_IAR10(((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) |
- ((CONFIG_IRQ_TIMER1 - 7) << IRQ_TIMER1_POS));
-
- bfin_write_SIC_IAR11(((CONFIG_IRQ_TIMER2 - 7) << IRQ_TIMER2_POS) |
- ((CONFIG_IRQ_TIMER3 - 7) << IRQ_TIMER3_POS) |
- ((CONFIG_IRQ_TIMER4 - 7) << IRQ_TIMER4_POS) |
- ((CONFIG_IRQ_TIMER5 - 7) << IRQ_TIMER5_POS) |
- ((CONFIG_IRQ_TIMER6 - 7) << IRQ_TIMER6_POS) |
- ((CONFIG_IRQ_TIMER7 - 7) << IRQ_TIMER7_POS) |
- ((CONFIG_IRQ_PINT2 - 7) << IRQ_PINT2_POS) |
- ((CONFIG_IRQ_PINT3 - 7) << IRQ_PINT3_POS));
-
- SSYNC();
-}
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0
-if (BF561)
-
-source "arch/blackfin/mach-bf561/boards/Kconfig"
-
-menu "BF561 Specific Configuration"
-
-if (!SMP)
-
-comment "Core B Support"
-
-config BF561_COREB
- bool "Enable Core B loader"
- default y
-
-endif
-
-comment "Interrupt Priority Assignment"
-
-menu "Priority"
-
-config IRQ_PLL_WAKEUP
- int "PLL Wakeup Interrupt"
- default 7
-config IRQ_DMA1_ERROR
- int "DMA1 Error (generic)"
- default 7
-config IRQ_DMA2_ERROR
- int "DMA2 Error (generic)"
- default 7
-config IRQ_IMDMA_ERROR
- int "IMDMA Error (generic)"
- default 7
-config IRQ_PPI0_ERROR
- int "PPI0 Error Interrupt"
- default 7
-config IRQ_PPI1_ERROR
- int "PPI1 Error Interrupt"
- default 7
-config IRQ_SPORT0_ERROR
- int "SPORT0 Error Interrupt"
- default 7
-config IRQ_SPORT1_ERROR
- int "SPORT1 Error Interrupt"
- default 7
-config IRQ_SPI_ERROR
- int "SPI Error Interrupt"
- default 7
-config IRQ_UART_ERROR
- int "UART Error Interrupt"
- default 7
-config IRQ_RESERVED_ERROR
- int "Reserved Interrupt"
- default 7
-config IRQ_DMA1_0
- int "DMA1 0 Interrupt(PPI1)"
- default 8
-config IRQ_DMA1_1
- int "DMA1 1 Interrupt(PPI2)"
- default 8
-config IRQ_DMA1_2
- int "DMA1 2 Interrupt"
- default 8
-config IRQ_DMA1_3
- int "DMA1 3 Interrupt"
- default 8
-config IRQ_DMA1_4
- int "DMA1 4 Interrupt"
- default 8
-config IRQ_DMA1_5
- int "DMA1 5 Interrupt"
- default 8
-config IRQ_DMA1_6
- int "DMA1 6 Interrupt"
- default 8
-config IRQ_DMA1_7
- int "DMA1 7 Interrupt"
- default 8
-config IRQ_DMA1_8
- int "DMA1 8 Interrupt"
- default 8
-config IRQ_DMA1_9
- int "DMA1 9 Interrupt"
- default 8
-config IRQ_DMA1_10
- int "DMA1 10 Interrupt"
- default 8
-config IRQ_DMA1_11
- int "DMA1 11 Interrupt"
- default 8
-config IRQ_DMA2_0
- int "DMA2 0 (SPORT0 RX)"
- default 9
-config IRQ_DMA2_1
- int "DMA2 1 (SPORT0 TX)"
- default 9
-config IRQ_DMA2_2
- int "DMA2 2 (SPORT1 RX)"
- default 9
-config IRQ_DMA2_3
- int "DMA2 3 (SPORT2 TX)"
- default 9
-config IRQ_DMA2_4
- int "DMA2 4 (SPI)"
- default 9
-config IRQ_DMA2_5
- int "DMA2 5 (UART RX)"
- default 9
-config IRQ_DMA2_6
- int "DMA2 6 (UART TX)"
- default 9
-config IRQ_DMA2_7
- int "DMA2 7 Interrupt"
- default 9
-config IRQ_DMA2_8
- int "DMA2 8 Interrupt"
- default 9
-config IRQ_DMA2_9
- int "DMA2 9 Interrupt"
- default 9
-config IRQ_DMA2_10
- int "DMA2 10 Interrupt"
- default 9
-config IRQ_DMA2_11
- int "DMA2 11 Interrupt"
- default 9
-config IRQ_TIMER0
- int "TIMER 0 Interrupt"
- default 7 if TICKSOURCE_GPTMR0
- default 8
-config IRQ_TIMER1
- int "TIMER 1 Interrupt"
- default 10
-config IRQ_TIMER2
- int "TIMER 2 Interrupt"
- default 10
-config IRQ_TIMER3
- int "TIMER 3 Interrupt"
- default 10
-config IRQ_TIMER4
- int "TIMER 4 Interrupt"
- default 10
-config IRQ_TIMER5
- int "TIMER 5 Interrupt"
- default 10
-config IRQ_TIMER6
- int "TIMER 6 Interrupt"
- default 10
-config IRQ_TIMER7
- int "TIMER 7 Interrupt"
- default 10
-config IRQ_TIMER8
- int "TIMER 8 Interrupt"
- default 10
-config IRQ_TIMER9
- int "TIMER 9 Interrupt"
- default 10
-config IRQ_TIMER10
- int "TIMER 10 Interrupt"
- default 10
-config IRQ_TIMER11
- int "TIMER 11 Interrupt"
- default 10
-config IRQ_PROG0_INTA
- int "Programmable Flags0 A (8)"
- default 11
-config IRQ_PROG0_INTB
- int "Programmable Flags0 B (8)"
- default 11
-config IRQ_PROG1_INTA
- int "Programmable Flags1 A (8)"
- default 11
-config IRQ_PROG1_INTB
- int "Programmable Flags1 B (8)"
- default 11
-config IRQ_PROG2_INTA
- int "Programmable Flags2 A (8)"
- default 11
-config IRQ_PROG2_INTB
- int "Programmable Flags2 B (8)"
- default 11
-config IRQ_DMA1_WRRD0
- int "MDMA1 0 write/read INT"
- default 8
-config IRQ_DMA1_WRRD1
- int "MDMA1 1 write/read INT"
- default 8
-config IRQ_DMA2_WRRD0
- int "MDMA2 0 write/read INT"
- default 9
-config IRQ_DMA2_WRRD1
- int "MDMA2 1 write/read INT"
- default 9
-config IRQ_IMDMA_WRRD0
- int "IMDMA 0 write/read INT"
- default 12
-config IRQ_IMDMA_WRRD1
- int "IMDMA 1 write/read INT"
- default 12
-config IRQ_WDTIMER
- int "Watch Dog Timer"
- default 13
-
- help
- Enter the priority numbers between 7-13 ONLY. Others are Reserved.
- This applies to all the above. It is not recommended to assign the
- highest priority number 7 to UART or any other device.
-
-endmenu
-
-endmenu
-
-endif
+++ /dev/null
-#
-# arch/blackfin/mach-bf561/Makefile
-#
-
-obj-y := ints-priority.o dma.o
-
-obj-$(CONFIG_BF561_COREB) += coreb.o
-obj-$(CONFIG_SMP) += smp.o secondary.o atomic.o
-obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
+++ /dev/null
-/*
- * Copyright 2007-2008 Analog Devices Inc.
- * Philippe Gerum <rpm@xenomai.org>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/linkage.h>
-#include <asm/blackfin.h>
-#include <asm/cache.h>
-#include <asm/asm-offsets.h>
-#include <asm/rwlock.h>
-#include <asm/cplb.h>
-
-.text
-
-.macro coreslot_loadaddr reg:req
- \reg\().l = _corelock;
- \reg\().h = _corelock;
-.endm
-
-.macro safe_testset addr:req, scratch:req
-#if ANOMALY_05000477
- cli \scratch;
- testset (\addr);
- sti \scratch;
-#else
- testset (\addr);
-#endif
-.endm
-
-/*
- * r0 = address of atomic data to flush and invalidate (32bit).
- *
- * Clear interrupts and return the old mask.
- * We assume that no atomic data can span cachelines.
- *
- * Clobbers: r2:0, p0
- */
-ENTRY(_get_core_lock)
- r1 = -L1_CACHE_BYTES;
- r1 = r0 & r1;
- cli r0;
- coreslot_loadaddr p0;
-.Lretry_corelock:
- safe_testset p0, r2;
- if cc jump .Ldone_corelock;
- SSYNC(r2);
- jump .Lretry_corelock
-.Ldone_corelock:
- p0 = r1;
- /* flush core internal write buffer before invalidate dcache */
- CSYNC(r2);
- flushinv[p0];
- SSYNC(r2);
- rts;
-ENDPROC(_get_core_lock)
-
-/*
- * r0 = address of atomic data in uncacheable memory region (32bit).
- *
- * Clear interrupts and return the old mask.
- *
- * Clobbers: r0, p0
- */
-ENTRY(_get_core_lock_noflush)
- cli r0;
- coreslot_loadaddr p0;
-.Lretry_corelock_noflush:
- safe_testset p0, r2;
- if cc jump .Ldone_corelock_noflush;
- SSYNC(r2);
- jump .Lretry_corelock_noflush
-.Ldone_corelock_noflush:
- /*
- * SMP kgdb runs into dead loop without NOP here, when one core
- * single steps over get_core_lock_noflush and the other executes
- * get_core_lock as a slave node.
- */
- nop;
- CSYNC(r2);
- rts;
-ENDPROC(_get_core_lock_noflush)
-
-/*
- * r0 = interrupt mask to restore.
- * r1 = address of atomic data to flush and invalidate (32bit).
- *
- * Interrupts are masked on entry (see _get_core_lock).
- * Clobbers: r2:0, p0
- */
-ENTRY(_put_core_lock)
- /* Write-through cache assumed, so no flush needed here. */
- coreslot_loadaddr p0;
- r1 = 0;
- [p0] = r1;
- SSYNC(r2);
- sti r0;
- rts;
-ENDPROC(_put_core_lock)
-
-#ifdef __ARCH_SYNC_CORE_DCACHE
-
-ENTRY(___raw_smp_mark_barrier_asm)
- [--sp] = rets;
- [--sp] = ( r7:5 );
- [--sp] = r0;
- [--sp] = p1;
- [--sp] = p0;
- call _get_core_lock_noflush;
-
- /*
- * Calculate current core mask
- */
- GET_CPUID(p1, r7);
- r6 = 1;
- r6 <<= r7;
-
- /*
- * Set bit of other cores in barrier mask. Don't change current core bit.
- */
- p1.l = _barrier_mask;
- p1.h = _barrier_mask;
- r7 = [p1];
- r5 = r7 & r6;
- r7 = ~r6;
- cc = r5 == 0;
- if cc jump 1f;
- r7 = r7 | r6;
-1:
- [p1] = r7;
- SSYNC(r2);
-
- call _put_core_lock;
- p0 = [sp++];
- p1 = [sp++];
- r0 = [sp++];
- ( r7:5 ) = [sp++];
- rets = [sp++];
- rts;
-ENDPROC(___raw_smp_mark_barrier_asm)
-
-ENTRY(___raw_smp_check_barrier_asm)
- [--sp] = rets;
- [--sp] = ( r7:5 );
- [--sp] = r0;
- [--sp] = p1;
- [--sp] = p0;
- call _get_core_lock_noflush;
-
- /*
- * Calculate current core mask
- */
- GET_CPUID(p1, r7);
- r6 = 1;
- r6 <<= r7;
-
- /*
- * Clear current core bit in barrier mask if it is set.
- */
- p1.l = _barrier_mask;
- p1.h = _barrier_mask;
- r7 = [p1];
- r5 = r7 & r6;
- cc = r5 == 0;
- if cc jump 1f;
- r6 = ~r6;
- r7 = r7 & r6;
- [p1] = r7;
- SSYNC(r2);
-
- call _put_core_lock;
-
- /*
- * Invalidate the entire D-cache of current core.
- */
- sp += -12;
- call _resync_core_dcache
- sp += 12;
- jump 2f;
-1:
- call _put_core_lock;
-2:
- p0 = [sp++];
- p1 = [sp++];
- r0 = [sp++];
- ( r7:5 ) = [sp++];
- rets = [sp++];
- rts;
-ENDPROC(___raw_smp_check_barrier_asm)
-
-/*
- * r0 = irqflags
- * r1 = address of atomic data
- *
- * Clobbers: r2:0, p1:0
- */
-_start_lock_coherent:
-
- [--sp] = rets;
- [--sp] = ( r7:6 );
- r7 = r0;
- p1 = r1;
-
- /*
- * Determine whether the atomic data was previously
- * owned by another CPU (=r6).
- */
- GET_CPUID(p0, r2);
- r1 = 1;
- r1 <<= r2;
- r2 = ~r1;
-
- r1 = [p1];
- r1 >>= 28; /* CPU fingerprints are stored in the high nibble. */
- r6 = r1 & r2;
- r1 = [p1];
- r1 <<= 4;
- r1 >>= 4;
- [p1] = r1;
-
- /*
- * Release the core lock now, but keep IRQs disabled while we are
- * performing the remaining housekeeping chores for the current CPU.
- */
- coreslot_loadaddr p0;
- r1 = 0;
- [p0] = r1;
-
- /*
- * If another CPU has owned the same atomic section before us,
- * then our D-cached copy of the shared data protected by the
- * current spin/write_lock may be obsolete.
- */
- cc = r6 == 0;
- if cc jump .Lcache_synced
-
- /*
- * Invalidate the entire D-cache of the current core.
- */
- sp += -12;
- call _resync_core_dcache
- sp += 12;
-
-.Lcache_synced:
- SSYNC(r2);
- sti r7;
- ( r7:6 ) = [sp++];
- rets = [sp++];
- rts
-
-/*
- * r0 = irqflags
- * r1 = address of atomic data
- *
- * Clobbers: r2:0, p1:0
- */
-_end_lock_coherent:
-
- p1 = r1;
- GET_CPUID(p0, r2);
- r2 += 28;
- r1 = 1;
- r1 <<= r2;
- r2 = [p1];
- r2 = r1 | r2;
- [p1] = r2;
- r1 = p1;
- jump _put_core_lock;
-
-#endif /* __ARCH_SYNC_CORE_DCACHE */
-
-/*
- * r0 = &spinlock->lock
- *
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_spin_is_locked_asm)
- p1 = r0;
- [--sp] = rets;
- call _get_core_lock;
- r3 = [p1];
- cc = bittst( r3, 0 );
- r3 = cc;
- r1 = p1;
- call _put_core_lock;
- rets = [sp++];
- r0 = r3;
- rts;
-ENDPROC(___raw_spin_is_locked_asm)
-
-/*
- * r0 = &spinlock->lock
- *
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_spin_lock_asm)
- p1 = r0;
- [--sp] = rets;
-.Lretry_spinlock:
- call _get_core_lock;
- r1 = p1;
- r2 = [p1];
- cc = bittst( r2, 0 );
- if cc jump .Lbusy_spinlock
-#ifdef __ARCH_SYNC_CORE_DCACHE
- r3 = p1;
- bitset ( r2, 0 ); /* Raise the lock bit. */
- [p1] = r2;
- call _start_lock_coherent
-#else
- r2 = 1;
- [p1] = r2;
- call _put_core_lock;
-#endif
- rets = [sp++];
- rts;
-
-.Lbusy_spinlock:
- /* We don't touch the atomic area if busy, so that flush
- will behave like nop in _put_core_lock. */
- call _put_core_lock;
- SSYNC(r2);
- r0 = p1;
- jump .Lretry_spinlock
-ENDPROC(___raw_spin_lock_asm)
-
-/*
- * r0 = &spinlock->lock
- *
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_spin_trylock_asm)
- p1 = r0;
- [--sp] = rets;
- call _get_core_lock;
- r1 = p1;
- r3 = [p1];
- cc = bittst( r3, 0 );
- if cc jump .Lfailed_trylock
-#ifdef __ARCH_SYNC_CORE_DCACHE
- bitset ( r3, 0 ); /* Raise the lock bit. */
- [p1] = r3;
- call _start_lock_coherent
-#else
- r2 = 1;
- [p1] = r2;
- call _put_core_lock;
-#endif
- r0 = 1;
- rets = [sp++];
- rts;
-.Lfailed_trylock:
- call _put_core_lock;
- r0 = 0;
- rets = [sp++];
- rts;
-ENDPROC(___raw_spin_trylock_asm)
-
-/*
- * r0 = &spinlock->lock
- *
- * Clobbers: r2:0, p1:0
- */
-ENTRY(___raw_spin_unlock_asm)
- p1 = r0;
- [--sp] = rets;
- call _get_core_lock;
- r2 = [p1];
- bitclr ( r2, 0 );
- [p1] = r2;
- r1 = p1;
-#ifdef __ARCH_SYNC_CORE_DCACHE
- call _end_lock_coherent
-#else
- call _put_core_lock;
-#endif
- rets = [sp++];
- rts;
-ENDPROC(___raw_spin_unlock_asm)
-
-/*
- * r0 = &rwlock->lock
- *
- * Clobbers: r2:0, p1:0
- */
-ENTRY(___raw_read_lock_asm)
- p1 = r0;
- [--sp] = rets;
- call _get_core_lock;
-.Lrdlock_try:
- r1 = [p1];
- r1 += -1;
- [p1] = r1;
- cc = r1 < 0;
- if cc jump .Lrdlock_failed
- r1 = p1;
-#ifdef __ARCH_SYNC_CORE_DCACHE
- call _start_lock_coherent
-#else
- call _put_core_lock;
-#endif
- rets = [sp++];
- rts;
-
-.Lrdlock_failed:
- r1 += 1;
- [p1] = r1;
-.Lrdlock_wait:
- r1 = p1;
- call _put_core_lock;
- SSYNC(r2);
- r0 = p1;
- call _get_core_lock;
- r1 = [p1];
- cc = r1 < 2;
- if cc jump .Lrdlock_wait;
- jump .Lrdlock_try
-ENDPROC(___raw_read_lock_asm)
-
-/*
- * r0 = &rwlock->lock
- *
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_read_trylock_asm)
- p1 = r0;
- [--sp] = rets;
- call _get_core_lock;
- r1 = [p1];
- cc = r1 <= 0;
- if cc jump .Lfailed_tryrdlock;
- r1 += -1;
- [p1] = r1;
- r1 = p1;
-#ifdef __ARCH_SYNC_CORE_DCACHE
- call _start_lock_coherent
-#else
- call _put_core_lock;
-#endif
- rets = [sp++];
- r0 = 1;
- rts;
-.Lfailed_tryrdlock:
- r1 = p1;
- call _put_core_lock;
- rets = [sp++];
- r0 = 0;
- rts;
-ENDPROC(___raw_read_trylock_asm)
-
-/*
- * r0 = &rwlock->lock
- *
- * Note: Processing controlled by a reader lock should not have
- * any side-effect on cache issues with the other core, so we
- * just release the core lock and exit (no _end_lock_coherent).
- *
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_read_unlock_asm)
- p1 = r0;
- [--sp] = rets;
- call _get_core_lock;
- r1 = [p1];
- r1 += 1;
- [p1] = r1;
- r1 = p1;
- call _put_core_lock;
- rets = [sp++];
- rts;
-ENDPROC(___raw_read_unlock_asm)
-
-/*
- * r0 = &rwlock->lock
- *
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_write_lock_asm)
- p1 = r0;
- r3.l = lo(RW_LOCK_BIAS);
- r3.h = hi(RW_LOCK_BIAS);
- [--sp] = rets;
- call _get_core_lock;
-.Lwrlock_try:
- r1 = [p1];
- r1 = r1 - r3;
-#ifdef __ARCH_SYNC_CORE_DCACHE
- r2 = r1;
- r2 <<= 4;
- r2 >>= 4;
- cc = r2 == 0;
-#else
- cc = r1 == 0;
-#endif
- if !cc jump .Lwrlock_wait
- [p1] = r1;
- r1 = p1;
-#ifdef __ARCH_SYNC_CORE_DCACHE
- call _start_lock_coherent
-#else
- call _put_core_lock;
-#endif
- rets = [sp++];
- rts;
-
-.Lwrlock_wait:
- r1 = p1;
- call _put_core_lock;
- SSYNC(r2);
- r0 = p1;
- call _get_core_lock;
- r1 = [p1];
-#ifdef __ARCH_SYNC_CORE_DCACHE
- r1 <<= 4;
- r1 >>= 4;
-#endif
- cc = r1 == r3;
- if !cc jump .Lwrlock_wait;
- jump .Lwrlock_try
-ENDPROC(___raw_write_lock_asm)
-
-/*
- * r0 = &rwlock->lock
- *
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_write_trylock_asm)
- p1 = r0;
- [--sp] = rets;
- call _get_core_lock;
- r1 = [p1];
- r2.l = lo(RW_LOCK_BIAS);
- r2.h = hi(RW_LOCK_BIAS);
- cc = r1 == r2;
- if !cc jump .Lfailed_trywrlock;
-#ifdef __ARCH_SYNC_CORE_DCACHE
- r1 >>= 28;
- r1 <<= 28;
-#else
- r1 = 0;
-#endif
- [p1] = r1;
- r1 = p1;
-#ifdef __ARCH_SYNC_CORE_DCACHE
- call _start_lock_coherent
-#else
- call _put_core_lock;
-#endif
- rets = [sp++];
- r0 = 1;
- rts;
-
-.Lfailed_trywrlock:
- r1 = p1;
- call _put_core_lock;
- rets = [sp++];
- r0 = 0;
- rts;
-ENDPROC(___raw_write_trylock_asm)
-
-/*
- * r0 = &rwlock->lock
- *
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_write_unlock_asm)
- p1 = r0;
- r3.l = lo(RW_LOCK_BIAS);
- r3.h = hi(RW_LOCK_BIAS);
- [--sp] = rets;
- call _get_core_lock;
- r1 = [p1];
- r1 = r1 + r3;
- [p1] = r1;
- r1 = p1;
-#ifdef __ARCH_SYNC_CORE_DCACHE
- call _end_lock_coherent
-#else
- call _put_core_lock;
-#endif
- rets = [sp++];
- rts;
-ENDPROC(___raw_write_unlock_asm)
-
-/*
- * r0 = ptr
- * r1 = value
- *
- * ADD a signed value to a 32bit word and return the new value atomically.
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_atomic_add_asm)
- p1 = r0;
- r3 = r1;
- [--sp] = rets;
- call _get_core_lock;
- r2 = [p1];
- r3 = r3 + r2;
- [p1] = r3;
- r1 = p1;
- call _put_core_lock;
- r0 = r3;
- rets = [sp++];
- rts;
-ENDPROC(___raw_atomic_add_asm)
-
-/*
- * r0 = ptr
- * r1 = value
- *
- * ADD a signed value to a 32bit word and return the old value atomically.
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_atomic_xadd_asm)
- p1 = r0;
- r3 = r1;
- [--sp] = rets;
- call _get_core_lock;
- r3 = [p1];
- r2 = r3 + r2;
- [p1] = r2;
- r1 = p1;
- call _put_core_lock;
- r0 = r3;
- rets = [sp++];
- rts;
-ENDPROC(___raw_atomic_add_asm)
-
-/*
- * r0 = ptr
- * r1 = mask
- *
- * AND the mask bits from a 32bit word and return the old 32bit value
- * atomically.
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_atomic_and_asm)
- p1 = r0;
- r3 = r1;
- [--sp] = rets;
- call _get_core_lock;
- r3 = [p1];
- r2 = r2 & r3;
- [p1] = r2;
- r1 = p1;
- call _put_core_lock;
- r0 = r3;
- rets = [sp++];
- rts;
-ENDPROC(___raw_atomic_and_asm)
-
-/*
- * r0 = ptr
- * r1 = mask
- *
- * OR the mask bits into a 32bit word and return the old 32bit value
- * atomically.
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_atomic_or_asm)
- p1 = r0;
- r3 = r1;
- [--sp] = rets;
- call _get_core_lock;
- r3 = [p1];
- r2 = r2 | r3;
- [p1] = r2;
- r1 = p1;
- call _put_core_lock;
- r0 = r3;
- rets = [sp++];
- rts;
-ENDPROC(___raw_atomic_or_asm)
-
-/*
- * r0 = ptr
- * r1 = mask
- *
- * XOR the mask bits with a 32bit word and return the old 32bit value
- * atomically.
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_atomic_xor_asm)
- p1 = r0;
- r3 = r1;
- [--sp] = rets;
- call _get_core_lock;
- r3 = [p1];
- r2 = r2 ^ r3;
- [p1] = r2;
- r1 = p1;
- call _put_core_lock;
- r0 = r3;
- rets = [sp++];
- rts;
-ENDPROC(___raw_atomic_xor_asm)
-
-/*
- * r0 = ptr
- * r1 = mask
- *
- * Perform a logical AND between the mask bits and a 32bit word, and
- * return the masked value. We need this on this architecture in
- * order to invalidate the local cache before testing.
- *
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_atomic_test_asm)
- p1 = r0;
- r3 = r1;
- r1 = -L1_CACHE_BYTES;
- r1 = r0 & r1;
- p0 = r1;
- /* flush core internal write buffer before invalidate dcache */
- CSYNC(r2);
- flushinv[p0];
- SSYNC(r2);
- r0 = [p1];
- r0 = r0 & r3;
- rts;
-ENDPROC(___raw_atomic_test_asm)
-
-/*
- * r0 = ptr
- * r1 = value
- *
- * Swap *ptr with value and return the old 32bit value atomically.
- * Clobbers: r3:0, p1:0
- */
-#define __do_xchg(src, dst) \
- p1 = r0; \
- r3 = r1; \
- [--sp] = rets; \
- call _get_core_lock; \
- r2 = src; \
- dst = r3; \
- r3 = r2; \
- r1 = p1; \
- call _put_core_lock; \
- r0 = r3; \
- rets = [sp++]; \
- rts;
-
-ENTRY(___raw_xchg_1_asm)
- __do_xchg(b[p1] (z), b[p1])
-ENDPROC(___raw_xchg_1_asm)
-
-ENTRY(___raw_xchg_2_asm)
- __do_xchg(w[p1] (z), w[p1])
-ENDPROC(___raw_xchg_2_asm)
-
-ENTRY(___raw_xchg_4_asm)
- __do_xchg([p1], [p1])
-ENDPROC(___raw_xchg_4_asm)
-
-/*
- * r0 = ptr
- * r1 = new
- * r2 = old
- *
- * Swap *ptr with new if *ptr == old and return the previous *ptr
- * value atomically.
- *
- * Clobbers: r3:0, p1:0
- */
-#define __do_cmpxchg(src, dst) \
- [--sp] = rets; \
- [--sp] = r4; \
- p1 = r0; \
- r3 = r1; \
- r4 = r2; \
- call _get_core_lock; \
- r2 = src; \
- cc = r2 == r4; \
- if !cc jump 1f; \
- dst = r3; \
- 1: r3 = r2; \
- r1 = p1; \
- call _put_core_lock; \
- r0 = r3; \
- r4 = [sp++]; \
- rets = [sp++]; \
- rts;
-
-ENTRY(___raw_cmpxchg_1_asm)
- __do_cmpxchg(b[p1] (z), b[p1])
-ENDPROC(___raw_cmpxchg_1_asm)
-
-ENTRY(___raw_cmpxchg_2_asm)
- __do_cmpxchg(w[p1] (z), w[p1])
-ENDPROC(___raw_cmpxchg_2_asm)
-
-ENTRY(___raw_cmpxchg_4_asm)
- __do_cmpxchg([p1], [p1])
-ENDPROC(___raw_cmpxchg_4_asm)
-
-/*
- * r0 = ptr
- * r1 = bitnr
- *
- * Set a bit in a 32bit word and return the old 32bit value atomically.
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_bit_set_asm)
- r2 = r1;
- r1 = 1;
- r1 <<= r2;
- jump ___raw_atomic_or_asm
-ENDPROC(___raw_bit_set_asm)
-
-/*
- * r0 = ptr
- * r1 = bitnr
- *
- * Clear a bit in a 32bit word and return the old 32bit value atomically.
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_bit_clear_asm)
- r2 = 1;
- r2 <<= r1;
- r1 = ~r2;
- jump ___raw_atomic_and_asm
-ENDPROC(___raw_bit_clear_asm)
-
-/*
- * r0 = ptr
- * r1 = bitnr
- *
- * Toggle a bit in a 32bit word and return the old 32bit value atomically.
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_bit_toggle_asm)
- r2 = r1;
- r1 = 1;
- r1 <<= r2;
- jump ___raw_atomic_xor_asm
-ENDPROC(___raw_bit_toggle_asm)
-
-/*
- * r0 = ptr
- * r1 = bitnr
- *
- * Test-and-set a bit in a 32bit word and return the old bit value atomically.
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_bit_test_set_asm)
- [--sp] = rets;
- [--sp] = r1;
- call ___raw_bit_set_asm
- r1 = [sp++];
- r2 = 1;
- r2 <<= r1;
- r0 = r0 & r2;
- cc = r0 == 0;
- if cc jump 1f
- r0 = 1;
-1:
- rets = [sp++];
- rts;
-ENDPROC(___raw_bit_test_set_asm)
-
-/*
- * r0 = ptr
- * r1 = bitnr
- *
- * Test-and-clear a bit in a 32bit word and return the old bit value atomically.
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_bit_test_clear_asm)
- [--sp] = rets;
- [--sp] = r1;
- call ___raw_bit_clear_asm
- r1 = [sp++];
- r2 = 1;
- r2 <<= r1;
- r0 = r0 & r2;
- cc = r0 == 0;
- if cc jump 1f
- r0 = 1;
-1:
- rets = [sp++];
- rts;
-ENDPROC(___raw_bit_test_clear_asm)
-
-/*
- * r0 = ptr
- * r1 = bitnr
- *
- * Test-and-toggle a bit in a 32bit word,
- * and return the old bit value atomically.
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_bit_test_toggle_asm)
- [--sp] = rets;
- [--sp] = r1;
- call ___raw_bit_toggle_asm
- r1 = [sp++];
- r2 = 1;
- r2 <<= r1;
- r0 = r0 & r2;
- cc = r0 == 0;
- if cc jump 1f
- r0 = 1;
-1:
- rets = [sp++];
- rts;
-ENDPROC(___raw_bit_test_toggle_asm)
-
-/*
- * r0 = ptr
- * r1 = bitnr
- *
- * Test a bit in a 32bit word and return its value.
- * We need this on this architecture in order to invalidate
- * the local cache before testing.
- *
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_bit_test_asm)
- r2 = r1;
- r1 = 1;
- r1 <<= r2;
- jump ___raw_atomic_test_asm
-ENDPROC(___raw_bit_test_asm)
-
-/*
- * r0 = ptr
- *
- * Fetch and return an uncached 32bit value.
- *
- * Clobbers: r2:0, p1:0
- */
-ENTRY(___raw_uncached_fetch_asm)
- p1 = r0;
- r1 = -L1_CACHE_BYTES;
- r1 = r0 & r1;
- p0 = r1;
- /* flush core internal write buffer before invalidate dcache */
- CSYNC(r2);
- flushinv[p0];
- SSYNC(r2);
- r0 = [p1];
- rts;
-ENDPROC(___raw_uncached_fetch_asm)
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0
-choice
- prompt "System type"
- default BFIN561_EZKIT
- help
- Select your board!
-
-config BFIN561_EZKIT
- bool "BF561-EZKIT"
- help
- BF561-EZKIT-LITE board support.
-
-config BFIN561_TEPLA
- bool "BF561-TEPLA"
- help
- BF561-TEPLA board support.
-
-config BFIN561_BLUETECHNIX_CM
- bool "Bluetechnix CM-BF561"
- help
- CM-BF561 support for EVAL- and DEV-Board.
-
-config BFIN561_ACVILON
- bool "BF561-ACVILON"
- help
- BF561-ACVILON System On Module support (SO-DIMM 144).
- For more information about Acvilon BF561 SoM
- please go to http://www.niistt.ru/
-
-endchoice
+++ /dev/null
-#
-# arch/blackfin/mach-bf561/boards/Makefile
-#
-
-obj-$(CONFIG_BFIN561_ACVILON) += acvilon.o
-obj-$(CONFIG_BFIN561_BLUETECHNIX_CM) += cm_bf561.o
-obj-$(CONFIG_BFIN561_EZKIT) += ezkit.o
-obj-$(CONFIG_BFIN561_TEPLA) += tepla.o
+++ /dev/null
-/*
- * File: arch/blackfin/mach-bf561/acvilon.c
- * Based on: arch/blackfin/mach-bf561/ezkit.c
- * Author:
- *
- * Created:
- * Description:
- *
- * Modified:
- * Copyright 2004-2006 Analog Devices Inc.
- * Copyright 2009 CJSC "NII STT"
- *
- * Bugs:
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- *
- *
- * For more information about Acvilon BF561 SoM please
- * go to http://www.niistt.ru/
- *
- */
-
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/mtd/rawnand.h>
-#include <linux/mtd/plat-ram.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <linux/gpio.h>
-#include <linux/jiffies.h>
-#include <linux/i2c-pca-platform.h>
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-#include <asm/cacheflush.h>
-#include <linux/i2c.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "Acvilon board";
-
-#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
-#include <linux/usb/isp1760.h>
-static struct resource bfin_isp1760_resources[] = {
- [0] = {
- .start = 0x20000000,
- .end = 0x20000000 + 0x000fffff,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_PF15,
- .end = IRQ_PF15,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
- },
-};
-
-static struct isp1760_platform_data isp1760_priv = {
- .is_isp1761 = 0,
- .port1_disable = 0,
- .bus_width_16 = 1,
- .port1_otg = 0,
- .analog_oc = 0,
- .dack_polarity_high = 0,
- .dreq_polarity_high = 0,
-};
-
-static struct platform_device bfin_isp1760_device = {
- .name = "isp1760-hcd",
- .id = 0,
- .dev = {
- .platform_data = &isp1760_priv,
- },
- .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
- .resource = bfin_isp1760_resources,
-};
-#endif
-
-static struct resource bfin_i2c_pca_resources[] = {
- {
- .name = "pca9564-regs",
- .start = 0x2C000000,
- .end = 0x2C000000 + 16,
- .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
- }, {
-
- .start = IRQ_PF8,
- .end = IRQ_PF8,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
- },
-};
-
-struct i2c_pca9564_pf_platform_data pca9564_platform_data = {
- .gpio = -1,
- .i2c_clock_speed = 330000,
- .timeout = HZ,
-};
-
-/* PCA9564 I2C Bus driver */
-static struct platform_device bfin_i2c_pca_device = {
- .name = "i2c-pca-platform",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_i2c_pca_resources),
- .resource = bfin_i2c_pca_resources,
- .dev = {
- .platform_data = &pca9564_platform_data,
- }
-};
-
-/* I2C devices fitted. */
-static struct i2c_board_info acvilon_i2c_devs[] __initdata = {
- {
- I2C_BOARD_INFO("ds1339", 0x68),
- },
- {
- I2C_BOARD_INFO("tcn75", 0x49),
- },
-};
-
-#if IS_ENABLED(CONFIG_MTD_PLATRAM)
-static struct platdata_mtd_ram mtd_ram_data = {
- .mapname = "rootfs(RAM)",
- .bankwidth = 4,
-};
-
-static struct resource mtd_ram_resource = {
- .start = 0x4000000,
- .end = 0x5ffffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device mtd_ram_device = {
- .name = "mtd-ram",
- .id = 0,
- .dev = {
- .platform_data = &mtd_ram_data,
- },
- .num_resources = 1,
- .resource = &mtd_ram_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SMSC911X)
-#include <linux/smsc911x.h>
-static struct resource smsc911x_resources[] = {
- {
- .name = "smsc911x-memory",
- .start = 0x28000000,
- .end = 0x28000000 + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PF7,
- .end = IRQ_PF7,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
- },
-};
-
-static struct smsc911x_platform_config smsc911x_config = {
- .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS,
- .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
- .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
- .phy_interface = PHY_INTERFACE_MODE_MII,
-};
-
-static struct platform_device smsc911x_device = {
- .name = "smsc911x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smsc911x_resources),
- .resource = smsc911x_resources,
- .dev = {
- .platform_data = &smsc911x_config,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = BFIN_UART_THR,
- .end = BFIN_UART_GCTL + 2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART_TX,
- .end = IRQ_UART_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART_RX,
- .end = IRQ_UART_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART_ERROR,
- .end = IRQ_UART_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART_TX,
- .end = CH_UART_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART_RX,
- .end = CH_UART_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- /* Passed to driver */
- .platform_data = &bfin_uart0_peripherals,
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_NAND_PLATFORM)
-
-static struct mtd_partition bfin_plat_nand_partitions[] = {
- {
- .name = "params(nand)",
- .size = 32 * 1024 * 1024,
- .offset = 0,
- }, {
- .name = "userfs(nand)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- },
-};
-
-#define BFIN_NAND_PLAT_CLE 2
-#define BFIN_NAND_PLAT_ALE 3
-
-static void bfin_plat_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
- unsigned int ctrl)
-{
- struct nand_chip *this = mtd_to_nand(mtd);
-
- if (cmd == NAND_CMD_NONE)
- return;
-
- if (ctrl & NAND_CLE)
- writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_CLE));
- else
- writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_ALE));
-}
-
-#define BFIN_NAND_PLAT_READY GPIO_PF10
-static int bfin_plat_nand_dev_ready(struct mtd_info *mtd)
-{
- return gpio_get_value(BFIN_NAND_PLAT_READY);
-}
-
-static struct platform_nand_data bfin_plat_nand_data = {
- .chip = {
- .nr_chips = 1,
- .chip_delay = 30,
- .partitions = bfin_plat_nand_partitions,
- .nr_partitions = ARRAY_SIZE(bfin_plat_nand_partitions),
- },
- .ctrl = {
- .cmd_ctrl = bfin_plat_nand_cmd_ctrl,
- .dev_ready = bfin_plat_nand_dev_ready,
- },
-};
-
-#define MAX(x, y) (x > y ? x : y)
-static struct resource bfin_plat_nand_resources = {
- .start = 0x24000000,
- .end = 0x24000000 + (1 << MAX(BFIN_NAND_PLAT_CLE, BFIN_NAND_PLAT_ALE)),
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device bfin_async_nand_device = {
- .name = "gen_nand",
- .id = -1,
- .num_resources = 1,
- .resource = &bfin_plat_nand_resources,
- .dev = {
- .platform_data = &bfin_plat_nand_data,
- },
-};
-
-static void bfin_plat_nand_init(void)
-{
- gpio_request(BFIN_NAND_PLAT_READY, "bfin_nand_plat");
-}
-#else
-static void bfin_plat_nand_init(void)
-{
-}
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_DATAFLASH)
-static struct mtd_partition bfin_spi_dataflash_partitions[] = {
- {
- .name = "bootloader",
- .size = 0x4200,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM},
- {
- .name = "u-boot",
- .size = 0x42000,
- .offset = MTDPART_OFS_APPEND,
- },
- {
- .name = "u-boot(params)",
- .size = 0x4200,
- .offset = MTDPART_OFS_APPEND,
- },
- {
- .name = "kernel",
- .size = 0x294000,
- .offset = MTDPART_OFS_APPEND,
- },
- {
- .name = "params",
- .size = 0x42000,
- .offset = MTDPART_OFS_APPEND,
- },
- {
- .name = "rootfs",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct flash_platform_data bfin_spi_dataflash_data = {
- .name = "SPI Dataflash",
- .parts = bfin_spi_dataflash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_dataflash_partitions),
-};
-
-/* DataFlash chip */
-static struct bfin5xx_spi_chip data_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip */
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 3,
- },
-#endif
-#if IS_ENABLED(CONFIG_MTD_DATAFLASH)
- { /* DataFlash chip */
- .modalias = "mtd_dataflash",
- .max_speed_hz = 33250000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 2, /* Framework chip select */
- .platform_data = &bfin_spi_dataflash_data,
- .controller_data = &data_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-};
-
-static struct resource bfin_gpios_resources = {
- .start = 31,
-/* .end = MAX_BLACKFIN_GPIOS - 1, */
- .end = 32,
- .flags = IORESOURCE_IRQ,
-};
-
-static struct platform_device bfin_gpios_device = {
- .name = "simple-gpio",
- .id = -1,
- .num_resources = 1,
- .resource = &bfin_gpios_resources,
-};
-
-static const unsigned int cclk_vlev_datasheet[] = {
- VRPAIR(VLEV_085, 250000000),
- VRPAIR(VLEV_090, 300000000),
- VRPAIR(VLEV_095, 313000000),
- VRPAIR(VLEV_100, 350000000),
- VRPAIR(VLEV_105, 400000000),
- VRPAIR(VLEV_110, 444000000),
- VRPAIR(VLEV_115, 450000000),
- VRPAIR(VLEV_120, 475000000),
- VRPAIR(VLEV_125, 500000000),
- VRPAIR(VLEV_130, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */ ,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-static struct platform_device *acvilon_devices[] __initdata = {
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-
- &bfin_gpios_device,
-
-#if IS_ENABLED(CONFIG_SMSC911X)
- &smsc911x_device,
-#endif
-
- &bfin_i2c_pca_device,
-
-#if IS_ENABLED(CONFIG_MTD_NAND_PLATFORM)
- &bfin_async_nand_device,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PLATRAM)
- &mtd_ram_device,
-#endif
-
-};
-
-static int __init acvilon_init(void)
-{
- int ret;
-
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
-
- bfin_plat_nand_init();
- ret =
- platform_add_devices(acvilon_devices, ARRAY_SIZE(acvilon_devices));
- if (ret < 0)
- return ret;
-
- i2c_register_board_info(0, acvilon_i2c_devs,
- ARRAY_SIZE(acvilon_i2c_devs));
-
- bfin_write_FIO0_FLAG_C(1 << 14);
- msleep(5);
- bfin_write_FIO0_FLAG_S(1 << 14);
-
- spi_register_board_info(bfin_spi_board_info,
- ARRAY_SIZE(bfin_spi_board_info));
- return 0;
-}
-
-arch_initcall(acvilon_init);
-
-static struct platform_device *acvilon_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(acvilon_early_devices,
- ARRAY_SIZE(acvilon_early_devices));
-}
+++ /dev/null
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2008-2009 Bluetechnix
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-#include <linux/usb/isp1362.h>
-#endif
-#include <linux/ata_platform.h>
-#include <linux/irq.h>
-#include <linux/gpio.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-#include <linux/mtd/physmap.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "Bluetechnix CM BF561";
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* all SPI peripherals info goes here */
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00020000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = 0xe0000,
- .offset = 0x20000
- }, {
- .name = "file system(spi)",
- .size = 0x700000,
- .offset = 0x00100000,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p64",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
- {
- .modalias = "ad183x",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 4,
- },
-#endif
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- .mode = SPI_MODE_3,
- },
-#endif
-};
-
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-
-#if IS_ENABLED(CONFIG_FB_HITACHI_TX09)
-static struct platform_device hitachi_fb_device = {
- .name = "hitachi-tx09",
-};
-#endif
-
-
-#if IS_ENABLED(CONFIG_SMC91X)
-#include <linux/smc91x.h>
-
-static struct smc91x_platdata smc91x_info = {
- .flags = SMC91X_USE_8BIT | SMC91X_USE_16BIT | SMC91X_USE_32BIT |
- SMC91X_NOWAIT,
- .leda = RPC_LED_100_10,
- .ledb = RPC_LED_TX_RX,
-};
-
-static struct resource smc91x_resources[] = {
- {
- .name = "smc91x-regs",
- .start = 0x28000300,
- .end = 0x28000300 + 16,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF0,
- .end = IRQ_PF0,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev = {
- .platform_data = &smc91x_info,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SMSC911X)
-#include <linux/smsc911x.h>
-
-static struct resource smsc911x_resources[] = {
- {
- .name = "smsc911x-memory",
- .start = 0x24008000,
- .end = 0x24008000 + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PF43,
- .end = IRQ_PF43,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
- },
-};
-
-static struct smsc911x_platform_config smsc911x_config = {
- .flags = SMSC911X_USE_16BIT,
- .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
- .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
- .phy_interface = PHY_INTERFACE_MODE_MII,
-};
-
-static struct platform_device smsc911x_device = {
- .name = "smsc911x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smsc911x_resources),
- .resource = smsc911x_resources,
- .dev = {
- .platform_data = &smsc911x_config,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
-static struct resource net2272_bfin_resources[] = {
- {
- .start = 0x24000000,
- .end = 0x24000000 + 0x100,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF45,
- .end = IRQ_PF45,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device net2272_bfin_device = {
- .name = "net2272",
- .id = -1,
- .num_resources = ARRAY_SIZE(net2272_bfin_resources),
- .resource = net2272_bfin_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-static struct resource isp1362_hcd_resources[] = {
- {
- .start = 0x24008000,
- .end = 0x24008000,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 0x24008004,
- .end = 0x24008004,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF47,
- .end = IRQ_PF47,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
- },
-};
-
-static struct isp1362_platform_data isp1362_priv = {
- .sel15Kres = 1,
- .clknotstop = 0,
- .oc_enable = 0,
- .int_act_high = 0,
- .int_edge_triggered = 0,
- .remote_wakeup_connected = 0,
- .no_power_switching = 1,
- .power_switching_mode = 0,
-};
-
-static struct platform_device isp1362_hcd_device = {
- .name = "isp1362-hcd",
- .id = 0,
- .dev = {
- .platform_data = &isp1362_priv,
- },
- .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
- .resource = isp1362_hcd_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = BFIN_UART_THR,
- .end = BFIN_UART_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART_TX,
- .end = IRQ_UART_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART_RX,
- .end = IRQ_UART_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART_ERROR,
- .end = IRQ_UART_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART_TX,
- .end = CH_UART_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART_RX,
- .end = CH_UART_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_PATA_PLATFORM)
-#define PATA_INT IRQ_PF46
-
-static struct pata_platform_info bfin_pata_platform_data = {
- .ioport_shift = 2,
-};
-
-static struct resource bfin_pata_resources[] = {
- {
- .start = 0x2400C000,
- .end = 0x2400C001F,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = 0x2400D018,
- .end = 0x2400D01B,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = PATA_INT,
- .end = PATA_INT,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device bfin_pata_device = {
- .name = "pata_platform",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_pata_resources),
- .resource = bfin_pata_resources,
- .dev = {
- .platform_data = &bfin_pata_platform_data,
- }
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
-static struct mtd_partition para_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x40000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0x100000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct physmap_flash_data para_flash_data = {
- .width = 2,
- .parts = para_partitions,
- .nr_parts = ARRAY_SIZE(para_partitions),
-};
-
-static struct resource para_flash_resource = {
- .start = 0x20000000,
- .end = 0x207fffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device para_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = ¶_flash_data,
- },
- .num_resources = 1,
- .resource = ¶_flash_resource,
-};
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
- VRPAIR(VLEV_085, 250000000),
- VRPAIR(VLEV_090, 300000000),
- VRPAIR(VLEV_095, 313000000),
- VRPAIR(VLEV_100, 350000000),
- VRPAIR(VLEV_105, 400000000),
- VRPAIR(VLEV_110, 444000000),
- VRPAIR(VLEV_115, 450000000),
- VRPAIR(VLEV_120, 475000000),
- VRPAIR(VLEV_125, 500000000),
- VRPAIR(VLEV_130, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-static struct platform_device *cm_bf561_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_FB_HITACHI_TX09)
- &hitachi_fb_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
- &isp1362_hcd_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
- &smc91x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SMSC911X)
- &smsc911x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
- &net2272_bfin_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_PATA_PLATFORM)
- &bfin_pata_device,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
- ¶_flash_device,
-#endif
-};
-
-static int __init net2272_init(void)
-{
-#if IS_ENABLED(CONFIG_USB_NET2272)
- int ret;
-
- ret = gpio_request(GPIO_PF46, "net2272");
- if (ret)
- return ret;
-
- /* Reset USB Chip, PF46 */
- gpio_direction_output(GPIO_PF46, 0);
- mdelay(2);
- gpio_set_value(GPIO_PF46, 1);
-#endif
-
- return 0;
-}
-
-static int __init cm_bf561_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- platform_add_devices(cm_bf561_devices, ARRAY_SIZE(cm_bf561_devices));
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
-#endif
-
-#if IS_ENABLED(CONFIG_PATA_PLATFORM)
- irq_set_status_flags(PATA_INT, IRQ_NOAUTOEN);
-#endif
-
- if (net2272_init())
- pr_warning("unable to configure net2272; it probably won't work\n");
-
- return 0;
-}
-
-arch_initcall(cm_bf561_init);
-
-static struct platform_device *cm_bf561_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(cm_bf561_early_devices,
- ARRAY_SIZE(cm_bf561_early_devices));
-}
+++ /dev/null
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <linux/gpio.h>
-#include <linux/delay.h>
-#include <linux/gpio/machine.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "ADI BF561-EZKIT";
-
-#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
-#include <linux/usb/isp1760.h>
-static struct resource bfin_isp1760_resources[] = {
- [0] = {
- .start = 0x2C0F0000,
- .end = 0x203C0000 + 0xfffff,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_PF10,
- .end = IRQ_PF10,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct isp1760_platform_data isp1760_priv = {
- .is_isp1761 = 0,
- .bus_width_16 = 1,
- .port1_otg = 0,
- .analog_oc = 0,
- .dack_polarity_high = 0,
- .dreq_polarity_high = 0,
-};
-
-static struct platform_device bfin_isp1760_device = {
- .name = "isp1760",
- .id = 0,
- .dev = {
- .platform_data = &isp1760_priv,
- },
- .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
- .resource = bfin_isp1760_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-#include <linux/usb/isp1362.h>
-
-static struct resource isp1362_hcd_resources[] = {
- {
- .start = 0x2c060000,
- .end = 0x2c060000,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 0x2c060004,
- .end = 0x2c060004,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF8,
- .end = IRQ_PF8,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
- },
-};
-
-static struct isp1362_platform_data isp1362_priv = {
- .sel15Kres = 1,
- .clknotstop = 0,
- .oc_enable = 0,
- .int_act_high = 0,
- .int_edge_triggered = 0,
- .remote_wakeup_connected = 0,
- .no_power_switching = 1,
- .power_switching_mode = 0,
-};
-
-static struct platform_device isp1362_hcd_device = {
- .name = "isp1362-hcd",
- .id = 0,
- .dev = {
- .platform_data = &isp1362_priv,
- },
- .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
- .resource = isp1362_hcd_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
-static struct resource net2272_bfin_resources[] = {
- {
- .start = 0x2C000000,
- .end = 0x2C000000 + 0x7F,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 1,
- .flags = IORESOURCE_BUS,
- }, {
- .start = IRQ_PF10,
- .end = IRQ_PF10,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
- },
-};
-
-static struct platform_device net2272_bfin_device = {
- .name = "net2272",
- .id = -1,
- .num_resources = ARRAY_SIZE(net2272_bfin_resources),
- .resource = net2272_bfin_resources,
-};
-#endif
-
-/*
- * USB-LAN EzExtender board
- * Driver needs to know address, irq and flag pin.
- */
-#if IS_ENABLED(CONFIG_SMC91X)
-#include <linux/smc91x.h>
-
-static struct smc91x_platdata smc91x_info = {
- .flags = SMC91X_USE_8BIT | SMC91X_USE_16BIT | SMC91X_USE_32BIT |
- SMC91X_NOWAIT,
- .leda = RPC_LED_100_10,
- .ledb = RPC_LED_TX_RX,
-};
-
-static struct resource smc91x_resources[] = {
- {
- .name = "smc91x-regs",
- .start = 0x2C010300,
- .end = 0x2C010300 + 16,
- .flags = IORESOURCE_MEM,
- }, {
-
- .start = IRQ_PF9,
- .end = IRQ_PF9,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev = {
- .platform_data = &smc91x_info,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = BFIN_UART_THR,
- .end = BFIN_UART_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART_TX,
- .end = IRQ_UART_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART_RX,
- .end = IRQ_UART_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART_ERROR,
- .end = IRQ_UART_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART_TX,
- .end = CH_UART_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART_RX,
- .end = CH_UART_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
-static struct mtd_partition ezkit_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x40000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0x1C0000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = 0x800000 - 0x40000 - 0x1C0000 - 0x2000 * 8,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "config(nor)",
- .size = 0x2000 * 7,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "u-boot env(nor)",
- .size = 0x2000,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct physmap_flash_data ezkit_flash_data = {
- .width = 2,
- .parts = ezkit_partitions,
- .nr_parts = ARRAY_SIZE(ezkit_partitions),
-};
-
-static struct resource ezkit_flash_resource = {
- .start = 0x20000000,
- .end = 0x207fffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device ezkit_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &ezkit_flash_data,
- },
- .num_resources = 1,
- .resource = &ezkit_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
- {
- .modalias = "ad183x",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 4,
- .platform_data = "ad1836", /* only includes chip name for the moment */
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
-#include <linux/input.h>
-#include <linux/gpio_keys.h>
-
-static struct gpio_keys_button bfin_gpio_keys_table[] = {
- {BTN_0, GPIO_PF5, 1, "gpio-keys: BTN0"},
- {BTN_1, GPIO_PF6, 1, "gpio-keys: BTN1"},
- {BTN_2, GPIO_PF7, 1, "gpio-keys: BTN2"},
- {BTN_3, GPIO_PF8, 1, "gpio-keys: BTN3"},
-};
-
-static struct gpio_keys_platform_data bfin_gpio_keys_data = {
- .buttons = bfin_gpio_keys_table,
- .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
-};
-
-static struct platform_device bfin_device_gpiokeys = {
- .name = "gpio-keys",
- .dev = {
- .platform_data = &bfin_gpio_keys_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_GPIO)
-#include <linux/i2c-gpio.h>
-
-static struct gpiod_lookup_table bfin_i2c_gpiod_table = {
- .dev_id = "i2c-gpio",
- .table = {
- GPIO_LOOKUP_IDX("BFIN-GPIO", GPIO_PF1, NULL, 0,
- GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
- GPIO_LOOKUP_IDX("BFIN-GPIO", GPIO_PF0, NULL, 1,
- GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
- },
-};
-
-static struct i2c_gpio_platform_data i2c_gpio_data = {
- .udelay = 10,
-};
-
-static struct platform_device i2c_gpio_device = {
- .name = "i2c-gpio",
- .id = 0,
- .dev = {
- .platform_data = &i2c_gpio_data,
- },
-};
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
- VRPAIR(VLEV_085, 250000000),
- VRPAIR(VLEV_090, 300000000),
- VRPAIR(VLEV_095, 313000000),
- VRPAIR(VLEV_100, 350000000),
- VRPAIR(VLEV_105, 400000000),
- VRPAIR(VLEV_110, 444000000),
- VRPAIR(VLEV_115, 450000000),
- VRPAIR(VLEV_120, 475000000),
- VRPAIR(VLEV_125, 500000000),
- VRPAIR(VLEV_130, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_CAPTURE)
-#include <linux/videodev2.h>
-#include <media/blackfin/bfin_capture.h>
-#include <media/blackfin/ppi.h>
-
-static const unsigned short ppi_req[] = {
- P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
- P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
- P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
- 0,
-};
-
-static const struct ppi_info ppi_info = {
- .type = PPI_TYPE_PPI,
- .dma_ch = CH_PPI0,
- .irq_err = IRQ_PPI1_ERROR,
- .base = (void __iomem *)PPI0_CONTROL,
- .pin_req = ppi_req,
-};
-
-#if IS_ENABLED(CONFIG_VIDEO_ADV7183)
-#include <media/i2c/adv7183.h>
-static struct v4l2_input adv7183_inputs[] = {
- {
- .index = 0,
- .name = "Composite",
- .type = V4L2_INPUT_TYPE_CAMERA,
- .std = V4L2_STD_ALL,
- .capabilities = V4L2_IN_CAP_STD,
- },
- {
- .index = 1,
- .name = "S-Video",
- .type = V4L2_INPUT_TYPE_CAMERA,
- .std = V4L2_STD_ALL,
- .capabilities = V4L2_IN_CAP_STD,
- },
- {
- .index = 2,
- .name = "Component",
- .type = V4L2_INPUT_TYPE_CAMERA,
- .std = V4L2_STD_ALL,
- .capabilities = V4L2_IN_CAP_STD,
- },
-};
-
-static struct bcap_route adv7183_routes[] = {
- {
- .input = ADV7183_COMPOSITE4,
- .output = ADV7183_8BIT_OUT,
- },
- {
- .input = ADV7183_SVIDEO0,
- .output = ADV7183_8BIT_OUT,
- },
- {
- .input = ADV7183_COMPONENT0,
- .output = ADV7183_8BIT_OUT,
- },
-};
-
-
-static const unsigned adv7183_gpio[] = {
- GPIO_PF13, /* reset pin */
- GPIO_PF2, /* output enable pin */
-};
-
-static struct bfin_capture_config bfin_capture_data = {
- .card_name = "BF561",
- .inputs = adv7183_inputs,
- .num_inputs = ARRAY_SIZE(adv7183_inputs),
- .routes = adv7183_routes,
- .i2c_adapter_id = 0,
- .board_info = {
- .type = "adv7183",
- .addr = 0x20,
- .platform_data = (void *)adv7183_gpio,
- },
- .ppi_info = &ppi_info,
- .ppi_control = (PACK_EN | DLEN_8 | DMA32 | FLD_SEL),
-};
-#endif
-
-static struct platform_device bfin_capture_device = {
- .name = "bfin_capture",
- .dev = {
- .platform_data = &bfin_capture_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
-static struct platform_device bfin_i2s = {
- .name = "bfin-i2s",
- .id = CONFIG_SND_BF5XX_SPORT_NUM,
- /* TODO: add platform data here */
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
-static struct platform_device bfin_ac97 = {
- .name = "bfin-ac97",
- .id = CONFIG_SND_BF5XX_SPORT_NUM,
- /* TODO: add platform data here */
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
-static const char * const ad1836_link[] = {
- "bfin-i2s.0",
- "spi0.4",
-};
-static struct platform_device bfin_ad1836_machine = {
- .name = "bfin-snd-ad1836",
- .id = -1,
- .dev = {
- .platform_data = (void *)ad1836_link,
- },
-};
-#endif
-
-static struct platform_device *ezkit_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_SMC91X)
- &smc91x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
- &net2272_bfin_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
- &bfin_isp1760_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
- &bfin_device_gpiokeys,
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_GPIO)
- &i2c_gpio_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
- &isp1362_hcd_device,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
- &ezkit_flash_device,
-#endif
-
-#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_CAPTURE)
- &bfin_capture_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
- &bfin_i2s,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
- &bfin_ac97,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
- &bfin_ad1836_machine,
-#endif
-};
-
-static int __init net2272_init(void)
-{
-#if IS_ENABLED(CONFIG_USB_NET2272)
- int ret;
-
- ret = gpio_request(GPIO_PF11, "net2272");
- if (ret)
- return ret;
-
- /* Reset the USB chip */
- gpio_direction_output(GPIO_PF11, 0);
- mdelay(2);
- gpio_set_value(GPIO_PF11, 1);
-#endif
-
- return 0;
-}
-
-static int __init ezkit_init(void)
-{
- int ret;
-
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
-
-#if IS_ENABLED(CONFIG_I2C_GPIO)
- gpiod_add_lookup_table(&bfin_i2c_gpiod_table);
-#endif
- ret = platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices));
- if (ret < 0)
- return ret;
-
-#if IS_ENABLED(CONFIG_SMC91X)
- bfin_write_FIO0_DIR(bfin_read_FIO0_DIR() | (1 << 12));
- SSYNC();
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
- bfin_write_FIO0_DIR(bfin_read_FIO0_DIR() | (1 << 15));
- bfin_write_FIO0_FLAG_S(1 << 15);
- SSYNC();
- /*
- * This initialization lasts for approximately 4500 MCLKs.
- * MCLK = 12.288MHz
- */
- udelay(400);
-#endif
-
- if (net2272_init())
- pr_warning("unable to configure net2272; it probably won't work\n");
-
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
- return 0;
-}
-
-arch_initcall(ezkit_init);
-
-static struct platform_device *ezkit_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(ezkit_early_devices,
- ARRAY_SIZE(ezkit_early_devices));
-}
+++ /dev/null
-/*
- * Copyright 2004-2007 Analog Devices Inc.
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Thanks to Jamey Hicks.
- *
- * Only SMSC91C1111 was registered, may do more later.
- *
- * Licensed under the GPL-2
- */
-
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/irq.h>
-
-const char bfin_board_name[] = "Tepla-BF561";
-
-/*
- * Driver needs to know address, irq and flag pin.
- */
-static struct resource smc91x_resources[] = {
- {
- .start = 0x2C000300,
- .end = 0x2C000320,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PROG_INTB,
- .end = IRQ_PROG_INTB,
- .flags = IORESOURCE_IRQ|IORESOURCE_IRQ_HIGHLEVEL,
- }, {
- .start = IRQ_PF7,
- .end = IRQ_PF7,
- .flags = IORESOURCE_IRQ|IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
-};
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = BFIN_UART_THR,
- .end = BFIN_UART_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART_TX,
- .end = IRQ_UART_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART_RX,
- .end = IRQ_UART_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART_ERROR,
- .end = IRQ_UART_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART_TX,
- .end = CH_UART_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART_RX,
- .end = CH_UART_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#endif
-
-static struct platform_device *tepla_devices[] __initdata = {
- &smc91x_device,
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#endif
-};
-
-static int __init tepla_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- return platform_add_devices(tepla_devices, ARRAY_SIZE(tepla_devices));
-}
-
-arch_initcall(tepla_init);
-
-static struct platform_device *tepla_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(tepla_early_devices,
- ARRAY_SIZE(tepla_early_devices));
-}
+++ /dev/null
-/* Load firmware into Core B on a BF561
- *
- * Author: Bas Vermeulen <bvermeul@blackstar.xs4all.nl>
- *
- * Copyright 2004-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-/* The Core B reset func requires code in the application that is loaded into
- * Core B. In order to reset, the application needs to install an interrupt
- * handler for Supplemental Interrupt 0, that sets RETI to 0xff600000 and
- * writes bit 11 of SICB_SYSCR when bit 5 of SICA_SYSCR is 0. This causes Core
- * B to stall when Supplemental Interrupt 0 is set, and will reset PC to
- * 0xff600000 when COREB_SRAM_INIT is cleared.
- */
-
-#include <linux/device.h>
-#include <linux/fs.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/miscdevice.h>
-
-#define CMD_COREB_START _IO('b', 0)
-#define CMD_COREB_STOP _IO('b', 1)
-#define CMD_COREB_RESET _IO('b', 2)
-
-static long
-coreb_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
-{
- int ret = 0;
-
- switch (cmd) {
- case CMD_COREB_START:
- bfin_write_SYSCR(bfin_read_SYSCR() & ~0x0020);
- break;
- case CMD_COREB_STOP:
- bfin_write_SYSCR(bfin_read_SYSCR() | 0x0020);
- bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | 0x0080);
- break;
- case CMD_COREB_RESET:
- bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | 0x0080);
- break;
- default:
- ret = -EINVAL;
- break;
- }
-
- CSYNC();
-
- return ret;
-}
-
-static const struct file_operations coreb_fops = {
- .owner = THIS_MODULE,
- .unlocked_ioctl = coreb_ioctl,
- .llseek = noop_llseek,
-};
-
-static struct miscdevice coreb_dev = {
- .minor = MISC_DYNAMIC_MINOR,
- .name = "coreb",
- .fops = &coreb_fops,
-};
-builtin_misc_device(coreb_dev);
+++ /dev/null
-/*
- * the simple DMA Implementation for Blackfin
- *
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-
-#include <asm/blackfin.h>
-#include <asm/dma.h>
-
-struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
- (struct dma_register *) DMA1_0_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_1_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_2_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_3_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_4_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_5_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_6_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_7_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_8_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_9_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_10_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_11_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_0_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_1_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_2_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_3_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_4_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_5_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_6_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_7_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_8_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_9_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_10_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_11_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D2_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S2_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D3_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S3_NEXT_DESC_PTR,
- (struct dma_register *) IMDMA_D0_NEXT_DESC_PTR,
- (struct dma_register *) IMDMA_S0_NEXT_DESC_PTR,
- (struct dma_register *) IMDMA_D1_NEXT_DESC_PTR,
- (struct dma_register *) IMDMA_S1_NEXT_DESC_PTR,
-};
-EXPORT_SYMBOL(dma_io_base_addr);
-
-int channel2irq(unsigned int channel)
-{
- int ret_irq = -1;
-
- switch (channel) {
- case CH_PPI0:
- ret_irq = IRQ_PPI0;
- break;
- case CH_PPI1:
- ret_irq = IRQ_PPI1;
- break;
- case CH_SPORT0_RX:
- ret_irq = IRQ_SPORT0_RX;
- break;
- case CH_SPORT0_TX:
- ret_irq = IRQ_SPORT0_TX;
- break;
- case CH_SPORT1_RX:
- ret_irq = IRQ_SPORT1_RX;
- break;
- case CH_SPORT1_TX:
- ret_irq = IRQ_SPORT1_TX;
- break;
- case CH_SPI:
- ret_irq = IRQ_SPI;
- break;
- case CH_UART_RX:
- ret_irq = IRQ_UART_RX;
- break;
- case CH_UART_TX:
- ret_irq = IRQ_UART_TX;
- break;
-
- case CH_MEM_STREAM0_SRC:
- case CH_MEM_STREAM0_DEST:
- ret_irq = IRQ_MEM_DMA0;
- break;
- case CH_MEM_STREAM1_SRC:
- case CH_MEM_STREAM1_DEST:
- ret_irq = IRQ_MEM_DMA1;
- break;
- case CH_MEM_STREAM2_SRC:
- case CH_MEM_STREAM2_DEST:
- ret_irq = IRQ_MEM_DMA2;
- break;
- case CH_MEM_STREAM3_SRC:
- case CH_MEM_STREAM3_DEST:
- ret_irq = IRQ_MEM_DMA3;
- break;
-
- case CH_IMEM_STREAM0_SRC:
- case CH_IMEM_STREAM0_DEST:
- ret_irq = IRQ_IMEM_DMA0;
- break;
- case CH_IMEM_STREAM1_SRC:
- case CH_IMEM_STREAM1_DEST:
- ret_irq = IRQ_IMEM_DMA1;
- break;
- }
- return ret_irq;
-}
+++ /dev/null
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- * Graff Yang <graf.yang@analog.com>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/smp.h>
-#include <asm/blackfin.h>
-#include <asm/cacheflush.h>
-#include <mach/pll.h>
-
-int hotplug_coreb;
-
-void platform_cpu_die(void)
-{
- unsigned long iwr;
-
- hotplug_coreb = 1;
-
- /*
- * When CoreB wakes up, the code in _coreb_trampoline_start cannot
- * turn off the data cache. This causes the CoreB failed to boot.
- * As a workaround, we invalidate all the data cache before sleep.
- */
- blackfin_invalidate_entire_dcache();
-
- /* disable core timer */
- bfin_write_TCNTL(0);
-
- /* clear ipi interrupt IRQ_SUPPLE_0 of CoreB */
- bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (10 + 1)));
- SSYNC();
-
- /* set CoreB wakeup by ipi0, iwr will be discarded */
- bfin_iwr_set_sup0(&iwr, &iwr, &iwr);
- SSYNC();
-
- coreb_die();
-}
+++ /dev/null
-/*
- * DO NOT EDIT THIS FILE
- * This file is under version control at
- * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
- * and can be replaced with that version at any time
- * DO NOT EDIT THIS FILE
- *
- * Copyright 2004-2011 Analog Devices Inc.
- * Licensed under the Clear BSD license.
- */
-
-/* This file should be up to date with:
- * - Revision S, 05/23/2011; ADSP-BF561 Blackfin Processor Anomaly List
- */
-
-#ifndef _MACH_ANOMALY_H_
-#define _MACH_ANOMALY_H_
-
-/* We do not support 0.1, 0.2, or 0.4 silicon - sorry */
-#if __SILICON_REVISION__ < 3 || __SILICON_REVISION__ == 4
-# error will not work on BF561 silicon version 0.0, 0.1, 0.2, or 0.4
-#endif
-
-/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
-#define ANOMALY_05000074 (1)
-/* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */
-#define ANOMALY_05000099 (__SILICON_REVISION__ < 5)
-/* TESTSET Instructions Restricted to 32-Bit Aligned Memory Locations */
-#define ANOMALY_05000120 (1)
-/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
-#define ANOMALY_05000122 (1)
-/* SIGNBITS Instruction Not Functional under Certain Conditions */
-#define ANOMALY_05000127 (1)
-/* IMDMA S1/D1 Channel May Stall */
-#define ANOMALY_05000149 (1)
-/* Timers in PWM-Out Mode with PPI GP Receive (Input) Mode with 0 Frame Syncs */
-#define ANOMALY_05000156 (__SILICON_REVISION__ < 4)
-/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */
-#define ANOMALY_05000166 (1)
-/* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */
-#define ANOMALY_05000167 (1)
-/* Undefined Behavior when Power-Up Sequence Is Issued to SDRAM during Auto-Refresh */
-#define ANOMALY_05000168 (__SILICON_REVISION__ < 5)
-/* DATA CPLB Page Miss Can Result in Lost Write-Through Data Cache Writes */
-#define ANOMALY_05000169 (__SILICON_REVISION__ < 5)
-/* Boot-ROM Modifies SICA_IWRx Wakeup Registers */
-#define ANOMALY_05000171 (__SILICON_REVISION__ < 5)
-/* Cache Fill Buffer Data lost */
-#define ANOMALY_05000174 (__SILICON_REVISION__ < 5)
-/* Overlapping Sequencer and Memory Stalls */
-#define ANOMALY_05000175 (__SILICON_REVISION__ < 5)
-/* Overflow Bit Asserted when Multiplication of -1 by -1 Followed by Accumulator Saturation */
-#define ANOMALY_05000176 (__SILICON_REVISION__ < 5)
-/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */
-#define ANOMALY_05000179 (__SILICON_REVISION__ < 5)
-/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
-#define ANOMALY_05000180 (1)
-/* Disabling the PPI Resets the PPI Configuration Registers */
-#define ANOMALY_05000181 (__SILICON_REVISION__ < 5)
-/* Internal Memory DMA Does Not Operate at Full Speed */
-#define ANOMALY_05000182 (1)
-/* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */
-#define ANOMALY_05000184 (__SILICON_REVISION__ < 5)
-/* Early PPI Transmit when FS1 Asserts before FS2 in TX Mode with 2 External Frame Syncs */
-#define ANOMALY_05000185 (__SILICON_REVISION__ < 5)
-/* Upper PPI Pins Driven when PPI Packing Enabled and Data Length >8 Bits */
-#define ANOMALY_05000186 (__SILICON_REVISION__ < 5)
-/* IMDMA Corrupted Data after a Halt */
-#define ANOMALY_05000187 (1)
-/* IMDMA Restrictions on Descriptor and Buffer Placement in Memory */
-#define ANOMALY_05000188 (__SILICON_REVISION__ < 5)
-/* False Protection Exceptions when Speculative Fetch Is Cancelled */
-#define ANOMALY_05000189 (__SILICON_REVISION__ < 5)
-/* PPI Not Functional at Core Voltage < 1Volt */
-#define ANOMALY_05000190 (1)
-/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */
-#define ANOMALY_05000193 (__SILICON_REVISION__ < 5)
-/* Restarting SPORT in Specific Modes May Cause Data Corruption */
-#define ANOMALY_05000194 (__SILICON_REVISION__ < 5)
-/* Failing MMR Accesses when Preceding Memory Read Stalls */
-#define ANOMALY_05000198 (__SILICON_REVISION__ < 5)
-/* Current DMA Address Shows Wrong Value During Carry Fix */
-#define ANOMALY_05000199 (__SILICON_REVISION__ < 5)
-/* SPORT TFS and DT Are Incorrectly Driven During Inactive Channels in Certain Conditions */
-#define ANOMALY_05000200 (__SILICON_REVISION__ < 5)
-/* Possible Infinite Stall with Specific Dual-DAG Situation */
-#define ANOMALY_05000202 (__SILICON_REVISION__ < 5)
-/* Incorrect Data Read with Writethrough "Allocate Cache Lines on Reads Only" Cache Mode */
-#define ANOMALY_05000204 (__SILICON_REVISION__ < 5)
-/* Specific Sequence that Can Cause DMA Error or DMA Stopping */
-#define ANOMALY_05000205 (__SILICON_REVISION__ < 5)
-/* Recovery from "Brown-Out" Condition */
-#define ANOMALY_05000207 (__SILICON_REVISION__ < 5)
-/* VSTAT Status Bit in PLL_STAT Register Is Not Functional */
-#define ANOMALY_05000208 (1)
-/* Speed Path in Computational Unit Affects Certain Instructions */
-#define ANOMALY_05000209 (__SILICON_REVISION__ < 5)
-/* UART TX Interrupt Masked Erroneously */
-#define ANOMALY_05000215 (__SILICON_REVISION__ < 5)
-/* NMI Event at Boot Time Results in Unpredictable State */
-#define ANOMALY_05000219 (__SILICON_REVISION__ < 5)
-/* Data Corruption/Core Hang with L2/L3 Configured in Writeback Cache Mode */
-#define ANOMALY_05000220 (__SILICON_REVISION__ < 4)
-/* Incorrect Pulse-Width of UART Start Bit */
-#define ANOMALY_05000225 (__SILICON_REVISION__ < 5)
-/* Scratchpad Memory Bank Reads May Return Incorrect Data */
-#define ANOMALY_05000227 (__SILICON_REVISION__ < 5)
-/* UART Receiver is Less Robust Against Baudrate Differences in Certain Conditions */
-#define ANOMALY_05000230 (__SILICON_REVISION__ < 5)
-/* UART STB Bit Incorrectly Affects Receiver Setting */
-#define ANOMALY_05000231 (__SILICON_REVISION__ < 5)
-/* SPORT Data Transmit Lines Are Incorrectly Driven in Multichannel Mode */
-#define ANOMALY_05000232 (__SILICON_REVISION__ < 5)
-/* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */
-#define ANOMALY_05000242 (__SILICON_REVISION__ < 5)
-/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
-#define ANOMALY_05000244 (__SILICON_REVISION__ < 5)
-/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
-#define ANOMALY_05000245 (__SILICON_REVISION__ < 5)
-/* TESTSET Operation Forces Stall on the Other Core */
-#define ANOMALY_05000248 (__SILICON_REVISION__ < 5)
-/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
-#define ANOMALY_05000250 (__SILICON_REVISION__ > 2 && __SILICON_REVISION__ < 5)
-/* Exception Not Generated for MMR Accesses in Reserved Region */
-#define ANOMALY_05000251 (__SILICON_REVISION__ < 5)
-/* Maximum External Clock Speed for Timers */
-#define ANOMALY_05000253 (__SILICON_REVISION__ < 5)
-/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
-#define ANOMALY_05000254 (__SILICON_REVISION__ > 3)
-/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */
-/* Tempoary work around for kgdb bug 6333 in SMP kernel. It looks coreb hangs in exception
- * without handling anomaly 05000257 properly on bf561 v0.5. This work around may change
- * after the behavior and the root cause are confirmed with hardware team.
- */
-#define ANOMALY_05000257 (__SILICON_REVISION__ < 5 || (__SILICON_REVISION__ == 5 && CONFIG_SMP))
-/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */
-#define ANOMALY_05000258 (__SILICON_REVISION__ < 5)
-/* ICPLB_STATUS MMR Register May Be Corrupted */
-#define ANOMALY_05000260 (__SILICON_REVISION__ < 5)
-/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
-#define ANOMALY_05000261 (__SILICON_REVISION__ < 5)
-/* Stores To Data Cache May Be Lost */
-#define ANOMALY_05000262 (__SILICON_REVISION__ < 5)
-/* Hardware Loop Corrupted When Taking an ICPLB Exception */
-#define ANOMALY_05000263 (__SILICON_REVISION__ < 5)
-/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */
-#define ANOMALY_05000264 (__SILICON_REVISION__ < 5)
-/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
-#define ANOMALY_05000265 (__SILICON_REVISION__ < 5)
-/* IMDMA Destination IRQ Status Must Be Read Prior to Using IMDMA */
-#define ANOMALY_05000266 (__SILICON_REVISION__ > 3)
-/* IMDMA May Corrupt Data under Certain Conditions */
-#define ANOMALY_05000267 (1)
-/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */
-#define ANOMALY_05000269 (1)
-/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
-#define ANOMALY_05000270 (1)
-/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
-#define ANOMALY_05000272 (1)
-/* Data Cache Write Back to External Synchronous Memory May Be Lost */
-#define ANOMALY_05000274 (1)
-/* PPI Timing and Sampling Information Updates */
-#define ANOMALY_05000275 (__SILICON_REVISION__ > 2)
-/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */
-#define ANOMALY_05000276 (__SILICON_REVISION__ < 5)
-/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
-#define ANOMALY_05000277 (__SILICON_REVISION__ < 5)
-/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
-#define ANOMALY_05000278 (__SILICON_REVISION__ < 5)
-/* False Hardware Error when ISR Context Is Not Restored */
-/* Temporarily walk around for bug 5423 till this issue is confirmed by
- * official anomaly document. It looks 05000281 still exists on bf561
- * v0.5.
- */
-#define ANOMALY_05000281 (__SILICON_REVISION__ <= 5)
-/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */
-#define ANOMALY_05000283 (1)
-/* Reads Will Receive Incorrect Data under Certain Conditions */
-#define ANOMALY_05000287 (__SILICON_REVISION__ < 5)
-/* SPORTs May Receive Bad Data If FIFOs Fill Up */
-#define ANOMALY_05000288 (__SILICON_REVISION__ < 5)
-/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
-#define ANOMALY_05000301 (1)
-/* SSYNCs after Writes to DMA MMR Registers May Not Be Handled Correctly */
-#define ANOMALY_05000302 (1)
-/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */
-#define ANOMALY_05000305 (__SILICON_REVISION__ < 5)
-/* SCKELOW Bit Does Not Maintain State Through Hibernate */
-#define ANOMALY_05000307 (__SILICON_REVISION__ < 5)
-/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
-#define ANOMALY_05000310 (1)
-/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
-#define ANOMALY_05000312 (1)
-/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
-#define ANOMALY_05000313 (1)
-/* Killed System MMR Write Completes Erroneously on Next System MMR Access */
-#define ANOMALY_05000315 (1)
-/* PF2 Output Remains Asserted after SPI Master Boot */
-#define ANOMALY_05000320 (__SILICON_REVISION__ > 3)
-/* Erroneous GPIO Flag Pin Operations under Specific Sequences */
-#define ANOMALY_05000323 (1)
-/* SPORT Secondary Receive Channel Not Functional when Word Length >16 Bits */
-#define ANOMALY_05000326 (__SILICON_REVISION__ > 3)
-/* 24-Bit SPI Boot Mode Is Not Functional */
-#define ANOMALY_05000331 (__SILICON_REVISION__ < 5)
-/* Slave SPI Boot Mode Is Not Functional */
-#define ANOMALY_05000332 (__SILICON_REVISION__ < 5)
-/* Flag Data Register Writes One SCLK Cycle after Edge Is Detected May Clear Interrupt Status */
-#define ANOMALY_05000333 (__SILICON_REVISION__ < 5)
-/* ALT_TIMING Bit in PLL_CTL Register Is Not Functional */
-#define ANOMALY_05000339 (__SILICON_REVISION__ < 5)
-/* Memory DMA FIFO Causes Throughput Degradation on Writes to External Memory */
-#define ANOMALY_05000343 (__SILICON_REVISION__ < 5)
-/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
-#define ANOMALY_05000357 (1)
-/* Conflicting Column Address Widths Causes SDRAM Errors */
-#define ANOMALY_05000362 (1)
-/* UART Break Signal Issues */
-#define ANOMALY_05000363 (__SILICON_REVISION__ < 5)
-/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
-#define ANOMALY_05000366 (1)
-/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
-#define ANOMALY_05000371 (1)
-/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
-#define ANOMALY_05000403 (1)
-/* TESTSET Instruction Causes Data Corruption with Writeback Data Cache Enabled */
-#define ANOMALY_05000412 (1)
-/* Speculative Fetches Can Cause Undesired External FIFO Operations */
-#define ANOMALY_05000416 (1)
-/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
-#define ANOMALY_05000425 (1)
-/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
-#define ANOMALY_05000426 (1)
-/* Lost/Corrupted L2/L3 Memory Write after Speculative L2 Memory Read by Core B */
-#define ANOMALY_05000428 (__SILICON_REVISION__ > 3)
-/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
-#define ANOMALY_05000443 (1)
-/* SCKELOW Feature Is Not Functional */
-#define ANOMALY_05000458 (1)
-/* False Hardware Error when RETI Points to Invalid Memory */
-#define ANOMALY_05000461 (1)
-/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
-#define ANOMALY_05000462 (1)
-/* Boot Failure When SDRAM Control Signals Toggle Coming Out Of Reset */
-#define ANOMALY_05000471 (1)
-/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
-#define ANOMALY_05000473 (1)
-/* Possible Lockup Condition when Modifying PLL from External Memory */
-#define ANOMALY_05000475 (1)
-/* TESTSET Instruction Cannot Be Interrupted */
-#define ANOMALY_05000477 (1)
-/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
-#define ANOMALY_05000481 (1)
-/* PLL May Latch Incorrect Values Coming Out of Reset */
-#define ANOMALY_05000489 (1)
-/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
-#define ANOMALY_05000491 (1)
-/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
-#define ANOMALY_05000494 (1)
-/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
-#define ANOMALY_05000501 (1)
-
-/*
- * These anomalies have been "phased" out of analog.com anomaly sheets and are
- * here to show running on older silicon just isn't feasible.
- */
-
-/* Trace Buffers May Contain Errors in Emulation Mode and/or Exception, NMI, Reset Handlers */
-#define ANOMALY_05000116 (__SILICON_REVISION__ < 3)
-/* Erroneous Exception when Enabling Cache */
-#define ANOMALY_05000125 (__SILICON_REVISION__ < 3)
-/* Two bits in the Watchpoint Status Register (WPSTAT) are swapped */
-#define ANOMALY_05000134 (__SILICON_REVISION__ < 3)
-/* Enable wires from the Data Watchpoint Address Control Register (WPDACTL) are swapped */
-#define ANOMALY_05000135 (__SILICON_REVISION__ < 3)
-/* Stall in multi-unit DMA operations */
-#define ANOMALY_05000136 (__SILICON_REVISION__ < 3)
-/* Allowing the SPORT RX FIFO to fill will cause an overflow */
-#define ANOMALY_05000140 (__SILICON_REVISION__ < 3)
-/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */
-#define ANOMALY_05000141 (__SILICON_REVISION__ < 3)
-/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */
-#define ANOMALY_05000142 (__SILICON_REVISION__ < 3)
-/* DMA and TESTSET conflict when both are accessing external memory */
-#define ANOMALY_05000144 (__SILICON_REVISION__ < 3)
-/* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */
-#define ANOMALY_05000145 (__SILICON_REVISION__ < 3)
-/* MDMA may lose the first few words of a descriptor chain */
-#define ANOMALY_05000146 (__SILICON_REVISION__ < 3)
-/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */
-#define ANOMALY_05000147 (__SILICON_REVISION__ < 3)
-/* DMA engine may lose data due to incorrect handshaking */
-#define ANOMALY_05000150 (__SILICON_REVISION__ < 3)
-/* DMA stalls when all three controllers read data from the same source */
-#define ANOMALY_05000151 (__SILICON_REVISION__ < 3)
-/* Execution stall when executing in L2 and doing external accesses */
-#define ANOMALY_05000152 (__SILICON_REVISION__ < 3)
-/* Frame Delay in SPORT Multichannel Mode */
-#define ANOMALY_05000153 (__SILICON_REVISION__ < 3)
-/* SPORT TFS signal stays active in multichannel mode outside of valid channels */
-#define ANOMALY_05000154 (__SILICON_REVISION__ < 3)
-/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
-#define ANOMALY_05000157 (__SILICON_REVISION__ < 3)
-/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */
-#define ANOMALY_05000159 (__SILICON_REVISION__ < 3)
-/* A read from external memory may return a wrong value with data cache enabled */
-#define ANOMALY_05000160 (__SILICON_REVISION__ < 3)
-/* Data Cache Fill data can be corrupted after/during Instruction DMA if certain core stalls exist */
-#define ANOMALY_05000161 (__SILICON_REVISION__ < 3)
-/* DMEM_CONTROL<12> is not set on Reset */
-#define ANOMALY_05000162 (__SILICON_REVISION__ < 3)
-/* SPORT Transmit Data Is Not Gated by External Frame Sync in Certain Conditions */
-#define ANOMALY_05000163 (__SILICON_REVISION__ < 3)
-/* DSPID register values incorrect */
-#define ANOMALY_05000172 (__SILICON_REVISION__ < 3)
-/* DMA vs Core accesses to external memory */
-#define ANOMALY_05000173 (__SILICON_REVISION__ < 3)
-/* PPI does not invert the Driving PPICLK edge in Transmit Modes */
-#define ANOMALY_05000191 (__SILICON_REVISION__ < 3)
-/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
-#define ANOMALY_05000402 (__SILICON_REVISION__ == 4)
-
-/* Anomalies that don't exist on this proc */
-#define ANOMALY_05000119 (0)
-#define ANOMALY_05000158 (0)
-#define ANOMALY_05000183 (0)
-#define ANOMALY_05000233 (0)
-#define ANOMALY_05000234 (0)
-#define ANOMALY_05000273 (0)
-#define ANOMALY_05000311 (0)
-#define ANOMALY_05000353 (1)
-#define ANOMALY_05000364 (0)
-#define ANOMALY_05000380 (0)
-#define ANOMALY_05000383 (0)
-#define ANOMALY_05000386 (1)
-#define ANOMALY_05000389 (0)
-#define ANOMALY_05000400 (0)
-#define ANOMALY_05000430 (0)
-#define ANOMALY_05000432 (0)
-#define ANOMALY_05000435 (0)
-#define ANOMALY_05000440 (0)
-#define ANOMALY_05000447 (0)
-#define ANOMALY_05000448 (0)
-#define ANOMALY_05000456 (0)
-#define ANOMALY_05000450 (0)
-#define ANOMALY_05000465 (0)
-#define ANOMALY_05000467 (0)
-#define ANOMALY_05000474 (0)
-#define ANOMALY_05000480 (0)
-#define ANOMALY_05000485 (0)
-#define ANOMALY_16000030 (0)
-
-#endif
+++ /dev/null
-/*
- * SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561
- *
- * Copyright 2005-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __MACH_BF561_H__
-#define __MACH_BF561_H__
-
-#define OFFSET_(x) ((x) & 0x0000FFFF)
-
-/*some misc defines*/
-#define IMASK_IVG15 0x8000
-#define IMASK_IVG14 0x4000
-#define IMASK_IVG13 0x2000
-#define IMASK_IVG12 0x1000
-
-#define IMASK_IVG11 0x0800
-#define IMASK_IVG10 0x0400
-#define IMASK_IVG9 0x0200
-#define IMASK_IVG8 0x0100
-
-#define IMASK_IVG7 0x0080
-#define IMASK_IVGTMR 0x0040
-#define IMASK_IVGHW 0x0020
-
-/***************************
- * Blackfin Cache setup
- */
-
-
-#define BFIN_ISUBBANKS 4
-#define BFIN_IWAYS 4
-#define BFIN_ILINES 32
-
-#define BFIN_DSUBBANKS 4
-#define BFIN_DWAYS 2
-#define BFIN_DLINES 64
-
-#define WAY0_L 0x1
-#define WAY1_L 0x2
-#define WAY01_L 0x3
-#define WAY2_L 0x4
-#define WAY02_L 0x5
-#define WAY12_L 0x6
-#define WAY012_L 0x7
-
-#define WAY3_L 0x8
-#define WAY03_L 0x9
-#define WAY13_L 0xA
-#define WAY013_L 0xB
-
-#define WAY32_L 0xC
-#define WAY320_L 0xD
-#define WAY321_L 0xE
-#define WAYALL_L 0xF
-
-#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
-
-/* IAR0 BIT FIELDS */
-#define PLL_WAKEUP_BIT 0xFFFFFFFF
-#define DMA1_ERROR_BIT 0xFFFFFF0F
-#define DMA2_ERROR_BIT 0xFFFFF0FF
-#define IMDMA_ERROR_BIT 0xFFFF0FFF
-#define PPI1_ERROR_BIT 0xFFF0FFFF
-#define PPI2_ERROR_BIT 0xFF0FFFFF
-#define SPORT0_ERROR_BIT 0xF0FFFFFF
-#define SPORT1_ERROR_BIT 0x0FFFFFFF
-/* IAR1 BIT FIELDS */
-#define SPI_ERROR_BIT 0xFFFFFFFF
-#define UART_ERROR_BIT 0xFFFFFF0F
-#define RESERVED_ERROR_BIT 0xFFFFF0FF
-#define DMA1_0_BIT 0xFFFF0FFF
-#define DMA1_1_BIT 0xFFF0FFFF
-#define DMA1_2_BIT 0xFF0FFFFF
-#define DMA1_3_BIT 0xF0FFFFFF
-#define DMA1_4_BIT 0x0FFFFFFF
-/* IAR2 BIT FIELDS */
-#define DMA1_5_BIT 0xFFFFFFFF
-#define DMA1_6_BIT 0xFFFFFF0F
-#define DMA1_7_BIT 0xFFFFF0FF
-#define DMA1_8_BIT 0xFFFF0FFF
-#define DMA1_9_BIT 0xFFF0FFFF
-#define DMA1_10_BIT 0xFF0FFFFF
-#define DMA1_11_BIT 0xF0FFFFFF
-#define DMA2_0_BIT 0x0FFFFFFF
-/* IAR3 BIT FIELDS */
-#define DMA2_1_BIT 0xFFFFFFFF
-#define DMA2_2_BIT 0xFFFFFF0F
-#define DMA2_3_BIT 0xFFFFF0FF
-#define DMA2_4_BIT 0xFFFF0FFF
-#define DMA2_5_BIT 0xFFF0FFFF
-#define DMA2_6_BIT 0xFF0FFFFF
-#define DMA2_7_BIT 0xF0FFFFFF
-#define DMA2_8_BIT 0x0FFFFFFF
-/* IAR4 BIT FIELDS */
-#define DMA2_9_BIT 0xFFFFFFFF
-#define DMA2_10_BIT 0xFFFFFF0F
-#define DMA2_11_BIT 0xFFFFF0FF
-#define TIMER0_BIT 0xFFFF0FFF
-#define TIMER1_BIT 0xFFF0FFFF
-#define TIMER2_BIT 0xFF0FFFFF
-#define TIMER3_BIT 0xF0FFFFFF
-#define TIMER4_BIT 0x0FFFFFFF
-/* IAR5 BIT FIELDS */
-#define TIMER5_BIT 0xFFFFFFFF
-#define TIMER6_BIT 0xFFFFFF0F
-#define TIMER7_BIT 0xFFFFF0FF
-#define TIMER8_BIT 0xFFFF0FFF
-#define TIMER9_BIT 0xFFF0FFFF
-#define TIMER10_BIT 0xFF0FFFFF
-#define TIMER11_BIT 0xF0FFFFFF
-#define PROG0_INTA_BIT 0x0FFFFFFF
-/* IAR6 BIT FIELDS */
-#define PROG0_INTB_BIT 0xFFFFFFFF
-#define PROG1_INTA_BIT 0xFFFFFF0F
-#define PROG1_INTB_BIT 0xFFFFF0FF
-#define PROG2_INTA_BIT 0xFFFF0FFF
-#define PROG2_INTB_BIT 0xFFF0FFFF
-#define DMA1_WRRD0_BIT 0xFF0FFFFF
-#define DMA1_WRRD1_BIT 0xF0FFFFFF
-#define DMA2_WRRD0_BIT 0x0FFFFFFF
-/* IAR7 BIT FIELDS */
-#define DMA2_WRRD1_BIT 0xFFFFFFFF
-#define IMDMA_WRRD0_BIT 0xFFFFFF0F
-#define IMDMA_WRRD1_BIT 0xFFFFF0FF
-#define WATCH_BIT 0xFFFF0FFF
-#define RESERVED_1_BIT 0xFFF0FFFF
-#define RESERVED_2_BIT 0xFF0FFFFF
-#define SUPPLE_0_BIT 0xF0FFFFFF
-#define SUPPLE_1_BIT 0x0FFFFFFF
-
-/* Miscellaneous Values */
-
-/****************************** EBIU Settings ********************************/
-#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
-#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
-
-#if defined(CONFIG_C_AMBEN_ALL)
-#define V_AMBEN AMBEN_ALL
-#elif defined(CONFIG_C_AMBEN)
-#define V_AMBEN 0x0
-#elif defined(CONFIG_C_AMBEN_B0)
-#define V_AMBEN AMBEN_B0
-#elif defined(CONFIG_C_AMBEN_B0_B1)
-#define V_AMBEN AMBEN_B0_B1
-#elif defined(CONFIG_C_AMBEN_B0_B1_B2)
-#define V_AMBEN AMBEN_B0_B1_B2
-#endif
-
-#ifdef CONFIG_C_AMCKEN
-#define V_AMCKEN AMCKEN
-#else
-#define V_AMCKEN 0x0
-#endif
-
-#ifdef CONFIG_C_B0PEN
-#define V_B0PEN 0x10
-#else
-#define V_B0PEN 0x00
-#endif
-
-#ifdef CONFIG_C_B1PEN
-#define V_B1PEN 0x20
-#else
-#define V_B1PEN 0x00
-#endif
-
-#ifdef CONFIG_C_B2PEN
-#define V_B2PEN 0x40
-#else
-#define V_B2PEN 0x00
-#endif
-
-#ifdef CONFIG_C_B3PEN
-#define V_B3PEN 0x80
-#else
-#define V_B3PEN 0x00
-#endif
-
-#ifdef CONFIG_C_CDPRIO
-#define V_CDPRIO 0x100
-#else
-#define V_CDPRIO 0x0
-#endif
-
-#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO | V_B0PEN | V_B1PEN | V_B2PEN | V_B3PEN | 0x0002)
-
-#ifdef CONFIG_BF561
-#define CPU "BF561"
-#define CPUID 0x27bb
-#endif
-
-#ifndef CPU
-#error "Unknown CPU type - This kernel doesn't seem to be configured properly"
-#endif
-
-#endif /* __MACH_BF561_H__ */
+++ /dev/null
-/*
- * mach/bfin_serial.h - Blackfin UART/Serial definitions
- *
- * Copyright 2006-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MACH_SERIAL_H__
-#define __BFIN_MACH_SERIAL_H__
-
-#define BFIN_UART_NR_PORTS 1
-
-#endif
+++ /dev/null
-/*
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_BLACKFIN_H_
-#define _MACH_BLACKFIN_H_
-
-#define BF561_FAMILY
-
-#include "bf561.h"
-#include "anomaly.h"
-
-#include <asm/def_LPBlackfin.h>
-#include "defBF561.h"
-
-#ifndef __ASSEMBLY__
-# include <asm/cdef_LPBlackfin.h>
-# include "cdefBF561.h"
-#endif
-
-#define bfin_read_FIO_FLAG_D() bfin_read_FIO0_FLAG_D()
-#define bfin_write_FIO_FLAG_D(val) bfin_write_FIO0_FLAG_D(val)
-#define bfin_read_FIO_DIR() bfin_read_FIO0_DIR()
-#define bfin_write_FIO_DIR(val) bfin_write_FIO0_DIR(val)
-#define bfin_read_FIO_INEN() bfin_read_FIO0_INEN()
-#define bfin_write_FIO_INEN(val) bfin_write_FIO0_INEN(val)
-
-/* Weird muxer funcs which pick SIC regs from IMASK base */
-#define __SIC_MUX(base, x) ((base) + ((x) << 2))
-#define bfin_read_SIC_IMASK(x) bfin_read32(__SIC_MUX(SIC_IMASK0, x))
-#define bfin_write_SIC_IMASK(x, val) bfin_write32(__SIC_MUX(SIC_IMASK0, x), val)
-#define bfin_read_SICB_IMASK(x) bfin_read32(__SIC_MUX(SICB_IMASK0, x))
-#define bfin_write_SICB_IMASK(x, val) bfin_write32(__SIC_MUX(SICB_IMASK0, x), val)
-#define bfin_read_SIC_ISR(x) bfin_read32(__SIC_MUX(SIC_ISR0, x))
-#define bfin_write_SIC_ISR(x, val) bfin_write32(__SIC_MUX(SIC_ISR0, x), val)
-#define bfin_read_SICB_ISR(x) bfin_read32(__SIC_MUX(SICB_ISR0, x))
-#define bfin_write_SICB_ISR(x, val) bfin_write32(__SIC_MUX(SICB_ISR0, x), val)
-
-#endif /* _MACH_BLACKFIN_H_ */
+++ /dev/null
-/*
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CDEF_BF561_H
-#define _CDEF_BF561_H
-
-/*********************************************************************************** */
-/* System MMR Register Map */
-/*********************************************************************************** */
-
-/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
-#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
-#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val)
-#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
-#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val)
-#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val)
-#define bfin_read_CHIPID() bfin_read32(CHIPID)
-
-/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */
-#define bfin_read_SWRST() bfin_read16(SWRST)
-#define bfin_write_SWRST(val) bfin_write16(SWRST,val)
-#define bfin_read_SYSCR() bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val) bfin_write16(SYSCR,val)
-#define bfin_read_SIC_RVECT() bfin_read16(SIC_RVECT)
-#define bfin_write_SIC_RVECT(val) bfin_write16(SIC_RVECT,val)
-#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
-#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0,val)
-#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)
-#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1,val)
-#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
-#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0,val)
-#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
-#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1,val)
-#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
-#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2,val)
-#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
-#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3,val)
-#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4)
-#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4,val)
-#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5)
-#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5,val)
-#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6)
-#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6,val)
-#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7)
-#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7,val)
-#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
-#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0,val)
-#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
-#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1,val)
-#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
-#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0,val)
-#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
-#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1,val)
-
-/* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */
-#define bfin_read_SICB_SWRST() bfin_read16(SICB_SWRST)
-#define bfin_write_SICB_SWRST(val) bfin_write16(SICB_SWRST,val)
-#define bfin_read_SICB_SYSCR() bfin_read16(SICB_SYSCR)
-#define bfin_write_SICB_SYSCR(val) bfin_write16(SICB_SYSCR,val)
-#define bfin_read_SICB_RVECT() bfin_read16(SICB_RVECT)
-#define bfin_write_SICB_RVECT(val) bfin_write16(SICB_RVECT,val)
-#define bfin_read_SICB_IMASK0() bfin_read32(SICB_IMASK0)
-#define bfin_write_SICB_IMASK0(val) bfin_write32(SICB_IMASK0,val)
-#define bfin_read_SICB_IMASK1() bfin_read32(SICB_IMASK1)
-#define bfin_write_SICB_IMASK1(val) bfin_write32(SICB_IMASK1,val)
-#define bfin_read_SICB_IAR0() bfin_read32(SICB_IAR0)
-#define bfin_write_SICB_IAR0(val) bfin_write32(SICB_IAR0,val)
-#define bfin_read_SICB_IAR1() bfin_read32(SICB_IAR1)
-#define bfin_write_SICB_IAR1(val) bfin_write32(SICB_IAR1,val)
-#define bfin_read_SICB_IAR2() bfin_read32(SICB_IAR2)
-#define bfin_write_SICB_IAR2(val) bfin_write32(SICB_IAR2,val)
-#define bfin_read_SICB_IAR3() bfin_read32(SICB_IAR3)
-#define bfin_write_SICB_IAR3(val) bfin_write32(SICB_IAR3,val)
-#define bfin_read_SICB_IAR4() bfin_read32(SICB_IAR4)
-#define bfin_write_SICB_IAR4(val) bfin_write32(SICB_IAR4,val)
-#define bfin_read_SICB_IAR5() bfin_read32(SICB_IAR5)
-#define bfin_write_SICB_IAR5(val) bfin_write32(SICB_IAR5,val)
-#define bfin_read_SICB_IAR6() bfin_read32(SICB_IAR6)
-#define bfin_write_SICB_IAR6(val) bfin_write32(SICB_IAR6,val)
-#define bfin_read_SICB_IAR7() bfin_read32(SICB_IAR7)
-#define bfin_write_SICB_IAR7(val) bfin_write32(SICB_IAR7,val)
-#define bfin_read_SICB_ISR0() bfin_read32(SICB_ISR0)
-#define bfin_write_SICB_ISR0(val) bfin_write32(SICB_ISR0,val)
-#define bfin_read_SICB_ISR1() bfin_read32(SICB_ISR1)
-#define bfin_write_SICB_ISR1(val) bfin_write32(SICB_ISR1,val)
-#define bfin_read_SICB_IWR0() bfin_read32(SICB_IWR0)
-#define bfin_write_SICB_IWR0(val) bfin_write32(SICB_IWR0,val)
-#define bfin_read_SICB_IWR1() bfin_read32(SICB_IWR1)
-#define bfin_write_SICB_IWR1(val) bfin_write32(SICB_IWR1,val)
-/* Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) */
-#define bfin_read_WDOGA_CTL() bfin_read16(WDOGA_CTL)
-#define bfin_write_WDOGA_CTL(val) bfin_write16(WDOGA_CTL,val)
-#define bfin_read_WDOGA_CNT() bfin_read32(WDOGA_CNT)
-#define bfin_write_WDOGA_CNT(val) bfin_write32(WDOGA_CNT,val)
-#define bfin_read_WDOGA_STAT() bfin_read32(WDOGA_STAT)
-#define bfin_write_WDOGA_STAT(val) bfin_write32(WDOGA_STAT,val)
-
-/* Watchdog Timer registers for Core B (0xFFC0 1200-0xFFC0 12FF) */
-#define bfin_read_WDOGB_CTL() bfin_read16(WDOGB_CTL)
-#define bfin_write_WDOGB_CTL(val) bfin_write16(WDOGB_CTL,val)
-#define bfin_read_WDOGB_CNT() bfin_read32(WDOGB_CNT)
-#define bfin_write_WDOGB_CNT(val) bfin_write32(WDOGB_CNT,val)
-#define bfin_read_WDOGB_STAT() bfin_read32(WDOGB_STAT)
-#define bfin_write_WDOGB_STAT(val) bfin_write32(WDOGB_STAT,val)
-
-/* UART Controller (0xFFC00400 - 0xFFC004FF) */
-#define bfin_read_UART_THR() bfin_read16(UART_THR)
-#define bfin_write_UART_THR(val) bfin_write16(UART_THR,val)
-#define bfin_read_UART_RBR() bfin_read16(UART_RBR)
-#define bfin_write_UART_RBR(val) bfin_write16(UART_RBR,val)
-#define bfin_read_UART_DLL() bfin_read16(UART_DLL)
-#define bfin_write_UART_DLL(val) bfin_write16(UART_DLL,val)
-#define bfin_read_UART_IER() bfin_read16(UART_IER)
-#define bfin_write_UART_IER(val) bfin_write16(UART_IER,val)
-#define bfin_read_UART_DLH() bfin_read16(UART_DLH)
-#define bfin_write_UART_DLH(val) bfin_write16(UART_DLH,val)
-#define bfin_read_UART_IIR() bfin_read16(UART_IIR)
-#define bfin_write_UART_IIR(val) bfin_write16(UART_IIR,val)
-#define bfin_read_UART_LCR() bfin_read16(UART_LCR)
-#define bfin_write_UART_LCR(val) bfin_write16(UART_LCR,val)
-#define bfin_read_UART_MCR() bfin_read16(UART_MCR)
-#define bfin_write_UART_MCR(val) bfin_write16(UART_MCR,val)
-#define bfin_read_UART_LSR() bfin_read16(UART_LSR)
-#define bfin_write_UART_LSR(val) bfin_write16(UART_LSR,val)
-#define bfin_read_UART_MSR() bfin_read16(UART_MSR)
-#define bfin_write_UART_MSR(val) bfin_write16(UART_MSR,val)
-#define bfin_read_UART_SCR() bfin_read16(UART_SCR)
-#define bfin_write_UART_SCR(val) bfin_write16(UART_SCR,val)
-#define bfin_read_UART_GCTL() bfin_read16(UART_GCTL)
-#define bfin_write_UART_GCTL(val) bfin_write16(UART_GCTL,val)
-
-/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
-#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL)
-#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL,val)
-#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG)
-#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG,val)
-#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT)
-#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT,val)
-#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR)
-#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR,val)
-#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR)
-#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR,val)
-#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD)
-#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD,val)
-#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW)
-#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW,val)
-
-/* Timer 0-7 registers (0xFFC0 0600-0xFFC0 06FF) */
-#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG,val)
-#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER,val)
-#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD,val)
-#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH,val)
-#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG,val)
-#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER,val)
-#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD,val)
-#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH,val)
-#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG,val)
-#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER,val)
-#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD,val)
-#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH,val)
-#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
-#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG,val)
-#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
-#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER,val)
-#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
-#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD,val)
-#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
-#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH,val)
-#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
-#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG,val)
-#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
-#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER,val)
-#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
-#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD,val)
-#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
-#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH,val)
-#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
-#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG,val)
-#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
-#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER,val)
-#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
-#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD,val)
-#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
-#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH,val)
-#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
-#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG,val)
-#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
-#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER,val)
-#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
-#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD,val)
-#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
-#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH,val)
-#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
-#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG,val)
-#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
-#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER,val)
-#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
-#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD,val)
-#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
-#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH,val)
-
-/* Timer registers 8-11 (0xFFC0 1600-0xFFC0 16FF) */
-#define bfin_read_TMRS8_ENABLE() bfin_read16(TMRS8_ENABLE)
-#define bfin_write_TMRS8_ENABLE(val) bfin_write16(TMRS8_ENABLE,val)
-#define bfin_read_TMRS8_DISABLE() bfin_read16(TMRS8_DISABLE)
-#define bfin_write_TMRS8_DISABLE(val) bfin_write16(TMRS8_DISABLE,val)
-#define bfin_read_TMRS8_STATUS() bfin_read32(TMRS8_STATUS)
-#define bfin_write_TMRS8_STATUS(val) bfin_write32(TMRS8_STATUS,val)
-#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG)
-#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG,val)
-#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER)
-#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER,val)
-#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD)
-#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD,val)
-#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH)
-#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH,val)
-#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG)
-#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG,val)
-#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER)
-#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER,val)
-#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD)
-#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD,val)
-#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH)
-#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH,val)
-#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG)
-#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG,val)
-#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER)
-#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER,val)
-#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD)
-#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD,val)
-#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH)
-#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH,val)
-#define bfin_read_TIMER11_CONFIG() bfin_read16(TIMER11_CONFIG)
-#define bfin_write_TIMER11_CONFIG(val) bfin_write16(TIMER11_CONFIG,val)
-#define bfin_read_TIMER11_COUNTER() bfin_read32(TIMER11_COUNTER)
-#define bfin_write_TIMER11_COUNTER(val) bfin_write32(TIMER11_COUNTER,val)
-#define bfin_read_TIMER11_PERIOD() bfin_read32(TIMER11_PERIOD)
-#define bfin_write_TIMER11_PERIOD(val) bfin_write32(TIMER11_PERIOD,val)
-#define bfin_read_TIMER11_WIDTH() bfin_read32(TIMER11_WIDTH)
-#define bfin_write_TIMER11_WIDTH(val) bfin_write32(TIMER11_WIDTH,val)
-#define bfin_read_TMRS4_ENABLE() bfin_read16(TMRS4_ENABLE)
-#define bfin_write_TMRS4_ENABLE(val) bfin_write16(TMRS4_ENABLE,val)
-#define bfin_read_TMRS4_DISABLE() bfin_read16(TMRS4_DISABLE)
-#define bfin_write_TMRS4_DISABLE(val) bfin_write16(TMRS4_DISABLE,val)
-#define bfin_read_TMRS4_STATUS() bfin_read32(TMRS4_STATUS)
-#define bfin_write_TMRS4_STATUS(val) bfin_write32(TMRS4_STATUS,val)
-
-/* Programmable Flag 0 registers (0xFFC0 0700-0xFFC0 07FF) */
-#define bfin_read_FIO0_FLAG_D() bfin_read16(FIO0_FLAG_D)
-#define bfin_write_FIO0_FLAG_D(val) bfin_write16(FIO0_FLAG_D,val)
-#define bfin_read_FIO0_FLAG_C() bfin_read16(FIO0_FLAG_C)
-#define bfin_write_FIO0_FLAG_C(val) bfin_write16(FIO0_FLAG_C,val)
-#define bfin_read_FIO0_FLAG_S() bfin_read16(FIO0_FLAG_S)
-#define bfin_write_FIO0_FLAG_S(val) bfin_write16(FIO0_FLAG_S,val)
-#define bfin_read_FIO0_FLAG_T() bfin_read16(FIO0_FLAG_T)
-#define bfin_write_FIO0_FLAG_T(val) bfin_write16(FIO0_FLAG_T,val)
-#define bfin_read_FIO0_MASKA_D() bfin_read16(FIO0_MASKA_D)
-#define bfin_write_FIO0_MASKA_D(val) bfin_write16(FIO0_MASKA_D,val)
-#define bfin_read_FIO0_MASKA_C() bfin_read16(FIO0_MASKA_C)
-#define bfin_write_FIO0_MASKA_C(val) bfin_write16(FIO0_MASKA_C,val)
-#define bfin_read_FIO0_MASKA_S() bfin_read16(FIO0_MASKA_S)
-#define bfin_write_FIO0_MASKA_S(val) bfin_write16(FIO0_MASKA_S,val)
-#define bfin_read_FIO0_MASKA_T() bfin_read16(FIO0_MASKA_T)
-#define bfin_write_FIO0_MASKA_T(val) bfin_write16(FIO0_MASKA_T,val)
-#define bfin_read_FIO0_MASKB_D() bfin_read16(FIO0_MASKB_D)
-#define bfin_write_FIO0_MASKB_D(val) bfin_write16(FIO0_MASKB_D,val)
-#define bfin_read_FIO0_MASKB_C() bfin_read16(FIO0_MASKB_C)
-#define bfin_write_FIO0_MASKB_C(val) bfin_write16(FIO0_MASKB_C,val)
-#define bfin_read_FIO0_MASKB_S() bfin_read16(FIO0_MASKB_S)
-#define bfin_write_FIO0_MASKB_S(val) bfin_write16(FIO0_MASKB_S,val)
-#define bfin_read_FIO0_MASKB_T() bfin_read16(FIO0_MASKB_T)
-#define bfin_write_FIO0_MASKB_T(val) bfin_write16(FIO0_MASKB_T,val)
-#define bfin_read_FIO0_DIR() bfin_read16(FIO0_DIR)
-#define bfin_write_FIO0_DIR(val) bfin_write16(FIO0_DIR,val)
-#define bfin_read_FIO0_POLAR() bfin_read16(FIO0_POLAR)
-#define bfin_write_FIO0_POLAR(val) bfin_write16(FIO0_POLAR,val)
-#define bfin_read_FIO0_EDGE() bfin_read16(FIO0_EDGE)
-#define bfin_write_FIO0_EDGE(val) bfin_write16(FIO0_EDGE,val)
-#define bfin_read_FIO0_BOTH() bfin_read16(FIO0_BOTH)
-#define bfin_write_FIO0_BOTH(val) bfin_write16(FIO0_BOTH,val)
-#define bfin_read_FIO0_INEN() bfin_read16(FIO0_INEN)
-#define bfin_write_FIO0_INEN(val) bfin_write16(FIO0_INEN,val)
-/* Programmable Flag 1 registers (0xFFC0 1500-0xFFC0 15FF) */
-#define bfin_read_FIO1_FLAG_D() bfin_read16(FIO1_FLAG_D)
-#define bfin_write_FIO1_FLAG_D(val) bfin_write16(FIO1_FLAG_D,val)
-#define bfin_read_FIO1_FLAG_C() bfin_read16(FIO1_FLAG_C)
-#define bfin_write_FIO1_FLAG_C(val) bfin_write16(FIO1_FLAG_C,val)
-#define bfin_read_FIO1_FLAG_S() bfin_read16(FIO1_FLAG_S)
-#define bfin_write_FIO1_FLAG_S(val) bfin_write16(FIO1_FLAG_S,val)
-#define bfin_read_FIO1_FLAG_T() bfin_read16(FIO1_FLAG_T)
-#define bfin_write_FIO1_FLAG_T(val) bfin_write16(FIO1_FLAG_T,val)
-#define bfin_read_FIO1_MASKA_D() bfin_read16(FIO1_MASKA_D)
-#define bfin_write_FIO1_MASKA_D(val) bfin_write16(FIO1_MASKA_D,val)
-#define bfin_read_FIO1_MASKA_C() bfin_read16(FIO1_MASKA_C)
-#define bfin_write_FIO1_MASKA_C(val) bfin_write16(FIO1_MASKA_C,val)
-#define bfin_read_FIO1_MASKA_S() bfin_read16(FIO1_MASKA_S)
-#define bfin_write_FIO1_MASKA_S(val) bfin_write16(FIO1_MASKA_S,val)
-#define bfin_read_FIO1_MASKA_T() bfin_read16(FIO1_MASKA_T)
-#define bfin_write_FIO1_MASKA_T(val) bfin_write16(FIO1_MASKA_T,val)
-#define bfin_read_FIO1_MASKB_D() bfin_read16(FIO1_MASKB_D)
-#define bfin_write_FIO1_MASKB_D(val) bfin_write16(FIO1_MASKB_D,val)
-#define bfin_read_FIO1_MASKB_C() bfin_read16(FIO1_MASKB_C)
-#define bfin_write_FIO1_MASKB_C(val) bfin_write16(FIO1_MASKB_C,val)
-#define bfin_read_FIO1_MASKB_S() bfin_read16(FIO1_MASKB_S)
-#define bfin_write_FIO1_MASKB_S(val) bfin_write16(FIO1_MASKB_S,val)
-#define bfin_read_FIO1_MASKB_T() bfin_read16(FIO1_MASKB_T)
-#define bfin_write_FIO1_MASKB_T(val) bfin_write16(FIO1_MASKB_T,val)
-#define bfin_read_FIO1_DIR() bfin_read16(FIO1_DIR)
-#define bfin_write_FIO1_DIR(val) bfin_write16(FIO1_DIR,val)
-#define bfin_read_FIO1_POLAR() bfin_read16(FIO1_POLAR)
-#define bfin_write_FIO1_POLAR(val) bfin_write16(FIO1_POLAR,val)
-#define bfin_read_FIO1_EDGE() bfin_read16(FIO1_EDGE)
-#define bfin_write_FIO1_EDGE(val) bfin_write16(FIO1_EDGE,val)
-#define bfin_read_FIO1_BOTH() bfin_read16(FIO1_BOTH)
-#define bfin_write_FIO1_BOTH(val) bfin_write16(FIO1_BOTH,val)
-#define bfin_read_FIO1_INEN() bfin_read16(FIO1_INEN)
-#define bfin_write_FIO1_INEN(val) bfin_write16(FIO1_INEN,val)
-/* Programmable Flag registers (0xFFC0 1700-0xFFC0 17FF) */
-#define bfin_read_FIO2_FLAG_D() bfin_read16(FIO2_FLAG_D)
-#define bfin_write_FIO2_FLAG_D(val) bfin_write16(FIO2_FLAG_D,val)
-#define bfin_read_FIO2_FLAG_C() bfin_read16(FIO2_FLAG_C)
-#define bfin_write_FIO2_FLAG_C(val) bfin_write16(FIO2_FLAG_C,val)
-#define bfin_read_FIO2_FLAG_S() bfin_read16(FIO2_FLAG_S)
-#define bfin_write_FIO2_FLAG_S(val) bfin_write16(FIO2_FLAG_S,val)
-#define bfin_read_FIO2_FLAG_T() bfin_read16(FIO2_FLAG_T)
-#define bfin_write_FIO2_FLAG_T(val) bfin_write16(FIO2_FLAG_T,val)
-#define bfin_read_FIO2_MASKA_D() bfin_read16(FIO2_MASKA_D)
-#define bfin_write_FIO2_MASKA_D(val) bfin_write16(FIO2_MASKA_D,val)
-#define bfin_read_FIO2_MASKA_C() bfin_read16(FIO2_MASKA_C)
-#define bfin_write_FIO2_MASKA_C(val) bfin_write16(FIO2_MASKA_C,val)
-#define bfin_read_FIO2_MASKA_S() bfin_read16(FIO2_MASKA_S)
-#define bfin_write_FIO2_MASKA_S(val) bfin_write16(FIO2_MASKA_S,val)
-#define bfin_read_FIO2_MASKA_T() bfin_read16(FIO2_MASKA_T)
-#define bfin_write_FIO2_MASKA_T(val) bfin_write16(FIO2_MASKA_T,val)
-#define bfin_read_FIO2_MASKB_D() bfin_read16(FIO2_MASKB_D)
-#define bfin_write_FIO2_MASKB_D(val) bfin_write16(FIO2_MASKB_D,val)
-#define bfin_read_FIO2_MASKB_C() bfin_read16(FIO2_MASKB_C)
-#define bfin_write_FIO2_MASKB_C(val) bfin_write16(FIO2_MASKB_C,val)
-#define bfin_read_FIO2_MASKB_S() bfin_read16(FIO2_MASKB_S)
-#define bfin_write_FIO2_MASKB_S(val) bfin_write16(FIO2_MASKB_S,val)
-#define bfin_read_FIO2_MASKB_T() bfin_read16(FIO2_MASKB_T)
-#define bfin_write_FIO2_MASKB_T(val) bfin_write16(FIO2_MASKB_T,val)
-#define bfin_read_FIO2_DIR() bfin_read16(FIO2_DIR)
-#define bfin_write_FIO2_DIR(val) bfin_write16(FIO2_DIR,val)
-#define bfin_read_FIO2_POLAR() bfin_read16(FIO2_POLAR)
-#define bfin_write_FIO2_POLAR(val) bfin_write16(FIO2_POLAR,val)
-#define bfin_read_FIO2_EDGE() bfin_read16(FIO2_EDGE)
-#define bfin_write_FIO2_EDGE(val) bfin_write16(FIO2_EDGE,val)
-#define bfin_read_FIO2_BOTH() bfin_read16(FIO2_BOTH)
-#define bfin_write_FIO2_BOTH(val) bfin_write16(FIO2_BOTH,val)
-#define bfin_read_FIO2_INEN() bfin_read16(FIO2_INEN)
-#define bfin_write_FIO2_INEN(val) bfin_write16(FIO2_INEN,val)
-/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
-#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1,val)
-#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2,val)
-#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV,val)
-#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV,val)
-#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX,val)
-#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX,val)
-#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX,val)
-#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX,val)
-#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX)
-#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX,val)
-#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX)
-#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX,val)
-#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1,val)
-#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2,val)
-#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV,val)
-#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV,val)
-#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT,val)
-#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL,val)
-#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1,val)
-#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2,val)
-#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0,val)
-#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1,val)
-#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2,val)
-#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3,val)
-#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0,val)
-#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1,val)
-#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2,val)
-#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3,val)
-/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
-#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1,val)
-#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2,val)
-#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV,val)
-#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV,val)
-#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX,val)
-#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX,val)
-#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX,val)
-#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX,val)
-#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX)
-#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX,val)
-#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX)
-#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX,val)
-#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1,val)
-#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2,val)
-#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV,val)
-#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV,val)
-#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT,val)
-#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL,val)
-#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1,val)
-#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2,val)
-#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
-#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0,val)
-#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
-#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1,val)
-#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
-#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2,val)
-#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
-#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3,val)
-#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
-#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0,val)
-#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
-#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1,val)
-#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
-#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2,val)
-#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
-#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3,val)
-/* Asynchronous Memory Controller - External Bus Interface Unit */
-#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL,val)
-#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0,val)
-#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1,val)
-/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
-#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
-#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL,val)
-#define bfin_read_EBIU_SDBCTL() bfin_read32(EBIU_SDBCTL)
-#define bfin_write_EBIU_SDBCTL(val) bfin_write32(EBIU_SDBCTL,val)
-#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
-#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC,val)
-#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
-#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT,val)
-/* Parallel Peripheral Interface (PPI) 0 registers (0xFFC0 1000-0xFFC0 10FF) */
-#define bfin_read_PPI0_CONTROL() bfin_read16(PPI0_CONTROL)
-#define bfin_write_PPI0_CONTROL(val) bfin_write16(PPI0_CONTROL,val)
-#define bfin_read_PPI0_STATUS() bfin_read16(PPI0_STATUS)
-#define bfin_write_PPI0_STATUS(val) bfin_write16(PPI0_STATUS,val)
-#define bfin_clear_PPI0_STATUS() bfin_read_PPI0_STATUS()
-#define bfin_read_PPI0_COUNT() bfin_read16(PPI0_COUNT)
-#define bfin_write_PPI0_COUNT(val) bfin_write16(PPI0_COUNT,val)
-#define bfin_read_PPI0_DELAY() bfin_read16(PPI0_DELAY)
-#define bfin_write_PPI0_DELAY(val) bfin_write16(PPI0_DELAY,val)
-#define bfin_read_PPI0_FRAME() bfin_read16(PPI0_FRAME)
-#define bfin_write_PPI0_FRAME(val) bfin_write16(PPI0_FRAME,val)
-/* Parallel Peripheral Interface (PPI) 1 registers (0xFFC0 1300-0xFFC0 13FF) */
-#define bfin_read_PPI1_CONTROL() bfin_read16(PPI1_CONTROL)
-#define bfin_write_PPI1_CONTROL(val) bfin_write16(PPI1_CONTROL,val)
-#define bfin_read_PPI1_STATUS() bfin_read16(PPI1_STATUS)
-#define bfin_write_PPI1_STATUS(val) bfin_write16(PPI1_STATUS,val)
-#define bfin_clear_PPI1_STATUS() bfin_read_PPI1_STATUS()
-#define bfin_read_PPI1_COUNT() bfin_read16(PPI1_COUNT)
-#define bfin_write_PPI1_COUNT(val) bfin_write16(PPI1_COUNT,val)
-#define bfin_read_PPI1_DELAY() bfin_read16(PPI1_DELAY)
-#define bfin_write_PPI1_DELAY(val) bfin_write16(PPI1_DELAY,val)
-#define bfin_read_PPI1_FRAME() bfin_read16(PPI1_FRAME)
-#define bfin_write_PPI1_FRAME(val) bfin_write16(PPI1_FRAME,val)
-/*DMA traffic control registers */
-#define bfin_read_DMAC0_TC_PER() bfin_read16(DMAC0_TC_PER)
-#define bfin_write_DMAC0_TC_PER(val) bfin_write16(DMAC0_TC_PER,val)
-#define bfin_read_DMAC0_TC_CNT() bfin_read16(DMAC0_TC_CNT)
-#define bfin_write_DMAC0_TC_CNT(val) bfin_write16(DMAC0_TC_CNT,val)
-#define bfin_read_DMAC1_TC_PER() bfin_read16(DMAC1_TC_PER)
-#define bfin_write_DMAC1_TC_PER(val) bfin_write16(DMAC1_TC_PER,val)
-#define bfin_read_DMAC1_TC_CNT() bfin_read16(DMAC1_TC_CNT)
-#define bfin_write_DMAC1_TC_CNT(val) bfin_write16(DMAC1_TC_CNT,val)
-/* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */
-#define bfin_read_DMA1_0_CONFIG() bfin_read16(DMA1_0_CONFIG)
-#define bfin_write_DMA1_0_CONFIG(val) bfin_write16(DMA1_0_CONFIG,val)
-#define bfin_read_DMA1_0_NEXT_DESC_PTR() bfin_read32(DMA1_0_NEXT_DESC_PTR)
-#define bfin_write_DMA1_0_NEXT_DESC_PTR(val) bfin_write32(DMA1_0_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_0_START_ADDR() bfin_read32(DMA1_0_START_ADDR)
-#define bfin_write_DMA1_0_START_ADDR(val) bfin_write32(DMA1_0_START_ADDR,val)
-#define bfin_read_DMA1_0_X_COUNT() bfin_read16(DMA1_0_X_COUNT)
-#define bfin_write_DMA1_0_X_COUNT(val) bfin_write16(DMA1_0_X_COUNT,val)
-#define bfin_read_DMA1_0_Y_COUNT() bfin_read16(DMA1_0_Y_COUNT)
-#define bfin_write_DMA1_0_Y_COUNT(val) bfin_write16(DMA1_0_Y_COUNT,val)
-#define bfin_read_DMA1_0_X_MODIFY() bfin_read16(DMA1_0_X_MODIFY)
-#define bfin_write_DMA1_0_X_MODIFY(val) bfin_write16(DMA1_0_X_MODIFY,val)
-#define bfin_read_DMA1_0_Y_MODIFY() bfin_read16(DMA1_0_Y_MODIFY)
-#define bfin_write_DMA1_0_Y_MODIFY(val) bfin_write16(DMA1_0_Y_MODIFY,val)
-#define bfin_read_DMA1_0_CURR_DESC_PTR() bfin_read32(DMA1_0_CURR_DESC_PTR)
-#define bfin_write_DMA1_0_CURR_DESC_PTR(val) bfin_write32(DMA1_0_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_0_CURR_ADDR() bfin_read32(DMA1_0_CURR_ADDR)
-#define bfin_write_DMA1_0_CURR_ADDR(val) bfin_write32(DMA1_0_CURR_ADDR,val)
-#define bfin_read_DMA1_0_CURR_X_COUNT() bfin_read16(DMA1_0_CURR_X_COUNT)
-#define bfin_write_DMA1_0_CURR_X_COUNT(val) bfin_write16(DMA1_0_CURR_X_COUNT,val)
-#define bfin_read_DMA1_0_CURR_Y_COUNT() bfin_read16(DMA1_0_CURR_Y_COUNT)
-#define bfin_write_DMA1_0_CURR_Y_COUNT(val) bfin_write16(DMA1_0_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_0_IRQ_STATUS() bfin_read16(DMA1_0_IRQ_STATUS)
-#define bfin_write_DMA1_0_IRQ_STATUS(val) bfin_write16(DMA1_0_IRQ_STATUS,val)
-#define bfin_read_DMA1_0_PERIPHERAL_MAP() bfin_read16(DMA1_0_PERIPHERAL_MAP)
-#define bfin_write_DMA1_0_PERIPHERAL_MAP(val) bfin_write16(DMA1_0_PERIPHERAL_MAP,val)
-#define bfin_read_DMA1_1_CONFIG() bfin_read16(DMA1_1_CONFIG)
-#define bfin_write_DMA1_1_CONFIG(val) bfin_write16(DMA1_1_CONFIG,val)
-#define bfin_read_DMA1_1_NEXT_DESC_PTR() bfin_read32(DMA1_1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_1_NEXT_DESC_PTR(val) bfin_write32(DMA1_1_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_1_START_ADDR() bfin_read32(DMA1_1_START_ADDR)
-#define bfin_write_DMA1_1_START_ADDR(val) bfin_write32(DMA1_1_START_ADDR,val)
-#define bfin_read_DMA1_1_X_COUNT() bfin_read16(DMA1_1_X_COUNT)
-#define bfin_write_DMA1_1_X_COUNT(val) bfin_write16(DMA1_1_X_COUNT,val)
-#define bfin_read_DMA1_1_Y_COUNT() bfin_read16(DMA1_1_Y_COUNT)
-#define bfin_write_DMA1_1_Y_COUNT(val) bfin_write16(DMA1_1_Y_COUNT,val)
-#define bfin_read_DMA1_1_X_MODIFY() bfin_read16(DMA1_1_X_MODIFY)
-#define bfin_write_DMA1_1_X_MODIFY(val) bfin_write16(DMA1_1_X_MODIFY,val)
-#define bfin_read_DMA1_1_Y_MODIFY() bfin_read16(DMA1_1_Y_MODIFY)
-#define bfin_write_DMA1_1_Y_MODIFY(val) bfin_write16(DMA1_1_Y_MODIFY,val)
-#define bfin_read_DMA1_1_CURR_DESC_PTR() bfin_read32(DMA1_1_CURR_DESC_PTR)
-#define bfin_write_DMA1_1_CURR_DESC_PTR(val) bfin_write32(DMA1_1_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_1_CURR_ADDR() bfin_read32(DMA1_1_CURR_ADDR)
-#define bfin_write_DMA1_1_CURR_ADDR(val) bfin_write32(DMA1_1_CURR_ADDR,val)
-#define bfin_read_DMA1_1_CURR_X_COUNT() bfin_read16(DMA1_1_CURR_X_COUNT)
-#define bfin_write_DMA1_1_CURR_X_COUNT(val) bfin_write16(DMA1_1_CURR_X_COUNT,val)
-#define bfin_read_DMA1_1_CURR_Y_COUNT() bfin_read16(DMA1_1_CURR_Y_COUNT)
-#define bfin_write_DMA1_1_CURR_Y_COUNT(val) bfin_write16(DMA1_1_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_1_IRQ_STATUS() bfin_read16(DMA1_1_IRQ_STATUS)
-#define bfin_write_DMA1_1_IRQ_STATUS(val) bfin_write16(DMA1_1_IRQ_STATUS,val)
-#define bfin_read_DMA1_1_PERIPHERAL_MAP() bfin_read16(DMA1_1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_1_PERIPHERAL_MAP(val) bfin_write16(DMA1_1_PERIPHERAL_MAP,val)
-#define bfin_read_DMA1_2_CONFIG() bfin_read16(DMA1_2_CONFIG)
-#define bfin_write_DMA1_2_CONFIG(val) bfin_write16(DMA1_2_CONFIG,val)
-#define bfin_read_DMA1_2_NEXT_DESC_PTR() bfin_read32(DMA1_2_NEXT_DESC_PTR)
-#define bfin_write_DMA1_2_NEXT_DESC_PTR(val) bfin_write32(DMA1_2_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_2_START_ADDR() bfin_read32(DMA1_2_START_ADDR)
-#define bfin_write_DMA1_2_START_ADDR(val) bfin_write32(DMA1_2_START_ADDR,val)
-#define bfin_read_DMA1_2_X_COUNT() bfin_read16(DMA1_2_X_COUNT)
-#define bfin_write_DMA1_2_X_COUNT(val) bfin_write16(DMA1_2_X_COUNT,val)
-#define bfin_read_DMA1_2_Y_COUNT() bfin_read16(DMA1_2_Y_COUNT)
-#define bfin_write_DMA1_2_Y_COUNT(val) bfin_write16(DMA1_2_Y_COUNT,val)
-#define bfin_read_DMA1_2_X_MODIFY() bfin_read16(DMA1_2_X_MODIFY)
-#define bfin_write_DMA1_2_X_MODIFY(val) bfin_write16(DMA1_2_X_MODIFY,val)
-#define bfin_read_DMA1_2_Y_MODIFY() bfin_read16(DMA1_2_Y_MODIFY)
-#define bfin_write_DMA1_2_Y_MODIFY(val) bfin_write16(DMA1_2_Y_MODIFY,val)
-#define bfin_read_DMA1_2_CURR_DESC_PTR() bfin_read32(DMA1_2_CURR_DESC_PTR)
-#define bfin_write_DMA1_2_CURR_DESC_PTR(val) bfin_write32(DMA1_2_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_2_CURR_ADDR() bfin_read32(DMA1_2_CURR_ADDR)
-#define bfin_write_DMA1_2_CURR_ADDR(val) bfin_write32(DMA1_2_CURR_ADDR,val)
-#define bfin_read_DMA1_2_CURR_X_COUNT() bfin_read16(DMA1_2_CURR_X_COUNT)
-#define bfin_write_DMA1_2_CURR_X_COUNT(val) bfin_write16(DMA1_2_CURR_X_COUNT,val)
-#define bfin_read_DMA1_2_CURR_Y_COUNT() bfin_read16(DMA1_2_CURR_Y_COUNT)
-#define bfin_write_DMA1_2_CURR_Y_COUNT(val) bfin_write16(DMA1_2_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_2_IRQ_STATUS() bfin_read16(DMA1_2_IRQ_STATUS)
-#define bfin_write_DMA1_2_IRQ_STATUS(val) bfin_write16(DMA1_2_IRQ_STATUS,val)
-#define bfin_read_DMA1_2_PERIPHERAL_MAP() bfin_read16(DMA1_2_PERIPHERAL_MAP)
-#define bfin_write_DMA1_2_PERIPHERAL_MAP(val) bfin_write16(DMA1_2_PERIPHERAL_MAP,val)
-#define bfin_read_DMA1_3_CONFIG() bfin_read16(DMA1_3_CONFIG)
-#define bfin_write_DMA1_3_CONFIG(val) bfin_write16(DMA1_3_CONFIG,val)
-#define bfin_read_DMA1_3_NEXT_DESC_PTR() bfin_read32(DMA1_3_NEXT_DESC_PTR)
-#define bfin_write_DMA1_3_NEXT_DESC_PTR(val) bfin_write32(DMA1_3_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_3_START_ADDR() bfin_read32(DMA1_3_START_ADDR)
-#define bfin_write_DMA1_3_START_ADDR(val) bfin_write32(DMA1_3_START_ADDR,val)
-#define bfin_read_DMA1_3_X_COUNT() bfin_read16(DMA1_3_X_COUNT)
-#define bfin_write_DMA1_3_X_COUNT(val) bfin_write16(DMA1_3_X_COUNT,val)
-#define bfin_read_DMA1_3_Y_COUNT() bfin_read16(DMA1_3_Y_COUNT)
-#define bfin_write_DMA1_3_Y_COUNT(val) bfin_write16(DMA1_3_Y_COUNT,val)
-#define bfin_read_DMA1_3_X_MODIFY() bfin_read16(DMA1_3_X_MODIFY)
-#define bfin_write_DMA1_3_X_MODIFY(val) bfin_write16(DMA1_3_X_MODIFY,val)
-#define bfin_read_DMA1_3_Y_MODIFY() bfin_read16(DMA1_3_Y_MODIFY)
-#define bfin_write_DMA1_3_Y_MODIFY(val) bfin_write16(DMA1_3_Y_MODIFY,val)
-#define bfin_read_DMA1_3_CURR_DESC_PTR() bfin_read32(DMA1_3_CURR_DESC_PTR)
-#define bfin_write_DMA1_3_CURR_DESC_PTR(val) bfin_write32(DMA1_3_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_3_CURR_ADDR() bfin_read32(DMA1_3_CURR_ADDR)
-#define bfin_write_DMA1_3_CURR_ADDR(val) bfin_write32(DMA1_3_CURR_ADDR,val)
-#define bfin_read_DMA1_3_CURR_X_COUNT() bfin_read16(DMA1_3_CURR_X_COUNT)
-#define bfin_write_DMA1_3_CURR_X_COUNT(val) bfin_write16(DMA1_3_CURR_X_COUNT,val)
-#define bfin_read_DMA1_3_CURR_Y_COUNT() bfin_read16(DMA1_3_CURR_Y_COUNT)
-#define bfin_write_DMA1_3_CURR_Y_COUNT(val) bfin_write16(DMA1_3_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_3_IRQ_STATUS() bfin_read16(DMA1_3_IRQ_STATUS)
-#define bfin_write_DMA1_3_IRQ_STATUS(val) bfin_write16(DMA1_3_IRQ_STATUS,val)
-#define bfin_read_DMA1_3_PERIPHERAL_MAP() bfin_read16(DMA1_3_PERIPHERAL_MAP)
-#define bfin_write_DMA1_3_PERIPHERAL_MAP(val) bfin_write16(DMA1_3_PERIPHERAL_MAP,val)
-#define bfin_read_DMA1_4_CONFIG() bfin_read16(DMA1_4_CONFIG)
-#define bfin_write_DMA1_4_CONFIG(val) bfin_write16(DMA1_4_CONFIG,val)
-#define bfin_read_DMA1_4_NEXT_DESC_PTR() bfin_read32(DMA1_4_NEXT_DESC_PTR)
-#define bfin_write_DMA1_4_NEXT_DESC_PTR(val) bfin_write32(DMA1_4_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_4_START_ADDR() bfin_read32(DMA1_4_START_ADDR)
-#define bfin_write_DMA1_4_START_ADDR(val) bfin_write32(DMA1_4_START_ADDR,val)
-#define bfin_read_DMA1_4_X_COUNT() bfin_read16(DMA1_4_X_COUNT)
-#define bfin_write_DMA1_4_X_COUNT(val) bfin_write16(DMA1_4_X_COUNT,val)
-#define bfin_read_DMA1_4_Y_COUNT() bfin_read16(DMA1_4_Y_COUNT)
-#define bfin_write_DMA1_4_Y_COUNT(val) bfin_write16(DMA1_4_Y_COUNT,val)
-#define bfin_read_DMA1_4_X_MODIFY() bfin_read16(DMA1_4_X_MODIFY)
-#define bfin_write_DMA1_4_X_MODIFY(val) bfin_write16(DMA1_4_X_MODIFY,val)
-#define bfin_read_DMA1_4_Y_MODIFY() bfin_read16(DMA1_4_Y_MODIFY)
-#define bfin_write_DMA1_4_Y_MODIFY(val) bfin_write16(DMA1_4_Y_MODIFY,val)
-#define bfin_read_DMA1_4_CURR_DESC_PTR() bfin_read32(DMA1_4_CURR_DESC_PTR)
-#define bfin_write_DMA1_4_CURR_DESC_PTR(val) bfin_write32(DMA1_4_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_4_CURR_ADDR() bfin_read32(DMA1_4_CURR_ADDR)
-#define bfin_write_DMA1_4_CURR_ADDR(val) bfin_write32(DMA1_4_CURR_ADDR,val)
-#define bfin_read_DMA1_4_CURR_X_COUNT() bfin_read16(DMA1_4_CURR_X_COUNT)
-#define bfin_write_DMA1_4_CURR_X_COUNT(val) bfin_write16(DMA1_4_CURR_X_COUNT,val)
-#define bfin_read_DMA1_4_CURR_Y_COUNT() bfin_read16(DMA1_4_CURR_Y_COUNT)
-#define bfin_write_DMA1_4_CURR_Y_COUNT(val) bfin_write16(DMA1_4_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_4_IRQ_STATUS() bfin_read16(DMA1_4_IRQ_STATUS)
-#define bfin_write_DMA1_4_IRQ_STATUS(val) bfin_write16(DMA1_4_IRQ_STATUS,val)
-#define bfin_read_DMA1_4_PERIPHERAL_MAP() bfin_read16(DMA1_4_PERIPHERAL_MAP)
-#define bfin_write_DMA1_4_PERIPHERAL_MAP(val) bfin_write16(DMA1_4_PERIPHERAL_MAP,val)
-#define bfin_read_DMA1_5_CONFIG() bfin_read16(DMA1_5_CONFIG)
-#define bfin_write_DMA1_5_CONFIG(val) bfin_write16(DMA1_5_CONFIG,val)
-#define bfin_read_DMA1_5_NEXT_DESC_PTR() bfin_read32(DMA1_5_NEXT_DESC_PTR)
-#define bfin_write_DMA1_5_NEXT_DESC_PTR(val) bfin_write32(DMA1_5_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_5_START_ADDR() bfin_read32(DMA1_5_START_ADDR)
-#define bfin_write_DMA1_5_START_ADDR(val) bfin_write32(DMA1_5_START_ADDR,val)
-#define bfin_read_DMA1_5_X_COUNT() bfin_read16(DMA1_5_X_COUNT)
-#define bfin_write_DMA1_5_X_COUNT(val) bfin_write16(DMA1_5_X_COUNT,val)
-#define bfin_read_DMA1_5_Y_COUNT() bfin_read16(DMA1_5_Y_COUNT)
-#define bfin_write_DMA1_5_Y_COUNT(val) bfin_write16(DMA1_5_Y_COUNT,val)
-#define bfin_read_DMA1_5_X_MODIFY() bfin_read16(DMA1_5_X_MODIFY)
-#define bfin_write_DMA1_5_X_MODIFY(val) bfin_write16(DMA1_5_X_MODIFY,val)
-#define bfin_read_DMA1_5_Y_MODIFY() bfin_read16(DMA1_5_Y_MODIFY)
-#define bfin_write_DMA1_5_Y_MODIFY(val) bfin_write16(DMA1_5_Y_MODIFY,val)
-#define bfin_read_DMA1_5_CURR_DESC_PTR() bfin_read32(DMA1_5_CURR_DESC_PTR)
-#define bfin_write_DMA1_5_CURR_DESC_PTR(val) bfin_write32(DMA1_5_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_5_CURR_ADDR() bfin_read32(DMA1_5_CURR_ADDR)
-#define bfin_write_DMA1_5_CURR_ADDR(val) bfin_write32(DMA1_5_CURR_ADDR,val)
-#define bfin_read_DMA1_5_CURR_X_COUNT() bfin_read16(DMA1_5_CURR_X_COUNT)
-#define bfin_write_DMA1_5_CURR_X_COUNT(val) bfin_write16(DMA1_5_CURR_X_COUNT,val)
-#define bfin_read_DMA1_5_CURR_Y_COUNT() bfin_read16(DMA1_5_CURR_Y_COUNT)
-#define bfin_write_DMA1_5_CURR_Y_COUNT(val) bfin_write16(DMA1_5_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_5_IRQ_STATUS() bfin_read16(DMA1_5_IRQ_STATUS)
-#define bfin_write_DMA1_5_IRQ_STATUS(val) bfin_write16(DMA1_5_IRQ_STATUS,val)
-#define bfin_read_DMA1_5_PERIPHERAL_MAP() bfin_read16(DMA1_5_PERIPHERAL_MAP)
-#define bfin_write_DMA1_5_PERIPHERAL_MAP(val) bfin_write16(DMA1_5_PERIPHERAL_MAP,val)
-#define bfin_read_DMA1_6_CONFIG() bfin_read16(DMA1_6_CONFIG)
-#define bfin_write_DMA1_6_CONFIG(val) bfin_write16(DMA1_6_CONFIG,val)
-#define bfin_read_DMA1_6_NEXT_DESC_PTR() bfin_read32(DMA1_6_NEXT_DESC_PTR)
-#define bfin_write_DMA1_6_NEXT_DESC_PTR(val) bfin_write32(DMA1_6_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_6_START_ADDR() bfin_read32(DMA1_6_START_ADDR)
-#define bfin_write_DMA1_6_START_ADDR(val) bfin_write32(DMA1_6_START_ADDR,val)
-#define bfin_read_DMA1_6_X_COUNT() bfin_read16(DMA1_6_X_COUNT)
-#define bfin_write_DMA1_6_X_COUNT(val) bfin_write16(DMA1_6_X_COUNT,val)
-#define bfin_read_DMA1_6_Y_COUNT() bfin_read16(DMA1_6_Y_COUNT)
-#define bfin_write_DMA1_6_Y_COUNT(val) bfin_write16(DMA1_6_Y_COUNT,val)
-#define bfin_read_DMA1_6_X_MODIFY() bfin_read16(DMA1_6_X_MODIFY)
-#define bfin_write_DMA1_6_X_MODIFY(val) bfin_write16(DMA1_6_X_MODIFY,val)
-#define bfin_read_DMA1_6_Y_MODIFY() bfin_read16(DMA1_6_Y_MODIFY)
-#define bfin_write_DMA1_6_Y_MODIFY(val) bfin_write16(DMA1_6_Y_MODIFY,val)
-#define bfin_read_DMA1_6_CURR_DESC_PTR() bfin_read32(DMA1_6_CURR_DESC_PTR)
-#define bfin_write_DMA1_6_CURR_DESC_PTR(val) bfin_write32(DMA1_6_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_6_CURR_ADDR() bfin_read32(DMA1_6_CURR_ADDR)
-#define bfin_write_DMA1_6_CURR_ADDR(val) bfin_write32(DMA1_6_CURR_ADDR,val)
-#define bfin_read_DMA1_6_CURR_X_COUNT() bfin_read16(DMA1_6_CURR_X_COUNT)
-#define bfin_write_DMA1_6_CURR_X_COUNT(val) bfin_write16(DMA1_6_CURR_X_COUNT,val)
-#define bfin_read_DMA1_6_CURR_Y_COUNT() bfin_read16(DMA1_6_CURR_Y_COUNT)
-#define bfin_write_DMA1_6_CURR_Y_COUNT(val) bfin_write16(DMA1_6_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_6_IRQ_STATUS() bfin_read16(DMA1_6_IRQ_STATUS)
-#define bfin_write_DMA1_6_IRQ_STATUS(val) bfin_write16(DMA1_6_IRQ_STATUS,val)
-#define bfin_read_DMA1_6_PERIPHERAL_MAP() bfin_read16(DMA1_6_PERIPHERAL_MAP)
-#define bfin_write_DMA1_6_PERIPHERAL_MAP(val) bfin_write16(DMA1_6_PERIPHERAL_MAP,val)
-#define bfin_read_DMA1_7_CONFIG() bfin_read16(DMA1_7_CONFIG)
-#define bfin_write_DMA1_7_CONFIG(val) bfin_write16(DMA1_7_CONFIG,val)
-#define bfin_read_DMA1_7_NEXT_DESC_PTR() bfin_read32(DMA1_7_NEXT_DESC_PTR)
-#define bfin_write_DMA1_7_NEXT_DESC_PTR(val) bfin_write32(DMA1_7_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_7_START_ADDR() bfin_read32(DMA1_7_START_ADDR)
-#define bfin_write_DMA1_7_START_ADDR(val) bfin_write32(DMA1_7_START_ADDR,val)
-#define bfin_read_DMA1_7_X_COUNT() bfin_read16(DMA1_7_X_COUNT)
-#define bfin_write_DMA1_7_X_COUNT(val) bfin_write16(DMA1_7_X_COUNT,val)
-#define bfin_read_DMA1_7_Y_COUNT() bfin_read16(DMA1_7_Y_COUNT)
-#define bfin_write_DMA1_7_Y_COUNT(val) bfin_write16(DMA1_7_Y_COUNT,val)
-#define bfin_read_DMA1_7_X_MODIFY() bfin_read16(DMA1_7_X_MODIFY)
-#define bfin_write_DMA1_7_X_MODIFY(val) bfin_write16(DMA1_7_X_MODIFY,val)
-#define bfin_read_DMA1_7_Y_MODIFY() bfin_read16(DMA1_7_Y_MODIFY)
-#define bfin_write_DMA1_7_Y_MODIFY(val) bfin_write16(DMA1_7_Y_MODIFY,val)
-#define bfin_read_DMA1_7_CURR_DESC_PTR() bfin_read32(DMA1_7_CURR_DESC_PTR)
-#define bfin_write_DMA1_7_CURR_DESC_PTR(val) bfin_write32(DMA1_7_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_7_CURR_ADDR() bfin_read32(DMA1_7_CURR_ADDR)
-#define bfin_write_DMA1_7_CURR_ADDR(val) bfin_write32(DMA1_7_CURR_ADDR,val)
-#define bfin_read_DMA1_7_CURR_X_COUNT() bfin_read16(DMA1_7_CURR_X_COUNT)
-#define bfin_write_DMA1_7_CURR_X_COUNT(val) bfin_write16(DMA1_7_CURR_X_COUNT,val)
-#define bfin_read_DMA1_7_CURR_Y_COUNT() bfin_read16(DMA1_7_CURR_Y_COUNT)
-#define bfin_write_DMA1_7_CURR_Y_COUNT(val) bfin_write16(DMA1_7_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_7_IRQ_STATUS() bfin_read16(DMA1_7_IRQ_STATUS)
-#define bfin_write_DMA1_7_IRQ_STATUS(val) bfin_write16(DMA1_7_IRQ_STATUS,val)
-#define bfin_read_DMA1_7_PERIPHERAL_MAP() bfin_read16(DMA1_7_PERIPHERAL_MAP)
-#define bfin_write_DMA1_7_PERIPHERAL_MAP(val) bfin_write16(DMA1_7_PERIPHERAL_MAP,val)
-#define bfin_read_DMA1_8_CONFIG() bfin_read16(DMA1_8_CONFIG)
-#define bfin_write_DMA1_8_CONFIG(val) bfin_write16(DMA1_8_CONFIG,val)
-#define bfin_read_DMA1_8_NEXT_DESC_PTR() bfin_read32(DMA1_8_NEXT_DESC_PTR)
-#define bfin_write_DMA1_8_NEXT_DESC_PTR(val) bfin_write32(DMA1_8_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_8_START_ADDR() bfin_read32(DMA1_8_START_ADDR)
-#define bfin_write_DMA1_8_START_ADDR(val) bfin_write32(DMA1_8_START_ADDR,val)
-#define bfin_read_DMA1_8_X_COUNT() bfin_read16(DMA1_8_X_COUNT)
-#define bfin_write_DMA1_8_X_COUNT(val) bfin_write16(DMA1_8_X_COUNT,val)
-#define bfin_read_DMA1_8_Y_COUNT() bfin_read16(DMA1_8_Y_COUNT)
-#define bfin_write_DMA1_8_Y_COUNT(val) bfin_write16(DMA1_8_Y_COUNT,val)
-#define bfin_read_DMA1_8_X_MODIFY() bfin_read16(DMA1_8_X_MODIFY)
-#define bfin_write_DMA1_8_X_MODIFY(val) bfin_write16(DMA1_8_X_MODIFY,val)
-#define bfin_read_DMA1_8_Y_MODIFY() bfin_read16(DMA1_8_Y_MODIFY)
-#define bfin_write_DMA1_8_Y_MODIFY(val) bfin_write16(DMA1_8_Y_MODIFY,val)
-#define bfin_read_DMA1_8_CURR_DESC_PTR() bfin_read32(DMA1_8_CURR_DESC_PTR)
-#define bfin_write_DMA1_8_CURR_DESC_PTR(val) bfin_write32(DMA1_8_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_8_CURR_ADDR() bfin_read32(DMA1_8_CURR_ADDR)
-#define bfin_write_DMA1_8_CURR_ADDR(val) bfin_write32(DMA1_8_CURR_ADDR,val)
-#define bfin_read_DMA1_8_CURR_X_COUNT() bfin_read16(DMA1_8_CURR_X_COUNT)
-#define bfin_write_DMA1_8_CURR_X_COUNT(val) bfin_write16(DMA1_8_CURR_X_COUNT,val)
-#define bfin_read_DMA1_8_CURR_Y_COUNT() bfin_read16(DMA1_8_CURR_Y_COUNT)
-#define bfin_write_DMA1_8_CURR_Y_COUNT(val) bfin_write16(DMA1_8_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_8_IRQ_STATUS() bfin_read16(DMA1_8_IRQ_STATUS)
-#define bfin_write_DMA1_8_IRQ_STATUS(val) bfin_write16(DMA1_8_IRQ_STATUS,val)
-#define bfin_read_DMA1_8_PERIPHERAL_MAP() bfin_read16(DMA1_8_PERIPHERAL_MAP)
-#define bfin_write_DMA1_8_PERIPHERAL_MAP(val) bfin_write16(DMA1_8_PERIPHERAL_MAP,val)
-#define bfin_read_DMA1_9_CONFIG() bfin_read16(DMA1_9_CONFIG)
-#define bfin_write_DMA1_9_CONFIG(val) bfin_write16(DMA1_9_CONFIG,val)
-#define bfin_read_DMA1_9_NEXT_DESC_PTR() bfin_read32(DMA1_9_NEXT_DESC_PTR)
-#define bfin_write_DMA1_9_NEXT_DESC_PTR(val) bfin_write32(DMA1_9_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_9_START_ADDR() bfin_read32(DMA1_9_START_ADDR)
-#define bfin_write_DMA1_9_START_ADDR(val) bfin_write32(DMA1_9_START_ADDR,val)
-#define bfin_read_DMA1_9_X_COUNT() bfin_read16(DMA1_9_X_COUNT)
-#define bfin_write_DMA1_9_X_COUNT(val) bfin_write16(DMA1_9_X_COUNT,val)
-#define bfin_read_DMA1_9_Y_COUNT() bfin_read16(DMA1_9_Y_COUNT)
-#define bfin_write_DMA1_9_Y_COUNT(val) bfin_write16(DMA1_9_Y_COUNT,val)
-#define bfin_read_DMA1_9_X_MODIFY() bfin_read16(DMA1_9_X_MODIFY)
-#define bfin_write_DMA1_9_X_MODIFY(val) bfin_write16(DMA1_9_X_MODIFY,val)
-#define bfin_read_DMA1_9_Y_MODIFY() bfin_read16(DMA1_9_Y_MODIFY)
-#define bfin_write_DMA1_9_Y_MODIFY(val) bfin_write16(DMA1_9_Y_MODIFY,val)
-#define bfin_read_DMA1_9_CURR_DESC_PTR() bfin_read32(DMA1_9_CURR_DESC_PTR)
-#define bfin_write_DMA1_9_CURR_DESC_PTR(val) bfin_write32(DMA1_9_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_9_CURR_ADDR() bfin_read32(DMA1_9_CURR_ADDR)
-#define bfin_write_DMA1_9_CURR_ADDR(val) bfin_write32(DMA1_9_CURR_ADDR,val)
-#define bfin_read_DMA1_9_CURR_X_COUNT() bfin_read16(DMA1_9_CURR_X_COUNT)
-#define bfin_write_DMA1_9_CURR_X_COUNT(val) bfin_write16(DMA1_9_CURR_X_COUNT,val)
-#define bfin_read_DMA1_9_CURR_Y_COUNT() bfin_read16(DMA1_9_CURR_Y_COUNT)
-#define bfin_write_DMA1_9_CURR_Y_COUNT(val) bfin_write16(DMA1_9_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_9_IRQ_STATUS() bfin_read16(DMA1_9_IRQ_STATUS)
-#define bfin_write_DMA1_9_IRQ_STATUS(val) bfin_write16(DMA1_9_IRQ_STATUS,val)
-#define bfin_read_DMA1_9_PERIPHERAL_MAP() bfin_read16(DMA1_9_PERIPHERAL_MAP)
-#define bfin_write_DMA1_9_PERIPHERAL_MAP(val) bfin_write16(DMA1_9_PERIPHERAL_MAP,val)
-#define bfin_read_DMA1_10_CONFIG() bfin_read16(DMA1_10_CONFIG)
-#define bfin_write_DMA1_10_CONFIG(val) bfin_write16(DMA1_10_CONFIG,val)
-#define bfin_read_DMA1_10_NEXT_DESC_PTR() bfin_read32(DMA1_10_NEXT_DESC_PTR)
-#define bfin_write_DMA1_10_NEXT_DESC_PTR(val) bfin_write32(DMA1_10_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_10_START_ADDR() bfin_read32(DMA1_10_START_ADDR)
-#define bfin_write_DMA1_10_START_ADDR(val) bfin_write32(DMA1_10_START_ADDR,val)
-#define bfin_read_DMA1_10_X_COUNT() bfin_read16(DMA1_10_X_COUNT)
-#define bfin_write_DMA1_10_X_COUNT(val) bfin_write16(DMA1_10_X_COUNT,val)
-#define bfin_read_DMA1_10_Y_COUNT() bfin_read16(DMA1_10_Y_COUNT)
-#define bfin_write_DMA1_10_Y_COUNT(val) bfin_write16(DMA1_10_Y_COUNT,val)
-#define bfin_read_DMA1_10_X_MODIFY() bfin_read16(DMA1_10_X_MODIFY)
-#define bfin_write_DMA1_10_X_MODIFY(val) bfin_write16(DMA1_10_X_MODIFY,val)
-#define bfin_read_DMA1_10_Y_MODIFY() bfin_read16(DMA1_10_Y_MODIFY)
-#define bfin_write_DMA1_10_Y_MODIFY(val) bfin_write16(DMA1_10_Y_MODIFY,val)
-#define bfin_read_DMA1_10_CURR_DESC_PTR() bfin_read32(DMA1_10_CURR_DESC_PTR)
-#define bfin_write_DMA1_10_CURR_DESC_PTR(val) bfin_write32(DMA1_10_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_10_CURR_ADDR() bfin_read32(DMA1_10_CURR_ADDR)
-#define bfin_write_DMA1_10_CURR_ADDR(val) bfin_write32(DMA1_10_CURR_ADDR,val)
-#define bfin_read_DMA1_10_CURR_X_COUNT() bfin_read16(DMA1_10_CURR_X_COUNT)
-#define bfin_write_DMA1_10_CURR_X_COUNT(val) bfin_write16(DMA1_10_CURR_X_COUNT,val)
-#define bfin_read_DMA1_10_CURR_Y_COUNT() bfin_read16(DMA1_10_CURR_Y_COUNT)
-#define bfin_write_DMA1_10_CURR_Y_COUNT(val) bfin_write16(DMA1_10_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_10_IRQ_STATUS() bfin_read16(DMA1_10_IRQ_STATUS)
-#define bfin_write_DMA1_10_IRQ_STATUS(val) bfin_write16(DMA1_10_IRQ_STATUS,val)
-#define bfin_read_DMA1_10_PERIPHERAL_MAP() bfin_read16(DMA1_10_PERIPHERAL_MAP)
-#define bfin_write_DMA1_10_PERIPHERAL_MAP(val) bfin_write16(DMA1_10_PERIPHERAL_MAP,val)
-#define bfin_read_DMA1_11_CONFIG() bfin_read16(DMA1_11_CONFIG)
-#define bfin_write_DMA1_11_CONFIG(val) bfin_write16(DMA1_11_CONFIG,val)
-#define bfin_read_DMA1_11_NEXT_DESC_PTR() bfin_read32(DMA1_11_NEXT_DESC_PTR)
-#define bfin_write_DMA1_11_NEXT_DESC_PTR(val) bfin_write32(DMA1_11_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_11_START_ADDR() bfin_read32(DMA1_11_START_ADDR)
-#define bfin_write_DMA1_11_START_ADDR(val) bfin_write32(DMA1_11_START_ADDR,val)
-#define bfin_read_DMA1_11_X_COUNT() bfin_read16(DMA1_11_X_COUNT)
-#define bfin_write_DMA1_11_X_COUNT(val) bfin_write16(DMA1_11_X_COUNT,val)
-#define bfin_read_DMA1_11_Y_COUNT() bfin_read16(DMA1_11_Y_COUNT)
-#define bfin_write_DMA1_11_Y_COUNT(val) bfin_write16(DMA1_11_Y_COUNT,val)
-#define bfin_read_DMA1_11_X_MODIFY() bfin_read16(DMA1_11_X_MODIFY)
-#define bfin_write_DMA1_11_X_MODIFY(val) bfin_write16(DMA1_11_X_MODIFY,val)
-#define bfin_read_DMA1_11_Y_MODIFY() bfin_read16(DMA1_11_Y_MODIFY)
-#define bfin_write_DMA1_11_Y_MODIFY(val) bfin_write16(DMA1_11_Y_MODIFY,val)
-#define bfin_read_DMA1_11_CURR_DESC_PTR() bfin_read32(DMA1_11_CURR_DESC_PTR)
-#define bfin_write_DMA1_11_CURR_DESC_PTR(val) bfin_write32(DMA1_11_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_11_CURR_ADDR() bfin_read32(DMA1_11_CURR_ADDR)
-#define bfin_write_DMA1_11_CURR_ADDR(val) bfin_write32(DMA1_11_CURR_ADDR,val)
-#define bfin_read_DMA1_11_CURR_X_COUNT() bfin_read16(DMA1_11_CURR_X_COUNT)
-#define bfin_write_DMA1_11_CURR_X_COUNT(val) bfin_write16(DMA1_11_CURR_X_COUNT,val)
-#define bfin_read_DMA1_11_CURR_Y_COUNT() bfin_read16(DMA1_11_CURR_Y_COUNT)
-#define bfin_write_DMA1_11_CURR_Y_COUNT(val) bfin_write16(DMA1_11_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_11_IRQ_STATUS() bfin_read16(DMA1_11_IRQ_STATUS)
-#define bfin_write_DMA1_11_IRQ_STATUS(val) bfin_write16(DMA1_11_IRQ_STATUS,val)
-#define bfin_read_DMA1_11_PERIPHERAL_MAP() bfin_read16(DMA1_11_PERIPHERAL_MAP)
-#define bfin_write_DMA1_11_PERIPHERAL_MAP(val) bfin_write16(DMA1_11_PERIPHERAL_MAP,val)
-/* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) */
-#define bfin_read_MDMA_D2_CONFIG() bfin_read16(MDMA_D2_CONFIG)
-#define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG,val)
-#define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_read32(MDMA_D2_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_write32(MDMA_D2_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_D2_START_ADDR() bfin_read32(MDMA_D2_START_ADDR)
-#define bfin_write_MDMA_D2_START_ADDR(val) bfin_write32(MDMA_D2_START_ADDR,val)
-#define bfin_read_MDMA_D2_X_COUNT() bfin_read16(MDMA_D2_X_COUNT)
-#define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT,val)
-#define bfin_read_MDMA_D2_Y_COUNT() bfin_read16(MDMA_D2_Y_COUNT)
-#define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT,val)
-#define bfin_read_MDMA_D2_X_MODIFY() bfin_read16(MDMA_D2_X_MODIFY)
-#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY,val)
-#define bfin_read_MDMA_D2_Y_MODIFY() bfin_read16(MDMA_D2_Y_MODIFY)
-#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY,val)
-#define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_read32(MDMA_D2_CURR_DESC_PTR)
-#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_write32(MDMA_D2_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_D2_CURR_ADDR() bfin_read32(MDMA_D2_CURR_ADDR)
-#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_write32(MDMA_D2_CURR_ADDR,val)
-#define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT)
-#define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT,val)
-#define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT)
-#define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS)
-#define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS,val)
-#define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP,val)
-#define bfin_read_MDMA_S2_CONFIG() bfin_read16(MDMA_S2_CONFIG)
-#define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG,val)
-#define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_read32(MDMA_S2_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_write32(MDMA_S2_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_S2_START_ADDR() bfin_read32(MDMA_S2_START_ADDR)
-#define bfin_write_MDMA_S2_START_ADDR(val) bfin_write32(MDMA_S2_START_ADDR,val)
-#define bfin_read_MDMA_S2_X_COUNT() bfin_read16(MDMA_S2_X_COUNT)
-#define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT,val)
-#define bfin_read_MDMA_S2_Y_COUNT() bfin_read16(MDMA_S2_Y_COUNT)
-#define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT,val)
-#define bfin_read_MDMA_S2_X_MODIFY() bfin_read16(MDMA_S2_X_MODIFY)
-#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY,val)
-#define bfin_read_MDMA_S2_Y_MODIFY() bfin_read16(MDMA_S2_Y_MODIFY)
-#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY,val)
-#define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_read32(MDMA_S2_CURR_DESC_PTR)
-#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_write32(MDMA_S2_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_S2_CURR_ADDR() bfin_read32(MDMA_S2_CURR_ADDR)
-#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_write32(MDMA_S2_CURR_ADDR,val)
-#define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT)
-#define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT,val)
-#define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT)
-#define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS)
-#define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS,val)
-#define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP,val)
-#define bfin_read_MDMA_D3_CONFIG() bfin_read16(MDMA_D3_CONFIG)
-#define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG,val)
-#define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_read32(MDMA_D3_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_write32(MDMA_D3_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_D3_START_ADDR() bfin_read32(MDMA_D3_START_ADDR)
-#define bfin_write_MDMA_D3_START_ADDR(val) bfin_write32(MDMA_D3_START_ADDR,val)
-#define bfin_read_MDMA_D3_X_COUNT() bfin_read16(MDMA_D3_X_COUNT)
-#define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT,val)
-#define bfin_read_MDMA_D3_Y_COUNT() bfin_read16(MDMA_D3_Y_COUNT)
-#define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT,val)
-#define bfin_read_MDMA_D3_X_MODIFY() bfin_read16(MDMA_D3_X_MODIFY)
-#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY,val)
-#define bfin_read_MDMA_D3_Y_MODIFY() bfin_read16(MDMA_D3_Y_MODIFY)
-#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY,val)
-#define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_read32(MDMA_D3_CURR_DESC_PTR)
-#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_write32(MDMA_D3_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_D3_CURR_ADDR() bfin_read32(MDMA_D3_CURR_ADDR)
-#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_write32(MDMA_D3_CURR_ADDR,val)
-#define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT)
-#define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT,val)
-#define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT)
-#define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS)
-#define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS,val)
-#define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP,val)
-#define bfin_read_MDMA_S3_CONFIG() bfin_read16(MDMA_S3_CONFIG)
-#define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG,val)
-#define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_read32(MDMA_S3_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_write32(MDMA_S3_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_S3_START_ADDR() bfin_read32(MDMA_S3_START_ADDR)
-#define bfin_write_MDMA_S3_START_ADDR(val) bfin_write32(MDMA_S3_START_ADDR,val)
-#define bfin_read_MDMA_S3_X_COUNT() bfin_read16(MDMA_S3_X_COUNT)
-#define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT,val)
-#define bfin_read_MDMA_S3_Y_COUNT() bfin_read16(MDMA_S3_Y_COUNT)
-#define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT,val)
-#define bfin_read_MDMA_S3_X_MODIFY() bfin_read16(MDMA_S3_X_MODIFY)
-#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY,val)
-#define bfin_read_MDMA_S3_Y_MODIFY() bfin_read16(MDMA_S3_Y_MODIFY)
-#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY,val)
-#define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_read32(MDMA_S3_CURR_DESC_PTR)
-#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_write32(MDMA_S3_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_S3_CURR_ADDR() bfin_read32(MDMA_S3_CURR_ADDR)
-#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_write32(MDMA_S3_CURR_ADDR,val)
-#define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT)
-#define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT,val)
-#define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT)
-#define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS)
-#define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS,val)
-#define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP,val)
-/* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */
-#define bfin_read_DMA2_0_CONFIG() bfin_read16(DMA2_0_CONFIG)
-#define bfin_write_DMA2_0_CONFIG(val) bfin_write16(DMA2_0_CONFIG,val)
-#define bfin_read_DMA2_0_NEXT_DESC_PTR() bfin_read32(DMA2_0_NEXT_DESC_PTR)
-#define bfin_write_DMA2_0_NEXT_DESC_PTR(val) bfin_write32(DMA2_0_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_0_START_ADDR() bfin_read32(DMA2_0_START_ADDR)
-#define bfin_write_DMA2_0_START_ADDR(val) bfin_write32(DMA2_0_START_ADDR,val)
-#define bfin_read_DMA2_0_X_COUNT() bfin_read16(DMA2_0_X_COUNT)
-#define bfin_write_DMA2_0_X_COUNT(val) bfin_write16(DMA2_0_X_COUNT,val)
-#define bfin_read_DMA2_0_Y_COUNT() bfin_read16(DMA2_0_Y_COUNT)
-#define bfin_write_DMA2_0_Y_COUNT(val) bfin_write16(DMA2_0_Y_COUNT,val)
-#define bfin_read_DMA2_0_X_MODIFY() bfin_read16(DMA2_0_X_MODIFY)
-#define bfin_write_DMA2_0_X_MODIFY(val) bfin_write16(DMA2_0_X_MODIFY,val)
-#define bfin_read_DMA2_0_Y_MODIFY() bfin_read16(DMA2_0_Y_MODIFY)
-#define bfin_write_DMA2_0_Y_MODIFY(val) bfin_write16(DMA2_0_Y_MODIFY,val)
-#define bfin_read_DMA2_0_CURR_DESC_PTR() bfin_read32(DMA2_0_CURR_DESC_PTR)
-#define bfin_write_DMA2_0_CURR_DESC_PTR(val) bfin_write32(DMA2_0_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_0_CURR_ADDR() bfin_read32(DMA2_0_CURR_ADDR)
-#define bfin_write_DMA2_0_CURR_ADDR(val) bfin_write32(DMA2_0_CURR_ADDR,val)
-#define bfin_read_DMA2_0_CURR_X_COUNT() bfin_read16(DMA2_0_CURR_X_COUNT)
-#define bfin_write_DMA2_0_CURR_X_COUNT(val) bfin_write16(DMA2_0_CURR_X_COUNT,val)
-#define bfin_read_DMA2_0_CURR_Y_COUNT() bfin_read16(DMA2_0_CURR_Y_COUNT)
-#define bfin_write_DMA2_0_CURR_Y_COUNT(val) bfin_write16(DMA2_0_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_0_IRQ_STATUS() bfin_read16(DMA2_0_IRQ_STATUS)
-#define bfin_write_DMA2_0_IRQ_STATUS(val) bfin_write16(DMA2_0_IRQ_STATUS,val)
-#define bfin_read_DMA2_0_PERIPHERAL_MAP() bfin_read16(DMA2_0_PERIPHERAL_MAP)
-#define bfin_write_DMA2_0_PERIPHERAL_MAP(val) bfin_write16(DMA2_0_PERIPHERAL_MAP,val)
-#define bfin_read_DMA2_1_CONFIG() bfin_read16(DMA2_1_CONFIG)
-#define bfin_write_DMA2_1_CONFIG(val) bfin_write16(DMA2_1_CONFIG,val)
-#define bfin_read_DMA2_1_NEXT_DESC_PTR() bfin_read32(DMA2_1_NEXT_DESC_PTR)
-#define bfin_write_DMA2_1_NEXT_DESC_PTR(val) bfin_write32(DMA2_1_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_1_START_ADDR() bfin_read32(DMA2_1_START_ADDR)
-#define bfin_write_DMA2_1_START_ADDR(val) bfin_write32(DMA2_1_START_ADDR,val)
-#define bfin_read_DMA2_1_X_COUNT() bfin_read16(DMA2_1_X_COUNT)
-#define bfin_write_DMA2_1_X_COUNT(val) bfin_write16(DMA2_1_X_COUNT,val)
-#define bfin_read_DMA2_1_Y_COUNT() bfin_read16(DMA2_1_Y_COUNT)
-#define bfin_write_DMA2_1_Y_COUNT(val) bfin_write16(DMA2_1_Y_COUNT,val)
-#define bfin_read_DMA2_1_X_MODIFY() bfin_read16(DMA2_1_X_MODIFY)
-#define bfin_write_DMA2_1_X_MODIFY(val) bfin_write16(DMA2_1_X_MODIFY,val)
-#define bfin_read_DMA2_1_Y_MODIFY() bfin_read16(DMA2_1_Y_MODIFY)
-#define bfin_write_DMA2_1_Y_MODIFY(val) bfin_write16(DMA2_1_Y_MODIFY,val)
-#define bfin_read_DMA2_1_CURR_DESC_PTR() bfin_read32(DMA2_1_CURR_DESC_PTR)
-#define bfin_write_DMA2_1_CURR_DESC_PTR(val) bfin_write32(DMA2_1_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_1_CURR_ADDR() bfin_read32(DMA2_1_CURR_ADDR)
-#define bfin_write_DMA2_1_CURR_ADDR(val) bfin_write32(DMA2_1_CURR_ADDR,val)
-#define bfin_read_DMA2_1_CURR_X_COUNT() bfin_read16(DMA2_1_CURR_X_COUNT)
-#define bfin_write_DMA2_1_CURR_X_COUNT(val) bfin_write16(DMA2_1_CURR_X_COUNT,val)
-#define bfin_read_DMA2_1_CURR_Y_COUNT() bfin_read16(DMA2_1_CURR_Y_COUNT)
-#define bfin_write_DMA2_1_CURR_Y_COUNT(val) bfin_write16(DMA2_1_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_1_IRQ_STATUS() bfin_read16(DMA2_1_IRQ_STATUS)
-#define bfin_write_DMA2_1_IRQ_STATUS(val) bfin_write16(DMA2_1_IRQ_STATUS,val)
-#define bfin_read_DMA2_1_PERIPHERAL_MAP() bfin_read16(DMA2_1_PERIPHERAL_MAP)
-#define bfin_write_DMA2_1_PERIPHERAL_MAP(val) bfin_write16(DMA2_1_PERIPHERAL_MAP,val)
-#define bfin_read_DMA2_2_CONFIG() bfin_read16(DMA2_2_CONFIG)
-#define bfin_write_DMA2_2_CONFIG(val) bfin_write16(DMA2_2_CONFIG,val)
-#define bfin_read_DMA2_2_NEXT_DESC_PTR() bfin_read32(DMA2_2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_2_NEXT_DESC_PTR(val) bfin_write32(DMA2_2_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_2_START_ADDR() bfin_read32(DMA2_2_START_ADDR)
-#define bfin_write_DMA2_2_START_ADDR(val) bfin_write32(DMA2_2_START_ADDR,val)
-#define bfin_read_DMA2_2_X_COUNT() bfin_read16(DMA2_2_X_COUNT)
-#define bfin_write_DMA2_2_X_COUNT(val) bfin_write16(DMA2_2_X_COUNT,val)
-#define bfin_read_DMA2_2_Y_COUNT() bfin_read16(DMA2_2_Y_COUNT)
-#define bfin_write_DMA2_2_Y_COUNT(val) bfin_write16(DMA2_2_Y_COUNT,val)
-#define bfin_read_DMA2_2_X_MODIFY() bfin_read16(DMA2_2_X_MODIFY)
-#define bfin_write_DMA2_2_X_MODIFY(val) bfin_write16(DMA2_2_X_MODIFY,val)
-#define bfin_read_DMA2_2_Y_MODIFY() bfin_read16(DMA2_2_Y_MODIFY)
-#define bfin_write_DMA2_2_Y_MODIFY(val) bfin_write16(DMA2_2_Y_MODIFY,val)
-#define bfin_read_DMA2_2_CURR_DESC_PTR() bfin_read32(DMA2_2_CURR_DESC_PTR)
-#define bfin_write_DMA2_2_CURR_DESC_PTR(val) bfin_write32(DMA2_2_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_2_CURR_ADDR() bfin_read32(DMA2_2_CURR_ADDR)
-#define bfin_write_DMA2_2_CURR_ADDR(val) bfin_write32(DMA2_2_CURR_ADDR,val)
-#define bfin_read_DMA2_2_CURR_X_COUNT() bfin_read16(DMA2_2_CURR_X_COUNT)
-#define bfin_write_DMA2_2_CURR_X_COUNT(val) bfin_write16(DMA2_2_CURR_X_COUNT,val)
-#define bfin_read_DMA2_2_CURR_Y_COUNT() bfin_read16(DMA2_2_CURR_Y_COUNT)
-#define bfin_write_DMA2_2_CURR_Y_COUNT(val) bfin_write16(DMA2_2_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_2_IRQ_STATUS() bfin_read16(DMA2_2_IRQ_STATUS)
-#define bfin_write_DMA2_2_IRQ_STATUS(val) bfin_write16(DMA2_2_IRQ_STATUS,val)
-#define bfin_read_DMA2_2_PERIPHERAL_MAP() bfin_read16(DMA2_2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_2_PERIPHERAL_MAP(val) bfin_write16(DMA2_2_PERIPHERAL_MAP,val)
-#define bfin_read_DMA2_3_CONFIG() bfin_read16(DMA2_3_CONFIG)
-#define bfin_write_DMA2_3_CONFIG(val) bfin_write16(DMA2_3_CONFIG,val)
-#define bfin_read_DMA2_3_NEXT_DESC_PTR() bfin_read32(DMA2_3_NEXT_DESC_PTR)
-#define bfin_write_DMA2_3_NEXT_DESC_PTR(val) bfin_write32(DMA2_3_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_3_START_ADDR() bfin_read32(DMA2_3_START_ADDR)
-#define bfin_write_DMA2_3_START_ADDR(val) bfin_write32(DMA2_3_START_ADDR,val)
-#define bfin_read_DMA2_3_X_COUNT() bfin_read16(DMA2_3_X_COUNT)
-#define bfin_write_DMA2_3_X_COUNT(val) bfin_write16(DMA2_3_X_COUNT,val)
-#define bfin_read_DMA2_3_Y_COUNT() bfin_read16(DMA2_3_Y_COUNT)
-#define bfin_write_DMA2_3_Y_COUNT(val) bfin_write16(DMA2_3_Y_COUNT,val)
-#define bfin_read_DMA2_3_X_MODIFY() bfin_read16(DMA2_3_X_MODIFY)
-#define bfin_write_DMA2_3_X_MODIFY(val) bfin_write16(DMA2_3_X_MODIFY,val)
-#define bfin_read_DMA2_3_Y_MODIFY() bfin_read16(DMA2_3_Y_MODIFY)
-#define bfin_write_DMA2_3_Y_MODIFY(val) bfin_write16(DMA2_3_Y_MODIFY,val)
-#define bfin_read_DMA2_3_CURR_DESC_PTR() bfin_read32(DMA2_3_CURR_DESC_PTR)
-#define bfin_write_DMA2_3_CURR_DESC_PTR(val) bfin_write32(DMA2_3_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_3_CURR_ADDR() bfin_read32(DMA2_3_CURR_ADDR)
-#define bfin_write_DMA2_3_CURR_ADDR(val) bfin_write32(DMA2_3_CURR_ADDR,val)
-#define bfin_read_DMA2_3_CURR_X_COUNT() bfin_read16(DMA2_3_CURR_X_COUNT)
-#define bfin_write_DMA2_3_CURR_X_COUNT(val) bfin_write16(DMA2_3_CURR_X_COUNT,val)
-#define bfin_read_DMA2_3_CURR_Y_COUNT() bfin_read16(DMA2_3_CURR_Y_COUNT)
-#define bfin_write_DMA2_3_CURR_Y_COUNT(val) bfin_write16(DMA2_3_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_3_IRQ_STATUS() bfin_read16(DMA2_3_IRQ_STATUS)
-#define bfin_write_DMA2_3_IRQ_STATUS(val) bfin_write16(DMA2_3_IRQ_STATUS,val)
-#define bfin_read_DMA2_3_PERIPHERAL_MAP() bfin_read16(DMA2_3_PERIPHERAL_MAP)
-#define bfin_write_DMA2_3_PERIPHERAL_MAP(val) bfin_write16(DMA2_3_PERIPHERAL_MAP,val)
-#define bfin_read_DMA2_4_CONFIG() bfin_read16(DMA2_4_CONFIG)
-#define bfin_write_DMA2_4_CONFIG(val) bfin_write16(DMA2_4_CONFIG,val)
-#define bfin_read_DMA2_4_NEXT_DESC_PTR() bfin_read32(DMA2_4_NEXT_DESC_PTR)
-#define bfin_write_DMA2_4_NEXT_DESC_PTR(val) bfin_write32(DMA2_4_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_4_START_ADDR() bfin_read32(DMA2_4_START_ADDR)
-#define bfin_write_DMA2_4_START_ADDR(val) bfin_write32(DMA2_4_START_ADDR,val)
-#define bfin_read_DMA2_4_X_COUNT() bfin_read16(DMA2_4_X_COUNT)
-#define bfin_write_DMA2_4_X_COUNT(val) bfin_write16(DMA2_4_X_COUNT,val)
-#define bfin_read_DMA2_4_Y_COUNT() bfin_read16(DMA2_4_Y_COUNT)
-#define bfin_write_DMA2_4_Y_COUNT(val) bfin_write16(DMA2_4_Y_COUNT,val)
-#define bfin_read_DMA2_4_X_MODIFY() bfin_read16(DMA2_4_X_MODIFY)
-#define bfin_write_DMA2_4_X_MODIFY(val) bfin_write16(DMA2_4_X_MODIFY,val)
-#define bfin_read_DMA2_4_Y_MODIFY() bfin_read16(DMA2_4_Y_MODIFY)
-#define bfin_write_DMA2_4_Y_MODIFY(val) bfin_write16(DMA2_4_Y_MODIFY,val)
-#define bfin_read_DMA2_4_CURR_DESC_PTR() bfin_read32(DMA2_4_CURR_DESC_PTR)
-#define bfin_write_DMA2_4_CURR_DESC_PTR(val) bfin_write32(DMA2_4_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_4_CURR_ADDR() bfin_read32(DMA2_4_CURR_ADDR)
-#define bfin_write_DMA2_4_CURR_ADDR(val) bfin_write32(DMA2_4_CURR_ADDR,val)
-#define bfin_read_DMA2_4_CURR_X_COUNT() bfin_read16(DMA2_4_CURR_X_COUNT)
-#define bfin_write_DMA2_4_CURR_X_COUNT(val) bfin_write16(DMA2_4_CURR_X_COUNT,val)
-#define bfin_read_DMA2_4_CURR_Y_COUNT() bfin_read16(DMA2_4_CURR_Y_COUNT)
-#define bfin_write_DMA2_4_CURR_Y_COUNT(val) bfin_write16(DMA2_4_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_4_IRQ_STATUS() bfin_read16(DMA2_4_IRQ_STATUS)
-#define bfin_write_DMA2_4_IRQ_STATUS(val) bfin_write16(DMA2_4_IRQ_STATUS,val)
-#define bfin_read_DMA2_4_PERIPHERAL_MAP() bfin_read16(DMA2_4_PERIPHERAL_MAP)
-#define bfin_write_DMA2_4_PERIPHERAL_MAP(val) bfin_write16(DMA2_4_PERIPHERAL_MAP,val)
-#define bfin_read_DMA2_5_CONFIG() bfin_read16(DMA2_5_CONFIG)
-#define bfin_write_DMA2_5_CONFIG(val) bfin_write16(DMA2_5_CONFIG,val)
-#define bfin_read_DMA2_5_NEXT_DESC_PTR() bfin_read32(DMA2_5_NEXT_DESC_PTR)
-#define bfin_write_DMA2_5_NEXT_DESC_PTR(val) bfin_write32(DMA2_5_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_5_START_ADDR() bfin_read32(DMA2_5_START_ADDR)
-#define bfin_write_DMA2_5_START_ADDR(val) bfin_write32(DMA2_5_START_ADDR,val)
-#define bfin_read_DMA2_5_X_COUNT() bfin_read16(DMA2_5_X_COUNT)
-#define bfin_write_DMA2_5_X_COUNT(val) bfin_write16(DMA2_5_X_COUNT,val)
-#define bfin_read_DMA2_5_Y_COUNT() bfin_read16(DMA2_5_Y_COUNT)
-#define bfin_write_DMA2_5_Y_COUNT(val) bfin_write16(DMA2_5_Y_COUNT,val)
-#define bfin_read_DMA2_5_X_MODIFY() bfin_read16(DMA2_5_X_MODIFY)
-#define bfin_write_DMA2_5_X_MODIFY(val) bfin_write16(DMA2_5_X_MODIFY,val)
-#define bfin_read_DMA2_5_Y_MODIFY() bfin_read16(DMA2_5_Y_MODIFY)
-#define bfin_write_DMA2_5_Y_MODIFY(val) bfin_write16(DMA2_5_Y_MODIFY,val)
-#define bfin_read_DMA2_5_CURR_DESC_PTR() bfin_read32(DMA2_5_CURR_DESC_PTR)
-#define bfin_write_DMA2_5_CURR_DESC_PTR(val) bfin_write32(DMA2_5_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_5_CURR_ADDR() bfin_read32(DMA2_5_CURR_ADDR)
-#define bfin_write_DMA2_5_CURR_ADDR(val) bfin_write32(DMA2_5_CURR_ADDR,val)
-#define bfin_read_DMA2_5_CURR_X_COUNT() bfin_read16(DMA2_5_CURR_X_COUNT)
-#define bfin_write_DMA2_5_CURR_X_COUNT(val) bfin_write16(DMA2_5_CURR_X_COUNT,val)
-#define bfin_read_DMA2_5_CURR_Y_COUNT() bfin_read16(DMA2_5_CURR_Y_COUNT)
-#define bfin_write_DMA2_5_CURR_Y_COUNT(val) bfin_write16(DMA2_5_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_5_IRQ_STATUS() bfin_read16(DMA2_5_IRQ_STATUS)
-#define bfin_write_DMA2_5_IRQ_STATUS(val) bfin_write16(DMA2_5_IRQ_STATUS,val)
-#define bfin_read_DMA2_5_PERIPHERAL_MAP() bfin_read16(DMA2_5_PERIPHERAL_MAP)
-#define bfin_write_DMA2_5_PERIPHERAL_MAP(val) bfin_write16(DMA2_5_PERIPHERAL_MAP,val)
-#define bfin_read_DMA2_6_CONFIG() bfin_read16(DMA2_6_CONFIG)
-#define bfin_write_DMA2_6_CONFIG(val) bfin_write16(DMA2_6_CONFIG,val)
-#define bfin_read_DMA2_6_NEXT_DESC_PTR() bfin_read32(DMA2_6_NEXT_DESC_PTR)
-#define bfin_write_DMA2_6_NEXT_DESC_PTR(val) bfin_write32(DMA2_6_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_6_START_ADDR() bfin_read32(DMA2_6_START_ADDR)
-#define bfin_write_DMA2_6_START_ADDR(val) bfin_write32(DMA2_6_START_ADDR,val)
-#define bfin_read_DMA2_6_X_COUNT() bfin_read16(DMA2_6_X_COUNT)
-#define bfin_write_DMA2_6_X_COUNT(val) bfin_write16(DMA2_6_X_COUNT,val)
-#define bfin_read_DMA2_6_Y_COUNT() bfin_read16(DMA2_6_Y_COUNT)
-#define bfin_write_DMA2_6_Y_COUNT(val) bfin_write16(DMA2_6_Y_COUNT,val)
-#define bfin_read_DMA2_6_X_MODIFY() bfin_read16(DMA2_6_X_MODIFY)
-#define bfin_write_DMA2_6_X_MODIFY(val) bfin_write16(DMA2_6_X_MODIFY,val)
-#define bfin_read_DMA2_6_Y_MODIFY() bfin_read16(DMA2_6_Y_MODIFY)
-#define bfin_write_DMA2_6_Y_MODIFY(val) bfin_write16(DMA2_6_Y_MODIFY,val)
-#define bfin_read_DMA2_6_CURR_DESC_PTR() bfin_read32(DMA2_6_CURR_DESC_PTR)
-#define bfin_write_DMA2_6_CURR_DESC_PTR(val) bfin_write32(DMA2_6_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_6_CURR_ADDR() bfin_read32(DMA2_6_CURR_ADDR)
-#define bfin_write_DMA2_6_CURR_ADDR(val) bfin_write32(DMA2_6_CURR_ADDR,val)
-#define bfin_read_DMA2_6_CURR_X_COUNT() bfin_read16(DMA2_6_CURR_X_COUNT)
-#define bfin_write_DMA2_6_CURR_X_COUNT(val) bfin_write16(DMA2_6_CURR_X_COUNT,val)
-#define bfin_read_DMA2_6_CURR_Y_COUNT() bfin_read16(DMA2_6_CURR_Y_COUNT)
-#define bfin_write_DMA2_6_CURR_Y_COUNT(val) bfin_write16(DMA2_6_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_6_IRQ_STATUS() bfin_read16(DMA2_6_IRQ_STATUS)
-#define bfin_write_DMA2_6_IRQ_STATUS(val) bfin_write16(DMA2_6_IRQ_STATUS,val)
-#define bfin_read_DMA2_6_PERIPHERAL_MAP() bfin_read16(DMA2_6_PERIPHERAL_MAP)
-#define bfin_write_DMA2_6_PERIPHERAL_MAP(val) bfin_write16(DMA2_6_PERIPHERAL_MAP,val)
-#define bfin_read_DMA2_7_CONFIG() bfin_read16(DMA2_7_CONFIG)
-#define bfin_write_DMA2_7_CONFIG(val) bfin_write16(DMA2_7_CONFIG,val)
-#define bfin_read_DMA2_7_NEXT_DESC_PTR() bfin_read32(DMA2_7_NEXT_DESC_PTR)
-#define bfin_write_DMA2_7_NEXT_DESC_PTR(val) bfin_write32(DMA2_7_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_7_START_ADDR() bfin_read32(DMA2_7_START_ADDR)
-#define bfin_write_DMA2_7_START_ADDR(val) bfin_write32(DMA2_7_START_ADDR,val)
-#define bfin_read_DMA2_7_X_COUNT() bfin_read16(DMA2_7_X_COUNT)
-#define bfin_write_DMA2_7_X_COUNT(val) bfin_write16(DMA2_7_X_COUNT,val)
-#define bfin_read_DMA2_7_Y_COUNT() bfin_read16(DMA2_7_Y_COUNT)
-#define bfin_write_DMA2_7_Y_COUNT(val) bfin_write16(DMA2_7_Y_COUNT,val)
-#define bfin_read_DMA2_7_X_MODIFY() bfin_read16(DMA2_7_X_MODIFY)
-#define bfin_write_DMA2_7_X_MODIFY(val) bfin_write16(DMA2_7_X_MODIFY,val)
-#define bfin_read_DMA2_7_Y_MODIFY() bfin_read16(DMA2_7_Y_MODIFY)
-#define bfin_write_DMA2_7_Y_MODIFY(val) bfin_write16(DMA2_7_Y_MODIFY,val)
-#define bfin_read_DMA2_7_CURR_DESC_PTR() bfin_read32(DMA2_7_CURR_DESC_PTR)
-#define bfin_write_DMA2_7_CURR_DESC_PTR(val) bfin_write32(DMA2_7_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_7_CURR_ADDR() bfin_read32(DMA2_7_CURR_ADDR)
-#define bfin_write_DMA2_7_CURR_ADDR(val) bfin_write32(DMA2_7_CURR_ADDR,val)
-#define bfin_read_DMA2_7_CURR_X_COUNT() bfin_read16(DMA2_7_CURR_X_COUNT)
-#define bfin_write_DMA2_7_CURR_X_COUNT(val) bfin_write16(DMA2_7_CURR_X_COUNT,val)
-#define bfin_read_DMA2_7_CURR_Y_COUNT() bfin_read16(DMA2_7_CURR_Y_COUNT)
-#define bfin_write_DMA2_7_CURR_Y_COUNT(val) bfin_write16(DMA2_7_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_7_IRQ_STATUS() bfin_read16(DMA2_7_IRQ_STATUS)
-#define bfin_write_DMA2_7_IRQ_STATUS(val) bfin_write16(DMA2_7_IRQ_STATUS,val)
-#define bfin_read_DMA2_7_PERIPHERAL_MAP() bfin_read16(DMA2_7_PERIPHERAL_MAP)
-#define bfin_write_DMA2_7_PERIPHERAL_MAP(val) bfin_write16(DMA2_7_PERIPHERAL_MAP,val)
-#define bfin_read_DMA2_8_CONFIG() bfin_read16(DMA2_8_CONFIG)
-#define bfin_write_DMA2_8_CONFIG(val) bfin_write16(DMA2_8_CONFIG,val)
-#define bfin_read_DMA2_8_NEXT_DESC_PTR() bfin_read32(DMA2_8_NEXT_DESC_PTR)
-#define bfin_write_DMA2_8_NEXT_DESC_PTR(val) bfin_write32(DMA2_8_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_8_START_ADDR() bfin_read32(DMA2_8_START_ADDR)
-#define bfin_write_DMA2_8_START_ADDR(val) bfin_write32(DMA2_8_START_ADDR,val)
-#define bfin_read_DMA2_8_X_COUNT() bfin_read16(DMA2_8_X_COUNT)
-#define bfin_write_DMA2_8_X_COUNT(val) bfin_write16(DMA2_8_X_COUNT,val)
-#define bfin_read_DMA2_8_Y_COUNT() bfin_read16(DMA2_8_Y_COUNT)
-#define bfin_write_DMA2_8_Y_COUNT(val) bfin_write16(DMA2_8_Y_COUNT,val)
-#define bfin_read_DMA2_8_X_MODIFY() bfin_read16(DMA2_8_X_MODIFY)
-#define bfin_write_DMA2_8_X_MODIFY(val) bfin_write16(DMA2_8_X_MODIFY,val)
-#define bfin_read_DMA2_8_Y_MODIFY() bfin_read16(DMA2_8_Y_MODIFY)
-#define bfin_write_DMA2_8_Y_MODIFY(val) bfin_write16(DMA2_8_Y_MODIFY,val)
-#define bfin_read_DMA2_8_CURR_DESC_PTR() bfin_read32(DMA2_8_CURR_DESC_PTR)
-#define bfin_write_DMA2_8_CURR_DESC_PTR(val) bfin_write32(DMA2_8_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_8_CURR_ADDR() bfin_read32(DMA2_8_CURR_ADDR)
-#define bfin_write_DMA2_8_CURR_ADDR(val) bfin_write32(DMA2_8_CURR_ADDR,val)
-#define bfin_read_DMA2_8_CURR_X_COUNT() bfin_read16(DMA2_8_CURR_X_COUNT)
-#define bfin_write_DMA2_8_CURR_X_COUNT(val) bfin_write16(DMA2_8_CURR_X_COUNT,val)
-#define bfin_read_DMA2_8_CURR_Y_COUNT() bfin_read16(DMA2_8_CURR_Y_COUNT)
-#define bfin_write_DMA2_8_CURR_Y_COUNT(val) bfin_write16(DMA2_8_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_8_IRQ_STATUS() bfin_read16(DMA2_8_IRQ_STATUS)
-#define bfin_write_DMA2_8_IRQ_STATUS(val) bfin_write16(DMA2_8_IRQ_STATUS,val)
-#define bfin_read_DMA2_8_PERIPHERAL_MAP() bfin_read16(DMA2_8_PERIPHERAL_MAP)
-#define bfin_write_DMA2_8_PERIPHERAL_MAP(val) bfin_write16(DMA2_8_PERIPHERAL_MAP,val)
-#define bfin_read_DMA2_9_CONFIG() bfin_read16(DMA2_9_CONFIG)
-#define bfin_write_DMA2_9_CONFIG(val) bfin_write16(DMA2_9_CONFIG,val)
-#define bfin_read_DMA2_9_NEXT_DESC_PTR() bfin_read32(DMA2_9_NEXT_DESC_PTR)
-#define bfin_write_DMA2_9_NEXT_DESC_PTR(val) bfin_write32(DMA2_9_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_9_START_ADDR() bfin_read32(DMA2_9_START_ADDR)
-#define bfin_write_DMA2_9_START_ADDR(val) bfin_write32(DMA2_9_START_ADDR,val)
-#define bfin_read_DMA2_9_X_COUNT() bfin_read16(DMA2_9_X_COUNT)
-#define bfin_write_DMA2_9_X_COUNT(val) bfin_write16(DMA2_9_X_COUNT,val)
-#define bfin_read_DMA2_9_Y_COUNT() bfin_read16(DMA2_9_Y_COUNT)
-#define bfin_write_DMA2_9_Y_COUNT(val) bfin_write16(DMA2_9_Y_COUNT,val)
-#define bfin_read_DMA2_9_X_MODIFY() bfin_read16(DMA2_9_X_MODIFY)
-#define bfin_write_DMA2_9_X_MODIFY(val) bfin_write16(DMA2_9_X_MODIFY,val)
-#define bfin_read_DMA2_9_Y_MODIFY() bfin_read16(DMA2_9_Y_MODIFY)
-#define bfin_write_DMA2_9_Y_MODIFY(val) bfin_write16(DMA2_9_Y_MODIFY,val)
-#define bfin_read_DMA2_9_CURR_DESC_PTR() bfin_read32(DMA2_9_CURR_DESC_PTR)
-#define bfin_write_DMA2_9_CURR_DESC_PTR(val) bfin_write32(DMA2_9_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_9_CURR_ADDR() bfin_read32(DMA2_9_CURR_ADDR)
-#define bfin_write_DMA2_9_CURR_ADDR(val) bfin_write32(DMA2_9_CURR_ADDR,val)
-#define bfin_read_DMA2_9_CURR_X_COUNT() bfin_read16(DMA2_9_CURR_X_COUNT)
-#define bfin_write_DMA2_9_CURR_X_COUNT(val) bfin_write16(DMA2_9_CURR_X_COUNT,val)
-#define bfin_read_DMA2_9_CURR_Y_COUNT() bfin_read16(DMA2_9_CURR_Y_COUNT)
-#define bfin_write_DMA2_9_CURR_Y_COUNT(val) bfin_write16(DMA2_9_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_9_IRQ_STATUS() bfin_read16(DMA2_9_IRQ_STATUS)
-#define bfin_write_DMA2_9_IRQ_STATUS(val) bfin_write16(DMA2_9_IRQ_STATUS,val)
-#define bfin_read_DMA2_9_PERIPHERAL_MAP() bfin_read16(DMA2_9_PERIPHERAL_MAP)
-#define bfin_write_DMA2_9_PERIPHERAL_MAP(val) bfin_write16(DMA2_9_PERIPHERAL_MAP,val)
-#define bfin_read_DMA2_10_CONFIG() bfin_read16(DMA2_10_CONFIG)
-#define bfin_write_DMA2_10_CONFIG(val) bfin_write16(DMA2_10_CONFIG,val)
-#define bfin_read_DMA2_10_NEXT_DESC_PTR() bfin_read32(DMA2_10_NEXT_DESC_PTR)
-#define bfin_write_DMA2_10_NEXT_DESC_PTR(val) bfin_write32(DMA2_10_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_10_START_ADDR() bfin_read32(DMA2_10_START_ADDR)
-#define bfin_write_DMA2_10_START_ADDR(val) bfin_write32(DMA2_10_START_ADDR,val)
-#define bfin_read_DMA2_10_X_COUNT() bfin_read16(DMA2_10_X_COUNT)
-#define bfin_write_DMA2_10_X_COUNT(val) bfin_write16(DMA2_10_X_COUNT,val)
-#define bfin_read_DMA2_10_Y_COUNT() bfin_read16(DMA2_10_Y_COUNT)
-#define bfin_write_DMA2_10_Y_COUNT(val) bfin_write16(DMA2_10_Y_COUNT,val)
-#define bfin_read_DMA2_10_X_MODIFY() bfin_read16(DMA2_10_X_MODIFY)
-#define bfin_write_DMA2_10_X_MODIFY(val) bfin_write16(DMA2_10_X_MODIFY,val)
-#define bfin_read_DMA2_10_Y_MODIFY() bfin_read16(DMA2_10_Y_MODIFY)
-#define bfin_write_DMA2_10_Y_MODIFY(val) bfin_write16(DMA2_10_Y_MODIFY,val)
-#define bfin_read_DMA2_10_CURR_DESC_PTR() bfin_read32(DMA2_10_CURR_DESC_PTR)
-#define bfin_write_DMA2_10_CURR_DESC_PTR(val) bfin_write32(DMA2_10_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_10_CURR_ADDR() bfin_read32(DMA2_10_CURR_ADDR)
-#define bfin_write_DMA2_10_CURR_ADDR(val) bfin_write32(DMA2_10_CURR_ADDR,val)
-#define bfin_read_DMA2_10_CURR_X_COUNT() bfin_read16(DMA2_10_CURR_X_COUNT)
-#define bfin_write_DMA2_10_CURR_X_COUNT(val) bfin_write16(DMA2_10_CURR_X_COUNT,val)
-#define bfin_read_DMA2_10_CURR_Y_COUNT() bfin_read16(DMA2_10_CURR_Y_COUNT)
-#define bfin_write_DMA2_10_CURR_Y_COUNT(val) bfin_write16(DMA2_10_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_10_IRQ_STATUS() bfin_read16(DMA2_10_IRQ_STATUS)
-#define bfin_write_DMA2_10_IRQ_STATUS(val) bfin_write16(DMA2_10_IRQ_STATUS,val)
-#define bfin_read_DMA2_10_PERIPHERAL_MAP() bfin_read16(DMA2_10_PERIPHERAL_MAP)
-#define bfin_write_DMA2_10_PERIPHERAL_MAP(val) bfin_write16(DMA2_10_PERIPHERAL_MAP,val)
-#define bfin_read_DMA2_11_CONFIG() bfin_read16(DMA2_11_CONFIG)
-#define bfin_write_DMA2_11_CONFIG(val) bfin_write16(DMA2_11_CONFIG,val)
-#define bfin_read_DMA2_11_NEXT_DESC_PTR() bfin_read32(DMA2_11_NEXT_DESC_PTR)
-#define bfin_write_DMA2_11_NEXT_DESC_PTR(val) bfin_write32(DMA2_11_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_11_START_ADDR() bfin_read32(DMA2_11_START_ADDR)
-#define bfin_write_DMA2_11_START_ADDR(val) bfin_write32(DMA2_11_START_ADDR,val)
-#define bfin_read_DMA2_11_X_COUNT() bfin_read16(DMA2_11_X_COUNT)
-#define bfin_write_DMA2_11_X_COUNT(val) bfin_write16(DMA2_11_X_COUNT,val)
-#define bfin_read_DMA2_11_Y_COUNT() bfin_read16(DMA2_11_Y_COUNT)
-#define bfin_write_DMA2_11_Y_COUNT(val) bfin_write16(DMA2_11_Y_COUNT,val)
-#define bfin_read_DMA2_11_X_MODIFY() bfin_read16(DMA2_11_X_MODIFY)
-#define bfin_write_DMA2_11_X_MODIFY(val) bfin_write16(DMA2_11_X_MODIFY,val)
-#define bfin_read_DMA2_11_Y_MODIFY() bfin_read16(DMA2_11_Y_MODIFY)
-#define bfin_write_DMA2_11_Y_MODIFY(val) bfin_write16(DMA2_11_Y_MODIFY,val)
-#define bfin_read_DMA2_11_CURR_DESC_PTR() bfin_read32(DMA2_11_CURR_DESC_PTR)
-#define bfin_write_DMA2_11_CURR_DESC_PTR(val) bfin_write32(DMA2_11_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_11_CURR_ADDR() bfin_read32(DMA2_11_CURR_ADDR)
-#define bfin_write_DMA2_11_CURR_ADDR(val) bfin_write32(DMA2_11_CURR_ADDR,val)
-#define bfin_read_DMA2_11_CURR_X_COUNT() bfin_read16(DMA2_11_CURR_X_COUNT)
-#define bfin_write_DMA2_11_CURR_X_COUNT(val) bfin_write16(DMA2_11_CURR_X_COUNT,val)
-#define bfin_read_DMA2_11_CURR_Y_COUNT() bfin_read16(DMA2_11_CURR_Y_COUNT)
-#define bfin_write_DMA2_11_CURR_Y_COUNT(val) bfin_write16(DMA2_11_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_11_IRQ_STATUS() bfin_read16(DMA2_11_IRQ_STATUS)
-#define bfin_write_DMA2_11_IRQ_STATUS(val) bfin_write16(DMA2_11_IRQ_STATUS,val)
-#define bfin_read_DMA2_11_PERIPHERAL_MAP() bfin_read16(DMA2_11_PERIPHERAL_MAP)
-#define bfin_write_DMA2_11_PERIPHERAL_MAP(val) bfin_write16(DMA2_11_PERIPHERAL_MAP,val)
-/* Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) */
-#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
-#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG,val)
-#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR)
-#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR,val)
-#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
-#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT,val)
-#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
-#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT,val)
-#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
-#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY,val)
-#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
-#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY,val)
-#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR)
-#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR,val)
-#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
-#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT,val)
-#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
-#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS,val)
-#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP,val)
-#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
-#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG,val)
-#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR)
-#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR,val)
-#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
-#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT,val)
-#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
-#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT,val)
-#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
-#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY,val)
-#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
-#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY,val)
-#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR)
-#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR,val)
-#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
-#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT,val)
-#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
-#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS,val)
-#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP,val)
-#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
-#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG,val)
-#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR)
-#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR,val)
-#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
-#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT,val)
-#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
-#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT,val)
-#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
-#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY,val)
-#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
-#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY,val)
-#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR)
-#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR,val)
-#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
-#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT,val)
-#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
-#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS,val)
-#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP,val)
-#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
-#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG,val)
-#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR)
-#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR,val)
-#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
-#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT,val)
-#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
-#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT,val)
-#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
-#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY,val)
-#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
-#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY,val)
-#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR)
-#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR,val)
-#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
-#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT,val)
-#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
-#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS,val)
-#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP,val)
-/* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */
-#define bfin_read_IMDMA_D0_CONFIG() bfin_read16(IMDMA_D0_CONFIG)
-#define bfin_write_IMDMA_D0_CONFIG(val) bfin_write16(IMDMA_D0_CONFIG,val)
-#define bfin_read_IMDMA_D0_NEXT_DESC_PTR() bfin_read32(IMDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_IMDMA_D0_NEXT_DESC_PTR(val) bfin_write32(IMDMA_D0_NEXT_DESC_PTR,val)
-#define bfin_read_IMDMA_D0_START_ADDR() bfin_read32(IMDMA_D0_START_ADDR)
-#define bfin_write_IMDMA_D0_START_ADDR(val) bfin_write32(IMDMA_D0_START_ADDR,val)
-#define bfin_read_IMDMA_D0_X_COUNT() bfin_read16(IMDMA_D0_X_COUNT)
-#define bfin_write_IMDMA_D0_X_COUNT(val) bfin_write16(IMDMA_D0_X_COUNT,val)
-#define bfin_read_IMDMA_D0_Y_COUNT() bfin_read16(IMDMA_D0_Y_COUNT)
-#define bfin_write_IMDMA_D0_Y_COUNT(val) bfin_write16(IMDMA_D0_Y_COUNT,val)
-#define bfin_read_IMDMA_D0_X_MODIFY() bfin_read16(IMDMA_D0_X_MODIFY)
-#define bfin_write_IMDMA_D0_X_MODIFY(val) bfin_write16(IMDMA_D0_X_MODIFY,val)
-#define bfin_read_IMDMA_D0_Y_MODIFY() bfin_read16(IMDMA_D0_Y_MODIFY)
-#define bfin_write_IMDMA_D0_Y_MODIFY(val) bfin_write16(IMDMA_D0_Y_MODIFY,val)
-#define bfin_read_IMDMA_D0_CURR_DESC_PTR() bfin_read32(IMDMA_D0_CURR_DESC_PTR)
-#define bfin_write_IMDMA_D0_CURR_DESC_PTR(val) bfin_write32(IMDMA_D0_CURR_DESC_PTR,val)
-#define bfin_read_IMDMA_D0_CURR_ADDR() bfin_read32(IMDMA_D0_CURR_ADDR)
-#define bfin_write_IMDMA_D0_CURR_ADDR(val) bfin_write32(IMDMA_D0_CURR_ADDR,val)
-#define bfin_read_IMDMA_D0_CURR_X_COUNT() bfin_read16(IMDMA_D0_CURR_X_COUNT)
-#define bfin_write_IMDMA_D0_CURR_X_COUNT(val) bfin_write16(IMDMA_D0_CURR_X_COUNT,val)
-#define bfin_read_IMDMA_D0_CURR_Y_COUNT() bfin_read16(IMDMA_D0_CURR_Y_COUNT)
-#define bfin_write_IMDMA_D0_CURR_Y_COUNT(val) bfin_write16(IMDMA_D0_CURR_Y_COUNT,val)
-#define bfin_read_IMDMA_D0_IRQ_STATUS() bfin_read16(IMDMA_D0_IRQ_STATUS)
-#define bfin_write_IMDMA_D0_IRQ_STATUS(val) bfin_write16(IMDMA_D0_IRQ_STATUS,val)
-#define bfin_read_IMDMA_S0_CONFIG() bfin_read16(IMDMA_S0_CONFIG)
-#define bfin_write_IMDMA_S0_CONFIG(val) bfin_write16(IMDMA_S0_CONFIG,val)
-#define bfin_read_IMDMA_S0_NEXT_DESC_PTR() bfin_read32(IMDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_IMDMA_S0_NEXT_DESC_PTR(val) bfin_write32(IMDMA_S0_NEXT_DESC_PTR,val)
-#define bfin_read_IMDMA_S0_START_ADDR() bfin_read32(IMDMA_S0_START_ADDR)
-#define bfin_write_IMDMA_S0_START_ADDR(val) bfin_write32(IMDMA_S0_START_ADDR,val)
-#define bfin_read_IMDMA_S0_X_COUNT() bfin_read16(IMDMA_S0_X_COUNT)
-#define bfin_write_IMDMA_S0_X_COUNT(val) bfin_write16(IMDMA_S0_X_COUNT,val)
-#define bfin_read_IMDMA_S0_Y_COUNT() bfin_read16(IMDMA_S0_Y_COUNT)
-#define bfin_write_IMDMA_S0_Y_COUNT(val) bfin_write16(IMDMA_S0_Y_COUNT,val)
-#define bfin_read_IMDMA_S0_X_MODIFY() bfin_read16(IMDMA_S0_X_MODIFY)
-#define bfin_write_IMDMA_S0_X_MODIFY(val) bfin_write16(IMDMA_S0_X_MODIFY,val)
-#define bfin_read_IMDMA_S0_Y_MODIFY() bfin_read16(IMDMA_S0_Y_MODIFY)
-#define bfin_write_IMDMA_S0_Y_MODIFY(val) bfin_write16(IMDMA_S0_Y_MODIFY,val)
-#define bfin_read_IMDMA_S0_CURR_DESC_PTR() bfin_read32(IMDMA_S0_CURR_DESC_PTR)
-#define bfin_write_IMDMA_S0_CURR_DESC_PTR(val) bfin_write32(IMDMA_S0_CURR_DESC_PTR,val)
-#define bfin_read_IMDMA_S0_CURR_ADDR() bfin_read32(IMDMA_S0_CURR_ADDR)
-#define bfin_write_IMDMA_S0_CURR_ADDR(val) bfin_write32(IMDMA_S0_CURR_ADDR,val)
-#define bfin_read_IMDMA_S0_CURR_X_COUNT() bfin_read16(IMDMA_S0_CURR_X_COUNT)
-#define bfin_write_IMDMA_S0_CURR_X_COUNT(val) bfin_write16(IMDMA_S0_CURR_X_COUNT,val)
-#define bfin_read_IMDMA_S0_CURR_Y_COUNT() bfin_read16(IMDMA_S0_CURR_Y_COUNT)
-#define bfin_write_IMDMA_S0_CURR_Y_COUNT(val) bfin_write16(IMDMA_S0_CURR_Y_COUNT,val)
-#define bfin_read_IMDMA_S0_IRQ_STATUS() bfin_read16(IMDMA_S0_IRQ_STATUS)
-#define bfin_write_IMDMA_S0_IRQ_STATUS(val) bfin_write16(IMDMA_S0_IRQ_STATUS,val)
-#define bfin_read_IMDMA_D1_CONFIG() bfin_read16(IMDMA_D1_CONFIG)
-#define bfin_write_IMDMA_D1_CONFIG(val) bfin_write16(IMDMA_D1_CONFIG,val)
-#define bfin_read_IMDMA_D1_NEXT_DESC_PTR() bfin_read32(IMDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_IMDMA_D1_NEXT_DESC_PTR(val) bfin_write32(IMDMA_D1_NEXT_DESC_PTR,val)
-#define bfin_read_IMDMA_D1_START_ADDR() bfin_read32(IMDMA_D1_START_ADDR)
-#define bfin_write_IMDMA_D1_START_ADDR(val) bfin_write32(IMDMA_D1_START_ADDR,val)
-#define bfin_read_IMDMA_D1_X_COUNT() bfin_read16(IMDMA_D1_X_COUNT)
-#define bfin_write_IMDMA_D1_X_COUNT(val) bfin_write16(IMDMA_D1_X_COUNT,val)
-#define bfin_read_IMDMA_D1_Y_COUNT() bfin_read16(IMDMA_D1_Y_COUNT)
-#define bfin_write_IMDMA_D1_Y_COUNT(val) bfin_write16(IMDMA_D1_Y_COUNT,val)
-#define bfin_read_IMDMA_D1_X_MODIFY() bfin_read16(IMDMA_D1_X_MODIFY)
-#define bfin_write_IMDMA_D1_X_MODIFY(val) bfin_write16(IMDMA_D1_X_MODIFY,val)
-#define bfin_read_IMDMA_D1_Y_MODIFY() bfin_read16(IMDMA_D1_Y_MODIFY)
-#define bfin_write_IMDMA_D1_Y_MODIFY(val) bfin_write16(IMDMA_D1_Y_MODIFY,val)
-#define bfin_read_IMDMA_D1_CURR_DESC_PTR() bfin_read32(IMDMA_D1_CURR_DESC_PTR)
-#define bfin_write_IMDMA_D1_CURR_DESC_PTR(val) bfin_write32(IMDMA_D1_CURR_DESC_PTR,val)
-#define bfin_read_IMDMA_D1_CURR_ADDR() bfin_read32(IMDMA_D1_CURR_ADDR)
-#define bfin_write_IMDMA_D1_CURR_ADDR(val) bfin_write32(IMDMA_D1_CURR_ADDR,val)
-#define bfin_read_IMDMA_D1_CURR_X_COUNT() bfin_read16(IMDMA_D1_CURR_X_COUNT)
-#define bfin_write_IMDMA_D1_CURR_X_COUNT(val) bfin_write16(IMDMA_D1_CURR_X_COUNT,val)
-#define bfin_read_IMDMA_D1_CURR_Y_COUNT() bfin_read16(IMDMA_D1_CURR_Y_COUNT)
-#define bfin_write_IMDMA_D1_CURR_Y_COUNT(val) bfin_write16(IMDMA_D1_CURR_Y_COUNT,val)
-#define bfin_read_IMDMA_D1_IRQ_STATUS() bfin_read16(IMDMA_D1_IRQ_STATUS)
-#define bfin_write_IMDMA_D1_IRQ_STATUS(val) bfin_write16(IMDMA_D1_IRQ_STATUS,val)
-#define bfin_read_IMDMA_S1_CONFIG() bfin_read16(IMDMA_S1_CONFIG)
-#define bfin_write_IMDMA_S1_CONFIG(val) bfin_write16(IMDMA_S1_CONFIG,val)
-#define bfin_read_IMDMA_S1_NEXT_DESC_PTR() bfin_read32(IMDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_IMDMA_S1_NEXT_DESC_PTR(val) bfin_write32(IMDMA_S1_NEXT_DESC_PTR,val)
-#define bfin_read_IMDMA_S1_START_ADDR() bfin_read32(IMDMA_S1_START_ADDR)
-#define bfin_write_IMDMA_S1_START_ADDR(val) bfin_write32(IMDMA_S1_START_ADDR,val)
-#define bfin_read_IMDMA_S1_X_COUNT() bfin_read16(IMDMA_S1_X_COUNT)
-#define bfin_write_IMDMA_S1_X_COUNT(val) bfin_write16(IMDMA_S1_X_COUNT,val)
-#define bfin_read_IMDMA_S1_Y_COUNT() bfin_read16(IMDMA_S1_Y_COUNT)
-#define bfin_write_IMDMA_S1_Y_COUNT(val) bfin_write16(IMDMA_S1_Y_COUNT,val)
-#define bfin_read_IMDMA_S1_X_MODIFY() bfin_read16(IMDMA_S1_X_MODIFY)
-#define bfin_write_IMDMA_S1_X_MODIFY(val) bfin_write16(IMDMA_S1_X_MODIFY,val)
-#define bfin_read_IMDMA_S1_Y_MODIFY() bfin_read16(IMDMA_S1_Y_MODIFY)
-#define bfin_write_IMDMA_S1_Y_MODIFY(val) bfin_write16(IMDMA_S1_Y_MODIFY,val)
-#define bfin_read_IMDMA_S1_CURR_DESC_PTR() bfin_read32(IMDMA_S1_CURR_DESC_PTR)
-#define bfin_write_IMDMA_S1_CURR_DESC_PTR(val) bfin_write32(IMDMA_S1_CURR_DESC_PTR,val)
-#define bfin_read_IMDMA_S1_CURR_ADDR() bfin_read32(IMDMA_S1_CURR_ADDR)
-#define bfin_write_IMDMA_S1_CURR_ADDR(val) bfin_write32(IMDMA_S1_CURR_ADDR,val)
-#define bfin_read_IMDMA_S1_CURR_X_COUNT() bfin_read16(IMDMA_S1_CURR_X_COUNT)
-#define bfin_write_IMDMA_S1_CURR_X_COUNT(val) bfin_write16(IMDMA_S1_CURR_X_COUNT,val)
-#define bfin_read_IMDMA_S1_CURR_Y_COUNT() bfin_read16(IMDMA_S1_CURR_Y_COUNT)
-#define bfin_write_IMDMA_S1_CURR_Y_COUNT(val) bfin_write16(IMDMA_S1_CURR_Y_COUNT,val)
-#define bfin_read_IMDMA_S1_IRQ_STATUS() bfin_read16(IMDMA_S1_IRQ_STATUS)
-#define bfin_write_IMDMA_S1_IRQ_STATUS(val) bfin_write16(IMDMA_S1_IRQ_STATUS,val)
-
-#endif /* _CDEF_BF561_H */
+++ /dev/null
-/*
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF561_H
-#define _DEF_BF561_H
-
-/*********************************************************************************** */
-/* System MMR Register Map */
-/*********************************************************************************** */
-
-/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
-
-#define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */
-#define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */
-#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */
-#define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */
-#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */
-#define CHIPID 0xFFC00014 /* Chip ID Register */
-
-/* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */
-#define DOUBLE_FAULT (DOUBLE_FAULT_B|DOUBLE_FAULT_A)
-#define RESET_DOUBLE (SWRST_DBL_FAULT_B|SWRST_DBL_FAULT_A)
-#define RESET_WDOG (SWRST_WDT_B|SWRST_WDT_A)
-#define RESET_SOFTWARE (SWRST_OCCURRED)
-
-/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */
-#define SWRST 0xFFC00100 /* Software Reset register */
-#define SYSCR 0xFFC00104 /* System Reset Configuration register */
-#define SIC_RVECT 0xFFC00108 /* SIC Reset Vector Address Register */
-#define SIC_IMASK0 0xFFC0010C /* SIC Interrupt Mask register 0 */
-#define SIC_IMASK1 0xFFC00110 /* SIC Interrupt Mask register 1 */
-#define SIC_IAR0 0xFFC00124 /* SIC Interrupt Assignment Register 0 */
-#define SIC_IAR1 0xFFC00128 /* SIC Interrupt Assignment Register 1 */
-#define SIC_IAR2 0xFFC0012C /* SIC Interrupt Assignment Register 2 */
-#define SIC_IAR3 0xFFC00130 /* SIC Interrupt Assignment Register 3 */
-#define SIC_IAR4 0xFFC00134 /* SIC Interrupt Assignment Register 4 */
-#define SIC_IAR5 0xFFC00138 /* SIC Interrupt Assignment Register 5 */
-#define SIC_IAR6 0xFFC0013C /* SIC Interrupt Assignment Register 6 */
-#define SIC_IAR7 0xFFC00140 /* SIC Interrupt Assignment Register 7 */
-#define SIC_ISR0 0xFFC00114 /* SIC Interrupt Status register 0 */
-#define SIC_ISR1 0xFFC00118 /* SIC Interrupt Status register 1 */
-#define SIC_IWR0 0xFFC0011C /* SIC Interrupt Wakeup-Enable register 0 */
-#define SIC_IWR1 0xFFC00120 /* SIC Interrupt Wakeup-Enable register 1 */
-
-/* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */
-#define SICB_SWRST 0xFFC01100 /* reserved */
-#define SICB_SYSCR 0xFFC01104 /* reserved */
-#define SICB_RVECT 0xFFC01108 /* SIC Reset Vector Address Register */
-#define SICB_IMASK0 0xFFC0110C /* SIC Interrupt Mask register 0 */
-#define SICB_IMASK1 0xFFC01110 /* SIC Interrupt Mask register 1 */
-#define SICB_IAR0 0xFFC01124 /* SIC Interrupt Assignment Register 0 */
-#define SICB_IAR1 0xFFC01128 /* SIC Interrupt Assignment Register 1 */
-#define SICB_IAR2 0xFFC0112C /* SIC Interrupt Assignment Register 2 */
-#define SICB_IAR3 0xFFC01130 /* SIC Interrupt Assignment Register 3 */
-#define SICB_IAR4 0xFFC01134 /* SIC Interrupt Assignment Register 4 */
-#define SICB_IAR5 0xFFC01138 /* SIC Interrupt Assignment Register 5 */
-#define SICB_IAR6 0xFFC0113C /* SIC Interrupt Assignment Register 6 */
-#define SICB_IAR7 0xFFC01140 /* SIC Interrupt Assignment Register 7 */
-#define SICB_ISR0 0xFFC01114 /* SIC Interrupt Status register 0 */
-#define SICB_ISR1 0xFFC01118 /* SIC Interrupt Status register 1 */
-#define SICB_IWR0 0xFFC0111C /* SIC Interrupt Wakeup-Enable register 0 */
-#define SICB_IWR1 0xFFC01120 /* SIC Interrupt Wakeup-Enable register 1 */
-
-/* Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) */
-#define WDOGA_CTL 0xFFC00200 /* Watchdog Control register */
-#define WDOGA_CNT 0xFFC00204 /* Watchdog Count register */
-#define WDOGA_STAT 0xFFC00208 /* Watchdog Status register */
-
-/* Watchdog Timer registers for Core B (0xFFC0 1200-0xFFC0 12FF) */
-#define WDOGB_CTL 0xFFC01200 /* Watchdog Control register */
-#define WDOGB_CNT 0xFFC01204 /* Watchdog Count register */
-#define WDOGB_STAT 0xFFC01208 /* Watchdog Status register */
-
-/* UART Controller (0xFFC00400 - 0xFFC004FF) */
-
-/*
- * Because include/linux/serial_reg.h have defined UART_*,
- * So we define blackfin uart regs to BFIN_UART0_*.
- */
-#define BFIN_UART_THR 0xFFC00400 /* Transmit Holding register */
-#define BFIN_UART_RBR 0xFFC00400 /* Receive Buffer register */
-#define BFIN_UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
-#define BFIN_UART_IER 0xFFC00404 /* Interrupt Enable Register */
-#define BFIN_UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
-#define BFIN_UART_IIR 0xFFC00408 /* Interrupt Identification Register */
-#define BFIN_UART_LCR 0xFFC0040C /* Line Control Register */
-#define BFIN_UART_MCR 0xFFC00410 /* Modem Control Register */
-#define BFIN_UART_LSR 0xFFC00414 /* Line Status Register */
-#define BFIN_UART_MSR 0xFFC00418 /* Modem Status Register */
-#define BFIN_UART_SCR 0xFFC0041C /* SCR Scratch Register */
-#define BFIN_UART_GCTL 0xFFC00424 /* Global Control Register */
-
-/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
-#define SPI0_REGBASE 0xFFC00500
-#define SPI_CTL 0xFFC00500 /* SPI Control Register */
-#define SPI_FLG 0xFFC00504 /* SPI Flag register */
-#define SPI_STAT 0xFFC00508 /* SPI Status register */
-#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */
-#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */
-#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */
-#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */
-
-/* Timer 0-7 registers (0xFFC0 0600-0xFFC0 06FF) */
-#define TIMER0_CONFIG 0xFFC00600 /* Timer0 Configuration register */
-#define TIMER0_COUNTER 0xFFC00604 /* Timer0 Counter register */
-#define TIMER0_PERIOD 0xFFC00608 /* Timer0 Period register */
-#define TIMER0_WIDTH 0xFFC0060C /* Timer0 Width register */
-
-#define TIMER1_CONFIG 0xFFC00610 /* Timer1 Configuration register */
-#define TIMER1_COUNTER 0xFFC00614 /* Timer1 Counter register */
-#define TIMER1_PERIOD 0xFFC00618 /* Timer1 Period register */
-#define TIMER1_WIDTH 0xFFC0061C /* Timer1 Width register */
-
-#define TIMER2_CONFIG 0xFFC00620 /* Timer2 Configuration register */
-#define TIMER2_COUNTER 0xFFC00624 /* Timer2 Counter register */
-#define TIMER2_PERIOD 0xFFC00628 /* Timer2 Period register */
-#define TIMER2_WIDTH 0xFFC0062C /* Timer2 Width register */
-
-#define TIMER3_CONFIG 0xFFC00630 /* Timer3 Configuration register */
-#define TIMER3_COUNTER 0xFFC00634 /* Timer3 Counter register */
-#define TIMER3_PERIOD 0xFFC00638 /* Timer3 Period register */
-#define TIMER3_WIDTH 0xFFC0063C /* Timer3 Width register */
-
-#define TIMER4_CONFIG 0xFFC00640 /* Timer4 Configuration register */
-#define TIMER4_COUNTER 0xFFC00644 /* Timer4 Counter register */
-#define TIMER4_PERIOD 0xFFC00648 /* Timer4 Period register */
-#define TIMER4_WIDTH 0xFFC0064C /* Timer4 Width register */
-
-#define TIMER5_CONFIG 0xFFC00650 /* Timer5 Configuration register */
-#define TIMER5_COUNTER 0xFFC00654 /* Timer5 Counter register */
-#define TIMER5_PERIOD 0xFFC00658 /* Timer5 Period register */
-#define TIMER5_WIDTH 0xFFC0065C /* Timer5 Width register */
-
-#define TIMER6_CONFIG 0xFFC00660 /* Timer6 Configuration register */
-#define TIMER6_COUNTER 0xFFC00664 /* Timer6 Counter register */
-#define TIMER6_PERIOD 0xFFC00668 /* Timer6 Period register */
-#define TIMER6_WIDTH 0xFFC0066C /* Timer6 Width register */
-
-#define TIMER7_CONFIG 0xFFC00670 /* Timer7 Configuration register */
-#define TIMER7_COUNTER 0xFFC00674 /* Timer7 Counter register */
-#define TIMER7_PERIOD 0xFFC00678 /* Timer7 Period register */
-#define TIMER7_WIDTH 0xFFC0067C /* Timer7 Width register */
-
-#define TMRS8_ENABLE 0xFFC00680 /* Timer Enable Register */
-#define TMRS8_DISABLE 0xFFC00684 /* Timer Disable register */
-#define TMRS8_STATUS 0xFFC00688 /* Timer Status register */
-
-/* Timer registers 8-11 (0xFFC0 1600-0xFFC0 16FF) */
-#define TIMER8_CONFIG 0xFFC01600 /* Timer8 Configuration register */
-#define TIMER8_COUNTER 0xFFC01604 /* Timer8 Counter register */
-#define TIMER8_PERIOD 0xFFC01608 /* Timer8 Period register */
-#define TIMER8_WIDTH 0xFFC0160C /* Timer8 Width register */
-
-#define TIMER9_CONFIG 0xFFC01610 /* Timer9 Configuration register */
-#define TIMER9_COUNTER 0xFFC01614 /* Timer9 Counter register */
-#define TIMER9_PERIOD 0xFFC01618 /* Timer9 Period register */
-#define TIMER9_WIDTH 0xFFC0161C /* Timer9 Width register */
-
-#define TIMER10_CONFIG 0xFFC01620 /* Timer10 Configuration register */
-#define TIMER10_COUNTER 0xFFC01624 /* Timer10 Counter register */
-#define TIMER10_PERIOD 0xFFC01628 /* Timer10 Period register */
-#define TIMER10_WIDTH 0xFFC0162C /* Timer10 Width register */
-
-#define TIMER11_CONFIG 0xFFC01630 /* Timer11 Configuration register */
-#define TIMER11_COUNTER 0xFFC01634 /* Timer11 Counter register */
-#define TIMER11_PERIOD 0xFFC01638 /* Timer11 Period register */
-#define TIMER11_WIDTH 0xFFC0163C /* Timer11 Width register */
-
-#define TMRS4_ENABLE 0xFFC01640 /* Timer Enable Register */
-#define TMRS4_DISABLE 0xFFC01644 /* Timer Disable register */
-#define TMRS4_STATUS 0xFFC01648 /* Timer Status register */
-
-/* Programmable Flag 0 registers (0xFFC0 0700-0xFFC0 07FF) */
-#define FIO0_FLAG_D 0xFFC00700 /* Flag Data register */
-#define FIO0_FLAG_C 0xFFC00704 /* Flag Clear register */
-#define FIO0_FLAG_S 0xFFC00708 /* Flag Set register */
-#define FIO0_FLAG_T 0xFFC0070C /* Flag Toggle register */
-#define FIO0_MASKA_D 0xFFC00710 /* Flag Mask Interrupt A Data register */
-#define FIO0_MASKA_C 0xFFC00714 /* Flag Mask Interrupt A Clear register */
-#define FIO0_MASKA_S 0xFFC00718 /* Flag Mask Interrupt A Set register */
-#define FIO0_MASKA_T 0xFFC0071C /* Flag Mask Interrupt A Toggle register */
-#define FIO0_MASKB_D 0xFFC00720 /* Flag Mask Interrupt B Data register */
-#define FIO0_MASKB_C 0xFFC00724 /* Flag Mask Interrupt B Clear register */
-#define FIO0_MASKB_S 0xFFC00728 /* Flag Mask Interrupt B Set register */
-#define FIO0_MASKB_T 0xFFC0072C /* Flag Mask Interrupt B Toggle register */
-#define FIO0_DIR 0xFFC00730 /* Flag Direction register */
-#define FIO0_POLAR 0xFFC00734 /* Flag Polarity register */
-#define FIO0_EDGE 0xFFC00738 /* Flag Interrupt Sensitivity register */
-#define FIO0_BOTH 0xFFC0073C /* Flag Set on Both Edges register */
-#define FIO0_INEN 0xFFC00740 /* Flag Input Enable register */
-
-/* Programmable Flag 1 registers (0xFFC0 1500-0xFFC0 15FF) */
-#define FIO1_FLAG_D 0xFFC01500 /* Flag Data register (mask used to directly */
-#define FIO1_FLAG_C 0xFFC01504 /* Flag Clear register */
-#define FIO1_FLAG_S 0xFFC01508 /* Flag Set register */
-#define FIO1_FLAG_T 0xFFC0150C /* Flag Toggle register (mask used to */
-#define FIO1_MASKA_D 0xFFC01510 /* Flag Mask Interrupt A Data register */
-#define FIO1_MASKA_C 0xFFC01514 /* Flag Mask Interrupt A Clear register */
-#define FIO1_MASKA_S 0xFFC01518 /* Flag Mask Interrupt A Set register */
-#define FIO1_MASKA_T 0xFFC0151C /* Flag Mask Interrupt A Toggle register */
-#define FIO1_MASKB_D 0xFFC01520 /* Flag Mask Interrupt B Data register */
-#define FIO1_MASKB_C 0xFFC01524 /* Flag Mask Interrupt B Clear register */
-#define FIO1_MASKB_S 0xFFC01528 /* Flag Mask Interrupt B Set register */
-#define FIO1_MASKB_T 0xFFC0152C /* Flag Mask Interrupt B Toggle register */
-#define FIO1_DIR 0xFFC01530 /* Flag Direction register */
-#define FIO1_POLAR 0xFFC01534 /* Flag Polarity register */
-#define FIO1_EDGE 0xFFC01538 /* Flag Interrupt Sensitivity register */
-#define FIO1_BOTH 0xFFC0153C /* Flag Set on Both Edges register */
-#define FIO1_INEN 0xFFC01540 /* Flag Input Enable register */
-
-/* Programmable Flag registers (0xFFC0 1700-0xFFC0 17FF) */
-#define FIO2_FLAG_D 0xFFC01700 /* Flag Data register (mask used to directly */
-#define FIO2_FLAG_C 0xFFC01704 /* Flag Clear register */
-#define FIO2_FLAG_S 0xFFC01708 /* Flag Set register */
-#define FIO2_FLAG_T 0xFFC0170C /* Flag Toggle register (mask used to */
-#define FIO2_MASKA_D 0xFFC01710 /* Flag Mask Interrupt A Data register */
-#define FIO2_MASKA_C 0xFFC01714 /* Flag Mask Interrupt A Clear register */
-#define FIO2_MASKA_S 0xFFC01718 /* Flag Mask Interrupt A Set register */
-#define FIO2_MASKA_T 0xFFC0171C /* Flag Mask Interrupt A Toggle register */
-#define FIO2_MASKB_D 0xFFC01720 /* Flag Mask Interrupt B Data register */
-#define FIO2_MASKB_C 0xFFC01724 /* Flag Mask Interrupt B Clear register */
-#define FIO2_MASKB_S 0xFFC01728 /* Flag Mask Interrupt B Set register */
-#define FIO2_MASKB_T 0xFFC0172C /* Flag Mask Interrupt B Toggle register */
-#define FIO2_DIR 0xFFC01730 /* Flag Direction register */
-#define FIO2_POLAR 0xFFC01734 /* Flag Polarity register */
-#define FIO2_EDGE 0xFFC01738 /* Flag Interrupt Sensitivity register */
-#define FIO2_BOTH 0xFFC0173C /* Flag Set on Both Edges register */
-#define FIO2_INEN 0xFFC01740 /* Flag Input Enable register */
-
-/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
-#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
-#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
-#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
-#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
-#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
-#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
-#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
-#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
-#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
-#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
-#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
-#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
-#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
-#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
-#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
-#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
-#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
-#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
-
-/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
-#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
-#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
-#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
-#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
-#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
-#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
-#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
-#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
-#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
-#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
-#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
-#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
-#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
-#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
-#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
-#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
-#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
-#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
-
-/* Asynchronous Memory Controller - External Bus Interface Unit */
-#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
-#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
-#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
-
-/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
-#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
-#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
-#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
-#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
-
-/* Parallel Peripheral Interface (PPI) 0 registers (0xFFC0 1000-0xFFC0 10FF) */
-#define PPI0_CONTROL 0xFFC01000 /* PPI0 Control register */
-#define PPI0_STATUS 0xFFC01004 /* PPI0 Status register */
-#define PPI0_COUNT 0xFFC01008 /* PPI0 Transfer Count register */
-#define PPI0_DELAY 0xFFC0100C /* PPI0 Delay Count register */
-#define PPI0_FRAME 0xFFC01010 /* PPI0 Frame Length register */
-
-/*Parallel Peripheral Interface (PPI) 1 registers (0xFFC0 1300-0xFFC0 13FF) */
-#define PPI1_CONTROL 0xFFC01300 /* PPI1 Control register */
-#define PPI1_STATUS 0xFFC01304 /* PPI1 Status register */
-#define PPI1_COUNT 0xFFC01308 /* PPI1 Transfer Count register */
-#define PPI1_DELAY 0xFFC0130C /* PPI1 Delay Count register */
-#define PPI1_FRAME 0xFFC01310 /* PPI1 Frame Length register */
-
-/*DMA traffic control registers */
-#define DMAC0_TC_PER 0xFFC00B0C /* Traffic control periods */
-#define DMAC0_TC_CNT 0xFFC00B10 /* Traffic control current counts */
-#define DMAC1_TC_PER 0xFFC01B0C /* Traffic control periods */
-#define DMAC1_TC_CNT 0xFFC01B10 /* Traffic control current counts */
-
-/* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */
-#define DMA1_0_CONFIG 0xFFC01C08 /* DMA1 Channel 0 Configuration register */
-#define DMA1_0_NEXT_DESC_PTR 0xFFC01C00 /* DMA1 Channel 0 Next Descripter Ptr Reg */
-#define DMA1_0_START_ADDR 0xFFC01C04 /* DMA1 Channel 0 Start Address */
-#define DMA1_0_X_COUNT 0xFFC01C10 /* DMA1 Channel 0 Inner Loop Count */
-#define DMA1_0_Y_COUNT 0xFFC01C18 /* DMA1 Channel 0 Outer Loop Count */
-#define DMA1_0_X_MODIFY 0xFFC01C14 /* DMA1 Channel 0 Inner Loop Addr Increment */
-#define DMA1_0_Y_MODIFY 0xFFC01C1C /* DMA1 Channel 0 Outer Loop Addr Increment */
-#define DMA1_0_CURR_DESC_PTR 0xFFC01C20 /* DMA1 Channel 0 Current Descriptor Pointer */
-#define DMA1_0_CURR_ADDR 0xFFC01C24 /* DMA1 Channel 0 Current Address Pointer */
-#define DMA1_0_CURR_X_COUNT 0xFFC01C30 /* DMA1 Channel 0 Current Inner Loop Count */
-#define DMA1_0_CURR_Y_COUNT 0xFFC01C38 /* DMA1 Channel 0 Current Outer Loop Count */
-#define DMA1_0_IRQ_STATUS 0xFFC01C28 /* DMA1 Channel 0 Interrupt/Status Register */
-#define DMA1_0_PERIPHERAL_MAP 0xFFC01C2C /* DMA1 Channel 0 Peripheral Map Register */
-
-#define DMA1_1_CONFIG 0xFFC01C48 /* DMA1 Channel 1 Configuration register */
-#define DMA1_1_NEXT_DESC_PTR 0xFFC01C40 /* DMA1 Channel 1 Next Descripter Ptr Reg */
-#define DMA1_1_START_ADDR 0xFFC01C44 /* DMA1 Channel 1 Start Address */
-#define DMA1_1_X_COUNT 0xFFC01C50 /* DMA1 Channel 1 Inner Loop Count */
-#define DMA1_1_Y_COUNT 0xFFC01C58 /* DMA1 Channel 1 Outer Loop Count */
-#define DMA1_1_X_MODIFY 0xFFC01C54 /* DMA1 Channel 1 Inner Loop Addr Increment */
-#define DMA1_1_Y_MODIFY 0xFFC01C5C /* DMA1 Channel 1 Outer Loop Addr Increment */
-#define DMA1_1_CURR_DESC_PTR 0xFFC01C60 /* DMA1 Channel 1 Current Descriptor Pointer */
-#define DMA1_1_CURR_ADDR 0xFFC01C64 /* DMA1 Channel 1 Current Address Pointer */
-#define DMA1_1_CURR_X_COUNT 0xFFC01C70 /* DMA1 Channel 1 Current Inner Loop Count */
-#define DMA1_1_CURR_Y_COUNT 0xFFC01C78 /* DMA1 Channel 1 Current Outer Loop Count */
-#define DMA1_1_IRQ_STATUS 0xFFC01C68 /* DMA1 Channel 1 Interrupt/Status Register */
-#define DMA1_1_PERIPHERAL_MAP 0xFFC01C6C /* DMA1 Channel 1 Peripheral Map Register */
-
-#define DMA1_2_CONFIG 0xFFC01C88 /* DMA1 Channel 2 Configuration register */
-#define DMA1_2_NEXT_DESC_PTR 0xFFC01C80 /* DMA1 Channel 2 Next Descripter Ptr Reg */
-#define DMA1_2_START_ADDR 0xFFC01C84 /* DMA1 Channel 2 Start Address */
-#define DMA1_2_X_COUNT 0xFFC01C90 /* DMA1 Channel 2 Inner Loop Count */
-#define DMA1_2_Y_COUNT 0xFFC01C98 /* DMA1 Channel 2 Outer Loop Count */
-#define DMA1_2_X_MODIFY 0xFFC01C94 /* DMA1 Channel 2 Inner Loop Addr Increment */
-#define DMA1_2_Y_MODIFY 0xFFC01C9C /* DMA1 Channel 2 Outer Loop Addr Increment */
-#define DMA1_2_CURR_DESC_PTR 0xFFC01CA0 /* DMA1 Channel 2 Current Descriptor Pointer */
-#define DMA1_2_CURR_ADDR 0xFFC01CA4 /* DMA1 Channel 2 Current Address Pointer */
-#define DMA1_2_CURR_X_COUNT 0xFFC01CB0 /* DMA1 Channel 2 Current Inner Loop Count */
-#define DMA1_2_CURR_Y_COUNT 0xFFC01CB8 /* DMA1 Channel 2 Current Outer Loop Count */
-#define DMA1_2_IRQ_STATUS 0xFFC01CA8 /* DMA1 Channel 2 Interrupt/Status Register */
-#define DMA1_2_PERIPHERAL_MAP 0xFFC01CAC /* DMA1 Channel 2 Peripheral Map Register */
-
-#define DMA1_3_CONFIG 0xFFC01CC8 /* DMA1 Channel 3 Configuration register */
-#define DMA1_3_NEXT_DESC_PTR 0xFFC01CC0 /* DMA1 Channel 3 Next Descripter Ptr Reg */
-#define DMA1_3_START_ADDR 0xFFC01CC4 /* DMA1 Channel 3 Start Address */
-#define DMA1_3_X_COUNT 0xFFC01CD0 /* DMA1 Channel 3 Inner Loop Count */
-#define DMA1_3_Y_COUNT 0xFFC01CD8 /* DMA1 Channel 3 Outer Loop Count */
-#define DMA1_3_X_MODIFY 0xFFC01CD4 /* DMA1 Channel 3 Inner Loop Addr Increment */
-#define DMA1_3_Y_MODIFY 0xFFC01CDC /* DMA1 Channel 3 Outer Loop Addr Increment */
-#define DMA1_3_CURR_DESC_PTR 0xFFC01CE0 /* DMA1 Channel 3 Current Descriptor Pointer */
-#define DMA1_3_CURR_ADDR 0xFFC01CE4 /* DMA1 Channel 3 Current Address Pointer */
-#define DMA1_3_CURR_X_COUNT 0xFFC01CF0 /* DMA1 Channel 3 Current Inner Loop Count */
-#define DMA1_3_CURR_Y_COUNT 0xFFC01CF8 /* DMA1 Channel 3 Current Outer Loop Count */
-#define DMA1_3_IRQ_STATUS 0xFFC01CE8 /* DMA1 Channel 3 Interrupt/Status Register */
-#define DMA1_3_PERIPHERAL_MAP 0xFFC01CEC /* DMA1 Channel 3 Peripheral Map Register */
-
-#define DMA1_4_CONFIG 0xFFC01D08 /* DMA1 Channel 4 Configuration register */
-#define DMA1_4_NEXT_DESC_PTR 0xFFC01D00 /* DMA1 Channel 4 Next Descripter Ptr Reg */
-#define DMA1_4_START_ADDR 0xFFC01D04 /* DMA1 Channel 4 Start Address */
-#define DMA1_4_X_COUNT 0xFFC01D10 /* DMA1 Channel 4 Inner Loop Count */
-#define DMA1_4_Y_COUNT 0xFFC01D18 /* DMA1 Channel 4 Outer Loop Count */
-#define DMA1_4_X_MODIFY 0xFFC01D14 /* DMA1 Channel 4 Inner Loop Addr Increment */
-#define DMA1_4_Y_MODIFY 0xFFC01D1C /* DMA1 Channel 4 Outer Loop Addr Increment */
-#define DMA1_4_CURR_DESC_PTR 0xFFC01D20 /* DMA1 Channel 4 Current Descriptor Pointer */
-#define DMA1_4_CURR_ADDR 0xFFC01D24 /* DMA1 Channel 4 Current Address Pointer */
-#define DMA1_4_CURR_X_COUNT 0xFFC01D30 /* DMA1 Channel 4 Current Inner Loop Count */
-#define DMA1_4_CURR_Y_COUNT 0xFFC01D38 /* DMA1 Channel 4 Current Outer Loop Count */
-#define DMA1_4_IRQ_STATUS 0xFFC01D28 /* DMA1 Channel 4 Interrupt/Status Register */
-#define DMA1_4_PERIPHERAL_MAP 0xFFC01D2C /* DMA1 Channel 4 Peripheral Map Register */
-
-#define DMA1_5_CONFIG 0xFFC01D48 /* DMA1 Channel 5 Configuration register */
-#define DMA1_5_NEXT_DESC_PTR 0xFFC01D40 /* DMA1 Channel 5 Next Descripter Ptr Reg */
-#define DMA1_5_START_ADDR 0xFFC01D44 /* DMA1 Channel 5 Start Address */
-#define DMA1_5_X_COUNT 0xFFC01D50 /* DMA1 Channel 5 Inner Loop Count */
-#define DMA1_5_Y_COUNT 0xFFC01D58 /* DMA1 Channel 5 Outer Loop Count */
-#define DMA1_5_X_MODIFY 0xFFC01D54 /* DMA1 Channel 5 Inner Loop Addr Increment */
-#define DMA1_5_Y_MODIFY 0xFFC01D5C /* DMA1 Channel 5 Outer Loop Addr Increment */
-#define DMA1_5_CURR_DESC_PTR 0xFFC01D60 /* DMA1 Channel 5 Current Descriptor Pointer */
-#define DMA1_5_CURR_ADDR 0xFFC01D64 /* DMA1 Channel 5 Current Address Pointer */
-#define DMA1_5_CURR_X_COUNT 0xFFC01D70 /* DMA1 Channel 5 Current Inner Loop Count */
-#define DMA1_5_CURR_Y_COUNT 0xFFC01D78 /* DMA1 Channel 5 Current Outer Loop Count */
-#define DMA1_5_IRQ_STATUS 0xFFC01D68 /* DMA1 Channel 5 Interrupt/Status Register */
-#define DMA1_5_PERIPHERAL_MAP 0xFFC01D6C /* DMA1 Channel 5 Peripheral Map Register */
-
-#define DMA1_6_CONFIG 0xFFC01D88 /* DMA1 Channel 6 Configuration register */
-#define DMA1_6_NEXT_DESC_PTR 0xFFC01D80 /* DMA1 Channel 6 Next Descripter Ptr Reg */
-#define DMA1_6_START_ADDR 0xFFC01D84 /* DMA1 Channel 6 Start Address */
-#define DMA1_6_X_COUNT 0xFFC01D90 /* DMA1 Channel 6 Inner Loop Count */
-#define DMA1_6_Y_COUNT 0xFFC01D98 /* DMA1 Channel 6 Outer Loop Count */
-#define DMA1_6_X_MODIFY 0xFFC01D94 /* DMA1 Channel 6 Inner Loop Addr Increment */
-#define DMA1_6_Y_MODIFY 0xFFC01D9C /* DMA1 Channel 6 Outer Loop Addr Increment */
-#define DMA1_6_CURR_DESC_PTR 0xFFC01DA0 /* DMA1 Channel 6 Current Descriptor Pointer */
-#define DMA1_6_CURR_ADDR 0xFFC01DA4 /* DMA1 Channel 6 Current Address Pointer */
-#define DMA1_6_CURR_X_COUNT 0xFFC01DB0 /* DMA1 Channel 6 Current Inner Loop Count */
-#define DMA1_6_CURR_Y_COUNT 0xFFC01DB8 /* DMA1 Channel 6 Current Outer Loop Count */
-#define DMA1_6_IRQ_STATUS 0xFFC01DA8 /* DMA1 Channel 6 Interrupt/Status Register */
-#define DMA1_6_PERIPHERAL_MAP 0xFFC01DAC /* DMA1 Channel 6 Peripheral Map Register */
-
-#define DMA1_7_CONFIG 0xFFC01DC8 /* DMA1 Channel 7 Configuration register */
-#define DMA1_7_NEXT_DESC_PTR 0xFFC01DC0 /* DMA1 Channel 7 Next Descripter Ptr Reg */
-#define DMA1_7_START_ADDR 0xFFC01DC4 /* DMA1 Channel 7 Start Address */
-#define DMA1_7_X_COUNT 0xFFC01DD0 /* DMA1 Channel 7 Inner Loop Count */
-#define DMA1_7_Y_COUNT 0xFFC01DD8 /* DMA1 Channel 7 Outer Loop Count */
-#define DMA1_7_X_MODIFY 0xFFC01DD4 /* DMA1 Channel 7 Inner Loop Addr Increment */
-#define DMA1_7_Y_MODIFY 0xFFC01DDC /* DMA1 Channel 7 Outer Loop Addr Increment */
-#define DMA1_7_CURR_DESC_PTR 0xFFC01DE0 /* DMA1 Channel 7 Current Descriptor Pointer */
-#define DMA1_7_CURR_ADDR 0xFFC01DE4 /* DMA1 Channel 7 Current Address Pointer */
-#define DMA1_7_CURR_X_COUNT 0xFFC01DF0 /* DMA1 Channel 7 Current Inner Loop Count */
-#define DMA1_7_CURR_Y_COUNT 0xFFC01DF8 /* DMA1 Channel 7 Current Outer Loop Count */
-#define DMA1_7_IRQ_STATUS 0xFFC01DE8 /* DMA1 Channel 7 Interrupt/Status Register */
-#define DMA1_7_PERIPHERAL_MAP 0xFFC01DEC /* DMA1 Channel 7 Peripheral Map Register */
-
-#define DMA1_8_CONFIG 0xFFC01E08 /* DMA1 Channel 8 Configuration register */
-#define DMA1_8_NEXT_DESC_PTR 0xFFC01E00 /* DMA1 Channel 8 Next Descripter Ptr Reg */
-#define DMA1_8_START_ADDR 0xFFC01E04 /* DMA1 Channel 8 Start Address */
-#define DMA1_8_X_COUNT 0xFFC01E10 /* DMA1 Channel 8 Inner Loop Count */
-#define DMA1_8_Y_COUNT 0xFFC01E18 /* DMA1 Channel 8 Outer Loop Count */
-#define DMA1_8_X_MODIFY 0xFFC01E14 /* DMA1 Channel 8 Inner Loop Addr Increment */
-#define DMA1_8_Y_MODIFY 0xFFC01E1C /* DMA1 Channel 8 Outer Loop Addr Increment */
-#define DMA1_8_CURR_DESC_PTR 0xFFC01E20 /* DMA1 Channel 8 Current Descriptor Pointer */
-#define DMA1_8_CURR_ADDR 0xFFC01E24 /* DMA1 Channel 8 Current Address Pointer */
-#define DMA1_8_CURR_X_COUNT 0xFFC01E30 /* DMA1 Channel 8 Current Inner Loop Count */
-#define DMA1_8_CURR_Y_COUNT 0xFFC01E38 /* DMA1 Channel 8 Current Outer Loop Count */
-#define DMA1_8_IRQ_STATUS 0xFFC01E28 /* DMA1 Channel 8 Interrupt/Status Register */
-#define DMA1_8_PERIPHERAL_MAP 0xFFC01E2C /* DMA1 Channel 8 Peripheral Map Register */
-
-#define DMA1_9_CONFIG 0xFFC01E48 /* DMA1 Channel 9 Configuration register */
-#define DMA1_9_NEXT_DESC_PTR 0xFFC01E40 /* DMA1 Channel 9 Next Descripter Ptr Reg */
-#define DMA1_9_START_ADDR 0xFFC01E44 /* DMA1 Channel 9 Start Address */
-#define DMA1_9_X_COUNT 0xFFC01E50 /* DMA1 Channel 9 Inner Loop Count */
-#define DMA1_9_Y_COUNT 0xFFC01E58 /* DMA1 Channel 9 Outer Loop Count */
-#define DMA1_9_X_MODIFY 0xFFC01E54 /* DMA1 Channel 9 Inner Loop Addr Increment */
-#define DMA1_9_Y_MODIFY 0xFFC01E5C /* DMA1 Channel 9 Outer Loop Addr Increment */
-#define DMA1_9_CURR_DESC_PTR 0xFFC01E60 /* DMA1 Channel 9 Current Descriptor Pointer */
-#define DMA1_9_CURR_ADDR 0xFFC01E64 /* DMA1 Channel 9 Current Address Pointer */
-#define DMA1_9_CURR_X_COUNT 0xFFC01E70 /* DMA1 Channel 9 Current Inner Loop Count */
-#define DMA1_9_CURR_Y_COUNT 0xFFC01E78 /* DMA1 Channel 9 Current Outer Loop Count */
-#define DMA1_9_IRQ_STATUS 0xFFC01E68 /* DMA1 Channel 9 Interrupt/Status Register */
-#define DMA1_9_PERIPHERAL_MAP 0xFFC01E6C /* DMA1 Channel 9 Peripheral Map Register */
-
-#define DMA1_10_CONFIG 0xFFC01E88 /* DMA1 Channel 10 Configuration register */
-#define DMA1_10_NEXT_DESC_PTR 0xFFC01E80 /* DMA1 Channel 10 Next Descripter Ptr Reg */
-#define DMA1_10_START_ADDR 0xFFC01E84 /* DMA1 Channel 10 Start Address */
-#define DMA1_10_X_COUNT 0xFFC01E90 /* DMA1 Channel 10 Inner Loop Count */
-#define DMA1_10_Y_COUNT 0xFFC01E98 /* DMA1 Channel 10 Outer Loop Count */
-#define DMA1_10_X_MODIFY 0xFFC01E94 /* DMA1 Channel 10 Inner Loop Addr Increment */
-#define DMA1_10_Y_MODIFY 0xFFC01E9C /* DMA1 Channel 10 Outer Loop Addr Increment */
-#define DMA1_10_CURR_DESC_PTR 0xFFC01EA0 /* DMA1 Channel 10 Current Descriptor Pointer */
-#define DMA1_10_CURR_ADDR 0xFFC01EA4 /* DMA1 Channel 10 Current Address Pointer */
-#define DMA1_10_CURR_X_COUNT 0xFFC01EB0 /* DMA1 Channel 10 Current Inner Loop Count */
-#define DMA1_10_CURR_Y_COUNT 0xFFC01EB8 /* DMA1 Channel 10 Current Outer Loop Count */
-#define DMA1_10_IRQ_STATUS 0xFFC01EA8 /* DMA1 Channel 10 Interrupt/Status Register */
-#define DMA1_10_PERIPHERAL_MAP 0xFFC01EAC /* DMA1 Channel 10 Peripheral Map Register */
-
-#define DMA1_11_CONFIG 0xFFC01EC8 /* DMA1 Channel 11 Configuration register */
-#define DMA1_11_NEXT_DESC_PTR 0xFFC01EC0 /* DMA1 Channel 11 Next Descripter Ptr Reg */
-#define DMA1_11_START_ADDR 0xFFC01EC4 /* DMA1 Channel 11 Start Address */
-#define DMA1_11_X_COUNT 0xFFC01ED0 /* DMA1 Channel 11 Inner Loop Count */
-#define DMA1_11_Y_COUNT 0xFFC01ED8 /* DMA1 Channel 11 Outer Loop Count */
-#define DMA1_11_X_MODIFY 0xFFC01ED4 /* DMA1 Channel 11 Inner Loop Addr Increment */
-#define DMA1_11_Y_MODIFY 0xFFC01EDC /* DMA1 Channel 11 Outer Loop Addr Increment */
-#define DMA1_11_CURR_DESC_PTR 0xFFC01EE0 /* DMA1 Channel 11 Current Descriptor Pointer */
-#define DMA1_11_CURR_ADDR 0xFFC01EE4 /* DMA1 Channel 11 Current Address Pointer */
-#define DMA1_11_CURR_X_COUNT 0xFFC01EF0 /* DMA1 Channel 11 Current Inner Loop Count */
-#define DMA1_11_CURR_Y_COUNT 0xFFC01EF8 /* DMA1 Channel 11 Current Outer Loop Count */
-#define DMA1_11_IRQ_STATUS 0xFFC01EE8 /* DMA1 Channel 11 Interrupt/Status Register */
-#define DMA1_11_PERIPHERAL_MAP 0xFFC01EEC /* DMA1 Channel 11 Peripheral Map Register */
-
-/* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) */
-#define MDMA_D0_CONFIG 0xFFC01F08 /*MemDMA1 Stream 0 Destination Configuration */
-#define MDMA_D0_NEXT_DESC_PTR 0xFFC01F00 /*MemDMA1 Stream 0 Destination Next Descriptor Ptr Reg */
-#define MDMA_D0_START_ADDR 0xFFC01F04 /*MemDMA1 Stream 0 Destination Start Address */
-#define MDMA_D0_X_COUNT 0xFFC01F10 /*MemDMA1 Stream 0 Destination Inner-Loop Count */
-#define MDMA_D0_Y_COUNT 0xFFC01F18 /*MemDMA1 Stream 0 Destination Outer-Loop Count */
-#define MDMA_D0_X_MODIFY 0xFFC01F14 /*MemDMA1 Stream 0 Dest Inner-Loop Address-Increment */
-#define MDMA_D0_Y_MODIFY 0xFFC01F1C /*MemDMA1 Stream 0 Dest Outer-Loop Address-Increment */
-#define MDMA_D0_CURR_DESC_PTR 0xFFC01F20 /*MemDMA1 Stream 0 Dest Current Descriptor Ptr reg */
-#define MDMA_D0_CURR_ADDR 0xFFC01F24 /*MemDMA1 Stream 0 Destination Current Address */
-#define MDMA_D0_CURR_X_COUNT 0xFFC01F30 /*MemDMA1 Stream 0 Dest Current Inner-Loop Count */
-#define MDMA_D0_CURR_Y_COUNT 0xFFC01F38 /*MemDMA1 Stream 0 Dest Current Outer-Loop Count */
-#define MDMA_D0_IRQ_STATUS 0xFFC01F28 /*MemDMA1 Stream 0 Destination Interrupt/Status */
-#define MDMA_D0_PERIPHERAL_MAP 0xFFC01F2C /*MemDMA1 Stream 0 Destination Peripheral Map */
-
-#define MDMA_S0_CONFIG 0xFFC01F48 /*MemDMA1 Stream 0 Source Configuration */
-#define MDMA_S0_NEXT_DESC_PTR 0xFFC01F40 /*MemDMA1 Stream 0 Source Next Descriptor Ptr Reg */
-#define MDMA_S0_START_ADDR 0xFFC01F44 /*MemDMA1 Stream 0 Source Start Address */
-#define MDMA_S0_X_COUNT 0xFFC01F50 /*MemDMA1 Stream 0 Source Inner-Loop Count */
-#define MDMA_S0_Y_COUNT 0xFFC01F58 /*MemDMA1 Stream 0 Source Outer-Loop Count */
-#define MDMA_S0_X_MODIFY 0xFFC01F54 /*MemDMA1 Stream 0 Source Inner-Loop Address-Increment */
-#define MDMA_S0_Y_MODIFY 0xFFC01F5C /*MemDMA1 Stream 0 Source Outer-Loop Address-Increment */
-#define MDMA_S0_CURR_DESC_PTR 0xFFC01F60 /*MemDMA1 Stream 0 Source Current Descriptor Ptr reg */
-#define MDMA_S0_CURR_ADDR 0xFFC01F64 /*MemDMA1 Stream 0 Source Current Address */
-#define MDMA_S0_CURR_X_COUNT 0xFFC01F70 /*MemDMA1 Stream 0 Source Current Inner-Loop Count */
-#define MDMA_S0_CURR_Y_COUNT 0xFFC01F78 /*MemDMA1 Stream 0 Source Current Outer-Loop Count */
-#define MDMA_S0_IRQ_STATUS 0xFFC01F68 /*MemDMA1 Stream 0 Source Interrupt/Status */
-#define MDMA_S0_PERIPHERAL_MAP 0xFFC01F6C /*MemDMA1 Stream 0 Source Peripheral Map */
-
-#define MDMA_D1_CONFIG 0xFFC01F88 /*MemDMA1 Stream 1 Destination Configuration */
-#define MDMA_D1_NEXT_DESC_PTR 0xFFC01F80 /*MemDMA1 Stream 1 Destination Next Descriptor Ptr Reg */
-#define MDMA_D1_START_ADDR 0xFFC01F84 /*MemDMA1 Stream 1 Destination Start Address */
-#define MDMA_D1_X_COUNT 0xFFC01F90 /*MemDMA1 Stream 1 Destination Inner-Loop Count */
-#define MDMA_D1_Y_COUNT 0xFFC01F98 /*MemDMA1 Stream 1 Destination Outer-Loop Count */
-#define MDMA_D1_X_MODIFY 0xFFC01F94 /*MemDMA1 Stream 1 Dest Inner-Loop Address-Increment */
-#define MDMA_D1_Y_MODIFY 0xFFC01F9C /*MemDMA1 Stream 1 Dest Outer-Loop Address-Increment */
-#define MDMA_D1_CURR_DESC_PTR 0xFFC01FA0 /*MemDMA1 Stream 1 Dest Current Descriptor Ptr reg */
-#define MDMA_D1_CURR_ADDR 0xFFC01FA4 /*MemDMA1 Stream 1 Dest Current Address */
-#define MDMA_D1_CURR_X_COUNT 0xFFC01FB0 /*MemDMA1 Stream 1 Dest Current Inner-Loop Count */
-#define MDMA_D1_CURR_Y_COUNT 0xFFC01FB8 /*MemDMA1 Stream 1 Dest Current Outer-Loop Count */
-#define MDMA_D1_IRQ_STATUS 0xFFC01FA8 /*MemDMA1 Stream 1 Dest Interrupt/Status */
-#define MDMA_D1_PERIPHERAL_MAP 0xFFC01FAC /*MemDMA1 Stream 1 Dest Peripheral Map */
-
-#define MDMA_S1_CONFIG 0xFFC01FC8 /*MemDMA1 Stream 1 Source Configuration */
-#define MDMA_S1_NEXT_DESC_PTR 0xFFC01FC0 /*MemDMA1 Stream 1 Source Next Descriptor Ptr Reg */
-#define MDMA_S1_START_ADDR 0xFFC01FC4 /*MemDMA1 Stream 1 Source Start Address */
-#define MDMA_S1_X_COUNT 0xFFC01FD0 /*MemDMA1 Stream 1 Source Inner-Loop Count */
-#define MDMA_S1_Y_COUNT 0xFFC01FD8 /*MemDMA1 Stream 1 Source Outer-Loop Count */
-#define MDMA_S1_X_MODIFY 0xFFC01FD4 /*MemDMA1 Stream 1 Source Inner-Loop Address-Increment */
-#define MDMA_S1_Y_MODIFY 0xFFC01FDC /*MemDMA1 Stream 1 Source Outer-Loop Address-Increment */
-#define MDMA_S1_CURR_DESC_PTR 0xFFC01FE0 /*MemDMA1 Stream 1 Source Current Descriptor Ptr reg */
-#define MDMA_S1_CURR_ADDR 0xFFC01FE4 /*MemDMA1 Stream 1 Source Current Address */
-#define MDMA_S1_CURR_X_COUNT 0xFFC01FF0 /*MemDMA1 Stream 1 Source Current Inner-Loop Count */
-#define MDMA_S1_CURR_Y_COUNT 0xFFC01FF8 /*MemDMA1 Stream 1 Source Current Outer-Loop Count */
-#define MDMA_S1_IRQ_STATUS 0xFFC01FE8 /*MemDMA1 Stream 1 Source Interrupt/Status */
-#define MDMA_S1_PERIPHERAL_MAP 0xFFC01FEC /*MemDMA1 Stream 1 Source Peripheral Map */
-
-/* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */
-#define DMA2_0_CONFIG 0xFFC00C08 /* DMA2 Channel 0 Configuration register */
-#define DMA2_0_NEXT_DESC_PTR 0xFFC00C00 /* DMA2 Channel 0 Next Descripter Ptr Reg */
-#define DMA2_0_START_ADDR 0xFFC00C04 /* DMA2 Channel 0 Start Address */
-#define DMA2_0_X_COUNT 0xFFC00C10 /* DMA2 Channel 0 Inner Loop Count */
-#define DMA2_0_Y_COUNT 0xFFC00C18 /* DMA2 Channel 0 Outer Loop Count */
-#define DMA2_0_X_MODIFY 0xFFC00C14 /* DMA2 Channel 0 Inner Loop Addr Increment */
-#define DMA2_0_Y_MODIFY 0xFFC00C1C /* DMA2 Channel 0 Outer Loop Addr Increment */
-#define DMA2_0_CURR_DESC_PTR 0xFFC00C20 /* DMA2 Channel 0 Current Descriptor Pointer */
-#define DMA2_0_CURR_ADDR 0xFFC00C24 /* DMA2 Channel 0 Current Address Pointer */
-#define DMA2_0_CURR_X_COUNT 0xFFC00C30 /* DMA2 Channel 0 Current Inner Loop Count */
-#define DMA2_0_CURR_Y_COUNT 0xFFC00C38 /* DMA2 Channel 0 Current Outer Loop Count */
-#define DMA2_0_IRQ_STATUS 0xFFC00C28 /* DMA2 Channel 0 Interrupt/Status Register */
-#define DMA2_0_PERIPHERAL_MAP 0xFFC00C2C /* DMA2 Channel 0 Peripheral Map Register */
-
-#define DMA2_1_CONFIG 0xFFC00C48 /* DMA2 Channel 1 Configuration register */
-#define DMA2_1_NEXT_DESC_PTR 0xFFC00C40 /* DMA2 Channel 1 Next Descripter Ptr Reg */
-#define DMA2_1_START_ADDR 0xFFC00C44 /* DMA2 Channel 1 Start Address */
-#define DMA2_1_X_COUNT 0xFFC00C50 /* DMA2 Channel 1 Inner Loop Count */
-#define DMA2_1_Y_COUNT 0xFFC00C58 /* DMA2 Channel 1 Outer Loop Count */
-#define DMA2_1_X_MODIFY 0xFFC00C54 /* DMA2 Channel 1 Inner Loop Addr Increment */
-#define DMA2_1_Y_MODIFY 0xFFC00C5C /* DMA2 Channel 1 Outer Loop Addr Increment */
-#define DMA2_1_CURR_DESC_PTR 0xFFC00C60 /* DMA2 Channel 1 Current Descriptor Pointer */
-#define DMA2_1_CURR_ADDR 0xFFC00C64 /* DMA2 Channel 1 Current Address Pointer */
-#define DMA2_1_CURR_X_COUNT 0xFFC00C70 /* DMA2 Channel 1 Current Inner Loop Count */
-#define DMA2_1_CURR_Y_COUNT 0xFFC00C78 /* DMA2 Channel 1 Current Outer Loop Count */
-#define DMA2_1_IRQ_STATUS 0xFFC00C68 /* DMA2 Channel 1 Interrupt/Status Register */
-#define DMA2_1_PERIPHERAL_MAP 0xFFC00C6C /* DMA2 Channel 1 Peripheral Map Register */
-
-#define DMA2_2_CONFIG 0xFFC00C88 /* DMA2 Channel 2 Configuration register */
-#define DMA2_2_NEXT_DESC_PTR 0xFFC00C80 /* DMA2 Channel 2 Next Descripter Ptr Reg */
-#define DMA2_2_START_ADDR 0xFFC00C84 /* DMA2 Channel 2 Start Address */
-#define DMA2_2_X_COUNT 0xFFC00C90 /* DMA2 Channel 2 Inner Loop Count */
-#define DMA2_2_Y_COUNT 0xFFC00C98 /* DMA2 Channel 2 Outer Loop Count */
-#define DMA2_2_X_MODIFY 0xFFC00C94 /* DMA2 Channel 2 Inner Loop Addr Increment */
-#define DMA2_2_Y_MODIFY 0xFFC00C9C /* DMA2 Channel 2 Outer Loop Addr Increment */
-#define DMA2_2_CURR_DESC_PTR 0xFFC00CA0 /* DMA2 Channel 2 Current Descriptor Pointer */
-#define DMA2_2_CURR_ADDR 0xFFC00CA4 /* DMA2 Channel 2 Current Address Pointer */
-#define DMA2_2_CURR_X_COUNT 0xFFC00CB0 /* DMA2 Channel 2 Current Inner Loop Count */
-#define DMA2_2_CURR_Y_COUNT 0xFFC00CB8 /* DMA2 Channel 2 Current Outer Loop Count */
-#define DMA2_2_IRQ_STATUS 0xFFC00CA8 /* DMA2 Channel 2 Interrupt/Status Register */
-#define DMA2_2_PERIPHERAL_MAP 0xFFC00CAC /* DMA2 Channel 2 Peripheral Map Register */
-
-#define DMA2_3_CONFIG 0xFFC00CC8 /* DMA2 Channel 3 Configuration register */
-#define DMA2_3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA2 Channel 3 Next Descripter Ptr Reg */
-#define DMA2_3_START_ADDR 0xFFC00CC4 /* DMA2 Channel 3 Start Address */
-#define DMA2_3_X_COUNT 0xFFC00CD0 /* DMA2 Channel 3 Inner Loop Count */
-#define DMA2_3_Y_COUNT 0xFFC00CD8 /* DMA2 Channel 3 Outer Loop Count */
-#define DMA2_3_X_MODIFY 0xFFC00CD4 /* DMA2 Channel 3 Inner Loop Addr Increment */
-#define DMA2_3_Y_MODIFY 0xFFC00CDC /* DMA2 Channel 3 Outer Loop Addr Increment */
-#define DMA2_3_CURR_DESC_PTR 0xFFC00CE0 /* DMA2 Channel 3 Current Descriptor Pointer */
-#define DMA2_3_CURR_ADDR 0xFFC00CE4 /* DMA2 Channel 3 Current Address Pointer */
-#define DMA2_3_CURR_X_COUNT 0xFFC00CF0 /* DMA2 Channel 3 Current Inner Loop Count */
-#define DMA2_3_CURR_Y_COUNT 0xFFC00CF8 /* DMA2 Channel 3 Current Outer Loop Count */
-#define DMA2_3_IRQ_STATUS 0xFFC00CE8 /* DMA2 Channel 3 Interrupt/Status Register */
-#define DMA2_3_PERIPHERAL_MAP 0xFFC00CEC /* DMA2 Channel 3 Peripheral Map Register */
-
-#define DMA2_4_CONFIG 0xFFC00D08 /* DMA2 Channel 4 Configuration register */
-#define DMA2_4_NEXT_DESC_PTR 0xFFC00D00 /* DMA2 Channel 4 Next Descripter Ptr Reg */
-#define DMA2_4_START_ADDR 0xFFC00D04 /* DMA2 Channel 4 Start Address */
-#define DMA2_4_X_COUNT 0xFFC00D10 /* DMA2 Channel 4 Inner Loop Count */
-#define DMA2_4_Y_COUNT 0xFFC00D18 /* DMA2 Channel 4 Outer Loop Count */
-#define DMA2_4_X_MODIFY 0xFFC00D14 /* DMA2 Channel 4 Inner Loop Addr Increment */
-#define DMA2_4_Y_MODIFY 0xFFC00D1C /* DMA2 Channel 4 Outer Loop Addr Increment */
-#define DMA2_4_CURR_DESC_PTR 0xFFC00D20 /* DMA2 Channel 4 Current Descriptor Pointer */
-#define DMA2_4_CURR_ADDR 0xFFC00D24 /* DMA2 Channel 4 Current Address Pointer */
-#define DMA2_4_CURR_X_COUNT 0xFFC00D30 /* DMA2 Channel 4 Current Inner Loop Count */
-#define DMA2_4_CURR_Y_COUNT 0xFFC00D38 /* DMA2 Channel 4 Current Outer Loop Count */
-#define DMA2_4_IRQ_STATUS 0xFFC00D28 /* DMA2 Channel 4 Interrupt/Status Register */
-#define DMA2_4_PERIPHERAL_MAP 0xFFC00D2C /* DMA2 Channel 4 Peripheral Map Register */
-
-#define DMA2_5_CONFIG 0xFFC00D48 /* DMA2 Channel 5 Configuration register */
-#define DMA2_5_NEXT_DESC_PTR 0xFFC00D40 /* DMA2 Channel 5 Next Descripter Ptr Reg */
-#define DMA2_5_START_ADDR 0xFFC00D44 /* DMA2 Channel 5 Start Address */
-#define DMA2_5_X_COUNT 0xFFC00D50 /* DMA2 Channel 5 Inner Loop Count */
-#define DMA2_5_Y_COUNT 0xFFC00D58 /* DMA2 Channel 5 Outer Loop Count */
-#define DMA2_5_X_MODIFY 0xFFC00D54 /* DMA2 Channel 5 Inner Loop Addr Increment */
-#define DMA2_5_Y_MODIFY 0xFFC00D5C /* DMA2 Channel 5 Outer Loop Addr Increment */
-#define DMA2_5_CURR_DESC_PTR 0xFFC00D60 /* DMA2 Channel 5 Current Descriptor Pointer */
-#define DMA2_5_CURR_ADDR 0xFFC00D64 /* DMA2 Channel 5 Current Address Pointer */
-#define DMA2_5_CURR_X_COUNT 0xFFC00D70 /* DMA2 Channel 5 Current Inner Loop Count */
-#define DMA2_5_CURR_Y_COUNT 0xFFC00D78 /* DMA2 Channel 5 Current Outer Loop Count */
-#define DMA2_5_IRQ_STATUS 0xFFC00D68 /* DMA2 Channel 5 Interrupt/Status Register */
-#define DMA2_5_PERIPHERAL_MAP 0xFFC00D6C /* DMA2 Channel 5 Peripheral Map Register */
-
-#define DMA2_6_CONFIG 0xFFC00D88 /* DMA2 Channel 6 Configuration register */
-#define DMA2_6_NEXT_DESC_PTR 0xFFC00D80 /* DMA2 Channel 6 Next Descripter Ptr Reg */
-#define DMA2_6_START_ADDR 0xFFC00D84 /* DMA2 Channel 6 Start Address */
-#define DMA2_6_X_COUNT 0xFFC00D90 /* DMA2 Channel 6 Inner Loop Count */
-#define DMA2_6_Y_COUNT 0xFFC00D98 /* DMA2 Channel 6 Outer Loop Count */
-#define DMA2_6_X_MODIFY 0xFFC00D94 /* DMA2 Channel 6 Inner Loop Addr Increment */
-#define DMA2_6_Y_MODIFY 0xFFC00D9C /* DMA2 Channel 6 Outer Loop Addr Increment */
-#define DMA2_6_CURR_DESC_PTR 0xFFC00DA0 /* DMA2 Channel 6 Current Descriptor Pointer */
-#define DMA2_6_CURR_ADDR 0xFFC00DA4 /* DMA2 Channel 6 Current Address Pointer */
-#define DMA2_6_CURR_X_COUNT 0xFFC00DB0 /* DMA2 Channel 6 Current Inner Loop Count */
-#define DMA2_6_CURR_Y_COUNT 0xFFC00DB8 /* DMA2 Channel 6 Current Outer Loop Count */
-#define DMA2_6_IRQ_STATUS 0xFFC00DA8 /* DMA2 Channel 6 Interrupt/Status Register */
-#define DMA2_6_PERIPHERAL_MAP 0xFFC00DAC /* DMA2 Channel 6 Peripheral Map Register */
-
-#define DMA2_7_CONFIG 0xFFC00DC8 /* DMA2 Channel 7 Configuration register */
-#define DMA2_7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA2 Channel 7 Next Descripter Ptr Reg */
-#define DMA2_7_START_ADDR 0xFFC00DC4 /* DMA2 Channel 7 Start Address */
-#define DMA2_7_X_COUNT 0xFFC00DD0 /* DMA2 Channel 7 Inner Loop Count */
-#define DMA2_7_Y_COUNT 0xFFC00DD8 /* DMA2 Channel 7 Outer Loop Count */
-#define DMA2_7_X_MODIFY 0xFFC00DD4 /* DMA2 Channel 7 Inner Loop Addr Increment */
-#define DMA2_7_Y_MODIFY 0xFFC00DDC /* DMA2 Channel 7 Outer Loop Addr Increment */
-#define DMA2_7_CURR_DESC_PTR 0xFFC00DE0 /* DMA2 Channel 7 Current Descriptor Pointer */
-#define DMA2_7_CURR_ADDR 0xFFC00DE4 /* DMA2 Channel 7 Current Address Pointer */
-#define DMA2_7_CURR_X_COUNT 0xFFC00DF0 /* DMA2 Channel 7 Current Inner Loop Count */
-#define DMA2_7_CURR_Y_COUNT 0xFFC00DF8 /* DMA2 Channel 7 Current Outer Loop Count */
-#define DMA2_7_IRQ_STATUS 0xFFC00DE8 /* DMA2 Channel 7 Interrupt/Status Register */
-#define DMA2_7_PERIPHERAL_MAP 0xFFC00DEC /* DMA2 Channel 7 Peripheral Map Register */
-
-#define DMA2_8_CONFIG 0xFFC00E08 /* DMA2 Channel 8 Configuration register */
-#define DMA2_8_NEXT_DESC_PTR 0xFFC00E00 /* DMA2 Channel 8 Next Descripter Ptr Reg */
-#define DMA2_8_START_ADDR 0xFFC00E04 /* DMA2 Channel 8 Start Address */
-#define DMA2_8_X_COUNT 0xFFC00E10 /* DMA2 Channel 8 Inner Loop Count */
-#define DMA2_8_Y_COUNT 0xFFC00E18 /* DMA2 Channel 8 Outer Loop Count */
-#define DMA2_8_X_MODIFY 0xFFC00E14 /* DMA2 Channel 8 Inner Loop Addr Increment */
-#define DMA2_8_Y_MODIFY 0xFFC00E1C /* DMA2 Channel 8 Outer Loop Addr Increment */
-#define DMA2_8_CURR_DESC_PTR 0xFFC00E20 /* DMA2 Channel 8 Current Descriptor Pointer */
-#define DMA2_8_CURR_ADDR 0xFFC00E24 /* DMA2 Channel 8 Current Address Pointer */
-#define DMA2_8_CURR_X_COUNT 0xFFC00E30 /* DMA2 Channel 8 Current Inner Loop Count */
-#define DMA2_8_CURR_Y_COUNT 0xFFC00E38 /* DMA2 Channel 8 Current Outer Loop Count */
-#define DMA2_8_IRQ_STATUS 0xFFC00E28 /* DMA2 Channel 8 Interrupt/Status Register */
-#define DMA2_8_PERIPHERAL_MAP 0xFFC00E2C /* DMA2 Channel 8 Peripheral Map Register */
-
-#define DMA2_9_CONFIG 0xFFC00E48 /* DMA2 Channel 9 Configuration register */
-#define DMA2_9_NEXT_DESC_PTR 0xFFC00E40 /* DMA2 Channel 9 Next Descripter Ptr Reg */
-#define DMA2_9_START_ADDR 0xFFC00E44 /* DMA2 Channel 9 Start Address */
-#define DMA2_9_X_COUNT 0xFFC00E50 /* DMA2 Channel 9 Inner Loop Count */
-#define DMA2_9_Y_COUNT 0xFFC00E58 /* DMA2 Channel 9 Outer Loop Count */
-#define DMA2_9_X_MODIFY 0xFFC00E54 /* DMA2 Channel 9 Inner Loop Addr Increment */
-#define DMA2_9_Y_MODIFY 0xFFC00E5C /* DMA2 Channel 9 Outer Loop Addr Increment */
-#define DMA2_9_CURR_DESC_PTR 0xFFC00E60 /* DMA2 Channel 9 Current Descriptor Pointer */
-#define DMA2_9_CURR_ADDR 0xFFC00E64 /* DMA2 Channel 9 Current Address Pointer */
-#define DMA2_9_CURR_X_COUNT 0xFFC00E70 /* DMA2 Channel 9 Current Inner Loop Count */
-#define DMA2_9_CURR_Y_COUNT 0xFFC00E78 /* DMA2 Channel 9 Current Outer Loop Count */
-#define DMA2_9_IRQ_STATUS 0xFFC00E68 /* DMA2 Channel 9 Interrupt/Status Register */
-#define DMA2_9_PERIPHERAL_MAP 0xFFC00E6C /* DMA2 Channel 9 Peripheral Map Register */
-
-#define DMA2_10_CONFIG 0xFFC00E88 /* DMA2 Channel 10 Configuration register */
-#define DMA2_10_NEXT_DESC_PTR 0xFFC00E80 /* DMA2 Channel 10 Next Descripter Ptr Reg */
-#define DMA2_10_START_ADDR 0xFFC00E84 /* DMA2 Channel 10 Start Address */
-#define DMA2_10_X_COUNT 0xFFC00E90 /* DMA2 Channel 10 Inner Loop Count */
-#define DMA2_10_Y_COUNT 0xFFC00E98 /* DMA2 Channel 10 Outer Loop Count */
-#define DMA2_10_X_MODIFY 0xFFC00E94 /* DMA2 Channel 10 Inner Loop Addr Increment */
-#define DMA2_10_Y_MODIFY 0xFFC00E9C /* DMA2 Channel 10 Outer Loop Addr Increment */
-#define DMA2_10_CURR_DESC_PTR 0xFFC00EA0 /* DMA2 Channel 10 Current Descriptor Pointer */
-#define DMA2_10_CURR_ADDR 0xFFC00EA4 /* DMA2 Channel 10 Current Address Pointer */
-#define DMA2_10_CURR_X_COUNT 0xFFC00EB0 /* DMA2 Channel 10 Current Inner Loop Count */
-#define DMA2_10_CURR_Y_COUNT 0xFFC00EB8 /* DMA2 Channel 10 Current Outer Loop Count */
-#define DMA2_10_IRQ_STATUS 0xFFC00EA8 /* DMA2 Channel 10 Interrupt/Status Register */
-#define DMA2_10_PERIPHERAL_MAP 0xFFC00EAC /* DMA2 Channel 10 Peripheral Map Register */
-
-#define DMA2_11_CONFIG 0xFFC00EC8 /* DMA2 Channel 11 Configuration register */
-#define DMA2_11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA2 Channel 11 Next Descripter Ptr Reg */
-#define DMA2_11_START_ADDR 0xFFC00EC4 /* DMA2 Channel 11 Start Address */
-#define DMA2_11_X_COUNT 0xFFC00ED0 /* DMA2 Channel 11 Inner Loop Count */
-#define DMA2_11_Y_COUNT 0xFFC00ED8 /* DMA2 Channel 11 Outer Loop Count */
-#define DMA2_11_X_MODIFY 0xFFC00ED4 /* DMA2 Channel 11 Inner Loop Addr Increment */
-#define DMA2_11_Y_MODIFY 0xFFC00EDC /* DMA2 Channel 11 Outer Loop Addr Increment */
-#define DMA2_11_CURR_DESC_PTR 0xFFC00EE0 /* DMA2 Channel 11 Current Descriptor Pointer */
-#define DMA2_11_CURR_ADDR 0xFFC00EE4 /* DMA2 Channel 11 Current Address Pointer */
-#define DMA2_11_CURR_X_COUNT 0xFFC00EF0 /* DMA2 Channel 11 Current Inner Loop Count */
-#define DMA2_11_CURR_Y_COUNT 0xFFC00EF8 /* DMA2 Channel 11 Current Outer Loop Count */
-#define DMA2_11_IRQ_STATUS 0xFFC00EE8 /* DMA2 Channel 11 Interrupt/Status Register */
-#define DMA2_11_PERIPHERAL_MAP 0xFFC00EEC /* DMA2 Channel 11 Peripheral Map Register */
-
-/* Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) */
-#define MDMA_D2_CONFIG 0xFFC00F08 /*MemDMA2 Stream 0 Destination Configuration register */
-#define MDMA_D2_NEXT_DESC_PTR 0xFFC00F00 /*MemDMA2 Stream 0 Destination Next Descriptor Ptr Reg */
-#define MDMA_D2_START_ADDR 0xFFC00F04 /*MemDMA2 Stream 0 Destination Start Address */
-#define MDMA_D2_X_COUNT 0xFFC00F10 /*MemDMA2 Stream 0 Dest Inner-Loop Count register */
-#define MDMA_D2_Y_COUNT 0xFFC00F18 /*MemDMA2 Stream 0 Dest Outer-Loop Count register */
-#define MDMA_D2_X_MODIFY 0xFFC00F14 /*MemDMA2 Stream 0 Dest Inner-Loop Address-Increment */
-#define MDMA_D2_Y_MODIFY 0xFFC00F1C /*MemDMA2 Stream 0 Dest Outer-Loop Address-Increment */
-#define MDMA_D2_CURR_DESC_PTR 0xFFC00F20 /*MemDMA2 Stream 0 Dest Current Descriptor Ptr reg */
-#define MDMA_D2_CURR_ADDR 0xFFC00F24 /*MemDMA2 Stream 0 Destination Current Address */
-#define MDMA_D2_CURR_X_COUNT 0xFFC00F30 /*MemDMA2 Stream 0 Dest Current Inner-Loop Count reg */
-#define MDMA_D2_CURR_Y_COUNT 0xFFC00F38 /*MemDMA2 Stream 0 Dest Current Outer-Loop Count reg */
-#define MDMA_D2_IRQ_STATUS 0xFFC00F28 /*MemDMA2 Stream 0 Dest Interrupt/Status Register */
-#define MDMA_D2_PERIPHERAL_MAP 0xFFC00F2C /*MemDMA2 Stream 0 Destination Peripheral Map register */
-
-#define MDMA_S2_CONFIG 0xFFC00F48 /*MemDMA2 Stream 0 Source Configuration register */
-#define MDMA_S2_NEXT_DESC_PTR 0xFFC00F40 /*MemDMA2 Stream 0 Source Next Descriptor Ptr Reg */
-#define MDMA_S2_START_ADDR 0xFFC00F44 /*MemDMA2 Stream 0 Source Start Address */
-#define MDMA_S2_X_COUNT 0xFFC00F50 /*MemDMA2 Stream 0 Source Inner-Loop Count register */
-#define MDMA_S2_Y_COUNT 0xFFC00F58 /*MemDMA2 Stream 0 Source Outer-Loop Count register */
-#define MDMA_S2_X_MODIFY 0xFFC00F54 /*MemDMA2 Stream 0 Src Inner-Loop Addr-Increment reg */
-#define MDMA_S2_Y_MODIFY 0xFFC00F5C /*MemDMA2 Stream 0 Src Outer-Loop Addr-Increment reg */
-#define MDMA_S2_CURR_DESC_PTR 0xFFC00F60 /*MemDMA2 Stream 0 Source Current Descriptor Ptr reg */
-#define MDMA_S2_CURR_ADDR 0xFFC00F64 /*MemDMA2 Stream 0 Source Current Address */
-#define MDMA_S2_CURR_X_COUNT 0xFFC00F70 /*MemDMA2 Stream 0 Src Current Inner-Loop Count reg */
-#define MDMA_S2_CURR_Y_COUNT 0xFFC00F78 /*MemDMA2 Stream 0 Src Current Outer-Loop Count reg */
-#define MDMA_S2_IRQ_STATUS 0xFFC00F68 /*MemDMA2 Stream 0 Source Interrupt/Status Register */
-#define MDMA_S2_PERIPHERAL_MAP 0xFFC00F6C /*MemDMA2 Stream 0 Source Peripheral Map register */
-
-#define MDMA_D3_CONFIG 0xFFC00F88 /*MemDMA2 Stream 1 Destination Configuration register */
-#define MDMA_D3_NEXT_DESC_PTR 0xFFC00F80 /*MemDMA2 Stream 1 Destination Next Descriptor Ptr Reg */
-#define MDMA_D3_START_ADDR 0xFFC00F84 /*MemDMA2 Stream 1 Destination Start Address */
-#define MDMA_D3_X_COUNT 0xFFC00F90 /*MemDMA2 Stream 1 Dest Inner-Loop Count register */
-#define MDMA_D3_Y_COUNT 0xFFC00F98 /*MemDMA2 Stream 1 Dest Outer-Loop Count register */
-#define MDMA_D3_X_MODIFY 0xFFC00F94 /*MemDMA2 Stream 1 Dest Inner-Loop Address-Increment */
-#define MDMA_D3_Y_MODIFY 0xFFC00F9C /*MemDMA2 Stream 1 Dest Outer-Loop Address-Increment */
-#define MDMA_D3_CURR_DESC_PTR 0xFFC00FA0 /*MemDMA2 Stream 1 Destination Current Descriptor Ptr */
-#define MDMA_D3_CURR_ADDR 0xFFC00FA4 /*MemDMA2 Stream 1 Destination Current Address reg */
-#define MDMA_D3_CURR_X_COUNT 0xFFC00FB0 /*MemDMA2 Stream 1 Dest Current Inner-Loop Count reg */
-#define MDMA_D3_CURR_Y_COUNT 0xFFC00FB8 /*MemDMA2 Stream 1 Dest Current Outer-Loop Count reg */
-#define MDMA_D3_IRQ_STATUS 0xFFC00FA8 /*MemDMA2 Stream 1 Destination Interrupt/Status Reg */
-#define MDMA_D3_PERIPHERAL_MAP 0xFFC00FAC /*MemDMA2 Stream 1 Destination Peripheral Map register */
-
-#define MDMA_S3_CONFIG 0xFFC00FC8 /*MemDMA2 Stream 1 Source Configuration register */
-#define MDMA_S3_NEXT_DESC_PTR 0xFFC00FC0 /*MemDMA2 Stream 1 Source Next Descriptor Ptr Reg */
-#define MDMA_S3_START_ADDR 0xFFC00FC4 /*MemDMA2 Stream 1 Source Start Address */
-#define MDMA_S3_X_COUNT 0xFFC00FD0 /*MemDMA2 Stream 1 Source Inner-Loop Count register */
-#define MDMA_S3_Y_COUNT 0xFFC00FD8 /*MemDMA2 Stream 1 Source Outer-Loop Count register */
-#define MDMA_S3_X_MODIFY 0xFFC00FD4 /*MemDMA2 Stream 1 Src Inner-Loop Address-Increment */
-#define MDMA_S3_Y_MODIFY 0xFFC00FDC /*MemDMA2 Stream 1 Source Outer-Loop Address-Increment */
-#define MDMA_S3_CURR_DESC_PTR 0xFFC00FE0 /*MemDMA2 Stream 1 Source Current Descriptor Ptr reg */
-#define MDMA_S3_CURR_ADDR 0xFFC00FE4 /*MemDMA2 Stream 1 Source Current Address */
-#define MDMA_S3_CURR_X_COUNT 0xFFC00FF0 /*MemDMA2 Stream 1 Source Current Inner-Loop Count */
-#define MDMA_S3_CURR_Y_COUNT 0xFFC00FF8 /*MemDMA2 Stream 1 Source Current Outer-Loop Count */
-#define MDMA_S3_IRQ_STATUS 0xFFC00FE8 /*MemDMA2 Stream 1 Source Interrupt/Status Register */
-#define MDMA_S3_PERIPHERAL_MAP 0xFFC00FEC /*MemDMA2 Stream 1 Source Peripheral Map register */
-
-/* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */
-#define IMDMA_D0_CONFIG 0xFFC01808 /*IMDMA Stream 0 Destination Configuration */
-#define IMDMA_D0_NEXT_DESC_PTR 0xFFC01800 /*IMDMA Stream 0 Destination Next Descriptor Ptr Reg */
-#define IMDMA_D0_START_ADDR 0xFFC01804 /*IMDMA Stream 0 Destination Start Address */
-#define IMDMA_D0_X_COUNT 0xFFC01810 /*IMDMA Stream 0 Destination Inner-Loop Count */
-#define IMDMA_D0_Y_COUNT 0xFFC01818 /*IMDMA Stream 0 Destination Outer-Loop Count */
-#define IMDMA_D0_X_MODIFY 0xFFC01814 /*IMDMA Stream 0 Dest Inner-Loop Address-Increment */
-#define IMDMA_D0_Y_MODIFY 0xFFC0181C /*IMDMA Stream 0 Dest Outer-Loop Address-Increment */
-#define IMDMA_D0_CURR_DESC_PTR 0xFFC01820 /*IMDMA Stream 0 Destination Current Descriptor Ptr */
-#define IMDMA_D0_CURR_ADDR 0xFFC01824 /*IMDMA Stream 0 Destination Current Address */
-#define IMDMA_D0_CURR_X_COUNT 0xFFC01830 /*IMDMA Stream 0 Destination Current Inner-Loop Count */
-#define IMDMA_D0_CURR_Y_COUNT 0xFFC01838 /*IMDMA Stream 0 Destination Current Outer-Loop Count */
-#define IMDMA_D0_IRQ_STATUS 0xFFC01828 /*IMDMA Stream 0 Destination Interrupt/Status */
-
-#define IMDMA_S0_CONFIG 0xFFC01848 /*IMDMA Stream 0 Source Configuration */
-#define IMDMA_S0_NEXT_DESC_PTR 0xFFC01840 /*IMDMA Stream 0 Source Next Descriptor Ptr Reg */
-#define IMDMA_S0_START_ADDR 0xFFC01844 /*IMDMA Stream 0 Source Start Address */
-#define IMDMA_S0_X_COUNT 0xFFC01850 /*IMDMA Stream 0 Source Inner-Loop Count */
-#define IMDMA_S0_Y_COUNT 0xFFC01858 /*IMDMA Stream 0 Source Outer-Loop Count */
-#define IMDMA_S0_X_MODIFY 0xFFC01854 /*IMDMA Stream 0 Source Inner-Loop Address-Increment */
-#define IMDMA_S0_Y_MODIFY 0xFFC0185C /*IMDMA Stream 0 Source Outer-Loop Address-Increment */
-#define IMDMA_S0_CURR_DESC_PTR 0xFFC01860 /*IMDMA Stream 0 Source Current Descriptor Ptr reg */
-#define IMDMA_S0_CURR_ADDR 0xFFC01864 /*IMDMA Stream 0 Source Current Address */
-#define IMDMA_S0_CURR_X_COUNT 0xFFC01870 /*IMDMA Stream 0 Source Current Inner-Loop Count */
-#define IMDMA_S0_CURR_Y_COUNT 0xFFC01878 /*IMDMA Stream 0 Source Current Outer-Loop Count */
-#define IMDMA_S0_IRQ_STATUS 0xFFC01868 /*IMDMA Stream 0 Source Interrupt/Status */
-
-#define IMDMA_D1_CONFIG 0xFFC01888 /*IMDMA Stream 1 Destination Configuration */
-#define IMDMA_D1_NEXT_DESC_PTR 0xFFC01880 /*IMDMA Stream 1 Destination Next Descriptor Ptr Reg */
-#define IMDMA_D1_START_ADDR 0xFFC01884 /*IMDMA Stream 1 Destination Start Address */
-#define IMDMA_D1_X_COUNT 0xFFC01890 /*IMDMA Stream 1 Destination Inner-Loop Count */
-#define IMDMA_D1_Y_COUNT 0xFFC01898 /*IMDMA Stream 1 Destination Outer-Loop Count */
-#define IMDMA_D1_X_MODIFY 0xFFC01894 /*IMDMA Stream 1 Dest Inner-Loop Address-Increment */
-#define IMDMA_D1_Y_MODIFY 0xFFC0189C /*IMDMA Stream 1 Dest Outer-Loop Address-Increment */
-#define IMDMA_D1_CURR_DESC_PTR 0xFFC018A0 /*IMDMA Stream 1 Destination Current Descriptor Ptr */
-#define IMDMA_D1_CURR_ADDR 0xFFC018A4 /*IMDMA Stream 1 Destination Current Address */
-#define IMDMA_D1_CURR_X_COUNT 0xFFC018B0 /*IMDMA Stream 1 Destination Current Inner-Loop Count */
-#define IMDMA_D1_CURR_Y_COUNT 0xFFC018B8 /*IMDMA Stream 1 Destination Current Outer-Loop Count */
-#define IMDMA_D1_IRQ_STATUS 0xFFC018A8 /*IMDMA Stream 1 Destination Interrupt/Status */
-
-#define IMDMA_S1_CONFIG 0xFFC018C8 /*IMDMA Stream 1 Source Configuration */
-#define IMDMA_S1_NEXT_DESC_PTR 0xFFC018C0 /*IMDMA Stream 1 Source Next Descriptor Ptr Reg */
-#define IMDMA_S1_START_ADDR 0xFFC018C4 /*IMDMA Stream 1 Source Start Address */
-#define IMDMA_S1_X_COUNT 0xFFC018D0 /*IMDMA Stream 1 Source Inner-Loop Count */
-#define IMDMA_S1_Y_COUNT 0xFFC018D8 /*IMDMA Stream 1 Source Outer-Loop Count */
-#define IMDMA_S1_X_MODIFY 0xFFC018D4 /*IMDMA Stream 1 Source Inner-Loop Address-Increment */
-#define IMDMA_S1_Y_MODIFY 0xFFC018DC /*IMDMA Stream 1 Source Outer-Loop Address-Increment */
-#define IMDMA_S1_CURR_DESC_PTR 0xFFC018E0 /*IMDMA Stream 1 Source Current Descriptor Ptr reg */
-#define IMDMA_S1_CURR_ADDR 0xFFC018E4 /*IMDMA Stream 1 Source Current Address */
-#define IMDMA_S1_CURR_X_COUNT 0xFFC018F0 /*IMDMA Stream 1 Source Current Inner-Loop Count */
-#define IMDMA_S1_CURR_Y_COUNT 0xFFC018F8 /*IMDMA Stream 1 Source Current Outer-Loop Count */
-#define IMDMA_S1_IRQ_STATUS 0xFFC018E8 /*IMDMA Stream 1 Source Interrupt/Status */
-
-/*********************************************************************************** */
-/* System MMR Register Bits */
-/******************************************************************************* */
-
-/* CHIPID Masks */
-#define CHIPID_VERSION 0xF0000000
-#define CHIPID_FAMILY 0x0FFFF000
-#define CHIPID_MANUFACTURE 0x00000FFE
-
-/* SICA_SYSCR Masks */
-#define COREB_SRAM_INIT 0x0020
-
-/* SWRST Mask */
-#define SYSTEM_RESET 0x0007 /* Initiates a system software reset */
-#define DOUBLE_FAULT_A 0x0008 /* Core A Double Fault Causes Reset */
-#define DOUBLE_FAULT_B 0x0010 /* Core B Double Fault Causes Reset */
-#define SWRST_DBL_FAULT_A 0x0800 /* SWRST Core A Double Fault */
-#define SWRST_DBL_FAULT_B 0x1000 /* SWRST Core B Double Fault */
-#define SWRST_WDT_B 0x2000 /* SWRST Watchdog B */
-#define SWRST_WDT_A 0x4000 /* SWRST Watchdog A */
-#define SWRST_OCCURRED 0x8000 /* SWRST Status */
-
-/* ************* SYSTEM INTERRUPT CONTROLLER MASKS ***************** */
-
-/* SICu_IARv Masks */
-/* u = A or B */
-/* v = 0 to 7 */
-/* w = 0 or 1 */
-
-/* Per_number = 0 to 63 */
-/* IVG_number = 7 to 15 */
-#define Peripheral_IVG(Per_number, IVG_number) \
- ((IVG_number) - 7) << (((Per_number) % 8) * 4) /* Peripheral #Per_number assigned IVG #IVG_number */
- /* Usage: r0.l = lo(Peripheral_IVG(62, 10)); */
- /* r0.h = hi(Peripheral_IVG(62, 10)); */
-
-/* SICx_IMASKw Masks */
-/* masks are 32 bit wide, so two writes reguired for "64 bit" wide registers */
-#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
-#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
-#define SIC_MASK(x) (1 << (x)) /* Mask Peripheral #x interrupt */
-#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */
-
-/* SIC_IWR Masks */
-#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
-#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
-/* x = pos 0 to 31, for 32-63 use value-32 */
-#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */
-#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */
-
-/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */
-
-/* PPI_CONTROL Masks */
-#define PORT_EN 0x00000001 /* PPI Port Enable */
-#define PORT_DIR 0x00000002 /* PPI Port Direction */
-#define XFR_TYPE 0x0000000C /* PPI Transfer Type */
-#define PORT_CFG 0x00000030 /* PPI Port Configuration */
-#define FLD_SEL 0x00000040 /* PPI Active Field Select */
-#define PACK_EN 0x00000080 /* PPI Packing Mode */
-#define DMA32 0x00000100 /* PPI 32-bit DMA Enable */
-#define SKIP_EN 0x00000200 /* PPI Skip Element Enable */
-#define SKIP_EO 0x00000400 /* PPI Skip Even/Odd Elements */
-#define DLENGTH 0x00003800 /* PPI Data Length */
-#define DLEN_8 0x0 /* PPI Data Length mask for DLEN=8 */
-#define DLEN(x) (((x-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */
-#define DLEN_10 0x00000800 /* Data Length = 10 Bits */
-#define DLEN_11 0x00001000 /* Data Length = 11 Bits */
-#define DLEN_12 0x00001800 /* Data Length = 12 Bits */
-#define DLEN_13 0x00002000 /* Data Length = 13 Bits */
-#define DLEN_14 0x00002800 /* Data Length = 14 Bits */
-#define DLEN_15 0x00003000 /* Data Length = 15 Bits */
-#define DLEN_16 0x00003800 /* Data Length = 16 Bits */
-#define POL 0x0000C000 /* PPI Signal Polarities */
-#define POLC 0x4000 /* PPI Clock Polarity */
-#define POLS 0x8000 /* PPI Frame Sync Polarity */
-
-/* PPI_STATUS Masks */
-#define FLD 0x00000400 /* Field Indicator */
-#define FT_ERR 0x00000800 /* Frame Track Error */
-#define OVR 0x00001000 /* FIFO Overflow Error */
-#define UNDR 0x00002000 /* FIFO Underrun Error */
-#define ERR_DET 0x00004000 /* Error Detected Indicator */
-#define ERR_NCOR 0x00008000 /* Error Not Corrected Indicator */
-
-/* ********** DMA CONTROLLER MASKS *********************8 */
-
-/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP, IMDMA_yy_PERIPHERAL_MAP Masks */
-
-#define CTYPE 0x00000040 /* DMA Channel Type Indicator */
-#define CTYPE_P 6 /* DMA Channel Type Indicator BIT POSITION */
-#define PCAP8 0x00000080 /* DMA 8-bit Operation Indicator */
-#define PCAP16 0x00000100 /* DMA 16-bit Operation Indicator */
-#define PCAP32 0x00000200 /* DMA 32-bit Operation Indicator */
-#define PCAPWR 0x00000400 /* DMA Write Operation Indicator */
-#define PCAPRD 0x00000800 /* DMA Read Operation Indicator */
-#define PMAP 0x00007000 /* DMA Peripheral Map Field */
-
-/* ************* GENERAL PURPOSE TIMER MASKS ******************** */
-
-/* PWM Timer bit definitions */
-
-/* TIMER_ENABLE Register */
-#define TIMEN0 0x0001
-#define TIMEN1 0x0002
-#define TIMEN2 0x0004
-#define TIMEN3 0x0008
-#define TIMEN4 0x0010
-#define TIMEN5 0x0020
-#define TIMEN6 0x0040
-#define TIMEN7 0x0080
-#define TIMEN8 0x0001
-#define TIMEN9 0x0002
-#define TIMEN10 0x0004
-#define TIMEN11 0x0008
-
-#define TIMEN0_P 0x00
-#define TIMEN1_P 0x01
-#define TIMEN2_P 0x02
-#define TIMEN3_P 0x03
-#define TIMEN4_P 0x04
-#define TIMEN5_P 0x05
-#define TIMEN6_P 0x06
-#define TIMEN7_P 0x07
-#define TIMEN8_P 0x00
-#define TIMEN9_P 0x01
-#define TIMEN10_P 0x02
-#define TIMEN11_P 0x03
-
-/* TIMER_DISABLE Register */
-#define TIMDIS0 0x0001
-#define TIMDIS1 0x0002
-#define TIMDIS2 0x0004
-#define TIMDIS3 0x0008
-#define TIMDIS4 0x0010
-#define TIMDIS5 0x0020
-#define TIMDIS6 0x0040
-#define TIMDIS7 0x0080
-#define TIMDIS8 0x0001
-#define TIMDIS9 0x0002
-#define TIMDIS10 0x0004
-#define TIMDIS11 0x0008
-
-#define TIMDIS0_P 0x00
-#define TIMDIS1_P 0x01
-#define TIMDIS2_P 0x02
-#define TIMDIS3_P 0x03
-#define TIMDIS4_P 0x04
-#define TIMDIS5_P 0x05
-#define TIMDIS6_P 0x06
-#define TIMDIS7_P 0x07
-#define TIMDIS8_P 0x00
-#define TIMDIS9_P 0x01
-#define TIMDIS10_P 0x02
-#define TIMDIS11_P 0x03
-
-/* TIMER_STATUS Register */
-#define TIMIL0 0x00000001
-#define TIMIL1 0x00000002
-#define TIMIL2 0x00000004
-#define TIMIL3 0x00000008
-#define TIMIL4 0x00010000
-#define TIMIL5 0x00020000
-#define TIMIL6 0x00040000
-#define TIMIL7 0x00080000
-#define TIMIL8 0x0001
-#define TIMIL9 0x0002
-#define TIMIL10 0x0004
-#define TIMIL11 0x0008
-#define TOVF_ERR0 0x00000010
-#define TOVF_ERR1 0x00000020
-#define TOVF_ERR2 0x00000040
-#define TOVF_ERR3 0x00000080
-#define TOVF_ERR4 0x00100000
-#define TOVF_ERR5 0x00200000
-#define TOVF_ERR6 0x00400000
-#define TOVF_ERR7 0x00800000
-#define TOVF_ERR8 0x0010
-#define TOVF_ERR9 0x0020
-#define TOVF_ERR10 0x0040
-#define TOVF_ERR11 0x0080
-#define TRUN0 0x00001000
-#define TRUN1 0x00002000
-#define TRUN2 0x00004000
-#define TRUN3 0x00008000
-#define TRUN4 0x10000000
-#define TRUN5 0x20000000
-#define TRUN6 0x40000000
-#define TRUN7 0x80000000
-#define TRUN8 0x1000
-#define TRUN9 0x2000
-#define TRUN10 0x4000
-#define TRUN11 0x8000
-
-#define TIMIL0_P 0x00
-#define TIMIL1_P 0x01
-#define TIMIL2_P 0x02
-#define TIMIL3_P 0x03
-#define TIMIL4_P 0x10
-#define TIMIL5_P 0x11
-#define TIMIL6_P 0x12
-#define TIMIL7_P 0x13
-#define TIMIL8_P 0x00
-#define TIMIL9_P 0x01
-#define TIMIL10_P 0x02
-#define TIMIL11_P 0x03
-#define TOVF_ERR0_P 0x04
-#define TOVF_ERR1_P 0x05
-#define TOVF_ERR2_P 0x06
-#define TOVF_ERR3_P 0x07
-#define TOVF_ERR4_P 0x14
-#define TOVF_ERR5_P 0x15
-#define TOVF_ERR6_P 0x16
-#define TOVF_ERR7_P 0x17
-#define TOVF_ERR8_P 0x04
-#define TOVF_ERR9_P 0x05
-#define TOVF_ERR10_P 0x06
-#define TOVF_ERR11_P 0x07
-#define TRUN0_P 0x0C
-#define TRUN1_P 0x0D
-#define TRUN2_P 0x0E
-#define TRUN3_P 0x0F
-#define TRUN4_P 0x1C
-#define TRUN5_P 0x1D
-#define TRUN6_P 0x1E
-#define TRUN7_P 0x1F
-#define TRUN8_P 0x0C
-#define TRUN9_P 0x0D
-#define TRUN10_P 0x0E
-#define TRUN11_P 0x0F
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define TOVL_ERR0 TOVF_ERR0
-#define TOVL_ERR1 TOVF_ERR1
-#define TOVL_ERR2 TOVF_ERR2
-#define TOVL_ERR3 TOVF_ERR3
-#define TOVL_ERR4 TOVF_ERR4
-#define TOVL_ERR5 TOVF_ERR5
-#define TOVL_ERR6 TOVF_ERR6
-#define TOVL_ERR7 TOVF_ERR7
-#define TOVL_ERR8 TOVF_ERR8
-#define TOVL_ERR9 TOVF_ERR9
-#define TOVL_ERR10 TOVF_ERR10
-#define TOVL_ERR11 TOVF_ERR11
-#define TOVL_ERR0_P TOVF_ERR0_P
-#define TOVL_ERR1_P TOVF_ERR1_P
-#define TOVL_ERR2_P TOVF_ERR2_P
-#define TOVL_ERR3_P TOVF_ERR3_P
-#define TOVL_ERR4_P TOVF_ERR4_P
-#define TOVL_ERR5_P TOVF_ERR5_P
-#define TOVL_ERR6_P TOVF_ERR6_P
-#define TOVL_ERR7_P TOVF_ERR7_P
-#define TOVL_ERR8_P TOVF_ERR8_P
-#define TOVL_ERR9_P TOVF_ERR9_P
-#define TOVL_ERR10_P TOVF_ERR10_P
-#define TOVL_ERR11_P TOVF_ERR11_P
-
-/* TIMERx_CONFIG Registers */
-#define PWM_OUT 0x0001
-#define WDTH_CAP 0x0002
-#define EXT_CLK 0x0003
-#define PULSE_HI 0x0004
-#define PERIOD_CNT 0x0008
-#define IRQ_ENA 0x0010
-#define TIN_SEL 0x0020
-#define OUT_DIS 0x0040
-#define CLK_SEL 0x0080
-#define TOGGLE_HI 0x0100
-#define EMU_RUN 0x0200
-#define ERR_TYP(x) ((x & 0x03) << 14)
-
-#define TMODE_P0 0x00
-#define TMODE_P1 0x01
-#define PULSE_HI_P 0x02
-#define PERIOD_CNT_P 0x03
-#define IRQ_ENA_P 0x04
-#define TIN_SEL_P 0x05
-#define OUT_DIS_P 0x06
-#define CLK_SEL_P 0x07
-#define TOGGLE_HI_P 0x08
-#define EMU_RUN_P 0x09
-#define ERR_TYP_P0 0x0E
-#define ERR_TYP_P1 0x0F
-
-/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */
-
-/* AMGCTL Masks */
-#define AMCKEN 0x0001 /* Enable CLKOUT */
-#define AMBEN_B0 0x0002 /* Enable Asynchronous Memory Bank 0 only */
-#define AMBEN_B0_B1 0x0004 /* Enable Asynchronous Memory Banks 0 & 1 only */
-#define AMBEN_B0_B1_B2 0x0006 /* Enable Asynchronous Memory Banks 0, 1, and 2 */
-#define AMBEN_ALL 0x0008 /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */
-#define B0_PEN 0x0010 /* Enable 16-bit packing Bank 0 */
-#define B1_PEN 0x0020 /* Enable 16-bit packing Bank 1 */
-#define B2_PEN 0x0040 /* Enable 16-bit packing Bank 2 */
-#define B3_PEN 0x0080 /* Enable 16-bit packing Bank 3 */
-
-/* AMGCTL Bit Positions */
-#define AMCKEN_P 0x00000000 /* Enable CLKOUT */
-#define AMBEN_P0 0x00000001 /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */
-#define AMBEN_P1 0x00000002 /* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 enabled */
-#define AMBEN_P2 0x00000003 /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */
-#define B0_PEN_P 0x004 /* Enable 16-bit packing Bank 0 */
-#define B1_PEN_P 0x005 /* Enable 16-bit packing Bank 1 */
-#define B2_PEN_P 0x006 /* Enable 16-bit packing Bank 2 */
-#define B3_PEN_P 0x007 /* Enable 16-bit packing Bank 3 */
-
-/* AMBCTL0 Masks */
-#define B0RDYEN 0x00000001 /* Bank 0 RDY Enable, 0=disable, 1=enable */
-#define B0RDYPOL 0x00000002 /* Bank 0 RDY Active high, 0=active low, 1=active high */
-#define B0TT_1 0x00000004 /* Bank 0 Transition Time from Read to Write = 1 cycle */
-#define B0TT_2 0x00000008 /* Bank 0 Transition Time from Read to Write = 2 cycles */
-#define B0TT_3 0x0000000C /* Bank 0 Transition Time from Read to Write = 3 cycles */
-#define B0TT_4 0x00000000 /* Bank 0 Transition Time from Read to Write = 4 cycles */
-#define B0ST_1 0x00000010 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */
-#define B0ST_2 0x00000020 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */
-#define B0ST_3 0x00000030 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */
-#define B0ST_4 0x00000000 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */
-#define B0HT_1 0x00000040 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */
-#define B0HT_2 0x00000080 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */
-#define B0HT_3 0x000000C0 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */
-#define B0HT_0 0x00000000 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */
-#define B0RAT_1 0x00000100 /* Bank 0 Read Access Time = 1 cycle */
-#define B0RAT_2 0x00000200 /* Bank 0 Read Access Time = 2 cycles */
-#define B0RAT_3 0x00000300 /* Bank 0 Read Access Time = 3 cycles */
-#define B0RAT_4 0x00000400 /* Bank 0 Read Access Time = 4 cycles */
-#define B0RAT_5 0x00000500 /* Bank 0 Read Access Time = 5 cycles */
-#define B0RAT_6 0x00000600 /* Bank 0 Read Access Time = 6 cycles */
-#define B0RAT_7 0x00000700 /* Bank 0 Read Access Time = 7 cycles */
-#define B0RAT_8 0x00000800 /* Bank 0 Read Access Time = 8 cycles */
-#define B0RAT_9 0x00000900 /* Bank 0 Read Access Time = 9 cycles */
-#define B0RAT_10 0x00000A00 /* Bank 0 Read Access Time = 10 cycles */
-#define B0RAT_11 0x00000B00 /* Bank 0 Read Access Time = 11 cycles */
-#define B0RAT_12 0x00000C00 /* Bank 0 Read Access Time = 12 cycles */
-#define B0RAT_13 0x00000D00 /* Bank 0 Read Access Time = 13 cycles */
-#define B0RAT_14 0x00000E00 /* Bank 0 Read Access Time = 14 cycles */
-#define B0RAT_15 0x00000F00 /* Bank 0 Read Access Time = 15 cycles */
-#define B0WAT_1 0x00001000 /* Bank 0 Write Access Time = 1 cycle */
-#define B0WAT_2 0x00002000 /* Bank 0 Write Access Time = 2 cycles */
-#define B0WAT_3 0x00003000 /* Bank 0 Write Access Time = 3 cycles */
-#define B0WAT_4 0x00004000 /* Bank 0 Write Access Time = 4 cycles */
-#define B0WAT_5 0x00005000 /* Bank 0 Write Access Time = 5 cycles */
-#define B0WAT_6 0x00006000 /* Bank 0 Write Access Time = 6 cycles */
-#define B0WAT_7 0x00007000 /* Bank 0 Write Access Time = 7 cycles */
-#define B0WAT_8 0x00008000 /* Bank 0 Write Access Time = 8 cycles */
-#define B0WAT_9 0x00009000 /* Bank 0 Write Access Time = 9 cycles */
-#define B0WAT_10 0x0000A000 /* Bank 0 Write Access Time = 10 cycles */
-#define B0WAT_11 0x0000B000 /* Bank 0 Write Access Time = 11 cycles */
-#define B0WAT_12 0x0000C000 /* Bank 0 Write Access Time = 12 cycles */
-#define B0WAT_13 0x0000D000 /* Bank 0 Write Access Time = 13 cycles */
-#define B0WAT_14 0x0000E000 /* Bank 0 Write Access Time = 14 cycles */
-#define B0WAT_15 0x0000F000 /* Bank 0 Write Access Time = 15 cycles */
-#define B1RDYEN 0x00010000 /* Bank 1 RDY enable, 0=disable, 1=enable */
-#define B1RDYPOL 0x00020000 /* Bank 1 RDY Active high, 0=active low, 1=active high */
-#define B1TT_1 0x00040000 /* Bank 1 Transition Time from Read to Write = 1 cycle */
-#define B1TT_2 0x00080000 /* Bank 1 Transition Time from Read to Write = 2 cycles */
-#define B1TT_3 0x000C0000 /* Bank 1 Transition Time from Read to Write = 3 cycles */
-#define B1TT_4 0x00000000 /* Bank 1 Transition Time from Read to Write = 4 cycles */
-#define B1ST_1 0x00100000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B1ST_2 0x00200000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B1ST_3 0x00300000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B1ST_4 0x00000000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B1HT_1 0x00400000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B1HT_2 0x00800000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B1HT_3 0x00C00000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B1HT_0 0x00000000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B1RAT_1 0x01000000 /* Bank 1 Read Access Time = 1 cycle */
-#define B1RAT_2 0x02000000 /* Bank 1 Read Access Time = 2 cycles */
-#define B1RAT_3 0x03000000 /* Bank 1 Read Access Time = 3 cycles */
-#define B1RAT_4 0x04000000 /* Bank 1 Read Access Time = 4 cycles */
-#define B1RAT_5 0x05000000 /* Bank 1 Read Access Time = 5 cycles */
-#define B1RAT_6 0x06000000 /* Bank 1 Read Access Time = 6 cycles */
-#define B1RAT_7 0x07000000 /* Bank 1 Read Access Time = 7 cycles */
-#define B1RAT_8 0x08000000 /* Bank 1 Read Access Time = 8 cycles */
-#define B1RAT_9 0x09000000 /* Bank 1 Read Access Time = 9 cycles */
-#define B1RAT_10 0x0A000000 /* Bank 1 Read Access Time = 10 cycles */
-#define B1RAT_11 0x0B000000 /* Bank 1 Read Access Time = 11 cycles */
-#define B1RAT_12 0x0C000000 /* Bank 1 Read Access Time = 12 cycles */
-#define B1RAT_13 0x0D000000 /* Bank 1 Read Access Time = 13 cycles */
-#define B1RAT_14 0x0E000000 /* Bank 1 Read Access Time = 14 cycles */
-#define B1RAT_15 0x0F000000 /* Bank 1 Read Access Time = 15 cycles */
-#define B1WAT_1 0x10000000 /* Bank 1 Write Access Time = 1 cycle */
-#define B1WAT_2 0x20000000 /* Bank 1 Write Access Time = 2 cycles */
-#define B1WAT_3 0x30000000 /* Bank 1 Write Access Time = 3 cycles */
-#define B1WAT_4 0x40000000 /* Bank 1 Write Access Time = 4 cycles */
-#define B1WAT_5 0x50000000 /* Bank 1 Write Access Time = 5 cycles */
-#define B1WAT_6 0x60000000 /* Bank 1 Write Access Time = 6 cycles */
-#define B1WAT_7 0x70000000 /* Bank 1 Write Access Time = 7 cycles */
-#define B1WAT_8 0x80000000 /* Bank 1 Write Access Time = 8 cycles */
-#define B1WAT_9 0x90000000 /* Bank 1 Write Access Time = 9 cycles */
-#define B1WAT_10 0xA0000000 /* Bank 1 Write Access Time = 10 cycles */
-#define B1WAT_11 0xB0000000 /* Bank 1 Write Access Time = 11 cycles */
-#define B1WAT_12 0xC0000000 /* Bank 1 Write Access Time = 12 cycles */
-#define B1WAT_13 0xD0000000 /* Bank 1 Write Access Time = 13 cycles */
-#define B1WAT_14 0xE0000000 /* Bank 1 Write Access Time = 14 cycles */
-#define B1WAT_15 0xF0000000 /* Bank 1 Write Access Time = 15 cycles */
-
-/* AMBCTL1 Masks */
-#define B2RDYEN 0x00000001 /* Bank 2 RDY Enable, 0=disable, 1=enable */
-#define B2RDYPOL 0x00000002 /* Bank 2 RDY Active high, 0=active low, 1=active high */
-#define B2TT_1 0x00000004 /* Bank 2 Transition Time from Read to Write = 1 cycle */
-#define B2TT_2 0x00000008 /* Bank 2 Transition Time from Read to Write = 2 cycles */
-#define B2TT_3 0x0000000C /* Bank 2 Transition Time from Read to Write = 3 cycles */
-#define B2TT_4 0x00000000 /* Bank 2 Transition Time from Read to Write = 4 cycles */
-#define B2ST_1 0x00000010 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B2ST_2 0x00000020 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B2ST_3 0x00000030 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B2ST_4 0x00000000 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B2HT_1 0x00000040 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B2HT_2 0x00000080 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B2HT_3 0x000000C0 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B2HT_0 0x00000000 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B2RAT_1 0x00000100 /* Bank 2 Read Access Time = 1 cycle */
-#define B2RAT_2 0x00000200 /* Bank 2 Read Access Time = 2 cycles */
-#define B2RAT_3 0x00000300 /* Bank 2 Read Access Time = 3 cycles */
-#define B2RAT_4 0x00000400 /* Bank 2 Read Access Time = 4 cycles */
-#define B2RAT_5 0x00000500 /* Bank 2 Read Access Time = 5 cycles */
-#define B2RAT_6 0x00000600 /* Bank 2 Read Access Time = 6 cycles */
-#define B2RAT_7 0x00000700 /* Bank 2 Read Access Time = 7 cycles */
-#define B2RAT_8 0x00000800 /* Bank 2 Read Access Time = 8 cycles */
-#define B2RAT_9 0x00000900 /* Bank 2 Read Access Time = 9 cycles */
-#define B2RAT_10 0x00000A00 /* Bank 2 Read Access Time = 10 cycles */
-#define B2RAT_11 0x00000B00 /* Bank 2 Read Access Time = 11 cycles */
-#define B2RAT_12 0x00000C00 /* Bank 2 Read Access Time = 12 cycles */
-#define B2RAT_13 0x00000D00 /* Bank 2 Read Access Time = 13 cycles */
-#define B2RAT_14 0x00000E00 /* Bank 2 Read Access Time = 14 cycles */
-#define B2RAT_15 0x00000F00 /* Bank 2 Read Access Time = 15 cycles */
-#define B2WAT_1 0x00001000 /* Bank 2 Write Access Time = 1 cycle */
-#define B2WAT_2 0x00002000 /* Bank 2 Write Access Time = 2 cycles */
-#define B2WAT_3 0x00003000 /* Bank 2 Write Access Time = 3 cycles */
-#define B2WAT_4 0x00004000 /* Bank 2 Write Access Time = 4 cycles */
-#define B2WAT_5 0x00005000 /* Bank 2 Write Access Time = 5 cycles */
-#define B2WAT_6 0x00006000 /* Bank 2 Write Access Time = 6 cycles */
-#define B2WAT_7 0x00007000 /* Bank 2 Write Access Time = 7 cycles */
-#define B2WAT_8 0x00008000 /* Bank 2 Write Access Time = 8 cycles */
-#define B2WAT_9 0x00009000 /* Bank 2 Write Access Time = 9 cycles */
-#define B2WAT_10 0x0000A000 /* Bank 2 Write Access Time = 10 cycles */
-#define B2WAT_11 0x0000B000 /* Bank 2 Write Access Time = 11 cycles */
-#define B2WAT_12 0x0000C000 /* Bank 2 Write Access Time = 12 cycles */
-#define B2WAT_13 0x0000D000 /* Bank 2 Write Access Time = 13 cycles */
-#define B2WAT_14 0x0000E000 /* Bank 2 Write Access Time = 14 cycles */
-#define B2WAT_15 0x0000F000 /* Bank 2 Write Access Time = 15 cycles */
-#define B3RDYEN 0x00010000 /* Bank 3 RDY enable, 0=disable, 1=enable */
-#define B3RDYPOL 0x00020000 /* Bank 3 RDY Active high, 0=active low, 1=active high */
-#define B3TT_1 0x00040000 /* Bank 3 Transition Time from Read to Write = 1 cycle */
-#define B3TT_2 0x00080000 /* Bank 3 Transition Time from Read to Write = 2 cycles */
-#define B3TT_3 0x000C0000 /* Bank 3 Transition Time from Read to Write = 3 cycles */
-#define B3TT_4 0x00000000 /* Bank 3 Transition Time from Read to Write = 4 cycles */
-#define B3ST_1 0x00100000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B3ST_2 0x00200000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B3ST_3 0x00300000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B3ST_4 0x00000000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B3HT_1 0x00400000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B3HT_2 0x00800000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B3HT_3 0x00C00000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B3HT_0 0x00000000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B3RAT_1 0x01000000 /* Bank 3 Read Access Time = 1 cycle */
-#define B3RAT_2 0x02000000 /* Bank 3 Read Access Time = 2 cycles */
-#define B3RAT_3 0x03000000 /* Bank 3 Read Access Time = 3 cycles */
-#define B3RAT_4 0x04000000 /* Bank 3 Read Access Time = 4 cycles */
-#define B3RAT_5 0x05000000 /* Bank 3 Read Access Time = 5 cycles */
-#define B3RAT_6 0x06000000 /* Bank 3 Read Access Time = 6 cycles */
-#define B3RAT_7 0x07000000 /* Bank 3 Read Access Time = 7 cycles */
-#define B3RAT_8 0x08000000 /* Bank 3 Read Access Time = 8 cycles */
-#define B3RAT_9 0x09000000 /* Bank 3 Read Access Time = 9 cycles */
-#define B3RAT_10 0x0A000000 /* Bank 3 Read Access Time = 10 cycles */
-#define B3RAT_11 0x0B000000 /* Bank 3 Read Access Time = 11 cycles */
-#define B3RAT_12 0x0C000000 /* Bank 3 Read Access Time = 12 cycles */
-#define B3RAT_13 0x0D000000 /* Bank 3 Read Access Time = 13 cycles */
-#define B3RAT_14 0x0E000000 /* Bank 3 Read Access Time = 14 cycles */
-#define B3RAT_15 0x0F000000 /* Bank 3 Read Access Time = 15 cycles */
-#define B3WAT_1 0x10000000 /* Bank 3 Write Access Time = 1 cycle */
-#define B3WAT_2 0x20000000 /* Bank 3 Write Access Time = 2 cycles */
-#define B3WAT_3 0x30000000 /* Bank 3 Write Access Time = 3 cycles */
-#define B3WAT_4 0x40000000 /* Bank 3 Write Access Time = 4 cycles */
-#define B3WAT_5 0x50000000 /* Bank 3 Write Access Time = 5 cycles */
-#define B3WAT_6 0x60000000 /* Bank 3 Write Access Time = 6 cycles */
-#define B3WAT_7 0x70000000 /* Bank 3 Write Access Time = 7 cycles */
-#define B3WAT_8 0x80000000 /* Bank 3 Write Access Time = 8 cycles */
-#define B3WAT_9 0x90000000 /* Bank 3 Write Access Time = 9 cycles */
-#define B3WAT_10 0xA0000000 /* Bank 3 Write Access Time = 10 cycles */
-#define B3WAT_11 0xB0000000 /* Bank 3 Write Access Time = 11 cycles */
-#define B3WAT_12 0xC0000000 /* Bank 3 Write Access Time = 12 cycles */
-#define B3WAT_13 0xD0000000 /* Bank 3 Write Access Time = 13 cycles */
-#define B3WAT_14 0xE0000000 /* Bank 3 Write Access Time = 14 cycles */
-#define B3WAT_15 0xF0000000 /* Bank 3 Write Access Time = 15 cycles */
-
-/* ********************** SDRAM CONTROLLER MASKS *************************** */
-
-/* EBIU_SDGCTL Masks */
-#define SCTLE 0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */
-#define CL_2 0x00000008 /* SDRAM CAS latency = 2 cycles */
-#define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */
-#define PFE 0x00000010 /* Enable SDRAM prefetch */
-#define PFP 0x00000020 /* Prefetch has priority over AMC requests */
-#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
-#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
-#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
-#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
-#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
-#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
-#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
-#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
-#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
-#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
-#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
-#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
-#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
-#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
-#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
-#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
-#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
-#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
-#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
-#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
-#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
-#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
-#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
-#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
-#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
-#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
-#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
-#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
-#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
-#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
-#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
-#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
-#define PUPSD 0x00200000 /*Power-up start delay */
-#define PSM 0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */
-#define PSS 0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */
-#define SRFS 0x01000000 /* Start SDRAM self-refresh mode */
-#define EBUFE 0x02000000 /* Enable external buffering timing */
-#define FBBRW 0x04000000 /* Fast back-to-back read write enable */
-#define EMREN 0x10000000 /* Extended mode register enable */
-#define TCSR 0x20000000 /* Temp compensated self refresh value 85 deg C */
-#define CDDBG 0x40000000 /* Tristate SDRAM controls during bus grant */
-
-/* EBIU_SDBCTL Masks */
-#define EB0_E 0x00000001 /* Enable SDRAM external bank 0 */
-#define EB0_SZ_16 0x00000000 /* SDRAM external bank size = 16MB */
-#define EB0_SZ_32 0x00000002 /* SDRAM external bank size = 32MB */
-#define EB0_SZ_64 0x00000004 /* SDRAM external bank size = 64MB */
-#define EB0_SZ_128 0x00000006 /* SDRAM external bank size = 128MB */
-#define EB0_CAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */
-#define EB0_CAW_9 0x00000010 /* SDRAM external bank column address width = 9 bits */
-#define EB0_CAW_10 0x00000020 /* SDRAM external bank column address width = 9 bits */
-#define EB0_CAW_11 0x00000030 /* SDRAM external bank column address width = 9 bits */
-
-#define EB1_E 0x00000100 /* Enable SDRAM external bank 1 */
-#define EB1__SZ_16 0x00000000 /* SDRAM external bank size = 16MB */
-#define EB1__SZ_32 0x00000200 /* SDRAM external bank size = 32MB */
-#define EB1__SZ_64 0x00000400 /* SDRAM external bank size = 64MB */
-#define EB1__SZ_128 0x00000600 /* SDRAM external bank size = 128MB */
-#define EB1__CAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */
-#define EB1__CAW_9 0x00001000 /* SDRAM external bank column address width = 9 bits */
-#define EB1__CAW_10 0x00002000 /* SDRAM external bank column address width = 9 bits */
-#define EB1__CAW_11 0x00003000 /* SDRAM external bank column address width = 9 bits */
-
-#define EB2__E 0x00010000 /* Enable SDRAM external bank 2 */
-#define EB2__SZ_16 0x00000000 /* SDRAM external bank size = 16MB */
-#define EB2__SZ_32 0x00020000 /* SDRAM external bank size = 32MB */
-#define EB2__SZ_64 0x00040000 /* SDRAM external bank size = 64MB */
-#define EB2__SZ_128 0x00060000 /* SDRAM external bank size = 128MB */
-#define EB2__CAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */
-#define EB2__CAW_9 0x00100000 /* SDRAM external bank column address width = 9 bits */
-#define EB2__CAW_10 0x00200000 /* SDRAM external bank column address width = 9 bits */
-#define EB2__CAW_11 0x00300000 /* SDRAM external bank column address width = 9 bits */
-
-#define EB3__E 0x01000000 /* Enable SDRAM external bank 3 */
-#define EB3__SZ_16 0x00000000 /* SDRAM external bank size = 16MB */
-#define EB3__SZ_32 0x02000000 /* SDRAM external bank size = 32MB */
-#define EB3__SZ_64 0x04000000 /* SDRAM external bank size = 64MB */
-#define EB3__SZ_128 0x06000000 /* SDRAM external bank size = 128MB */
-#define EB3__CAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */
-#define EB3__CAW_9 0x10000000 /* SDRAM external bank column address width = 9 bits */
-#define EB3__CAW_10 0x20000000 /* SDRAM external bank column address width = 9 bits */
-#define EB3__CAW_11 0x30000000 /* SDRAM external bank column address width = 9 bits */
-
-/* EBIU_SDSTAT Masks */
-#define SDCI 0x00000001 /* SDRAM controller is idle */
-#define SDSRA 0x00000002 /* SDRAM SDRAM self refresh is active */
-#define SDPUA 0x00000004 /* SDRAM power up active */
-#define SDRS 0x00000008 /* SDRAM is in reset state */
-#define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */
-#define BGSTAT 0x00000020 /* Bus granted */
-
-#endif /* _DEF_BF561_H */
+++ /dev/null
-/* mach/dma.h - arch-specific DMA defines
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_DMA_H_
-#define _MACH_DMA_H_
-
-#define MAX_DMA_CHANNELS 36
-
-/* [#4267] IMDMA channels have no PERIPHERAL_MAP MMR */
-#define MAX_DMA_SUSPEND_CHANNELS 32
-
-#define CH_PPI0 0
-#define CH_PPI (CH_PPI0)
-#define CH_PPI1 1
-#define CH_SPORT0_RX 12
-#define CH_SPORT0_TX 13
-#define CH_SPORT1_RX 14
-#define CH_SPORT1_TX 15
-#define CH_SPI 16
-#define CH_UART_RX 17
-#define CH_UART_TX 18
-#define CH_MEM_STREAM0_DEST 24 /* TX */
-#define CH_MEM_STREAM0_SRC 25 /* RX */
-#define CH_MEM_STREAM1_DEST 26 /* TX */
-#define CH_MEM_STREAM1_SRC 27 /* RX */
-#define CH_MEM_STREAM2_DEST 28
-#define CH_MEM_STREAM2_SRC 29
-#define CH_MEM_STREAM3_DEST 30
-#define CH_MEM_STREAM3_SRC 31
-#define CH_IMEM_STREAM0_DEST 32
-#define CH_IMEM_STREAM0_SRC 33
-#define CH_IMEM_STREAM1_DEST 34
-#define CH_IMEM_STREAM1_SRC 35
-
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2008 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-
-#ifndef _MACH_GPIO_H_
-#define _MACH_GPIO_H_
-
-#define MAX_BLACKFIN_GPIOS 48
-
-#define GPIO_PF0 0
-#define GPIO_PF1 1
-#define GPIO_PF2 2
-#define GPIO_PF3 3
-#define GPIO_PF4 4
-#define GPIO_PF5 5
-#define GPIO_PF6 6
-#define GPIO_PF7 7
-#define GPIO_PF8 8
-#define GPIO_PF9 9
-#define GPIO_PF10 10
-#define GPIO_PF11 11
-#define GPIO_PF12 12
-#define GPIO_PF13 13
-#define GPIO_PF14 14
-#define GPIO_PF15 15
-#define GPIO_PF16 16
-#define GPIO_PF17 17
-#define GPIO_PF18 18
-#define GPIO_PF19 19
-#define GPIO_PF20 20
-#define GPIO_PF21 21
-#define GPIO_PF22 22
-#define GPIO_PF23 23
-#define GPIO_PF24 24
-#define GPIO_PF25 25
-#define GPIO_PF26 26
-#define GPIO_PF27 27
-#define GPIO_PF28 28
-#define GPIO_PF29 29
-#define GPIO_PF30 30
-#define GPIO_PF31 31
-#define GPIO_PF32 32
-#define GPIO_PF33 33
-#define GPIO_PF34 34
-#define GPIO_PF35 35
-#define GPIO_PF36 36
-#define GPIO_PF37 37
-#define GPIO_PF38 38
-#define GPIO_PF39 39
-#define GPIO_PF40 40
-#define GPIO_PF41 41
-#define GPIO_PF42 42
-#define GPIO_PF43 43
-#define GPIO_PF44 44
-#define GPIO_PF45 45
-#define GPIO_PF46 46
-#define GPIO_PF47 47
-
-#define PORT_FIO0 GPIO_PF0
-#define PORT_FIO1 GPIO_PF16
-#define PORT_FIO2 GPIO_PF32
-
-#include <mach-common/ports-f.h>
-
-#endif /* _MACH_GPIO_H_ */
+++ /dev/null
-/*
- * Copyright 2005-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BF561_IRQ_H_
-#define _BF561_IRQ_H_
-
-#include <mach-common/irq.h>
-
-#define NR_PERI_INTS (2 * 32)
-
-#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
-#define IRQ_DMA1_ERROR BFIN_IRQ(1) /* DMA1 Error (general) */
-#define IRQ_DMA_ERROR IRQ_DMA1_ERROR /* DMA1 Error (general) */
-#define IRQ_DMA2_ERROR BFIN_IRQ(2) /* DMA2 Error (general) */
-#define IRQ_IMDMA_ERROR BFIN_IRQ(3) /* IMDMA Error Interrupt */
-#define IRQ_PPI1_ERROR BFIN_IRQ(4) /* PPI1 Error Interrupt */
-#define IRQ_PPI_ERROR IRQ_PPI1_ERROR /* PPI1 Error Interrupt */
-#define IRQ_PPI2_ERROR BFIN_IRQ(5) /* PPI2 Error Interrupt */
-#define IRQ_SPORT0_ERROR BFIN_IRQ(6) /* SPORT0 Error Interrupt */
-#define IRQ_SPORT1_ERROR BFIN_IRQ(7) /* SPORT1 Error Interrupt */
-#define IRQ_SPI_ERROR BFIN_IRQ(8) /* SPI Error Interrupt */
-#define IRQ_UART_ERROR BFIN_IRQ(9) /* UART Error Interrupt */
-#define IRQ_RESERVED_ERROR BFIN_IRQ(10) /* Reversed */
-#define IRQ_DMA1_0 BFIN_IRQ(11) /* DMA1 0 Interrupt(PPI1) */
-#define IRQ_PPI IRQ_DMA1_0 /* DMA1 0 Interrupt(PPI1) */
-#define IRQ_PPI0 IRQ_DMA1_0 /* DMA1 0 Interrupt(PPI1) */
-#define IRQ_DMA1_1 BFIN_IRQ(12) /* DMA1 1 Interrupt(PPI2) */
-#define IRQ_PPI1 IRQ_DMA1_1 /* DMA1 1 Interrupt(PPI2) */
-#define IRQ_DMA1_2 BFIN_IRQ(13) /* DMA1 2 Interrupt */
-#define IRQ_DMA1_3 BFIN_IRQ(14) /* DMA1 3 Interrupt */
-#define IRQ_DMA1_4 BFIN_IRQ(15) /* DMA1 4 Interrupt */
-#define IRQ_DMA1_5 BFIN_IRQ(16) /* DMA1 5 Interrupt */
-#define IRQ_DMA1_6 BFIN_IRQ(17) /* DMA1 6 Interrupt */
-#define IRQ_DMA1_7 BFIN_IRQ(18) /* DMA1 7 Interrupt */
-#define IRQ_DMA1_8 BFIN_IRQ(19) /* DMA1 8 Interrupt */
-#define IRQ_DMA1_9 BFIN_IRQ(20) /* DMA1 9 Interrupt */
-#define IRQ_DMA1_10 BFIN_IRQ(21) /* DMA1 10 Interrupt */
-#define IRQ_DMA1_11 BFIN_IRQ(22) /* DMA1 11 Interrupt */
-#define IRQ_DMA2_0 BFIN_IRQ(23) /* DMA2 0 (SPORT0 RX) */
-#define IRQ_SPORT0_RX IRQ_DMA2_0 /* DMA2 0 (SPORT0 RX) */
-#define IRQ_DMA2_1 BFIN_IRQ(24) /* DMA2 1 (SPORT0 TX) */
-#define IRQ_SPORT0_TX IRQ_DMA2_1 /* DMA2 1 (SPORT0 TX) */
-#define IRQ_DMA2_2 BFIN_IRQ(25) /* DMA2 2 (SPORT1 RX) */
-#define IRQ_SPORT1_RX IRQ_DMA2_2 /* DMA2 2 (SPORT1 RX) */
-#define IRQ_DMA2_3 BFIN_IRQ(26) /* DMA2 3 (SPORT2 TX) */
-#define IRQ_SPORT1_TX IRQ_DMA2_3 /* DMA2 3 (SPORT2 TX) */
-#define IRQ_DMA2_4 BFIN_IRQ(27) /* DMA2 4 (SPI) */
-#define IRQ_SPI IRQ_DMA2_4 /* DMA2 4 (SPI) */
-#define IRQ_DMA2_5 BFIN_IRQ(28) /* DMA2 5 (UART RX) */
-#define IRQ_UART_RX IRQ_DMA2_5 /* DMA2 5 (UART RX) */
-#define IRQ_DMA2_6 BFIN_IRQ(29) /* DMA2 6 (UART TX) */
-#define IRQ_UART_TX IRQ_DMA2_6 /* DMA2 6 (UART TX) */
-#define IRQ_DMA2_7 BFIN_IRQ(30) /* DMA2 7 Interrupt */
-#define IRQ_DMA2_8 BFIN_IRQ(31) /* DMA2 8 Interrupt */
-#define IRQ_DMA2_9 BFIN_IRQ(32) /* DMA2 9 Interrupt */
-#define IRQ_DMA2_10 BFIN_IRQ(33) /* DMA2 10 Interrupt */
-#define IRQ_DMA2_11 BFIN_IRQ(34) /* DMA2 11 Interrupt */
-#define IRQ_TIMER0 BFIN_IRQ(35) /* TIMER 0 Interrupt */
-#define IRQ_TIMER1 BFIN_IRQ(36) /* TIMER 1 Interrupt */
-#define IRQ_TIMER2 BFIN_IRQ(37) /* TIMER 2 Interrupt */
-#define IRQ_TIMER3 BFIN_IRQ(38) /* TIMER 3 Interrupt */
-#define IRQ_TIMER4 BFIN_IRQ(39) /* TIMER 4 Interrupt */
-#define IRQ_TIMER5 BFIN_IRQ(40) /* TIMER 5 Interrupt */
-#define IRQ_TIMER6 BFIN_IRQ(41) /* TIMER 6 Interrupt */
-#define IRQ_TIMER7 BFIN_IRQ(42) /* TIMER 7 Interrupt */
-#define IRQ_TIMER8 BFIN_IRQ(43) /* TIMER 8 Interrupt */
-#define IRQ_TIMER9 BFIN_IRQ(44) /* TIMER 9 Interrupt */
-#define IRQ_TIMER10 BFIN_IRQ(45) /* TIMER 10 Interrupt */
-#define IRQ_TIMER11 BFIN_IRQ(46) /* TIMER 11 Interrupt */
-#define IRQ_PROG0_INTA BFIN_IRQ(47) /* Programmable Flags0 A (8) */
-#define IRQ_PROG_INTA IRQ_PROG0_INTA /* Programmable Flags0 A (8) */
-#define IRQ_PROG0_INTB BFIN_IRQ(48) /* Programmable Flags0 B (8) */
-#define IRQ_PROG_INTB IRQ_PROG0_INTB /* Programmable Flags0 B (8) */
-#define IRQ_PROG1_INTA BFIN_IRQ(49) /* Programmable Flags1 A (8) */
-#define IRQ_PROG1_INTB BFIN_IRQ(50) /* Programmable Flags1 B (8) */
-#define IRQ_PROG2_INTA BFIN_IRQ(51) /* Programmable Flags2 A (8) */
-#define IRQ_PROG2_INTB BFIN_IRQ(52) /* Programmable Flags2 B (8) */
-#define IRQ_DMA1_WRRD0 BFIN_IRQ(53) /* MDMA1 0 write/read INT */
-#define IRQ_DMA_WRRD0 IRQ_DMA1_WRRD0 /* MDMA1 0 write/read INT */
-#define IRQ_MEM_DMA0 IRQ_DMA1_WRRD0
-#define IRQ_DMA1_WRRD1 BFIN_IRQ(54) /* MDMA1 1 write/read INT */
-#define IRQ_DMA_WRRD1 IRQ_DMA1_WRRD1 /* MDMA1 1 write/read INT */
-#define IRQ_MEM_DMA1 IRQ_DMA1_WRRD1
-#define IRQ_DMA2_WRRD0 BFIN_IRQ(55) /* MDMA2 0 write/read INT */
-#define IRQ_MEM_DMA2 IRQ_DMA2_WRRD0
-#define IRQ_DMA2_WRRD1 BFIN_IRQ(56) /* MDMA2 1 write/read INT */
-#define IRQ_MEM_DMA3 IRQ_DMA2_WRRD1
-#define IRQ_IMDMA_WRRD0 BFIN_IRQ(57) /* IMDMA 0 write/read INT */
-#define IRQ_IMEM_DMA0 IRQ_IMDMA_WRRD0
-#define IRQ_IMDMA_WRRD1 BFIN_IRQ(58) /* IMDMA 1 write/read INT */
-#define IRQ_IMEM_DMA1 IRQ_IMDMA_WRRD1
-#define IRQ_WATCH BFIN_IRQ(59) /* Watch Dog Timer */
-#define IRQ_RESERVED_1 BFIN_IRQ(60) /* Reserved interrupt */
-#define IRQ_RESERVED_2 BFIN_IRQ(61) /* Reserved interrupt */
-#define IRQ_SUPPLE_0 BFIN_IRQ(62) /* Supplemental interrupt 0 */
-#define IRQ_SUPPLE_1 BFIN_IRQ(63) /* supplemental interrupt 1 */
-
-#define SYS_IRQS 71
-
-#define IRQ_PF0 73
-#define IRQ_PF1 74
-#define IRQ_PF2 75
-#define IRQ_PF3 76
-#define IRQ_PF4 77
-#define IRQ_PF5 78
-#define IRQ_PF6 79
-#define IRQ_PF7 80
-#define IRQ_PF8 81
-#define IRQ_PF9 82
-#define IRQ_PF10 83
-#define IRQ_PF11 84
-#define IRQ_PF12 85
-#define IRQ_PF13 86
-#define IRQ_PF14 87
-#define IRQ_PF15 88
-#define IRQ_PF16 89
-#define IRQ_PF17 90
-#define IRQ_PF18 91
-#define IRQ_PF19 92
-#define IRQ_PF20 93
-#define IRQ_PF21 94
-#define IRQ_PF22 95
-#define IRQ_PF23 96
-#define IRQ_PF24 97
-#define IRQ_PF25 98
-#define IRQ_PF26 99
-#define IRQ_PF27 100
-#define IRQ_PF28 101
-#define IRQ_PF29 102
-#define IRQ_PF30 103
-#define IRQ_PF31 104
-#define IRQ_PF32 105
-#define IRQ_PF33 106
-#define IRQ_PF34 107
-#define IRQ_PF35 108
-#define IRQ_PF36 109
-#define IRQ_PF37 110
-#define IRQ_PF38 111
-#define IRQ_PF39 112
-#define IRQ_PF40 113
-#define IRQ_PF41 114
-#define IRQ_PF42 115
-#define IRQ_PF43 116
-#define IRQ_PF44 117
-#define IRQ_PF45 118
-#define IRQ_PF46 119
-#define IRQ_PF47 120
-
-#define GPIO_IRQ_BASE IRQ_PF0
-
-#define NR_MACH_IRQS (IRQ_PF47 + 1)
-
-/* IAR0 BIT FIELDS */
-#define IRQ_PLL_WAKEUP_POS 0
-#define IRQ_DMA1_ERROR_POS 4
-#define IRQ_DMA2_ERROR_POS 8
-#define IRQ_IMDMA_ERROR_POS 12
-#define IRQ_PPI0_ERROR_POS 16
-#define IRQ_PPI1_ERROR_POS 20
-#define IRQ_SPORT0_ERROR_POS 24
-#define IRQ_SPORT1_ERROR_POS 28
-
-/* IAR1 BIT FIELDS */
-#define IRQ_SPI_ERROR_POS 0
-#define IRQ_UART_ERROR_POS 4
-#define IRQ_RESERVED_ERROR_POS 8
-#define IRQ_DMA1_0_POS 12
-#define IRQ_DMA1_1_POS 16
-#define IRQ_DMA1_2_POS 20
-#define IRQ_DMA1_3_POS 24
-#define IRQ_DMA1_4_POS 28
-
-/* IAR2 BIT FIELDS */
-#define IRQ_DMA1_5_POS 0
-#define IRQ_DMA1_6_POS 4
-#define IRQ_DMA1_7_POS 8
-#define IRQ_DMA1_8_POS 12
-#define IRQ_DMA1_9_POS 16
-#define IRQ_DMA1_10_POS 20
-#define IRQ_DMA1_11_POS 24
-#define IRQ_DMA2_0_POS 28
-
-/* IAR3 BIT FIELDS */
-#define IRQ_DMA2_1_POS 0
-#define IRQ_DMA2_2_POS 4
-#define IRQ_DMA2_3_POS 8
-#define IRQ_DMA2_4_POS 12
-#define IRQ_DMA2_5_POS 16
-#define IRQ_DMA2_6_POS 20
-#define IRQ_DMA2_7_POS 24
-#define IRQ_DMA2_8_POS 28
-
-/* IAR4 BIT FIELDS */
-#define IRQ_DMA2_9_POS 0
-#define IRQ_DMA2_10_POS 4
-#define IRQ_DMA2_11_POS 8
-#define IRQ_TIMER0_POS 12
-#define IRQ_TIMER1_POS 16
-#define IRQ_TIMER2_POS 20
-#define IRQ_TIMER3_POS 24
-#define IRQ_TIMER4_POS 28
-
-/* IAR5 BIT FIELDS */
-#define IRQ_TIMER5_POS 0
-#define IRQ_TIMER6_POS 4
-#define IRQ_TIMER7_POS 8
-#define IRQ_TIMER8_POS 12
-#define IRQ_TIMER9_POS 16
-#define IRQ_TIMER10_POS 20
-#define IRQ_TIMER11_POS 24
-#define IRQ_PROG0_INTA_POS 28
-
-/* IAR6 BIT FIELDS */
-#define IRQ_PROG0_INTB_POS 0
-#define IRQ_PROG1_INTA_POS 4
-#define IRQ_PROG1_INTB_POS 8
-#define IRQ_PROG2_INTA_POS 12
-#define IRQ_PROG2_INTB_POS 16
-#define IRQ_DMA1_WRRD0_POS 20
-#define IRQ_DMA1_WRRD1_POS 24
-#define IRQ_DMA2_WRRD0_POS 28
-
-/* IAR7 BIT FIELDS */
-#define IRQ_DMA2_WRRD1_POS 0
-#define IRQ_IMDMA_WRRD0_POS 4
-#define IRQ_IMDMA_WRRD1_POS 8
-#define IRQ_WDTIMER_POS 12
-#define IRQ_RESERVED_1_POS 16
-#define IRQ_RESERVED_2_POS 20
-#define IRQ_SUPPLE_0_POS 24
-#define IRQ_SUPPLE_1_POS 28
-
-#endif
+++ /dev/null
-/*
- * BF561 memory map
- *
- * Copyright 2004-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MACH_MEM_MAP_H__
-#define __BFIN_MACH_MEM_MAP_H__
-
-#ifndef __BFIN_MEM_MAP_H__
-# error "do not include mach/mem_map.h directly -- use asm/mem_map.h"
-#endif
-
-/* Async Memory Banks */
-#define ASYNC_BANK3_BASE 0x2C000000 /* Async Bank 3 */
-#define ASYNC_BANK3_SIZE 0x04000000 /* 64M */
-#define ASYNC_BANK2_BASE 0x28000000 /* Async Bank 2 */
-#define ASYNC_BANK2_SIZE 0x04000000 /* 64M */
-#define ASYNC_BANK1_BASE 0x24000000 /* Async Bank 1 */
-#define ASYNC_BANK1_SIZE 0x04000000 /* 64M */
-#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
-#define ASYNC_BANK0_SIZE 0x04000000 /* 64M */
-
-/* Boot ROM Memory */
-
-#define BOOT_ROM_START 0xEF000000
-#define BOOT_ROM_LENGTH 0x800
-
-/* Level 1 Memory */
-
-#ifdef CONFIG_BFIN_ICACHE
-#define BFIN_ICACHESIZE (16*1024)
-#else
-#define BFIN_ICACHESIZE (0*1024)
-#endif
-
-/* Memory Map for ADSP-BF561 processors */
-
-#define COREA_L1_CODE_START 0xFFA00000
-#define COREA_L1_DATA_A_START 0xFF800000
-#define COREA_L1_DATA_B_START 0xFF900000
-#define COREB_L1_CODE_START 0xFF600000
-#define COREB_L1_DATA_A_START 0xFF400000
-#define COREB_L1_DATA_B_START 0xFF500000
-
-#define L1_CODE_START COREA_L1_CODE_START
-#define L1_DATA_A_START COREA_L1_DATA_A_START
-#define L1_DATA_B_START COREA_L1_DATA_B_START
-
-#define L1_CODE_LENGTH 0x4000
-
-#ifdef CONFIG_BFIN_DCACHE
-
-#ifdef CONFIG_BFIN_DCACHE_BANKA
-#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE (16*1024)
-#define BFIN_DSUPBANKS 1
-#else
-#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
-#define BFIN_DCACHESIZE (32*1024)
-#define BFIN_DSUPBANKS 2
-#endif
-
-#else
-#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH 0x8000
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE (0*1024)
-#define BFIN_DSUPBANKS 0
-#endif /*CONFIG_BFIN_DCACHE*/
-
-/*
- * If we are in SMP mode, then the cache settings of Core B will match
- * the settings of Core A. If we aren't, then we assume Core B is not
- * using any cache. This allows the rest of the kernel to work with
- * the core in either mode as we are only loading user code into it and
- * it is the user's problem to make sure they aren't doing something
- * stupid there.
- *
- * Note that we treat the L1 code region as a contiguous blob to make
- * the rest of the kernel simpler. Easier to check one region than a
- * bunch of small ones. Again, possible misbehavior here is the fault
- * of the user -- don't try to use memory that doesn't exist.
- */
-#ifdef CONFIG_SMP
-# define COREB_L1_CODE_LENGTH L1_CODE_LENGTH
-# define COREB_L1_DATA_A_LENGTH L1_DATA_A_LENGTH
-# define COREB_L1_DATA_B_LENGTH L1_DATA_B_LENGTH
-#else
-# define COREB_L1_CODE_LENGTH 0x14000
-# define COREB_L1_DATA_A_LENGTH 0x8000
-# define COREB_L1_DATA_B_LENGTH 0x8000
-#endif
-
-/* Level 2 Memory */
-#define L2_START 0xFEB00000
-#define L2_LENGTH 0x20000
-
-/* Scratch Pad Memory */
-
-#define COREA_L1_SCRATCH_START 0xFFB00000
-#define COREB_L1_SCRATCH_START 0xFF700000
-
-#ifdef CONFIG_SMP
-
-/*
- * The following macros both return the address of the PDA for the
- * current core.
- *
- * In its first safe (and hairy) form, the macro neither clobbers any
- * register aside of the output Preg, nor uses the stack, since it
- * could be called with an invalid stack pointer, or the current stack
- * space being uncovered by any CPLB (e.g. early exception handling).
- *
- * The constraints on the second form are a bit relaxed, and the code
- * is allowed to use the specified Dreg for determining the PDA
- * address to be returned into Preg.
- */
-# define GET_PDA_SAFE(preg) \
- preg.l = lo(DSPID); \
- preg.h = hi(DSPID); \
- preg = [preg]; \
- preg = preg << 2; \
- preg = preg << 2; \
- preg = preg << 2; \
- preg = preg << 2; \
- preg = preg << 2; \
- preg = preg << 2; \
- preg = preg << 2; \
- preg = preg << 2; \
- preg = preg << 2; \
- preg = preg << 2; \
- preg = preg << 2; \
- preg = preg << 2; \
- if cc jump 2f; \
- cc = preg == 0x0; \
- preg.l = _cpu_pda; \
- preg.h = _cpu_pda; \
- if !cc jump 3f; \
-1: \
- /* preg = 0x0; */ \
- cc = !cc; /* restore cc to 0 */ \
- jump 4f; \
-2: \
- cc = preg == 0x0; \
- preg.l = _cpu_pda; \
- preg.h = _cpu_pda; \
- if cc jump 4f; \
- /* preg = 0x1000000; */ \
- cc = !cc; /* restore cc to 1 */ \
-3: \
- preg = [preg]; \
-4:
-
-# define GET_PDA(preg, dreg) \
- preg.l = lo(DSPID); \
- preg.h = hi(DSPID); \
- dreg = [preg]; \
- preg.l = _cpu_pda; \
- preg.h = _cpu_pda; \
- cc = bittst(dreg, 0); \
- if !cc jump 1f; \
- preg = [preg]; \
-1: \
-
-# define GET_CPUID(preg, dreg) \
- preg.l = lo(DSPID); \
- preg.h = hi(DSPID); \
- dreg = [preg]; \
- dreg = ROT dreg BY -1; \
- dreg = CC;
-
-# ifndef __ASSEMBLY__
-
-# include <asm/processor.h>
-
-static inline unsigned long get_l1_scratch_start_cpu(int cpu)
-{
- return cpu ? COREB_L1_SCRATCH_START : COREA_L1_SCRATCH_START;
-}
-static inline unsigned long get_l1_code_start_cpu(int cpu)
-{
- return cpu ? COREB_L1_CODE_START : COREA_L1_CODE_START;
-}
-static inline unsigned long get_l1_data_a_start_cpu(int cpu)
-{
- return cpu ? COREB_L1_DATA_A_START : COREA_L1_DATA_A_START;
-}
-static inline unsigned long get_l1_data_b_start_cpu(int cpu)
-{
- return cpu ? COREB_L1_DATA_B_START : COREA_L1_DATA_B_START;
-}
-
-static inline unsigned long get_l1_scratch_start(void)
-{
- return get_l1_scratch_start_cpu(blackfin_core_id());
-}
-static inline unsigned long get_l1_code_start(void)
-{
- return get_l1_code_start_cpu(blackfin_core_id());
-}
-static inline unsigned long get_l1_data_a_start(void)
-{
- return get_l1_data_a_start_cpu(blackfin_core_id());
-}
-static inline unsigned long get_l1_data_b_start(void)
-{
- return get_l1_data_b_start_cpu(blackfin_core_id());
-}
-
-# endif /* __ASSEMBLY__ */
-#endif /* CONFIG_SMP */
-
-#endif
+++ /dev/null
-/*
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_PLL_H
-#define _MACH_PLL_H
-
-#ifndef __ASSEMBLY__
-
-#ifdef CONFIG_SMP
-
-#include <asm/blackfin.h>
-#include <asm/irqflags.h>
-#include <mach/irq.h>
-
-#define SUPPLE_0_WAKEUP ((IRQ_SUPPLE_0 - (IRQ_CORETMR + 1)) % 32)
-#define SUPPLE_1_WAKEUP ((IRQ_SUPPLE_1 - (IRQ_CORETMR + 1)) % 32)
-
-static inline void
-bfin_iwr_restore(unsigned long iwr0, unsigned long iwr1, unsigned long iwr2)
-{
- unsigned long SICA_SICB_OFF = ((bfin_read_DSPID() & 0xff) ? 0x1000 : 0);
-
- bfin_write32(SIC_IWR0 + SICA_SICB_OFF, iwr0);
- bfin_write32(SIC_IWR1 + SICA_SICB_OFF, iwr1);
-}
-#define bfin_iwr_restore bfin_iwr_restore
-
-static inline void
-bfin_iwr_save(unsigned long niwr0, unsigned long niwr1, unsigned long niwr2,
- unsigned long *iwr0, unsigned long *iwr1, unsigned long *iwr2)
-{
- unsigned long SICA_SICB_OFF = ((bfin_read_DSPID() & 0xff) ? 0x1000 : 0);
-
- *iwr0 = bfin_read32(SIC_IWR0 + SICA_SICB_OFF);
- *iwr1 = bfin_read32(SIC_IWR1 + SICA_SICB_OFF);
- bfin_iwr_restore(niwr0, niwr1, niwr2);
-}
-#define bfin_iwr_save bfin_iwr_save
-
-static inline void
-bfin_iwr_set_sup0(unsigned long *iwr0, unsigned long *iwr1, unsigned long *iwr2)
-{
- bfin_iwr_save(0, IWR_ENABLE(SUPPLE_0_WAKEUP) |
- IWR_ENABLE(SUPPLE_1_WAKEUP), 0, iwr0, iwr1, iwr2);
-}
-
-#endif
-
-#endif
-
-#include <mach-common/pll.h>
-
-#endif
+++ /dev/null
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_PORTMUX_H_
-#define _MACH_PORTMUX_H_
-
-#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
-
-#define P_PPI0_CLK (P_DONTCARE)
-#define P_PPI0_FS1 (P_DONTCARE)
-#define P_PPI0_FS2 (P_DONTCARE)
-#define P_PPI0_FS3 (P_DONTCARE)
-#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF47))
-#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF46))
-#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF45))
-#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF44))
-#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF43))
-#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF42))
-#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF41))
-#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF40))
-#define P_PPI0_D0 (P_DONTCARE)
-#define P_PPI0_D1 (P_DONTCARE)
-#define P_PPI0_D2 (P_DONTCARE)
-#define P_PPI0_D3 (P_DONTCARE)
-#define P_PPI0_D4 (P_DONTCARE)
-#define P_PPI0_D5 (P_DONTCARE)
-#define P_PPI0_D6 (P_DONTCARE)
-#define P_PPI0_D7 (P_DONTCARE)
-#define P_PPI1_CLK (P_DONTCARE)
-#define P_PPI1_FS1 (P_DONTCARE)
-#define P_PPI1_FS2 (P_DONTCARE)
-#define P_PPI1_FS3 (P_DONTCARE)
-#define P_PPI1_D15 (P_DEFINED | P_IDENT(GPIO_PF39))
-#define P_PPI1_D14 (P_DEFINED | P_IDENT(GPIO_PF38))
-#define P_PPI1_D13 (P_DEFINED | P_IDENT(GPIO_PF37))
-#define P_PPI1_D12 (P_DEFINED | P_IDENT(GPIO_PF36))
-#define P_PPI1_D11 (P_DEFINED | P_IDENT(GPIO_PF35))
-#define P_PPI1_D10 (P_DEFINED | P_IDENT(GPIO_PF34))
-#define P_PPI1_D9 (P_DEFINED | P_IDENT(GPIO_PF33))
-#define P_PPI1_D8 (P_DEFINED | P_IDENT(GPIO_PF32))
-#define P_PPI1_D0 (P_DONTCARE)
-#define P_PPI1_D1 (P_DONTCARE)
-#define P_PPI1_D2 (P_DONTCARE)
-#define P_PPI1_D3 (P_DONTCARE)
-#define P_PPI1_D4 (P_DONTCARE)
-#define P_PPI1_D5 (P_DONTCARE)
-#define P_PPI1_D6 (P_DONTCARE)
-#define P_PPI1_D7 (P_DONTCARE)
-#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PF31))
-#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PF30))
-#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PF29))
-#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PF28))
-#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PF27))
-#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PF26))
-#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PF25))
-#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PF24))
-#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PF23))
-#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PF22))
-#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PF21))
-#define P_SPORT1_DRPRI (P_DONTCARE)
-#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PF20))
-#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PF19))
-#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PF18))
-#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PF17))
-#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PF16))
-#define P_SPORT0_DRPRI (P_DONTCARE)
-#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF15))
-#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF7))
-#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF6))
-#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5))
-#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF4))
-#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF3))
-#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2))
-#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1))
-#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0))
-#define P_TMR11 (P_DONTCARE)
-#define P_TMR10 (P_DONTCARE)
-#define P_TMR9 (P_DONTCARE)
-#define P_TMR8 (P_DONTCARE)
-#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PF7))
-#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PF6))
-#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PF5))
-#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PF4))
-#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PF3))
-#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PF2))
-#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PF1))
-#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PF0))
-#define P_SPI0_MOSI (P_DONTCARE)
-#define P_SPI0_MISO (P_DONTCARE)
-#define P_SPI0_SCK (P_DONTCARE)
-#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF2
-#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2
-
-#endif /* _MACH_PORTMUX_H_ */
+++ /dev/null
-/*
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_BF561_SMP
-#define _MACH_BF561_SMP
-
-/* This header has to stand alone to avoid circular deps */
-
-struct task_struct;
-
-void platform_init_cpus(void);
-
-void platform_prepare_cpus(unsigned int max_cpus);
-
-int platform_boot_secondary(unsigned int cpu, struct task_struct *idle);
-
-void platform_secondary_init(unsigned int cpu);
-
-void platform_request_ipi(int irq, /*irq_handler_t*/ void *handler);
-
-void platform_send_ipi(cpumask_t callmap, int irq);
-
-void platform_send_ipi_cpu(unsigned int cpu, int irq);
-
-void platform_clear_ipi(unsigned int cpu, int irq);
-
-void bfin_local_timer_setup(void);
-
-#endif /* !_MACH_BF561_SMP */
+++ /dev/null
-/*
- * Set up the interrupt priorities
- *
- * Copyright 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-#include <linux/irq.h>
-#include <asm/blackfin.h>
-
-void __init program_IAR(void)
-{
- /* Program the IAR0 Register with the configured priority */
- bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) |
- ((CONFIG_IRQ_DMA1_ERROR - 7) << IRQ_DMA1_ERROR_POS) |
- ((CONFIG_IRQ_DMA2_ERROR - 7) << IRQ_DMA2_ERROR_POS) |
- ((CONFIG_IRQ_IMDMA_ERROR - 7) << IRQ_IMDMA_ERROR_POS) |
- ((CONFIG_IRQ_PPI0_ERROR - 7) << IRQ_PPI0_ERROR_POS) |
- ((CONFIG_IRQ_PPI1_ERROR - 7) << IRQ_PPI1_ERROR_POS) |
- ((CONFIG_IRQ_SPORT0_ERROR - 7) << IRQ_SPORT0_ERROR_POS) |
- ((CONFIG_IRQ_SPORT1_ERROR - 7) << IRQ_SPORT1_ERROR_POS));
-
- bfin_write_SIC_IAR1(((CONFIG_IRQ_SPI_ERROR - 7) << IRQ_SPI_ERROR_POS) |
- ((CONFIG_IRQ_UART_ERROR - 7) << IRQ_UART_ERROR_POS) |
- ((CONFIG_IRQ_RESERVED_ERROR - 7) << IRQ_RESERVED_ERROR_POS) |
- ((CONFIG_IRQ_DMA1_0 - 7) << IRQ_DMA1_0_POS) |
- ((CONFIG_IRQ_DMA1_1 - 7) << IRQ_DMA1_1_POS) |
- ((CONFIG_IRQ_DMA1_2 - 7) << IRQ_DMA1_2_POS) |
- ((CONFIG_IRQ_DMA1_3 - 7) << IRQ_DMA1_3_POS) |
- ((CONFIG_IRQ_DMA1_4 - 7) << IRQ_DMA1_4_POS));
-
- bfin_write_SIC_IAR2(((CONFIG_IRQ_DMA1_5 - 7) << IRQ_DMA1_5_POS) |
- ((CONFIG_IRQ_DMA1_6 - 7) << IRQ_DMA1_6_POS) |
- ((CONFIG_IRQ_DMA1_7 - 7) << IRQ_DMA1_7_POS) |
- ((CONFIG_IRQ_DMA1_8 - 7) << IRQ_DMA1_8_POS) |
- ((CONFIG_IRQ_DMA1_9 - 7) << IRQ_DMA1_9_POS) |
- ((CONFIG_IRQ_DMA1_10 - 7) << IRQ_DMA1_10_POS) |
- ((CONFIG_IRQ_DMA1_11 - 7) << IRQ_DMA1_11_POS) |
- ((CONFIG_IRQ_DMA2_0 - 7) << IRQ_DMA2_0_POS));
-
- bfin_write_SIC_IAR3(((CONFIG_IRQ_DMA2_1 - 7) << IRQ_DMA2_1_POS) |
- ((CONFIG_IRQ_DMA2_2 - 7) << IRQ_DMA2_2_POS) |
- ((CONFIG_IRQ_DMA2_3 - 7) << IRQ_DMA2_3_POS) |
- ((CONFIG_IRQ_DMA2_4 - 7) << IRQ_DMA2_4_POS) |
- ((CONFIG_IRQ_DMA2_5 - 7) << IRQ_DMA2_5_POS) |
- ((CONFIG_IRQ_DMA2_6 - 7) << IRQ_DMA2_6_POS) |
- ((CONFIG_IRQ_DMA2_7 - 7) << IRQ_DMA2_7_POS) |
- ((CONFIG_IRQ_DMA2_8 - 7) << IRQ_DMA2_8_POS));
-
- bfin_write_SIC_IAR4(((CONFIG_IRQ_DMA2_9 - 7) << IRQ_DMA2_9_POS) |
- ((CONFIG_IRQ_DMA2_10 - 7) << IRQ_DMA2_10_POS) |
- ((CONFIG_IRQ_DMA2_11 - 7) << IRQ_DMA2_11_POS) |
- ((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) |
- ((CONFIG_IRQ_TIMER1 - 7) << IRQ_TIMER1_POS) |
- ((CONFIG_IRQ_TIMER2 - 7) << IRQ_TIMER2_POS) |
- ((CONFIG_IRQ_TIMER3 - 7) << IRQ_TIMER3_POS) |
- ((CONFIG_IRQ_TIMER4 - 7) << IRQ_TIMER4_POS));
-
- bfin_write_SIC_IAR5(((CONFIG_IRQ_TIMER5 - 7) << IRQ_TIMER5_POS) |
- ((CONFIG_IRQ_TIMER6 - 7) << IRQ_TIMER6_POS) |
- ((CONFIG_IRQ_TIMER7 - 7) << IRQ_TIMER7_POS) |
- ((CONFIG_IRQ_TIMER8 - 7) << IRQ_TIMER8_POS) |
- ((CONFIG_IRQ_TIMER9 - 7) << IRQ_TIMER9_POS) |
- ((CONFIG_IRQ_TIMER10 - 7) << IRQ_TIMER10_POS) |
- ((CONFIG_IRQ_TIMER11 - 7) << IRQ_TIMER11_POS) |
- ((CONFIG_IRQ_PROG0_INTA - 7) << IRQ_PROG0_INTA_POS));
-
- bfin_write_SIC_IAR6(((CONFIG_IRQ_PROG0_INTB - 7) << IRQ_PROG0_INTB_POS) |
- ((CONFIG_IRQ_PROG1_INTA - 7) << IRQ_PROG1_INTA_POS) |
- ((CONFIG_IRQ_PROG1_INTB - 7) << IRQ_PROG1_INTB_POS) |
- ((CONFIG_IRQ_PROG2_INTA - 7) << IRQ_PROG2_INTA_POS) |
- ((CONFIG_IRQ_PROG2_INTB - 7) << IRQ_PROG2_INTB_POS) |
- ((CONFIG_IRQ_DMA1_WRRD0 - 7) << IRQ_DMA1_WRRD0_POS) |
- ((CONFIG_IRQ_DMA1_WRRD1 - 7) << IRQ_DMA1_WRRD1_POS) |
- ((CONFIG_IRQ_DMA2_WRRD0 - 7) << IRQ_DMA2_WRRD0_POS));
-
- bfin_write_SIC_IAR7(((CONFIG_IRQ_DMA2_WRRD1 - 7) << IRQ_DMA2_WRRD1_POS) |
- ((CONFIG_IRQ_IMDMA_WRRD0 - 7) << IRQ_IMDMA_WRRD0_POS) |
- ((CONFIG_IRQ_IMDMA_WRRD1 - 7) << IRQ_IMDMA_WRRD1_POS) |
- ((CONFIG_IRQ_WDTIMER - 7) << IRQ_WDTIMER_POS) |
- (0 << IRQ_RESERVED_1_POS) | (0 << IRQ_RESERVED_2_POS) |
- (0 << IRQ_SUPPLE_0_POS) | (0 << IRQ_SUPPLE_1_POS));
-
- SSYNC();
-}
+++ /dev/null
-/*
- * BF561 coreB bootstrap file
- *
- * Copyright 2007-2009 Analog Devices Inc.
- * Philippe Gerum <rpm@xenomai.org>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/linkage.h>
-#include <linux/init.h>
-#include <asm/blackfin.h>
-#include <asm/asm-offsets.h>
-#include <asm/trace.h>
-
-/*
- * This code must come first as CoreB is hardcoded (in hardware)
- * to start at the beginning of its L1 instruction memory.
- */
-.section .l1.text.head
-
-/* Lay the initial stack into the L1 scratch area of Core B */
-#define INITIAL_STACK (COREB_L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12)
-
-ENTRY(_coreb_trampoline_start)
- /* Enable Cycle Counter and Nesting Of Interrupts */
-#ifdef CONFIG_BFIN_SCRATCH_REG_CYCLES
- R0 = SYSCFG_SNEN;
-#else
- R0 = SYSCFG_SNEN | SYSCFG_CCEN;
-#endif
- SYSCFG = R0;
-
- /* Optimization register tricks: keep a base value in the
- * reserved P registers so we use the load/store with an
- * offset syntax. R0 = [P5 + <constant>];
- * P5 - core MMR base
- * R6 - 0
- */
- r6 = 0;
- p5.l = 0;
- p5.h = hi(COREMMR_BASE);
-
- /* Zero out registers required by Blackfin ABI */
-
- /* Disable circular buffers */
- L0 = r6;
- L1 = r6;
- L2 = r6;
- L3 = r6;
-
- /* Disable hardware loops in case we were started by 'go' */
- LC0 = r6;
- LC1 = r6;
-
- /*
- * Clear ITEST_COMMAND and DTEST_COMMAND registers,
- * Leaving these as non-zero can confuse the emulator
- */
- [p5 + (DTEST_COMMAND - COREMMR_BASE)] = r6;
- [p5 + (ITEST_COMMAND - COREMMR_BASE)] = r6;
- CSYNC;
-
- trace_buffer_init(p0,r0);
-
- /* Turn off the icache */
- r1 = [p5 + (IMEM_CONTROL - COREMMR_BASE)];
- BITCLR (r1, ENICPLB_P);
- [p5 + (IMEM_CONTROL - COREMMR_BASE)] = r1;
- SSYNC;
-
- /* Turn off the dcache */
- r1 = [p5 + (DMEM_CONTROL - COREMMR_BASE)];
- BITCLR (r1, ENDCPLB_P);
- [p5 + (DMEM_CONTROL - COREMMR_BASE)] = r1;
- SSYNC;
-
- /* in case of double faults, save a few things */
- p1.l = _initial_pda_coreb;
- p1.h = _initial_pda_coreb;
- r4 = RETX;
-#ifdef CONFIG_DEBUG_DOUBLEFAULT
- /* Only save these if we are storing them,
- * This happens here, since L1 gets clobbered
- * below
- */
- GET_PDA(p0, r0);
- r0 = [p0 + PDA_DF_RETX];
- r1 = [p0 + PDA_DF_DCPLB];
- r2 = [p0 + PDA_DF_ICPLB];
- r3 = [p0 + PDA_DF_SEQSTAT];
- [p1 + PDA_INIT_DF_RETX] = r0;
- [p1 + PDA_INIT_DF_DCPLB] = r1;
- [p1 + PDA_INIT_DF_ICPLB] = r2;
- [p1 + PDA_INIT_DF_SEQSTAT] = r3;
-#endif
- [p1 + PDA_INIT_RETX] = r4;
-
- /* Initialize stack pointer */
- sp.l = lo(INITIAL_STACK);
- sp.h = hi(INITIAL_STACK);
- fp = sp;
- usp = sp;
-
- /* This section keeps the processor in supervisor mode
- * during core B startup. Branches to the idle task.
- */
-
- /* EVT15 = _real_start */
-
- p1.l = _coreb_start;
- p1.h = _coreb_start;
- [p5 + (EVT15 - COREMMR_BASE)] = p1;
- csync;
-
- r0 = EVT_IVG15 (z);
- sti r0;
-
- raise 15;
- p0.l = .LWAIT_HERE;
- p0.h = .LWAIT_HERE;
- reti = p0;
-#if defined(ANOMALY_05000281)
- nop; nop; nop;
-#endif
- rti;
-
-.LWAIT_HERE:
- jump .LWAIT_HERE;
-ENDPROC(_coreb_trampoline_start)
-
-#ifdef CONFIG_HOTPLUG_CPU
-.section ".text"
-ENTRY(_coreb_die)
- sp.l = lo(INITIAL_STACK);
- sp.h = hi(INITIAL_STACK);
- fp = sp;
- usp = sp;
-
- CLI R2;
- SSYNC;
- IDLE;
- STI R2;
-
- R0 = IWR_DISABLE_ALL;
- P0.H = hi(SYSMMR_BASE);
- P0.L = lo(SYSMMR_BASE);
- [P0 + (SICB_IWR0 - SYSMMR_BASE)] = R0;
- [P0 + (SICB_IWR1 - SYSMMR_BASE)] = R0;
- SSYNC;
-
- p0.h = hi(COREB_L1_CODE_START);
- p0.l = lo(COREB_L1_CODE_START);
- jump (p0);
-ENDPROC(_coreb_die)
-#endif
-
-__INIT
-ENTRY(_coreb_start)
- [--sp] = reti;
-
- p0.l = lo(WDOGB_CTL);
- p0.h = hi(WDOGB_CTL);
- r0 = 0xAD6(z);
- w[p0] = r0; /* Clear the watchdog. */
- ssync;
-
- /*
- * switch to IDLE stack.
- */
- p0.l = _secondary_stack;
- p0.h = _secondary_stack;
- sp = [p0];
- usp = sp;
- fp = sp;
-#ifdef CONFIG_HOTPLUG_CPU
- p0.l = _hotplug_coreb;
- p0.h = _hotplug_coreb;
- r0 = [p0];
- cc = BITTST(r0, 0);
- if cc jump 3f;
-#endif
- sp += -12;
- call _init_pda
- sp += 12;
-#ifdef CONFIG_HOTPLUG_CPU
-3:
-#endif
- call _secondary_start_kernel;
-.L_exit:
- jump.s .L_exit;
-ENDPROC(_coreb_start)
+++ /dev/null
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- * Philippe Gerum <rpm@xenomai.org>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/delay.h>
-#include <asm/smp.h>
-#include <asm/dma.h>
-#include <asm/time.h>
-
-static DEFINE_SPINLOCK(boot_lock);
-
-/*
- * platform_init_cpus() - Tell the world about how many cores we
- * have. This is called while setting up the architecture support
- * (setup_arch()), so don't be too demanding here with respect to
- * available kernel services.
- */
-
-void __init platform_init_cpus(void)
-{
- struct cpumask mask;
-
- cpumask_set_cpu(0, &mask); /* CoreA */
- cpumask_set_cpu(1, &mask); /* CoreB */
- init_cpu_possible(&mask);
-}
-
-void __init platform_prepare_cpus(unsigned int max_cpus)
-{
- struct cpumask mask;
-
- bfin_relocate_coreb_l1_mem();
-
- /* Both cores ought to be present on a bf561! */
- cpumask_set_cpu(0, &mask); /* CoreA */
- cpumask_set_cpu(1, &mask); /* CoreB */
- init_cpu_present(&mask);
-}
-
-int __init setup_profiling_timer(unsigned int multiplier) /* not supported */
-{
- return -EINVAL;
-}
-
-void platform_secondary_init(unsigned int cpu)
-{
- /* Clone setup for peripheral interrupt sources from CoreA. */
- bfin_write_SICB_IMASK0(bfin_read_SIC_IMASK0());
- bfin_write_SICB_IMASK1(bfin_read_SIC_IMASK1());
- SSYNC();
-
- /* Clone setup for IARs from CoreA. */
- bfin_write_SICB_IAR0(bfin_read_SIC_IAR0());
- bfin_write_SICB_IAR1(bfin_read_SIC_IAR1());
- bfin_write_SICB_IAR2(bfin_read_SIC_IAR2());
- bfin_write_SICB_IAR3(bfin_read_SIC_IAR3());
- bfin_write_SICB_IAR4(bfin_read_SIC_IAR4());
- bfin_write_SICB_IAR5(bfin_read_SIC_IAR5());
- bfin_write_SICB_IAR6(bfin_read_SIC_IAR6());
- bfin_write_SICB_IAR7(bfin_read_SIC_IAR7());
- bfin_write_SICB_IWR0(IWR_DISABLE_ALL);
- bfin_write_SICB_IWR1(IWR_DISABLE_ALL);
- SSYNC();
-
- /* We are done with local CPU inits, unblock the boot CPU. */
- spin_lock(&boot_lock);
- spin_unlock(&boot_lock);
-}
-
-int platform_boot_secondary(unsigned int cpu, struct task_struct *idle)
-{
- unsigned long timeout;
-
- printk(KERN_INFO "Booting Core B.\n");
-
- spin_lock(&boot_lock);
-
- if ((bfin_read_SYSCR() & COREB_SRAM_INIT) == 0) {
- /* CoreB already running, sending ipi to wakeup it */
- smp_send_reschedule(cpu);
- } else {
- /* Kick CoreB, which should start execution from CORE_SRAM_BASE. */
- bfin_write_SYSCR(bfin_read_SYSCR() & ~COREB_SRAM_INIT);
- SSYNC();
- }
-
- timeout = jiffies + HZ;
- /* release the lock and let coreb run */
- spin_unlock(&boot_lock);
- while (time_before(jiffies, timeout)) {
- if (cpu_online(cpu))
- break;
- udelay(100);
- barrier();
- }
-
- if (cpu_online(cpu)) {
- return 0;
- } else
- panic("CPU%u: processor failed to boot\n", cpu);
-}
-
-static const char supple0[] = "IRQ_SUPPLE_0";
-static const char supple1[] = "IRQ_SUPPLE_1";
-void __init platform_request_ipi(int irq, void *handler)
-{
- int ret;
- const char *name = (irq == IRQ_SUPPLE_0) ? supple0 : supple1;
-
- ret = request_irq(irq, handler, IRQF_PERCPU | IRQF_NO_SUSPEND |
- IRQF_FORCE_RESUME, name, handler);
- if (ret)
- panic("Cannot request %s for IPI service", name);
-}
-
-void platform_send_ipi(cpumask_t callmap, int irq)
-{
- unsigned int cpu;
- int offset = (irq == IRQ_SUPPLE_0) ? 6 : 8;
-
- for_each_cpu(cpu, &callmap) {
- BUG_ON(cpu >= 2);
- SSYNC();
- bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (offset + cpu)));
- SSYNC();
- }
-}
-
-void platform_send_ipi_cpu(unsigned int cpu, int irq)
-{
- int offset = (irq == IRQ_SUPPLE_0) ? 6 : 8;
- BUG_ON(cpu >= 2);
- SSYNC();
- bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (offset + cpu)));
- SSYNC();
-}
-
-void platform_clear_ipi(unsigned int cpu, int irq)
-{
- int offset = (irq == IRQ_SUPPLE_0) ? 10 : 12;
- BUG_ON(cpu >= 2);
- SSYNC();
- bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (offset + cpu)));
- SSYNC();
-}
-
-/*
- * Setup core B's local core timer.
- * In SMP, core timer is used for clock event device.
- */
-void bfin_local_timer_setup(void)
-{
-#if defined(CONFIG_TICKSOURCE_CORETMR)
- struct irq_data *data = irq_get_irq_data(IRQ_CORETMR);
- struct irq_chip *chip = irq_data_get_irq_chip(data);
-
- bfin_coretmr_init();
- bfin_coretmr_clockevent_init();
-
- chip->irq_unmask(data);
-#else
- /* Power down the core timer, just to play safe. */
- bfin_write_TCNTL(0);
-#endif
-
-}
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0
-config BF60x
- def_bool y
- depends on (BF609)
- select IRQ_PREFLOW_FASTEOI
-
-if (BF60x)
-
-source "arch/blackfin/mach-bf609/boards/Kconfig"
-
-menu "BF609 Specific Configuration"
-
-config SEC_IRQ_PRIORITY_LEVELS
- int "SEC interrupt priority levels"
- default 7
- range 0 7
- help
- Divide the total number of interrupt priority levels into sub-levels.
- There is 2 ^ (SEC_IRQ_PRIORITY_LEVELS + 1) different levels.
-
-config L1_PARITY_CHECK
- bool "Enable L1 parity check"
- default n
- help
- Enable the L1 parity check in L1 sram. A fault event is raised
- when L1 parity error is found.
-
-comment "System Cross Bar Priority Assignment"
-
-config SCB_PRIORITY
- bool "Init System Cross Bar Priority"
- default n
-
-menuconfig SCB0_MI0
- bool "SCB0 Master Interface 0 (DDR)"
- default n
- depends on SCB_PRIORITY
- help
- The slave interface id of each slot should be set according following table.
- Core 0 -- 0
- Core 1 -- 2
- SCB1 -- 9
- SCB2 -- 10
- SCB3 -- 11
- SCB4 -- 12
- SCB5 -- 5
- SCB6 -- 6
- SCB7 -- 8
- SCB8 -- 7
- SCB9 -- 4
- USB -- 13
-
-if SCB0_MI0
-
-config SCB0_MI0_SLOT0
- int "Slot 0 slave interface id"
- default 0
- range 0 13
-
-config SCB0_MI0_SLOT1
- int "Slot 1 slave interface id"
- default 2
- range 0 13
-
-config SCB0_MI0_SLOT2
- int "Slot 2 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI0_SLOT3
- int "Slot 3 slave interface id"
- default 5
- range 0 13
-
-config SCB0_MI0_SLOT4
- int "Slot 4 slave interface id"
- default 6
- range 0 13
-
-config SCB0_MI0_SLOT5
- int "Slot 5 slave interface id"
- default 7
- range 0 13
-
-config SCB0_MI0_SLOT6
- int "Slot 6 slave interface id"
- default 8
- range 0 13
-
-config SCB0_MI0_SLOT7
- int "Slot 7 slave interface id"
- default 9
- range 0 13
-
-config SCB0_MI0_SLOT8
- int "Slot 8 slave interface id"
- default 10
- range 0 13
-
-config SCB0_MI0_SLOT9
- int "Slot 9 slave interface id"
- default 11
- range 0 13
-
-config SCB0_MI0_SLOT10
- int "Slot 10 slave interface id"
- default 13
- range 0 13
-
-config SCB0_MI0_SLOT11
- int "Slot 11 slave interface id"
- default 12
- range 0 13
-
-config SCB0_MI0_SLOT12
- int "Slot 12 slave interface id"
- default 0
- range 0 13
-
-config SCB0_MI0_SLOT13
- int "Slot 13 slave interface id"
- default 2
- range 0 13
-
-config SCB0_MI0_SLOT14
- int "Slot 14 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI0_SLOT15
- int "Slot 15 slave interface id"
- default 5
- range 0 13
-
-config SCB0_MI0_SLOT16
- int "Slot 16 slave interface id"
- default 6
- range 0 13
-
-config SCB0_MI0_SLOT17
- int "Slot 17 slave interface id"
- default 7
- range 0 13
-
-config SCB0_MI0_SLOT18
- int "Slot 18 slave interface id"
- default 8
- range 0 13
-
-config SCB0_MI0_SLOT19
- int "Slot 19 slave interface id"
- default 9
- range 0 13
-
-config SCB0_MI0_SLOT20
- int "Slot 20 slave interface id"
- default 10
- range 0 13
-
-config SCB0_MI0_SLOT21
- int "Slot 21 slave interface id"
- default 11
- range 0 13
-
-config SCB0_MI0_SLOT22
- int "Slot 22 slave interface id"
- default 13
- range 0 13
-
-config SCB0_MI0_SLOT23
- int "Slot 23 slave interface id"
- default 12
- range 0 13
-
-config SCB0_MI0_SLOT24
- int "Slot 24 slave interface id"
- default 0
- range 0 13
-
-config SCB0_MI0_SLOT25
- int "Slot 25 slave interface id"
- default 2
- range 0 13
-
-config SCB0_MI0_SLOT26
- int "Slot 26 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI0_SLOT27
- int "Slot 27 slave interface id"
- default 5
- range 0 13
-
-config SCB0_MI0_SLOT28
- int "Slot 28 slave interface id"
- default 6
- range 0 13
-
-config SCB0_MI0_SLOT29
- int "Slot 29 slave interface id"
- default 7
- range 0 13
-
-config SCB0_MI0_SLOT30
- int "Slot 30 slave interface id"
- default 8
- range 0 13
-
-config SCB0_MI0_SLOT31
- int "Slot 31 slave interface id"
- default 13
- range 0 13
-
-endif # SCB0_MI0
-
-menuconfig SCB0_MI1
- bool "SCB0 Master Interface 1 (SMC)"
- default n
- depends on SCB_PRIORITY
- help
- The slave interface id of each slot should be set according following table.
- Core 0 -- 0
- Core 1 -- 2
- SCB1 -- 9
- SCB2 -- 10
- SCB3 -- 11
- SCB4 -- 12
- SCB5 -- 5
- SCB6 -- 6
- SCB7 -- 8
- SCB8 -- 7
- SCB9 -- 4
- USB -- 13
-
-if SCB0_MI1
-
-config SCB0_MI1_SLOT0
- int "Slot 0 slave interface id"
- default 0
- range 0 13
-
-config SCB0_MI1_SLOT1
- int "Slot 1 slave interface id"
- default 2
- range 0 13
-
-config SCB0_MI1_SLOT2
- int "Slot 2 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI1_SLOT3
- int "Slot 3 slave interface id"
- default 5
- range 0 13
-
-config SCB0_MI1_SLOT4
- int "Slot 4 slave interface id"
- default 6
- range 0 13
-
-config SCB0_MI1_SLOT5
- int "Slot 5 slave interface id"
- default 7
- range 0 13
-
-config SCB0_MI1_SLOT6
- int "Slot 6 slave interface id"
- default 8
- range 0 13
-
-config SCB0_MI1_SLOT7
- int "Slot 7 slave interface id"
- default 9
- range 0 13
-
-config SCB0_MI1_SLOT8
- int "Slot 8 slave interface id"
- default 10
- range 0 13
-
-config SCB0_MI1_SLOT9
- int "Slot 9 slave interface id"
- default 11
- range 0 13
-
-config SCB0_MI1_SLOT10
- int "Slot 10 slave interface id"
- default 13
- range 0 13
-
-config SCB0_MI1_SLOT11
- int "Slot 11 slave interface id"
- default 12
- range 0 13
-
-config SCB0_MI1_SLOT12
- int "Slot 12 slave interface id"
- default 0
- range 0 13
-
-config SCB0_MI1_SLOT13
- int "Slot 13 slave interface id"
- default 2
- range 0 13
-
-config SCB0_MI1_SLOT14
- int "Slot 14 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI1_SLOT15
- int "Slot 15 slave interface id"
- default 5
- range 0 13
-
-config SCB0_MI1_SLOT16
- int "Slot 16 slave interface id"
- default 6
- range 0 13
-
-config SCB0_MI1_SLOT17
- int "Slot 17 slave interface id"
- default 7
- range 0 13
-
-config SCB0_MI1_SLOT18
- int "Slot 18 slave interface id"
- default 8
- range 0 13
-
-config SCB0_MI1_SLOT19
- int "Slot 19 slave interface id"
- default 9
- range 0 13
-
-config SCB0_MI1_SLOT20
- int "Slot 20 slave interface id"
- default 10
- range 0 13
-
-config SCB0_MI1_SLOT21
- int "Slot 21 slave interface id"
- default 11
- range 0 13
-
-config SCB0_MI1_SLOT22
- int "Slot 22 slave interface id"
- default 13
- range 0 13
-
-config SCB0_MI1_SLOT23
- int "Slot 23 slave interface id"
- default 12
- range 0 13
-
-config SCB0_MI1_SLOT24
- int "Slot 24 slave interface id"
- default 0
- range 0 13
-
-config SCB0_MI1_SLOT25
- int "Slot 25 slave interface id"
- default 2
- range 0 13
-
-config SCB0_MI1_SLOT26
- int "Slot 26 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI1_SLOT27
- int "Slot 27 slave interface id"
- default 5
- range 0 13
-
-config SCB0_MI1_SLOT28
- int "Slot 28 slave interface id"
- default 6
- range 0 13
-
-config SCB0_MI1_SLOT29
- int "Slot 29 slave interface id"
- default 7
- range 0 13
-
-config SCB0_MI1_SLOT30
- int "Slot 30 slave interface id"
- default 8
- range 0 13
-
-config SCB0_MI1_SLOT31
- int "Slot 31 slave interface id"
- default 13
- range 0 13
-
-endif # SCB0_MI1
-
-menuconfig SCB0_MI2
- bool "SCB0 Master Interface 2 (Data L2)"
- default n
- depends on SCB_PRIORITY
- help
- The slave interface id of each slot should be set according following table.
- Core 0 -- 0
- Core 1 -- 2
- SCB1 -- 9
- SCB2 -- 10
- SCB3 -- 11
- SCB4 -- 12
- SCB5 -- 5
- SCB6 -- 6
- SCB7 -- 8
- SCB8 -- 7
- SCB9 -- 4
- USB -- 13
-
-if SCB0_MI2
-
-config SCB0_MI2_SLOT0
- int "Slot 0 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI2_SLOT1
- int "Slot 1 slave interface id"
- default 5
- range 0 13
-
-config SCB0_MI2_SLOT2
- int "Slot 2 slave interface id"
- default 6
- range 0 13
-
-config SCB0_MI2_SLOT3
- int "Slot 3 slave interface id"
- default 7
- range 0 13
-
-config SCB0_MI2_SLOT4
- int "Slot 4 slave interface id"
- default 8
- range 0 13
-
-config SCB0_MI2_SLOT5
- int "Slot 5 slave interface id"
- default 9
- range 0 13
-
-config SCB0_MI2_SLOT6
- int "Slot 6 slave interface id"
- default 10
- range 0 13
-
-config SCB0_MI2_SLOT7
- int "Slot 7 slave interface id"
- default 11
- range 0 13
-
-config SCB0_MI2_SLOT8
- int "Slot 8 slave interface id"
- default 13
- range 0 13
-
-config SCB0_MI2_SLOT9
- int "Slot 9 slave interface id"
- default 12
- range 0 13
-
-config SCB0_MI2_SLOT10
- int "Slot 10 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI2_SLOT11
- int "Slot 11 slave interface id"
- default 5
- range 0 13
-
-config SCB0_MI2_SLOT12
- int "Slot 12 slave interface id"
- default 6
- range 0 13
-
-config SCB0_MI2_SLOT13
- int "Slot 13 slave interface id"
- default 7
- range 0 13
-
-config SCB0_MI2_SLOT14
- int "Slot 14 slave interface id"
- default 8
- range 0 13
-
-config SCB0_MI2_SLOT15
- int "Slot 15 slave interface id"
- default 9
- range 0 13
-
-config SCB0_MI2_SLOT16
- int "Slot 16 slave interface id"
- default 10
- range 0 13
-
-config SCB0_MI2_SLOT17
- int "Slot 17 slave interface id"
- default 11
- range 0 13
-
-config SCB0_MI2_SLOT18
- int "Slot 18 slave interface id"
- default 13
- range 0 13
-
-config SCB0_MI2_SLOT19
- int "Slot 19 slave interface id"
- default 12
- range 0 13
-
-config SCB0_MI2_SLOT20
- int "Slot 20 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI2_SLOT21
- int "Slot 21 slave interface id"
- default 5
- range 0 13
-
-config SCB0_MI2_SLOT22
- int "Slot 22 slave interface id"
- default 6
- range 0 13
-
-config SCB0_MI2_SLOT23
- int "Slot 23 slave interface id"
- default 7
- range 0 13
-
-config SCB0_MI2_SLOT24
- int "Slot 24 slave interface id"
- default 8
- range 0 13
-
-config SCB0_MI2_SLOT25
- int "Slot 25 slave interface id"
- default 9
- range 0 13
-
-config SCB0_MI2_SLOT26
- int "Slot 26 slave interface id"
- default 10
- range 0 13
-
-config SCB0_MI2_SLOT27
- int "Slot 27 slave interface id"
- default 11
- range 0 13
-
-config SCB0_MI2_SLOT28
- int "Slot 28 slave interface id"
- default 13
- range 0 13
-
-config SCB0_MI2_SLOT29
- int "Slot 29 slave interface id"
- default 12
- range 0 13
-
-config SCB0_MI2_SLOT30
- int "Slot 30 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI2_SLOT31
- int "Slot 31 slave interface id"
- default 7
- range 0 13
-
-endif # SCB0_MI2
-
-menuconfig SCB0_MI3
- bool "SCB0 Master Interface 3 (L1A)"
- default n
- depends on SCB_PRIORITY
- help
- The slave interface id of each slot should be set according following table.
- Core 0 -- 0
- Core 1 -- 2
- SCB1 -- 9
- SCB2 -- 10
- SCB3 -- 11
- SCB4 -- 12
- SCB5 -- 5
- SCB6 -- 6
- SCB7 -- 8
- SCB8 -- 7
- SCB9 -- 4
- USB -- 13
-
-if SCB0_MI3
-
-config SCB0_MI3_SLOT0
- int "Slot 0 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI3_SLOT1
- int "Slot 1 slave interface id"
- default 5
- range 0 13
-
-config SCB0_MI3_SLOT2
- int "Slot 2 slave interface id"
- default 6
- range 0 13
-
-config SCB0_MI3_SLOT3
- int "Slot 3 slave interface id"
- default 7
- range 0 13
-
-config SCB0_MI3_SLOT4
- int "Slot 4 slave interface id"
- default 8
- range 0 13
-
-config SCB0_MI3_SLOT5
- int "Slot 5 slave interface id"
- default 9
- range 0 13
-
-config SCB0_MI3_SLOT6
- int "Slot 6 slave interface id"
- default 10
- range 0 13
-
-config SCB0_MI3_SLOT7
- int "Slot 7 slave interface id"
- default 11
- range 0 13
-
-config SCB0_MI3_SLOT8
- int "Slot 8 slave interface id"
- default 13
- range 0 13
-
-config SCB0_MI3_SLOT9
- int "Slot 9 slave interface id"
- default 12
- range 0 13
-
-config SCB0_MI3_SLOT10
- int "Slot 10 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI3_SLOT11
- int "Slot 11 slave interface id"
- default 5
- range 0 13
-
-config SCB0_MI3_SLOT12
- int "Slot 12 slave interface id"
- default 6
- range 0 13
-
-config SCB0_MI3_SLOT13
- int "Slot 13 slave interface id"
- default 7
- range 0 13
-
-config SCB0_MI3_SLOT14
- int "Slot 14 slave interface id"
- default 8
- range 0 13
-
-config SCB0_MI3_SLOT15
- int "Slot 15 slave interface id"
- default 9
- range 0 13
-
-config SCB0_MI3_SLOT16
- int "Slot 16 slave interface id"
- default 10
- range 0 13
-
-config SCB0_MI3_SLOT17
- int "Slot 17 slave interface id"
- default 11
- range 0 13
-
-config SCB0_MI3_SLOT18
- int "Slot 18 slave interface id"
- default 13
- range 0 13
-
-config SCB0_MI3_SLOT19
- int "Slot 19 slave interface id"
- default 12
- range 0 13
-
-config SCB0_MI3_SLOT20
- int "Slot 20 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI3_SLOT21
- int "Slot 21 slave interface id"
- default 5
- range 0 13
-
-config SCB0_MI3_SLOT22
- int "Slot 22 slave interface id"
- default 6
- range 0 13
-
-config SCB0_MI3_SLOT23
- int "Slot 23 slave interface id"
- default 7
- range 0 13
-
-config SCB0_MI3_SLOT24
- int "Slot 24 slave interface id"
- default 8
- range 0 13
-
-config SCB0_MI3_SLOT25
- int "Slot 25 slave interface id"
- default 9
- range 0 13
-
-config SCB0_MI3_SLOT26
- int "Slot 26 slave interface id"
- default 10
- range 0 13
-
-config SCB0_MI3_SLOT27
- int "Slot 27 slave interface id"
- default 11
- range 0 13
-
-config SCB0_MI3_SLOT28
- int "Slot 28 slave interface id"
- default 13
- range 0 13
-
-config SCB0_MI3_SLOT29
- int "Slot 29 slave interface id"
- default 12
- range 0 13
-
-config SCB0_MI3_SLOT30
- int "Slot 30 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI3_SLOT31
- int "Slot 31 slave interface id"
- default 7
- range 0 13
-
-endif # SCB0_MI3
-
-menuconfig SCB0_MI4
- bool "SCB0 Master Interface 4 (L1B)"
- default n
- depends on SCB_PRIORITY
- help
- The slave interface id of each slot should be set according following table.
- Core 0 -- 0
- Core 1 -- 2
- SCB1 -- 9
- SCB2 -- 10
- SCB3 -- 11
- SCB4 -- 12
- SCB5 -- 5
- SCB6 -- 6
- SCB7 -- 8
- SCB8 -- 7
- SCB9 -- 4
- USB -- 13
-
-if SCB0_MI4
-
-config SCB0_MI4_SLOT0
- int "Slot 0 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI4_SLOT1
- int "Slot 1 slave interface id"
- default 5
- range 0 13
-
-config SCB0_MI4_SLOT2
- int "Slot 2 slave interface id"
- default 6
- range 0 13
-
-config SCB0_MI4_SLOT3
- int "Slot 3 slave interface id"
- default 7
- range 0 13
-
-config SCB0_MI4_SLOT4
- int "Slot 4 slave interface id"
- default 8
- range 0 13
-
-config SCB0_MI4_SLOT5
- int "Slot 5 slave interface id"
- default 9
- range 0 13
-
-config SCB0_MI4_SLOT6
- int "Slot 6 slave interface id"
- default 10
- range 0 13
-
-config SCB0_MI4_SLOT7
- int "Slot 7 slave interface id"
- default 11
- range 0 13
-
-config SCB0_MI4_SLOT8
- int "Slot 8 slave interface id"
- default 13
- range 0 13
-
-config SCB0_MI4_SLOT9
- int "Slot 9 slave interface id"
- default 12
- range 0 13
-
-config SCB0_MI4_SLOT10
- int "Slot 10 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI4_SLOT11
- int "Slot 11 slave interface id"
- default 5
- range 0 13
-
-config SCB0_MI4_SLOT12
- int "Slot 12 slave interface id"
- default 6
- range 0 13
-
-config SCB0_MI4_SLOT13
- int "Slot 13 slave interface id"
- default 7
- range 0 13
-
-config SCB0_MI4_SLOT14
- int "Slot 14 slave interface id"
- default 8
- range 0 13
-
-config SCB0_MI4_SLOT15
- int "Slot 15 slave interface id"
- default 9
- range 0 13
-
-config SCB0_MI4_SLOT16
- int "Slot 16 slave interface id"
- default 10
- range 0 13
-
-config SCB0_MI4_SLOT17
- int "Slot 17 slave interface id"
- default 11
- range 0 13
-
-config SCB0_MI4_SLOT18
- int "Slot 18 slave interface id"
- default 13
- range 0 13
-
-config SCB0_MI4_SLOT19
- int "Slot 19 slave interface id"
- default 12
- range 0 13
-
-config SCB0_MI4_SLOT20
- int "Slot 20 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI4_SLOT21
- int "Slot 21 slave interface id"
- default 5
- range 0 13
-
-config SCB0_MI4_SLOT22
- int "Slot 22 slave interface id"
- default 6
- range 0 13
-
-config SCB0_MI4_SLOT23
- int "Slot 23 slave interface id"
- default 7
- range 0 13
-
-config SCB0_MI4_SLOT24
- int "Slot 24 slave interface id"
- default 8
- range 0 13
-
-config SCB0_MI4_SLOT25
- int "Slot 25 slave interface id"
- default 9
- range 0 13
-
-config SCB0_MI4_SLOT26
- int "Slot 26 slave interface id"
- default 10
- range 0 13
-
-config SCB0_MI4_SLOT27
- int "Slot 27 slave interface id"
- default 11
- range 0 13
-
-config SCB0_MI4_SLOT28
- int "Slot 28 slave interface id"
- default 13
- range 0 13
-
-config SCB0_MI4_SLOT29
- int "Slot 29 slave interface id"
- default 12
- range 0 13
-
-config SCB0_MI4_SLOT30
- int "Slot 30 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI4_SLOT31
- int "Slot 31 slave interface id"
- default 7
- range 0 13
-
-endif # SCB0_MI4
-
-menuconfig SCB0_MI5
- bool "SCB0 Master Interface 5 (SMMR)"
- default n
- depends on SCB_PRIORITY
- help
- The slave interface id of each slot should be set according following table.
- MMR0 -- 1
- MMR1 -- 3
- SCB2 -- 10
- SCB4 -- 12
-
-if SCB0_MI5
-
-config SCB0_MI5_SLOT0
- int "Slot 0 slave interface id"
- default 1
- range 0 13
-
-config SCB0_MI5_SLOT1
- int "Slot 1 slave interface id"
- default 3
- range 0 13
-
-config SCB0_MI5_SLOT2
- int "Slot 2 slave interface id"
- default 10
- range 0 13
-
-config SCB0_MI5_SLOT3
- int "Slot 3 slave interface id"
- default 12
- range 0 13
-
-config SCB0_MI5_SLOT4
- int "Slot 4 slave interface id"
- default 1
- range 0 13
-
-config SCB0_MI5_SLOT5
- int "Slot 5 slave interface id"
- default 3
- range 0 13
-
-config SCB0_MI5_SLOT6
- int "Slot 6 slave interface id"
- default 10
- range 0 13
-
-config SCB0_MI5_SLOT7
- int "Slot 7 slave interface id"
- default 12
- range 0 13
-
-config SCB0_MI5_SLOT8
- int "Slot 8 slave interface id"
- default 1
- range 0 13
-
-config SCB0_MI5_SLOT9
- int "Slot 9 slave interface id"
- default 3
- range 0 13
-
-config SCB0_MI5_SLOT10
- int "Slot 10 slave interface id"
- default 10
- range 0 13
-
-config SCB0_MI5_SLOT11
- int "Slot 11 slave interface id"
- default 12
- range 0 13
-
-config SCB0_MI5_SLOT12
- int "Slot 12 slave interface id"
- default 1
- range 0 13
-
-config SCB0_MI5_SLOT13
- int "Slot 13 slave interface id"
- default 3
- range 0 13
-
-config SCB0_MI5_SLOT14
- int "Slot 14 slave interface id"
- default 10
- range 0 13
-
-config SCB0_MI5_SLOT15
- int "Slot 15 slave interface id"
- default 12
- range 0 13
-
-endif # SCB0_MI5
-
-menuconfig SCB1_MI0
- bool "SCB1 Master Interface 0"
- default n
- depends on SCB_PRIORITY
- help
- The slave interface id of each slot should be set according following table.
- SPORT0A -- 0
- SPORT0B -- 1
- SPORT1A -- 2
- SPORT1B -- 3
- SPORT2A -- 4
- SPORT2B -- 5
- SPI0TX -- 6
- SPI0RX -- 7
- SPI1TX -- 8
- SPI1RX -- 9
-
-if SCB1_MI0
-
-config SCB1_MI0_SLOT0
- int "Slot 0 slave interface id"
- default 0
- range 0 9
-
-config SCB1_MI0_SLOT1
- int "Slot 1 slave interface id"
- default 1
- range 0 9
-
-config SCB1_MI0_SLOT2
- int "Slot 2 slave interface id"
- default 2
- range 0 9
-
-config SCB1_MI0_SLOT3
- int "Slot 3 slave interface id"
- default 3
- range 0 9
-
-config SCB1_MI0_SLOT4
- int "Slot 4 slave interface id"
- default 4
- range 0 9
-
-config SCB1_MI0_SLOT5
- int "Slot 5 slave interface id"
- default 5
- range 0 9
-
-config SCB1_MI0_SLOT6
- int "Slot 6 slave interface id"
- default 6
- range 0 9
-
-config SCB1_MI0_SLOT7
- int "Slot 7 slave interface id"
- default 7
- range 0 9
-
-config SCB1_MI0_SLOT8
- int "Slot 8 slave interface id"
- default 8
- range 0 9
-
-config SCB1_MI0_SLOT9
- int "Slot 9 slave interface id"
- default 9
- range 0 9
-
-config SCB1_MI0_SLOT10
- int "Slot 10 slave interface id"
- default 0
- range 0 9
-
-config SCB1_MI0_SLOT11
- int "Slot 11 slave interface id"
- default 1
- range 0 9
-
-config SCB1_MI0_SLOT12
- int "Slot 12 slave interface id"
- default 2
- range 0 9
-
-config SCB1_MI0_SLOT13
- int "Slot 13 slave interface id"
- default 3
- range 0 9
-
-config SCB1_MI0_SLOT14
- int "Slot 14 slave interface id"
- default 4
- range 0 9
-
-config SCB1_MI0_SLOT15
- int "Slot 15 slave interface id"
- default 5
- range 0 9
-
-config SCB1_MI0_SLOT16
- int "Slot 16 slave interface id"
- default 6
- range 0 13
-
-config SCB1_MI0_SLOT17
- int "Slot 17 slave interface id"
- default 7
- range 0 13
-
-config SCB1_MI0_SLOT18
- int "Slot 18 slave interface id"
- default 8
- range 0 13
-
-config SCB1_MI0_SLOT19
- int "Slot 19 slave interface id"
- default 9
- range 0 13
-
-endif # SCB1_MI0
-
-menuconfig SCB2_MI0
- bool "SCB2 Master Interface 0"
- default n
- depends on SCB_PRIORITY
- help
- The slave interface id of each slot should be set according following table.
- RSI -- 0
- SDU DMA -- 1
- SDU -- 2
- EMAC0 -- 3
- EMAC1 -- 4
-
-if SCB2_MI0
-
-config SCB2_MI0_SLOT0
- int "Slot 0 slave interface id"
- default 0
- range 0 4
-
-config SCB2_MI0_SLOT1
- int "Slot 1 slave interface id"
- default 1
- range 0 4
-
-config SCB2_MI0_SLOT2
- int "Slot 2 slave interface id"
- default 2
- range 0 4
-
-config SCB2_MI0_SLOT3
- int "Slot 3 slave interface id"
- default 3
- range 0 4
-
-config SCB2_MI0_SLOT4
- int "Slot 4 slave interface id"
- default 4
- range 0 4
-
-config SCB2_MI0_SLOT5
- int "Slot 5 slave interface id"
- default 0
- range 0 4
-
-config SCB2_MI0_SLOT6
- int "Slot 6 slave interface id"
- default 1
- range 0 4
-
-config SCB2_MI0_SLOT7
- int "Slot 7 slave interface id"
- default 2
- range 0 4
-
-config SCB2_MI0_SLOT8
- int "Slot 8 slave interface id"
- default 3
- range 0 4
-
-config SCB2_MI0_SLOT9
- int "Slot 9 slave interface id"
- default 4
- range 0 4
-
-endif # SCB2_MI0
-
-menuconfig SCB3_MI0
- bool "SCB3 Master Interface 0"
- default n
- depends on SCB_PRIORITY
- help
- The slave interface id of each slot should be set according following table.
- LP0 -- 0
- LP1 -- 1
- LP2 -- 2
- LP3 -- 3
- UART0TX -- 4
- UART0RX -- 5
- UART1TX -- 4
- UART1RX -- 5
-
-if SCB3_MI0
-
-config SCB3_MI0_SLOT0
- int "Slot 0 slave interface id"
- default 0
- range 0 7
-
-config SCB3_MI0_SLOT1
- int "Slot 1 slave interface id"
- default 1
- range 0 7
-
-config SCB3_MI0_SLOT2
- int "Slot 2 slave interface id"
- default 2
- range 0 7
-
-config SCB3_MI0_SLOT3
- int "Slot 3 slave interface id"
- default 3
- range 0 7
-
-config SCB3_MI0_SLOT4
- int "Slot 4 slave interface id"
- default 4
- range 0 7
-
-config SCB3_MI0_SLOT5
- int "Slot 5 slave interface id"
- default 5
- range 0 7
-
-config SCB3_MI0_SLOT6
- int "Slot 6 slave interface id"
- default 6
- range 0 7
-
-config SCB3_MI0_SLOT7
- int "Slot 7 slave interface id"
- default 7
- range 0 7
-
-config SCB3_MI0_SLOT8
- int "Slot 8 slave interface id"
- default 0
- range 0 7
-
-config SCB3_MI0_SLOT9
- int "Slot 9 slave interface id"
- default 1
- range 0 7
-
-config SCB3_MI0_SLOT10
- int "Slot 10 slave interface id"
- default 2
- range 0 7
-
-config SCB3_MI0_SLOT11
- int "Slot 11 slave interface id"
- default 3
- range 0 7
-
-config SCB3_MI0_SLOT12
- int "Slot 12 slave interface id"
- default 4
- range 0 7
-
-config SCB3_MI0_SLOT13
- int "Slot 13 slave interface id"
- default 5
- range 0 7
-
-config SCB3_MI0_SLOT14
- int "Slot 14 slave interface id"
- default 6
- range 0 7
-
-config SCB3_MI0_SLOT15
- int "Slot 15 slave interface id"
- default 7
- range 0 7
-
-endif # SCB3_MI0
-
-menuconfig SCB4_MI0
- bool "SCB4 Master Interface 0"
- default n
- depends on SCB_PRIORITY
- help
- The slave interface id of each slot should be set according following table.
- MDA21 -- 0
- MDA22 -- 1
- MDA23 -- 2
- MDA24 -- 3
- MDA25 -- 4
- MDA26 -- 5
- MDA27 -- 6
- MDA28 -- 7
-
-if SCB4_MI0
-
-config SCB4_MI0_SLOT0
- int "Slot 0 slave interface id"
- default 0
- range 0 7
-
-config SCB4_MI0_SLOT1
- int "Slot 1 slave interface id"
- default 1
- range 0 7
-
-config SCB4_MI0_SLOT2
- int "Slot 2 slave interface id"
- default 2
- range 0 7
-
-config SCB4_MI0_SLOT3
- int "Slot 3 slave interface id"
- default 3
- range 0 7
-
-config SCB4_MI0_SLOT4
- int "Slot 4 slave interface id"
- default 4
- range 0 7
-
-config SCB4_MI0_SLOT5
- int "Slot 5 slave interface id"
- default 5
- range 0 7
-
-config SCB4_MI0_SLOT6
- int "Slot 6 slave interface id"
- default 6
- range 0 7
-
-config SCB4_MI0_SLOT7
- int "Slot 7 slave interface id"
- default 7
- range 0 7
-
-config SCB4_MI0_SLOT8
- int "Slot 8 slave interface id"
- default 0
- range 0 7
-
-config SCB4_MI0_SLOT9
- int "Slot 9 slave interface id"
- default 1
- range 0 7
-
-config SCB4_MI0_SLOT10
- int "Slot 10 slave interface id"
- default 2
- range 0 7
-
-config SCB4_MI0_SLOT11
- int "Slot 11 slave interface id"
- default 3
- range 0 7
-
-config SCB4_MI0_SLOT12
- int "Slot 12 slave interface id"
- default 4
- range 0 7
-
-config SCB4_MI0_SLOT13
- int "Slot 13 slave interface id"
- default 5
- range 0 7
-
-config SCB4_MI0_SLOT14
- int "Slot 14 slave interface id"
- default 6
- range 0 7
-
-config SCB4_MI0_SLOT15
- int "Slot 15 slave interface id"
- default 7
- range 0 7
-
-endif # SCB4_MI0
-
-menuconfig SCB5_MI0
- bool "SCB5 Master Interface 0"
- default n
- depends on SCB_PRIORITY
- help
- The slave interface id of each slot should be set according following table.
- PPI0 MDA29 -- 0
- PPI0 MDA30 -- 1
- PPI2 MDA31 -- 2
- PPI2 MDA32 -- 3
-
-if SCB5_MI0
-
-config SCB5_MI0_SLOT0
- int "Slot 0 slave interface id"
- default 0
- range 0 3
-
-config SCB5_MI0_SLOT1
- int "Slot 1 slave interface id"
- default 1
- range 0 3
-
-config SCB5_MI0_SLOT2
- int "Slot 2 slave interface id"
- default 2
- range 0 3
-
-config SCB5_MI0_SLOT3
- int "Slot 3 slave interface id"
- default 3
- range 0 3
-
-config SCB5_MI0_SLOT4
- int "Slot 4 slave interface id"
- default 0
- range 0 3
-
-config SCB5_MI0_SLOT5
- int "Slot 5 slave interface id"
- default 1
- range 0 3
-
-config SCB5_MI0_SLOT6
- int "Slot 6 slave interface id"
- default 2
- range 0 3
-
-config SCB5_MI0_SLOT7
- int "Slot 7 slave interface id"
- default 3
- range 0 3
-
-endif # SCB5_MI0
-
-menuconfig SCB6_MI0
- bool "SCB6 Master Interface 0"
- default n
- depends on SCB_PRIORITY
- help
- The slave interface id of each slot should be set according following table.
- PPI1 MDA33 -- 0
- PPI1 MDA34 -- 1
-
-if SCB6_MI0
-
-config SCB6_MI0_SLOT0
- int "Slot 0 slave interface id"
- default 0
- range 0 1
-
-config SCB6_MI0_SLOT1
- int "Slot 1 slave interface id"
- default 1
- range 0 1
-
-config SCB6_MI0_SLOT2
- int "Slot 2 slave interface id"
- default 0
- range 0 1
-
-config SCB6_MI0_SLOT3
- int "Slot 3 slave interface id"
- default 1
- range 0 1
-
-endif # SCB6_MI0
-
-menuconfig SCB7_MI0
- bool "SCB7 Master Interface 0"
- default n
- depends on SCB_PRIORITY
- help
- The slave interface id of each slot should be set according following table.
- PIXC0 -- 0
- PIXC1 -- 1
- PIXC2 -- 2
-
-if SCB7_MI0
-
-config SCB7_MI0_SLOT0
- int "Slot 0 slave interface id"
- default 0
- range 0 2
-
-config SCB7_MI0_SLOT1
- int "Slot 1 slave interface id"
- default 1
- range 0 2
-
-config SCB7_MI0_SLOT2
- int "Slot 2 slave interface id"
- default 2
- range 0 2
-
-config SCB7_MI0_SLOT3
- int "Slot 3 slave interface id"
- default 0
- range 0 2
-
-config SCB7_MI0_SLOT4
- int "Slot 4 slave interface id"
- default 1
- range 0 2
-
-config SCB7_MI0_SLOT5
- int "Slot 5 slave interface id"
- default 2
- range 0 2
-
-endif # SCB7_MI0
-
-menuconfig SCB8_MI0
- bool "SCB8 Master Interface 0"
- default n
- depends on SCB_PRIORITY
- help
- The slave interface id of each slot should be set according following table.
- PVP CPDOB -- 0
- PVP CPDOC -- 1
- PVP CPCO -- 2
- PVP CPCI -- 3
-
-if SCB8_MI0
-
-config SCB8_MI0_SLOT0
- int "Slot 0 slave interface id"
- default 0
- range 0 3
-
-config SCB8_MI0_SLOT1
- int "Slot 1 slave interface id"
- default 1
- range 0 3
-
-config SCB8_MI0_SLOT2
- int "Slot 2 slave interface id"
- default 2
- range 0 3
-
-config SCB8_MI0_SLOT3
- int "Slot 3 slave interface id"
- default 3
- range 0 3
-
-config SCB8_MI0_SLOT4
- int "Slot 4 slave interface id"
- default 0
- range 0 3
-
-config SCB8_MI0_SLOT5
- int "Slot 5 slave interface id"
- default 1
- range 0 3
-
-config SCB8_MI0_SLOT6
- int "Slot 6 slave interface id"
- default 2
- range 0 3
-
-config SCB8_MI0_SLOT7
- int "Slot 7 slave interface id"
- default 3
- range 0 3
-
-endif # SCB8_MI0
-
-menuconfig SCB9_MI0
- bool "SCB9 Master Interface 0"
- default n
- depends on SCB_PRIORITY
- help
- The slave interface id of each slot should be set according following table.
- PVP MPDO -- 0
- PVP MPDI -- 1
- PVP MPCO -- 2
- PVP MPCI -- 3
- PVP CPDOA -- 4
-
-if SCB9_MI0
-
-config SCB9_MI0_SLOT0
- int "Slot 0 slave interface id"
- default 0
- range 0 4
-
-config SCB9_MI0_SLOT1
- int "Slot 1 slave interface id"
- default 1
- range 0 4
-
-config SCB9_MI0_SLOT2
- int "Slot 2 slave interface id"
- default 2
- range 0 4
-
-config SCB9_MI0_SLOT3
- int "Slot 3 slave interface id"
- default 3
- range 0 4
-
-config SCB9_MI0_SLOT4
- int "Slot 4 slave interface id"
- default 4
- range 0 4
-
-config SCB9_MI0_SLOT5
- int "Slot 5 slave interface id"
- default 0
- range 0 4
-
-config SCB9_MI0_SLOT6
- int "Slot 6 slave interface id"
- default 1
- range 0 4
-
-config SCB9_MI0_SLOT7
- int "Slot 7 slave interface id"
- default 2
- range 0 4
-
-config SCB9_MI0_SLOT8
- int "Slot 8 slave interface id"
- default 3
- range 0 4
-
-config SCB9_MI0_SLOT9
- int "Slot 9 slave interface id"
- default 4
- range 0 4
-
-endif # SCB9_MI0
-
-endmenu
-
-endif
+++ /dev/null
-#
-# arch/blackfin/mach-bf609/Makefile
-#
-
-obj-y := dma.o clock.o ints-priority.o
-obj-$(CONFIG_PM) += pm.o dpm.o
-obj-$(CONFIG_SCB_PRIORITY) += scb.o
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0
-choice
- prompt "System type"
- default BFIN609_EZKIT
- help
- Select your board!
-
-config BFIN609_EZKIT
- bool "BF609-EZKIT"
- help
- BFIN609-EZKIT board support.
-
-endchoice
+++ /dev/null
-#
-# arch/blackfin/mach-bf609/boards/Makefile
-#
-
-obj-$(CONFIG_BFIN609_EZKIT) += ezkit.o
+++ /dev/null
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <linux/irq.h>
-#include <linux/i2c.h>
-#include <linux/interrupt.h>
-#include <linux/usb/musb.h>
-#include <linux/pinctrl/machine.h>
-#include <linux/pinctrl/pinconf-generic.h>
-#include <linux/platform_data/pinctrl-adi2.h>
-#include <linux/spi/adi_spi3.h>
-#include <linux/gpio.h>
-#include <asm/dma.h>
-#include <asm/nand.h>
-#include <asm/dpmc.h>
-#include <asm/portmux.h>
-#include <asm/bfin_sdh.h>
-#include <linux/input.h>
-#include <linux/spi/ad7877.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "ADI BF609-EZKIT";
-
-/*
- * Driver needs to know address, irq and flag pin.
- */
-
-#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
-#include <linux/usb/isp1760.h>
-static struct resource bfin_isp1760_resources[] = {
- [0] = {
- .start = 0x2C0C0000,
- .end = 0x2C0C0000 + 0xfffff,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_PG7,
- .end = IRQ_PG7,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct isp1760_platform_data isp1760_priv = {
- .is_isp1761 = 0,
- .bus_width_16 = 1,
- .port1_otg = 0,
- .analog_oc = 0,
- .dack_polarity_high = 0,
- .dreq_polarity_high = 0,
-};
-
-static struct platform_device bfin_isp1760_device = {
- .name = "isp1760",
- .id = 0,
- .dev = {
- .platform_data = &isp1760_priv,
- },
- .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
- .resource = bfin_isp1760_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_BFIN_ROTARY)
-#include <linux/platform_data/bfin_rotary.h>
-
-static struct bfin_rotary_platform_data bfin_rotary_data = {
- /*.rotary_up_key = KEY_UP,*/
- /*.rotary_down_key = KEY_DOWN,*/
- .rotary_rel_code = REL_WHEEL,
- .rotary_button_key = KEY_ENTER,
- .debounce = 10, /* 0..17 */
- .mode = ROT_QUAD_ENC | ROT_DEBE,
-};
-
-static struct resource bfin_rotary_resources[] = {
- {
- .start = CNT_CONFIG,
- .end = CNT_CONFIG + 0xff,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_CNT,
- .end = IRQ_CNT,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_rotary_device = {
- .name = "bfin-rotary",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_rotary_resources),
- .resource = bfin_rotary_resources,
- .dev = {
- .platform_data = &bfin_rotary_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_STMMAC_ETH)
-#include <linux/stmmac.h>
-#include <linux/phy.h>
-
-static struct stmmac_mdio_bus_data phy_private_data = {
- .phy_mask = 1,
-};
-
-static struct stmmac_dma_cfg eth_dma_cfg = {
- .pbl = 2,
-};
-
-int stmmac_ptp_clk_init(struct platform_device *pdev, void *priv)
-{
- bfin_write32(PADS0_EMAC_PTP_CLKSEL, 0);
- return 0;
-}
-
-static struct plat_stmmacenet_data eth_private_data = {
- .has_gmac = 1,
- .bus_id = 0,
- .enh_desc = 1,
- .phy_addr = 1,
- .mdio_bus_data = &phy_private_data,
- .dma_cfg = ð_dma_cfg,
- .force_thresh_dma_mode = 1,
- .interface = PHY_INTERFACE_MODE_RMII,
- .init = stmmac_ptp_clk_init,
-};
-
-static struct platform_device bfin_eth_device = {
- .name = "stmmaceth",
- .id = 0,
- .num_resources = 2,
- .resource = (struct resource[]) {
- {
- .start = EMAC0_MACCFG,
- .end = EMAC0_MACCFG + 0x1274,
- .flags = IORESOURCE_MEM,
- },
- {
- .name = "macirq",
- .start = IRQ_EMAC0_STAT,
- .end = IRQ_EMAC0_STAT,
- .flags = IORESOURCE_IRQ,
- },
- },
- .dev = {
- .power.can_wakeup = 1,
- .platform_data = ð_private_data,
- }
-};
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_ADXL34X)
-#include <linux/input/adxl34x.h>
-static const struct adxl34x_platform_data adxl34x_info = {
- .x_axis_offset = 0,
- .y_axis_offset = 0,
- .z_axis_offset = 0,
- .tap_threshold = 0x31,
- .tap_duration = 0x10,
- .tap_latency = 0x60,
- .tap_window = 0xF0,
- .tap_axis_control = ADXL_TAP_X_EN | ADXL_TAP_Y_EN | ADXL_TAP_Z_EN,
- .act_axis_control = 0xFF,
- .activity_threshold = 5,
- .inactivity_threshold = 3,
- .inactivity_time = 4,
- .free_fall_threshold = 0x7,
- .free_fall_time = 0x20,
- .data_rate = 0x8,
- .data_range = ADXL_FULL_RES,
-
- .ev_type = EV_ABS,
- .ev_code_x = ABS_X, /* EV_REL */
- .ev_code_y = ABS_Y, /* EV_REL */
- .ev_code_z = ABS_Z, /* EV_REL */
-
- .ev_code_tap = {BTN_TOUCH, BTN_TOUCH, BTN_TOUCH}, /* EV_KEY x,y,z */
-
-/* .ev_code_ff = KEY_F,*/ /* EV_KEY */
-/* .ev_code_act_inactivity = KEY_A,*/ /* EV_KEY */
- .power_mode = ADXL_AUTO_SLEEP | ADXL_LINK,
- .fifo_mode = ADXL_FIFO_STREAM,
- .orientation_enable = ADXL_EN_ORIENTATION_3D,
- .deadzone_angle = ADXL_DEADZONE_ANGLE_10p8,
- .divisor_length = ADXL_LP_FILTER_DIVISOR_16,
- /* EV_KEY {+Z, +Y, +X, -X, -Y, -Z} */
- .ev_codes_orient_3d = {BTN_Z, BTN_Y, BTN_X, BTN_A, BTN_B, BTN_C},
-};
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_REVID,
- .end = UART0_RXDIV+4,
- .flags = IORESOURCE_MEM,
- },
-#ifdef CONFIG_EARLY_PRINTK
- {
- .start = PORTD_FER,
- .end = PORTD_FER+2,
- .flags = IORESOURCE_REG,
- },
- {
- .start = PORTD_MUX,
- .end = PORTD_MUX+3,
- .flags = IORESOURCE_REG,
- },
-#endif
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_STAT,
- .end = IRQ_UART0_STAT,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-#ifdef CONFIG_BFIN_UART0_CTSRTS
- { /* CTS pin -- 0 means not supported */
- .start = GPIO_PD10,
- .end = GPIO_PD10,
- .flags = IORESOURCE_IO,
- },
- { /* RTS pin -- 0 means not supported */
- .start = GPIO_PD9,
- .end = GPIO_PD9,
- .flags = IORESOURCE_IO,
- },
-#endif
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX,
-#ifdef CONFIG_BFIN_UART0_CTSRTS
- P_UART0_RTS, P_UART0_CTS,
-#endif
- 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_REVID,
- .end = UART1_RXDIV+4,
- .flags = IORESOURCE_MEM,
- },
-#ifdef CONFIG_EARLY_PRINTK
- {
- .start = PORTG_FER_SET,
- .end = PORTG_FER_SET+2,
- .flags = IORESOURCE_REG,
- },
-#endif
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_STAT,
- .end = IRQ_UART1_STAT,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-#ifdef CONFIG_BFIN_UART1_CTSRTS
- { /* CTS pin -- 0 means not supported */
- .start = GPIO_PG13,
- .end = GPIO_PG13,
- .flags = IORESOURCE_IO,
- },
- { /* RTS pin -- 0 means not supported */
- .start = GPIO_PG10,
- .end = GPIO_PG10,
- .flags = IORESOURCE_IO,
- },
-#endif
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX,
-#ifdef CONFIG_BFIN_UART1_CTSRTS
- P_UART1_RTS, P_UART1_CTS,
-#endif
- 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
-static struct resource musb_resources[] = {
- [0] = {
- .start = 0xFFCC1000,
- .end = 0xFFCC1398,
- .flags = IORESOURCE_MEM,
- },
- [1] = { /* general IRQ */
- .start = IRQ_USB_STAT,
- .end = IRQ_USB_STAT,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- .name = "mc"
- },
- [2] = { /* DMA IRQ */
- .start = IRQ_USB_DMA,
- .end = IRQ_USB_DMA,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- .name = "dma"
- },
-};
-
-static struct musb_hdrc_config musb_config = {
- .multipoint = 1,
- .dyn_fifo = 0,
- .dma = 1,
- .num_eps = 16,
- .dma_channels = 8,
- .clkin = 48, /* musb CLKIN in MHZ */
-};
-
-static struct musb_hdrc_platform_data musb_plat = {
-#if defined(CONFIG_USB_MUSB_HDRC) && defined(CONFIG_USB_GADGET_MUSB_HDRC)
- .mode = MUSB_OTG,
-#elif defined(CONFIG_USB_MUSB_HDRC)
- .mode = MUSB_HOST,
-#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
- .mode = MUSB_PERIPHERAL,
-#endif
- .config = &musb_config,
-};
-
-static u64 musb_dmamask = ~(u32)0;
-
-static struct platform_device musb_device = {
- .name = "musb-blackfin",
- .id = 0,
- .dev = {
- .dma_mask = &musb_dmamask,
- .coherent_dma_mask = 0xffffffff,
- .platform_data = &musb_plat,
- },
- .num_resources = ARRAY_SIZE(musb_resources),
- .resource = musb_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
-static struct resource bfin_sport2_uart_resources[] = {
- {
- .start = SPORT2_TCR1,
- .end = SPORT2_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT2_RX,
- .end = IRQ_SPORT2_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT2_ERROR,
- .end = IRQ_SPORT2_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport2_peripherals[] = {
- P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS,
- P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0
-};
-
-static struct platform_device bfin_sport2_uart_device = {
- .name = "bfin-sport-uart",
- .id = 2,
- .num_resources = ARRAY_SIZE(bfin_sport2_uart_resources),
- .resource = bfin_sport2_uart_resources,
- .dev = {
- .platform_data = &bfin_sport2_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_CAN_BFIN)
-
-static unsigned short bfin_can0_peripherals[] = {
- P_CAN0_RX, P_CAN0_TX, 0
-};
-
-static struct resource bfin_can0_resources[] = {
- {
- .start = 0xFFC00A00,
- .end = 0xFFC00FFF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_CAN0_RX,
- .end = IRQ_CAN0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_CAN0_TX,
- .end = IRQ_CAN0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_CAN0_STAT,
- .end = IRQ_CAN0_STAT,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_can0_device = {
- .name = "bfin_can",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_can0_resources),
- .resource = bfin_can0_resources,
- .dev = {
- .platform_data = &bfin_can0_peripherals, /* Passed to driver */
- },
-};
-
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
-static struct mtd_partition partition_info[] = {
- {
- .name = "bootloader(nand)",
- .offset = 0,
- .size = 0x80000,
- }, {
- .name = "linux kernel(nand)",
- .offset = MTDPART_OFS_APPEND,
- .size = 4 * 1024 * 1024,
- },
- {
- .name = "file system(nand)",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- },
-};
-
-static struct bf5xx_nand_platform bfin_nand_platform = {
- .data_width = NFC_NWIDTH_8,
- .partitions = partition_info,
- .nr_partitions = ARRAY_SIZE(partition_info),
- .rd_dly = 3,
- .wr_dly = 3,
-};
-
-static struct resource bfin_nand_resources[] = {
- {
- .start = 0xFFC03B00,
- .end = 0xFFC03B4F,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = CH_NFC,
- .end = CH_NFC,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_nand_device = {
- .name = "bfin-nand",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_nand_resources),
- .resource = bfin_nand_resources,
- .dev = {
- .platform_data = &bfin_nand_platform,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SDH_BFIN)
-
-static struct bfin_sd_host bfin_sdh_data = {
- .dma_chan = CH_RSI,
- .irq_int0 = IRQ_RSI_INT0,
- .pin_req = {P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0},
-};
-
-static struct platform_device bfin_sdh_device = {
- .name = "bfin-sdh",
- .id = 0,
- .dev = {
- .platform_data = &bfin_sdh_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
-static struct mtd_partition ezkit_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x80000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0x400000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = 0x1000000 - 0x80000 - 0x400000,
- .offset = MTDPART_OFS_APPEND,
- },
-};
-
-int bf609_nor_flash_init(struct platform_device *pdev)
-{
-#define CONFIG_SMC_GCTL_VAL 0x00000010
-
- bfin_write32(SMC_GCTL, CONFIG_SMC_GCTL_VAL);
- bfin_write32(SMC_B0CTL, 0x01002011);
- bfin_write32(SMC_B0TIM, 0x08170977);
- bfin_write32(SMC_B0ETIM, 0x00092231);
- return 0;
-}
-
-void bf609_nor_flash_exit(struct platform_device *pdev)
-{
- bfin_write32(SMC_GCTL, 0);
-}
-
-static struct physmap_flash_data ezkit_flash_data = {
- .width = 2,
- .parts = ezkit_partitions,
- .init = bf609_nor_flash_init,
- .exit = bf609_nor_flash_exit,
- .nr_parts = ARRAY_SIZE(ezkit_partitions),
-#ifdef CONFIG_ROMKERNEL
- .probe_type = "map_rom",
-#endif
-};
-
-static struct resource ezkit_flash_resource = {
- .start = 0xb0000000,
- .end = 0xb0ffffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device ezkit_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &ezkit_flash_data,
- },
- .num_resources = 1,
- .resource = &ezkit_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-/* SPI flash chip (w25q32) */
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00080000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = 0x00180000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(spi)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "w25q32",
-};
-
-static struct adi_spi3_chip spi_flash_chip_info = {
- .enable_dma = true, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
-static struct adi_spi3_chip spidev_chip_info = {
- .enable_dma = true,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF6XX_PCM)
-static struct platform_device bfin_pcm = {
- .name = "bfin-i2s-pcm-audio",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF6XX_SOC_I2S)
-#include <asm/bfin_sport3.h>
-static struct resource bfin_snd_resources[] = {
- {
- .start = SPORT0_CTL_A,
- .end = SPORT0_CTL_A,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = SPORT0_CTL_B,
- .end = SPORT0_CTL_B,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = CH_SPORT0_TX,
- .end = CH_SPORT0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_SPORT0_RX,
- .end = CH_SPORT0_RX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = IRQ_SPORT0_TX_STAT,
- .end = IRQ_SPORT0_TX_STAT,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_RX_STAT,
- .end = IRQ_SPORT0_RX_STAT,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static const unsigned short bfin_snd_pin[] = {
- P_SPORT0_ACLK, P_SPORT0_AFS, P_SPORT0_AD0, P_SPORT0_BCLK,
- P_SPORT0_BFS, P_SPORT0_BD0, 0,
-};
-
-static struct bfin_snd_platform_data bfin_snd_data = {
- .pin_req = bfin_snd_pin,
-};
-
-static struct platform_device bfin_i2s = {
- .name = "bfin-i2s",
- .num_resources = ARRAY_SIZE(bfin_snd_resources),
- .resource = bfin_snd_resources,
- .dev = {
- .platform_data = &bfin_snd_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
-static const char * const ad1836_link[] = {
- "bfin-i2s.0",
- "spi0.76",
-};
-static struct platform_device bfin_ad1836_machine = {
- .name = "bfin-snd-ad1836",
- .id = -1,
- .dev = {
- .platform_data = (void *)ad1836_link,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61)
-static struct platform_device adau1761_device = {
- .name = "bfin-eval-adau1x61",
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_SOC_ADAU1761)
-#include <sound/adau17x1.h>
-static struct adau1761_platform_data adau1761_info = {
- .lineout_mode = ADAU1761_OUTPUT_MODE_LINE,
- .headphone_mode = ADAU1761_OUTPUT_MODE_HEADPHONE_CAPLESS,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_CAPTURE)
-#include <linux/videodev2.h>
-#include <media/blackfin/bfin_capture.h>
-#include <media/blackfin/ppi.h>
-
-static const unsigned short ppi_req[] = {
- P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
- P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
- P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
- P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15,
-#if !IS_ENABLED(CONFIG_VIDEO_VS6624)
- P_PPI0_D16, P_PPI0_D17, P_PPI0_D18, P_PPI0_D19,
- P_PPI0_D20, P_PPI0_D21, P_PPI0_D22, P_PPI0_D23,
-#endif
- P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
- 0,
-};
-
-static const struct ppi_info ppi_info = {
- .type = PPI_TYPE_EPPI3,
- .dma_ch = CH_EPPI0_CH0,
- .irq_err = IRQ_EPPI0_STAT,
- .base = (void __iomem *)EPPI0_STAT,
- .pin_req = ppi_req,
-};
-
-#if IS_ENABLED(CONFIG_VIDEO_VS6624)
-static struct v4l2_input vs6624_inputs[] = {
- {
- .index = 0,
- .name = "Camera",
- .type = V4L2_INPUT_TYPE_CAMERA,
- .std = V4L2_STD_UNKNOWN,
- },
-};
-
-static struct bcap_route vs6624_routes[] = {
- {
- .input = 0,
- .output = 0,
- },
-};
-
-static const unsigned vs6624_ce_pin = GPIO_PE4;
-
-static struct bfin_capture_config bfin_capture_data = {
- .card_name = "BF609",
- .inputs = vs6624_inputs,
- .num_inputs = ARRAY_SIZE(vs6624_inputs),
- .routes = vs6624_routes,
- .i2c_adapter_id = 0,
- .board_info = {
- .type = "vs6624",
- .addr = 0x10,
- .platform_data = (void *)&vs6624_ce_pin,
- },
- .ppi_info = &ppi_info,
- .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FS1HI_FS2HI
- | EPPI_CTL_POLC3 | EPPI_CTL_SYNC2 | EPPI_CTL_NON656),
- .blank_pixels = 4,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_VIDEO_ADV7842)
-#include <media/i2c/adv7842.h>
-
-static struct v4l2_input adv7842_inputs[] = {
- {
- .index = 0,
- .name = "Composite",
- .type = V4L2_INPUT_TYPE_CAMERA,
- .std = V4L2_STD_ALL,
- .capabilities = V4L2_IN_CAP_STD,
- },
- {
- .index = 1,
- .name = "S-Video",
- .type = V4L2_INPUT_TYPE_CAMERA,
- .std = V4L2_STD_ALL,
- .capabilities = V4L2_IN_CAP_STD,
- },
- {
- .index = 2,
- .name = "Component",
- .type = V4L2_INPUT_TYPE_CAMERA,
- .capabilities = V4L2_IN_CAP_DV_TIMINGS,
- },
- {
- .index = 3,
- .name = "VGA",
- .type = V4L2_INPUT_TYPE_CAMERA,
- .capabilities = V4L2_IN_CAP_DV_TIMINGS,
- },
- {
- .index = 4,
- .name = "HDMI",
- .type = V4L2_INPUT_TYPE_CAMERA,
- .capabilities = V4L2_IN_CAP_DV_TIMINGS,
- },
-};
-
-static struct bcap_route adv7842_routes[] = {
- {
- .input = 3,
- .output = 0,
- .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FLDSEL
- | EPPI_CTL_ACTIVE656),
- },
- {
- .input = 4,
- .output = 0,
- },
- {
- .input = 2,
- .output = 0,
- },
- {
- .input = 1,
- .output = 0,
- },
- {
- .input = 0,
- .output = 1,
- .ppi_control = (EPPI_CTL_SPLTWRD | PACK_EN | DLEN_16
- | EPPI_CTL_FS1LO_FS2LO | EPPI_CTL_POLC2
- | EPPI_CTL_SYNC2 | EPPI_CTL_NON656),
- },
-};
-
-static struct adv7842_output_format adv7842_opf[] = {
- {
- .op_ch_sel = ADV7842_OP_CH_SEL_BRG,
- .op_format_sel = ADV7842_OP_FORMAT_SEL_SDR_ITU656_8,
- .blank_data = 1,
- .insert_av_codes = 1,
- },
- {
- .op_ch_sel = ADV7842_OP_CH_SEL_RGB,
- .op_format_sel = ADV7842_OP_FORMAT_SEL_SDR_ITU656_16,
- .blank_data = 1,
- },
-};
-
-static struct adv7842_platform_data adv7842_data = {
- .opf = adv7842_opf,
- .num_opf = ARRAY_SIZE(adv7842_opf),
- .ain_sel = ADV7842_AIN10_11_12_NC_SYNC_4_1,
- .prim_mode = ADV7842_PRIM_MODE_SDP,
- .vid_std_select = ADV7842_SDP_VID_STD_CVBS_SD_4x1,
- .hdmi_free_run_enable = 1,
- .sdp_free_run_auto = 1,
- .llc_dll_phase = 0x10,
- .i2c_sdp_io = 0x40,
- .i2c_sdp = 0x41,
- .i2c_cp = 0x42,
- .i2c_vdp = 0x43,
- .i2c_afe = 0x44,
- .i2c_hdmi = 0x45,
- .i2c_repeater = 0x46,
- .i2c_edid = 0x47,
- .i2c_infoframe = 0x48,
- .i2c_cec = 0x49,
- .i2c_avlink = 0x4a,
-};
-
-static struct bfin_capture_config bfin_capture_data = {
- .card_name = "BF609",
- .inputs = adv7842_inputs,
- .num_inputs = ARRAY_SIZE(adv7842_inputs),
- .routes = adv7842_routes,
- .i2c_adapter_id = 0,
- .board_info = {
- .type = "adv7842",
- .addr = 0x20,
- .platform_data = (void *)&adv7842_data,
- },
- .ppi_info = &ppi_info,
- .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FLDSEL
- | EPPI_CTL_ACTIVE656),
-};
-#endif
-
-static struct platform_device bfin_capture_device = {
- .name = "bfin_capture",
- .dev = {
- .platform_data = &bfin_capture_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_DISPLAY)
-#include <linux/videodev2.h>
-#include <media/blackfin/bfin_display.h>
-#include <media/blackfin/ppi.h>
-
-static const unsigned short ppi_req_disp[] = {
- P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
- P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
- P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
- P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15,
- P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
- 0,
-};
-
-static const struct ppi_info ppi_info = {
- .type = PPI_TYPE_EPPI3,
- .dma_ch = CH_EPPI0_CH0,
- .irq_err = IRQ_EPPI0_STAT,
- .base = (void __iomem *)EPPI0_STAT,
- .pin_req = ppi_req_disp,
-};
-
-#if IS_ENABLED(CONFIG_VIDEO_ADV7511)
-#include <media/i2c/adv7511.h>
-
-static struct v4l2_output adv7511_outputs[] = {
- {
- .index = 0,
- .name = "HDMI",
- .type = V4L2_INPUT_TYPE_CAMERA,
- .capabilities = V4L2_OUT_CAP_DV_TIMINGS,
- },
-};
-
-static struct disp_route adv7511_routes[] = {
- {
- .output = 0,
- },
-};
-
-static struct adv7511_platform_data adv7511_data = {
- .edid_addr = 0x7e,
-};
-
-static struct bfin_display_config bfin_display_data = {
- .card_name = "BF609",
- .outputs = adv7511_outputs,
- .num_outputs = ARRAY_SIZE(adv7511_outputs),
- .routes = adv7511_routes,
- .i2c_adapter_id = 0,
- .board_info = {
- .type = "adv7511",
- .addr = 0x39,
- .platform_data = (void *)&adv7511_data,
- },
- .ppi_info = &ppi_info,
- .ppi_control = (EPPI_CTL_SPLTWRD | PACK_EN | DLEN_16
- | EPPI_CTL_FS1LO_FS2LO | EPPI_CTL_POLC3
- | EPPI_CTL_IFSGEN | EPPI_CTL_SYNC2
- | EPPI_CTL_NON656 | EPPI_CTL_DIR),
-};
-#endif
-
-#if IS_ENABLED(CONFIG_VIDEO_ADV7343)
-#include <media/i2c/adv7343.h>
-
-static struct v4l2_output adv7343_outputs[] = {
- {
- .index = 0,
- .name = "Composite",
- .type = V4L2_OUTPUT_TYPE_ANALOG,
- .std = V4L2_STD_ALL,
- .capabilities = V4L2_OUT_CAP_STD,
- },
- {
- .index = 1,
- .name = "S-Video",
- .type = V4L2_OUTPUT_TYPE_ANALOG,
- .std = V4L2_STD_ALL,
- .capabilities = V4L2_OUT_CAP_STD,
- },
- {
- .index = 2,
- .name = "Component",
- .type = V4L2_OUTPUT_TYPE_ANALOG,
- .std = V4L2_STD_ALL,
- .capabilities = V4L2_OUT_CAP_STD,
- },
-
-};
-
-static struct disp_route adv7343_routes[] = {
- {
- .output = ADV7343_COMPOSITE_ID,
- },
- {
- .output = ADV7343_SVIDEO_ID,
- },
- {
- .output = ADV7343_COMPONENT_ID,
- },
-};
-
-static struct adv7343_platform_data adv7343_data = {
- .mode_config = {
- .sleep_mode = false,
- .pll_control = false,
- .dac_1 = true,
- .dac_2 = true,
- .dac_3 = true,
- .dac_4 = true,
- .dac_5 = true,
- .dac_6 = true,
- },
- .sd_config = {
- .sd_dac_out1 = false,
- .sd_dac_out2 = false,
- },
-};
-
-static struct bfin_display_config bfin_display_data = {
- .card_name = "BF609",
- .outputs = adv7343_outputs,
- .num_outputs = ARRAY_SIZE(adv7343_outputs),
- .routes = adv7343_routes,
- .i2c_adapter_id = 0,
- .board_info = {
- .type = "adv7343",
- .addr = 0x2b,
- .platform_data = (void *)&adv7343_data,
- },
- .ppi_info = &ppi_info_disp,
- .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FS1LO_FS2LO
- | EPPI_CTL_POLC3 | EPPI_CTL_BLANKGEN | EPPI_CTL_SYNC2
- | EPPI_CTL_NON656 | EPPI_CTL_DIR),
-};
-#endif
-
-static struct platform_device bfin_display_device = {
- .name = "bfin_display",
- .dev = {
- .platform_data = &bfin_display_data,
- },
-};
-#endif
-
-#if defined(CONFIG_FB_BF609_NL8048) \
- || defined(CONFIG_FB_BF609_NL8048_MODULE)
-static struct resource nl8048_resources[] = {
- {
- .start = EPPI2_STAT,
- .end = EPPI2_STAT,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = CH_EPPI2_CH0,
- .end = CH_EPPI2_CH0,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = IRQ_EPPI2_STAT,
- .end = IRQ_EPPI2_STAT,
- .flags = IORESOURCE_IRQ,
- },
-};
-static struct platform_device bfin_fb_device = {
- .name = "bf609_nl8048",
- .num_resources = ARRAY_SIZE(nl8048_resources),
- .resource = nl8048_resources,
- .dev = {
- .platform_data = (void *)GPIO_PC15,
- },
-};
-#endif
-
-#if defined(CONFIG_BFIN_CRC)
-#define BFIN_CRC_NAME "bfin-crc"
-
-static struct resource bfin_crc0_resources[] = {
- {
- .start = REG_CRC0_CTL,
- .end = REG_CRC0_REVID+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_CRC0_DCNTEXP,
- .end = IRQ_CRC0_DCNTEXP,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_MEM_STREAM0_SRC_CRC0,
- .end = CH_MEM_STREAM0_SRC_CRC0,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_MEM_STREAM0_DEST_CRC0,
- .end = CH_MEM_STREAM0_DEST_CRC0,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_crc0_device = {
- .name = BFIN_CRC_NAME,
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_crc0_resources),
- .resource = bfin_crc0_resources,
-};
-
-static struct resource bfin_crc1_resources[] = {
- {
- .start = REG_CRC1_CTL,
- .end = REG_CRC1_REVID+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_CRC1_DCNTEXP,
- .end = IRQ_CRC1_DCNTEXP,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_MEM_STREAM1_SRC_CRC1,
- .end = CH_MEM_STREAM1_SRC_CRC1,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_MEM_STREAM1_DEST_CRC1,
- .end = CH_MEM_STREAM1_DEST_CRC1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_crc1_device = {
- .name = BFIN_CRC_NAME,
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_crc1_resources),
- .resource = bfin_crc1_resources,
-};
-#endif
-
-#if defined(CONFIG_CRYPTO_DEV_BFIN_CRC)
-#define BFIN_CRYPTO_CRC_NAME "bfin-hmac-crc"
-#define BFIN_CRYPTO_CRC_POLY_DATA 0x5c5c5c5c
-
-static struct resource bfin_crypto_crc_resources[] = {
- {
- .start = REG_CRC0_CTL,
- .end = REG_CRC0_REVID+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_CRC0_DCNTEXP,
- .end = IRQ_CRC0_DCNTEXP,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_MEM_STREAM0_SRC_CRC0,
- .end = CH_MEM_STREAM0_SRC_CRC0,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_crypto_crc_device = {
- .name = BFIN_CRYPTO_CRC_NAME,
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_crypto_crc_resources),
- .resource = bfin_crypto_crc_resources,
- .dev = {
- .platform_data = (void *)BFIN_CRYPTO_CRC_POLY_DATA,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
-static const struct ad7877_platform_data bfin_ad7877_ts_info = {
- .model = 7877,
- .vref_delay_usecs = 50, /* internal, no capacitor */
- .x_plate_ohms = 419,
- .y_plate_ohms = 486,
- .pressure_max = 1000,
- .pressure_min = 0,
- .stopacq_polarity = 1,
- .first_conversion_delay = 3,
- .acquisition_time = 1,
- .averaging = 1,
- .pen_down_acc_interval = 1,
-};
-#endif
-
-#ifdef CONFIG_PINCTRL_ADI2
-
-# define ADI_PINT_DEVNAME "adi-gpio-pint"
-# define ADI_GPIO_DEVNAME "adi-gpio"
-# define ADI_PINCTRL_DEVNAME "pinctrl-adi2"
-
-static struct platform_device bfin_pinctrl_device = {
- .name = ADI_PINCTRL_DEVNAME,
- .id = 0,
-};
-
-static struct resource bfin_pint0_resources[] = {
- {
- .start = PINT0_MASK_SET,
- .end = PINT0_LATCH + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PINT0,
- .end = IRQ_PINT0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_pint0_device = {
- .name = ADI_PINT_DEVNAME,
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_pint0_resources),
- .resource = bfin_pint0_resources,
-};
-
-static struct resource bfin_pint1_resources[] = {
- {
- .start = PINT1_MASK_SET,
- .end = PINT1_LATCH + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PINT1,
- .end = IRQ_PINT1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_pint1_device = {
- .name = ADI_PINT_DEVNAME,
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_pint1_resources),
- .resource = bfin_pint1_resources,
-};
-
-static struct resource bfin_pint2_resources[] = {
- {
- .start = PINT2_MASK_SET,
- .end = PINT2_LATCH + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PINT2,
- .end = IRQ_PINT2,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_pint2_device = {
- .name = ADI_PINT_DEVNAME,
- .id = 2,
- .num_resources = ARRAY_SIZE(bfin_pint2_resources),
- .resource = bfin_pint2_resources,
-};
-
-static struct resource bfin_pint3_resources[] = {
- {
- .start = PINT3_MASK_SET,
- .end = PINT3_LATCH + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PINT3,
- .end = IRQ_PINT3,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_pint3_device = {
- .name = ADI_PINT_DEVNAME,
- .id = 3,
- .num_resources = ARRAY_SIZE(bfin_pint3_resources),
- .resource = bfin_pint3_resources,
-};
-
-static struct resource bfin_pint4_resources[] = {
- {
- .start = PINT4_MASK_SET,
- .end = PINT4_LATCH + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PINT4,
- .end = IRQ_PINT4,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_pint4_device = {
- .name = ADI_PINT_DEVNAME,
- .id = 4,
- .num_resources = ARRAY_SIZE(bfin_pint4_resources),
- .resource = bfin_pint4_resources,
-};
-
-static struct resource bfin_pint5_resources[] = {
- {
- .start = PINT5_MASK_SET,
- .end = PINT5_LATCH + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PINT5,
- .end = IRQ_PINT5,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_pint5_device = {
- .name = ADI_PINT_DEVNAME,
- .id = 5,
- .num_resources = ARRAY_SIZE(bfin_pint5_resources),
- .resource = bfin_pint5_resources,
-};
-
-static struct resource bfin_gpa_resources[] = {
- {
- .start = PORTA_FER,
- .end = PORTA_MUX + 3,
- .flags = IORESOURCE_MEM,
- },
- { /* optional */
- .start = IRQ_PA0,
- .end = IRQ_PA0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpa_pdata = {
- .port_pin_base = GPIO_PA0,
- .port_width = GPIO_BANKSIZE,
- .pint_id = 0, /* PINT0 */
- .pint_assign = true, /* PINT upper 16 bit */
- .pint_map = 0, /* mapping mask in PINT */
-};
-
-static struct platform_device bfin_gpa_device = {
- .name = ADI_GPIO_DEVNAME,
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_gpa_resources),
- .resource = bfin_gpa_resources,
- .dev = {
- .platform_data = &bfin_gpa_pdata, /* Passed to driver */
- },
-};
-
-static struct resource bfin_gpb_resources[] = {
- {
- .start = PORTB_FER,
- .end = PORTB_MUX + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PB0,
- .end = IRQ_PB0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpb_pdata = {
- .port_pin_base = GPIO_PB0,
- .port_width = GPIO_BANKSIZE,
- .pint_id = 0,
- .pint_assign = false,
- .pint_map = 1,
-};
-
-static struct platform_device bfin_gpb_device = {
- .name = ADI_GPIO_DEVNAME,
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_gpb_resources),
- .resource = bfin_gpb_resources,
- .dev = {
- .platform_data = &bfin_gpb_pdata, /* Passed to driver */
- },
-};
-
-static struct resource bfin_gpc_resources[] = {
- {
- .start = PORTC_FER,
- .end = PORTC_MUX + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PC0,
- .end = IRQ_PC0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpc_pdata = {
- .port_pin_base = GPIO_PC0,
- .port_width = GPIO_BANKSIZE,
- .pint_id = 1,
- .pint_assign = false,
- .pint_map = 1,
-};
-
-static struct platform_device bfin_gpc_device = {
- .name = ADI_GPIO_DEVNAME,
- .id = 2,
- .num_resources = ARRAY_SIZE(bfin_gpc_resources),
- .resource = bfin_gpc_resources,
- .dev = {
- .platform_data = &bfin_gpc_pdata, /* Passed to driver */
- },
-};
-
-static struct resource bfin_gpd_resources[] = {
- {
- .start = PORTD_FER,
- .end = PORTD_MUX + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PD0,
- .end = IRQ_PD0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpd_pdata = {
- .port_pin_base = GPIO_PD0,
- .port_width = GPIO_BANKSIZE,
- .pint_id = 2,
- .pint_assign = false,
- .pint_map = 1,
-};
-
-static struct platform_device bfin_gpd_device = {
- .name = ADI_GPIO_DEVNAME,
- .id = 3,
- .num_resources = ARRAY_SIZE(bfin_gpd_resources),
- .resource = bfin_gpd_resources,
- .dev = {
- .platform_data = &bfin_gpd_pdata, /* Passed to driver */
- },
-};
-
-static struct resource bfin_gpe_resources[] = {
- {
- .start = PORTE_FER,
- .end = PORTE_MUX + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PE0,
- .end = IRQ_PE0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpe_pdata = {
- .port_pin_base = GPIO_PE0,
- .port_width = GPIO_BANKSIZE,
- .pint_id = 3,
- .pint_assign = false,
- .pint_map = 1,
-};
-
-static struct platform_device bfin_gpe_device = {
- .name = ADI_GPIO_DEVNAME,
- .id = 4,
- .num_resources = ARRAY_SIZE(bfin_gpe_resources),
- .resource = bfin_gpe_resources,
- .dev = {
- .platform_data = &bfin_gpe_pdata, /* Passed to driver */
- },
-};
-
-static struct resource bfin_gpf_resources[] = {
- {
- .start = PORTF_FER,
- .end = PORTF_MUX + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PF0,
- .end = IRQ_PF0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpf_pdata = {
- .port_pin_base = GPIO_PF0,
- .port_width = GPIO_BANKSIZE,
- .pint_id = 4,
- .pint_assign = false,
- .pint_map = 1,
-};
-
-static struct platform_device bfin_gpf_device = {
- .name = ADI_GPIO_DEVNAME,
- .id = 5,
- .num_resources = ARRAY_SIZE(bfin_gpf_resources),
- .resource = bfin_gpf_resources,
- .dev = {
- .platform_data = &bfin_gpf_pdata, /* Passed to driver */
- },
-};
-
-static struct resource bfin_gpg_resources[] = {
- {
- .start = PORTG_FER,
- .end = PORTG_MUX + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PG0,
- .end = IRQ_PG0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpg_pdata = {
- .port_pin_base = GPIO_PG0,
- .port_width = GPIO_BANKSIZE,
- .pint_id = 5,
- .pint_assign = false,
- .pint_map = 1,
-};
-
-static struct platform_device bfin_gpg_device = {
- .name = ADI_GPIO_DEVNAME,
- .id = 6,
- .num_resources = ARRAY_SIZE(bfin_gpg_resources),
- .resource = bfin_gpg_resources,
- .dev = {
- .platform_data = &bfin_gpg_pdata, /* Passed to driver */
- },
-};
-
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
-#include <linux/input.h>
-#include <linux/gpio_keys.h>
-
-static struct gpio_keys_button bfin_gpio_keys_table[] = {
- {BTN_0, GPIO_PB10, 1, "gpio-keys: BTN0"},
- {BTN_1, GPIO_PE1, 1, "gpio-keys: BTN1"},
-};
-
-static struct gpio_keys_platform_data bfin_gpio_keys_data = {
- .buttons = bfin_gpio_keys_table,
- .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
-};
-
-static struct platform_device bfin_device_gpiokeys = {
- .name = "gpio-keys",
- .dev = {
- .platform_data = &bfin_gpio_keys_data,
- },
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = MAX_CTRL_CS + GPIO_PD11, /* SPI_SSEL1*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
- {
- .modalias = "ad7877",
- .platform_data = &bfin_ad7877_ts_info,
- .irq = IRQ_PD9,
- .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = MAX_CTRL_CS + GPIO_PC15, /* SPI_SSEL4 */
- },
-#endif
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = MAX_CTRL_CS + GPIO_PD11, /* SPI_SSEL1*/
- .controller_data = &spidev_chip_info,
- },
-#endif
-#if IS_ENABLED(CONFIG_INPUT_ADXL34X_SPI)
- {
- .modalias = "adxl34x",
- .platform_data = &adxl34x_info,
- .irq = IRQ_PC5,
- .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 1,
- .chip_select = 2,
- .mode = SPI_MODE_3,
- },
-#endif
-};
-#if IS_ENABLED(CONFIG_SPI_ADI_V3)
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = CH_SPI0_TX,
- .end = CH_SPI0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_SPI0_RX,
- .end = CH_SPI0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-/* SPI (1) */
-static struct resource bfin_spi1_resource[] = {
- {
- .start = SPI1_REGBASE,
- .end = SPI1_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = CH_SPI1_TX,
- .end = CH_SPI1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_SPI1_RX,
- .end = CH_SPI1_RX,
- .flags = IORESOURCE_DMA,
- },
-
-};
-
-/* SPI controller data */
-static struct adi_spi3_master bf60x_spi_master_info0 = {
- .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct platform_device bf60x_spi_master0 = {
- .name = "adi-spi3",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bf60x_spi_master_info0, /* Passed to driver */
- },
-};
-
-static struct adi_spi3_master bf60x_spi_master_info1 = {
- .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
- .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
-};
-
-static struct platform_device bf60x_spi_master1 = {
- .name = "adi-spi3",
- .id = 1, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi1_resource),
- .resource = bfin_spi1_resource,
- .dev = {
- .platform_data = &bf60x_spi_master_info1, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_CLKDIV,
- .end = TWI0_CLKDIV + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI0,
- .end = IRQ_TWI0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi0_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-
-static const u16 bfin_twi1_pins[] = {P_TWI1_SCL, P_TWI1_SDA, 0};
-
-static struct resource bfin_twi1_resource[] = {
- [0] = {
- .start = TWI1_CLKDIV,
- .end = TWI1_CLKDIV + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI1,
- .end = IRQ_TWI1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi1_device = {
- .name = "i2c-bfin-twi",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_twi1_resource),
- .resource = bfin_twi1_resource,
- .dev = {
- .platform_data = &bfin_twi1_pins,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_PINCTRL_MCP23S08)
-#include <linux/spi/mcp23s08.h>
-static const struct mcp23s08_platform_data bfin_mcp23s08_soft_switch0 = {
- .base = 120,
-};
-static const struct mcp23s08_platform_data bfin_mcp23s08_soft_switch1 = {
- .base = 130,
-};
-static const struct mcp23s08_platform_data bfin_mcp23s08_soft_switch2 = {
- .base = 140,
-};
-# if IS_ENABLED(CONFIG_VIDEO_ADV7842)
-static const struct mcp23s08_platform_data bfin_adv7842_soft_switch = {
- .base = 150,
-};
-# endif
-# if IS_ENABLED(CONFIG_VIDEO_ADV7511) || IS_ENABLED(CONFIG_VIDEO_ADV7343)
-static const struct mcp23s08_platform_data bfin_adv7511_soft_switch = {
- .base = 160,
-};
-# endif
-#endif
-
-static struct i2c_board_info __initdata bfin_i2c_board_info0[] = {
-#if IS_ENABLED(CONFIG_INPUT_ADXL34X_I2C)
- {
- I2C_BOARD_INFO("adxl34x", 0x53),
- .irq = IRQ_PC5,
- .platform_data = (void *)&adxl34x_info,
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_ADAU1761)
- {
- I2C_BOARD_INFO("adau1761", 0x38),
- .platform_data = (void *)&adau1761_info
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_SSM2602)
- {
- I2C_BOARD_INFO("ssm2602", 0x1b),
- },
-#endif
-#if IS_ENABLED(CONFIG_PINCTRL_MCP23S08)
- {
- I2C_BOARD_INFO("mcp23017", 0x21),
- .platform_data = (void *)&bfin_mcp23s08_soft_switch0
- },
- {
- I2C_BOARD_INFO("mcp23017", 0x22),
- .platform_data = (void *)&bfin_mcp23s08_soft_switch1
- },
- {
- I2C_BOARD_INFO("mcp23017", 0x23),
- .platform_data = (void *)&bfin_mcp23s08_soft_switch2
- },
-# if IS_ENABLED(CONFIG_VIDEO_ADV7842)
- {
- I2C_BOARD_INFO("mcp23017", 0x26),
- .platform_data = (void *)&bfin_adv7842_soft_switch
- },
-# endif
-# if IS_ENABLED(CONFIG_VIDEO_ADV7511) || IS_ENABLED(CONFIG_VIDEO_ADV7343)
- {
- I2C_BOARD_INFO("mcp23017", 0x25),
- .platform_data = (void *)&bfin_adv7511_soft_switch
- },
-# endif
-#endif
-};
-
-static struct i2c_board_info __initdata bfin_i2c_board_info1[] = {
-};
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
-/*
- * Internal VLEV BF54XSBBC1533
- ****temporarily using these values until data sheet is updated
- */
- VRPAIR(VLEV_085, 150000000),
- VRPAIR(VLEV_090, 250000000),
- VRPAIR(VLEV_110, 276000000),
- VRPAIR(VLEV_115, 301000000),
- VRPAIR(VLEV_120, 525000000),
- VRPAIR(VLEV_125, 550000000),
- VRPAIR(VLEV_130, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-static struct platform_device *ezkit_devices[] __initdata = {
-
- &bfin_dpmc,
-#if defined(CONFIG_PINCTRL_ADI2)
- &bfin_pinctrl_device,
- &bfin_pint0_device,
- &bfin_pint1_device,
- &bfin_pint2_device,
- &bfin_pint3_device,
- &bfin_pint4_device,
- &bfin_pint5_device,
- &bfin_gpa_device,
- &bfin_gpb_device,
- &bfin_gpc_device,
- &bfin_gpd_device,
- &bfin_gpe_device,
- &bfin_gpf_device,
- &bfin_gpg_device,
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_STMMAC_ETH)
- &bfin_eth_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
- &musb_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
- &bfin_isp1760_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
- &bfin_sport2_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_CAN_BFIN)
- &bfin_can0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
- &bfin_nand_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SDH_BFIN)
- &bfin_sdh_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_ADI_V3)
- &bf60x_spi_master0,
- &bf60x_spi_master1,
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_BFIN_ROTARY)
- &bfin_rotary_device,
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi0_device,
-#if !defined(CONFIG_BF542)
- &i2c_bfin_twi1_device,
-#endif
-#endif
-
-#if defined(CONFIG_BFIN_CRC)
- &bfin_crc0_device,
- &bfin_crc1_device,
-#endif
-#if defined(CONFIG_CRYPTO_DEV_BFIN_CRC)
- &bfin_crypto_crc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
- &bfin_device_gpiokeys,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
- &ezkit_flash_device,
-#endif
-#if IS_ENABLED(CONFIG_SND_BF6XX_PCM)
- &bfin_pcm,
-#endif
-#if IS_ENABLED(CONFIG_SND_BF6XX_SOC_I2S)
- &bfin_i2s,
-#endif
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
- &bfin_ad1836_machine,
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61)
- &adau1761_device,
-#endif
-#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_CAPTURE)
- &bfin_capture_device,
-#endif
-#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_DISPLAY)
- &bfin_display_device,
-#endif
-
-};
-
-/* Pin control settings */
-static struct pinctrl_map __initdata bfin_pinmux_map[] = {
- /* per-device maps */
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.0", "pinctrl-adi2.0", NULL, "uart0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.1", "pinctrl-adi2.0", NULL, "uart1"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.0", "pinctrl-adi2.0", NULL, "uart0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.1", "pinctrl-adi2.0", NULL, "uart1"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-sdh.0", "pinctrl-adi2.0", NULL, "rsi0"),
- PIN_MAP_MUX_GROUP_DEFAULT("stmmaceth.0", "pinctrl-adi2.0", NULL, "eth0"),
- PIN_MAP_MUX_GROUP_DEFAULT("adi-spi3.0", "pinctrl-adi2.0", NULL, "spi0"),
- PIN_MAP_MUX_GROUP_DEFAULT("adi-spi3.1", "pinctrl-adi2.0", NULL, "spi1"),
- PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.0", "pinctrl-adi2.0", NULL, "twi0"),
- PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.1", "pinctrl-adi2.0", NULL, "twi1"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-rotary", "pinctrl-adi2.0", NULL, "rotary"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin_can.0", "pinctrl-adi2.0", NULL, "can0"),
- PIN_MAP_MUX_GROUP_DEFAULT("physmap-flash.0", "pinctrl-adi2.0", NULL, "smc0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bf609_nl8048.0", "pinctrl-adi2.0", "ppi2_16bgrp", "ppi2"),
- PIN_MAP_MUX_GROUP("bfin_display.0", "8bit", "pinctrl-adi2.0", "ppi2_8bgrp", "ppi2"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin_display.0", "pinctrl-adi2.0", "ppi2_16bgrp", "ppi2"),
- PIN_MAP_MUX_GROUP("bfin_display.0", "16bit", "pinctrl-adi2.0", "ppi2_16bgrp", "ppi2"),
- PIN_MAP_MUX_GROUP("bfin_capture.0", "8bit", "pinctrl-adi2.0", "ppi0_8bgrp", "ppi0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin_capture.0", "pinctrl-adi2.0", "ppi0_16bgrp", "ppi0"),
- PIN_MAP_MUX_GROUP("bfin_capture.0", "16bit", "pinctrl-adi2.0", "ppi0_16bgrp", "ppi0"),
- PIN_MAP_MUX_GROUP("bfin_capture.0", "24bit", "pinctrl-adi2.0", "ppi0_24bgrp", "ppi0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.0", "pinctrl-adi2.0", NULL, "sport0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.0", "pinctrl-adi2.0", NULL, "sport0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.1", "pinctrl-adi2.0", NULL, "sport1"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.1", "pinctrl-adi2.0", NULL, "sport1"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.2", "pinctrl-adi2.0", NULL, "sport2"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.2", "pinctrl-adi2.0", NULL, "sport2"),
-};
-
-static int __init ezkit_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
-
- /* Initialize pinmuxing */
- pinctrl_register_mappings(bfin_pinmux_map,
- ARRAY_SIZE(bfin_pinmux_map));
-
- i2c_register_board_info(0, bfin_i2c_board_info0,
- ARRAY_SIZE(bfin_i2c_board_info0));
- i2c_register_board_info(1, bfin_i2c_board_info1,
- ARRAY_SIZE(bfin_i2c_board_info1));
-
- platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices));
-
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
-
- return 0;
-}
-
-arch_initcall(ezkit_init);
-
-static struct platform_device *ezkit_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(ezkit_early_devices,
- ARRAY_SIZE(ezkit_early_devices));
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/string.h>
-#include <linux/clk.h>
-#include <linux/mutex.h>
-#include <linux/spinlock.h>
-#include <linux/debugfs.h>
-#include <linux/device.h>
-#include <linux/init.h>
-#include <linux/timer.h>
-#include <linux/io.h>
-#include <linux/seq_file.h>
-#include <linux/clkdev.h>
-
-#include <asm/clocks.h>
-
-#define CGU0_CTL_DF (1 << 0)
-
-#define CGU0_CTL_MSEL_SHIFT 8
-#define CGU0_CTL_MSEL_MASK (0x7f << 8)
-
-#define CGU0_STAT_PLLEN (1 << 0)
-#define CGU0_STAT_PLLBP (1 << 1)
-#define CGU0_STAT_PLLLK (1 << 2)
-#define CGU0_STAT_CLKSALGN (1 << 3)
-#define CGU0_STAT_CCBF0 (1 << 4)
-#define CGU0_STAT_CCBF1 (1 << 5)
-#define CGU0_STAT_SCBF0 (1 << 6)
-#define CGU0_STAT_SCBF1 (1 << 7)
-#define CGU0_STAT_DCBF (1 << 8)
-#define CGU0_STAT_OCBF (1 << 9)
-#define CGU0_STAT_ADDRERR (1 << 16)
-#define CGU0_STAT_LWERR (1 << 17)
-#define CGU0_STAT_DIVERR (1 << 18)
-#define CGU0_STAT_WDFMSERR (1 << 19)
-#define CGU0_STAT_WDIVERR (1 << 20)
-#define CGU0_STAT_PLOCKERR (1 << 21)
-
-#define CGU0_DIV_CSEL_SHIFT 0
-#define CGU0_DIV_CSEL_MASK 0x0000001F
-#define CGU0_DIV_S0SEL_SHIFT 5
-#define CGU0_DIV_S0SEL_MASK (0x3 << CGU0_DIV_S0SEL_SHIFT)
-#define CGU0_DIV_SYSSEL_SHIFT 8
-#define CGU0_DIV_SYSSEL_MASK (0x1f << CGU0_DIV_SYSSEL_SHIFT)
-#define CGU0_DIV_S1SEL_SHIFT 13
-#define CGU0_DIV_S1SEL_MASK (0x3 << CGU0_DIV_S1SEL_SHIFT)
-#define CGU0_DIV_DSEL_SHIFT 16
-#define CGU0_DIV_DSEL_MASK (0x1f << CGU0_DIV_DSEL_SHIFT)
-#define CGU0_DIV_OSEL_SHIFT 22
-#define CGU0_DIV_OSEL_MASK (0x7f << CGU0_DIV_OSEL_SHIFT)
-
-#define CLK(_clk, _devname, _conname) \
- { \
- .clk = &_clk, \
- .dev_id = _devname, \
- .con_id = _conname, \
- }
-
-#define NEEDS_INITIALIZATION 0x11
-
-static LIST_HEAD(clk_list);
-
-static void clk_reg_write_mask(u32 reg, uint32_t val, uint32_t mask)
-{
- u32 val2;
-
- val2 = bfin_read32(reg);
- val2 &= ~mask;
- val2 |= val;
- bfin_write32(reg, val2);
-}
-
-int wait_for_pll_align(void)
-{
- int i = 10000;
- while (i-- && (bfin_read32(CGU0_STAT) & CGU0_STAT_CLKSALGN));
-
- if (bfin_read32(CGU0_STAT) & CGU0_STAT_CLKSALGN) {
- printk(KERN_CRIT "fail to align clk\n");
- return -1;
- }
-
- return 0;
-}
-
-int clk_enable(struct clk *clk)
-{
- int ret = -EIO;
- if (clk->ops && clk->ops->enable)
- ret = clk->ops->enable(clk);
- return ret;
-}
-EXPORT_SYMBOL(clk_enable);
-
-void clk_disable(struct clk *clk)
-{
- if (!clk)
- return;
-
- if (clk->ops && clk->ops->disable)
- clk->ops->disable(clk);
-}
-EXPORT_SYMBOL(clk_disable);
-
-
-unsigned long clk_get_rate(struct clk *clk)
-{
- unsigned long ret = 0;
- if (clk->ops && clk->ops->get_rate)
- ret = clk->ops->get_rate(clk);
- return ret;
-}
-EXPORT_SYMBOL(clk_get_rate);
-
-long clk_round_rate(struct clk *clk, unsigned long rate)
-{
- long ret = 0;
- if (clk->ops && clk->ops->round_rate)
- ret = clk->ops->round_rate(clk, rate);
- return ret;
-}
-EXPORT_SYMBOL(clk_round_rate);
-
-int clk_set_rate(struct clk *clk, unsigned long rate)
-{
- int ret = -EIO;
- if (clk->ops && clk->ops->set_rate)
- ret = clk->ops->set_rate(clk, rate);
- return ret;
-}
-EXPORT_SYMBOL(clk_set_rate);
-
-unsigned long vco_get_rate(struct clk *clk)
-{
- return clk->rate;
-}
-
-unsigned long pll_get_rate(struct clk *clk)
-{
- u32 df;
- u32 msel;
- u32 ctl = bfin_read32(CGU0_CTL);
- u32 stat = bfin_read32(CGU0_STAT);
- if (stat & CGU0_STAT_PLLBP)
- return 0;
- msel = (ctl & CGU0_CTL_MSEL_MASK) >> CGU0_CTL_MSEL_SHIFT;
- df = (ctl & CGU0_CTL_DF);
- clk->parent->rate = clk_get_rate(clk->parent);
- return clk->parent->rate / (df + 1) * msel * 2;
-}
-
-unsigned long pll_round_rate(struct clk *clk, unsigned long rate)
-{
- u32 div;
- div = rate / clk->parent->rate;
- return clk->parent->rate * div;
-}
-
-int pll_set_rate(struct clk *clk, unsigned long rate)
-{
- u32 msel;
- u32 stat = bfin_read32(CGU0_STAT);
- if (!(stat & CGU0_STAT_PLLEN))
- return -EBUSY;
- if (!(stat & CGU0_STAT_PLLLK))
- return -EBUSY;
- if (wait_for_pll_align())
- return -EBUSY;
- msel = rate / clk->parent->rate / 2;
- clk_reg_write_mask(CGU0_CTL, msel << CGU0_CTL_MSEL_SHIFT,
- CGU0_CTL_MSEL_MASK);
- clk->rate = rate;
- return 0;
-}
-
-unsigned long cclk_get_rate(struct clk *clk)
-{
- if (clk->parent)
- return clk->parent->rate;
- else
- return 0;
-}
-
-unsigned long sys_clk_get_rate(struct clk *clk)
-{
- unsigned long drate;
- u32 msel;
- u32 df;
- u32 ctl = bfin_read32(CGU0_CTL);
- u32 div = bfin_read32(CGU0_DIV);
- div = (div & clk->mask) >> clk->shift;
- msel = (ctl & CGU0_CTL_MSEL_MASK) >> CGU0_CTL_MSEL_SHIFT;
- df = (ctl & CGU0_CTL_DF);
-
- if (!strcmp(clk->parent->name, "SYS_CLKIN")) {
- drate = clk->parent->rate / (df + 1);
- drate *= msel;
- drate /= div;
- return drate;
- } else {
- clk->parent->rate = clk_get_rate(clk->parent);
- return clk->parent->rate / div;
- }
-}
-
-unsigned long dummy_get_rate(struct clk *clk)
-{
- clk->parent->rate = clk_get_rate(clk->parent);
- return clk->parent->rate;
-}
-
-unsigned long sys_clk_round_rate(struct clk *clk, unsigned long rate)
-{
- unsigned long max_rate;
- unsigned long drate;
- int i;
- u32 msel;
- u32 df;
- u32 ctl = bfin_read32(CGU0_CTL);
-
- msel = (ctl & CGU0_CTL_MSEL_MASK) >> CGU0_CTL_MSEL_SHIFT;
- df = (ctl & CGU0_CTL_DF);
- max_rate = clk->parent->rate / (df + 1) * msel;
-
- if (rate > max_rate)
- return 0;
-
- for (i = 1; i < clk->mask; i++) {
- drate = max_rate / i;
- if (rate >= drate)
- return drate;
- }
- return 0;
-}
-
-int sys_clk_set_rate(struct clk *clk, unsigned long rate)
-{
- u32 div = bfin_read32(CGU0_DIV);
- div = (div & clk->mask) >> clk->shift;
-
- rate = clk_round_rate(clk, rate);
-
- if (!rate)
- return -EINVAL;
-
- div = (clk_get_rate(clk) * div) / rate;
-
- if (wait_for_pll_align())
- return -EBUSY;
- clk_reg_write_mask(CGU0_DIV, div << clk->shift,
- clk->mask);
- clk->rate = rate;
- return 0;
-}
-
-static struct clk_ops vco_ops = {
- .get_rate = vco_get_rate,
-};
-
-static struct clk_ops pll_ops = {
- .get_rate = pll_get_rate,
- .set_rate = pll_set_rate,
-};
-
-static struct clk_ops cclk_ops = {
- .get_rate = cclk_get_rate,
-};
-
-static struct clk_ops sys_clk_ops = {
- .get_rate = sys_clk_get_rate,
- .set_rate = sys_clk_set_rate,
- .round_rate = sys_clk_round_rate,
-};
-
-static struct clk_ops dummy_clk_ops = {
- .get_rate = dummy_get_rate,
-};
-
-static struct clk sys_clkin = {
- .name = "SYS_CLKIN",
- .rate = CONFIG_CLKIN_HZ,
- .ops = &vco_ops,
-};
-
-static struct clk pll_clk = {
- .name = "PLLCLK",
- .rate = 500000000,
- .parent = &sys_clkin,
- .ops = &pll_ops,
- .flags = NEEDS_INITIALIZATION,
-};
-
-static struct clk cclk = {
- .name = "CCLK",
- .rate = 500000000,
- .mask = CGU0_DIV_CSEL_MASK,
- .shift = CGU0_DIV_CSEL_SHIFT,
- .parent = &sys_clkin,
- .ops = &sys_clk_ops,
- .flags = NEEDS_INITIALIZATION,
-};
-
-static struct clk cclk0 = {
- .name = "CCLK0",
- .parent = &cclk,
- .ops = &cclk_ops,
-};
-
-static struct clk cclk1 = {
- .name = "CCLK1",
- .parent = &cclk,
- .ops = &cclk_ops,
-};
-
-static struct clk sysclk = {
- .name = "SYSCLK",
- .rate = 500000000,
- .mask = CGU0_DIV_SYSSEL_MASK,
- .shift = CGU0_DIV_SYSSEL_SHIFT,
- .parent = &sys_clkin,
- .ops = &sys_clk_ops,
- .flags = NEEDS_INITIALIZATION,
-};
-
-static struct clk sclk0 = {
- .name = "SCLK0",
- .rate = 500000000,
- .mask = CGU0_DIV_S0SEL_MASK,
- .shift = CGU0_DIV_S0SEL_SHIFT,
- .parent = &sysclk,
- .ops = &sys_clk_ops,
-};
-
-static struct clk sclk1 = {
- .name = "SCLK1",
- .rate = 500000000,
- .mask = CGU0_DIV_S1SEL_MASK,
- .shift = CGU0_DIV_S1SEL_SHIFT,
- .parent = &sysclk,
- .ops = &sys_clk_ops,
-};
-
-static struct clk dclk = {
- .name = "DCLK",
- .rate = 500000000,
- .mask = CGU0_DIV_DSEL_MASK,
- .shift = CGU0_DIV_DSEL_SHIFT,
- .parent = &sys_clkin,
- .ops = &sys_clk_ops,
-};
-
-static struct clk oclk = {
- .name = "OCLK",
- .rate = 500000000,
- .mask = CGU0_DIV_OSEL_MASK,
- .shift = CGU0_DIV_OSEL_SHIFT,
- .parent = &pll_clk,
-};
-
-static struct clk ethclk = {
- .name = "stmmaceth",
- .parent = &sclk0,
- .ops = &dummy_clk_ops,
-};
-
-static struct clk ethpclk = {
- .name = "pclk",
- .parent = &sclk0,
- .ops = &dummy_clk_ops,
-};
-
-static struct clk spiclk = {
- .name = "spi",
- .parent = &sclk1,
- .ops = &dummy_clk_ops,
-};
-
-static struct clk_lookup bf609_clks[] = {
- CLK(sys_clkin, NULL, "SYS_CLKIN"),
- CLK(pll_clk, NULL, "PLLCLK"),
- CLK(cclk, NULL, "CCLK"),
- CLK(cclk0, NULL, "CCLK0"),
- CLK(cclk1, NULL, "CCLK1"),
- CLK(sysclk, NULL, "SYSCLK"),
- CLK(sclk0, NULL, "SCLK0"),
- CLK(sclk1, NULL, "SCLK1"),
- CLK(dclk, NULL, "DCLK"),
- CLK(oclk, NULL, "OCLK"),
- CLK(ethclk, NULL, "stmmaceth"),
- CLK(ethpclk, NULL, "pclk"),
- CLK(spiclk, NULL, "spi"),
-};
-
-int __init clk_init(void)
-{
- int i;
- struct clk *clkp;
- for (i = 0; i < ARRAY_SIZE(bf609_clks); i++) {
- clkp = bf609_clks[i].clk;
- if (clkp->flags & NEEDS_INITIALIZATION)
- clk_get_rate(clkp);
- }
- clkdev_add_table(bf609_clks, ARRAY_SIZE(bf609_clks));
- return 0;
-}
+++ /dev/null
-/*
- * the simple DMA Implementation for Blackfin
- *
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-
-#include <asm/blackfin.h>
-#include <asm/dma.h>
-
-struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
- (struct dma_register *) DMA0_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_NEXT_DESC_PTR,
- (struct dma_register *) DMA3_NEXT_DESC_PTR,
- (struct dma_register *) DMA4_NEXT_DESC_PTR,
- (struct dma_register *) DMA5_NEXT_DESC_PTR,
- (struct dma_register *) DMA6_NEXT_DESC_PTR,
- (struct dma_register *) DMA7_NEXT_DESC_PTR,
- (struct dma_register *) DMA8_NEXT_DESC_PTR,
- (struct dma_register *) DMA9_NEXT_DESC_PTR,
- (struct dma_register *) DMA10_NEXT_DESC_PTR,
- (struct dma_register *) DMA11_NEXT_DESC_PTR,
- (struct dma_register *) DMA12_NEXT_DESC_PTR,
- (struct dma_register *) DMA13_NEXT_DESC_PTR,
- (struct dma_register *) DMA14_NEXT_DESC_PTR,
- (struct dma_register *) DMA15_NEXT_DESC_PTR,
- (struct dma_register *) DMA16_NEXT_DESC_PTR,
- (struct dma_register *) DMA17_NEXT_DESC_PTR,
- (struct dma_register *) DMA18_NEXT_DESC_PTR,
- (struct dma_register *) DMA19_NEXT_DESC_PTR,
- (struct dma_register *) DMA20_NEXT_DESC_PTR,
- (struct dma_register *) MDMA0_SRC_CRC0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA0_DEST_CRC0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA1_SRC_CRC1_NEXT_DESC_PTR,
- (struct dma_register *) MDMA1_DEST_CRC1_NEXT_DESC_PTR,
- (struct dma_register *) MDMA2_SRC_NEXT_DESC_PTR,
- (struct dma_register *) MDMA2_DEST_NEXT_DESC_PTR,
- (struct dma_register *) MDMA3_SRC_NEXT_DESC_PTR,
- (struct dma_register *) MDMA3_DEST_NEXT_DESC_PTR,
- (struct dma_register *) DMA29_NEXT_DESC_PTR,
- (struct dma_register *) DMA30_NEXT_DESC_PTR,
- (struct dma_register *) DMA31_NEXT_DESC_PTR,
- (struct dma_register *) DMA32_NEXT_DESC_PTR,
- (struct dma_register *) DMA33_NEXT_DESC_PTR,
- (struct dma_register *) DMA34_NEXT_DESC_PTR,
- (struct dma_register *) DMA35_NEXT_DESC_PTR,
- (struct dma_register *) DMA36_NEXT_DESC_PTR,
- (struct dma_register *) DMA37_NEXT_DESC_PTR,
- (struct dma_register *) DMA38_NEXT_DESC_PTR,
- (struct dma_register *) DMA39_NEXT_DESC_PTR,
- (struct dma_register *) DMA40_NEXT_DESC_PTR,
- (struct dma_register *) DMA41_NEXT_DESC_PTR,
- (struct dma_register *) DMA42_NEXT_DESC_PTR,
- (struct dma_register *) DMA43_NEXT_DESC_PTR,
- (struct dma_register *) DMA44_NEXT_DESC_PTR,
- (struct dma_register *) DMA45_NEXT_DESC_PTR,
- (struct dma_register *) DMA46_NEXT_DESC_PTR,
-};
-EXPORT_SYMBOL(dma_io_base_addr);
-
-int channel2irq(unsigned int channel)
-{
- int ret_irq = -1;
-
- switch (channel) {
- case CH_SPORT0_RX:
- ret_irq = IRQ_SPORT0_RX;
- break;
- case CH_SPORT0_TX:
- ret_irq = IRQ_SPORT0_TX;
- break;
- case CH_SPORT1_RX:
- ret_irq = IRQ_SPORT1_RX;
- break;
- case CH_SPORT1_TX:
- ret_irq = IRQ_SPORT1_TX;
- break;
- case CH_SPORT2_RX:
- ret_irq = IRQ_SPORT2_RX;
- break;
- case CH_SPORT2_TX:
- ret_irq = IRQ_SPORT2_TX;
- break;
- case CH_SPI0_TX:
- ret_irq = IRQ_SPI0_TX;
- break;
- case CH_SPI0_RX:
- ret_irq = IRQ_SPI0_RX;
- break;
- case CH_SPI1_TX:
- ret_irq = IRQ_SPI1_TX;
- break;
- case CH_SPI1_RX:
- ret_irq = IRQ_SPI1_RX;
- break;
- case CH_RSI:
- ret_irq = IRQ_RSI;
- break;
- case CH_SDU:
- ret_irq = IRQ_SDU;
- break;
- case CH_LP0:
- ret_irq = IRQ_LP0;
- break;
- case CH_LP1:
- ret_irq = IRQ_LP1;
- break;
- case CH_LP2:
- ret_irq = IRQ_LP2;
- break;
- case CH_LP3:
- ret_irq = IRQ_LP3;
- break;
- case CH_UART0_RX:
- ret_irq = IRQ_UART0_RX;
- break;
- case CH_UART0_TX:
- ret_irq = IRQ_UART0_TX;
- break;
- case CH_UART1_RX:
- ret_irq = IRQ_UART1_RX;
- break;
- case CH_UART1_TX:
- ret_irq = IRQ_UART1_TX;
- break;
- case CH_EPPI0_CH0:
- ret_irq = IRQ_EPPI0_CH0;
- break;
- case CH_EPPI0_CH1:
- ret_irq = IRQ_EPPI0_CH1;
- break;
- case CH_EPPI1_CH0:
- ret_irq = IRQ_EPPI1_CH0;
- break;
- case CH_EPPI1_CH1:
- ret_irq = IRQ_EPPI1_CH1;
- break;
- case CH_EPPI2_CH0:
- ret_irq = IRQ_EPPI2_CH0;
- break;
- case CH_EPPI2_CH1:
- ret_irq = IRQ_EPPI2_CH1;
- break;
- case CH_PIXC_CH0:
- ret_irq = IRQ_PIXC_CH0;
- break;
- case CH_PIXC_CH1:
- ret_irq = IRQ_PIXC_CH1;
- break;
- case CH_PIXC_CH2:
- ret_irq = IRQ_PIXC_CH2;
- break;
- case CH_PVP_CPDOB:
- ret_irq = IRQ_PVP_CPDOB;
- break;
- case CH_PVP_CPDOC:
- ret_irq = IRQ_PVP_CPDOC;
- break;
- case CH_PVP_CPSTAT:
- ret_irq = IRQ_PVP_CPSTAT;
- break;
- case CH_PVP_CPCI:
- ret_irq = IRQ_PVP_CPCI;
- break;
- case CH_PVP_MPDO:
- ret_irq = IRQ_PVP_MPDO;
- break;
- case CH_PVP_MPDI:
- ret_irq = IRQ_PVP_MPDI;
- break;
- case CH_PVP_MPSTAT:
- ret_irq = IRQ_PVP_MPSTAT;
- break;
- case CH_PVP_MPCI:
- ret_irq = IRQ_PVP_MPCI;
- break;
- case CH_PVP_CPDOA:
- ret_irq = IRQ_PVP_CPDOA;
- break;
- case CH_MEM_STREAM0_SRC:
- case CH_MEM_STREAM0_DEST:
- ret_irq = IRQ_MDMAS0;
- break;
- case CH_MEM_STREAM1_SRC:
- case CH_MEM_STREAM1_DEST:
- ret_irq = IRQ_MDMAS1;
- break;
- case CH_MEM_STREAM2_SRC:
- case CH_MEM_STREAM2_DEST:
- ret_irq = IRQ_MDMAS2;
- break;
- case CH_MEM_STREAM3_SRC:
- case CH_MEM_STREAM3_DEST:
- ret_irq = IRQ_MDMAS3;
- break;
- }
- return ret_irq;
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-#include <linux/linkage.h>
-#include <asm/blackfin.h>
-#include <asm/dpmc.h>
-
-#include <asm/context.S>
-
-#define PM_STACK (COREA_L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12)
-
-.section .l1.text
-ENTRY(_enter_hibernate)
- /* switch stack to L1 scratch, prepare for ddr srfr */
- P0.H = HI(PM_STACK);
- P0.L = LO(PM_STACK);
- SP = P0;
-
- call _bf609_ddr_sr;
- call _bfin_hibernate_syscontrol;
-
- P0.H = HI(DPM0_RESTORE4);
- P0.L = LO(DPM0_RESTORE4);
- P1.H = _bf609_pm_data;
- P1.L = _bf609_pm_data;
- [P0] = P1;
-
- P0.H = HI(DPM0_CTL);
- P0.L = LO(DPM0_CTL);
- R3.H = HI(0x00000010);
- R3.L = LO(0x00000010);
-
- bfin_init_pm_bench_cycles;
-
- [P0] = R3;
-
- SSYNC;
-ENDPROC(_enter_hibernate)
-
-/* DPM wake up interrupt won't wake up core on bf60x if its core IMASK
- * is disabled. This behavior differ from bf5xx serial processor.
- */
-ENTRY(_dummy_deepsleep)
- [--sp] = SYSCFG;
- [--sp] = (R7:0,P5:0);
- cli r0;
-
- /* get wake up interrupt ID */
- P0.l = LO(SEC_SCI_BASE + SEC_CSID);
- P0.h = HI(SEC_SCI_BASE + SEC_CSID);
- R0 = [P0];
-
- /* ACK wake up interrupt in SEC */
- P1.l = LO(SEC_END);
- P1.h = HI(SEC_END);
-
- [P1] = R0;
- SSYNC;
-
- /* restore EVT 11 entry */
- p0.h = hi(EVT11);
- p0.l = lo(EVT11);
- p1.h = _evt_evt11;
- p1.l = _evt_evt11;
-
- [p0] = p1;
- SSYNC;
-
- (R7:0,P5:0) = [sp++];
- SYSCFG = [sp++];
- RTI;
-ENDPROC(_dummy_deepsleep)
-
-ENTRY(_enter_deepsleep)
- LINK 0xC;
- [--sp] = (R7:0,P5:0);
-
- /* Change EVT 11 entry to dummy handler for wake up event */
- p0.h = hi(EVT11);
- p0.l = lo(EVT11);
- p1.h = _dummy_deepsleep;
- p1.l = _dummy_deepsleep;
-
- [p0] = p1;
-
- P0.H = HI(PM_STACK);
- P0.L = LO(PM_STACK);
-
- EX_SCRATCH_REG = SP;
- SP = P0;
-
- SSYNC;
-
- /* should put ddr to self refresh mode before sleep */
- call _bf609_ddr_sr;
-
- /* Set DPM controller to deep sleep mode */
- P0.H = HI(DPM0_CTL);
- P0.L = LO(DPM0_CTL);
- R3.H = HI(0x00000008);
- R3.L = LO(0x00000008);
- [P0] = R3;
- CSYNC;
-
- /* Enable evt 11 in IMASK before idle, otherwise core doesn't wake up. */
- r0.l = 0x800;
- r0.h = 0;
- sti r0;
- SSYNC;
-
- bfin_init_pm_bench_cycles;
-
- /* Fall into deep sleep in idle*/
- idle;
- SSYNC;
-
- /* Restore PLL after wake up from deep sleep */
- call _bf609_resume_ccbuf;
-
- /* turn ddr out of self refresh mode */
- call _bf609_ddr_sr_exit;
-
- SP = EX_SCRATCH_REG;
-
- (R7:0,P5:0) = [SP++];
- UNLINK;
- RTS;
-ENDPROC(_enter_deepsleep)
-
-.section .text
-ENTRY(_bf609_hibernate)
- bfin_cpu_reg_save;
- bfin_core_mmr_save;
-
- P0.H = _bf609_pm_data;
- P0.L = _bf609_pm_data;
- R1.H = 0xDEAD;
- R1.L = 0xBEEF;
- R2.H = .Lpm_resume_here;
- R2.L = .Lpm_resume_here;
- [P0++] = R1;
- [P0++] = R2;
- [P0++] = SP;
-
- P1.H = _enter_hibernate;
- P1.L = _enter_hibernate;
-
- call (P1);
-.Lpm_resume_here:
-
- bfin_core_mmr_restore;
- bfin_cpu_reg_restore;
-
- [--sp] = RETI; /* Clear Global Interrupt Disable */
- SP += 4;
-
- RTS;
-
-ENDPROC(_bf609_hibernate)
-
+++ /dev/null
-/*
- * DO NOT EDIT THIS FILE
- * This file is under version control at
- * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
- * and can be replaced with that version at any time
- * DO NOT EDIT THIS FILE
- *
- * Copyright 2004-2012 Analog Devices Inc.
- * Licensed under the Clear BSD license.
- */
-
-/* This file should be up to date with:
- * - Revision A, 15/06/2012; ADSP-BF609 Blackfin Processor Anomaly List
- */
-
-#if __SILICON_REVISION__ < 0
-# error will not work on BF609 silicon version
-#endif
-
-#ifndef _MACH_ANOMALY_H_
-#define _MACH_ANOMALY_H_
-
-/* TRU_STAT.ADDRERR and TRU_ERRADDR.ADDR May Not Reflect the Correct Status */
-#define ANOMALY_16000003 (1)
-/* The EPPI Data Enable (DEN) Signal is Not Functional */
-#define ANOMALY_16000004 (__SILICON_REVISION__ < 1)
-/* Using L1 Instruction Cache with Parity Enabled is Unreliable */
-#define ANOMALY_16000005 (__SILICON_REVISION__ < 1)
-/* SEQSTAT.SYSNMI Clears Upon Entering the NMI ISR */
-#define ANOMALY_16000006 (__SILICON_REVISION__ < 1)
-/* DDR2 Memory Reads May Fail Intermittently */
-#define ANOMALY_16000007 (1)
-/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
-#define ANOMALY_16000008 (1)
-/* TestSET Instruction Cannot Be Interrupted */
-#define ANOMALY_16000009 (1)
-/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
-#define ANOMALY_16000010 (1)
-/* False Hardware Error when RETI Points to Invalid Memory */
-#define ANOMALY_16000011 (1)
-/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
-#define ANOMALY_16000012 (1)
-/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
-#define ANOMALY_16000013 (1)
-/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
-#define ANOMALY_16000014 (1)
-/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
-#define ANOMALY_16000015 (1)
-/* Speculative Fetches Can Cause Undesired External FIFO Operations */
-#define ANOMALY_16000017 (1)
-/* RSI Boot Cleanup Routine Does Not Clear Registers */
-#define ANOMALY_16000018 (__SILICON_REVISION__ < 1)
-/* SPI Master Boot Device Auto-detection Frequency is Set Incorrectly */
-#define ANOMALY_16000019 (__SILICON_REVISION__ < 1)
-/* rom_SysControl() Fails to Set DDR0_CTL.INIT for Wakeup From Hibernate */
-#define ANOMALY_16000020 (__SILICON_REVISION__ < 1)
-/* rom_SysControl() Fails to Save and Restore DDR0_PHYCTL3 for Hibernate/Wakeup Sequence */
-#define ANOMALY_16000021 (__SILICON_REVISION__ < 1)
-/* Boot Code Fails to Enable Parity Fault Detection */
-#define ANOMALY_16000022 (__SILICON_REVISION__ < 1)
-/* Rom_SysControl Does not Update CGU0_CLKOUTSEL */
-#define ANOMALY_16000023 (__SILICON_REVISION__ < 1)
-/* Spurious Fault Signaled After Clearing an Externally Generated Fault */
-#define ANOMALY_16000024 (1)
-/* SPORT May Drive Data Pins During Inactive Channels in Multichannel Mode */
-#define ANOMALY_16000025 (1)
-/* USB DMA interrupt status do not show the DMA channel interrupt in the DMA ISR */
-#define ANOMALY_16000027 (__SILICON_REVISION__ < 1)
-/* Default SPI Master Boot Mode Setting is Incorrect */
-#define ANOMALY_16000028 (__SILICON_REVISION__ < 1)
-/* PPI tDFSPI Timing Does Not Meet Data Sheet Specification */
-#define ANOMALY_16000027 (__SILICON_REVISION__ < 1)
-/* Interrupted Core Reads of MMRs May Cause Data Loss */
-#define ANOMALY_16000030 (__SILICON_REVISION__ < 1)
-/* Incorrect Default USB_PLL_OSC.PLLM Value */
-#define ANOMALY_16000031 (__SILICON_REVISION__ < 1)
-/* Core Reads of System MMRs May Cause the Core to Hang */
-#define ANOMALY_16000032 (__SILICON_REVISION__ < 1)
-/* PPI Data Underflow on First Word Not Reported in Certain Modes */
-#define ANOMALY_16000033 (1)
-/* CNV1 Red Pixel Substitution feature not functional in the PVP */
-#define ANOMALY_16000034 (__SILICON_REVISION__ < 1)
-/* IPF0 Output Port Color Separation feature not functional */
-#define ANOMALY_16000035 (__SILICON_REVISION__ < 1)
-/* Spurious USB Wake From Hibernate May Occur When USB_VBUS is Low */
-#define ANOMALY_16000036 (__SILICON_REVISION__ < 1)
-/* Core RAISE 2 Instruction Not Latched When Executed at Priority Level 0, 1, or 2 */
-#define ANOMALY_16000037 (__SILICON_REVISION__ < 1)
-/* Spurious Unhandled NMI or L1 Memory Parity Error Interrupt May Occur Upon Entering the NMI ISR */
-#define ANOMALY_16000038 (__SILICON_REVISION__ < 1)
-/* CGU_STAT.PLOCKERR Bit May be Unreliable */
-#define ANOMALY_16000039 (1)
-/* JTAG Emulator Reads of SDU_IDCODE Alter Register Contents */
-#define ANOMALY_16000040 (1)
-/* IFLUSH Instruction Causes Parity Error When Parity Is Enabled */
-#define ANOMALY_16000041 (1)
-/* Instruction Cache Failure When Parity Is Enabled */
-#define ANOMALY_16000042 (__SILICON_REVISION__ == 1)
-
-/* Anomalies that don't exist on this proc */
-#define ANOMALY_05000158 (0)
-#define ANOMALY_05000189 (0)
-#define ANOMALY_05000198 (0)
-#define ANOMALY_05000220 (0)
-#define ANOMALY_05000230 (0)
-#define ANOMALY_05000231 (0)
-#define ANOMALY_05000244 (0)
-#define ANOMALY_05000263 (0)
-#define ANOMALY_05000273 (0)
-#define ANOMALY_05000274 (0)
-#define ANOMALY_05000278 (0)
-#define ANOMALY_05000281 (0)
-#define ANOMALY_05000287 (0)
-#define ANOMALY_05000311 (0)
-#define ANOMALY_05000312 (0)
-#define ANOMALY_05000323 (0)
-#define ANOMALY_05000363 (0)
-#define ANOMALY_05000380 (0)
-#define ANOMALY_05000448 (0)
-#define ANOMALY_05000450 (0)
-#define ANOMALY_05000456 (0)
-#define ANOMALY_05000480 (0)
-#define ANOMALY_05000481 (1)
-
-/* Reuse BF5xx anomalies IDs for the same anomaly in BF60x */
-#define ANOMALY_05000491 ANOMALY_16000008
-#define ANOMALY_05000477 ANOMALY_16000009
-#define ANOMALY_05000443 ANOMALY_16000010
-#define ANOMALY_05000461 ANOMALY_16000011
-#define ANOMALY_05000426 ANOMALY_16000012
-#define ANOMALY_05000310 ANOMALY_16000013
-#define ANOMALY_05000245 ANOMALY_16000014
-#define ANOMALY_05000074 ANOMALY_16000015
-#define ANOMALY_05000416 ANOMALY_16000017
-
-
-#endif
+++ /dev/null
-/*
- * Copyright 2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __MACH_BF609_H__
-#define __MACH_BF609_H__
-
-#define OFFSET_(x) ((x) & 0x0000FFFF)
-
-/*some misc defines*/
-#define IMASK_IVG15 0x8000
-#define IMASK_IVG14 0x4000
-#define IMASK_IVG13 0x2000
-#define IMASK_IVG12 0x1000
-
-#define IMASK_IVG11 0x0800
-#define IMASK_IVG10 0x0400
-#define IMASK_IVG9 0x0200
-#define IMASK_IVG8 0x0100
-
-#define IMASK_IVG7 0x0080
-#define IMASK_IVGTMR 0x0040
-#define IMASK_IVGHW 0x0020
-
-/***************************/
-
-
-#define BFIN_DSUBBANKS 4
-#define BFIN_DWAYS 2
-#define BFIN_DLINES 64
-#define BFIN_ISUBBANKS 4
-#define BFIN_IWAYS 4
-#define BFIN_ILINES 32
-
-#define WAY0_L 0x1
-#define WAY1_L 0x2
-#define WAY01_L 0x3
-#define WAY2_L 0x4
-#define WAY02_L 0x5
-#define WAY12_L 0x6
-#define WAY012_L 0x7
-
-#define WAY3_L 0x8
-#define WAY03_L 0x9
-#define WAY13_L 0xA
-#define WAY013_L 0xB
-
-#define WAY32_L 0xC
-#define WAY320_L 0xD
-#define WAY321_L 0xE
-#define WAYALL_L 0xF
-
-#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
-
-/********************************* EBIU Settings ************************************/
-#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
-#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
-
-#ifdef CONFIG_C_AMBEN_ALL
-#define V_AMBEN AMBEN_ALL
-#endif
-#ifdef CONFIG_C_AMBEN
-#define V_AMBEN 0x0
-#endif
-#ifdef CONFIG_C_AMBEN_B0
-#define V_AMBEN AMBEN_B0
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1
-#define V_AMBEN AMBEN_B0_B1
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1_B2
-#define V_AMBEN AMBEN_B0_B1_B2
-#endif
-#ifdef CONFIG_C_AMCKEN
-#define V_AMCKEN AMCKEN
-#else
-#define V_AMCKEN 0x0
-#endif
-
-#define AMGCTLVAL (V_AMBEN | V_AMCKEN)
-
-#if defined(CONFIG_BF609)
-# define CPU "BF609"
-# define CPUID 0x27fe /* temperary fake value */
-#endif
-
-#ifndef CPU
-#error "Unknown CPU type - This kernel doesn't seem to be configured properly"
-#endif
-
-#endif /* __MACH_BF609_H__ */
+++ /dev/null
-/*
- * mach/bfin_serial.h - Blackfin UART/Serial definitions
- *
- * Copyright 2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MACH_SERIAL_H__
-#define __BFIN_MACH_SERIAL_H__
-
-#define BFIN_UART_NR_PORTS 2
-#define BFIN_UART_TX_FIFO_SIZE 8
-
-#define BFIN_UART_BF60X_STYLE
-
-#endif
+++ /dev/null
-/*
- * Copyright 2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_BLACKFIN_H_
-#define _MACH_BLACKFIN_H_
-
-#include "bf609.h"
-#include "anomaly.h"
-
-#include <asm/def_LPBlackfin.h>
-#ifdef CONFIG_BF609
-# include "defBF609.h"
-#endif
-
-#ifndef __ASSEMBLY__
-# include <asm/cdef_LPBlackfin.h>
-# ifdef CONFIG_BF609
-# include "cdefBF609.h"
-# endif
-#endif
-
-#endif
+++ /dev/null
-/*
- * Copyright 2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CDEF_BF609_H
-#define _CDEF_BF609_H
-
-/* include cdefBF60x_base.h for the set of #defines that are common to all ADSP-BF60x bfin_read_()rocessors */
-#include "cdefBF60x_base.h"
-
-/* The following are the #defines needed by ADSP-BF609 that are not in the common header */
-
-#endif /* _CDEF_BF609_H */
+++ /dev/null
-/*
- * Copyright 2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CDEF_BF60X_H
-#define _CDEF_BF60X_H
-
-/* ************************************************************** */
-/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF60x */
-/* ************************************************************** */
-
-/* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */
-
-#define bfin_read_CHIPID() bfin_read32(CHIPID)
-#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
-
-/* System Reset and Interrubfin_read_()t Controller (0xFFC00100 - 0xFFC00104) */
-
-/* SEC0 Registers */
-#define bfin_read_SEC0_CCTL() bfin_read32(SEC0_CCTL)
-#define bfin_write_SEC0_CCTL(val) bfin_write32(SEC0_CCTL, val)
-#define bfin_read_SEC0_CSID() bfin_read32(SEC0_CSID)
-#define bfin_write_SEC0_CSID(val) bfin_write32(SEC0_CSID, val)
-#define bfin_read_SEC_GCTL() bfin_read32(SEC_GCTL)
-#define bfin_write_SEC_GCTL(val) bfin_write32(SEC_GCTL, val)
-
-#define bfin_read_SEC_FCTL() bfin_read32(SEC_FCTL)
-#define bfin_write_SEC_FCTL(val) bfin_write32(SEC_FCTL, val)
-
-#define bfin_read_SEC_SCTL(sid) bfin_read32((SEC_SCTL0 + (sid) * 8))
-#define bfin_write_SEC_SCTL(sid, val) bfin_write32((SEC_SCTL0 + (sid) * 8), val)
-
-#define bfin_read_SEC_SSTAT(sid) bfin_read32((SEC_SSTAT0 + (sid) * 8))
-#define bfin_write_SEC_SSTAT(sid, val) bfin_write32((SEC_SSTAT0 + (sid) * 8), val)
-
-/* RCU0 Registers */
-#define bfin_read_RCU0_CTL() bfin_read32(RCU0_CTL)
-#define bfin_write_RCU0_CTL(val) bfin_write32(RCU0_CTL, val)
-
-/* Watchdog Timer Registers */
-#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
-#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
-#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
-
-/* RTC Registers */
-
-/* UART0 Registers */
-
-#define bfin_read_UART0_REVID() bfin_read32(UART0_REVID)
-#define bfin_write_UART0_REVID(val) bfin_write32(UART0_REVID, val)
-#define bfin_read_UART0_GCTL() bfin_read32(UART0_GCTL)
-#define bfin_write_UART0_GCTL(val) bfin_write32(UART0_GCTL, val)
-#define bfin_read_UART0_STAT() bfin_read32(UART0_STAT)
-#define bfin_write_UART0_STAT(val) bfin_write32(UART0_STAT, val)
-#define bfin_read_UART0_SCR() bfin_read32(UART0_SCR)
-#define bfin_write_UART0_SCR(val) bfin_write32(UART0_SCR, val)
-#define bfin_read_UART0_CLK() bfin_read32(UART0_CLK)
-#define bfin_write_UART0_CLK(val) bfin_write32(UART0_CLK, val)
-#define bfin_read_UART0_IER() bfin_read32(UART0_IER)
-#define bfin_write_UART0_IER(val) bfin_write32(UART0_IER, val)
-#define bfin_read_UART0_IER_SET() bfin_read32(UART0_IER_SET)
-#define bfin_write_UART0_IER_SET(val) bfin_write32(UART0_IER_SET, val)
-#define bfin_read_UART0_IER_CLEAR() bfin_read32(UART0_IER_CLEAR)
-#define bfin_write_UART0_IER_CLEAR(val) bfin_write32(UART0_IER_CLEAR, val)
-#define bfin_read_UART0_RBR() bfin_read32(UART0_RBR)
-#define bfin_write_UART0_RBR(val) bfin_write32(UART0_RBR, val)
-#define bfin_read_UART0_THR() bfin_read32(UART0_THR)
-#define bfin_write_UART0_THR(val) bfin_write32(UART0_THR, val)
-#define bfin_read_UART0_TAIP() bfin_read32(UART0_TAIP)
-#define bfin_write_UART0_TAIP(val) bfin_write32(UART0_TAIP, val)
-#define bfin_read_UART0_TSR() bfin_read32(UART0_TSR)
-#define bfin_write_UART0_TSR(val) bfin_write32(UART0_TSR, val)
-#define bfin_read_UART0_RSR() bfin_read32(UART0_RSR)
-#define bfin_write_UART0_RSR(val) bfin_write32(UART0_RSR, val)
-#define bfin_read_UART0_TXCNT() bfin_read32(UART0_TXCNT)
-#define bfin_write_UART0_TXCNT(val) bfin_write32(UART0_TXCNT, val)
-#define bfin_read_UART0_RXCNT() bfin_read32(UART0_RXCNT)
-#define bfin_write_UART0_RXCNT(val) bfin_write32(UART0_RXCNT, val)
-
-/* UART1 Registers */
-
-#define bfin_read_UART1_REVID() bfin_read32(UART1_REVID)
-#define bfin_write_UART1_REVID(val) bfin_write32(UART1_REVID, val)
-#define bfin_read_UART1_GCTL() bfin_read32(UART1_GCTL)
-#define bfin_write_UART1_GCTL(val) bfin_write32(UART1_GCTL, val)
-#define bfin_read_UART1_STAT() bfin_read32(UART1_STAT)
-#define bfin_write_UART1_STAT(val) bfin_write32(UART1_STAT, val)
-#define bfin_read_UART1_SCR() bfin_read32(UART1_SCR)
-#define bfin_write_UART1_SCR(val) bfin_write32(UART1_SCR, val)
-#define bfin_read_UART1_CLK() bfin_read32(UART1_CLK)
-#define bfin_write_UART1_CLK(val) bfin_write32(UART1_CLK, val)
-#define bfin_read_UART1_IER() bfin_read32(UART1_IER)
-#define bfin_write_UART1_IER(val) bfin_write32(UART1_IER, val)
-#define bfin_read_UART1_IER_SET() bfin_read32(UART1_IER_SET)
-#define bfin_write_UART1_IER_SET(val) bfin_write32(UART1_IER_SET, val)
-#define bfin_read_UART1_IER_CLEAR() bfin_read32(UART1_IER_CLEAR)
-#define bfin_write_UART1_IER_CLEAR(val) bfin_write32(UART1_IER_CLEAR, val)
-#define bfin_read_UART1_RBR() bfin_read32(UART1_RBR)
-#define bfin_write_UART1_RBR(val) bfin_write32(UART1_RBR, val)
-#define bfin_read_UART1_THR() bfin_read32(UART1_THR)
-#define bfin_write_UART1_THR(val) bfin_write32(UART1_THR, val)
-#define bfin_read_UART1_TAIP() bfin_read32(UART1_TAIP)
-#define bfin_write_UART1_TAIP(val) bfin_write32(UART1_TAIP, val)
-#define bfin_read_UART1_TSR() bfin_read32(UART1_TSR)
-#define bfin_write_UART1_TSR(val) bfin_write32(UART1_TSR, val)
-#define bfin_read_UART1_RSR() bfin_read32(UART1_RSR)
-#define bfin_write_UART1_RSR(val) bfin_write32(UART1_RSR, val)
-#define bfin_read_UART1_TXCNT() bfin_read32(UART1_TXCNT)
-#define bfin_write_UART1_TXCNT(val) bfin_write32(UART1_TXCNT, val)
-#define bfin_read_UART1_RXCNT() bfin_read32(UART1_RXCNT)
-#define bfin_write_UART1_RXCNT(val) bfin_write32(UART1_RXCNT, val)
-
-
-/* SPI0 Registers */
-
-#define bfin_read_SPI0_CTL() bfin_read32(SPI0_CTL)
-#define bfin_write_SPI0_CTL(val) bfin_write32(SPI0_CTL, val)
-#define bfin_read_SPI0_RXCTL() bfin_read32(SPI0_RXCTL)
-#define bfin_write_SPI0_RXCTL(val) bfin_write32(SPI0_RXCTL, val)
-#define bfin_read_SPI0_TXCTL() bfin_read32(SPI0_TXCTL)
-#define bfin_write_SPI0_TXCTL(val) bfin_write32(SPI0_TXCTL, val)
-#define bfin_read_SPI0_CLK() bfin_read32(SPI0_CLK)
-#define bfin_write_SPI0_CLK(val) bfin_write32(SPI0_CLK, val)
-#define bfin_read_SPI0_DLY() bfin_read32(SPI0_DLY)
-#define bfin_write_SPI0_DLY(val) bfin_write32(SPI0_DLY, val)
-#define bfin_read_SPI0_SLVSEL() bfin_read32(SPI0_SLVSEL)
-#define bfin_write_SPI0_SLVSEL(val) bfin_write32(SPI0_SLVSEL, val)
-#define bfin_read_SPI0_RWC() bfin_read32(SPI0_RWC)
-#define bfin_write_SPI0_RWC(val) bfin_write32(SPI0_RWC, val)
-#define bfin_read_SPI0_RWCR() bfin_read32(SPI0_RWCR)
-#define bfin_write_SPI0_RWCR(val) bfin_write32(SPI0_RWCR, val)
-#define bfin_read_SPI0_TWC() bfin_read32(SPI0_TWC)
-#define bfin_write_SPI0_TWC(val) bfin_write32(SPI0_TWC, val)
-#define bfin_read_SPI0_TWCR() bfin_read32(SPI0_TWCR)
-#define bfin_write_SPI0_TWCR(val) bfin_write32(SPI0_TWCR, val)
-#define bfin_read_SPI0_IMSK() bfin_read32(SPI0_IMSK)
-#define bfin_write_SPI0_IMSK(val) bfin_write32(SPI0_IMSK, val)
-#define bfin_read_SPI0_IMSK_CLR() bfin_read32(SPI0_IMSK_CLR)
-#define bfin_write_SPI0_IMSK_CLR(val) bfin_write32(SPI0_IMSK_CLR, val)
-#define bfin_read_SPI0_IMSK_SET() bfin_read32(SPI0_IMSK_SET)
-#define bfin_write_SPI0_IMSK_SET(val) bfin_write32(SPI0_IMSK_SET, val)
-#define bfin_read_SPI0_STAT() bfin_read32(SPI0_STAT)
-#define bfin_write_SPI0_STAT(val) bfin_write32(SPI0_STAT, val)
-#define bfin_read_SPI0_ILAT() bfin_read32(SPI0_ILAT)
-#define bfin_write_SPI0_ILAT(val) bfin_write32(SPI0_ILAT, val)
-#define bfin_read_SPI0_ILAT_CLR() bfin_read32(SPI0_ILAT_CLR)
-#define bfin_write_SPI0_ILAT_CLR(val) bfin_write32(SPI0_ILAT_CLR, val)
-#define bfin_read_SPI0_RFIFO() bfin_read32(SPI0_RFIFO)
-#define bfin_write_SPI0_RFIFO(val) bfin_write32(SPI0_RFIFO, val)
-#define bfin_read_SPI0_TFIFO() bfin_read32(SPI0_TFIFO)
-#define bfin_write_SPI0_TFIFO(val) bfin_write32(SPI0_TFIFO, val)
-
-/* SPI1 Registers */
-
-#define bfin_read_SPI1_CTL() bfin_read32(SPI1_CTL)
-#define bfin_write_SPI1_CTL(val) bfin_write32(SPI1_CTL, val)
-#define bfin_read_SPI1_RXCTL() bfin_read32(SPI1_RXCTL)
-#define bfin_write_SPI1_RXCTL(val) bfin_write32(SPI1_RXCTL, val)
-#define bfin_read_SPI1_TXCTL() bfin_read32(SPI1_TXCTL)
-#define bfin_write_SPI1_TXCTL(val) bfin_write32(SPI1_TXCTL, val)
-#define bfin_read_SPI1_CLK() bfin_read32(SPI1_CLK)
-#define bfin_write_SPI1_CLK(val) bfin_write32(SPI1_CLK, val)
-#define bfin_read_SPI1_DLY() bfin_read32(SPI1_DLY)
-#define bfin_write_SPI1_DLY(val) bfin_write32(SPI1_DLY, val)
-#define bfin_read_SPI1_SLVSEL() bfin_read32(SPI1_SLVSEL)
-#define bfin_write_SPI1_SLVSEL(val) bfin_write32(SPI1_SLVSEL, val)
-#define bfin_read_SPI1_RWC() bfin_read32(SPI1_RWC)
-#define bfin_write_SPI1_RWC(val) bfin_write32(SPI1_RWC, val)
-#define bfin_read_SPI1_RWCR() bfin_read32(SPI1_RWCR)
-#define bfin_write_SPI1_RWCR(val) bfin_write32(SPI1_RWCR, val)
-#define bfin_read_SPI1_TWC() bfin_read32(SPI1_TWC)
-#define bfin_write_SPI1_TWC(val) bfin_write32(SPI1_TWC, val)
-#define bfin_read_SPI1_TWCR() bfin_read32(SPI1_TWCR)
-#define bfin_write_SPI1_TWCR(val) bfin_write32(SPI1_TWCR, val)
-#define bfin_read_SPI1_IMSK() bfin_read32(SPI1_IMSK)
-#define bfin_write_SPI1_IMSK(val) bfin_write32(SPI1_IMSK, val)
-#define bfin_read_SPI1_IMSK_CLR() bfin_read32(SPI1_IMSK_CLR)
-#define bfin_write_SPI1_IMSK_CLR(val) bfin_write32(SPI1_IMSK_CLR, val)
-#define bfin_read_SPI1_IMSK_SET() bfin_read32(SPI1_IMSK_SET)
-#define bfin_write_SPI1_IMSK_SET(val) bfin_write32(SPI1_IMSK_SET, val)
-#define bfin_read_SPI1_STAT() bfin_read32(SPI1_STAT)
-#define bfin_write_SPI1_STAT(val) bfin_write32(SPI1_STAT, val)
-#define bfin_read_SPI1_ILAT() bfin_read32(SPI1_ILAT)
-#define bfin_write_SPI1_ILAT(val) bfin_write32(SPI1_ILAT, val)
-#define bfin_read_SPI1_ILAT_CLR() bfin_read32(SPI1_ILAT_CLR)
-#define bfin_write_SPI1_ILAT_CLR(val) bfin_write32(SPI1_ILAT_CLR, val)
-#define bfin_read_SPI1_RFIFO() bfin_read32(SPI1_RFIFO)
-#define bfin_write_SPI1_RFIFO(val) bfin_write32(SPI1_RFIFO, val)
-#define bfin_read_SPI1_TFIFO() bfin_read32(SPI1_TFIFO)
-#define bfin_write_SPI1_TFIFO(val) bfin_write32(SPI1_TFIFO, val)
-
-/* Timer 0-7 registers */
-#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
-#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
-#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
-#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
-#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
-#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
-#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
-#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
-#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
-#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
-#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val)
-#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
-#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
-#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
-#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val)
-#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
-#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val)
-#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
-#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val)
-#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
-#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
-#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
-#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val)
-#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
-#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val)
-#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
-#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val)
-#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
-#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
-#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
-#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val)
-#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
-#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val)
-#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
-#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val)
-#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
-#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
-#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
-#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val)
-#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
-#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val)
-#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
-#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val)
-#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
-#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
-#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
-#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val)
-#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
-#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val)
-
-
-
-
-/* Two Wire Interface Registers (TWI0) */
-
-/* SPORT1 Registers */
-
-
-/* SMC Registers */
-#define bfin_read_SMC_GCTL() bfin_read32(SMC_GCTL)
-#define bfin_write_SMC_GCTL(val) bfin_write32(SMC_GCTL, val)
-#define bfin_read_SMC_GSTAT() bfin_read32(SMC_GSTAT)
-#define bfin_read_SMC_B0CTL() bfin_read32(SMC_B0CTL)
-#define bfin_write_SMC_B0CTL(val) bfin_write32(SMC_B0CTL, val)
-#define bfin_read_SMC_B0TIM() bfin_read32(SMC_B0TIM)
-#define bfin_write_SMC_B0TIM(val) bfin_write32(SMC_B0TIM, val)
-#define bfin_read_SMC_B0ETIM() bfin_read32(SMC_B0ETIM)
-#define bfin_write_SMC_B0ETIM(val) bfin_write32(SMC_B0ETIM, val)
-#define bfin_read_SMC_B1CTL() bfin_read32(SMC_B1CTL)
-#define bfin_write_SMC_B1CTL(val) bfin_write32(SMC_B1CTL, val)
-#define bfin_read_SMC_B1TIM() bfin_read32(SMC_B1TIM)
-#define bfin_write_SMC_B1TIM(val) bfin_write32(SMC_B1TIM, val)
-#define bfin_read_SMC_B1ETIM() bfin_read32(SMC_B1ETIM)
-#define bfin_write_SMC_B1ETIM(val) bfin_write32(SMC_B1ETIM, val)
-#define bfin_read_SMC_B2CTL() bfin_read32(SMC_B2CTL)
-#define bfin_write_SMC_B2CTL(val) bfin_write32(SMC_B2CTL, val)
-#define bfin_read_SMC_B2TIM() bfin_read32(SMC_B2TIM)
-#define bfin_write_SMC_B2TIM(val) bfin_write32(SMC_B2TIM, val)
-#define bfin_read_SMC_B2ETIM() bfin_read32(SMC_B2ETIM)
-#define bfin_write_SMC_B2ETIM(val) bfin_write32(SMC_B2ETIM, val)
-#define bfin_read_SMC_B3CTL() bfin_read32(SMC_B3CTL)
-#define bfin_write_SMC_B3CTL(val) bfin_write32(SMC_B3CTL, val)
-#define bfin_read_SMC_B3TIM() bfin_read32(SMC_B3TIM)
-#define bfin_write_SMC_B3TIM(val) bfin_write32(SMC_B3TIM, val)
-#define bfin_read_SMC_B3ETIM() bfin_read32(SMC_B3ETIM)
-#define bfin_write_SMC_B3ETIM(val) bfin_write32(SMC_B3ETIM, val)
-
-/* DDR2 Memory Control Registers */
-#define bfin_read_DMC0_CFG() bfin_read32(DMC0_CFG)
-#define bfin_write_DMC0_CFG(val) bfin_write32(DMC0_CFG, val)
-#define bfin_read_DMC0_TR0() bfin_read32(DMC0_TR0)
-#define bfin_write_DMC0_TR0(val) bfin_write32(DMC0_TR0, val)
-#define bfin_read_DMC0_TR1() bfin_read32(DMC0_TR1)
-#define bfin_write_DMC0_TR1(val) bfin_write32(DMC0_TR1, val)
-#define bfin_read_DMC0_TR2() bfin_read32(DMC0_TR2)
-#define bfin_write_DMC0_TR2(val) bfin_write32(DMC0_TR2, val)
-#define bfin_read_DMC0_MR() bfin_read32(DMC0_MR)
-#define bfin_write_DMC0_MR(val) bfin_write32(DMC0_MR, val)
-#define bfin_read_DMC0_EMR1() bfin_read32(DMC0_EMR1)
-#define bfin_write_DMC0_EMR1(val) bfin_write32(DMC0_EMR1, val)
-#define bfin_read_DMC0_CTL() bfin_read32(DMC0_CTL)
-#define bfin_write_DMC0_CTL(val) bfin_write32(DMC0_CTL, val)
-#define bfin_read_DMC0_EFFCTL() bfin_read32(DMC0_EFFCTL)
-#define bfin_write_DMC0_EFFCTL(val) bfin_write32(DMC0_EFFCTL, val)
-#define bfin_read_DMC0_STAT() bfin_read32(DMC0_STAT)
-#define bfin_write_DMC0_STAT(val) bfin_write32(DMC0_STAT, val)
-#define bfin_read_DMC0_DLLCTL() bfin_read32(DMC0_DLLCTL)
-#define bfin_write_DMC0_DLLCTL(val) bfin_write32(DMC0_DLLCTL, val)
-
-/* DDR BankRead and Write Count Registers */
-
-
-/* DMA Channel 0 Registers */
-
-#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val)
-#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val)
-#define bfin_read_DMA0_CONFIG() bfin_read32(DMA0_CONFIG)
-#define bfin_write_DMA0_CONFIG(val) bfin_write32(DMA0_CONFIG, val)
-#define bfin_read_DMA0_X_COUNT() bfin_read32(DMA0_X_COUNT)
-#define bfin_write_DMA0_X_COUNT(val) bfin_write32(DMA0_X_COUNT, val)
-#define bfin_read_DMA0_X_MODIFY() bfin_read32(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val) bfin_write32(DMA0_X_MODIFY, val)
-#define bfin_read_DMA0_Y_COUNT() bfin_read32(DMA0_Y_COUNT)
-#define bfin_write_DMA0_Y_COUNT(val) bfin_write32(DMA0_Y_COUNT, val)
-#define bfin_read_DMA0_Y_MODIFY() bfin_read32(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val) bfin_write32(DMA0_Y_MODIFY, val)
-#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val)
-#define bfin_read_DMA0_PREV_DESC_PTR() bfin_read32(DMA0_PREV_DESC_PTR)
-#define bfin_write_DMA0_PREV_DESC_PTR(val) bfin_write32(DMA0_PREV_DESC_PTR, val)
-#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val)
-#define bfin_read_DMA0_IRQ_STATUS() bfin_read32(DMA0_IRQ_STATUS)
-#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write32(DMA0_IRQ_STATUS, val)
-#define bfin_read_DMA0_CURR_X_COUNT() bfin_read32(DMA0_CURR_X_COUNT)
-#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write32(DMA0_CURR_X_COUNT, val)
-#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read32(DMA0_CURR_Y_COUNT)
-#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write32(DMA0_CURR_Y_COUNT, val)
-#define bfin_read_DMA0_BWL_COUNT() bfin_read32(DMA0_BWL_COUNT)
-#define bfin_write_DMA0_BWL_COUNT(val) bfin_write32(DMA0_BWL_COUNT, val)
-#define bfin_read_DMA0_CURR_BWL_COUNT() bfin_read32(DMA0_CURR_BWL_COUNT)
-#define bfin_write_DMA0_CURR_BWL_COUNT(val) bfin_write32(DMA0_CURR_BWL_COUNT, val)
-#define bfin_read_DMA0_BWM_COUNT() bfin_read32(DMA0_BWM_COUNT)
-#define bfin_write_DMA0_BWM_COUNT(val) bfin_write32(DMA0_BWM_COUNT, val)
-#define bfin_read_DMA0_CURR_BWM_COUNT() bfin_read32(DMA0_CURR_BWM_COUNT)
-#define bfin_write_DMA0_CURR_BWM_COUNT(val) bfin_write32(DMA0_CURR_BWM_COUNT, val)
-
-/* DMA Channel 1 Registers */
-
-#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val)
-#define bfin_read_DMA1_CONFIG() bfin_read32(DMA1_CONFIG)
-#define bfin_write_DMA1_CONFIG(val) bfin_write32(DMA1_CONFIG, val)
-#define bfin_read_DMA1_X_COUNT() bfin_read32(DMA1_X_COUNT)
-#define bfin_write_DMA1_X_COUNT(val) bfin_write32(DMA1_X_COUNT, val)
-#define bfin_read_DMA1_X_MODIFY() bfin_read32(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val) bfin_write32(DMA1_X_MODIFY, val)
-#define bfin_read_DMA1_Y_COUNT() bfin_read32(DMA1_Y_COUNT)
-#define bfin_write_DMA1_Y_COUNT(val) bfin_write32(DMA1_Y_COUNT, val)
-#define bfin_read_DMA1_Y_MODIFY() bfin_read32(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val) bfin_write32(DMA1_Y_MODIFY, val)
-#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_PREV_DESC_PTR() bfin_read32(DMA1_PREV_DESC_PTR)
-#define bfin_write_DMA1_PREV_DESC_PTR(val) bfin_write32(DMA1_PREV_DESC_PTR, val)
-#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val)
-#define bfin_read_DMA1_IRQ_STATUS() bfin_read32(DMA1_IRQ_STATUS)
-#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write32(DMA1_IRQ_STATUS, val)
-#define bfin_read_DMA1_CURR_X_COUNT() bfin_read32(DMA1_CURR_X_COUNT)
-#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write32(DMA1_CURR_X_COUNT, val)
-#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read32(DMA1_CURR_Y_COUNT)
-#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write32(DMA1_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_BWL_COUNT() bfin_read32(DMA1_BWL_COUNT)
-#define bfin_write_DMA1_BWL_COUNT(val) bfin_write32(DMA1_BWL_COUNT, val)
-#define bfin_read_DMA1_CURR_BWL_COUNT() bfin_read32(DMA1_CURR_BWL_COUNT)
-#define bfin_write_DMA1_CURR_BWL_COUNT(val) bfin_write32(DMA1_CURR_BWL_COUNT, val)
-#define bfin_read_DMA1_BWM_COUNT() bfin_read32(DMA1_BWM_COUNT)
-#define bfin_write_DMA1_BWM_COUNT(val) bfin_write32(DMA1_BWM_COUNT, val)
-#define bfin_read_DMA1_CURR_BWM_COUNT() bfin_read32(DMA1_CURR_BWM_COUNT)
-#define bfin_write_DMA1_CURR_BWM_COUNT(val) bfin_write32(DMA1_CURR_BWM_COUNT, val)
-
-/* DMA Channel 2 Registers */
-
-#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val)
-#define bfin_read_DMA2_CONFIG() bfin_read32(DMA2_CONFIG)
-#define bfin_write_DMA2_CONFIG(val) bfin_write32(DMA2_CONFIG, val)
-#define bfin_read_DMA2_X_COUNT() bfin_read32(DMA2_X_COUNT)
-#define bfin_write_DMA2_X_COUNT(val) bfin_write32(DMA2_X_COUNT, val)
-#define bfin_read_DMA2_X_MODIFY() bfin_read32(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val) bfin_write32(DMA2_X_MODIFY, val)
-#define bfin_read_DMA2_Y_COUNT() bfin_read32(DMA2_Y_COUNT)
-#define bfin_write_DMA2_Y_COUNT(val) bfin_write32(DMA2_Y_COUNT, val)
-#define bfin_read_DMA2_Y_MODIFY() bfin_read32(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val) bfin_write32(DMA2_Y_MODIFY, val)
-#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_PREV_DESC_PTR() bfin_read32(DMA2_PREV_DESC_PTR)
-#define bfin_write_DMA2_PREV_DESC_PTR(val) bfin_write32(DMA2_PREV_DESC_PTR, val)
-#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val)
-#define bfin_read_DMA2_IRQ_STATUS() bfin_read32(DMA2_IRQ_STATUS)
-#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write32(DMA2_IRQ_STATUS, val)
-#define bfin_read_DMA2_CURR_X_COUNT() bfin_read32(DMA2_CURR_X_COUNT)
-#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write32(DMA2_CURR_X_COUNT, val)
-#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read32(DMA2_CURR_Y_COUNT)
-#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write32(DMA2_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_BWL_COUNT() bfin_read32(DMA2_BWL_COUNT)
-#define bfin_write_DMA2_BWL_COUNT(val) bfin_write32(DMA2_BWL_COUNT, val)
-#define bfin_read_DMA2_CURR_BWL_COUNT() bfin_read32(DMA2_CURR_BWL_COUNT)
-#define bfin_write_DMA2_CURR_BWL_COUNT(val) bfin_write32(DMA2_CURR_BWL_COUNT, val)
-#define bfin_read_DMA2_BWM_COUNT() bfin_read32(DMA2_BWM_COUNT)
-#define bfin_write_DMA2_BWM_COUNT(val) bfin_write32(DMA2_BWM_COUNT, val)
-#define bfin_read_DMA2_CURR_BWM_COUNT() bfin_read32(DMA2_CURR_BWM_COUNT)
-#define bfin_write_DMA2_CURR_BWM_COUNT(val) bfin_write32(DMA2_CURR_BWM_COUNT, val)
-
-/* DMA Channel 3 Registers */
-
-#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val)
-#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val)
-#define bfin_read_DMA3_CONFIG() bfin_read32(DMA3_CONFIG)
-#define bfin_write_DMA3_CONFIG(val) bfin_write32(DMA3_CONFIG, val)
-#define bfin_read_DMA3_X_COUNT() bfin_read32(DMA3_X_COUNT)
-#define bfin_write_DMA3_X_COUNT(val) bfin_write32(DMA3_X_COUNT, val)
-#define bfin_read_DMA3_X_MODIFY() bfin_read32(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val) bfin_write32(DMA3_X_MODIFY, val)
-#define bfin_read_DMA3_Y_COUNT() bfin_read32(DMA3_Y_COUNT)
-#define bfin_write_DMA3_Y_COUNT(val) bfin_write32(DMA3_Y_COUNT, val)
-#define bfin_read_DMA3_Y_MODIFY() bfin_read32(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val) bfin_write32(DMA3_Y_MODIFY, val)
-#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val)
-#define bfin_read_DMA3_PREV_DESC_PTR() bfin_read32(DMA3_PREV_DESC_PTR)
-#define bfin_write_DMA3_PREV_DESC_PTR(val) bfin_write32(DMA3_PREV_DESC_PTR, val)
-#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val)
-#define bfin_read_DMA3_IRQ_STATUS() bfin_read32(DMA3_IRQ_STATUS)
-#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write32(DMA3_IRQ_STATUS, val)
-#define bfin_read_DMA3_CURR_X_COUNT() bfin_read32(DMA3_CURR_X_COUNT)
-#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write32(DMA3_CURR_X_COUNT, val)
-#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read32(DMA3_CURR_Y_COUNT)
-#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write32(DMA3_CURR_Y_COUNT, val)
-#define bfin_read_DMA3_BWL_COUNT() bfin_read32(DMA3_BWL_COUNT)
-#define bfin_write_DMA3_BWL_COUNT(val) bfin_write32(DMA3_BWL_COUNT, val)
-#define bfin_read_DMA3_CURR_BWL_COUNT() bfin_read32(DMA3_CURR_BWL_COUNT)
-#define bfin_write_DMA3_CURR_BWL_COUNT(val) bfin_write32(DMA3_CURR_BWL_COUNT, val)
-#define bfin_read_DMA3_BWM_COUNT() bfin_read32(DMA3_BWM_COUNT)
-#define bfin_write_DMA3_BWM_COUNT(val) bfin_write32(DMA3_BWM_COUNT, val)
-#define bfin_read_DMA3_CURR_BWM_COUNT() bfin_read32(DMA3_CURR_BWM_COUNT)
-#define bfin_write_DMA3_CURR_BWM_COUNT(val) bfin_write32(DMA3_CURR_BWM_COUNT, val)
-
-/* DMA Channel 4 Registers */
-
-#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val)
-#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val)
-#define bfin_read_DMA4_CONFIG() bfin_read32(DMA4_CONFIG)
-#define bfin_write_DMA4_CONFIG(val) bfin_write32(DMA4_CONFIG, val)
-#define bfin_read_DMA4_X_COUNT() bfin_read32(DMA4_X_COUNT)
-#define bfin_write_DMA4_X_COUNT(val) bfin_write32(DMA4_X_COUNT, val)
-#define bfin_read_DMA4_X_MODIFY() bfin_read32(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val) bfin_write32(DMA4_X_MODIFY, val)
-#define bfin_read_DMA4_Y_COUNT() bfin_read32(DMA4_Y_COUNT)
-#define bfin_write_DMA4_Y_COUNT(val) bfin_write32(DMA4_Y_COUNT, val)
-#define bfin_read_DMA4_Y_MODIFY() bfin_read32(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val) bfin_write32(DMA4_Y_MODIFY, val)
-#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val)
-#define bfin_read_DMA4_PREV_DESC_PTR() bfin_read32(DMA4_PREV_DESC_PTR)
-#define bfin_write_DMA4_PREV_DESC_PTR(val) bfin_write32(DMA4_PREV_DESC_PTR, val)
-#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val)
-#define bfin_read_DMA4_IRQ_STATUS() bfin_read32(DMA4_IRQ_STATUS)
-#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write32(DMA4_IRQ_STATUS, val)
-#define bfin_read_DMA4_CURR_X_COUNT() bfin_read32(DMA4_CURR_X_COUNT)
-#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write32(DMA4_CURR_X_COUNT, val)
-#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read32(DMA4_CURR_Y_COUNT)
-#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write32(DMA4_CURR_Y_COUNT, val)
-#define bfin_read_DMA4_BWL_COUNT() bfin_read32(DMA4_BWL_COUNT)
-#define bfin_write_DMA4_BWL_COUNT(val) bfin_write32(DMA4_BWL_COUNT, val)
-#define bfin_read_DMA4_CURR_BWL_COUNT() bfin_read32(DMA4_CURR_BWL_COUNT)
-#define bfin_write_DMA4_CURR_BWL_COUNT(val) bfin_write32(DMA4_CURR_BWL_COUNT, val)
-#define bfin_read_DMA4_BWM_COUNT() bfin_read32(DMA4_BWM_COUNT)
-#define bfin_write_DMA4_BWM_COUNT(val) bfin_write32(DMA4_BWM_COUNT, val)
-#define bfin_read_DMA4_CURR_BWM_COUNT() bfin_read32(DMA4_CURR_BWM_COUNT)
-#define bfin_write_DMA4_CURR_BWM_COUNT(val) bfin_write32(DMA4_CURR_BWM_COUNT, val)
-
-/* DMA Channel 5 Registers */
-
-#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val)
-#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val)
-#define bfin_read_DMA5_CONFIG() bfin_read32(DMA5_CONFIG)
-#define bfin_write_DMA5_CONFIG(val) bfin_write32(DMA5_CONFIG, val)
-#define bfin_read_DMA5_X_COUNT() bfin_read32(DMA5_X_COUNT)
-#define bfin_write_DMA5_X_COUNT(val) bfin_write32(DMA5_X_COUNT, val)
-#define bfin_read_DMA5_X_MODIFY() bfin_read32(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val) bfin_write32(DMA5_X_MODIFY, val)
-#define bfin_read_DMA5_Y_COUNT() bfin_read32(DMA5_Y_COUNT)
-#define bfin_write_DMA5_Y_COUNT(val) bfin_write32(DMA5_Y_COUNT, val)
-#define bfin_read_DMA5_Y_MODIFY() bfin_read32(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val) bfin_write32(DMA5_Y_MODIFY, val)
-#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val)
-#define bfin_read_DMA5_PREV_DESC_PTR() bfin_read32(DMA5_PREV_DESC_PTR)
-#define bfin_write_DMA5_PREV_DESC_PTR(val) bfin_write32(DMA5_PREV_DESC_PTR, val)
-#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val)
-#define bfin_read_DMA5_IRQ_STATUS() bfin_read32(DMA5_IRQ_STATUS)
-#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write32(DMA5_IRQ_STATUS, val)
-#define bfin_read_DMA5_CURR_X_COUNT() bfin_read32(DMA5_CURR_X_COUNT)
-#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write32(DMA5_CURR_X_COUNT, val)
-#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read32(DMA5_CURR_Y_COUNT)
-#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write32(DMA5_CURR_Y_COUNT, val)
-#define bfin_read_DMA5_BWL_COUNT() bfin_read32(DMA5_BWL_COUNT)
-#define bfin_write_DMA5_BWL_COUNT(val) bfin_write32(DMA5_BWL_COUNT, val)
-#define bfin_read_DMA5_CURR_BWL_COUNT() bfin_read32(DMA5_CURR_BWL_COUNT)
-#define bfin_write_DMA5_CURR_BWL_COUNT(val) bfin_write32(DMA5_CURR_BWL_COUNT, val)
-#define bfin_read_DMA5_BWM_COUNT() bfin_read32(DMA5_BWM_COUNT)
-#define bfin_write_DMA5_BWM_COUNT(val) bfin_write32(DMA5_BWM_COUNT, val)
-#define bfin_read_DMA5_CURR_BWM_COUNT() bfin_read32(DMA5_CURR_BWM_COUNT)
-#define bfin_write_DMA5_CURR_BWM_COUNT(val) bfin_write32(DMA5_CURR_BWM_COUNT, val)
-
-/* DMA Channel 6 Registers */
-
-#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
-#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val)
-#define bfin_read_DMA6_CONFIG() bfin_read32(DMA6_CONFIG)
-#define bfin_write_DMA6_CONFIG(val) bfin_write32(DMA6_CONFIG, val)
-#define bfin_read_DMA6_X_COUNT() bfin_read32(DMA6_X_COUNT)
-#define bfin_write_DMA6_X_COUNT(val) bfin_write32(DMA6_X_COUNT, val)
-#define bfin_read_DMA6_X_MODIFY() bfin_read32(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val) bfin_write32(DMA6_X_MODIFY, val)
-#define bfin_read_DMA6_Y_COUNT() bfin_read32(DMA6_Y_COUNT)
-#define bfin_write_DMA6_Y_COUNT(val) bfin_write32(DMA6_Y_COUNT, val)
-#define bfin_read_DMA6_Y_MODIFY() bfin_read32(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val) bfin_write32(DMA6_Y_MODIFY, val)
-#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val)
-#define bfin_read_DMA6_PREV_DESC_PTR() bfin_read32(DMA6_PREV_DESC_PTR)
-#define bfin_write_DMA6_PREV_DESC_PTR(val) bfin_write32(DMA6_PREV_DESC_PTR, val)
-#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val)
-#define bfin_read_DMA6_IRQ_STATUS() bfin_read32(DMA6_IRQ_STATUS)
-#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write32(DMA6_IRQ_STATUS, val)
-#define bfin_read_DMA6_CURR_X_COUNT() bfin_read32(DMA6_CURR_X_COUNT)
-#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write32(DMA6_CURR_X_COUNT, val)
-#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read32(DMA6_CURR_Y_COUNT)
-#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write32(DMA6_CURR_Y_COUNT, val)
-#define bfin_read_DMA6_BWL_COUNT() bfin_read32(DMA6_BWL_COUNT)
-#define bfin_write_DMA6_BWL_COUNT(val) bfin_write32(DMA6_BWL_COUNT, val)
-#define bfin_read_DMA6_CURR_BWL_COUNT() bfin_read32(DMA6_CURR_BWL_COUNT)
-#define bfin_write_DMA6_CURR_BWL_COUNT(val) bfin_write32(DMA6_CURR_BWL_COUNT, val)
-#define bfin_read_DMA6_BWM_COUNT() bfin_read32(DMA6_BWM_COUNT)
-#define bfin_write_DMA6_BWM_COUNT(val) bfin_write32(DMA6_BWM_COUNT, val)
-#define bfin_read_DMA6_CURR_BWM_COUNT() bfin_read32(DMA6_CURR_BWM_COUNT)
-#define bfin_write_DMA6_CURR_BWM_COUNT(val) bfin_write32(DMA6_CURR_BWM_COUNT, val)
-
-/* DMA Channel 7 Registers */
-
-#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val)
-#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val)
-#define bfin_read_DMA7_CONFIG() bfin_read32(DMA7_CONFIG)
-#define bfin_write_DMA7_CONFIG(val) bfin_write32(DMA7_CONFIG, val)
-#define bfin_read_DMA7_X_COUNT() bfin_read32(DMA7_X_COUNT)
-#define bfin_write_DMA7_X_COUNT(val) bfin_write32(DMA7_X_COUNT, val)
-#define bfin_read_DMA7_X_MODIFY() bfin_read32(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val) bfin_write32(DMA7_X_MODIFY, val)
-#define bfin_read_DMA7_Y_COUNT() bfin_read32(DMA7_Y_COUNT)
-#define bfin_write_DMA7_Y_COUNT(val) bfin_write32(DMA7_Y_COUNT, val)
-#define bfin_read_DMA7_Y_MODIFY() bfin_read32(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val) bfin_write32(DMA7_Y_MODIFY, val)
-#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val)
-#define bfin_read_DMA7_PREV_DESC_PTR() bfin_read32(DMA7_PREV_DESC_PTR)
-#define bfin_write_DMA7_PREV_DESC_PTR(val) bfin_write32(DMA7_PREV_DESC_PTR, val)
-#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val)
-#define bfin_read_DMA7_IRQ_STATUS() bfin_read32(DMA7_IRQ_STATUS)
-#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write32(DMA7_IRQ_STATUS, val)
-#define bfin_read_DMA7_CURR_X_COUNT() bfin_read32(DMA7_CURR_X_COUNT)
-#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write32(DMA7_CURR_X_COUNT, val)
-#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read32(DMA7_CURR_Y_COUNT)
-#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write32(DMA7_CURR_Y_COUNT, val)
-#define bfin_read_DMA7_BWL_COUNT() bfin_read32(DMA7_BWL_COUNT)
-#define bfin_write_DMA7_BWL_COUNT(val) bfin_write32(DMA7_BWL_COUNT, val)
-#define bfin_read_DMA7_CURR_BWL_COUNT() bfin_read32(DMA7_CURR_BWL_COUNT)
-#define bfin_write_DMA7_CURR_BWL_COUNT(val) bfin_write32(DMA7_CURR_BWL_COUNT, val)
-#define bfin_read_DMA7_BWM_COUNT() bfin_read32(DMA7_BWM_COUNT)
-#define bfin_write_DMA7_BWM_COUNT(val) bfin_write32(DMA7_BWM_COUNT, val)
-#define bfin_read_DMA7_CURR_BWM_COUNT() bfin_read32(DMA7_CURR_BWM_COUNT)
-#define bfin_write_DMA7_CURR_BWM_COUNT(val) bfin_write32(DMA7_CURR_BWM_COUNT, val)
-
-/* DMA Channel 8 Registers */
-
-#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR)
-#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR, val)
-#define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR)
-#define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR, val)
-#define bfin_read_DMA8_CONFIG() bfin_read32(DMA8_CONFIG)
-#define bfin_write_DMA8_CONFIG(val) bfin_write32(DMA8_CONFIG, val)
-#define bfin_read_DMA8_X_COUNT() bfin_read32(DMA8_X_COUNT)
-#define bfin_write_DMA8_X_COUNT(val) bfin_write32(DMA8_X_COUNT, val)
-#define bfin_read_DMA8_X_MODIFY() bfin_read32(DMA8_X_MODIFY)
-#define bfin_write_DMA8_X_MODIFY(val) bfin_write32(DMA8_X_MODIFY, val)
-#define bfin_read_DMA8_Y_COUNT() bfin_read32(DMA8_Y_COUNT)
-#define bfin_write_DMA8_Y_COUNT(val) bfin_write32(DMA8_Y_COUNT, val)
-#define bfin_read_DMA8_Y_MODIFY() bfin_read32(DMA8_Y_MODIFY)
-#define bfin_write_DMA8_Y_MODIFY(val) bfin_write32(DMA8_Y_MODIFY, val)
-#define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR)
-#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR, val)
-#define bfin_read_DMA8_PREV_DESC_PTR() bfin_read32(DMA8_PREV_DESC_PTR)
-#define bfin_write_DMA8_PREV_DESC_PTR(val) bfin_write32(DMA8_PREV_DESC_PTR, val)
-#define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR)
-#define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR, val)
-#define bfin_read_DMA8_IRQ_STATUS() bfin_read32(DMA8_IRQ_STATUS)
-#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write32(DMA8_IRQ_STATUS, val)
-#define bfin_read_DMA8_CURR_X_COUNT() bfin_read32(DMA8_CURR_X_COUNT)
-#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write32(DMA8_CURR_X_COUNT, val)
-#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read32(DMA8_CURR_Y_COUNT)
-#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write32(DMA8_CURR_Y_COUNT, val)
-#define bfin_read_DMA8_BWL_COUNT() bfin_read32(DMA8_BWL_COUNT)
-#define bfin_write_DMA8_BWL_COUNT(val) bfin_write32(DMA8_BWL_COUNT, val)
-#define bfin_read_DMA8_CURR_BWL_COUNT() bfin_read32(DMA8_CURR_BWL_COUNT)
-#define bfin_write_DMA8_CURR_BWL_COUNT(val) bfin_write32(DMA8_CURR_BWL_COUNT, val)
-#define bfin_read_DMA8_BWM_COUNT() bfin_read32(DMA8_BWM_COUNT)
-#define bfin_write_DMA8_BWM_COUNT(val) bfin_write32(DMA8_BWM_COUNT, val)
-#define bfin_read_DMA8_CURR_BWM_COUNT() bfin_read32(DMA8_CURR_BWM_COUNT)
-#define bfin_write_DMA8_CURR_BWM_COUNT(val) bfin_write32(DMA8_CURR_BWM_COUNT, val)
-
-/* DMA Channel 9 Registers */
-
-#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR)
-#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR, val)
-#define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR)
-#define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR, val)
-#define bfin_read_DMA9_CONFIG() bfin_read32(DMA9_CONFIG)
-#define bfin_write_DMA9_CONFIG(val) bfin_write32(DMA9_CONFIG, val)
-#define bfin_read_DMA9_X_COUNT() bfin_read32(DMA9_X_COUNT)
-#define bfin_write_DMA9_X_COUNT(val) bfin_write32(DMA9_X_COUNT, val)
-#define bfin_read_DMA9_X_MODIFY() bfin_read32(DMA9_X_MODIFY)
-#define bfin_write_DMA9_X_MODIFY(val) bfin_write32(DMA9_X_MODIFY, val)
-#define bfin_read_DMA9_Y_COUNT() bfin_read32(DMA9_Y_COUNT)
-#define bfin_write_DMA9_Y_COUNT(val) bfin_write32(DMA9_Y_COUNT, val)
-#define bfin_read_DMA9_Y_MODIFY() bfin_read32(DMA9_Y_MODIFY)
-#define bfin_write_DMA9_Y_MODIFY(val) bfin_write32(DMA9_Y_MODIFY, val)
-#define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR)
-#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR, val)
-#define bfin_read_DMA9_PREV_DESC_PTR() bfin_read32(DMA9_PREV_DESC_PTR)
-#define bfin_write_DMA9_PREV_DESC_PTR(val) bfin_write32(DMA9_PREV_DESC_PTR, val)
-#define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR)
-#define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR, val)
-#define bfin_read_DMA9_IRQ_STATUS() bfin_read32(DMA9_IRQ_STATUS)
-#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write32(DMA9_IRQ_STATUS, val)
-#define bfin_read_DMA9_CURR_X_COUNT() bfin_read32(DMA9_CURR_X_COUNT)
-#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write32(DMA9_CURR_X_COUNT, val)
-#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read32(DMA9_CURR_Y_COUNT)
-#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write32(DMA9_CURR_Y_COUNT, val)
-#define bfin_read_DMA9_BWL_COUNT() bfin_read32(DMA9_BWL_COUNT)
-#define bfin_write_DMA9_BWL_COUNT(val) bfin_write32(DMA9_BWL_COUNT, val)
-#define bfin_read_DMA9_CURR_BWL_COUNT() bfin_read32(DMA9_CURR_BWL_COUNT)
-#define bfin_write_DMA9_CURR_BWL_COUNT(val) bfin_write32(DMA9_CURR_BWL_COUNT, val)
-#define bfin_read_DMA9_BWM_COUNT() bfin_read32(DMA9_BWM_COUNT)
-#define bfin_write_DMA9_BWM_COUNT(val) bfin_write32(DMA9_BWM_COUNT, val)
-#define bfin_read_DMA9_CURR_BWM_COUNT() bfin_read32(DMA9_CURR_BWM_COUNT)
-#define bfin_write_DMA9_CURR_BWM_COUNT(val) bfin_write32(DMA9_CURR_BWM_COUNT, val)
-
-/* DMA Channel 10 Registers */
-
-#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR)
-#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR, val)
-#define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR)
-#define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR, val)
-#define bfin_read_DMA10_CONFIG() bfin_read32(DMA10_CONFIG)
-#define bfin_write_DMA10_CONFIG(val) bfin_write32(DMA10_CONFIG, val)
-#define bfin_read_DMA10_X_COUNT() bfin_read32(DMA10_X_COUNT)
-#define bfin_write_DMA10_X_COUNT(val) bfin_write32(DMA10_X_COUNT, val)
-#define bfin_read_DMA10_X_MODIFY() bfin_read32(DMA10_X_MODIFY)
-#define bfin_write_DMA10_X_MODIFY(val) bfin_write32(DMA10_X_MODIFY, val)
-#define bfin_read_DMA10_Y_COUNT() bfin_read32(DMA10_Y_COUNT)
-#define bfin_write_DMA10_Y_COUNT(val) bfin_write32(DMA10_Y_COUNT, val)
-#define bfin_read_DMA10_Y_MODIFY() bfin_read32(DMA10_Y_MODIFY)
-#define bfin_write_DMA10_Y_MODIFY(val) bfin_write32(DMA10_Y_MODIFY, val)
-#define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR)
-#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR, val)
-#define bfin_read_DMA10_PREV_DESC_PTR() bfin_read32(DMA10_PREV_DESC_PTR)
-#define bfin_write_DMA10_PREV_DESC_PTR(val) bfin_write32(DMA10_PREV_DESC_PTR, val)
-#define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR)
-#define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR, val)
-#define bfin_read_DMA10_IRQ_STATUS() bfin_read32(DMA10_IRQ_STATUS)
-#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write32(DMA10_IRQ_STATUS, val)
-#define bfin_read_DMA10_CURR_X_COUNT() bfin_read32(DMA10_CURR_X_COUNT)
-#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write32(DMA10_CURR_X_COUNT, val)
-#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read32(DMA10_CURR_Y_COUNT)
-#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write32(DMA10_CURR_Y_COUNT, val)
-#define bfin_read_DMA10_BWL_COUNT() bfin_read32(DMA10_BWL_COUNT)
-#define bfin_write_DMA10_BWL_COUNT(val) bfin_write32(DMA10_BWL_COUNT, val)
-#define bfin_read_DMA10_CURR_BWL_COUNT() bfin_read32(DMA10_CURR_BWL_COUNT)
-#define bfin_write_DMA10_CURR_BWL_COUNT(val) bfin_write32(DMA10_CURR_BWL_COUNT, val)
-#define bfin_read_DMA10_BWM_COUNT() bfin_read32(DMA10_BWM_COUNT)
-#define bfin_write_DMA10_BWM_COUNT(val) bfin_write32(DMA10_BWM_COUNT, val)
-#define bfin_read_DMA10_CURR_BWM_COUNT() bfin_read32(DMA10_CURR_BWM_COUNT)
-#define bfin_write_DMA10_CURR_BWM_COUNT(val) bfin_write32(DMA10_CURR_BWM_COUNT, val)
-
-/* DMA Channel 11 Registers */
-
-#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR)
-#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR, val)
-#define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR)
-#define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR, val)
-#define bfin_read_DMA11_CONFIG() bfin_read32(DMA11_CONFIG)
-#define bfin_write_DMA11_CONFIG(val) bfin_write32(DMA11_CONFIG, val)
-#define bfin_read_DMA11_X_COUNT() bfin_read32(DMA11_X_COUNT)
-#define bfin_write_DMA11_X_COUNT(val) bfin_write32(DMA11_X_COUNT, val)
-#define bfin_read_DMA11_X_MODIFY() bfin_read32(DMA11_X_MODIFY)
-#define bfin_write_DMA11_X_MODIFY(val) bfin_write32(DMA11_X_MODIFY, val)
-#define bfin_read_DMA11_Y_COUNT() bfin_read32(DMA11_Y_COUNT)
-#define bfin_write_DMA11_Y_COUNT(val) bfin_write32(DMA11_Y_COUNT, val)
-#define bfin_read_DMA11_Y_MODIFY() bfin_read32(DMA11_Y_MODIFY)
-#define bfin_write_DMA11_Y_MODIFY(val) bfin_write32(DMA11_Y_MODIFY, val)
-#define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR)
-#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR, val)
-#define bfin_read_DMA11_PREV_DESC_PTR() bfin_read32(DMA11_PREV_DESC_PTR)
-#define bfin_write_DMA11_PREV_DESC_PTR(val) bfin_write32(DMA11_PREV_DESC_PTR, val)
-#define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR)
-#define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR, val)
-#define bfin_read_DMA11_IRQ_STATUS() bfin_read32(DMA11_IRQ_STATUS)
-#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write32(DMA11_IRQ_STATUS, val)
-#define bfin_read_DMA11_CURR_X_COUNT() bfin_read32(DMA11_CURR_X_COUNT)
-#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write32(DMA11_CURR_X_COUNT, val)
-#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read32(DMA11_CURR_Y_COUNT)
-#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write32(DMA11_CURR_Y_COUNT, val)
-#define bfin_read_DMA11_BWL_COUNT() bfin_read32(DMA11_BWL_COUNT)
-#define bfin_write_DMA11_BWL_COUNT(val) bfin_write32(DMA11_BWL_COUNT, val)
-#define bfin_read_DMA11_CURR_BWL_COUNT() bfin_read32(DMA11_CURR_BWL_COUNT)
-#define bfin_write_DMA11_CURR_BWL_COUNT(val) bfin_write32(DMA11_CURR_BWL_COUNT, val)
-#define bfin_read_DMA11_BWM_COUNT() bfin_read32(DMA11_BWM_COUNT)
-#define bfin_write_DMA11_BWM_COUNT(val) bfin_write32(DMA11_BWM_COUNT, val)
-#define bfin_read_DMA11_CURR_BWM_COUNT() bfin_read32(DMA11_CURR_BWM_COUNT)
-#define bfin_write_DMA11_CURR_BWM_COUNT(val) bfin_write32(DMA11_CURR_BWM_COUNT, val)
-
-/* DMA Channel 12 Registers */
-
-#define bfin_read_DMA12_NEXT_DESC_PTR() bfin_read32(DMA12_NEXT_DESC_PTR)
-#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_write32(DMA12_NEXT_DESC_PTR, val)
-#define bfin_read_DMA12_START_ADDR() bfin_read32(DMA12_START_ADDR)
-#define bfin_write_DMA12_START_ADDR(val) bfin_write32(DMA12_START_ADDR, val)
-#define bfin_read_DMA12_CONFIG() bfin_read32(DMA12_CONFIG)
-#define bfin_write_DMA12_CONFIG(val) bfin_write32(DMA12_CONFIG, val)
-#define bfin_read_DMA12_X_COUNT() bfin_read32(DMA12_X_COUNT)
-#define bfin_write_DMA12_X_COUNT(val) bfin_write32(DMA12_X_COUNT, val)
-#define bfin_read_DMA12_X_MODIFY() bfin_read32(DMA12_X_MODIFY)
-#define bfin_write_DMA12_X_MODIFY(val) bfin_write32(DMA12_X_MODIFY, val)
-#define bfin_read_DMA12_Y_COUNT() bfin_read32(DMA12_Y_COUNT)
-#define bfin_write_DMA12_Y_COUNT(val) bfin_write32(DMA12_Y_COUNT, val)
-#define bfin_read_DMA12_Y_MODIFY() bfin_read32(DMA12_Y_MODIFY)
-#define bfin_write_DMA12_Y_MODIFY(val) bfin_write32(DMA12_Y_MODIFY, val)
-#define bfin_read_DMA12_CURR_DESC_PTR() bfin_read32(DMA12_CURR_DESC_PTR)
-#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_write32(DMA12_CURR_DESC_PTR, val)
-#define bfin_read_DMA12_PREV_DESC_PTR() bfin_read32(DMA12_PREV_DESC_PTR)
-#define bfin_write_DMA12_PREV_DESC_PTR(val) bfin_write32(DMA12_PREV_DESC_PTR, val)
-#define bfin_read_DMA12_CURR_ADDR() bfin_read32(DMA12_CURR_ADDR)
-#define bfin_write_DMA12_CURR_ADDR(val) bfin_write32(DMA12_CURR_ADDR, val)
-#define bfin_read_DMA12_IRQ_STATUS() bfin_read32(DMA12_IRQ_STATUS)
-#define bfin_write_DMA12_IRQ_STATUS(val) bfin_write32(DMA12_IRQ_STATUS, val)
-#define bfin_read_DMA12_CURR_X_COUNT() bfin_read32(DMA12_CURR_X_COUNT)
-#define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write32(DMA12_CURR_X_COUNT, val)
-#define bfin_read_DMA12_CURR_Y_COUNT() bfin_read32(DMA12_CURR_Y_COUNT)
-#define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write32(DMA12_CURR_Y_COUNT, val)
-#define bfin_read_DMA12_BWL_COUNT() bfin_read32(DMA12_BWL_COUNT)
-#define bfin_write_DMA12_BWL_COUNT(val) bfin_write32(DMA12_BWL_COUNT, val)
-#define bfin_read_DMA12_CURR_BWL_COUNT() bfin_read32(DMA12_CURR_BWL_COUNT)
-#define bfin_write_DMA12_CURR_BWL_COUNT(val) bfin_write32(DMA12_CURR_BWL_COUNT, val)
-#define bfin_read_DMA12_BWM_COUNT() bfin_read32(DMA12_BWM_COUNT)
-#define bfin_write_DMA12_BWM_COUNT(val) bfin_write32(DMA12_BWM_COUNT, val)
-#define bfin_read_DMA12_CURR_BWM_COUNT() bfin_read32(DMA12_CURR_BWM_COUNT)
-#define bfin_write_DMA12_CURR_BWM_COUNT(val) bfin_write32(DMA12_CURR_BWM_COUNT, val)
-
-/* DMA Channel 13 Registers */
-
-#define bfin_read_DMA13_NEXT_DESC_PTR() bfin_read32(DMA13_NEXT_DESC_PTR)
-#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_write32(DMA13_NEXT_DESC_PTR, val)
-#define bfin_read_DMA13_START_ADDR() bfin_read32(DMA13_START_ADDR)
-#define bfin_write_DMA13_START_ADDR(val) bfin_write32(DMA13_START_ADDR, val)
-#define bfin_read_DMA13_CONFIG() bfin_read32(DMA13_CONFIG)
-#define bfin_write_DMA13_CONFIG(val) bfin_write32(DMA13_CONFIG, val)
-#define bfin_read_DMA13_X_COUNT() bfin_read32(DMA13_X_COUNT)
-#define bfin_write_DMA13_X_COUNT(val) bfin_write32(DMA13_X_COUNT, val)
-#define bfin_read_DMA13_X_MODIFY() bfin_read32(DMA13_X_MODIFY)
-#define bfin_write_DMA13_X_MODIFY(val) bfin_write32(DMA13_X_MODIFY, val)
-#define bfin_read_DMA13_Y_COUNT() bfin_read32(DMA13_Y_COUNT)
-#define bfin_write_DMA13_Y_COUNT(val) bfin_write32(DMA13_Y_COUNT, val)
-#define bfin_read_DMA13_Y_MODIFY() bfin_read32(DMA13_Y_MODIFY)
-#define bfin_write_DMA13_Y_MODIFY(val) bfin_write32(DMA13_Y_MODIFY, val)
-#define bfin_read_DMA13_CURR_DESC_PTR() bfin_read32(DMA13_CURR_DESC_PTR)
-#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_write32(DMA13_CURR_DESC_PTR, val)
-#define bfin_read_DMA13_PREV_DESC_PTR() bfin_read32(DMA13_PREV_DESC_PTR)
-#define bfin_write_DMA13_PREV_DESC_PTR(val) bfin_write32(DMA13_PREV_DESC_PTR, val)
-#define bfin_read_DMA13_CURR_ADDR() bfin_read32(DMA13_CURR_ADDR)
-#define bfin_write_DMA13_CURR_ADDR(val) bfin_write32(DMA13_CURR_ADDR, val)
-#define bfin_read_DMA13_IRQ_STATUS() bfin_read32(DMA13_IRQ_STATUS)
-#define bfin_write_DMA13_IRQ_STATUS(val) bfin_write32(DMA13_IRQ_STATUS, val)
-#define bfin_read_DMA13_CURR_X_COUNT() bfin_read32(DMA13_CURR_X_COUNT)
-#define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write32(DMA13_CURR_X_COUNT, val)
-#define bfin_read_DMA13_CURR_Y_COUNT() bfin_read32(DMA13_CURR_Y_COUNT)
-#define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write32(DMA13_CURR_Y_COUNT, val)
-#define bfin_read_DMA13_BWL_COUNT() bfin_read32(DMA13_BWL_COUNT)
-#define bfin_write_DMA13_BWL_COUNT(val) bfin_write32(DMA13_BWL_COUNT, val)
-#define bfin_read_DMA13_CURR_BWL_COUNT() bfin_read32(DMA13_CURR_BWL_COUNT)
-#define bfin_write_DMA13_CURR_BWL_COUNT(val) bfin_write32(DMA13_CURR_BWL_COUNT, val)
-#define bfin_read_DMA13_BWM_COUNT() bfin_read32(DMA13_BWM_COUNT)
-#define bfin_write_DMA13_BWM_COUNT(val) bfin_write32(DMA13_BWM_COUNT, val)
-#define bfin_read_DMA13_CURR_BWM_COUNT() bfin_read32(DMA13_CURR_BWM_COUNT)
-#define bfin_write_DMA13_CURR_BWM_COUNT(val) bfin_write32(DMA13_CURR_BWM_COUNT, val)
-
-/* DMA Channel 14 Registers */
-
-#define bfin_read_DMA14_NEXT_DESC_PTR() bfin_read32(DMA14_NEXT_DESC_PTR)
-#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_write32(DMA14_NEXT_DESC_PTR, val)
-#define bfin_read_DMA14_START_ADDR() bfin_read32(DMA14_START_ADDR)
-#define bfin_write_DMA14_START_ADDR(val) bfin_write32(DMA14_START_ADDR, val)
-#define bfin_read_DMA14_CONFIG() bfin_read32(DMA14_CONFIG)
-#define bfin_write_DMA14_CONFIG(val) bfin_write32(DMA14_CONFIG, val)
-#define bfin_read_DMA14_X_COUNT() bfin_read32(DMA14_X_COUNT)
-#define bfin_write_DMA14_X_COUNT(val) bfin_write32(DMA14_X_COUNT, val)
-#define bfin_read_DMA14_X_MODIFY() bfin_read32(DMA14_X_MODIFY)
-#define bfin_write_DMA14_X_MODIFY(val) bfin_write32(DMA14_X_MODIFY, val)
-#define bfin_read_DMA14_Y_COUNT() bfin_read32(DMA14_Y_COUNT)
-#define bfin_write_DMA14_Y_COUNT(val) bfin_write32(DMA14_Y_COUNT, val)
-#define bfin_read_DMA14_Y_MODIFY() bfin_read32(DMA14_Y_MODIFY)
-#define bfin_write_DMA14_Y_MODIFY(val) bfin_write32(DMA14_Y_MODIFY, val)
-#define bfin_read_DMA14_CURR_DESC_PTR() bfin_read32(DMA14_CURR_DESC_PTR)
-#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_write32(DMA14_CURR_DESC_PTR, val)
-#define bfin_read_DMA14_PREV_DESC_PTR() bfin_read32(DMA14_PREV_DESC_PTR)
-#define bfin_write_DMA14_PREV_DESC_PTR(val) bfin_write32(DMA14_PREV_DESC_PTR, val)
-#define bfin_read_DMA14_CURR_ADDR() bfin_read32(DMA14_CURR_ADDR)
-#define bfin_write_DMA14_CURR_ADDR(val) bfin_write32(DMA14_CURR_ADDR, val)
-#define bfin_read_DMA14_IRQ_STATUS() bfin_read32(DMA14_IRQ_STATUS)
-#define bfin_write_DMA14_IRQ_STATUS(val) bfin_write32(DMA14_IRQ_STATUS, val)
-#define bfin_read_DMA14_CURR_X_COUNT() bfin_read32(DMA14_CURR_X_COUNT)
-#define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write32(DMA14_CURR_X_COUNT, val)
-#define bfin_read_DMA14_CURR_Y_COUNT() bfin_read32(DMA14_CURR_Y_COUNT)
-#define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write32(DMA14_CURR_Y_COUNT, val)
-#define bfin_read_DMA14_BWL_COUNT() bfin_read32(DMA14_BWL_COUNT)
-#define bfin_write_DMA14_BWL_COUNT(val) bfin_write32(DMA14_BWL_COUNT, val)
-#define bfin_read_DMA14_CURR_BWL_COUNT() bfin_read32(DMA14_CURR_BWL_COUNT)
-#define bfin_write_DMA14_CURR_BWL_COUNT(val) bfin_write32(DMA14_CURR_BWL_COUNT, val)
-#define bfin_read_DMA14_BWM_COUNT() bfin_read32(DMA14_BWM_COUNT)
-#define bfin_write_DMA14_BWM_COUNT(val) bfin_write32(DMA14_BWM_COUNT, val)
-#define bfin_read_DMA14_CURR_BWM_COUNT() bfin_read32(DMA14_CURR_BWM_COUNT)
-#define bfin_write_DMA14_CURR_BWM_COUNT(val) bfin_write32(DMA14_CURR_BWM_COUNT, val)
-
-/* DMA Channel 15 Registers */
-
-#define bfin_read_DMA15_NEXT_DESC_PTR() bfin_read32(DMA15_NEXT_DESC_PTR)
-#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_write32(DMA15_NEXT_DESC_PTR, val)
-#define bfin_read_DMA15_START_ADDR() bfin_read32(DMA15_START_ADDR)
-#define bfin_write_DMA15_START_ADDR(val) bfin_write32(DMA15_START_ADDR, val)
-#define bfin_read_DMA15_CONFIG() bfin_read32(DMA15_CONFIG)
-#define bfin_write_DMA15_CONFIG(val) bfin_write32(DMA15_CONFIG, val)
-#define bfin_read_DMA15_X_COUNT() bfin_read32(DMA15_X_COUNT)
-#define bfin_write_DMA15_X_COUNT(val) bfin_write32(DMA15_X_COUNT, val)
-#define bfin_read_DMA15_X_MODIFY() bfin_read32(DMA15_X_MODIFY)
-#define bfin_write_DMA15_X_MODIFY(val) bfin_write32(DMA15_X_MODIFY, val)
-#define bfin_read_DMA15_Y_COUNT() bfin_read32(DMA15_Y_COUNT)
-#define bfin_write_DMA15_Y_COUNT(val) bfin_write32(DMA15_Y_COUNT, val)
-#define bfin_read_DMA15_Y_MODIFY() bfin_read32(DMA15_Y_MODIFY)
-#define bfin_write_DMA15_Y_MODIFY(val) bfin_write32(DMA15_Y_MODIFY, val)
-#define bfin_read_DMA15_CURR_DESC_PTR() bfin_read32(DMA15_CURR_DESC_PTR)
-#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_write32(DMA15_CURR_DESC_PTR, val)
-#define bfin_read_DMA15_PREV_DESC_PTR() bfin_read32(DMA15_PREV_DESC_PTR)
-#define bfin_write_DMA15_PREV_DESC_PTR(val) bfin_write32(DMA15_PREV_DESC_PTR, val)
-#define bfin_read_DMA15_CURR_ADDR() bfin_read32(DMA15_CURR_ADDR)
-#define bfin_write_DMA15_CURR_ADDR(val) bfin_write32(DMA15_CURR_ADDR, val)
-#define bfin_read_DMA15_IRQ_STATUS() bfin_read32(DMA15_IRQ_STATUS)
-#define bfin_write_DMA15_IRQ_STATUS(val) bfin_write32(DMA15_IRQ_STATUS, val)
-#define bfin_read_DMA15_CURR_X_COUNT() bfin_read32(DMA15_CURR_X_COUNT)
-#define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write32(DMA15_CURR_X_COUNT, val)
-#define bfin_read_DMA15_CURR_Y_COUNT() bfin_read32(DMA15_CURR_Y_COUNT)
-#define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write32(DMA15_CURR_Y_COUNT, val)
-#define bfin_read_DMA15_BWL_COUNT() bfin_read32(DMA15_BWL_COUNT)
-#define bfin_write_DMA15_BWL_COUNT(val) bfin_write32(DMA15_BWL_COUNT, val)
-#define bfin_read_DMA15_CURR_BWL_COUNT() bfin_read32(DMA15_CURR_BWL_COUNT)
-#define bfin_write_DMA15_CURR_BWL_COUNT(val) bfin_write32(DMA15_CURR_BWL_COUNT, val)
-#define bfin_read_DMA15_BWM_COUNT() bfin_read32(DMA15_BWM_COUNT)
-#define bfin_write_DMA15_BWM_COUNT(val) bfin_write32(DMA15_BWM_COUNT, val)
-#define bfin_read_DMA15_CURR_BWM_COUNT() bfin_read32(DMA15_CURR_BWM_COUNT)
-#define bfin_write_DMA15_CURR_BWM_COUNT(val) bfin_write32(DMA15_CURR_BWM_COUNT, val)
-
-/* DMA Channel 16 Registers */
-
-#define bfin_read_DMA16_NEXT_DESC_PTR() bfin_read32(DMA16_NEXT_DESC_PTR)
-#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_write32(DMA16_NEXT_DESC_PTR, val)
-#define bfin_read_DMA16_START_ADDR() bfin_read32(DMA16_START_ADDR)
-#define bfin_write_DMA16_START_ADDR(val) bfin_write32(DMA16_START_ADDR, val)
-#define bfin_read_DMA16_CONFIG() bfin_read32(DMA16_CONFIG)
-#define bfin_write_DMA16_CONFIG(val) bfin_write32(DMA16_CONFIG, val)
-#define bfin_read_DMA16_X_COUNT() bfin_read32(DMA16_X_COUNT)
-#define bfin_write_DMA16_X_COUNT(val) bfin_write32(DMA16_X_COUNT, val)
-#define bfin_read_DMA16_X_MODIFY() bfin_read32(DMA16_X_MODIFY)
-#define bfin_write_DMA16_X_MODIFY(val) bfin_write32(DMA16_X_MODIFY, val)
-#define bfin_read_DMA16_Y_COUNT() bfin_read32(DMA16_Y_COUNT)
-#define bfin_write_DMA16_Y_COUNT(val) bfin_write32(DMA16_Y_COUNT, val)
-#define bfin_read_DMA16_Y_MODIFY() bfin_read32(DMA16_Y_MODIFY)
-#define bfin_write_DMA16_Y_MODIFY(val) bfin_write32(DMA16_Y_MODIFY, val)
-#define bfin_read_DMA16_CURR_DESC_PTR() bfin_read32(DMA16_CURR_DESC_PTR)
-#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_write32(DMA16_CURR_DESC_PTR, val)
-#define bfin_read_DMA16_PREV_DESC_PTR() bfin_read32(DMA16_PREV_DESC_PTR)
-#define bfin_write_DMA16_PREV_DESC_PTR(val) bfin_write32(DMA16_PREV_DESC_PTR, val)
-#define bfin_read_DMA16_CURR_ADDR() bfin_read32(DMA16_CURR_ADDR)
-#define bfin_write_DMA16_CURR_ADDR(val) bfin_write32(DMA16_CURR_ADDR, val)
-#define bfin_read_DMA16_IRQ_STATUS() bfin_read32(DMA16_IRQ_STATUS)
-#define bfin_write_DMA16_IRQ_STATUS(val) bfin_write32(DMA16_IRQ_STATUS, val)
-#define bfin_read_DMA16_CURR_X_COUNT() bfin_read32(DMA16_CURR_X_COUNT)
-#define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write32(DMA16_CURR_X_COUNT, val)
-#define bfin_read_DMA16_CURR_Y_COUNT() bfin_read32(DMA16_CURR_Y_COUNT)
-#define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write32(DMA16_CURR_Y_COUNT, val)
-#define bfin_read_DMA16_BWL_COUNT() bfin_read32(DMA16_BWL_COUNT)
-#define bfin_write_DMA16_BWL_COUNT(val) bfin_write32(DMA16_BWL_COUNT, val)
-#define bfin_read_DMA16_CURR_BWL_COUNT() bfin_read32(DMA16_CURR_BWL_COUNT)
-#define bfin_write_DMA16_CURR_BWL_COUNT(val) bfin_write32(DMA16_CURR_BWL_COUNT, val)
-#define bfin_read_DMA16_BWM_COUNT() bfin_read32(DMA16_BWM_COUNT)
-#define bfin_write_DMA16_BWM_COUNT(val) bfin_write32(DMA16_BWM_COUNT, val)
-#define bfin_read_DMA16_CURR_BWM_COUNT() bfin_read32(DMA16_CURR_BWM_COUNT)
-#define bfin_write_DMA16_CURR_BWM_COUNT(val) bfin_write32(DMA16_CURR_BWM_COUNT, val)
-
-/* DMA Channel 17 Registers */
-
-#define bfin_read_DMA17_NEXT_DESC_PTR() bfin_read32(DMA17_NEXT_DESC_PTR)
-#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_write32(DMA17_NEXT_DESC_PTR, val)
-#define bfin_read_DMA17_START_ADDR() bfin_read32(DMA17_START_ADDR)
-#define bfin_write_DMA17_START_ADDR(val) bfin_write32(DMA17_START_ADDR, val)
-#define bfin_read_DMA17_CONFIG() bfin_read32(DMA17_CONFIG)
-#define bfin_write_DMA17_CONFIG(val) bfin_write32(DMA17_CONFIG, val)
-#define bfin_read_DMA17_X_COUNT() bfin_read32(DMA17_X_COUNT)
-#define bfin_write_DMA17_X_COUNT(val) bfin_write32(DMA17_X_COUNT, val)
-#define bfin_read_DMA17_X_MODIFY() bfin_read32(DMA17_X_MODIFY)
-#define bfin_write_DMA17_X_MODIFY(val) bfin_write32(DMA17_X_MODIFY, val)
-#define bfin_read_DMA17_Y_COUNT() bfin_read32(DMA17_Y_COUNT)
-#define bfin_write_DMA17_Y_COUNT(val) bfin_write32(DMA17_Y_COUNT, val)
-#define bfin_read_DMA17_Y_MODIFY() bfin_read32(DMA17_Y_MODIFY)
-#define bfin_write_DMA17_Y_MODIFY(val) bfin_write32(DMA17_Y_MODIFY, val)
-#define bfin_read_DMA17_CURR_DESC_PTR() bfin_read32(DMA17_CURR_DESC_PTR)
-#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_write32(DMA17_CURR_DESC_PTR, val)
-#define bfin_read_DMA17_PREV_DESC_PTR() bfin_read32(DMA17_PREV_DESC_PTR)
-#define bfin_write_DMA17_PREV_DESC_PTR(val) bfin_write32(DMA17_PREV_DESC_PTR, val)
-#define bfin_read_DMA17_CURR_ADDR() bfin_read32(DMA17_CURR_ADDR)
-#define bfin_write_DMA17_CURR_ADDR(val) bfin_write32(DMA17_CURR_ADDR, val)
-#define bfin_read_DMA17_IRQ_STATUS() bfin_read32(DMA17_IRQ_STATUS)
-#define bfin_write_DMA17_IRQ_STATUS(val) bfin_write32(DMA17_IRQ_STATUS, val)
-#define bfin_read_DMA17_CURR_X_COUNT() bfin_read32(DMA17_CURR_X_COUNT)
-#define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write32(DMA17_CURR_X_COUNT, val)
-#define bfin_read_DMA17_CURR_Y_COUNT() bfin_read32(DMA17_CURR_Y_COUNT)
-#define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write32(DMA17_CURR_Y_COUNT, val)
-#define bfin_read_DMA17_BWL_COUNT() bfin_read32(DMA17_BWL_COUNT)
-#define bfin_write_DMA17_BWL_COUNT(val) bfin_write32(DMA17_BWL_COUNT, val)
-#define bfin_read_DMA17_CURR_BWL_COUNT() bfin_read32(DMA17_CURR_BWL_COUNT)
-#define bfin_write_DMA17_CURR_BWL_COUNT(val) bfin_write32(DMA17_CURR_BWL_COUNT, val)
-#define bfin_read_DMA17_BWM_COUNT() bfin_read32(DMA17_BWM_COUNT)
-#define bfin_write_DMA17_BWM_COUNT(val) bfin_write32(DMA17_BWM_COUNT, val)
-#define bfin_read_DMA17_CURR_BWM_COUNT() bfin_read32(DMA17_CURR_BWM_COUNT)
-#define bfin_write_DMA17_CURR_BWM_COUNT(val) bfin_write32(DMA17_CURR_BWM_COUNT, val)
-
-/* DMA Channel 18 Registers */
-
-#define bfin_read_DMA18_NEXT_DESC_PTR() bfin_read32(DMA18_NEXT_DESC_PTR)
-#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_write32(DMA18_NEXT_DESC_PTR, val)
-#define bfin_read_DMA18_START_ADDR() bfin_read32(DMA18_START_ADDR)
-#define bfin_write_DMA18_START_ADDR(val) bfin_write32(DMA18_START_ADDR, val)
-#define bfin_read_DMA18_CONFIG() bfin_read32(DMA18_CONFIG)
-#define bfin_write_DMA18_CONFIG(val) bfin_write32(DMA18_CONFIG, val)
-#define bfin_read_DMA18_X_COUNT() bfin_read32(DMA18_X_COUNT)
-#define bfin_write_DMA18_X_COUNT(val) bfin_write32(DMA18_X_COUNT, val)
-#define bfin_read_DMA18_X_MODIFY() bfin_read32(DMA18_X_MODIFY)
-#define bfin_write_DMA18_X_MODIFY(val) bfin_write32(DMA18_X_MODIFY, val)
-#define bfin_read_DMA18_Y_COUNT() bfin_read32(DMA18_Y_COUNT)
-#define bfin_write_DMA18_Y_COUNT(val) bfin_write32(DMA18_Y_COUNT, val)
-#define bfin_read_DMA18_Y_MODIFY() bfin_read32(DMA18_Y_MODIFY)
-#define bfin_write_DMA18_Y_MODIFY(val) bfin_write32(DMA18_Y_MODIFY, val)
-#define bfin_read_DMA18_CURR_DESC_PTR() bfin_read32(DMA18_CURR_DESC_PTR)
-#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_write32(DMA18_CURR_DESC_PTR, val)
-#define bfin_read_DMA18_PREV_DESC_PTR() bfin_read32(DMA18_PREV_DESC_PTR)
-#define bfin_write_DMA18_PREV_DESC_PTR(val) bfin_write32(DMA18_PREV_DESC_PTR, val)
-#define bfin_read_DMA18_CURR_ADDR() bfin_read32(DMA18_CURR_ADDR)
-#define bfin_write_DMA18_CURR_ADDR(val) bfin_write32(DMA18_CURR_ADDR, val)
-#define bfin_read_DMA18_IRQ_STATUS() bfin_read32(DMA18_IRQ_STATUS)
-#define bfin_write_DMA18_IRQ_STATUS(val) bfin_write32(DMA18_IRQ_STATUS, val)
-#define bfin_read_DMA18_CURR_X_COUNT() bfin_read32(DMA18_CURR_X_COUNT)
-#define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write32(DMA18_CURR_X_COUNT, val)
-#define bfin_read_DMA18_CURR_Y_COUNT() bfin_read32(DMA18_CURR_Y_COUNT)
-#define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write32(DMA18_CURR_Y_COUNT, val)
-#define bfin_read_DMA18_BWL_COUNT() bfin_read32(DMA18_BWL_COUNT)
-#define bfin_write_DMA18_BWL_COUNT(val) bfin_write32(DMA18_BWL_COUNT, val)
-#define bfin_read_DMA18_CURR_BWL_COUNT() bfin_read32(DMA18_CURR_BWL_COUNT)
-#define bfin_write_DMA18_CURR_BWL_COUNT(val) bfin_write32(DMA18_CURR_BWL_COUNT, val)
-#define bfin_read_DMA18_BWM_COUNT() bfin_read32(DMA18_BWM_COUNT)
-#define bfin_write_DMA18_BWM_COUNT(val) bfin_write32(DMA18_BWM_COUNT, val)
-#define bfin_read_DMA18_CURR_BWM_COUNT() bfin_read32(DMA18_CURR_BWM_COUNT)
-#define bfin_write_DMA18_CURR_BWM_COUNT(val) bfin_write32(DMA18_CURR_BWM_COUNT, val)
-
-/* DMA Channel 19 Registers */
-
-#define bfin_read_DMA19_NEXT_DESC_PTR() bfin_read32(DMA19_NEXT_DESC_PTR)
-#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_write32(DMA19_NEXT_DESC_PTR, val)
-#define bfin_read_DMA19_START_ADDR() bfin_read32(DMA19_START_ADDR)
-#define bfin_write_DMA19_START_ADDR(val) bfin_write32(DMA19_START_ADDR, val)
-#define bfin_read_DMA19_CONFIG() bfin_read32(DMA19_CONFIG)
-#define bfin_write_DMA19_CONFIG(val) bfin_write32(DMA19_CONFIG, val)
-#define bfin_read_DMA19_X_COUNT() bfin_read32(DMA19_X_COUNT)
-#define bfin_write_DMA19_X_COUNT(val) bfin_write32(DMA19_X_COUNT, val)
-#define bfin_read_DMA19_X_MODIFY() bfin_read32(DMA19_X_MODIFY)
-#define bfin_write_DMA19_X_MODIFY(val) bfin_write32(DMA19_X_MODIFY, val)
-#define bfin_read_DMA19_Y_COUNT() bfin_read32(DMA19_Y_COUNT)
-#define bfin_write_DMA19_Y_COUNT(val) bfin_write32(DMA19_Y_COUNT, val)
-#define bfin_read_DMA19_Y_MODIFY() bfin_read32(DMA19_Y_MODIFY)
-#define bfin_write_DMA19_Y_MODIFY(val) bfin_write32(DMA19_Y_MODIFY, val)
-#define bfin_read_DMA19_CURR_DESC_PTR() bfin_read32(DMA19_CURR_DESC_PTR)
-#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_write32(DMA19_CURR_DESC_PTR, val)
-#define bfin_read_DMA19_PREV_DESC_PTR() bfin_read32(DMA19_PREV_DESC_PTR)
-#define bfin_write_DMA19_PREV_DESC_PTR(val) bfin_write32(DMA19_PREV_DESC_PTR, val)
-#define bfin_read_DMA19_CURR_ADDR() bfin_read32(DMA19_CURR_ADDR)
-#define bfin_write_DMA19_CURR_ADDR(val) bfin_write32(DMA19_CURR_ADDR, val)
-#define bfin_read_DMA19_IRQ_STATUS() bfin_read32(DMA19_IRQ_STATUS)
-#define bfin_write_DMA19_IRQ_STATUS(val) bfin_write32(DMA19_IRQ_STATUS, val)
-#define bfin_read_DMA19_CURR_X_COUNT() bfin_read32(DMA19_CURR_X_COUNT)
-#define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write32(DMA19_CURR_X_COUNT, val)
-#define bfin_read_DMA19_CURR_Y_COUNT() bfin_read32(DMA19_CURR_Y_COUNT)
-#define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write32(DMA19_CURR_Y_COUNT, val)
-#define bfin_read_DMA19_BWL_COUNT() bfin_read32(DMA19_BWL_COUNT)
-#define bfin_write_DMA19_BWL_COUNT(val) bfin_write32(DMA19_BWL_COUNT, val)
-#define bfin_read_DMA19_CURR_BWL_COUNT() bfin_read32(DMA19_CURR_BWL_COUNT)
-#define bfin_write_DMA19_CURR_BWL_COUNT(val) bfin_write32(DMA19_CURR_BWL_COUNT, val)
-#define bfin_read_DMA19_BWM_COUNT() bfin_read32(DMA19_BWM_COUNT)
-#define bfin_write_DMA19_BWM_COUNT(val) bfin_write32(DMA19_BWM_COUNT, val)
-#define bfin_read_DMA19_CURR_BWM_COUNT() bfin_read32(DMA19_CURR_BWM_COUNT)
-#define bfin_write_DMA19_CURR_BWM_COUNT(val) bfin_write32(DMA19_CURR_BWM_COUNT, val)
-
-/* DMA Channel 20 Registers */
-
-#define bfin_read_DMA20_NEXT_DESC_PTR() bfin_read32(DMA20_NEXT_DESC_PTR)
-#define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_write32(DMA20_NEXT_DESC_PTR, val)
-#define bfin_read_DMA20_START_ADDR() bfin_read32(DMA20_START_ADDR)
-#define bfin_write_DMA20_START_ADDR(val) bfin_write32(DMA20_START_ADDR, val)
-#define bfin_read_DMA20_CONFIG() bfin_read32(DMA20_CONFIG)
-#define bfin_write_DMA20_CONFIG(val) bfin_write32(DMA20_CONFIG, val)
-#define bfin_read_DMA20_X_COUNT() bfin_read32(DMA20_X_COUNT)
-#define bfin_write_DMA20_X_COUNT(val) bfin_write32(DMA20_X_COUNT, val)
-#define bfin_read_DMA20_X_MODIFY() bfin_read32(DMA20_X_MODIFY)
-#define bfin_write_DMA20_X_MODIFY(val) bfin_write32(DMA20_X_MODIFY, val)
-#define bfin_read_DMA20_Y_COUNT() bfin_read32(DMA20_Y_COUNT)
-#define bfin_write_DMA20_Y_COUNT(val) bfin_write32(DMA20_Y_COUNT, val)
-#define bfin_read_DMA20_Y_MODIFY() bfin_read32(DMA20_Y_MODIFY)
-#define bfin_write_DMA20_Y_MODIFY(val) bfin_write32(DMA20_Y_MODIFY, val)
-#define bfin_read_DMA20_CURR_DESC_PTR() bfin_read32(DMA20_CURR_DESC_PTR)
-#define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_write32(DMA20_CURR_DESC_PTR, val)
-#define bfin_read_DMA20_PREV_DESC_PTR() bfin_read32(DMA20_PREV_DESC_PTR)
-#define bfin_write_DMA20_PREV_DESC_PTR(val) bfin_write32(DMA20_PREV_DESC_PTR, val)
-#define bfin_read_DMA20_CURR_ADDR() bfin_read32(DMA20_CURR_ADDR)
-#define bfin_write_DMA20_CURR_ADDR(val) bfin_write32(DMA20_CURR_ADDR, val)
-#define bfin_read_DMA20_IRQ_STATUS() bfin_read32(DMA20_IRQ_STATUS)
-#define bfin_write_DMA20_IRQ_STATUS(val) bfin_write32(DMA20_IRQ_STATUS, val)
-#define bfin_read_DMA20_CURR_X_COUNT() bfin_read32(DMA20_CURR_X_COUNT)
-#define bfin_write_DMA20_CURR_X_COUNT(val) bfin_write32(DMA20_CURR_X_COUNT, val)
-#define bfin_read_DMA20_CURR_Y_COUNT() bfin_read32(DMA20_CURR_Y_COUNT)
-#define bfin_write_DMA20_CURR_Y_COUNT(val) bfin_write32(DMA20_CURR_Y_COUNT, val)
-#define bfin_read_DMA20_BWL_COUNT() bfin_read32(DMA20_BWL_COUNT)
-#define bfin_write_DMA20_BWL_COUNT(val) bfin_write32(DMA20_BWL_COUNT, val)
-#define bfin_read_DMA20_CURR_BWL_COUNT() bfin_read32(DMA20_CURR_BWL_COUNT)
-#define bfin_write_DMA20_CURR_BWL_COUNT(val) bfin_write32(DMA20_CURR_BWL_COUNT, val)
-#define bfin_read_DMA20_BWM_COUNT() bfin_read32(DMA20_BWM_COUNT)
-#define bfin_write_DMA20_BWM_COUNT(val) bfin_write32(DMA20_BWM_COUNT, val)
-#define bfin_read_DMA20_CURR_BWM_COUNT() bfin_read32(DMA20_CURR_BWM_COUNT)
-#define bfin_write_DMA20_CURR_BWM_COUNT(val) bfin_write32(DMA20_CURR_BWM_COUNT, val)
-
-
-/* MDMA Stream 0 Registers (DMA Channel 21 and 22) */
-
-#define bfin_read_MDMA0_DEST_CRC0_NEXT_DESC_PTR() bfin_read32(MDMA0_DEST_CRC0_NEXT_DESC_PTR)
-#define bfin_write_MDMA0_DEST_CRC0_NEXT_DESC_PTR(val) bfin_write32(MDMA0_DEST_CRC0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA0_DEST_CRC0_START_ADDR() bfin_read32(MDMA0_DEST_CRC0_START_ADDR)
-#define bfin_write_MDMA0_DEST_CRC0_START_ADDR(val) bfin_write32(MDMA0_DEST_CRC0_START_ADDR, val)
-#define bfin_read_MDMA0_DEST_CRC0_CONFIG() bfin_read32(MDMA0_DEST_CRC0_CONFIG)
-#define bfin_write_MDMA0_DEST_CRC0_CONFIG(val) bfin_write32(MDMA0_DEST_CRC0_CONFIG, val)
-#define bfin_read_MDMA0_DEST_CRC0_X_COUNT() bfin_read32(MDMA0_DEST_CRC0_X_COUNT)
-#define bfin_write_MDMA0_DEST_CRC0_X_COUNT(val) bfin_write32(MDMA0_DEST_CRC0_X_COUNT, val)
-#define bfin_read_MDMA0_DEST_CRC0_X_MODIFY() bfin_read32(MDMA0_DEST_CRC0_X_MODIFY)
-#define bfin_write_MDMA0_DEST_CRC0_X_MODIFY(val) bfin_write32(MDMA0_DEST_CRC0_X_MODIFY, val)
-#define bfin_read_MDMA0_DEST_CRC0_Y_COUNT() bfin_read32(MDMA0_DEST_CRC0_Y_COUNT)
-#define bfin_write_MDMA0_DEST_CRC0_Y_COUNT(val) bfin_write32(MDMA0_DEST_CRC0_Y_COUNT, val)
-#define bfin_read_MDMA0_DEST_CRC0_Y_MODIFY() bfin_read32(MDMA0_DEST_CRC0_Y_MODIFY)
-#define bfin_write_MDMA0_DEST_CRC0_Y_MODIFY(val) bfin_write32(MDMA0_DEST_CRC0_Y_MODIFY, val)
-#define bfin_read_MDMA0_DEST_CRC0_CURR_DESC_PTR() bfin_read32(MDMA0_DEST_CRC0_CURR_DESC_PTR)
-#define bfin_write_MDMA0_DEST_CRC0_CURR_DESC_PTR(val) bfin_write32(MDMA0_DEST_CRC0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA0_DEST_CRC0_PREV_DESC_PTR() bfin_read32(MDMA0_DEST_CRC0_PREV_DESC_PTR)
-#define bfin_write_MDMA0_DEST_CRC0_PREV_DESC_PTR(val) bfin_write32(MDMA0_DEST_CRC0_PREV_DESC_PTR, val)
-#define bfin_read_MDMA0_DEST_CRC0_CURR_ADDR() bfin_read32(MDMA0_DEST_CRC0_CURR_ADDR)
-#define bfin_write_MDMA0_DEST_CRC0_CURR_ADDR(val) bfin_write32(MDMA0_DEST_CRC0_CURR_ADDR, val)
-#define bfin_read_MDMA0_DEST_CRC0_IRQ_STATUS() bfin_read32(MDMA0_DEST_CRC0_IRQ_STATUS)
-#define bfin_write_MDMA0_DEST_CRC0_IRQ_STATUS(val) bfin_write32(MDMA0_DEST_CRC0_IRQ_STATUS, val)
-#define bfin_read_MDMA0_DEST_CRC0_CURR_X_COUNT() bfin_read32(MDMA0_DEST_CRC0_CURR_X_COUNT)
-#define bfin_write_MDMA0_DEST_CRC0_CURR_X_COUNT(val) bfin_write32(MDMA0_DEST_CRC0_CURR_X_COUNT, val)
-#define bfin_read_MDMA0_DEST_CRC0_CURR_Y_COUNT() bfin_read32(MDMA0_DEST_CRC0_CURR_Y_COUNT)
-#define bfin_write_MDMA0_DEST_CRC0_CURR_Y_COUNT(val) bfin_write32(MDMA0_DEST_CRC0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA0_SRC_CRC0_NEXT_DESC_PTR() bfin_read32(MDMA0_SRC_CRC0_NEXT_DESC_PTR)
-#define bfin_write_MDMA0_SRC_CRC0_NEXT_DESC_PTR(val) bfin_write32(MDMA0_SRC_CRC0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA0_SRC_CRC0_START_ADDR() bfin_read32(MDMA0_SRC_CRC0_START_ADDR)
-#define bfin_write_MDMA0_SRC_CRC0_START_ADDR(val) bfin_write32(MDMA0_SRC_CRC0_START_ADDR, val)
-#define bfin_read_MDMA0_SRC_CRC0_CONFIG() bfin_read32(MDMA0_SRC_CRC0_CONFIG)
-#define bfin_write_MDMA0_SRC_CRC0_CONFIG(val) bfin_write32(MDMA0_SRC_CRC0_CONFIG, val)
-#define bfin_read_MDMA0_SRC_CRC0_X_COUNT() bfin_read32(MDMA0_SRC_CRC0_X_COUNT)
-#define bfin_write_MDMA0_SRC_CRC0_X_COUNT(val) bfin_write32(MDMA0_SRC_CRC0_X_COUNT, val)
-#define bfin_read_MDMA0_SRC_CRC0_X_MODIFY() bfin_read32(MDMA0_SRC_CRC0_X_MODIFY)
-#define bfin_write_MDMA0_SRC_CRC0_X_MODIFY(val) bfin_write32(MDMA0_SRC_CRC0_X_MODIFY, val)
-#define bfin_read_MDMA0_SRC_CRC0_Y_COUNT() bfin_read32(MDMA0_SRC_CRC0_Y_COUNT)
-#define bfin_write_MDMA0_SRC_CRC0_Y_COUNT(val) bfin_write32(MDMA0_SRC_CRC0_Y_COUNT, val)
-#define bfin_read_MDMA0_SRC_CRC0_Y_MODIFY() bfin_read32(MDMA0_SRC_CRC0_Y_MODIFY)
-#define bfin_write_MDMA0_SRC_CRC0_Y_MODIFY(val) bfin_write32(MDMA0_SRC_CRC0_Y_MODIFY, val)
-#define bfin_read_MDMA0_SRC_CRC0_CURR_DESC_PTR() bfin_read32(MDMA0_SRC_CRC0_CURR_DESC_PTR)
-#define bfin_write_MDMA0_SRC_CRC0_CURR_DESC_PTR(val) bfin_write32(MDMA0_SRC_CRC0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA0_SRC_CRC0_PREV_DESC_PTR() bfin_read32(MDMA0_SRC_CRC0_PREV_DESC_PTR)
-#define bfin_write_MDMA0_SRC_CRC0_PREV_DESC_PTR(val) bfin_write32(MDMA0_SRC_CRC0_PREV_DESC_PTR, val)
-#define bfin_read_MDMA0_SRC_CRC0_CURR_ADDR() bfin_read32(MDMA0_SRC_CRC0_CURR_ADDR)
-#define bfin_write_MDMA0_SRC_CRC0_CURR_ADDR(val) bfin_write32(MDMA0_SRC_CRC0_CURR_ADDR, val)
-#define bfin_read_MDMA0_SRC_CRC0_IRQ_STATUS() bfin_read32(MDMA0_SRC_CRC0_IRQ_STATUS)
-#define bfin_write_MDMA0_SRC_CRC0_IRQ_STATUS(val) bfin_write32(MDMA0_SRC_CRC0_IRQ_STATUS, val)
-#define bfin_read_MDMA0_SRC_CRC0_CURR_X_COUNT() bfin_read32(MDMA0_SRC_CRC0_CURR_X_COUNT)
-#define bfin_write_MDMA0_SRC_CRC0_CURR_X_COUNT(val) bfin_write32(MDMA0_SRC_CRC0_CURR_X_COUNT, val)
-#define bfin_read_MDMA0_SRC_CRC0_CURR_Y_COUNT() bfin_read32(MDMA0_SRC_CRC0_CURR_Y_COUNT)
-#define bfin_write_MDMA0_SRC_CRC0_CURR_Y_COUNT(val) bfin_write32(MDMA0_SRC_CRC0_CURR_Y_COUNT, val)
-
-/* MDMA Stream 1 Registers (DMA Channel 23 and 24) */
-
-#define bfin_read_MDMA1_DEST_CRC1_NEXT_DESC_PTR() bfin_read32(MDMA1_DEST_CRC1_NEXT_DESC_PTR)
-#define bfin_write_MDMA1_DEST_CRC1_NEXT_DESC_PTR(val) bfin_write32(MDMA1_DEST_CRC1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA1_DEST_CRC1_START_ADDR() bfin_read32(MDMA1_DEST_CRC1_START_ADDR)
-#define bfin_write_MDMA1_DEST_CRC1_START_ADDR(val) bfin_write32(MDMA1_DEST_CRC1_START_ADDR, val)
-#define bfin_read_MDMA1_DEST_CRC1_CONFIG() bfin_read32(MDMA1_DEST_CRC1_CONFIG)
-#define bfin_write_MDMA1_DEST_CRC1_CONFIG(val) bfin_write32(MDMA1_DEST_CRC1_CONFIG, val)
-#define bfin_read_MDMA1_DEST_CRC1_X_COUNT() bfin_read32(MDMA1_DEST_CRC1_X_COUNT)
-#define bfin_write_MDMA1_DEST_CRC1_X_COUNT(val) bfin_write32(MDMA1_DEST_CRC1_X_COUNT, val)
-#define bfin_read_MDMA1_DEST_CRC1_X_MODIFY() bfin_read32(MDMA1_DEST_CRC1_X_MODIFY)
-#define bfin_write_MDMA1_DEST_CRC1_X_MODIFY(val) bfin_write32(MDMA1_DEST_CRC1_X_MODIFY, val)
-#define bfin_read_MDMA1_DEST_CRC1_Y_COUNT() bfin_read32(MDMA1_DEST_CRC1_Y_COUNT)
-#define bfin_write_MDMA1_DEST_CRC1_Y_COUNT(val) bfin_write32(MDMA1_DEST_CRC1_Y_COUNT, val)
-#define bfin_read_MDMA1_DEST_CRC1_Y_MODIFY() bfin_read32(MDMA1_DEST_CRC1_Y_MODIFY)
-#define bfin_write_MDMA1_DEST_CRC1_Y_MODIFY(val) bfin_write32(MDMA1_DEST_CRC1_Y_MODIFY, val)
-#define bfin_read_MDMA1_DEST_CRC1_CURR_DESC_PTR() bfin_read32(MDMA1_DEST_CRC1_CURR_DESC_PTR)
-#define bfin_write_MDMA1_DEST_CRC1_CURR_DESC_PTR(val) bfin_write32(MDMA1_DEST_CRC1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA1_DEST_CRC1_PREV_DESC_PTR() bfin_read32(MDMA1_DEST_CRC1_PREV_DESC_PTR)
-#define bfin_write_MDMA1_DEST_CRC1_PREV_DESC_PTR(val) bfin_write32(MDMA1_DEST_CRC1_PREV_DESC_PTR, val)
-#define bfin_read_MDMA1_DEST_CRC1_CURR_ADDR() bfin_read32(MDMA1_DEST_CRC1_CURR_ADDR)
-#define bfin_write_MDMA1_DEST_CRC1_CURR_ADDR(val) bfin_write32(MDMA1_DEST_CRC1_CURR_ADDR, val)
-#define bfin_read_MDMA1_DEST_CRC1_IRQ_STATUS() bfin_read32(MDMA1_DEST_CRC1_IRQ_STATUS)
-#define bfin_write_MDMA1_DEST_CRC1_IRQ_STATUS(val) bfin_write32(MDMA1_DEST_CRC1_IRQ_STATUS, val)
-#define bfin_read_MDMA1_DEST_CRC1_CURR_X_COUNT() bfin_read32(MDMA1_DEST_CRC1_CURR_X_COUNT)
-#define bfin_write_MDMA1_DEST_CRC1_CURR_X_COUNT(val) bfin_write32(MDMA1_DEST_CRC1_CURR_X_COUNT, val)
-#define bfin_read_MDMA1_DEST_CRC1_CURR_Y_COUNT() bfin_read32(MDMA1_DEST_CRC1_CURR_Y_COUNT)
-#define bfin_write_MDMA1_DEST_CRC1_CURR_Y_COUNT(val) bfin_write32(MDMA1_DEST_CRC1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA1_SRC_CRC1_NEXT_DESC_PTR() bfin_read32(MDMA1_SRC_CRC1_NEXT_DESC_PTR)
-#define bfin_write_MDMA1_SRC_CRC1_NEXT_DESC_PTR(val) bfin_write32(MDMA1_SRC_CRC1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA1_SRC_CRC1_START_ADDR() bfin_read32(MDMA1_SRC_CRC1_START_ADDR)
-#define bfin_write_MDMA1_SRC_CRC1_START_ADDR(val) bfin_write32(MDMA1_SRC_CRC1_START_ADDR, val)
-#define bfin_read_MDMA1_SRC_CRC1_CONFIG() bfin_read32(MDMA1_SRC_CRC1_CONFIG)
-#define bfin_write_MDMA1_SRC_CRC1_CONFIG(val) bfin_write32(MDMA1_SRC_CRC1_CONFIG, val)
-#define bfin_read_MDMA1_SRC_CRC1_X_COUNT() bfin_read32(MDMA1_SRC_CRC1_X_COUNT)
-#define bfin_write_MDMA1_SRC_CRC1_X_COUNT(val) bfin_write32(MDMA1_SRC_CRC1_X_COUNT, val)
-#define bfin_read_MDMA1_SRC_CRC1_X_MODIFY() bfin_read32(MDMA1_SRC_CRC1_X_MODIFY)
-#define bfin_write_MDMA1_SRC_CRC1_X_MODIFY(val) bfin_write32(MDMA1_SRC_CRC1_X_MODIFY, val)
-#define bfin_read_MDMA1_SRC_CRC1_Y_COUNT() bfin_read32(MDMA1_SRC_CRC1_Y_COUNT)
-#define bfin_write_MDMA1_SRC_CRC1_Y_COUNT(val) bfin_write32(MDMA1_SRC_CRC1_Y_COUNT, val)
-#define bfin_read_MDMA1_SRC_CRC1_Y_MODIFY() bfin_read32(MDMA1_SRC_CRC1_Y_MODIFY)
-#define bfin_write_MDMA1_SRC_CRC1_Y_MODIFY(val) bfin_write32(MDMA1_SRC_CRC1_Y_MODIFY, val)
-#define bfin_read_MDMA1_SRC_CRC1_CURR_DESC_PTR() bfin_read32(MDMA1_SRC_CRC1_CURR_DESC_PTR)
-#define bfin_write_MDMA1_SRC_CRC1_CURR_DESC_PTR(val) bfin_write32(MDMA1_SRC_CRC1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA1_SRC_CRC1_PREV_DESC_PTR() bfin_read32(MDMA1_SRC_CRC1_PREV_DESC_PTR)
-#define bfin_write_MDMA1_SRC_CRC1_PREV_DESC_PTR(val) bfin_write32(MDMA1_SRC_CRC1_PREV_DESC_PTR, val)
-#define bfin_read_MDMA1_SRC_CRC1_CURR_ADDR() bfin_read32(MDMA1_SRC_CRC1_CURR_ADDR)
-#define bfin_write_MDMA1_SRC_CRC1_CURR_ADDR(val) bfin_write32(MDMA1_SRC_CRC1_CURR_ADDR, val)
-#define bfin_read_MDMA1_SRC_CRC1_IRQ_STATUS() bfin_read32(MDMA1_SRC_CRC1_IRQ_STATUS)
-#define bfin_write_MDMA1_SRC_CRC1_IRQ_STATUS(val) bfin_write32(MDMA1_SRC_CRC1_IRQ_STATUS, val)
-#define bfin_read_MDMA1_SRC_CRC1_CURR_X_COUNT() bfin_read32(MDMA1_SRC_CRC1_CURR_X_COUNT)
-#define bfin_write_MDMA1_SRC_CRC1_CURR_X_COUNT(val) bfin_write32(MDMA1_SRC_CRC1_CURR_X_COUNT, val)
-#define bfin_read_MDMA1_SRC_CRC1_CURR_Y_COUNT() bfin_read32(MDMA1_SRC_CRC1_CURR_Y_COUNT)
-#define bfin_write_MDMA1_SRC_CRC1_CURR_Y_COUNT(val) bfin_write32(MDMA1_SRC_CRC1_CURR_Y_COUNT, val)
-
-
-/* MDMA Stream 2 Registers (DMA Channel 25 and 26) */
-
-#define bfin_read_MDMA2_DEST_NEXT_DESC_PTR() bfin_read32(MDMA2_DEST_NEXT_DESC_PTR)
-#define bfin_write_MDMA2_DEST_NEXT_DESC_PTR(val) bfin_write32(MDMA2_DEST_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA2_DEST_START_ADDR() bfin_read32(MDMA2_DEST_START_ADDR)
-#define bfin_write_MDMA2_DEST_START_ADDR(val) bfin_write32(MDMA2_DEST_START_ADDR, val)
-#define bfin_read_MDMA2_DEST_CONFIG() bfin_read32(MDMA2_DEST_CONFIG)
-#define bfin_write_MDMA2_DEST_CONFIG(val) bfin_write32(MDMA2_DEST_CONFIG, val)
-#define bfin_read_MDMA2_DEST_X_COUNT() bfin_read32(MDMA2_DEST_X_COUNT)
-#define bfin_write_MDMA2_DEST_X_COUNT(val) bfin_write32(MDMA2_DEST_X_COUNT, val)
-#define bfin_read_MDMA2_DEST_X_MODIFY() bfin_read32(MDMA2_DEST_X_MODIFY)
-#define bfin_write_MDMA2_DEST_X_MODIFY(val) bfin_write32(MDMA2_DEST_X_MODIFY, val)
-#define bfin_read_MDMA2_DEST_Y_COUNT() bfin_read32(MDMA2_DEST_Y_COUNT)
-#define bfin_write_MDMA2_DEST_Y_COUNT(val) bfin_write32(MDMA2_DEST_Y_COUNT, val)
-#define bfin_read_MDMA2_DEST_Y_MODIFY() bfin_read32(MDMA2_DEST_Y_MODIFY)
-#define bfin_write_MDMA2_DEST_Y_MODIFY(val) bfin_write32(MDMA2_DEST_Y_MODIFY, val)
-#define bfin_read_MDMA2_DEST_CURR_DESC_PTR() bfin_read32(MDMA2_DEST_CURR_DESC_PTR)
-#define bfin_write_MDMA2_DEST_CURR_DESC_PTR(val) bfin_write32(MDMA2_DEST_CURR_DESC_PTR, val)
-#define bfin_read_MDMA2_DEST_PREV_DESC_PTR() bfin_read32(MDMA2_DEST_PREV_DESC_PTR)
-#define bfin_write_MDMA2_DEST_PREV_DESC_PTR(val) bfin_write32(MDMA2_DEST_PREV_DESC_PTR, val)
-#define bfin_read_MDMA2_DEST_CURR_ADDR() bfin_read32(MDMA2_DEST_CURR_ADDR)
-#define bfin_write_MDMA2_DEST_CURR_ADDR(val) bfin_write32(MDMA2_DEST_CURR_ADDR, val)
-#define bfin_read_MDMA2_DEST_IRQ_STATUS() bfin_read32(MDMA2_DEST_IRQ_STATUS)
-#define bfin_write_MDMA2_DEST_IRQ_STATUS(val) bfin_write32(MDMA2_DEST_IRQ_STATUS, val)
-#define bfin_read_MDMA2_DEST_CURR_X_COUNT() bfin_read32(MDMA2_DEST_CURR_X_COUNT)
-#define bfin_write_MDMA2_DEST_CURR_X_COUNT(val) bfin_write32(MDMA2_DEST_CURR_X_COUNT, val)
-#define bfin_read_MDMA2_DEST_CURR_Y_COUNT() bfin_read32(MDMA2_DEST_CURR_Y_COUNT)
-#define bfin_write_MDMA2_DEST_CURR_Y_COUNT(val) bfin_write32(MDMA2_DEST_CURR_Y_COUNT, val)
-#define bfin_read_MDMA2_SRC_NEXT_DESC_PTR() bfin_read32(MDMA2_SRC_NEXT_DESC_PTR)
-#define bfin_write_MDMA2_SRC_NEXT_DESC_PTR(val) bfin_write32(MDMA2_SRC_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA2_SRC_START_ADDR() bfin_read32(MDMA2_SRC_START_ADDR)
-#define bfin_write_MDMA2_SRC_START_ADDR(val) bfin_write32(MDMA2_SRC_START_ADDR, val)
-#define bfin_read_MDMA2_SRC_CONFIG() bfin_read32(MDMA2_SRC_CONFIG)
-#define bfin_write_MDMA2_SRC_CONFIG(val) bfin_write32(MDMA2_SRC_CONFIG, val)
-#define bfin_read_MDMA2_SRC_X_COUNT() bfin_read32(MDMA2_SRC_X_COUNT)
-#define bfin_write_MDMA2_SRC_X_COUNT(val) bfin_write32(MDMA2_SRC_X_COUNT, val)
-#define bfin_read_MDMA2_SRC_X_MODIFY() bfin_read32(MDMA2_SRC_X_MODIFY)
-#define bfin_write_MDMA2_SRC_X_MODIFY(val) bfin_write32(MDMA2_SRC_X_MODIFY, val)
-#define bfin_read_MDMA2_SRC_Y_COUNT() bfin_read32(MDMA2_SRC_Y_COUNT)
-#define bfin_write_MDMA2_SRC_Y_COUNT(val) bfin_write32(MDMA2_SRC_Y_COUNT, val)
-#define bfin_read_MDMA2_SRC_Y_MODIFY() bfin_read32(MDMA2_SRC_Y_MODIFY)
-#define bfin_write_MDMA2_SRC_Y_MODIFY(val) bfin_write32(MDMA2_SRC_Y_MODIFY, val)
-#define bfin_read_MDMA2_SRC_CURR_DESC_PTR() bfin_read32(MDMA2_SRC_CURR_DESC_PTR)
-#define bfin_write_MDMA2_SRC_CURR_DESC_PTR(val) bfin_write32(MDMA2_SRC_CURR_DESC_PTR, val)
-#define bfin_read_MDMA2_SRC_PREV_DESC_PTR() bfin_read32(MDMA2_SRC_PREV_DESC_PTR)
-#define bfin_write_MDMA2_SRC_PREV_DESC_PTR(val) bfin_write32(MDMA2_SRC_PREV_DESC_PTR, val)
-#define bfin_read_MDMA2_SRC_CURR_ADDR() bfin_read32(MDMA2_SRC_CURR_ADDR)
-#define bfin_write_MDMA2_SRC_CURR_ADDR(val) bfin_write32(MDMA2_SRC_CURR_ADDR, val)
-#define bfin_read_MDMA2_SRC_IRQ_STATUS() bfin_read32(MDMA2_SRC_IRQ_STATUS)
-#define bfin_write_MDMA2_SRC_IRQ_STATUS(val) bfin_write32(MDMA2_SRC_IRQ_STATUS, val)
-#define bfin_read_MDMA2_SRC_CURR_X_COUNT() bfin_read32(MDMA2_SRC_CURR_X_COUNT)
-#define bfin_write_MDMA2_SRC_CURR_X_COUNT(val) bfin_write32(MDMA2_SRC_CURR_X_COUNT, val)
-#define bfin_read_MDMA2_SRC_CURR_Y_COUNT() bfin_read32(MDMA2_SRC_CURR_Y_COUNT)
-#define bfin_write_MDMA2_SRC_CURR_Y_COUNT(val) bfin_write32(MDMA2_SRC_CURR_Y_COUNT, val)
-
-/* MDMA Stream 3 Registers (DMA Channel 27 and 28) */
-
-#define bfin_read_MDMA3_DEST_NEXT_DESC_PTR() bfin_read32(MDMA3_DEST_NEXT_DESC_PTR)
-#define bfin_write_MDMA3_DEST_NEXT_DESC_PTR(val) bfin_write32(MDMA3_DEST_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA3_DEST_START_ADDR() bfin_read32(MDMA3_DEST_START_ADDR)
-#define bfin_write_MDMA3_DEST_START_ADDR(val) bfin_write32(MDMA3_DEST_START_ADDR, val)
-#define bfin_read_MDMA3_DEST_CONFIG() bfin_read32(MDMA3_DEST_CONFIG)
-#define bfin_write_MDMA3_DEST_CONFIG(val) bfin_write32(MDMA3_DEST_CONFIG, val)
-#define bfin_read_MDMA3_DEST_X_COUNT() bfin_read32(MDMA3_DEST_X_COUNT)
-#define bfin_write_MDMA3_DEST_X_COUNT(val) bfin_write32(MDMA3_DEST_X_COUNT, val)
-#define bfin_read_MDMA3_DEST_X_MODIFY() bfin_read32(MDMA3_DEST_X_MODIFY)
-#define bfin_write_MDMA3_DEST_X_MODIFY(val) bfin_write32(MDMA3_DEST_X_MODIFY, val)
-#define bfin_read_MDMA3_DEST_Y_COUNT() bfin_read32(MDMA3_DEST_Y_COUNT)
-#define bfin_write_MDMA3_DEST_Y_COUNT(val) bfin_write32(MDMA3_DEST_Y_COUNT, val)
-#define bfin_read_MDMA3_DEST_Y_MODIFY() bfin_read32(MDMA3_DEST_Y_MODIFY)
-#define bfin_write_MDMA3_DEST_Y_MODIFY(val) bfin_write32(MDMA3_DEST_Y_MODIFY, val)
-#define bfin_read_MDMA3_DEST_CURR_DESC_PTR() bfin_read32(MDMA3_DEST_CURR_DESC_PTR)
-#define bfin_write_MDMA3_DEST_CURR_DESC_PTR(val) bfin_write32(MDMA3_DEST_CURR_DESC_PTR, val)
-#define bfin_read_MDMA3_DEST_PREV_DESC_PTR() bfin_read32(MDMA3_DEST_PREV_DESC_PTR)
-#define bfin_write_MDMA3_DEST_PREV_DESC_PTR(val) bfin_write32(MDMA3_DEST_PREV_DESC_PTR, val)
-#define bfin_read_MDMA3_DEST_CURR_ADDR() bfin_read32(MDMA3_DEST_CURR_ADDR)
-#define bfin_write_MDMA3_DEST_CURR_ADDR(val) bfin_write32(MDMA3_DEST_CURR_ADDR, val)
-#define bfin_read_MDMA3_DEST_IRQ_STATUS() bfin_read32(MDMA3_DEST_IRQ_STATUS)
-#define bfin_write_MDMA3_DEST_IRQ_STATUS(val) bfin_write32(MDMA3_DEST_IRQ_STATUS, val)
-#define bfin_read_MDMA3_DEST_CURR_X_COUNT() bfin_read32(MDMA3_DEST_CURR_X_COUNT)
-#define bfin_write_MDMA3_DEST_CURR_X_COUNT(val) bfin_write32(MDMA3_DEST_CURR_X_COUNT, val)
-#define bfin_read_MDMA3_DEST_CURR_Y_COUNT() bfin_read32(MDMA3_DEST_CURR_Y_COUNT)
-#define bfin_write_MDMA3_DEST_CURR_Y_COUNT(val) bfin_write32(MDMA3_DEST_CURR_Y_COUNT, val)
-#define bfin_read_MDMA3_SRC_NEXT_DESC_PTR() bfin_read32(MDMA3_SRC_NEXT_DESC_PTR)
-#define bfin_write_MDMA3_SRC_NEXT_DESC_PTR(val) bfin_write32(MDMA3_SRC_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA3_SRC_START_ADDR() bfin_read32(MDMA3_SRC_START_ADDR)
-#define bfin_write_MDMA3_SRC_START_ADDR(val) bfin_write32(MDMA3_SRC_START_ADDR, val)
-#define bfin_read_MDMA3_SRC_CONFIG() bfin_read32(MDMA3_SRC_CONFIG)
-#define bfin_write_MDMA3_SRC_CONFIG(val) bfin_write32(MDMA3_SRC_CONFIG, val)
-#define bfin_read_MDMA3_SRC_X_COUNT() bfin_read32(MDMA3_SRC_X_COUNT)
-#define bfin_write_MDMA3_SRC_X_COUNT(val) bfin_write32(MDMA3_SRC_X_COUNT, val)
-#define bfin_read_MDMA3_SRC_X_MODIFY() bfin_read32(MDMA3_SRC_X_MODIFY)
-#define bfin_write_MDMA3_SRC_X_MODIFY(val) bfin_write32(MDMA3_SRC_X_MODIFY, val)
-#define bfin_read_MDMA3_SRC_Y_COUNT() bfin_read32(MDMA3_SRC_Y_COUNT)
-#define bfin_write_MDMA3_SRC_Y_COUNT(val) bfin_write32(MDMA3_SRC_Y_COUNT, val)
-#define bfin_read_MDMA3_SRC_Y_MODIFY() bfin_read32(MDMA3_SRC_Y_MODIFY)
-#define bfin_write_MDMA3_SRC_Y_MODIFY(val) bfin_write32(MDMA3_SRC_Y_MODIFY, val)
-#define bfin_read_MDMA3_SRC_CURR_DESC_PTR() bfin_read32(MDMA3_SRC_CURR_DESC_PTR)
-#define bfin_write_MDMA3_SRC_CURR_DESC_PTR(val) bfin_write32(MDMA3_SRC_CURR_DESC_PTR, val)
-#define bfin_read_MDMA3_SRC_PREV_DESC_PTR() bfin_read32(MDMA3_SRC_PREV_DESC_PTR)
-#define bfin_write_MDMA3_SRC_PREV_DESC_PTR(val) bfin_write32(MDMA3_SRC_PREV_DESC_PTR, val)
-#define bfin_read_MDMA3_SRC_CURR_ADDR() bfin_read32(MDMA3_SRC_CURR_ADDR)
-#define bfin_write_MDMA3_SRC_CURR_ADDR(val) bfin_write32(MDMA3_SRC_CURR_ADDR, val)
-#define bfin_read_MDMA3_SRC_IRQ_STATUS() bfin_read32(MDMA3_SRC_IRQ_STATUS)
-#define bfin_write_MDMA3_SRC_IRQ_STATUS(val) bfin_write32(MDMA3_SRC_IRQ_STATUS, val)
-#define bfin_read_MDMA3_SRC_CURR_X_COUNT() bfin_read32(MDMA3_SRC_CURR_X_COUNT)
-#define bfin_write_MDMA3_SRC_CURR_X_COUNT(val) bfin_write32(MDMA3_SRC_CURR_X_COUNT, val)
-#define bfin_read_MDMA3_SRC_CURR_Y_COUNT() bfin_read32(MDMA3_SRC_CURR_Y_COUNT)
-#define bfin_write_MDMA3_SRC_CURR_Y_COUNT(val) bfin_write32(MDMA3_SRC_CURR_Y_COUNT, val)
-
-
-/* DMA Channel 29 Registers */
-
-#define bfin_read_DMA29_NEXT_DESC_PTR() bfin_read32(DMA29_NEXT_DESC_PTR)
-#define bfin_write_DMA29_NEXT_DESC_PTR(val) bfin_write32(DMA29_NEXT_DESC_PTR, val)
-#define bfin_read_DMA29_START_ADDR() bfin_read32(DMA29_START_ADDR)
-#define bfin_write_DMA29_START_ADDR(val) bfin_write32(DMA29_START_ADDR, val)
-#define bfin_read_DMA29_CONFIG() bfin_read32(DMA29_CONFIG)
-#define bfin_write_DMA29_CONFIG(val) bfin_write32(DMA29_CONFIG, val)
-#define bfin_read_DMA29_X_COUNT() bfin_read32(DMA29_X_COUNT)
-#define bfin_write_DMA29_X_COUNT(val) bfin_write32(DMA29_X_COUNT, val)
-#define bfin_read_DMA29_X_MODIFY() bfin_read32(DMA29_X_MODIFY)
-#define bfin_write_DMA29_X_MODIFY(val) bfin_write32(DMA29_X_MODIFY, val)
-#define bfin_read_DMA29_Y_COUNT() bfin_read32(DMA29_Y_COUNT)
-#define bfin_write_DMA29_Y_COUNT(val) bfin_write32(DMA29_Y_COUNT, val)
-#define bfin_read_DMA29_Y_MODIFY() bfin_read32(DMA29_Y_MODIFY)
-#define bfin_write_DMA29_Y_MODIFY(val) bfin_write32(DMA29_Y_MODIFY, val)
-#define bfin_read_DMA29_CURR_DESC_PTR() bfin_read32(DMA29_CURR_DESC_PTR)
-#define bfin_write_DMA29_CURR_DESC_PTR(val) bfin_write32(DMA29_CURR_DESC_PTR, val)
-#define bfin_read_DMA29_PREV_DESC_PTR() bfin_read32(DMA29_PREV_DESC_PTR)
-#define bfin_write_DMA29_PREV_DESC_PTR(val) bfin_write32(DMA29_PREV_DESC_PTR, val)
-#define bfin_read_DMA29_CURR_ADDR() bfin_read32(DMA29_CURR_ADDR)
-#define bfin_write_DMA29_CURR_ADDR(val) bfin_write32(DMA29_CURR_ADDR, val)
-#define bfin_read_DMA29_IRQ_STATUS() bfin_read32(DMA29_IRQ_STATUS)
-#define bfin_write_DMA29_IRQ_STATUS(val) bfin_write32(DMA29_IRQ_STATUS, val)
-#define bfin_read_DMA29_CURR_X_COUNT() bfin_read32(DMA29_CURR_X_COUNT)
-#define bfin_write_DMA29_CURR_X_COUNT(val) bfin_write32(DMA29_CURR_X_COUNT, val)
-#define bfin_read_DMA29_CURR_Y_COUNT() bfin_read32(DMA29_CURR_Y_COUNT)
-#define bfin_write_DMA29_CURR_Y_COUNT(val) bfin_write32(DMA29_CURR_Y_COUNT, val)
-#define bfin_read_DMA29_BWL_COUNT() bfin_read32(DMA29_BWL_COUNT)
-#define bfin_write_DMA29_BWL_COUNT(val) bfin_write32(DMA29_BWL_COUNT, val)
-#define bfin_read_DMA29_CURR_BWL_COUNT() bfin_read32(DMA29_CURR_BWL_COUNT)
-#define bfin_write_DMA29_CURR_BWL_COUNT(val) bfin_write32(DMA29_CURR_BWL_COUNT, val)
-#define bfin_read_DMA29_BWM_COUNT() bfin_read32(DMA29_BWM_COUNT)
-#define bfin_write_DMA29_BWM_COUNT(val) bfin_write32(DMA29_BWM_COUNT, val)
-#define bfin_read_DMA29_CURR_BWM_COUNT() bfin_read32(DMA29_CURR_BWM_COUNT)
-#define bfin_write_DMA29_CURR_BWM_COUNT(val) bfin_write32(DMA29_CURR_BWM_COUNT, val)
-
-/* DMA Channel 30 Registers */
-
-#define bfin_read_DMA30_NEXT_DESC_PTR() bfin_read32(DMA30_NEXT_DESC_PTR)
-#define bfin_write_DMA30_NEXT_DESC_PTR(val) bfin_write32(DMA30_NEXT_DESC_PTR, val)
-#define bfin_read_DMA30_START_ADDR() bfin_read32(DMA30_START_ADDR)
-#define bfin_write_DMA30_START_ADDR(val) bfin_write32(DMA30_START_ADDR, val)
-#define bfin_read_DMA30_CONFIG() bfin_read32(DMA30_CONFIG)
-#define bfin_write_DMA30_CONFIG(val) bfin_write32(DMA30_CONFIG, val)
-#define bfin_read_DMA30_X_COUNT() bfin_read32(DMA30_X_COUNT)
-#define bfin_write_DMA30_X_COUNT(val) bfin_write32(DMA30_X_COUNT, val)
-#define bfin_read_DMA30_X_MODIFY() bfin_read32(DMA30_X_MODIFY)
-#define bfin_write_DMA30_X_MODIFY(val) bfin_write32(DMA30_X_MODIFY, val)
-#define bfin_read_DMA30_Y_COUNT() bfin_read32(DMA30_Y_COUNT)
-#define bfin_write_DMA30_Y_COUNT(val) bfin_write32(DMA30_Y_COUNT, val)
-#define bfin_read_DMA30_Y_MODIFY() bfin_read32(DMA30_Y_MODIFY)
-#define bfin_write_DMA30_Y_MODIFY(val) bfin_write32(DMA30_Y_MODIFY, val)
-#define bfin_read_DMA30_CURR_DESC_PTR() bfin_read32(DMA30_CURR_DESC_PTR)
-#define bfin_write_DMA30_CURR_DESC_PTR(val) bfin_write32(DMA30_CURR_DESC_PTR, val)
-#define bfin_read_DMA30_PREV_DESC_PTR() bfin_read32(DMA30_PREV_DESC_PTR)
-#define bfin_write_DMA30_PREV_DESC_PTR(val) bfin_write32(DMA30_PREV_DESC_PTR, val)
-#define bfin_read_DMA30_CURR_ADDR() bfin_read32(DMA30_CURR_ADDR)
-#define bfin_write_DMA30_CURR_ADDR(val) bfin_write32(DMA30_CURR_ADDR, val)
-#define bfin_read_DMA30_IRQ_STATUS() bfin_read32(DMA30_IRQ_STATUS)
-#define bfin_write_DMA30_IRQ_STATUS(val) bfin_write32(DMA30_IRQ_STATUS, val)
-#define bfin_read_DMA30_CURR_X_COUNT() bfin_read32(DMA30_CURR_X_COUNT)
-#define bfin_write_DMA30_CURR_X_COUNT(val) bfin_write32(DMA30_CURR_X_COUNT, val)
-#define bfin_read_DMA30_CURR_Y_COUNT() bfin_read32(DMA30_CURR_Y_COUNT)
-#define bfin_write_DMA30_CURR_Y_COUNT(val) bfin_write32(DMA30_CURR_Y_COUNT, val)
-#define bfin_read_DMA30_BWL_COUNT() bfin_read32(DMA30_BWL_COUNT)
-#define bfin_write_DMA30_BWL_COUNT(val) bfin_write32(DMA30_BWL_COUNT, val)
-#define bfin_read_DMA30_CURR_BWL_COUNT() bfin_read32(DMA30_CURR_BWL_COUNT)
-#define bfin_write_DMA30_CURR_BWL_COUNT(val) bfin_write32(DMA30_CURR_BWL_COUNT, val)
-#define bfin_read_DMA30_BWM_COUNT() bfin_read32(DMA30_BWM_COUNT)
-#define bfin_write_DMA30_BWM_COUNT(val) bfin_write32(DMA30_BWM_COUNT, val)
-#define bfin_read_DMA30_CURR_BWM_COUNT() bfin_read32(DMA30_CURR_BWM_COUNT)
-#define bfin_write_DMA30_CURR_BWM_COUNT(val) bfin_write32(DMA30_CURR_BWM_COUNT, val)
-
-/* DMA Channel 31 Registers */
-
-#define bfin_read_DMA31_NEXT_DESC_PTR() bfin_read32(DMA31_NEXT_DESC_PTR)
-#define bfin_write_DMA31_NEXT_DESC_PTR(val) bfin_write32(DMA31_NEXT_DESC_PTR, val)
-#define bfin_read_DMA31_START_ADDR() bfin_read32(DMA31_START_ADDR)
-#define bfin_write_DMA31_START_ADDR(val) bfin_write32(DMA31_START_ADDR, val)
-#define bfin_read_DMA31_CONFIG() bfin_read32(DMA31_CONFIG)
-#define bfin_write_DMA31_CONFIG(val) bfin_write32(DMA31_CONFIG, val)
-#define bfin_read_DMA31_X_COUNT() bfin_read32(DMA31_X_COUNT)
-#define bfin_write_DMA31_X_COUNT(val) bfin_write32(DMA31_X_COUNT, val)
-#define bfin_read_DMA31_X_MODIFY() bfin_read32(DMA31_X_MODIFY)
-#define bfin_write_DMA31_X_MODIFY(val) bfin_write32(DMA31_X_MODIFY, val)
-#define bfin_read_DMA31_Y_COUNT() bfin_read32(DMA31_Y_COUNT)
-#define bfin_write_DMA31_Y_COUNT(val) bfin_write32(DMA31_Y_COUNT, val)
-#define bfin_read_DMA31_Y_MODIFY() bfin_read32(DMA31_Y_MODIFY)
-#define bfin_write_DMA31_Y_MODIFY(val) bfin_write32(DMA31_Y_MODIFY, val)
-#define bfin_read_DMA31_CURR_DESC_PTR() bfin_read32(DMA31_CURR_DESC_PTR)
-#define bfin_write_DMA31_CURR_DESC_PTR(val) bfin_write32(DMA31_CURR_DESC_PTR, val)
-#define bfin_read_DMA31_PREV_DESC_PTR() bfin_read32(DMA31_PREV_DESC_PTR)
-#define bfin_write_DMA31_PREV_DESC_PTR(val) bfin_write32(DMA31_PREV_DESC_PTR, val)
-#define bfin_read_DMA31_CURR_ADDR() bfin_read32(DMA31_CURR_ADDR)
-#define bfin_write_DMA31_CURR_ADDR(val) bfin_write32(DMA31_CURR_ADDR, val)
-#define bfin_read_DMA31_IRQ_STATUS() bfin_read32(DMA31_IRQ_STATUS)
-#define bfin_write_DMA31_IRQ_STATUS(val) bfin_write32(DMA31_IRQ_STATUS, val)
-#define bfin_read_DMA31_CURR_X_COUNT() bfin_read32(DMA31_CURR_X_COUNT)
-#define bfin_write_DMA31_CURR_X_COUNT(val) bfin_write32(DMA31_CURR_X_COUNT, val)
-#define bfin_read_DMA31_CURR_Y_COUNT() bfin_read32(DMA31_CURR_Y_COUNT)
-#define bfin_write_DMA31_CURR_Y_COUNT(val) bfin_write32(DMA31_CURR_Y_COUNT, val)
-#define bfin_read_DMA31_BWL_COUNT() bfin_read32(DMA31_BWL_COUNT)
-#define bfin_write_DMA31_BWL_COUNT(val) bfin_write32(DMA31_BWL_COUNT, val)
-#define bfin_read_DMA31_CURR_BWL_COUNT() bfin_read32(DMA31_CURR_BWL_COUNT)
-#define bfin_write_DMA31_CURR_BWL_COUNT(val) bfin_write32(DMA31_CURR_BWL_COUNT, val)
-#define bfin_read_DMA31_BWM_COUNT() bfin_read32(DMA31_BWM_COUNT)
-#define bfin_write_DMA31_BWM_COUNT(val) bfin_write32(DMA31_BWM_COUNT, val)
-#define bfin_read_DMA31_CURR_BWM_COUNT() bfin_read32(DMA31_CURR_BWM_COUNT)
-#define bfin_write_DMA31_CURR_BWM_COUNT(val) bfin_write32(DMA31_CURR_BWM_COUNT, val)
-
-/* DMA Channel 32 Registers */
-
-#define bfin_read_DMA32_NEXT_DESC_PTR() bfin_read32(DMA32_NEXT_DESC_PTR)
-#define bfin_write_DMA32_NEXT_DESC_PTR(val) bfin_write32(DMA32_NEXT_DESC_PTR, val)
-#define bfin_read_DMA32_START_ADDR() bfin_read32(DMA32_START_ADDR)
-#define bfin_write_DMA32_START_ADDR(val) bfin_write32(DMA32_START_ADDR, val)
-#define bfin_read_DMA32_CONFIG() bfin_read32(DMA32_CONFIG)
-#define bfin_write_DMA32_CONFIG(val) bfin_write32(DMA32_CONFIG, val)
-#define bfin_read_DMA32_X_COUNT() bfin_read32(DMA32_X_COUNT)
-#define bfin_write_DMA32_X_COUNT(val) bfin_write32(DMA32_X_COUNT, val)
-#define bfin_read_DMA32_X_MODIFY() bfin_read32(DMA32_X_MODIFY)
-#define bfin_write_DMA32_X_MODIFY(val) bfin_write32(DMA32_X_MODIFY, val)
-#define bfin_read_DMA32_Y_COUNT() bfin_read32(DMA32_Y_COUNT)
-#define bfin_write_DMA32_Y_COUNT(val) bfin_write32(DMA32_Y_COUNT, val)
-#define bfin_read_DMA32_Y_MODIFY() bfin_read32(DMA32_Y_MODIFY)
-#define bfin_write_DMA32_Y_MODIFY(val) bfin_write32(DMA32_Y_MODIFY, val)
-#define bfin_read_DMA32_CURR_DESC_PTR() bfin_read32(DMA32_CURR_DESC_PTR)
-#define bfin_write_DMA32_CURR_DESC_PTR(val) bfin_write32(DMA32_CURR_DESC_PTR, val)
-#define bfin_read_DMA32_PREV_DESC_PTR() bfin_read32(DMA32_PREV_DESC_PTR)
-#define bfin_write_DMA32_PREV_DESC_PTR(val) bfin_write32(DMA32_PREV_DESC_PTR, val)
-#define bfin_read_DMA32_CURR_ADDR() bfin_read32(DMA32_CURR_ADDR)
-#define bfin_write_DMA32_CURR_ADDR(val) bfin_write32(DMA32_CURR_ADDR, val)
-#define bfin_read_DMA32_IRQ_STATUS() bfin_read32(DMA32_IRQ_STATUS)
-#define bfin_write_DMA32_IRQ_STATUS(val) bfin_write32(DMA32_IRQ_STATUS, val)
-#define bfin_read_DMA32_CURR_X_COUNT() bfin_read32(DMA32_CURR_X_COUNT)
-#define bfin_write_DMA32_CURR_X_COUNT(val) bfin_write32(DMA32_CURR_X_COUNT, val)
-#define bfin_read_DMA32_CURR_Y_COUNT() bfin_read32(DMA32_CURR_Y_COUNT)
-#define bfin_write_DMA32_CURR_Y_COUNT(val) bfin_write32(DMA32_CURR_Y_COUNT, val)
-#define bfin_read_DMA32_BWL_COUNT() bfin_read32(DMA32_BWL_COUNT)
-#define bfin_write_DMA32_BWL_COUNT(val) bfin_write32(DMA32_BWL_COUNT, val)
-#define bfin_read_DMA32_CURR_BWL_COUNT() bfin_read32(DMA32_CURR_BWL_COUNT)
-#define bfin_write_DMA32_CURR_BWL_COUNT(val) bfin_write32(DMA32_CURR_BWL_COUNT, val)
-#define bfin_read_DMA32_BWM_COUNT() bfin_read32(DMA32_BWM_COUNT)
-#define bfin_write_DMA32_BWM_COUNT(val) bfin_write32(DMA32_BWM_COUNT, val)
-#define bfin_read_DMA32_CURR_BWM_COUNT() bfin_read32(DMA32_CURR_BWM_COUNT)
-#define bfin_write_DMA32_CURR_BWM_COUNT(val) bfin_write32(DMA32_CURR_BWM_COUNT, val)
-
-/* DMA Channel 33 Registers */
-
-#define bfin_read_DMA33_NEXT_DESC_PTR() bfin_read32(DMA33_NEXT_DESC_PTR)
-#define bfin_write_DMA33_NEXT_DESC_PTR(val) bfin_write32(DMA33_NEXT_DESC_PTR, val)
-#define bfin_read_DMA33_START_ADDR() bfin_read32(DMA33_START_ADDR)
-#define bfin_write_DMA33_START_ADDR(val) bfin_write32(DMA33_START_ADDR, val)
-#define bfin_read_DMA33_CONFIG() bfin_read32(DMA33_CONFIG)
-#define bfin_write_DMA33_CONFIG(val) bfin_write32(DMA33_CONFIG, val)
-#define bfin_read_DMA33_X_COUNT() bfin_read32(DMA33_X_COUNT)
-#define bfin_write_DMA33_X_COUNT(val) bfin_write32(DMA33_X_COUNT, val)
-#define bfin_read_DMA33_X_MODIFY() bfin_read32(DMA33_X_MODIFY)
-#define bfin_write_DMA33_X_MODIFY(val) bfin_write32(DMA33_X_MODIFY, val)
-#define bfin_read_DMA33_Y_COUNT() bfin_read32(DMA33_Y_COUNT)
-#define bfin_write_DMA33_Y_COUNT(val) bfin_write32(DMA33_Y_COUNT, val)
-#define bfin_read_DMA33_Y_MODIFY() bfin_read32(DMA33_Y_MODIFY)
-#define bfin_write_DMA33_Y_MODIFY(val) bfin_write32(DMA33_Y_MODIFY, val)
-#define bfin_read_DMA33_CURR_DESC_PTR() bfin_read32(DMA33_CURR_DESC_PTR)
-#define bfin_write_DMA33_CURR_DESC_PTR(val) bfin_write32(DMA33_CURR_DESC_PTR, val)
-#define bfin_read_DMA33_PREV_DESC_PTR() bfin_read32(DMA33_PREV_DESC_PTR)
-#define bfin_write_DMA33_PREV_DESC_PTR(val) bfin_write32(DMA33_PREV_DESC_PTR, val)
-#define bfin_read_DMA33_CURR_ADDR() bfin_read32(DMA33_CURR_ADDR)
-#define bfin_write_DMA33_CURR_ADDR(val) bfin_write32(DMA33_CURR_ADDR, val)
-#define bfin_read_DMA33_IRQ_STATUS() bfin_read32(DMA33_IRQ_STATUS)
-#define bfin_write_DMA33_IRQ_STATUS(val) bfin_write32(DMA33_IRQ_STATUS, val)
-#define bfin_read_DMA33_CURR_X_COUNT() bfin_read32(DMA33_CURR_X_COUNT)
-#define bfin_write_DMA33_CURR_X_COUNT(val) bfin_write32(DMA33_CURR_X_COUNT, val)
-#define bfin_read_DMA33_CURR_Y_COUNT() bfin_read32(DMA33_CURR_Y_COUNT)
-#define bfin_write_DMA33_CURR_Y_COUNT(val) bfin_write32(DMA33_CURR_Y_COUNT, val)
-#define bfin_read_DMA33_BWL_COUNT() bfin_read32(DMA33_BWL_COUNT)
-#define bfin_write_DMA33_BWL_COUNT(val) bfin_write32(DMA33_BWL_COUNT, val)
-#define bfin_read_DMA33_CURR_BWL_COUNT() bfin_read32(DMA33_CURR_BWL_COUNT)
-#define bfin_write_DMA33_CURR_BWL_COUNT(val) bfin_write32(DMA33_CURR_BWL_COUNT, val)
-#define bfin_read_DMA33_BWM_COUNT() bfin_read32(DMA33_BWM_COUNT)
-#define bfin_write_DMA33_BWM_COUNT(val) bfin_write32(DMA33_BWM_COUNT, val)
-#define bfin_read_DMA33_CURR_BWM_COUNT() bfin_read32(DMA33_CURR_BWM_COUNT)
-#define bfin_write_DMA33_CURR_BWM_COUNT(val) bfin_write32(DMA33_CURR_BWM_COUNT, val)
-
-/* DMA Channel 34 Registers */
-
-#define bfin_read_DMA34_NEXT_DESC_PTR() bfin_read32(DMA34_NEXT_DESC_PTR)
-#define bfin_write_DMA34_NEXT_DESC_PTR(val) bfin_write32(DMA34_NEXT_DESC_PTR, val)
-#define bfin_read_DMA34_START_ADDR() bfin_read32(DMA34_START_ADDR)
-#define bfin_write_DMA34_START_ADDR(val) bfin_write32(DMA34_START_ADDR, val)
-#define bfin_read_DMA34_CONFIG() bfin_read32(DMA34_CONFIG)
-#define bfin_write_DMA34_CONFIG(val) bfin_write32(DMA34_CONFIG, val)
-#define bfin_read_DMA34_X_COUNT() bfin_read32(DMA34_X_COUNT)
-#define bfin_write_DMA34_X_COUNT(val) bfin_write32(DMA34_X_COUNT, val)
-#define bfin_read_DMA34_X_MODIFY() bfin_read32(DMA34_X_MODIFY)
-#define bfin_write_DMA34_X_MODIFY(val) bfin_write32(DMA34_X_MODIFY, val)
-#define bfin_read_DMA34_Y_COUNT() bfin_read32(DMA34_Y_COUNT)
-#define bfin_write_DMA34_Y_COUNT(val) bfin_write32(DMA34_Y_COUNT, val)
-#define bfin_read_DMA34_Y_MODIFY() bfin_read32(DMA34_Y_MODIFY)
-#define bfin_write_DMA34_Y_MODIFY(val) bfin_write32(DMA34_Y_MODIFY, val)
-#define bfin_read_DMA34_CURR_DESC_PTR() bfin_read32(DMA34_CURR_DESC_PTR)
-#define bfin_write_DMA34_CURR_DESC_PTR(val) bfin_write32(DMA34_CURR_DESC_PTR, val)
-#define bfin_read_DMA34_PREV_DESC_PTR() bfin_read32(DMA34_PREV_DESC_PTR)
-#define bfin_write_DMA34_PREV_DESC_PTR(val) bfin_write32(DMA34_PREV_DESC_PTR, val)
-#define bfin_read_DMA34_CURR_ADDR() bfin_read32(DMA34_CURR_ADDR)
-#define bfin_write_DMA34_CURR_ADDR(val) bfin_write32(DMA34_CURR_ADDR, val)
-#define bfin_read_DMA34_IRQ_STATUS() bfin_read32(DMA34_IRQ_STATUS)
-#define bfin_write_DMA34_IRQ_STATUS(val) bfin_write32(DMA34_IRQ_STATUS, val)
-#define bfin_read_DMA34_CURR_X_COUNT() bfin_read32(DMA34_CURR_X_COUNT)
-#define bfin_write_DMA34_CURR_X_COUNT(val) bfin_write32(DMA34_CURR_X_COUNT, val)
-#define bfin_read_DMA34_CURR_Y_COUNT() bfin_read32(DMA34_CURR_Y_COUNT)
-#define bfin_write_DMA34_CURR_Y_COUNT(val) bfin_write32(DMA34_CURR_Y_COUNT, val)
-#define bfin_read_DMA34_BWL_COUNT() bfin_read32(DMA34_BWL_COUNT)
-#define bfin_write_DMA34_BWL_COUNT(val) bfin_write32(DMA34_BWL_COUNT, val)
-#define bfin_read_DMA34_CURR_BWL_COUNT() bfin_read32(DMA34_CURR_BWL_COUNT)
-#define bfin_write_DMA34_CURR_BWL_COUNT(val) bfin_write32(DMA34_CURR_BWL_COUNT, val)
-#define bfin_read_DMA34_BWM_COUNT() bfin_read32(DMA34_BWM_COUNT)
-#define bfin_write_DMA34_BWM_COUNT(val) bfin_write32(DMA34_BWM_COUNT, val)
-#define bfin_read_DMA34_CURR_BWM_COUNT() bfin_read32(DMA34_CURR_BWM_COUNT)
-#define bfin_write_DMA34_CURR_BWM_COUNT(val) bfin_write32(DMA34_CURR_BWM_COUNT, val)
-
-/* DMA Channel 35 Registers */
-
-#define bfin_read_DMA35_NEXT_DESC_PTR() bfin_read32(DMA35_NEXT_DESC_PTR)
-#define bfin_write_DMA35_NEXT_DESC_PTR(val) bfin_write32(DMA35_NEXT_DESC_PTR, val)
-#define bfin_read_DMA35_START_ADDR() bfin_read32(DMA35_START_ADDR)
-#define bfin_write_DMA35_START_ADDR(val) bfin_write32(DMA35_START_ADDR, val)
-#define bfin_read_DMA35_CONFIG() bfin_read32(DMA35_CONFIG)
-#define bfin_write_DMA35_CONFIG(val) bfin_write32(DMA35_CONFIG, val)
-#define bfin_read_DMA35_X_COUNT() bfin_read32(DMA35_X_COUNT)
-#define bfin_write_DMA35_X_COUNT(val) bfin_write32(DMA35_X_COUNT, val)
-#define bfin_read_DMA35_X_MODIFY() bfin_read32(DMA35_X_MODIFY)
-#define bfin_write_DMA35_X_MODIFY(val) bfin_write32(DMA35_X_MODIFY, val)
-#define bfin_read_DMA35_Y_COUNT() bfin_read32(DMA35_Y_COUNT)
-#define bfin_write_DMA35_Y_COUNT(val) bfin_write32(DMA35_Y_COUNT, val)
-#define bfin_read_DMA35_Y_MODIFY() bfin_read32(DMA35_Y_MODIFY)
-#define bfin_write_DMA35_Y_MODIFY(val) bfin_write32(DMA35_Y_MODIFY, val)
-#define bfin_read_DMA35_CURR_DESC_PTR() bfin_read32(DMA35_CURR_DESC_PTR)
-#define bfin_write_DMA35_CURR_DESC_PTR(val) bfin_write32(DMA35_CURR_DESC_PTR, val)
-#define bfin_read_DMA35_PREV_DESC_PTR() bfin_read32(DMA35_PREV_DESC_PTR)
-#define bfin_write_DMA35_PREV_DESC_PTR(val) bfin_write32(DMA35_PREV_DESC_PTR, val)
-#define bfin_read_DMA35_CURR_ADDR() bfin_read32(DMA35_CURR_ADDR)
-#define bfin_write_DMA35_CURR_ADDR(val) bfin_write32(DMA35_CURR_ADDR, val)
-#define bfin_read_DMA35_IRQ_STATUS() bfin_read32(DMA35_IRQ_STATUS)
-#define bfin_write_DMA35_IRQ_STATUS(val) bfin_write32(DMA35_IRQ_STATUS, val)
-#define bfin_read_DMA35_CURR_X_COUNT() bfin_read32(DMA35_CURR_X_COUNT)
-#define bfin_write_DMA35_CURR_X_COUNT(val) bfin_write32(DMA35_CURR_X_COUNT, val)
-#define bfin_read_DMA35_CURR_Y_COUNT() bfin_read32(DMA35_CURR_Y_COUNT)
-#define bfin_write_DMA35_CURR_Y_COUNT(val) bfin_write32(DMA35_CURR_Y_COUNT, val)
-#define bfin_read_DMA35_BWL_COUNT() bfin_read32(DMA35_BWL_COUNT)
-#define bfin_write_DMA35_BWL_COUNT(val) bfin_write32(DMA35_BWL_COUNT, val)
-#define bfin_read_DMA35_CURR_BWL_COUNT() bfin_read32(DMA35_CURR_BWL_COUNT)
-#define bfin_write_DMA35_CURR_BWL_COUNT(val) bfin_write32(DMA35_CURR_BWL_COUNT, val)
-#define bfin_read_DMA35_BWM_COUNT() bfin_read32(DMA35_BWM_COUNT)
-#define bfin_write_DMA35_BWM_COUNT(val) bfin_write32(DMA35_BWM_COUNT, val)
-#define bfin_read_DMA35_CURR_BWM_COUNT() bfin_read32(DMA35_CURR_BWM_COUNT)
-#define bfin_write_DMA35_CURR_BWM_COUNT(val) bfin_write32(DMA35_CURR_BWM_COUNT, val)
-
-/* DMA Channel 36 Registers */
-
-#define bfin_read_DMA36_NEXT_DESC_PTR() bfin_read32(DMA36_NEXT_DESC_PTR)
-#define bfin_write_DMA36_NEXT_DESC_PTR(val) bfin_write32(DMA36_NEXT_DESC_PTR, val)
-#define bfin_read_DMA36_START_ADDR() bfin_read32(DMA36_START_ADDR)
-#define bfin_write_DMA36_START_ADDR(val) bfin_write32(DMA36_START_ADDR, val)
-#define bfin_read_DMA36_CONFIG() bfin_read32(DMA36_CONFIG)
-#define bfin_write_DMA36_CONFIG(val) bfin_write32(DMA36_CONFIG, val)
-#define bfin_read_DMA36_X_COUNT() bfin_read32(DMA36_X_COUNT)
-#define bfin_write_DMA36_X_COUNT(val) bfin_write32(DMA36_X_COUNT, val)
-#define bfin_read_DMA36_X_MODIFY() bfin_read32(DMA36_X_MODIFY)
-#define bfin_write_DMA36_X_MODIFY(val) bfin_write32(DMA36_X_MODIFY, val)
-#define bfin_read_DMA36_Y_COUNT() bfin_read32(DMA36_Y_COUNT)
-#define bfin_write_DMA36_Y_COUNT(val) bfin_write32(DMA36_Y_COUNT, val)
-#define bfin_read_DMA36_Y_MODIFY() bfin_read32(DMA36_Y_MODIFY)
-#define bfin_write_DMA36_Y_MODIFY(val) bfin_write32(DMA36_Y_MODIFY, val)
-#define bfin_read_DMA36_CURR_DESC_PTR() bfin_read32(DMA36_CURR_DESC_PTR)
-#define bfin_write_DMA36_CURR_DESC_PTR(val) bfin_write32(DMA36_CURR_DESC_PTR, val)
-#define bfin_read_DMA36_PREV_DESC_PTR() bfin_read32(DMA36_PREV_DESC_PTR)
-#define bfin_write_DMA36_PREV_DESC_PTR(val) bfin_write32(DMA36_PREV_DESC_PTR, val)
-#define bfin_read_DMA36_CURR_ADDR() bfin_read32(DMA36_CURR_ADDR)
-#define bfin_write_DMA36_CURR_ADDR(val) bfin_write32(DMA36_CURR_ADDR, val)
-#define bfin_read_DMA36_IRQ_STATUS() bfin_read32(DMA36_IRQ_STATUS)
-#define bfin_write_DMA36_IRQ_STATUS(val) bfin_write32(DMA36_IRQ_STATUS, val)
-#define bfin_read_DMA36_CURR_X_COUNT() bfin_read32(DMA36_CURR_X_COUNT)
-#define bfin_write_DMA36_CURR_X_COUNT(val) bfin_write32(DMA36_CURR_X_COUNT, val)
-#define bfin_read_DMA36_CURR_Y_COUNT() bfin_read32(DMA36_CURR_Y_COUNT)
-#define bfin_write_DMA36_CURR_Y_COUNT(val) bfin_write32(DMA36_CURR_Y_COUNT, val)
-#define bfin_read_DMA36_BWL_COUNT() bfin_read32(DMA36_BWL_COUNT)
-#define bfin_write_DMA36_BWL_COUNT(val) bfin_write32(DMA36_BWL_COUNT, val)
-#define bfin_read_DMA36_CURR_BWL_COUNT() bfin_read32(DMA36_CURR_BWL_COUNT)
-#define bfin_write_DMA36_CURR_BWL_COUNT(val) bfin_write32(DMA36_CURR_BWL_COUNT, val)
-#define bfin_read_DMA36_BWM_COUNT() bfin_read32(DMA36_BWM_COUNT)
-#define bfin_write_DMA36_BWM_COUNT(val) bfin_write32(DMA36_BWM_COUNT, val)
-#define bfin_read_DMA36_CURR_BWM_COUNT() bfin_read32(DMA36_CURR_BWM_COUNT)
-#define bfin_write_DMA36_CURR_BWM_COUNT(val) bfin_write32(DMA36_CURR_BWM_COUNT, val)
-
-/* DMA Channel 37 Registers */
-
-#define bfin_read_DMA37_NEXT_DESC_PTR() bfin_read32(DMA37_NEXT_DESC_PTR)
-#define bfin_write_DMA37_NEXT_DESC_PTR(val) bfin_write32(DMA37_NEXT_DESC_PTR, val)
-#define bfin_read_DMA37_START_ADDR() bfin_read32(DMA37_START_ADDR)
-#define bfin_write_DMA37_START_ADDR(val) bfin_write32(DMA37_START_ADDR, val)
-#define bfin_read_DMA37_CONFIG() bfin_read32(DMA37_CONFIG)
-#define bfin_write_DMA37_CONFIG(val) bfin_write32(DMA37_CONFIG, val)
-#define bfin_read_DMA37_X_COUNT() bfin_read32(DMA37_X_COUNT)
-#define bfin_write_DMA37_X_COUNT(val) bfin_write32(DMA37_X_COUNT, val)
-#define bfin_read_DMA37_X_MODIFY() bfin_read32(DMA37_X_MODIFY)
-#define bfin_write_DMA37_X_MODIFY(val) bfin_write32(DMA37_X_MODIFY, val)
-#define bfin_read_DMA37_Y_COUNT() bfin_read32(DMA37_Y_COUNT)
-#define bfin_write_DMA37_Y_COUNT(val) bfin_write32(DMA37_Y_COUNT, val)
-#define bfin_read_DMA37_Y_MODIFY() bfin_read32(DMA37_Y_MODIFY)
-#define bfin_write_DMA37_Y_MODIFY(val) bfin_write32(DMA37_Y_MODIFY, val)
-#define bfin_read_DMA37_CURR_DESC_PTR() bfin_read32(DMA37_CURR_DESC_PTR)
-#define bfin_write_DMA37_CURR_DESC_PTR(val) bfin_write32(DMA37_CURR_DESC_PTR, val)
-#define bfin_read_DMA37_PREV_DESC_PTR() bfin_read32(DMA37_PREV_DESC_PTR)
-#define bfin_write_DMA37_PREV_DESC_PTR(val) bfin_write32(DMA37_PREV_DESC_PTR, val)
-#define bfin_read_DMA37_CURR_ADDR() bfin_read32(DMA37_CURR_ADDR)
-#define bfin_write_DMA37_CURR_ADDR(val) bfin_write32(DMA37_CURR_ADDR, val)
-#define bfin_read_DMA37_IRQ_STATUS() bfin_read32(DMA37_IRQ_STATUS)
-#define bfin_write_DMA37_IRQ_STATUS(val) bfin_write32(DMA37_IRQ_STATUS, val)
-#define bfin_read_DMA37_CURR_X_COUNT() bfin_read32(DMA37_CURR_X_COUNT)
-#define bfin_write_DMA37_CURR_X_COUNT(val) bfin_write32(DMA37_CURR_X_COUNT, val)
-#define bfin_read_DMA37_CURR_Y_COUNT() bfin_read32(DMA37_CURR_Y_COUNT)
-#define bfin_write_DMA37_CURR_Y_COUNT(val) bfin_write32(DMA37_CURR_Y_COUNT, val)
-#define bfin_read_DMA37_BWL_COUNT() bfin_read32(DMA37_BWL_COUNT)
-#define bfin_write_DMA37_BWL_COUNT(val) bfin_write32(DMA37_BWL_COUNT, val)
-#define bfin_read_DMA37_CURR_BWL_COUNT() bfin_read32(DMA37_CURR_BWL_COUNT)
-#define bfin_write_DMA37_CURR_BWL_COUNT(val) bfin_write32(DMA37_CURR_BWL_COUNT, val)
-#define bfin_read_DMA37_BWM_COUNT() bfin_read32(DMA37_BWM_COUNT)
-#define bfin_write_DMA37_BWM_COUNT(val) bfin_write32(DMA37_BWM_COUNT, val)
-#define bfin_read_DMA37_CURR_BWM_COUNT() bfin_read32(DMA37_CURR_BWM_COUNT)
-#define bfin_write_DMA37_CURR_BWM_COUNT(val) bfin_write32(DMA37_CURR_BWM_COUNT, val)
-
-/* DMA Channel 38 Registers */
-
-#define bfin_read_DMA38_NEXT_DESC_PTR() bfin_read32(DMA38_NEXT_DESC_PTR)
-#define bfin_write_DMA38_NEXT_DESC_PTR(val) bfin_write32(DMA38_NEXT_DESC_PTR, val)
-#define bfin_read_DMA38_START_ADDR() bfin_read32(DMA38_START_ADDR)
-#define bfin_write_DMA38_START_ADDR(val) bfin_write32(DMA38_START_ADDR, val)
-#define bfin_read_DMA38_CONFIG() bfin_read32(DMA38_CONFIG)
-#define bfin_write_DMA38_CONFIG(val) bfin_write32(DMA38_CONFIG, val)
-#define bfin_read_DMA38_X_COUNT() bfin_read32(DMA38_X_COUNT)
-#define bfin_write_DMA38_X_COUNT(val) bfin_write32(DMA38_X_COUNT, val)
-#define bfin_read_DMA38_X_MODIFY() bfin_read32(DMA38_X_MODIFY)
-#define bfin_write_DMA38_X_MODIFY(val) bfin_write32(DMA38_X_MODIFY, val)
-#define bfin_read_DMA38_Y_COUNT() bfin_read32(DMA38_Y_COUNT)
-#define bfin_write_DMA38_Y_COUNT(val) bfin_write32(DMA38_Y_COUNT, val)
-#define bfin_read_DMA38_Y_MODIFY() bfin_read32(DMA38_Y_MODIFY)
-#define bfin_write_DMA38_Y_MODIFY(val) bfin_write32(DMA38_Y_MODIFY, val)
-#define bfin_read_DMA38_CURR_DESC_PTR() bfin_read32(DMA38_CURR_DESC_PTR)
-#define bfin_write_DMA38_CURR_DESC_PTR(val) bfin_write32(DMA38_CURR_DESC_PTR, val)
-#define bfin_read_DMA38_PREV_DESC_PTR() bfin_read32(DMA38_PREV_DESC_PTR)
-#define bfin_write_DMA38_PREV_DESC_PTR(val) bfin_write32(DMA38_PREV_DESC_PTR, val)
-#define bfin_read_DMA38_CURR_ADDR() bfin_read32(DMA38_CURR_ADDR)
-#define bfin_write_DMA38_CURR_ADDR(val) bfin_write32(DMA38_CURR_ADDR, val)
-#define bfin_read_DMA38_IRQ_STATUS() bfin_read32(DMA38_IRQ_STATUS)
-#define bfin_write_DMA38_IRQ_STATUS(val) bfin_write32(DMA38_IRQ_STATUS, val)
-#define bfin_read_DMA38_CURR_X_COUNT() bfin_read32(DMA38_CURR_X_COUNT)
-#define bfin_write_DMA38_CURR_X_COUNT(val) bfin_write32(DMA38_CURR_X_COUNT, val)
-#define bfin_read_DMA38_CURR_Y_COUNT() bfin_read32(DMA38_CURR_Y_COUNT)
-#define bfin_write_DMA38_CURR_Y_COUNT(val) bfin_write32(DMA38_CURR_Y_COUNT, val)
-#define bfin_read_DMA38_BWL_COUNT() bfin_read32(DMA38_BWL_COUNT)
-#define bfin_write_DMA38_BWL_COUNT(val) bfin_write32(DMA38_BWL_COUNT, val)
-#define bfin_read_DMA38_CURR_BWL_COUNT() bfin_read32(DMA38_CURR_BWL_COUNT)
-#define bfin_write_DMA38_CURR_BWL_COUNT(val) bfin_write32(DMA38_CURR_BWL_COUNT, val)
-#define bfin_read_DMA38_BWM_COUNT() bfin_read32(DMA38_BWM_COUNT)
-#define bfin_write_DMA38_BWM_COUNT(val) bfin_write32(DMA38_BWM_COUNT, val)
-#define bfin_read_DMA38_CURR_BWM_COUNT() bfin_read32(DMA38_CURR_BWM_COUNT)
-#define bfin_write_DMA38_CURR_BWM_COUNT(val) bfin_write32(DMA38_CURR_BWM_COUNT, val)
-
-/* DMA Channel 39 Registers */
-
-#define bfin_read_DMA39_NEXT_DESC_PTR() bfin_read32(DMA39_NEXT_DESC_PTR)
-#define bfin_write_DMA39_NEXT_DESC_PTR(val) bfin_write32(DMA39_NEXT_DESC_PTR, val)
-#define bfin_read_DMA39_START_ADDR() bfin_read32(DMA39_START_ADDR)
-#define bfin_write_DMA39_START_ADDR(val) bfin_write32(DMA39_START_ADDR, val)
-#define bfin_read_DMA39_CONFIG() bfin_read32(DMA39_CONFIG)
-#define bfin_write_DMA39_CONFIG(val) bfin_write32(DMA39_CONFIG, val)
-#define bfin_read_DMA39_X_COUNT() bfin_read32(DMA39_X_COUNT)
-#define bfin_write_DMA39_X_COUNT(val) bfin_write32(DMA39_X_COUNT, val)
-#define bfin_read_DMA39_X_MODIFY() bfin_read32(DMA39_X_MODIFY)
-#define bfin_write_DMA39_X_MODIFY(val) bfin_write32(DMA39_X_MODIFY, val)
-#define bfin_read_DMA39_Y_COUNT() bfin_read32(DMA39_Y_COUNT)
-#define bfin_write_DMA39_Y_COUNT(val) bfin_write32(DMA39_Y_COUNT, val)
-#define bfin_read_DMA39_Y_MODIFY() bfin_read32(DMA39_Y_MODIFY)
-#define bfin_write_DMA39_Y_MODIFY(val) bfin_write32(DMA39_Y_MODIFY, val)
-#define bfin_read_DMA39_CURR_DESC_PTR() bfin_read32(DMA39_CURR_DESC_PTR)
-#define bfin_write_DMA39_CURR_DESC_PTR(val) bfin_write32(DMA39_CURR_DESC_PTR, val)
-#define bfin_read_DMA39_PREV_DESC_PTR() bfin_read32(DMA39_PREV_DESC_PTR)
-#define bfin_write_DMA39_PREV_DESC_PTR(val) bfin_write32(DMA39_PREV_DESC_PTR, val)
-#define bfin_read_DMA39_CURR_ADDR() bfin_read32(DMA39_CURR_ADDR)
-#define bfin_write_DMA39_CURR_ADDR(val) bfin_write32(DMA39_CURR_ADDR, val)
-#define bfin_read_DMA39_IRQ_STATUS() bfin_read32(DMA39_IRQ_STATUS)
-#define bfin_write_DMA39_IRQ_STATUS(val) bfin_write32(DMA39_IRQ_STATUS, val)
-#define bfin_read_DMA39_CURR_X_COUNT() bfin_read32(DMA39_CURR_X_COUNT)
-#define bfin_write_DMA39_CURR_X_COUNT(val) bfin_write32(DMA39_CURR_X_COUNT, val)
-#define bfin_read_DMA39_CURR_Y_COUNT() bfin_read32(DMA39_CURR_Y_COUNT)
-#define bfin_write_DMA39_CURR_Y_COUNT(val) bfin_write32(DMA39_CURR_Y_COUNT, val)
-#define bfin_read_DMA39_BWL_COUNT() bfin_read32(DMA39_BWL_COUNT)
-#define bfin_write_DMA39_BWL_COUNT(val) bfin_write32(DMA39_BWL_COUNT, val)
-#define bfin_read_DMA39_CURR_BWL_COUNT() bfin_read32(DMA39_CURR_BWL_COUNT)
-#define bfin_write_DMA39_CURR_BWL_COUNT(val) bfin_write32(DMA39_CURR_BWL_COUNT, val)
-#define bfin_read_DMA39_BWM_COUNT() bfin_read32(DMA39_BWM_COUNT)
-#define bfin_write_DMA39_BWM_COUNT(val) bfin_write32(DMA39_BWM_COUNT, val)
-#define bfin_read_DMA39_CURR_BWM_COUNT() bfin_read32(DMA39_CURR_BWM_COUNT)
-#define bfin_write_DMA39_CURR_BWM_COUNT(val) bfin_write32(DMA39_CURR_BWM_COUNT, val)
-
-/* DMA Channel 40 Registers */
-
-#define bfin_read_DMA40_NEXT_DESC_PTR() bfin_read32(DMA40_NEXT_DESC_PTR)
-#define bfin_write_DMA40_NEXT_DESC_PTR(val) bfin_write32(DMA40_NEXT_DESC_PTR, val)
-#define bfin_read_DMA40_START_ADDR() bfin_read32(DMA40_START_ADDR)
-#define bfin_write_DMA40_START_ADDR(val) bfin_write32(DMA40_START_ADDR, val)
-#define bfin_read_DMA40_CONFIG() bfin_read32(DMA40_CONFIG)
-#define bfin_write_DMA40_CONFIG(val) bfin_write32(DMA40_CONFIG, val)
-#define bfin_read_DMA40_X_COUNT() bfin_read32(DMA40_X_COUNT)
-#define bfin_write_DMA40_X_COUNT(val) bfin_write32(DMA40_X_COUNT, val)
-#define bfin_read_DMA40_X_MODIFY() bfin_read32(DMA40_X_MODIFY)
-#define bfin_write_DMA40_X_MODIFY(val) bfin_write32(DMA40_X_MODIFY, val)
-#define bfin_read_DMA40_Y_COUNT() bfin_read32(DMA40_Y_COUNT)
-#define bfin_write_DMA40_Y_COUNT(val) bfin_write32(DMA40_Y_COUNT, val)
-#define bfin_read_DMA40_Y_MODIFY() bfin_read32(DMA40_Y_MODIFY)
-#define bfin_write_DMA40_Y_MODIFY(val) bfin_write32(DMA40_Y_MODIFY, val)
-#define bfin_read_DMA40_CURR_DESC_PTR() bfin_read32(DMA40_CURR_DESC_PTR)
-#define bfin_write_DMA40_CURR_DESC_PTR(val) bfin_write32(DMA40_CURR_DESC_PTR, val)
-#define bfin_read_DMA40_PREV_DESC_PTR() bfin_read32(DMA40_PREV_DESC_PTR)
-#define bfin_write_DMA40_PREV_DESC_PTR(val) bfin_write32(DMA40_PREV_DESC_PTR, val)
-#define bfin_read_DMA40_CURR_ADDR() bfin_read32(DMA40_CURR_ADDR)
-#define bfin_write_DMA40_CURR_ADDR(val) bfin_write32(DMA40_CURR_ADDR, val)
-#define bfin_read_DMA40_IRQ_STATUS() bfin_read32(DMA40_IRQ_STATUS)
-#define bfin_write_DMA40_IRQ_STATUS(val) bfin_write32(DMA40_IRQ_STATUS, val)
-#define bfin_read_DMA40_CURR_X_COUNT() bfin_read32(DMA40_CURR_X_COUNT)
-#define bfin_write_DMA40_CURR_X_COUNT(val) bfin_write32(DMA40_CURR_X_COUNT, val)
-#define bfin_read_DMA40_CURR_Y_COUNT() bfin_read32(DMA40_CURR_Y_COUNT)
-#define bfin_write_DMA40_CURR_Y_COUNT(val) bfin_write32(DMA40_CURR_Y_COUNT, val)
-#define bfin_read_DMA40_BWL_COUNT() bfin_read32(DMA40_BWL_COUNT)
-#define bfin_write_DMA40_BWL_COUNT(val) bfin_write32(DMA40_BWL_COUNT, val)
-#define bfin_read_DMA40_CURR_BWL_COUNT() bfin_read32(DMA40_CURR_BWL_COUNT)
-#define bfin_write_DMA40_CURR_BWL_COUNT(val) bfin_write32(DMA40_CURR_BWL_COUNT, val)
-#define bfin_read_DMA40_BWM_COUNT() bfin_read32(DMA40_BWM_COUNT)
-#define bfin_write_DMA40_BWM_COUNT(val) bfin_write32(DMA40_BWM_COUNT, val)
-#define bfin_read_DMA40_CURR_BWM_COUNT() bfin_read32(DMA40_CURR_BWM_COUNT)
-#define bfin_write_DMA40_CURR_BWM_COUNT(val) bfin_write32(DMA40_CURR_BWM_COUNT, val)
-
-/* DMA Channel 41 Registers */
-
-#define bfin_read_DMA41_NEXT_DESC_PTR() bfin_read32(DMA41_NEXT_DESC_PTR)
-#define bfin_write_DMA41_NEXT_DESC_PTR(val) bfin_write32(DMA41_NEXT_DESC_PTR, val)
-#define bfin_read_DMA41_START_ADDR() bfin_read32(DMA41_START_ADDR)
-#define bfin_write_DMA41_START_ADDR(val) bfin_write32(DMA41_START_ADDR, val)
-#define bfin_read_DMA41_CONFIG() bfin_read32(DMA41_CONFIG)
-#define bfin_write_DMA41_CONFIG(val) bfin_write32(DMA41_CONFIG, val)
-#define bfin_read_DMA41_X_COUNT() bfin_read32(DMA41_X_COUNT)
-#define bfin_write_DMA41_X_COUNT(val) bfin_write32(DMA41_X_COUNT, val)
-#define bfin_read_DMA41_X_MODIFY() bfin_read32(DMA41_X_MODIFY)
-#define bfin_write_DMA41_X_MODIFY(val) bfin_write32(DMA41_X_MODIFY, val)
-#define bfin_read_DMA41_Y_COUNT() bfin_read32(DMA41_Y_COUNT)
-#define bfin_write_DMA41_Y_COUNT(val) bfin_write32(DMA41_Y_COUNT, val)
-#define bfin_read_DMA41_Y_MODIFY() bfin_read32(DMA41_Y_MODIFY)
-#define bfin_write_DMA41_Y_MODIFY(val) bfin_write32(DMA41_Y_MODIFY, val)
-#define bfin_read_DMA41_CURR_DESC_PTR() bfin_read32(DMA41_CURR_DESC_PTR)
-#define bfin_write_DMA41_CURR_DESC_PTR(val) bfin_write32(DMA41_CURR_DESC_PTR, val)
-#define bfin_read_DMA41_PREV_DESC_PTR() bfin_read32(DMA41_PREV_DESC_PTR)
-#define bfin_write_DMA41_PREV_DESC_PTR(val) bfin_write32(DMA41_PREV_DESC_PTR, val)
-#define bfin_read_DMA41_CURR_ADDR() bfin_read32(DMA41_CURR_ADDR)
-#define bfin_write_DMA41_CURR_ADDR(val) bfin_write32(DMA41_CURR_ADDR, val)
-#define bfin_read_DMA41_IRQ_STATUS() bfin_read32(DMA41_IRQ_STATUS)
-#define bfin_write_DMA41_IRQ_STATUS(val) bfin_write32(DMA41_IRQ_STATUS, val)
-#define bfin_read_DMA41_CURR_X_COUNT() bfin_read32(DMA41_CURR_X_COUNT)
-#define bfin_write_DMA41_CURR_X_COUNT(val) bfin_write32(DMA41_CURR_X_COUNT, val)
-#define bfin_read_DMA41_CURR_Y_COUNT() bfin_read32(DMA41_CURR_Y_COUNT)
-#define bfin_write_DMA41_CURR_Y_COUNT(val) bfin_write32(DMA41_CURR_Y_COUNT, val)
-#define bfin_read_DMA41_BWL_COUNT() bfin_read32(DMA41_BWL_COUNT)
-#define bfin_write_DMA41_BWL_COUNT(val) bfin_write32(DMA41_BWL_COUNT, val)
-#define bfin_read_DMA41_CURR_BWL_COUNT() bfin_read32(DMA41_CURR_BWL_COUNT)
-#define bfin_write_DMA41_CURR_BWL_COUNT(val) bfin_write32(DMA41_CURR_BWL_COUNT, val)
-#define bfin_read_DMA41_BWM_COUNT() bfin_read32(DMA41_BWM_COUNT)
-#define bfin_write_DMA41_BWM_COUNT(val) bfin_write32(DMA41_BWM_COUNT, val)
-#define bfin_read_DMA41_CURR_BWM_COUNT() bfin_read32(DMA41_CURR_BWM_COUNT)
-#define bfin_write_DMA41_CURR_BWM_COUNT(val) bfin_write32(DMA41_CURR_BWM_COUNT, val)
-
-/* DMA Channel 42 Registers */
-
-#define bfin_read_DMA42_NEXT_DESC_PTR() bfin_read32(DMA42_NEXT_DESC_PTR)
-#define bfin_write_DMA42_NEXT_DESC_PTR(val) bfin_write32(DMA42_NEXT_DESC_PTR, val)
-#define bfin_read_DMA42_START_ADDR() bfin_read32(DMA42_START_ADDR)
-#define bfin_write_DMA42_START_ADDR(val) bfin_write32(DMA42_START_ADDR, val)
-#define bfin_read_DMA42_CONFIG() bfin_read32(DMA42_CONFIG)
-#define bfin_write_DMA42_CONFIG(val) bfin_write32(DMA42_CONFIG, val)
-#define bfin_read_DMA42_X_COUNT() bfin_read32(DMA42_X_COUNT)
-#define bfin_write_DMA42_X_COUNT(val) bfin_write32(DMA42_X_COUNT, val)
-#define bfin_read_DMA42_X_MODIFY() bfin_read32(DMA42_X_MODIFY)
-#define bfin_write_DMA42_X_MODIFY(val) bfin_write32(DMA42_X_MODIFY, val)
-#define bfin_read_DMA42_Y_COUNT() bfin_read32(DMA42_Y_COUNT)
-#define bfin_write_DMA42_Y_COUNT(val) bfin_write32(DMA42_Y_COUNT, val)
-#define bfin_read_DMA42_Y_MODIFY() bfin_read32(DMA42_Y_MODIFY)
-#define bfin_write_DMA42_Y_MODIFY(val) bfin_write32(DMA42_Y_MODIFY, val)
-#define bfin_read_DMA42_CURR_DESC_PTR() bfin_read32(DMA42_CURR_DESC_PTR)
-#define bfin_write_DMA42_CURR_DESC_PTR(val) bfin_write32(DMA42_CURR_DESC_PTR, val)
-#define bfin_read_DMA42_PREV_DESC_PTR() bfin_read32(DMA42_PREV_DESC_PTR)
-#define bfin_write_DMA42_PREV_DESC_PTR(val) bfin_write32(DMA42_PREV_DESC_PTR, val)
-#define bfin_read_DMA42_CURR_ADDR() bfin_read32(DMA42_CURR_ADDR)
-#define bfin_write_DMA42_CURR_ADDR(val) bfin_write32(DMA42_CURR_ADDR, val)
-#define bfin_read_DMA42_IRQ_STATUS() bfin_read32(DMA42_IRQ_STATUS)
-#define bfin_write_DMA42_IRQ_STATUS(val) bfin_write32(DMA42_IRQ_STATUS, val)
-#define bfin_read_DMA42_CURR_X_COUNT() bfin_read32(DMA42_CURR_X_COUNT)
-#define bfin_write_DMA42_CURR_X_COUNT(val) bfin_write32(DMA42_CURR_X_COUNT, val)
-#define bfin_read_DMA42_CURR_Y_COUNT() bfin_read32(DMA42_CURR_Y_COUNT)
-#define bfin_write_DMA42_CURR_Y_COUNT(val) bfin_write32(DMA42_CURR_Y_COUNT, val)
-#define bfin_read_DMA42_BWL_COUNT() bfin_read32(DMA42_BWL_COUNT)
-#define bfin_write_DMA42_BWL_COUNT(val) bfin_write32(DMA42_BWL_COUNT, val)
-#define bfin_read_DMA42_CURR_BWL_COUNT() bfin_read32(DMA42_CURR_BWL_COUNT)
-#define bfin_write_DMA42_CURR_BWL_COUNT(val) bfin_write32(DMA42_CURR_BWL_COUNT, val)
-#define bfin_read_DMA42_BWM_COUNT() bfin_read32(DMA42_BWM_COUNT)
-#define bfin_write_DMA42_BWM_COUNT(val) bfin_write32(DMA42_BWM_COUNT, val)
-#define bfin_read_DMA42_CURR_BWM_COUNT() bfin_read32(DMA42_CURR_BWM_COUNT)
-#define bfin_write_DMA42_CURR_BWM_COUNT(val) bfin_write32(DMA42_CURR_BWM_COUNT, val)
-
-/* DMA Channel 43 Registers */
-
-#define bfin_read_DMA43_NEXT_DESC_PTR() bfin_read32(DMA43_NEXT_DESC_PTR)
-#define bfin_write_DMA43_NEXT_DESC_PTR(val) bfin_write32(DMA43_NEXT_DESC_PTR, val)
-#define bfin_read_DMA43_START_ADDR() bfin_read32(DMA43_START_ADDR)
-#define bfin_write_DMA43_START_ADDR(val) bfin_write32(DMA43_START_ADDR, val)
-#define bfin_read_DMA43_CONFIG() bfin_read32(DMA43_CONFIG)
-#define bfin_write_DMA43_CONFIG(val) bfin_write32(DMA43_CONFIG, val)
-#define bfin_read_DMA43_X_COUNT() bfin_read32(DMA43_X_COUNT)
-#define bfin_write_DMA43_X_COUNT(val) bfin_write32(DMA43_X_COUNT, val)
-#define bfin_read_DMA43_X_MODIFY() bfin_read32(DMA43_X_MODIFY)
-#define bfin_write_DMA43_X_MODIFY(val) bfin_write32(DMA43_X_MODIFY, val)
-#define bfin_read_DMA43_Y_COUNT() bfin_read32(DMA43_Y_COUNT)
-#define bfin_write_DMA43_Y_COUNT(val) bfin_write32(DMA43_Y_COUNT, val)
-#define bfin_read_DMA43_Y_MODIFY() bfin_read32(DMA43_Y_MODIFY)
-#define bfin_write_DMA43_Y_MODIFY(val) bfin_write32(DMA43_Y_MODIFY, val)
-#define bfin_read_DMA43_CURR_DESC_PTR() bfin_read32(DMA43_CURR_DESC_PTR)
-#define bfin_write_DMA43_CURR_DESC_PTR(val) bfin_write32(DMA43_CURR_DESC_PTR, val)
-#define bfin_read_DMA43_PREV_DESC_PTR() bfin_read32(DMA43_PREV_DESC_PTR)
-#define bfin_write_DMA43_PREV_DESC_PTR(val) bfin_write32(DMA43_PREV_DESC_PTR, val)
-#define bfin_read_DMA43_CURR_ADDR() bfin_read32(DMA43_CURR_ADDR)
-#define bfin_write_DMA43_CURR_ADDR(val) bfin_write32(DMA43_CURR_ADDR, val)
-#define bfin_read_DMA43_IRQ_STATUS() bfin_read32(DMA43_IRQ_STATUS)
-#define bfin_write_DMA43_IRQ_STATUS(val) bfin_write32(DMA43_IRQ_STATUS, val)
-#define bfin_read_DMA43_CURR_X_COUNT() bfin_read32(DMA43_CURR_X_COUNT)
-#define bfin_write_DMA43_CURR_X_COUNT(val) bfin_write32(DMA43_CURR_X_COUNT, val)
-#define bfin_read_DMA43_CURR_Y_COUNT() bfin_read32(DMA43_CURR_Y_COUNT)
-#define bfin_write_DMA43_CURR_Y_COUNT(val) bfin_write32(DMA43_CURR_Y_COUNT, val)
-#define bfin_read_DMA43_BWL_COUNT() bfin_read32(DMA43_BWL_COUNT)
-#define bfin_write_DMA43_BWL_COUNT(val) bfin_write32(DMA43_BWL_COUNT, val)
-#define bfin_read_DMA43_CURR_BWL_COUNT() bfin_read32(DMA43_CURR_BWL_COUNT)
-#define bfin_write_DMA43_CURR_BWL_COUNT(val) bfin_write32(DMA43_CURR_BWL_COUNT, val)
-#define bfin_read_DMA43_BWM_COUNT() bfin_read32(DMA43_BWM_COUNT)
-#define bfin_write_DMA43_BWM_COUNT(val) bfin_write32(DMA43_BWM_COUNT, val)
-#define bfin_read_DMA43_CURR_BWM_COUNT() bfin_read32(DMA43_CURR_BWM_COUNT)
-#define bfin_write_DMA43_CURR_BWM_COUNT(val) bfin_write32(DMA43_CURR_BWM_COUNT, val)
-
-/* DMA Channel 44 Registers */
-
-#define bfin_read_DMA44_NEXT_DESC_PTR() bfin_read32(DMA44_NEXT_DESC_PTR)
-#define bfin_write_DMA44_NEXT_DESC_PTR(val) bfin_write32(DMA44_NEXT_DESC_PTR, val)
-#define bfin_read_DMA44_START_ADDR() bfin_read32(DMA44_START_ADDR)
-#define bfin_write_DMA44_START_ADDR(val) bfin_write32(DMA44_START_ADDR, val)
-#define bfin_read_DMA44_CONFIG() bfin_read32(DMA44_CONFIG)
-#define bfin_write_DMA44_CONFIG(val) bfin_write32(DMA44_CONFIG, val)
-#define bfin_read_DMA44_X_COUNT() bfin_read32(DMA44_X_COUNT)
-#define bfin_write_DMA44_X_COUNT(val) bfin_write32(DMA44_X_COUNT, val)
-#define bfin_read_DMA44_X_MODIFY() bfin_read32(DMA44_X_MODIFY)
-#define bfin_write_DMA44_X_MODIFY(val) bfin_write32(DMA44_X_MODIFY, val)
-#define bfin_read_DMA44_Y_COUNT() bfin_read32(DMA44_Y_COUNT)
-#define bfin_write_DMA44_Y_COUNT(val) bfin_write32(DMA44_Y_COUNT, val)
-#define bfin_read_DMA44_Y_MODIFY() bfin_read32(DMA44_Y_MODIFY)
-#define bfin_write_DMA44_Y_MODIFY(val) bfin_write32(DMA44_Y_MODIFY, val)
-#define bfin_read_DMA44_CURR_DESC_PTR() bfin_read32(DMA44_CURR_DESC_PTR)
-#define bfin_write_DMA44_CURR_DESC_PTR(val) bfin_write32(DMA44_CURR_DESC_PTR, val)
-#define bfin_read_DMA44_PREV_DESC_PTR() bfin_read32(DMA44_PREV_DESC_PTR)
-#define bfin_write_DMA44_PREV_DESC_PTR(val) bfin_write32(DMA44_PREV_DESC_PTR, val)
-#define bfin_read_DMA44_CURR_ADDR() bfin_read32(DMA44_CURR_ADDR)
-#define bfin_write_DMA44_CURR_ADDR(val) bfin_write32(DMA44_CURR_ADDR, val)
-#define bfin_read_DMA44_IRQ_STATUS() bfin_read32(DMA44_IRQ_STATUS)
-#define bfin_write_DMA44_IRQ_STATUS(val) bfin_write32(DMA44_IRQ_STATUS, val)
-#define bfin_read_DMA44_CURR_X_COUNT() bfin_read32(DMA44_CURR_X_COUNT)
-#define bfin_write_DMA44_CURR_X_COUNT(val) bfin_write32(DMA44_CURR_X_COUNT, val)
-#define bfin_read_DMA44_CURR_Y_COUNT() bfin_read32(DMA44_CURR_Y_COUNT)
-#define bfin_write_DMA44_CURR_Y_COUNT(val) bfin_write32(DMA44_CURR_Y_COUNT, val)
-#define bfin_read_DMA44_BWL_COUNT() bfin_read32(DMA44_BWL_COUNT)
-#define bfin_write_DMA44_BWL_COUNT(val) bfin_write32(DMA44_BWL_COUNT, val)
-#define bfin_read_DMA44_CURR_BWL_COUNT() bfin_read32(DMA44_CURR_BWL_COUNT)
-#define bfin_write_DMA44_CURR_BWL_COUNT(val) bfin_write32(DMA44_CURR_BWL_COUNT, val)
-#define bfin_read_DMA44_BWM_COUNT() bfin_read32(DMA44_BWM_COUNT)
-#define bfin_write_DMA44_BWM_COUNT(val) bfin_write32(DMA44_BWM_COUNT, val)
-#define bfin_read_DMA44_CURR_BWM_COUNT() bfin_read32(DMA44_CURR_BWM_COUNT)
-#define bfin_write_DMA44_CURR_BWM_COUNT(val) bfin_write32(DMA44_CURR_BWM_COUNT, val)
-
-/* DMA Channel 45 Registers */
-
-#define bfin_read_DMA45_NEXT_DESC_PTR() bfin_read32(DMA45_NEXT_DESC_PTR)
-#define bfin_write_DMA45_NEXT_DESC_PTR(val) bfin_write32(DMA45_NEXT_DESC_PTR, val)
-#define bfin_read_DMA45_START_ADDR() bfin_read32(DMA45_START_ADDR)
-#define bfin_write_DMA45_START_ADDR(val) bfin_write32(DMA45_START_ADDR, val)
-#define bfin_read_DMA45_CONFIG() bfin_read32(DMA45_CONFIG)
-#define bfin_write_DMA45_CONFIG(val) bfin_write32(DMA45_CONFIG, val)
-#define bfin_read_DMA45_X_COUNT() bfin_read32(DMA45_X_COUNT)
-#define bfin_write_DMA45_X_COUNT(val) bfin_write32(DMA45_X_COUNT, val)
-#define bfin_read_DMA45_X_MODIFY() bfin_read32(DMA45_X_MODIFY)
-#define bfin_write_DMA45_X_MODIFY(val) bfin_write32(DMA45_X_MODIFY, val)
-#define bfin_read_DMA45_Y_COUNT() bfin_read32(DMA45_Y_COUNT)
-#define bfin_write_DMA45_Y_COUNT(val) bfin_write32(DMA45_Y_COUNT, val)
-#define bfin_read_DMA45_Y_MODIFY() bfin_read32(DMA45_Y_MODIFY)
-#define bfin_write_DMA45_Y_MODIFY(val) bfin_write32(DMA45_Y_MODIFY, val)
-#define bfin_read_DMA45_CURR_DESC_PTR() bfin_read32(DMA45_CURR_DESC_PTR)
-#define bfin_write_DMA45_CURR_DESC_PTR(val) bfin_write32(DMA45_CURR_DESC_PTR, val)
-#define bfin_read_DMA45_PREV_DESC_PTR() bfin_read32(DMA45_PREV_DESC_PTR)
-#define bfin_write_DMA45_PREV_DESC_PTR(val) bfin_write32(DMA45_PREV_DESC_PTR, val)
-#define bfin_read_DMA45_CURR_ADDR() bfin_read32(DMA45_CURR_ADDR)
-#define bfin_write_DMA45_CURR_ADDR(val) bfin_write32(DMA45_CURR_ADDR, val)
-#define bfin_read_DMA45_IRQ_STATUS() bfin_read32(DMA45_IRQ_STATUS)
-#define bfin_write_DMA45_IRQ_STATUS(val) bfin_write32(DMA45_IRQ_STATUS, val)
-#define bfin_read_DMA45_CURR_X_COUNT() bfin_read32(DMA45_CURR_X_COUNT)
-#define bfin_write_DMA45_CURR_X_COUNT(val) bfin_write32(DMA45_CURR_X_COUNT, val)
-#define bfin_read_DMA45_CURR_Y_COUNT() bfin_read32(DMA45_CURR_Y_COUNT)
-#define bfin_write_DMA45_CURR_Y_COUNT(val) bfin_write32(DMA45_CURR_Y_COUNT, val)
-#define bfin_read_DMA45_BWL_COUNT() bfin_read32(DMA45_BWL_COUNT)
-#define bfin_write_DMA45_BWL_COUNT(val) bfin_write32(DMA45_BWL_COUNT, val)
-#define bfin_read_DMA45_CURR_BWL_COUNT() bfin_read32(DMA45_CURR_BWL_COUNT)
-#define bfin_write_DMA45_CURR_BWL_COUNT(val) bfin_write32(DMA45_CURR_BWL_COUNT, val)
-#define bfin_read_DMA45_BWM_COUNT() bfin_read32(DMA45_BWM_COUNT)
-#define bfin_write_DMA45_BWM_COUNT(val) bfin_write32(DMA45_BWM_COUNT, val)
-#define bfin_read_DMA45_CURR_BWM_COUNT() bfin_read32(DMA45_CURR_BWM_COUNT)
-#define bfin_write_DMA45_CURR_BWM_COUNT(val) bfin_write32(DMA45_CURR_BWM_COUNT, val)
-
-/* DMA Channel 46 Registers */
-
-#define bfin_read_DMA46_NEXT_DESC_PTR() bfin_read32(DMA46_NEXT_DESC_PTR)
-#define bfin_write_DMA46_NEXT_DESC_PTR(val) bfin_write32(DMA46_NEXT_DESC_PTR, val)
-#define bfin_read_DMA46_START_ADDR() bfin_read32(DMA46_START_ADDR)
-#define bfin_write_DMA46_START_ADDR(val) bfin_write32(DMA46_START_ADDR, val)
-#define bfin_read_DMA46_CONFIG() bfin_read32(DMA46_CONFIG)
-#define bfin_write_DMA46_CONFIG(val) bfin_write32(DMA46_CONFIG, val)
-#define bfin_read_DMA46_X_COUNT() bfin_read32(DMA46_X_COUNT)
-#define bfin_write_DMA46_X_COUNT(val) bfin_write32(DMA46_X_COUNT, val)
-#define bfin_read_DMA46_X_MODIFY() bfin_read32(DMA46_X_MODIFY)
-#define bfin_write_DMA46_X_MODIFY(val) bfin_write32(DMA46_X_MODIFY, val)
-#define bfin_read_DMA46_Y_COUNT() bfin_read32(DMA46_Y_COUNT)
-#define bfin_write_DMA46_Y_COUNT(val) bfin_write32(DMA46_Y_COUNT, val)
-#define bfin_read_DMA46_Y_MODIFY() bfin_read32(DMA46_Y_MODIFY)
-#define bfin_write_DMA46_Y_MODIFY(val) bfin_write32(DMA46_Y_MODIFY, val)
-#define bfin_read_DMA46_CURR_DESC_PTR() bfin_read32(DMA46_CURR_DESC_PTR)
-#define bfin_write_DMA46_CURR_DESC_PTR(val) bfin_write32(DMA46_CURR_DESC_PTR, val)
-#define bfin_read_DMA46_PREV_DESC_PTR() bfin_read32(DMA46_PREV_DESC_PTR)
-#define bfin_write_DMA46_PREV_DESC_PTR(val) bfin_write32(DMA46_PREV_DESC_PTR, val)
-#define bfin_read_DMA46_CURR_ADDR() bfin_read32(DMA46_CURR_ADDR)
-#define bfin_write_DMA46_CURR_ADDR(val) bfin_write32(DMA46_CURR_ADDR, val)
-#define bfin_read_DMA46_IRQ_STATUS() bfin_read32(DMA46_IRQ_STATUS)
-#define bfin_write_DMA46_IRQ_STATUS(val) bfin_write32(DMA46_IRQ_STATUS, val)
-#define bfin_read_DMA46_CURR_X_COUNT() bfin_read32(DMA46_CURR_X_COUNT)
-#define bfin_write_DMA46_CURR_X_COUNT(val) bfin_write32(DMA46_CURR_X_COUNT, val)
-#define bfin_read_DMA46_CURR_Y_COUNT() bfin_read32(DMA46_CURR_Y_COUNT)
-#define bfin_write_DMA46_CURR_Y_COUNT(val) bfin_write32(DMA46_CURR_Y_COUNT, val)
-#define bfin_read_DMA46_BWL_COUNT() bfin_read32(DMA46_BWL_COUNT)
-#define bfin_write_DMA46_BWL_COUNT(val) bfin_write32(DMA46_BWL_COUNT, val)
-#define bfin_read_DMA46_CURR_BWL_COUNT() bfin_read32(DMA46_CURR_BWL_COUNT)
-#define bfin_write_DMA46_CURR_BWL_COUNT(val) bfin_write32(DMA46_CURR_BWL_COUNT, val)
-#define bfin_read_DMA46_BWM_COUNT() bfin_read32(DMA46_BWM_COUNT)
-#define bfin_write_DMA46_BWM_COUNT(val) bfin_write32(DMA46_BWM_COUNT, val)
-#define bfin_read_DMA46_CURR_BWM_COUNT() bfin_read32(DMA46_CURR_BWM_COUNT)
-#define bfin_write_DMA46_CURR_BWM_COUNT(val) bfin_write32(DMA46_CURR_BWM_COUNT, val)
-
-
-/* EPPI1 Registers */
-
-
-/* Port Interrubfin_read_()t 0 Registers (32-bit) */
-
-#define bfin_read_PINT0_MASK_SET() bfin_read32(PINT0_MASK_SET)
-#define bfin_write_PINT0_MASK_SET(val) bfin_write32(PINT0_MASK_SET, val)
-#define bfin_read_PINT0_MASK_CLEAR() bfin_read32(PINT0_MASK_CLEAR)
-#define bfin_write_PINT0_MASK_CLEAR(val) bfin_write32(PINT0_MASK_CLEAR, val)
-#define bfin_read_PINT0_REQUEST() bfin_read32(PINT0_REQUEST)
-#define bfin_write_PINT0_REQUEST(val) bfin_write32(PINT0_REQUEST, val)
-#define bfin_read_PINT0_ASSIGN() bfin_read32(PINT0_ASSIGN)
-#define bfin_write_PINT0_ASSIGN(val) bfin_write32(PINT0_ASSIGN, val)
-#define bfin_read_PINT0_EDGE_SET() bfin_read32(PINT0_EDGE_SET)
-#define bfin_write_PINT0_EDGE_SET(val) bfin_write32(PINT0_EDGE_SET, val)
-#define bfin_read_PINT0_EDGE_CLEAR() bfin_read32(PINT0_EDGE_CLEAR)
-#define bfin_write_PINT0_EDGE_CLEAR(val) bfin_write32(PINT0_EDGE_CLEAR, val)
-#define bfin_read_PINT0_INVERT_SET() bfin_read32(PINT0_INVERT_SET)
-#define bfin_write_PINT0_INVERT_SET(val) bfin_write32(PINT0_INVERT_SET, val)
-#define bfin_read_PINT0_INVERT_CLEAR() bfin_read32(PINT0_INVERT_CLEAR)
-#define bfin_write_PINT0_INVERT_CLEAR(val) bfin_write32(PINT0_INVERT_CLEAR, val)
-#define bfin_read_PINT0_PINSTATE() bfin_read32(PINT0_PINSTATE)
-#define bfin_write_PINT0_PINSTATE(val) bfin_write32(PINT0_PINSTATE, val)
-#define bfin_read_PINT0_LATCH() bfin_read32(PINT0_LATCH)
-#define bfin_write_PINT0_LATCH(val) bfin_write32(PINT0_LATCH, val)
-
-/* Port Interrubfin_read_()t 1 Registers (32-bit) */
-
-#define bfin_read_PINT1_MASK_SET() bfin_read32(PINT1_MASK_SET)
-#define bfin_write_PINT1_MASK_SET(val) bfin_write32(PINT1_MASK_SET, val)
-#define bfin_read_PINT1_MASK_CLEAR() bfin_read32(PINT1_MASK_CLEAR)
-#define bfin_write_PINT1_MASK_CLEAR(val) bfin_write32(PINT1_MASK_CLEAR, val)
-#define bfin_read_PINT1_REQUEST() bfin_read32(PINT1_REQUEST)
-#define bfin_write_PINT1_REQUEST(val) bfin_write32(PINT1_REQUEST, val)
-#define bfin_read_PINT1_ASSIGN() bfin_read32(PINT1_ASSIGN)
-#define bfin_write_PINT1_ASSIGN(val) bfin_write32(PINT1_ASSIGN, val)
-#define bfin_read_PINT1_EDGE_SET() bfin_read32(PINT1_EDGE_SET)
-#define bfin_write_PINT1_EDGE_SET(val) bfin_write32(PINT1_EDGE_SET, val)
-#define bfin_read_PINT1_EDGE_CLEAR() bfin_read32(PINT1_EDGE_CLEAR)
-#define bfin_write_PINT1_EDGE_CLEAR(val) bfin_write32(PINT1_EDGE_CLEAR, val)
-#define bfin_read_PINT1_INVERT_SET() bfin_read32(PINT1_INVERT_SET)
-#define bfin_write_PINT1_INVERT_SET(val) bfin_write32(PINT1_INVERT_SET, val)
-#define bfin_read_PINT1_INVERT_CLEAR() bfin_read32(PINT1_INVERT_CLEAR)
-#define bfin_write_PINT1_INVERT_CLEAR(val) bfin_write32(PINT1_INVERT_CLEAR, val)
-#define bfin_read_PINT1_PINSTATE() bfin_read32(PINT1_PINSTATE)
-#define bfin_write_PINT1_PINSTATE(val) bfin_write32(PINT1_PINSTATE, val)
-#define bfin_read_PINT1_LATCH() bfin_read32(PINT1_LATCH)
-#define bfin_write_PINT1_LATCH(val) bfin_write32(PINT1_LATCH, val)
-
-/* Port Interrubfin_read_()t 2 Registers (32-bit) */
-
-#define bfin_read_PINT2_MASK_SET() bfin_read32(PINT2_MASK_SET)
-#define bfin_write_PINT2_MASK_SET(val) bfin_write32(PINT2_MASK_SET, val)
-#define bfin_read_PINT2_MASK_CLEAR() bfin_read32(PINT2_MASK_CLEAR)
-#define bfin_write_PINT2_MASK_CLEAR(val) bfin_write32(PINT2_MASK_CLEAR, val)
-#define bfin_read_PINT2_REQUEST() bfin_read32(PINT2_REQUEST)
-#define bfin_write_PINT2_REQUEST(val) bfin_write32(PINT2_REQUEST, val)
-#define bfin_read_PINT2_ASSIGN() bfin_read32(PINT2_ASSIGN)
-#define bfin_write_PINT2_ASSIGN(val) bfin_write32(PINT2_ASSIGN, val)
-#define bfin_read_PINT2_EDGE_SET() bfin_read32(PINT2_EDGE_SET)
-#define bfin_write_PINT2_EDGE_SET(val) bfin_write32(PINT2_EDGE_SET, val)
-#define bfin_read_PINT2_EDGE_CLEAR() bfin_read32(PINT2_EDGE_CLEAR)
-#define bfin_write_PINT2_EDGE_CLEAR(val) bfin_write32(PINT2_EDGE_CLEAR, val)
-#define bfin_read_PINT2_INVERT_SET() bfin_read32(PINT2_INVERT_SET)
-#define bfin_write_PINT2_INVERT_SET(val) bfin_write32(PINT2_INVERT_SET, val)
-#define bfin_read_PINT2_INVERT_CLEAR() bfin_read32(PINT2_INVERT_CLEAR)
-#define bfin_write_PINT2_INVERT_CLEAR(val) bfin_write32(PINT2_INVERT_CLEAR, val)
-#define bfin_read_PINT2_PINSTATE() bfin_read32(PINT2_PINSTATE)
-#define bfin_write_PINT2_PINSTATE(val) bfin_write32(PINT2_PINSTATE, val)
-#define bfin_read_PINT2_LATCH() bfin_read32(PINT2_LATCH)
-#define bfin_write_PINT2_LATCH(val) bfin_write32(PINT2_LATCH, val)
-
-/* Port Interrubfin_read_()t 3 Registers (32-bit) */
-
-#define bfin_read_PINT3_MASK_SET() bfin_read32(PINT3_MASK_SET)
-#define bfin_write_PINT3_MASK_SET(val) bfin_write32(PINT3_MASK_SET, val)
-#define bfin_read_PINT3_MASK_CLEAR() bfin_read32(PINT3_MASK_CLEAR)
-#define bfin_write_PINT3_MASK_CLEAR(val) bfin_write32(PINT3_MASK_CLEAR, val)
-#define bfin_read_PINT3_REQUEST() bfin_read32(PINT3_REQUEST)
-#define bfin_write_PINT3_REQUEST(val) bfin_write32(PINT3_REQUEST, val)
-#define bfin_read_PINT3_ASSIGN() bfin_read32(PINT3_ASSIGN)
-#define bfin_write_PINT3_ASSIGN(val) bfin_write32(PINT3_ASSIGN, val)
-#define bfin_read_PINT3_EDGE_SET() bfin_read32(PINT3_EDGE_SET)
-#define bfin_write_PINT3_EDGE_SET(val) bfin_write32(PINT3_EDGE_SET, val)
-#define bfin_read_PINT3_EDGE_CLEAR() bfin_read32(PINT3_EDGE_CLEAR)
-#define bfin_write_PINT3_EDGE_CLEAR(val) bfin_write32(PINT3_EDGE_CLEAR, val)
-#define bfin_read_PINT3_INVERT_SET() bfin_read32(PINT3_INVERT_SET)
-#define bfin_write_PINT3_INVERT_SET(val) bfin_write32(PINT3_INVERT_SET, val)
-#define bfin_read_PINT3_INVERT_CLEAR() bfin_read32(PINT3_INVERT_CLEAR)
-#define bfin_write_PINT3_INVERT_CLEAR(val) bfin_write32(PINT3_INVERT_CLEAR, val)
-#define bfin_read_PINT3_PINSTATE() bfin_read32(PINT3_PINSTATE)
-#define bfin_write_PINT3_PINSTATE(val) bfin_write32(PINT3_PINSTATE, val)
-#define bfin_read_PINT3_LATCH() bfin_read32(PINT3_LATCH)
-#define bfin_write_PINT3_LATCH(val) bfin_write32(PINT3_LATCH, val)
-
-/* Port Interrubfin_read_()t 4 Registers (32-bit) */
-
-#define bfin_read_PINT4_MASK_SET() bfin_read32(PINT4_MASK_SET)
-#define bfin_write_PINT4_MASK_SET(val) bfin_write32(PINT4_MASK_SET, val)
-#define bfin_read_PINT4_MASK_CLEAR() bfin_read32(PINT4_MASK_CLEAR)
-#define bfin_write_PINT4_MASK_CLEAR(val) bfin_write32(PINT4_MASK_CLEAR, val)
-#define bfin_read_PINT4_REQUEST() bfin_read32(PINT4_REQUEST)
-#define bfin_write_PINT4_REQUEST(val) bfin_write32(PINT4_REQUEST, val)
-#define bfin_read_PINT4_ASSIGN() bfin_read32(PINT4_ASSIGN)
-#define bfin_write_PINT4_ASSIGN(val) bfin_write32(PINT4_ASSIGN, val)
-#define bfin_read_PINT4_EDGE_SET() bfin_read32(PINT4_EDGE_SET)
-#define bfin_write_PINT4_EDGE_SET(val) bfin_write32(PINT4_EDGE_SET, val)
-#define bfin_read_PINT4_EDGE_CLEAR() bfin_read32(PINT4_EDGE_CLEAR)
-#define bfin_write_PINT4_EDGE_CLEAR(val) bfin_write32(PINT4_EDGE_CLEAR, val)
-#define bfin_read_PINT4_INVERT_SET() bfin_read32(PINT4_INVERT_SET)
-#define bfin_write_PINT4_INVERT_SET(val) bfin_write32(PINT4_INVERT_SET, val)
-#define bfin_read_PINT4_INVERT_CLEAR() bfin_read32(PINT4_INVERT_CLEAR)
-#define bfin_write_PINT4_INVERT_CLEAR(val) bfin_write32(PINT4_INVERT_CLEAR, val)
-#define bfin_read_PINT4_PINSTATE() bfin_read32(PINT4_PINSTATE)
-#define bfin_write_PINT4_PINSTATE(val) bfin_write32(PINT4_PINSTATE, val)
-#define bfin_read_PINT4_LATCH() bfin_read32(PINT4_LATCH)
-#define bfin_write_PINT4_LATCH(val) bfin_write32(PINT4_LATCH, val)
-
-/* Port Interrubfin_read_()t 5 Registers (32-bit) */
-
-#define bfin_read_PINT5_MASK_SET() bfin_read32(PINT5_MASK_SET)
-#define bfin_write_PINT5_MASK_SET(val) bfin_write32(PINT5_MASK_SET, val)
-#define bfin_read_PINT5_MASK_CLEAR() bfin_read32(PINT5_MASK_CLEAR)
-#define bfin_write_PINT5_MASK_CLEAR(val) bfin_write32(PINT5_MASK_CLEAR, val)
-#define bfin_read_PINT5_REQUEST() bfin_read32(PINT5_REQUEST)
-#define bfin_write_PINT5_REQUEST(val) bfin_write32(PINT5_REQUEST, val)
-#define bfin_read_PINT5_ASSIGN() bfin_read32(PINT5_ASSIGN)
-#define bfin_write_PINT5_ASSIGN(val) bfin_write32(PINT5_ASSIGN, val)
-#define bfin_read_PINT5_EDGE_SET() bfin_read32(PINT5_EDGE_SET)
-#define bfin_write_PINT5_EDGE_SET(val) bfin_write32(PINT5_EDGE_SET, val)
-#define bfin_read_PINT5_EDGE_CLEAR() bfin_read32(PINT5_EDGE_CLEAR)
-#define bfin_write_PINT5_EDGE_CLEAR(val) bfin_write32(PINT5_EDGE_CLEAR, val)
-#define bfin_read_PINT5_INVERT_SET() bfin_read32(PINT5_INVERT_SET)
-#define bfin_write_PINT5_INVERT_SET(val) bfin_write32(PINT5_INVERT_SET, val)
-#define bfin_read_PINT5_INVERT_CLEAR() bfin_read32(PINT5_INVERT_CLEAR)
-#define bfin_write_PINT5_INVERT_CLEAR(val) bfin_write32(PINT5_INVERT_CLEAR, val)
-#define bfin_read_PINT5_PINSTATE() bfin_read32(PINT5_PINSTATE)
-#define bfin_write_PINT5_PINSTATE(val) bfin_write32(PINT5_PINSTATE, val)
-#define bfin_read_PINT5_LATCH() bfin_read32(PINT5_LATCH)
-#define bfin_write_PINT5_LATCH(val) bfin_write32(PINT5_LATCH, val)
-
-/* Port A Registers */
-
-#define bfin_read_PORTA_FER() bfin_read32(PORTA_FER)
-#define bfin_write_PORTA_FER(val) bfin_write32(PORTA_FER, val)
-#define bfin_read_PORTA_FER_SET() bfin_read32(PORTA_FER_SET)
-#define bfin_write_PORTA_FER_SET(val) bfin_write32(PORTA_FER_SET, val)
-#define bfin_read_PORTA_FER_CLEAR() bfin_read32(PORTA_FER_CLEAR)
-#define bfin_write_PORTA_FER_CLEAR(val) bfin_write32(PORTA_FER_CLEAR, val)
-#define bfin_read_PORTA() bfin_read32(PORTA)
-#define bfin_write_PORTA(val) bfin_write32(PORTA, val)
-#define bfin_read_PORTA_SET() bfin_read32(PORTA_SET)
-#define bfin_write_PORTA_SET(val) bfin_write32(PORTA_SET, val)
-#define bfin_read_PORTA_CLEAR() bfin_read32(PORTA_CLEAR)
-#define bfin_write_PORTA_CLEAR(val) bfin_write32(PORTA_CLEAR, val)
-#define bfin_read_PORTA_DIR() bfin_read32(PORTA_DIR)
-#define bfin_write_PORTA_DIR(val) bfin_write32(PORTA_DIR, val)
-#define bfin_read_PORTA_DIR_SET() bfin_read32(PORTA_DIR_SET)
-#define bfin_write_PORTA_DIR_SET(val) bfin_write32(PORTA_DIR_SET, val)
-#define bfin_read_PORTA_DIR_CLEAR() bfin_read32(PORTA_DIR_CLEAR)
-#define bfin_write_PORTA_DIR_CLEAR(val) bfin_write32(PORTA_DIR_CLEAR, val)
-#define bfin_read_PORTA_INEN() bfin_read32(PORTA_INEN)
-#define bfin_write_PORTA_INEN(val) bfin_write32(PORTA_INEN, val)
-#define bfin_read_PORTA_INEN_SET() bfin_read32(PORTA_INEN_SET)
-#define bfin_write_PORTA_INEN_SET(val) bfin_write32(PORTA_INEN_SET, val)
-#define bfin_read_PORTA_INEN_CLEAR() bfin_read32(PORTA_INEN_CLEAR)
-#define bfin_write_PORTA_INEN_CLEAR(val) bfin_write32(PORTA_INEN_CLEAR, val)
-#define bfin_read_PORTA_MUX() bfin_read32(PORTA_MUX)
-#define bfin_write_PORTA_MUX(val) bfin_write32(PORTA_MUX, val)
-#define bfin_read_PORTA_DATA_TGL() bfin_read32(PORTA_DATA_TGL)
-#define bfin_write_PORTA_DATA_TGL(val) bfin_write32(PORTA_DATA_TGL, val)
-#define bfin_read_PORTA_POL() bfin_read32(PORTA_POL)
-#define bfin_write_PORTA_POL(val) bfin_write32(PORTA_POL, val)
-#define bfin_read_PORTA_POL_SET() bfin_read32(PORTA_POL_SET)
-#define bfin_write_PORTA_POL_SET(val) bfin_write32(PORTA_POL_SET, val)
-#define bfin_read_PORTA_POL_CLEAR() bfin_read32(PORTA_POL_CLEAR)
-#define bfin_write_PORTA_POL_CLEAR(val) bfin_write32(PORTA_POL_CLEAR, val)
-#define bfin_read_PORTA_LOCK() bfin_read32(PORTA_LOCK)
-#define bfin_write_PORTA_LOCK(val) bfin_write32(PORTA_LOCK, val)
-#define bfin_read_PORTA_REVID() bfin_read32(PORTA_REVID)
-#define bfin_write_PORTA_REVID(val) bfin_write32(PORTA_REVID, val)
-
-
-
-/* Port B Registers */
-#define bfin_read_PORTB_FER() bfin_read32(PORTB_FER)
-#define bfin_write_PORTB_FER(val) bfin_write32(PORTB_FER, val)
-#define bfin_read_PORTB_FER_SET() bfin_read32(PORTB_FER_SET)
-#define bfin_write_PORTB_FER_SET(val) bfin_write32(PORTB_FER_SET, val)
-#define bfin_read_PORTB_FER_CLEAR() bfin_read32(PORTB_FER_CLEAR)
-#define bfin_write_PORTB_FER_CLEAR(val) bfin_write32(PORTB_FER_CLEAR, val)
-#define bfin_read_PORTB() bfin_read32(PORTB)
-#define bfin_write_PORTB(val) bfin_write32(PORTB, val)
-#define bfin_read_PORTB_SET() bfin_read32(PORTB_SET)
-#define bfin_write_PORTB_SET(val) bfin_write32(PORTB_SET, val)
-#define bfin_read_PORTB_CLEAR() bfin_read32(PORTB_CLEAR)
-#define bfin_write_PORTB_CLEAR(val) bfin_write32(PORTB_CLEAR, val)
-#define bfin_read_PORTB_DIR() bfin_read32(PORTB_DIR)
-#define bfin_write_PORTB_DIR(val) bfin_write32(PORTB_DIR, val)
-#define bfin_read_PORTB_DIR_SET() bfin_read32(PORTB_DIR_SET)
-#define bfin_write_PORTB_DIR_SET(val) bfin_write32(PORTB_DIR_SET, val)
-#define bfin_read_PORTB_DIR_CLEAR() bfin_read32(PORTB_DIR_CLEAR)
-#define bfin_write_PORTB_DIR_CLEAR(val) bfin_write32(PORTB_DIR_CLEAR, val)
-#define bfin_read_PORTB_INEN() bfin_read32(PORTB_INEN)
-#define bfin_write_PORTB_INEN(val) bfin_write32(PORTB_INEN, val)
-#define bfin_read_PORTB_INEN_SET() bfin_read32(PORTB_INEN_SET)
-#define bfin_write_PORTB_INEN_SET(val) bfin_write32(PORTB_INEN_SET, val)
-#define bfin_read_PORTB_INEN_CLEAR() bfin_read32(PORTB_INEN_CLEAR)
-#define bfin_write_PORTB_INEN_CLEAR(val) bfin_write32(PORTB_INEN_CLEAR, val)
-#define bfin_read_PORTB_MUX() bfin_read32(PORTB_MUX)
-#define bfin_write_PORTB_MUX(val) bfin_write32(PORTB_MUX, val)
-#define bfin_read_PORTB_DATA_TGL() bfin_read32(PORTB_DATA_TGL)
-#define bfin_write_PORTB_DATA_TGL(val) bfin_write32(PORTB_DATA_TGL, val)
-#define bfin_read_PORTB_POL() bfin_read32(PORTB_POL)
-#define bfin_write_PORTB_POL(val) bfin_write32(PORTB_POL, val)
-#define bfin_read_PORTB_POL_SET() bfin_read32(PORTB_POL_SET)
-#define bfin_write_PORTB_POL_SET(val) bfin_write32(PORTB_POL_SET, val)
-#define bfin_read_PORTB_POL_CLEAR() bfin_read32(PORTB_POL_CLEAR)
-#define bfin_write_PORTB_POL_CLEAR(val) bfin_write32(PORTB_POL_CLEAR, val)
-#define bfin_read_PORTB_LOCK() bfin_read32(PORTB_LOCK)
-#define bfin_write_PORTB_LOCK(val) bfin_write32(PORTB_LOCK, val)
-#define bfin_read_PORTB_REVID() bfin_read32(PORTB_REVID)
-#define bfin_write_PORTB_REVID(val) bfin_write32(PORTB_REVID, val)
-
-
-/* Port C Registers */
-#define bfin_read_PORTC_FER() bfin_read32(PORTC_FER)
-#define bfin_write_PORTC_FER(val) bfin_write32(PORTC_FER, val)
-#define bfin_read_PORTC_FER_SET() bfin_read32(PORTC_FER_SET)
-#define bfin_write_PORTC_FER_SET(val) bfin_write32(PORTC_FER_SET, val)
-#define bfin_read_PORTC_FER_CLEAR() bfin_read32(PORTC_FER_CLEAR)
-#define bfin_write_PORTC_FER_CLEAR(val) bfin_write32(PORTC_FER_CLEAR, val)
-#define bfin_read_PORTC() bfin_read32(PORTC)
-#define bfin_write_PORTC(val) bfin_write32(PORTC, val)
-#define bfin_read_PORTC_SET() bfin_read32(PORTC_SET)
-#define bfin_write_PORTC_SET(val) bfin_write32(PORTC_SET, val)
-#define bfin_read_PORTC_CLEAR() bfin_read32(PORTC_CLEAR)
-#define bfin_write_PORTC_CLEAR(val) bfin_write32(PORTC_CLEAR, val)
-#define bfin_read_PORTC_DIR() bfin_read32(PORTC_DIR)
-#define bfin_write_PORTC_DIR(val) bfin_write32(PORTC_DIR, val)
-#define bfin_read_PORTC_DIR_SET() bfin_read32(PORTC_DIR_SET)
-#define bfin_write_PORTC_DIR_SET(val) bfin_write32(PORTC_DIR_SET, val)
-#define bfin_read_PORTC_DIR_CLEAR() bfin_read32(PORTC_DIR_CLEAR)
-#define bfin_write_PORTC_DIR_CLEAR(val) bfin_write32(PORTC_DIR_CLEAR, val)
-#define bfin_read_PORTC_INEN() bfin_read32(PORTC_INEN)
-#define bfin_write_PORTC_INEN(val) bfin_write32(PORTC_INEN, val)
-#define bfin_read_PORTC_INEN_SET() bfin_read32(PORTC_INEN_SET)
-#define bfin_write_PORTC_INEN_SET(val) bfin_write32(PORTC_INEN_SET, val)
-#define bfin_read_PORTC_INEN_CLEAR() bfin_read32(PORTC_INEN_CLEAR)
-#define bfin_write_PORTC_INEN_CLEAR(val) bfin_write32(PORTC_INEN_CLEAR, val)
-#define bfin_read_PORTC_MUX() bfin_read32(PORTC_MUX)
-#define bfin_write_PORTC_MUX(val) bfin_write32(PORTC_MUX, val)
-#define bfin_read_PORTC_DATA_TGL() bfin_read32(PORTC_DATA_TGL)
-#define bfin_write_PORTC_DATA_TGL(val) bfin_write32(PORTC_DATA_TGL, val)
-#define bfin_read_PORTC_POL() bfin_read32(PORTC_POL)
-#define bfin_write_PORTC_POL(val) bfin_write32(PORTC_POL, val)
-#define bfin_read_PORTC_POL_SET() bfin_read32(PORTC_POL_SET)
-#define bfin_write_PORTC_POL_SET(val) bfin_write32(PORTC_POL_SET, val)
-#define bfin_read_PORTC_POL_CLEAR() bfin_read32(PORTC_POL_CLEAR)
-#define bfin_write_PORTC_POL_CLEAR(val) bfin_write32(PORTC_POL_CLEAR, val)
-#define bfin_read_PORTC_LOCK() bfin_read32(PORTC_LOCK)
-#define bfin_write_PORTC_LOCK(val) bfin_write32(PORTC_LOCK, val)
-#define bfin_read_PORTC_REVID() bfin_read32(PORTC_REVID)
-#define bfin_write_PORTC_REVID(val) bfin_write32(PORTC_REVID, val)
-
-
-/* Port D Registers */
-#define bfin_read_PORTD_FER() bfin_read32(PORTD_FER)
-#define bfin_write_PORTD_FER(val) bfin_write32(PORTD_FER, val)
-#define bfin_read_PORTD_FER_SET() bfin_read32(PORTD_FER_SET)
-#define bfin_write_PORTD_FER_SET(val) bfin_write32(PORTD_FER_SET, val)
-#define bfin_read_PORTD_FER_CLEAR() bfin_read32(PORTD_FER_CLEAR)
-#define bfin_write_PORTD_FER_CLEAR(val) bfin_write32(PORTD_FER_CLEAR, val)
-#define bfin_read_PORTD() bfin_read32(PORTD)
-#define bfin_write_PORTD(val) bfin_write32(PORTD, val)
-#define bfin_read_PORTD_SET() bfin_read32(PORTD_SET)
-#define bfin_write_PORTD_SET(val) bfin_write32(PORTD_SET, val)
-#define bfin_read_PORTD_CLEAR() bfin_read32(PORTD_CLEAR)
-#define bfin_write_PORTD_CLEAR(val) bfin_write32(PORTD_CLEAR, val)
-#define bfin_read_PORTD_DIR() bfin_read32(PORTD_DIR)
-#define bfin_write_PORTD_DIR(val) bfin_write32(PORTD_DIR, val)
-#define bfin_read_PORTD_DIR_SET() bfin_read32(PORTD_DIR_SET)
-#define bfin_write_PORTD_DIR_SET(val) bfin_write32(PORTD_DIR_SET, val)
-#define bfin_read_PORTD_DIR_CLEAR() bfin_read32(PORTD_DIR_CLEAR)
-#define bfin_write_PORTD_DIR_CLEAR(val) bfin_write32(PORTD_DIR_CLEAR, val)
-#define bfin_read_PORTD_INEN() bfin_read32(PORTD_INEN)
-#define bfin_write_PORTD_INEN(val) bfin_write32(PORTD_INEN, val)
-#define bfin_read_PORTD_INEN_SET() bfin_read32(PORTD_INEN_SET)
-#define bfin_write_PORTD_INEN_SET(val) bfin_write32(PORTD_INEN_SET, val)
-#define bfin_read_PORTD_INEN_CLEAR() bfin_read32(PORTD_INEN_CLEAR)
-#define bfin_write_PORTD_INEN_CLEAR(val) bfin_write32(PORTD_INEN_CLEAR, val)
-#define bfin_read_PORTD_MUX() bfin_read32(PORTD_MUX)
-#define bfin_write_PORTD_MUX(val) bfin_write32(PORTD_MUX, val)
-#define bfin_read_PORTD_DATA_TGL() bfin_read32(PORTD_DATA_TGL)
-#define bfin_write_PORTD_DATA_TGL(val) bfin_write32(PORTD_DATA_TGL, val)
-#define bfin_read_PORTD_POL() bfin_read32(PORTD_POL)
-#define bfin_write_PORTD_POL(val) bfin_write32(PORTD_POL, val)
-#define bfin_read_PORTD_POL_SET() bfin_read32(PORTD_POL_SET)
-#define bfin_write_PORTD_POL_SET(val) bfin_write32(PORTD_POL_SET, val)
-#define bfin_read_PORTD_POL_CLEAR() bfin_read32(PORTD_POL_CLEAR)
-#define bfin_write_PORTD_POL_CLEAR(val) bfin_write32(PORTD_POL_CLEAR, val)
-#define bfin_read_PORTD_LOCK() bfin_read32(PORTD_LOCK)
-#define bfin_write_PORTD_LOCK(val) bfin_write32(PORTD_LOCK, val)
-#define bfin_read_PORTD_REVID() bfin_read32(PORTD_REVID)
-#define bfin_write_PORTD_REVID(val) bfin_write32(PORTD_REVID, val)
-
-
-/* Port E Registers */
-#define bfin_read_PORTE_FER() bfin_read32(PORTE_FER)
-#define bfin_write_PORTE_FER(val) bfin_write32(PORTE_FER, val)
-#define bfin_read_PORTE_FER_SET() bfin_read32(PORTE_FER_SET)
-#define bfin_write_PORTE_FER_SET(val) bfin_write32(PORTE_FER_SET, val)
-#define bfin_read_PORTE_FER_CLEAR() bfin_read32(PORTE_FER_CLEAR)
-#define bfin_write_PORTE_FER_CLEAR(val) bfin_write32(PORTE_FER_CLEAR, val)
-#define bfin_read_PORTE() bfin_read32(PORTE)
-#define bfin_write_PORTE(val) bfin_write32(PORTE, val)
-#define bfin_read_PORTE_SET() bfin_read32(PORTE_SET)
-#define bfin_write_PORTE_SET(val) bfin_write32(PORTE_SET, val)
-#define bfin_read_PORTE_CLEAR() bfin_read32(PORTE_CLEAR)
-#define bfin_write_PORTE_CLEAR(val) bfin_write32(PORTE_CLEAR, val)
-#define bfin_read_PORTE_DIR() bfin_read32(PORTE_DIR)
-#define bfin_write_PORTE_DIR(val) bfin_write32(PORTE_DIR, val)
-#define bfin_read_PORTE_DIR_SET() bfin_read32(PORTE_DIR_SET)
-#define bfin_write_PORTE_DIR_SET(val) bfin_write32(PORTE_DIR_SET, val)
-#define bfin_read_PORTE_DIR_CLEAR() bfin_read32(PORTE_DIR_CLEAR)
-#define bfin_write_PORTE_DIR_CLEAR(val) bfin_write32(PORTE_DIR_CLEAR, val)
-#define bfin_read_PORTE_INEN() bfin_read32(PORTE_INEN)
-#define bfin_write_PORTE_INEN(val) bfin_write32(PORTE_INEN, val)
-#define bfin_read_PORTE_INEN_SET() bfin_read32(PORTE_INEN_SET)
-#define bfin_write_PORTE_INEN_SET(val) bfin_write32(PORTE_INEN_SET, val)
-#define bfin_read_PORTE_INEN_CLEAR() bfin_read32(PORTE_INEN_CLEAR)
-#define bfin_write_PORTE_INEN_CLEAR(val) bfin_write32(PORTE_INEN_CLEAR, val)
-#define bfin_read_PORTE_MUX() bfin_read32(PORTE_MUX)
-#define bfin_write_PORTE_MUX(val) bfin_write32(PORTE_MUX, val)
-#define bfin_read_PORTE_DATA_TGL() bfin_read32(PORTE_DATA_TGL)
-#define bfin_write_PORTE_DATA_TGL(val) bfin_write32(PORTE_DATA_TGL, val)
-#define bfin_read_PORTE_POL() bfin_read32(PORTE_POL)
-#define bfin_write_PORTE_POL(val) bfin_write32(PORTE_POL, val)
-#define bfin_read_PORTE_POL_SET() bfin_read32(PORTE_POL_SET)
-#define bfin_write_PORTE_POL_SET(val) bfin_write32(PORTE_POL_SET, val)
-#define bfin_read_PORTE_POL_CLEAR() bfin_read32(PORTE_POL_CLEAR)
-#define bfin_write_PORTE_POL_CLEAR(val) bfin_write32(PORTE_POL_CLEAR, val)
-#define bfin_read_PORTE_LOCK() bfin_read32(PORTE_LOCK)
-#define bfin_write_PORTE_LOCK(val) bfin_write32(PORTE_LOCK, val)
-#define bfin_read_PORTE_REVID() bfin_read32(PORTE_REVID)
-#define bfin_write_PORTE_REVID(val) bfin_write32(PORTE_REVID, val)
-
-
-/* Port F Registers */
-#define bfin_read_PORTF_FER() bfin_read32(PORTF_FER)
-#define bfin_write_PORTF_FER(val) bfin_write32(PORTF_FER, val)
-#define bfin_read_PORTF_FER_SET() bfin_read32(PORTF_FER_SET)
-#define bfin_write_PORTF_FER_SET(val) bfin_write32(PORTF_FER_SET, val)
-#define bfin_read_PORTF_FER_CLEAR() bfin_read32(PORTF_FER_CLEAR)
-#define bfin_write_PORTF_FER_CLEAR(val) bfin_write32(PORTF_FER_CLEAR, val)
-#define bfin_read_PORTF() bfin_read32(PORTF)
-#define bfin_write_PORTF(val) bfin_write32(PORTF, val)
-#define bfin_read_PORTF_SET() bfin_read32(PORTF_SET)
-#define bfin_write_PORTF_SET(val) bfin_write32(PORTF_SET, val)
-#define bfin_read_PORTF_CLEAR() bfin_read32(PORTF_CLEAR)
-#define bfin_write_PORTF_CLEAR(val) bfin_write32(PORTF_CLEAR, val)
-#define bfin_read_PORTF_DIR() bfin_read32(PORTF_DIR)
-#define bfin_write_PORTF_DIR(val) bfin_write32(PORTF_DIR, val)
-#define bfin_read_PORTF_DIR_SET() bfin_read32(PORTF_DIR_SET)
-#define bfin_write_PORTF_DIR_SET(val) bfin_write32(PORTF_DIR_SET, val)
-#define bfin_read_PORTF_DIR_CLEAR() bfin_read32(PORTF_DIR_CLEAR)
-#define bfin_write_PORTF_DIR_CLEAR(val) bfin_write32(PORTF_DIR_CLEAR, val)
-#define bfin_read_PORTF_INEN() bfin_read32(PORTF_INEN)
-#define bfin_write_PORTF_INEN(val) bfin_write32(PORTF_INEN, val)
-#define bfin_read_PORTF_INEN_SET() bfin_read32(PORTF_INEN_SET)
-#define bfin_write_PORTF_INEN_SET(val) bfin_write32(PORTF_INEN_SET, val)
-#define bfin_read_PORTF_INEN_CLEAR() bfin_read32(PORTF_INEN_CLEAR)
-#define bfin_write_PORTF_INEN_CLEAR(val) bfin_write32(PORTF_INEN_CLEAR, val)
-#define bfin_read_PORTF_MUX() bfin_read32(PORTF_MUX)
-#define bfin_write_PORTF_MUX(val) bfin_write32(PORTF_MUX, val)
-#define bfin_read_PORTF_DATA_TGL() bfin_read32(PORTF_DATA_TGL)
-#define bfin_write_PORTF_DATA_TGL(val) bfin_write32(PORTF_DATA_TGL, val)
-#define bfin_read_PORTF_POL() bfin_read32(PORTF_POL)
-#define bfin_write_PORTF_POL(val) bfin_write32(PORTF_POL, val)
-#define bfin_read_PORTF_POL_SET() bfin_read32(PORTF_POL_SET)
-#define bfin_write_PORTF_POL_SET(val) bfin_write32(PORTF_POL_SET, val)
-#define bfin_read_PORTF_POL_CLEAR() bfin_read32(PORTF_POL_CLEAR)
-#define bfin_write_PORTF_POL_CLEAR(val) bfin_write32(PORTF_POL_CLEAR, val)
-#define bfin_read_PORTF_LOCK() bfin_read32(PORTF_LOCK)
-#define bfin_write_PORTF_LOCK(val) bfin_write32(PORTF_LOCK, val)
-#define bfin_read_PORTF_REVID() bfin_read32(PORTF_REVID)
-#define bfin_write_PORTF_REVID(val) bfin_write32(PORTF_REVID, val)
-
-
-/* Port G Registers */
-#define bfin_read_PORTG_FER() bfin_read32(PORTG_FER)
-#define bfin_write_PORTG_FER(val) bfin_write32(PORTG_FER, val)
-#define bfin_read_PORTG_FER_SET() bfin_read32(PORTG_FER_SET)
-#define bfin_write_PORTG_FER_SET(val) bfin_write32(PORTG_FER_SET, val)
-#define bfin_read_PORTG_FER_CLEAR() bfin_read32(PORTG_FER_CLEAR)
-#define bfin_write_PORTG_FER_CLEAR(val) bfin_write32(PORTG_FER_CLEAR, val)
-#define bfin_read_PORTG() bfin_read32(PORTG)
-#define bfin_write_PORTG(val) bfin_write32(PORTG, val)
-#define bfin_read_PORTG_SET() bfin_read32(PORTG_SET)
-#define bfin_write_PORTG_SET(val) bfin_write32(PORTG_SET, val)
-#define bfin_read_PORTG_CLEAR() bfin_read32(PORTG_CLEAR)
-#define bfin_write_PORTG_CLEAR(val) bfin_write32(PORTG_CLEAR, val)
-#define bfin_read_PORTG_DIR() bfin_read32(PORTG_DIR)
-#define bfin_write_PORTG_DIR(val) bfin_write32(PORTG_DIR, val)
-#define bfin_read_PORTG_DIR_SET() bfin_read32(PORTG_DIR_SET)
-#define bfin_write_PORTG_DIR_SET(val) bfin_write32(PORTG_DIR_SET, val)
-#define bfin_read_PORTG_DIR_CLEAR() bfin_read32(PORTG_DIR_CLEAR)
-#define bfin_write_PORTG_DIR_CLEAR(val) bfin_write32(PORTG_DIR_CLEAR, val)
-#define bfin_read_PORTG_INEN() bfin_read32(PORTG_INEN)
-#define bfin_write_PORTG_INEN(val) bfin_write32(PORTG_INEN, val)
-#define bfin_read_PORTG_INEN_SET() bfin_read32(PORTG_INEN_SET)
-#define bfin_write_PORTG_INEN_SET(val) bfin_write32(PORTG_INEN_SET, val)
-#define bfin_read_PORTG_INEN_CLEAR() bfin_read32(PORTG_INEN_CLEAR)
-#define bfin_write_PORTG_INEN_CLEAR(val) bfin_write32(PORTG_INEN_CLEAR, val)
-#define bfin_read_PORTG_MUX() bfin_read32(PORTG_MUX)
-#define bfin_write_PORTG_MUX(val) bfin_write32(PORTG_MUX, val)
-#define bfin_read_PORTG_DATA_TGL() bfin_read32(PORTG_DATA_TGL)
-#define bfin_write_PORTG_DATA_TGL(val) bfin_write32(PORTG_DATA_TGL, val)
-#define bfin_read_PORTG_POL() bfin_read32(PORTG_POL)
-#define bfin_write_PORTG_POL(val) bfin_write32(PORTG_POL, val)
-#define bfin_read_PORTG_POL_SET() bfin_read32(PORTG_POL_SET)
-#define bfin_write_PORTG_POL_SET(val) bfin_write32(PORTG_POL_SET, val)
-#define bfin_read_PORTG_POL_CLEAR() bfin_read32(PORTG_POL_CLEAR)
-#define bfin_write_PORTG_POL_CLEAR(val) bfin_write32(PORTG_POL_CLEAR, val)
-#define bfin_read_PORTG_LOCK() bfin_read32(PORTG_LOCK)
-#define bfin_write_PORTG_LOCK(val) bfin_write32(PORTG_LOCK, val)
-#define bfin_read_PORTG_REVID() bfin_read32(PORTG_REVID)
-#define bfin_write_PORTG_REVID(val) bfin_write32(PORTG_REVID, val)
-
-
-
-
-/* CAN Controller 0 Config 1 Registers */
-
-#define bfin_read_CAN0_MC1() bfin_read16(CAN0_MC1)
-#define bfin_write_CAN0_MC1(val) bfin_write16(CAN0_MC1, val)
-#define bfin_read_CAN0_MD1() bfin_read16(CAN0_MD1)
-#define bfin_write_CAN0_MD1(val) bfin_write16(CAN0_MD1, val)
-#define bfin_read_CAN0_TRS1() bfin_read16(CAN0_TRS1)
-#define bfin_write_CAN0_TRS1(val) bfin_write16(CAN0_TRS1, val)
-#define bfin_read_CAN0_TRR1() bfin_read16(CAN0_TRR1)
-#define bfin_write_CAN0_TRR1(val) bfin_write16(CAN0_TRR1, val)
-#define bfin_read_CAN0_TA1() bfin_read16(CAN0_TA1)
-#define bfin_write_CAN0_TA1(val) bfin_write16(CAN0_TA1, val)
-#define bfin_read_CAN0_AA1() bfin_read16(CAN0_AA1)
-#define bfin_write_CAN0_AA1(val) bfin_write16(CAN0_AA1, val)
-#define bfin_read_CAN0_RMP1() bfin_read16(CAN0_RMP1)
-#define bfin_write_CAN0_RMP1(val) bfin_write16(CAN0_RMP1, val)
-#define bfin_read_CAN0_RML1() bfin_read16(CAN0_RML1)
-#define bfin_write_CAN0_RML1(val) bfin_write16(CAN0_RML1, val)
-#define bfin_read_CAN0_MBTIF1() bfin_read16(CAN0_MBTIF1)
-#define bfin_write_CAN0_MBTIF1(val) bfin_write16(CAN0_MBTIF1, val)
-#define bfin_read_CAN0_MBRIF1() bfin_read16(CAN0_MBRIF1)
-#define bfin_write_CAN0_MBRIF1(val) bfin_write16(CAN0_MBRIF1, val)
-#define bfin_read_CAN0_MBIM1() bfin_read16(CAN0_MBIM1)
-#define bfin_write_CAN0_MBIM1(val) bfin_write16(CAN0_MBIM1, val)
-#define bfin_read_CAN0_RFH1() bfin_read16(CAN0_RFH1)
-#define bfin_write_CAN0_RFH1(val) bfin_write16(CAN0_RFH1, val)
-#define bfin_read_CAN0_OPSS1() bfin_read16(CAN0_OPSS1)
-#define bfin_write_CAN0_OPSS1(val) bfin_write16(CAN0_OPSS1, val)
-
-/* CAN Controller 0 Config 2 Registers */
-
-#define bfin_read_CAN0_MC2() bfin_read16(CAN0_MC2)
-#define bfin_write_CAN0_MC2(val) bfin_write16(CAN0_MC2, val)
-#define bfin_read_CAN0_MD2() bfin_read16(CAN0_MD2)
-#define bfin_write_CAN0_MD2(val) bfin_write16(CAN0_MD2, val)
-#define bfin_read_CAN0_TRS2() bfin_read16(CAN0_TRS2)
-#define bfin_write_CAN0_TRS2(val) bfin_write16(CAN0_TRS2, val)
-#define bfin_read_CAN0_TRR2() bfin_read16(CAN0_TRR2)
-#define bfin_write_CAN0_TRR2(val) bfin_write16(CAN0_TRR2, val)
-#define bfin_read_CAN0_TA2() bfin_read16(CAN0_TA2)
-#define bfin_write_CAN0_TA2(val) bfin_write16(CAN0_TA2, val)
-#define bfin_read_CAN0_AA2() bfin_read16(CAN0_AA2)
-#define bfin_write_CAN0_AA2(val) bfin_write16(CAN0_AA2, val)
-#define bfin_read_CAN0_RMP2() bfin_read16(CAN0_RMP2)
-#define bfin_write_CAN0_RMP2(val) bfin_write16(CAN0_RMP2, val)
-#define bfin_read_CAN0_RML2() bfin_read16(CAN0_RML2)
-#define bfin_write_CAN0_RML2(val) bfin_write16(CAN0_RML2, val)
-#define bfin_read_CAN0_MBTIF2() bfin_read16(CAN0_MBTIF2)
-#define bfin_write_CAN0_MBTIF2(val) bfin_write16(CAN0_MBTIF2, val)
-#define bfin_read_CAN0_MBRIF2() bfin_read16(CAN0_MBRIF2)
-#define bfin_write_CAN0_MBRIF2(val) bfin_write16(CAN0_MBRIF2, val)
-#define bfin_read_CAN0_MBIM2() bfin_read16(CAN0_MBIM2)
-#define bfin_write_CAN0_MBIM2(val) bfin_write16(CAN0_MBIM2, val)
-#define bfin_read_CAN0_RFH2() bfin_read16(CAN0_RFH2)
-#define bfin_write_CAN0_RFH2(val) bfin_write16(CAN0_RFH2, val)
-#define bfin_read_CAN0_OPSS2() bfin_read16(CAN0_OPSS2)
-#define bfin_write_CAN0_OPSS2(val) bfin_write16(CAN0_OPSS2, val)
-
-/* CAN Controller 0 Clock/Interrubfin_read_()t/Counter Registers */
-
-#define bfin_read_CAN0_CLOCK() bfin_read16(CAN0_CLOCK)
-#define bfin_write_CAN0_CLOCK(val) bfin_write16(CAN0_CLOCK, val)
-#define bfin_read_CAN0_TIMING() bfin_read16(CAN0_TIMING)
-#define bfin_write_CAN0_TIMING(val) bfin_write16(CAN0_TIMING, val)
-#define bfin_read_CAN0_DEBUG() bfin_read16(CAN0_DEBUG)
-#define bfin_write_CAN0_DEBUG(val) bfin_write16(CAN0_DEBUG, val)
-#define bfin_read_CAN0_STATUS() bfin_read16(CAN0_STATUS)
-#define bfin_write_CAN0_STATUS(val) bfin_write16(CAN0_STATUS, val)
-#define bfin_read_CAN0_CEC() bfin_read16(CAN0_CEC)
-#define bfin_write_CAN0_CEC(val) bfin_write16(CAN0_CEC, val)
-#define bfin_read_CAN0_GIS() bfin_read16(CAN0_GIS)
-#define bfin_write_CAN0_GIS(val) bfin_write16(CAN0_GIS, val)
-#define bfin_read_CAN0_GIM() bfin_read16(CAN0_GIM)
-#define bfin_write_CAN0_GIM(val) bfin_write16(CAN0_GIM, val)
-#define bfin_read_CAN0_GIF() bfin_read16(CAN0_GIF)
-#define bfin_write_CAN0_GIF(val) bfin_write16(CAN0_GIF, val)
-#define bfin_read_CAN0_CONTROL() bfin_read16(CAN0_CONTROL)
-#define bfin_write_CAN0_CONTROL(val) bfin_write16(CAN0_CONTROL, val)
-#define bfin_read_CAN0_INTR() bfin_read16(CAN0_INTR)
-#define bfin_write_CAN0_INTR(val) bfin_write16(CAN0_INTR, val)
-#define bfin_read_CAN0_MBTD() bfin_read16(CAN0_MBTD)
-#define bfin_write_CAN0_MBTD(val) bfin_write16(CAN0_MBTD, val)
-#define bfin_read_CAN0_EWR() bfin_read16(CAN0_EWR)
-#define bfin_write_CAN0_EWR(val) bfin_write16(CAN0_EWR, val)
-#define bfin_read_CAN0_ESR() bfin_read16(CAN0_ESR)
-#define bfin_write_CAN0_ESR(val) bfin_write16(CAN0_ESR, val)
-#define bfin_read_CAN0_UCCNT() bfin_read16(CAN0_UCCNT)
-#define bfin_write_CAN0_UCCNT(val) bfin_write16(CAN0_UCCNT, val)
-#define bfin_read_CAN0_UCRC() bfin_read16(CAN0_UCRC)
-#define bfin_write_CAN0_UCRC(val) bfin_write16(CAN0_UCRC, val)
-#define bfin_read_CAN0_UCCNF() bfin_read16(CAN0_UCCNF)
-#define bfin_write_CAN0_UCCNF(val) bfin_write16(CAN0_UCCNF, val)
-
-/* CAN Controller 0 Accebfin_read_()tance Registers */
-
-#define bfin_read_CAN0_AM00L() bfin_read16(CAN0_AM00L)
-#define bfin_write_CAN0_AM00L(val) bfin_write16(CAN0_AM00L, val)
-#define bfin_read_CAN0_AM00H() bfin_read16(CAN0_AM00H)
-#define bfin_write_CAN0_AM00H(val) bfin_write16(CAN0_AM00H, val)
-#define bfin_read_CAN0_AM01L() bfin_read16(CAN0_AM01L)
-#define bfin_write_CAN0_AM01L(val) bfin_write16(CAN0_AM01L, val)
-#define bfin_read_CAN0_AM01H() bfin_read16(CAN0_AM01H)
-#define bfin_write_CAN0_AM01H(val) bfin_write16(CAN0_AM01H, val)
-#define bfin_read_CAN0_AM02L() bfin_read16(CAN0_AM02L)
-#define bfin_write_CAN0_AM02L(val) bfin_write16(CAN0_AM02L, val)
-#define bfin_read_CAN0_AM02H() bfin_read16(CAN0_AM02H)
-#define bfin_write_CAN0_AM02H(val) bfin_write16(CAN0_AM02H, val)
-#define bfin_read_CAN0_AM03L() bfin_read16(CAN0_AM03L)
-#define bfin_write_CAN0_AM03L(val) bfin_write16(CAN0_AM03L, val)
-#define bfin_read_CAN0_AM03H() bfin_read16(CAN0_AM03H)
-#define bfin_write_CAN0_AM03H(val) bfin_write16(CAN0_AM03H, val)
-#define bfin_read_CAN0_AM04L() bfin_read16(CAN0_AM04L)
-#define bfin_write_CAN0_AM04L(val) bfin_write16(CAN0_AM04L, val)
-#define bfin_read_CAN0_AM04H() bfin_read16(CAN0_AM04H)
-#define bfin_write_CAN0_AM04H(val) bfin_write16(CAN0_AM04H, val)
-#define bfin_read_CAN0_AM05L() bfin_read16(CAN0_AM05L)
-#define bfin_write_CAN0_AM05L(val) bfin_write16(CAN0_AM05L, val)
-#define bfin_read_CAN0_AM05H() bfin_read16(CAN0_AM05H)
-#define bfin_write_CAN0_AM05H(val) bfin_write16(CAN0_AM05H, val)
-#define bfin_read_CAN0_AM06L() bfin_read16(CAN0_AM06L)
-#define bfin_write_CAN0_AM06L(val) bfin_write16(CAN0_AM06L, val)
-#define bfin_read_CAN0_AM06H() bfin_read16(CAN0_AM06H)
-#define bfin_write_CAN0_AM06H(val) bfin_write16(CAN0_AM06H, val)
-#define bfin_read_CAN0_AM07L() bfin_read16(CAN0_AM07L)
-#define bfin_write_CAN0_AM07L(val) bfin_write16(CAN0_AM07L, val)
-#define bfin_read_CAN0_AM07H() bfin_read16(CAN0_AM07H)
-#define bfin_write_CAN0_AM07H(val) bfin_write16(CAN0_AM07H, val)
-#define bfin_read_CAN0_AM08L() bfin_read16(CAN0_AM08L)
-#define bfin_write_CAN0_AM08L(val) bfin_write16(CAN0_AM08L, val)
-#define bfin_read_CAN0_AM08H() bfin_read16(CAN0_AM08H)
-#define bfin_write_CAN0_AM08H(val) bfin_write16(CAN0_AM08H, val)
-#define bfin_read_CAN0_AM09L() bfin_read16(CAN0_AM09L)
-#define bfin_write_CAN0_AM09L(val) bfin_write16(CAN0_AM09L, val)
-#define bfin_read_CAN0_AM09H() bfin_read16(CAN0_AM09H)
-#define bfin_write_CAN0_AM09H(val) bfin_write16(CAN0_AM09H, val)
-#define bfin_read_CAN0_AM10L() bfin_read16(CAN0_AM10L)
-#define bfin_write_CAN0_AM10L(val) bfin_write16(CAN0_AM10L, val)
-#define bfin_read_CAN0_AM10H() bfin_read16(CAN0_AM10H)
-#define bfin_write_CAN0_AM10H(val) bfin_write16(CAN0_AM10H, val)
-#define bfin_read_CAN0_AM11L() bfin_read16(CAN0_AM11L)
-#define bfin_write_CAN0_AM11L(val) bfin_write16(CAN0_AM11L, val)
-#define bfin_read_CAN0_AM11H() bfin_read16(CAN0_AM11H)
-#define bfin_write_CAN0_AM11H(val) bfin_write16(CAN0_AM11H, val)
-#define bfin_read_CAN0_AM12L() bfin_read16(CAN0_AM12L)
-#define bfin_write_CAN0_AM12L(val) bfin_write16(CAN0_AM12L, val)
-#define bfin_read_CAN0_AM12H() bfin_read16(CAN0_AM12H)
-#define bfin_write_CAN0_AM12H(val) bfin_write16(CAN0_AM12H, val)
-#define bfin_read_CAN0_AM13L() bfin_read16(CAN0_AM13L)
-#define bfin_write_CAN0_AM13L(val) bfin_write16(CAN0_AM13L, val)
-#define bfin_read_CAN0_AM13H() bfin_read16(CAN0_AM13H)
-#define bfin_write_CAN0_AM13H(val) bfin_write16(CAN0_AM13H, val)
-#define bfin_read_CAN0_AM14L() bfin_read16(CAN0_AM14L)
-#define bfin_write_CAN0_AM14L(val) bfin_write16(CAN0_AM14L, val)
-#define bfin_read_CAN0_AM14H() bfin_read16(CAN0_AM14H)
-#define bfin_write_CAN0_AM14H(val) bfin_write16(CAN0_AM14H, val)
-#define bfin_read_CAN0_AM15L() bfin_read16(CAN0_AM15L)
-#define bfin_write_CAN0_AM15L(val) bfin_write16(CAN0_AM15L, val)
-#define bfin_read_CAN0_AM15H() bfin_read16(CAN0_AM15H)
-#define bfin_write_CAN0_AM15H(val) bfin_write16(CAN0_AM15H, val)
-
-/* CAN Controller 0 Accebfin_read_()tance Registers */
-
-#define bfin_read_CAN0_AM16L() bfin_read16(CAN0_AM16L)
-#define bfin_write_CAN0_AM16L(val) bfin_write16(CAN0_AM16L, val)
-#define bfin_read_CAN0_AM16H() bfin_read16(CAN0_AM16H)
-#define bfin_write_CAN0_AM16H(val) bfin_write16(CAN0_AM16H, val)
-#define bfin_read_CAN0_AM17L() bfin_read16(CAN0_AM17L)
-#define bfin_write_CAN0_AM17L(val) bfin_write16(CAN0_AM17L, val)
-#define bfin_read_CAN0_AM17H() bfin_read16(CAN0_AM17H)
-#define bfin_write_CAN0_AM17H(val) bfin_write16(CAN0_AM17H, val)
-#define bfin_read_CAN0_AM18L() bfin_read16(CAN0_AM18L)
-#define bfin_write_CAN0_AM18L(val) bfin_write16(CAN0_AM18L, val)
-#define bfin_read_CAN0_AM18H() bfin_read16(CAN0_AM18H)
-#define bfin_write_CAN0_AM18H(val) bfin_write16(CAN0_AM18H, val)
-#define bfin_read_CAN0_AM19L() bfin_read16(CAN0_AM19L)
-#define bfin_write_CAN0_AM19L(val) bfin_write16(CAN0_AM19L, val)
-#define bfin_read_CAN0_AM19H() bfin_read16(CAN0_AM19H)
-#define bfin_write_CAN0_AM19H(val) bfin_write16(CAN0_AM19H, val)
-#define bfin_read_CAN0_AM20L() bfin_read16(CAN0_AM20L)
-#define bfin_write_CAN0_AM20L(val) bfin_write16(CAN0_AM20L, val)
-#define bfin_read_CAN0_AM20H() bfin_read16(CAN0_AM20H)
-#define bfin_write_CAN0_AM20H(val) bfin_write16(CAN0_AM20H, val)
-#define bfin_read_CAN0_AM21L() bfin_read16(CAN0_AM21L)
-#define bfin_write_CAN0_AM21L(val) bfin_write16(CAN0_AM21L, val)
-#define bfin_read_CAN0_AM21H() bfin_read16(CAN0_AM21H)
-#define bfin_write_CAN0_AM21H(val) bfin_write16(CAN0_AM21H, val)
-#define bfin_read_CAN0_AM22L() bfin_read16(CAN0_AM22L)
-#define bfin_write_CAN0_AM22L(val) bfin_write16(CAN0_AM22L, val)
-#define bfin_read_CAN0_AM22H() bfin_read16(CAN0_AM22H)
-#define bfin_write_CAN0_AM22H(val) bfin_write16(CAN0_AM22H, val)
-#define bfin_read_CAN0_AM23L() bfin_read16(CAN0_AM23L)
-#define bfin_write_CAN0_AM23L(val) bfin_write16(CAN0_AM23L, val)
-#define bfin_read_CAN0_AM23H() bfin_read16(CAN0_AM23H)
-#define bfin_write_CAN0_AM23H(val) bfin_write16(CAN0_AM23H, val)
-#define bfin_read_CAN0_AM24L() bfin_read16(CAN0_AM24L)
-#define bfin_write_CAN0_AM24L(val) bfin_write16(CAN0_AM24L, val)
-#define bfin_read_CAN0_AM24H() bfin_read16(CAN0_AM24H)
-#define bfin_write_CAN0_AM24H(val) bfin_write16(CAN0_AM24H, val)
-#define bfin_read_CAN0_AM25L() bfin_read16(CAN0_AM25L)
-#define bfin_write_CAN0_AM25L(val) bfin_write16(CAN0_AM25L, val)
-#define bfin_read_CAN0_AM25H() bfin_read16(CAN0_AM25H)
-#define bfin_write_CAN0_AM25H(val) bfin_write16(CAN0_AM25H, val)
-#define bfin_read_CAN0_AM26L() bfin_read16(CAN0_AM26L)
-#define bfin_write_CAN0_AM26L(val) bfin_write16(CAN0_AM26L, val)
-#define bfin_read_CAN0_AM26H() bfin_read16(CAN0_AM26H)
-#define bfin_write_CAN0_AM26H(val) bfin_write16(CAN0_AM26H, val)
-#define bfin_read_CAN0_AM27L() bfin_read16(CAN0_AM27L)
-#define bfin_write_CAN0_AM27L(val) bfin_write16(CAN0_AM27L, val)
-#define bfin_read_CAN0_AM27H() bfin_read16(CAN0_AM27H)
-#define bfin_write_CAN0_AM27H(val) bfin_write16(CAN0_AM27H, val)
-#define bfin_read_CAN0_AM28L() bfin_read16(CAN0_AM28L)
-#define bfin_write_CAN0_AM28L(val) bfin_write16(CAN0_AM28L, val)
-#define bfin_read_CAN0_AM28H() bfin_read16(CAN0_AM28H)
-#define bfin_write_CAN0_AM28H(val) bfin_write16(CAN0_AM28H, val)
-#define bfin_read_CAN0_AM29L() bfin_read16(CAN0_AM29L)
-#define bfin_write_CAN0_AM29L(val) bfin_write16(CAN0_AM29L, val)
-#define bfin_read_CAN0_AM29H() bfin_read16(CAN0_AM29H)
-#define bfin_write_CAN0_AM29H(val) bfin_write16(CAN0_AM29H, val)
-#define bfin_read_CAN0_AM30L() bfin_read16(CAN0_AM30L)
-#define bfin_write_CAN0_AM30L(val) bfin_write16(CAN0_AM30L, val)
-#define bfin_read_CAN0_AM30H() bfin_read16(CAN0_AM30H)
-#define bfin_write_CAN0_AM30H(val) bfin_write16(CAN0_AM30H, val)
-#define bfin_read_CAN0_AM31L() bfin_read16(CAN0_AM31L)
-#define bfin_write_CAN0_AM31L(val) bfin_write16(CAN0_AM31L, val)
-#define bfin_read_CAN0_AM31H() bfin_read16(CAN0_AM31H)
-#define bfin_write_CAN0_AM31H(val) bfin_write16(CAN0_AM31H, val)
-
-/* CAN Controller 0 Mailbox Data Registers */
-
-#define bfin_read_CAN0_MB00_DATA0() bfin_read16(CAN0_MB00_DATA0)
-#define bfin_write_CAN0_MB00_DATA0(val) bfin_write16(CAN0_MB00_DATA0, val)
-#define bfin_read_CAN0_MB00_DATA1() bfin_read16(CAN0_MB00_DATA1)
-#define bfin_write_CAN0_MB00_DATA1(val) bfin_write16(CAN0_MB00_DATA1, val)
-#define bfin_read_CAN0_MB00_DATA2() bfin_read16(CAN0_MB00_DATA2)
-#define bfin_write_CAN0_MB00_DATA2(val) bfin_write16(CAN0_MB00_DATA2, val)
-#define bfin_read_CAN0_MB00_DATA3() bfin_read16(CAN0_MB00_DATA3)
-#define bfin_write_CAN0_MB00_DATA3(val) bfin_write16(CAN0_MB00_DATA3, val)
-#define bfin_read_CAN0_MB00_LENGTH() bfin_read16(CAN0_MB00_LENGTH)
-#define bfin_write_CAN0_MB00_LENGTH(val) bfin_write16(CAN0_MB00_LENGTH, val)
-#define bfin_read_CAN0_MB00_TIMESTAMP() bfin_read16(CAN0_MB00_TIMESTAMP)
-#define bfin_write_CAN0_MB00_TIMESTAMP(val) bfin_write16(CAN0_MB00_TIMESTAMP, val)
-#define bfin_read_CAN0_MB00_ID0() bfin_read16(CAN0_MB00_ID0)
-#define bfin_write_CAN0_MB00_ID0(val) bfin_write16(CAN0_MB00_ID0, val)
-#define bfin_read_CAN0_MB00_ID1() bfin_read16(CAN0_MB00_ID1)
-#define bfin_write_CAN0_MB00_ID1(val) bfin_write16(CAN0_MB00_ID1, val)
-#define bfin_read_CAN0_MB01_DATA0() bfin_read16(CAN0_MB01_DATA0)
-#define bfin_write_CAN0_MB01_DATA0(val) bfin_write16(CAN0_MB01_DATA0, val)
-#define bfin_read_CAN0_MB01_DATA1() bfin_read16(CAN0_MB01_DATA1)
-#define bfin_write_CAN0_MB01_DATA1(val) bfin_write16(CAN0_MB01_DATA1, val)
-#define bfin_read_CAN0_MB01_DATA2() bfin_read16(CAN0_MB01_DATA2)
-#define bfin_write_CAN0_MB01_DATA2(val) bfin_write16(CAN0_MB01_DATA2, val)
-#define bfin_read_CAN0_MB01_DATA3() bfin_read16(CAN0_MB01_DATA3)
-#define bfin_write_CAN0_MB01_DATA3(val) bfin_write16(CAN0_MB01_DATA3, val)
-#define bfin_read_CAN0_MB01_LENGTH() bfin_read16(CAN0_MB01_LENGTH)
-#define bfin_write_CAN0_MB01_LENGTH(val) bfin_write16(CAN0_MB01_LENGTH, val)
-#define bfin_read_CAN0_MB01_TIMESTAMP() bfin_read16(CAN0_MB01_TIMESTAMP)
-#define bfin_write_CAN0_MB01_TIMESTAMP(val) bfin_write16(CAN0_MB01_TIMESTAMP, val)
-#define bfin_read_CAN0_MB01_ID0() bfin_read16(CAN0_MB01_ID0)
-#define bfin_write_CAN0_MB01_ID0(val) bfin_write16(CAN0_MB01_ID0, val)
-#define bfin_read_CAN0_MB01_ID1() bfin_read16(CAN0_MB01_ID1)
-#define bfin_write_CAN0_MB01_ID1(val) bfin_write16(CAN0_MB01_ID1, val)
-#define bfin_read_CAN0_MB02_DATA0() bfin_read16(CAN0_MB02_DATA0)
-#define bfin_write_CAN0_MB02_DATA0(val) bfin_write16(CAN0_MB02_DATA0, val)
-#define bfin_read_CAN0_MB02_DATA1() bfin_read16(CAN0_MB02_DATA1)
-#define bfin_write_CAN0_MB02_DATA1(val) bfin_write16(CAN0_MB02_DATA1, val)
-#define bfin_read_CAN0_MB02_DATA2() bfin_read16(CAN0_MB02_DATA2)
-#define bfin_write_CAN0_MB02_DATA2(val) bfin_write16(CAN0_MB02_DATA2, val)
-#define bfin_read_CAN0_MB02_DATA3() bfin_read16(CAN0_MB02_DATA3)
-#define bfin_write_CAN0_MB02_DATA3(val) bfin_write16(CAN0_MB02_DATA3, val)
-#define bfin_read_CAN0_MB02_LENGTH() bfin_read16(CAN0_MB02_LENGTH)
-#define bfin_write_CAN0_MB02_LENGTH(val) bfin_write16(CAN0_MB02_LENGTH, val)
-#define bfin_read_CAN0_MB02_TIMESTAMP() bfin_read16(CAN0_MB02_TIMESTAMP)
-#define bfin_write_CAN0_MB02_TIMESTAMP(val) bfin_write16(CAN0_MB02_TIMESTAMP, val)
-#define bfin_read_CAN0_MB02_ID0() bfin_read16(CAN0_MB02_ID0)
-#define bfin_write_CAN0_MB02_ID0(val) bfin_write16(CAN0_MB02_ID0, val)
-#define bfin_read_CAN0_MB02_ID1() bfin_read16(CAN0_MB02_ID1)
-#define bfin_write_CAN0_MB02_ID1(val) bfin_write16(CAN0_MB02_ID1, val)
-#define bfin_read_CAN0_MB03_DATA0() bfin_read16(CAN0_MB03_DATA0)
-#define bfin_write_CAN0_MB03_DATA0(val) bfin_write16(CAN0_MB03_DATA0, val)
-#define bfin_read_CAN0_MB03_DATA1() bfin_read16(CAN0_MB03_DATA1)
-#define bfin_write_CAN0_MB03_DATA1(val) bfin_write16(CAN0_MB03_DATA1, val)
-#define bfin_read_CAN0_MB03_DATA2() bfin_read16(CAN0_MB03_DATA2)
-#define bfin_write_CAN0_MB03_DATA2(val) bfin_write16(CAN0_MB03_DATA2, val)
-#define bfin_read_CAN0_MB03_DATA3() bfin_read16(CAN0_MB03_DATA3)
-#define bfin_write_CAN0_MB03_DATA3(val) bfin_write16(CAN0_MB03_DATA3, val)
-#define bfin_read_CAN0_MB03_LENGTH() bfin_read16(CAN0_MB03_LENGTH)
-#define bfin_write_CAN0_MB03_LENGTH(val) bfin_write16(CAN0_MB03_LENGTH, val)
-#define bfin_read_CAN0_MB03_TIMESTAMP() bfin_read16(CAN0_MB03_TIMESTAMP)
-#define bfin_write_CAN0_MB03_TIMESTAMP(val) bfin_write16(CAN0_MB03_TIMESTAMP, val)
-#define bfin_read_CAN0_MB03_ID0() bfin_read16(CAN0_MB03_ID0)
-#define bfin_write_CAN0_MB03_ID0(val) bfin_write16(CAN0_MB03_ID0, val)
-#define bfin_read_CAN0_MB03_ID1() bfin_read16(CAN0_MB03_ID1)
-#define bfin_write_CAN0_MB03_ID1(val) bfin_write16(CAN0_MB03_ID1, val)
-#define bfin_read_CAN0_MB04_DATA0() bfin_read16(CAN0_MB04_DATA0)
-#define bfin_write_CAN0_MB04_DATA0(val) bfin_write16(CAN0_MB04_DATA0, val)
-#define bfin_read_CAN0_MB04_DATA1() bfin_read16(CAN0_MB04_DATA1)
-#define bfin_write_CAN0_MB04_DATA1(val) bfin_write16(CAN0_MB04_DATA1, val)
-#define bfin_read_CAN0_MB04_DATA2() bfin_read16(CAN0_MB04_DATA2)
-#define bfin_write_CAN0_MB04_DATA2(val) bfin_write16(CAN0_MB04_DATA2, val)
-#define bfin_read_CAN0_MB04_DATA3() bfin_read16(CAN0_MB04_DATA3)
-#define bfin_write_CAN0_MB04_DATA3(val) bfin_write16(CAN0_MB04_DATA3, val)
-#define bfin_read_CAN0_MB04_LENGTH() bfin_read16(CAN0_MB04_LENGTH)
-#define bfin_write_CAN0_MB04_LENGTH(val) bfin_write16(CAN0_MB04_LENGTH, val)
-#define bfin_read_CAN0_MB04_TIMESTAMP() bfin_read16(CAN0_MB04_TIMESTAMP)
-#define bfin_write_CAN0_MB04_TIMESTAMP(val) bfin_write16(CAN0_MB04_TIMESTAMP, val)
-#define bfin_read_CAN0_MB04_ID0() bfin_read16(CAN0_MB04_ID0)
-#define bfin_write_CAN0_MB04_ID0(val) bfin_write16(CAN0_MB04_ID0, val)
-#define bfin_read_CAN0_MB04_ID1() bfin_read16(CAN0_MB04_ID1)
-#define bfin_write_CAN0_MB04_ID1(val) bfin_write16(CAN0_MB04_ID1, val)
-#define bfin_read_CAN0_MB05_DATA0() bfin_read16(CAN0_MB05_DATA0)
-#define bfin_write_CAN0_MB05_DATA0(val) bfin_write16(CAN0_MB05_DATA0, val)
-#define bfin_read_CAN0_MB05_DATA1() bfin_read16(CAN0_MB05_DATA1)
-#define bfin_write_CAN0_MB05_DATA1(val) bfin_write16(CAN0_MB05_DATA1, val)
-#define bfin_read_CAN0_MB05_DATA2() bfin_read16(CAN0_MB05_DATA2)
-#define bfin_write_CAN0_MB05_DATA2(val) bfin_write16(CAN0_MB05_DATA2, val)
-#define bfin_read_CAN0_MB05_DATA3() bfin_read16(CAN0_MB05_DATA3)
-#define bfin_write_CAN0_MB05_DATA3(val) bfin_write16(CAN0_MB05_DATA3, val)
-#define bfin_read_CAN0_MB05_LENGTH() bfin_read16(CAN0_MB05_LENGTH)
-#define bfin_write_CAN0_MB05_LENGTH(val) bfin_write16(CAN0_MB05_LENGTH, val)
-#define bfin_read_CAN0_MB05_TIMESTAMP() bfin_read16(CAN0_MB05_TIMESTAMP)
-#define bfin_write_CAN0_MB05_TIMESTAMP(val) bfin_write16(CAN0_MB05_TIMESTAMP, val)
-#define bfin_read_CAN0_MB05_ID0() bfin_read16(CAN0_MB05_ID0)
-#define bfin_write_CAN0_MB05_ID0(val) bfin_write16(CAN0_MB05_ID0, val)
-#define bfin_read_CAN0_MB05_ID1() bfin_read16(CAN0_MB05_ID1)
-#define bfin_write_CAN0_MB05_ID1(val) bfin_write16(CAN0_MB05_ID1, val)
-#define bfin_read_CAN0_MB06_DATA0() bfin_read16(CAN0_MB06_DATA0)
-#define bfin_write_CAN0_MB06_DATA0(val) bfin_write16(CAN0_MB06_DATA0, val)
-#define bfin_read_CAN0_MB06_DATA1() bfin_read16(CAN0_MB06_DATA1)
-#define bfin_write_CAN0_MB06_DATA1(val) bfin_write16(CAN0_MB06_DATA1, val)
-#define bfin_read_CAN0_MB06_DATA2() bfin_read16(CAN0_MB06_DATA2)
-#define bfin_write_CAN0_MB06_DATA2(val) bfin_write16(CAN0_MB06_DATA2, val)
-#define bfin_read_CAN0_MB06_DATA3() bfin_read16(CAN0_MB06_DATA3)
-#define bfin_write_CAN0_MB06_DATA3(val) bfin_write16(CAN0_MB06_DATA3, val)
-#define bfin_read_CAN0_MB06_LENGTH() bfin_read16(CAN0_MB06_LENGTH)
-#define bfin_write_CAN0_MB06_LENGTH(val) bfin_write16(CAN0_MB06_LENGTH, val)
-#define bfin_read_CAN0_MB06_TIMESTAMP() bfin_read16(CAN0_MB06_TIMESTAMP)
-#define bfin_write_CAN0_MB06_TIMESTAMP(val) bfin_write16(CAN0_MB06_TIMESTAMP, val)
-#define bfin_read_CAN0_MB06_ID0() bfin_read16(CAN0_MB06_ID0)
-#define bfin_write_CAN0_MB06_ID0(val) bfin_write16(CAN0_MB06_ID0, val)
-#define bfin_read_CAN0_MB06_ID1() bfin_read16(CAN0_MB06_ID1)
-#define bfin_write_CAN0_MB06_ID1(val) bfin_write16(CAN0_MB06_ID1, val)
-#define bfin_read_CAN0_MB07_DATA0() bfin_read16(CAN0_MB07_DATA0)
-#define bfin_write_CAN0_MB07_DATA0(val) bfin_write16(CAN0_MB07_DATA0, val)
-#define bfin_read_CAN0_MB07_DATA1() bfin_read16(CAN0_MB07_DATA1)
-#define bfin_write_CAN0_MB07_DATA1(val) bfin_write16(CAN0_MB07_DATA1, val)
-#define bfin_read_CAN0_MB07_DATA2() bfin_read16(CAN0_MB07_DATA2)
-#define bfin_write_CAN0_MB07_DATA2(val) bfin_write16(CAN0_MB07_DATA2, val)
-#define bfin_read_CAN0_MB07_DATA3() bfin_read16(CAN0_MB07_DATA3)
-#define bfin_write_CAN0_MB07_DATA3(val) bfin_write16(CAN0_MB07_DATA3, val)
-#define bfin_read_CAN0_MB07_LENGTH() bfin_read16(CAN0_MB07_LENGTH)
-#define bfin_write_CAN0_MB07_LENGTH(val) bfin_write16(CAN0_MB07_LENGTH, val)
-#define bfin_read_CAN0_MB07_TIMESTAMP() bfin_read16(CAN0_MB07_TIMESTAMP)
-#define bfin_write_CAN0_MB07_TIMESTAMP(val) bfin_write16(CAN0_MB07_TIMESTAMP, val)
-#define bfin_read_CAN0_MB07_ID0() bfin_read16(CAN0_MB07_ID0)
-#define bfin_write_CAN0_MB07_ID0(val) bfin_write16(CAN0_MB07_ID0, val)
-#define bfin_read_CAN0_MB07_ID1() bfin_read16(CAN0_MB07_ID1)
-#define bfin_write_CAN0_MB07_ID1(val) bfin_write16(CAN0_MB07_ID1, val)
-#define bfin_read_CAN0_MB08_DATA0() bfin_read16(CAN0_MB08_DATA0)
-#define bfin_write_CAN0_MB08_DATA0(val) bfin_write16(CAN0_MB08_DATA0, val)
-#define bfin_read_CAN0_MB08_DATA1() bfin_read16(CAN0_MB08_DATA1)
-#define bfin_write_CAN0_MB08_DATA1(val) bfin_write16(CAN0_MB08_DATA1, val)
-#define bfin_read_CAN0_MB08_DATA2() bfin_read16(CAN0_MB08_DATA2)
-#define bfin_write_CAN0_MB08_DATA2(val) bfin_write16(CAN0_MB08_DATA2, val)
-#define bfin_read_CAN0_MB08_DATA3() bfin_read16(CAN0_MB08_DATA3)
-#define bfin_write_CAN0_MB08_DATA3(val) bfin_write16(CAN0_MB08_DATA3, val)
-#define bfin_read_CAN0_MB08_LENGTH() bfin_read16(CAN0_MB08_LENGTH)
-#define bfin_write_CAN0_MB08_LENGTH(val) bfin_write16(CAN0_MB08_LENGTH, val)
-#define bfin_read_CAN0_MB08_TIMESTAMP() bfin_read16(CAN0_MB08_TIMESTAMP)
-#define bfin_write_CAN0_MB08_TIMESTAMP(val) bfin_write16(CAN0_MB08_TIMESTAMP, val)
-#define bfin_read_CAN0_MB08_ID0() bfin_read16(CAN0_MB08_ID0)
-#define bfin_write_CAN0_MB08_ID0(val) bfin_write16(CAN0_MB08_ID0, val)
-#define bfin_read_CAN0_MB08_ID1() bfin_read16(CAN0_MB08_ID1)
-#define bfin_write_CAN0_MB08_ID1(val) bfin_write16(CAN0_MB08_ID1, val)
-#define bfin_read_CAN0_MB09_DATA0() bfin_read16(CAN0_MB09_DATA0)
-#define bfin_write_CAN0_MB09_DATA0(val) bfin_write16(CAN0_MB09_DATA0, val)
-#define bfin_read_CAN0_MB09_DATA1() bfin_read16(CAN0_MB09_DATA1)
-#define bfin_write_CAN0_MB09_DATA1(val) bfin_write16(CAN0_MB09_DATA1, val)
-#define bfin_read_CAN0_MB09_DATA2() bfin_read16(CAN0_MB09_DATA2)
-#define bfin_write_CAN0_MB09_DATA2(val) bfin_write16(CAN0_MB09_DATA2, val)
-#define bfin_read_CAN0_MB09_DATA3() bfin_read16(CAN0_MB09_DATA3)
-#define bfin_write_CAN0_MB09_DATA3(val) bfin_write16(CAN0_MB09_DATA3, val)
-#define bfin_read_CAN0_MB09_LENGTH() bfin_read16(CAN0_MB09_LENGTH)
-#define bfin_write_CAN0_MB09_LENGTH(val) bfin_write16(CAN0_MB09_LENGTH, val)
-#define bfin_read_CAN0_MB09_TIMESTAMP() bfin_read16(CAN0_MB09_TIMESTAMP)
-#define bfin_write_CAN0_MB09_TIMESTAMP(val) bfin_write16(CAN0_MB09_TIMESTAMP, val)
-#define bfin_read_CAN0_MB09_ID0() bfin_read16(CAN0_MB09_ID0)
-#define bfin_write_CAN0_MB09_ID0(val) bfin_write16(CAN0_MB09_ID0, val)
-#define bfin_read_CAN0_MB09_ID1() bfin_read16(CAN0_MB09_ID1)
-#define bfin_write_CAN0_MB09_ID1(val) bfin_write16(CAN0_MB09_ID1, val)
-#define bfin_read_CAN0_MB10_DATA0() bfin_read16(CAN0_MB10_DATA0)
-#define bfin_write_CAN0_MB10_DATA0(val) bfin_write16(CAN0_MB10_DATA0, val)
-#define bfin_read_CAN0_MB10_DATA1() bfin_read16(CAN0_MB10_DATA1)
-#define bfin_write_CAN0_MB10_DATA1(val) bfin_write16(CAN0_MB10_DATA1, val)
-#define bfin_read_CAN0_MB10_DATA2() bfin_read16(CAN0_MB10_DATA2)
-#define bfin_write_CAN0_MB10_DATA2(val) bfin_write16(CAN0_MB10_DATA2, val)
-#define bfin_read_CAN0_MB10_DATA3() bfin_read16(CAN0_MB10_DATA3)
-#define bfin_write_CAN0_MB10_DATA3(val) bfin_write16(CAN0_MB10_DATA3, val)
-#define bfin_read_CAN0_MB10_LENGTH() bfin_read16(CAN0_MB10_LENGTH)
-#define bfin_write_CAN0_MB10_LENGTH(val) bfin_write16(CAN0_MB10_LENGTH, val)
-#define bfin_read_CAN0_MB10_TIMESTAMP() bfin_read16(CAN0_MB10_TIMESTAMP)
-#define bfin_write_CAN0_MB10_TIMESTAMP(val) bfin_write16(CAN0_MB10_TIMESTAMP, val)
-#define bfin_read_CAN0_MB10_ID0() bfin_read16(CAN0_MB10_ID0)
-#define bfin_write_CAN0_MB10_ID0(val) bfin_write16(CAN0_MB10_ID0, val)
-#define bfin_read_CAN0_MB10_ID1() bfin_read16(CAN0_MB10_ID1)
-#define bfin_write_CAN0_MB10_ID1(val) bfin_write16(CAN0_MB10_ID1, val)
-#define bfin_read_CAN0_MB11_DATA0() bfin_read16(CAN0_MB11_DATA0)
-#define bfin_write_CAN0_MB11_DATA0(val) bfin_write16(CAN0_MB11_DATA0, val)
-#define bfin_read_CAN0_MB11_DATA1() bfin_read16(CAN0_MB11_DATA1)
-#define bfin_write_CAN0_MB11_DATA1(val) bfin_write16(CAN0_MB11_DATA1, val)
-#define bfin_read_CAN0_MB11_DATA2() bfin_read16(CAN0_MB11_DATA2)
-#define bfin_write_CAN0_MB11_DATA2(val) bfin_write16(CAN0_MB11_DATA2, val)
-#define bfin_read_CAN0_MB11_DATA3() bfin_read16(CAN0_MB11_DATA3)
-#define bfin_write_CAN0_MB11_DATA3(val) bfin_write16(CAN0_MB11_DATA3, val)
-#define bfin_read_CAN0_MB11_LENGTH() bfin_read16(CAN0_MB11_LENGTH)
-#define bfin_write_CAN0_MB11_LENGTH(val) bfin_write16(CAN0_MB11_LENGTH, val)
-#define bfin_read_CAN0_MB11_TIMESTAMP() bfin_read16(CAN0_MB11_TIMESTAMP)
-#define bfin_write_CAN0_MB11_TIMESTAMP(val) bfin_write16(CAN0_MB11_TIMESTAMP, val)
-#define bfin_read_CAN0_MB11_ID0() bfin_read16(CAN0_MB11_ID0)
-#define bfin_write_CAN0_MB11_ID0(val) bfin_write16(CAN0_MB11_ID0, val)
-#define bfin_read_CAN0_MB11_ID1() bfin_read16(CAN0_MB11_ID1)
-#define bfin_write_CAN0_MB11_ID1(val) bfin_write16(CAN0_MB11_ID1, val)
-#define bfin_read_CAN0_MB12_DATA0() bfin_read16(CAN0_MB12_DATA0)
-#define bfin_write_CAN0_MB12_DATA0(val) bfin_write16(CAN0_MB12_DATA0, val)
-#define bfin_read_CAN0_MB12_DATA1() bfin_read16(CAN0_MB12_DATA1)
-#define bfin_write_CAN0_MB12_DATA1(val) bfin_write16(CAN0_MB12_DATA1, val)
-#define bfin_read_CAN0_MB12_DATA2() bfin_read16(CAN0_MB12_DATA2)
-#define bfin_write_CAN0_MB12_DATA2(val) bfin_write16(CAN0_MB12_DATA2, val)
-#define bfin_read_CAN0_MB12_DATA3() bfin_read16(CAN0_MB12_DATA3)
-#define bfin_write_CAN0_MB12_DATA3(val) bfin_write16(CAN0_MB12_DATA3, val)
-#define bfin_read_CAN0_MB12_LENGTH() bfin_read16(CAN0_MB12_LENGTH)
-#define bfin_write_CAN0_MB12_LENGTH(val) bfin_write16(CAN0_MB12_LENGTH, val)
-#define bfin_read_CAN0_MB12_TIMESTAMP() bfin_read16(CAN0_MB12_TIMESTAMP)
-#define bfin_write_CAN0_MB12_TIMESTAMP(val) bfin_write16(CAN0_MB12_TIMESTAMP, val)
-#define bfin_read_CAN0_MB12_ID0() bfin_read16(CAN0_MB12_ID0)
-#define bfin_write_CAN0_MB12_ID0(val) bfin_write16(CAN0_MB12_ID0, val)
-#define bfin_read_CAN0_MB12_ID1() bfin_read16(CAN0_MB12_ID1)
-#define bfin_write_CAN0_MB12_ID1(val) bfin_write16(CAN0_MB12_ID1, val)
-#define bfin_read_CAN0_MB13_DATA0() bfin_read16(CAN0_MB13_DATA0)
-#define bfin_write_CAN0_MB13_DATA0(val) bfin_write16(CAN0_MB13_DATA0, val)
-#define bfin_read_CAN0_MB13_DATA1() bfin_read16(CAN0_MB13_DATA1)
-#define bfin_write_CAN0_MB13_DATA1(val) bfin_write16(CAN0_MB13_DATA1, val)
-#define bfin_read_CAN0_MB13_DATA2() bfin_read16(CAN0_MB13_DATA2)
-#define bfin_write_CAN0_MB13_DATA2(val) bfin_write16(CAN0_MB13_DATA2, val)
-#define bfin_read_CAN0_MB13_DATA3() bfin_read16(CAN0_MB13_DATA3)
-#define bfin_write_CAN0_MB13_DATA3(val) bfin_write16(CAN0_MB13_DATA3, val)
-#define bfin_read_CAN0_MB13_LENGTH() bfin_read16(CAN0_MB13_LENGTH)
-#define bfin_write_CAN0_MB13_LENGTH(val) bfin_write16(CAN0_MB13_LENGTH, val)
-#define bfin_read_CAN0_MB13_TIMESTAMP() bfin_read16(CAN0_MB13_TIMESTAMP)
-#define bfin_write_CAN0_MB13_TIMESTAMP(val) bfin_write16(CAN0_MB13_TIMESTAMP, val)
-#define bfin_read_CAN0_MB13_ID0() bfin_read16(CAN0_MB13_ID0)
-#define bfin_write_CAN0_MB13_ID0(val) bfin_write16(CAN0_MB13_ID0, val)
-#define bfin_read_CAN0_MB13_ID1() bfin_read16(CAN0_MB13_ID1)
-#define bfin_write_CAN0_MB13_ID1(val) bfin_write16(CAN0_MB13_ID1, val)
-#define bfin_read_CAN0_MB14_DATA0() bfin_read16(CAN0_MB14_DATA0)
-#define bfin_write_CAN0_MB14_DATA0(val) bfin_write16(CAN0_MB14_DATA0, val)
-#define bfin_read_CAN0_MB14_DATA1() bfin_read16(CAN0_MB14_DATA1)
-#define bfin_write_CAN0_MB14_DATA1(val) bfin_write16(CAN0_MB14_DATA1, val)
-#define bfin_read_CAN0_MB14_DATA2() bfin_read16(CAN0_MB14_DATA2)
-#define bfin_write_CAN0_MB14_DATA2(val) bfin_write16(CAN0_MB14_DATA2, val)
-#define bfin_read_CAN0_MB14_DATA3() bfin_read16(CAN0_MB14_DATA3)
-#define bfin_write_CAN0_MB14_DATA3(val) bfin_write16(CAN0_MB14_DATA3, val)
-#define bfin_read_CAN0_MB14_LENGTH() bfin_read16(CAN0_MB14_LENGTH)
-#define bfin_write_CAN0_MB14_LENGTH(val) bfin_write16(CAN0_MB14_LENGTH, val)
-#define bfin_read_CAN0_MB14_TIMESTAMP() bfin_read16(CAN0_MB14_TIMESTAMP)
-#define bfin_write_CAN0_MB14_TIMESTAMP(val) bfin_write16(CAN0_MB14_TIMESTAMP, val)
-#define bfin_read_CAN0_MB14_ID0() bfin_read16(CAN0_MB14_ID0)
-#define bfin_write_CAN0_MB14_ID0(val) bfin_write16(CAN0_MB14_ID0, val)
-#define bfin_read_CAN0_MB14_ID1() bfin_read16(CAN0_MB14_ID1)
-#define bfin_write_CAN0_MB14_ID1(val) bfin_write16(CAN0_MB14_ID1, val)
-#define bfin_read_CAN0_MB15_DATA0() bfin_read16(CAN0_MB15_DATA0)
-#define bfin_write_CAN0_MB15_DATA0(val) bfin_write16(CAN0_MB15_DATA0, val)
-#define bfin_read_CAN0_MB15_DATA1() bfin_read16(CAN0_MB15_DATA1)
-#define bfin_write_CAN0_MB15_DATA1(val) bfin_write16(CAN0_MB15_DATA1, val)
-#define bfin_read_CAN0_MB15_DATA2() bfin_read16(CAN0_MB15_DATA2)
-#define bfin_write_CAN0_MB15_DATA2(val) bfin_write16(CAN0_MB15_DATA2, val)
-#define bfin_read_CAN0_MB15_DATA3() bfin_read16(CAN0_MB15_DATA3)
-#define bfin_write_CAN0_MB15_DATA3(val) bfin_write16(CAN0_MB15_DATA3, val)
-#define bfin_read_CAN0_MB15_LENGTH() bfin_read16(CAN0_MB15_LENGTH)
-#define bfin_write_CAN0_MB15_LENGTH(val) bfin_write16(CAN0_MB15_LENGTH, val)
-#define bfin_read_CAN0_MB15_TIMESTAMP() bfin_read16(CAN0_MB15_TIMESTAMP)
-#define bfin_write_CAN0_MB15_TIMESTAMP(val) bfin_write16(CAN0_MB15_TIMESTAMP, val)
-#define bfin_read_CAN0_MB15_ID0() bfin_read16(CAN0_MB15_ID0)
-#define bfin_write_CAN0_MB15_ID0(val) bfin_write16(CAN0_MB15_ID0, val)
-#define bfin_read_CAN0_MB15_ID1() bfin_read16(CAN0_MB15_ID1)
-#define bfin_write_CAN0_MB15_ID1(val) bfin_write16(CAN0_MB15_ID1, val)
-
-/* CAN Controller 0 Mailbox Data Registers */
-
-#define bfin_read_CAN0_MB16_DATA0() bfin_read16(CAN0_MB16_DATA0)
-#define bfin_write_CAN0_MB16_DATA0(val) bfin_write16(CAN0_MB16_DATA0, val)
-#define bfin_read_CAN0_MB16_DATA1() bfin_read16(CAN0_MB16_DATA1)
-#define bfin_write_CAN0_MB16_DATA1(val) bfin_write16(CAN0_MB16_DATA1, val)
-#define bfin_read_CAN0_MB16_DATA2() bfin_read16(CAN0_MB16_DATA2)
-#define bfin_write_CAN0_MB16_DATA2(val) bfin_write16(CAN0_MB16_DATA2, val)
-#define bfin_read_CAN0_MB16_DATA3() bfin_read16(CAN0_MB16_DATA3)
-#define bfin_write_CAN0_MB16_DATA3(val) bfin_write16(CAN0_MB16_DATA3, val)
-#define bfin_read_CAN0_MB16_LENGTH() bfin_read16(CAN0_MB16_LENGTH)
-#define bfin_write_CAN0_MB16_LENGTH(val) bfin_write16(CAN0_MB16_LENGTH, val)
-#define bfin_read_CAN0_MB16_TIMESTAMP() bfin_read16(CAN0_MB16_TIMESTAMP)
-#define bfin_write_CAN0_MB16_TIMESTAMP(val) bfin_write16(CAN0_MB16_TIMESTAMP, val)
-#define bfin_read_CAN0_MB16_ID0() bfin_read16(CAN0_MB16_ID0)
-#define bfin_write_CAN0_MB16_ID0(val) bfin_write16(CAN0_MB16_ID0, val)
-#define bfin_read_CAN0_MB16_ID1() bfin_read16(CAN0_MB16_ID1)
-#define bfin_write_CAN0_MB16_ID1(val) bfin_write16(CAN0_MB16_ID1, val)
-#define bfin_read_CAN0_MB17_DATA0() bfin_read16(CAN0_MB17_DATA0)
-#define bfin_write_CAN0_MB17_DATA0(val) bfin_write16(CAN0_MB17_DATA0, val)
-#define bfin_read_CAN0_MB17_DATA1() bfin_read16(CAN0_MB17_DATA1)
-#define bfin_write_CAN0_MB17_DATA1(val) bfin_write16(CAN0_MB17_DATA1, val)
-#define bfin_read_CAN0_MB17_DATA2() bfin_read16(CAN0_MB17_DATA2)
-#define bfin_write_CAN0_MB17_DATA2(val) bfin_write16(CAN0_MB17_DATA2, val)
-#define bfin_read_CAN0_MB17_DATA3() bfin_read16(CAN0_MB17_DATA3)
-#define bfin_write_CAN0_MB17_DATA3(val) bfin_write16(CAN0_MB17_DATA3, val)
-#define bfin_read_CAN0_MB17_LENGTH() bfin_read16(CAN0_MB17_LENGTH)
-#define bfin_write_CAN0_MB17_LENGTH(val) bfin_write16(CAN0_MB17_LENGTH, val)
-#define bfin_read_CAN0_MB17_TIMESTAMP() bfin_read16(CAN0_MB17_TIMESTAMP)
-#define bfin_write_CAN0_MB17_TIMESTAMP(val) bfin_write16(CAN0_MB17_TIMESTAMP, val)
-#define bfin_read_CAN0_MB17_ID0() bfin_read16(CAN0_MB17_ID0)
-#define bfin_write_CAN0_MB17_ID0(val) bfin_write16(CAN0_MB17_ID0, val)
-#define bfin_read_CAN0_MB17_ID1() bfin_read16(CAN0_MB17_ID1)
-#define bfin_write_CAN0_MB17_ID1(val) bfin_write16(CAN0_MB17_ID1, val)
-#define bfin_read_CAN0_MB18_DATA0() bfin_read16(CAN0_MB18_DATA0)
-#define bfin_write_CAN0_MB18_DATA0(val) bfin_write16(CAN0_MB18_DATA0, val)
-#define bfin_read_CAN0_MB18_DATA1() bfin_read16(CAN0_MB18_DATA1)
-#define bfin_write_CAN0_MB18_DATA1(val) bfin_write16(CAN0_MB18_DATA1, val)
-#define bfin_read_CAN0_MB18_DATA2() bfin_read16(CAN0_MB18_DATA2)
-#define bfin_write_CAN0_MB18_DATA2(val) bfin_write16(CAN0_MB18_DATA2, val)
-#define bfin_read_CAN0_MB18_DATA3() bfin_read16(CAN0_MB18_DATA3)
-#define bfin_write_CAN0_MB18_DATA3(val) bfin_write16(CAN0_MB18_DATA3, val)
-#define bfin_read_CAN0_MB18_LENGTH() bfin_read16(CAN0_MB18_LENGTH)
-#define bfin_write_CAN0_MB18_LENGTH(val) bfin_write16(CAN0_MB18_LENGTH, val)
-#define bfin_read_CAN0_MB18_TIMESTAMP() bfin_read16(CAN0_MB18_TIMESTAMP)
-#define bfin_write_CAN0_MB18_TIMESTAMP(val) bfin_write16(CAN0_MB18_TIMESTAMP, val)
-#define bfin_read_CAN0_MB18_ID0() bfin_read16(CAN0_MB18_ID0)
-#define bfin_write_CAN0_MB18_ID0(val) bfin_write16(CAN0_MB18_ID0, val)
-#define bfin_read_CAN0_MB18_ID1() bfin_read16(CAN0_MB18_ID1)
-#define bfin_write_CAN0_MB18_ID1(val) bfin_write16(CAN0_MB18_ID1, val)
-#define bfin_read_CAN0_MB19_DATA0() bfin_read16(CAN0_MB19_DATA0)
-#define bfin_write_CAN0_MB19_DATA0(val) bfin_write16(CAN0_MB19_DATA0, val)
-#define bfin_read_CAN0_MB19_DATA1() bfin_read16(CAN0_MB19_DATA1)
-#define bfin_write_CAN0_MB19_DATA1(val) bfin_write16(CAN0_MB19_DATA1, val)
-#define bfin_read_CAN0_MB19_DATA2() bfin_read16(CAN0_MB19_DATA2)
-#define bfin_write_CAN0_MB19_DATA2(val) bfin_write16(CAN0_MB19_DATA2, val)
-#define bfin_read_CAN0_MB19_DATA3() bfin_read16(CAN0_MB19_DATA3)
-#define bfin_write_CAN0_MB19_DATA3(val) bfin_write16(CAN0_MB19_DATA3, val)
-#define bfin_read_CAN0_MB19_LENGTH() bfin_read16(CAN0_MB19_LENGTH)
-#define bfin_write_CAN0_MB19_LENGTH(val) bfin_write16(CAN0_MB19_LENGTH, val)
-#define bfin_read_CAN0_MB19_TIMESTAMP() bfin_read16(CAN0_MB19_TIMESTAMP)
-#define bfin_write_CAN0_MB19_TIMESTAMP(val) bfin_write16(CAN0_MB19_TIMESTAMP, val)
-#define bfin_read_CAN0_MB19_ID0() bfin_read16(CAN0_MB19_ID0)
-#define bfin_write_CAN0_MB19_ID0(val) bfin_write16(CAN0_MB19_ID0, val)
-#define bfin_read_CAN0_MB19_ID1() bfin_read16(CAN0_MB19_ID1)
-#define bfin_write_CAN0_MB19_ID1(val) bfin_write16(CAN0_MB19_ID1, val)
-#define bfin_read_CAN0_MB20_DATA0() bfin_read16(CAN0_MB20_DATA0)
-#define bfin_write_CAN0_MB20_DATA0(val) bfin_write16(CAN0_MB20_DATA0, val)
-#define bfin_read_CAN0_MB20_DATA1() bfin_read16(CAN0_MB20_DATA1)
-#define bfin_write_CAN0_MB20_DATA1(val) bfin_write16(CAN0_MB20_DATA1, val)
-#define bfin_read_CAN0_MB20_DATA2() bfin_read16(CAN0_MB20_DATA2)
-#define bfin_write_CAN0_MB20_DATA2(val) bfin_write16(CAN0_MB20_DATA2, val)
-#define bfin_read_CAN0_MB20_DATA3() bfin_read16(CAN0_MB20_DATA3)
-#define bfin_write_CAN0_MB20_DATA3(val) bfin_write16(CAN0_MB20_DATA3, val)
-#define bfin_read_CAN0_MB20_LENGTH() bfin_read16(CAN0_MB20_LENGTH)
-#define bfin_write_CAN0_MB20_LENGTH(val) bfin_write16(CAN0_MB20_LENGTH, val)
-#define bfin_read_CAN0_MB20_TIMESTAMP() bfin_read16(CAN0_MB20_TIMESTAMP)
-#define bfin_write_CAN0_MB20_TIMESTAMP(val) bfin_write16(CAN0_MB20_TIMESTAMP, val)
-#define bfin_read_CAN0_MB20_ID0() bfin_read16(CAN0_MB20_ID0)
-#define bfin_write_CAN0_MB20_ID0(val) bfin_write16(CAN0_MB20_ID0, val)
-#define bfin_read_CAN0_MB20_ID1() bfin_read16(CAN0_MB20_ID1)
-#define bfin_write_CAN0_MB20_ID1(val) bfin_write16(CAN0_MB20_ID1, val)
-#define bfin_read_CAN0_MB21_DATA0() bfin_read16(CAN0_MB21_DATA0)
-#define bfin_write_CAN0_MB21_DATA0(val) bfin_write16(CAN0_MB21_DATA0, val)
-#define bfin_read_CAN0_MB21_DATA1() bfin_read16(CAN0_MB21_DATA1)
-#define bfin_write_CAN0_MB21_DATA1(val) bfin_write16(CAN0_MB21_DATA1, val)
-#define bfin_read_CAN0_MB21_DATA2() bfin_read16(CAN0_MB21_DATA2)
-#define bfin_write_CAN0_MB21_DATA2(val) bfin_write16(CAN0_MB21_DATA2, val)
-#define bfin_read_CAN0_MB21_DATA3() bfin_read16(CAN0_MB21_DATA3)
-#define bfin_write_CAN0_MB21_DATA3(val) bfin_write16(CAN0_MB21_DATA3, val)
-#define bfin_read_CAN0_MB21_LENGTH() bfin_read16(CAN0_MB21_LENGTH)
-#define bfin_write_CAN0_MB21_LENGTH(val) bfin_write16(CAN0_MB21_LENGTH, val)
-#define bfin_read_CAN0_MB21_TIMESTAMP() bfin_read16(CAN0_MB21_TIMESTAMP)
-#define bfin_write_CAN0_MB21_TIMESTAMP(val) bfin_write16(CAN0_MB21_TIMESTAMP, val)
-#define bfin_read_CAN0_MB21_ID0() bfin_read16(CAN0_MB21_ID0)
-#define bfin_write_CAN0_MB21_ID0(val) bfin_write16(CAN0_MB21_ID0, val)
-#define bfin_read_CAN0_MB21_ID1() bfin_read16(CAN0_MB21_ID1)
-#define bfin_write_CAN0_MB21_ID1(val) bfin_write16(CAN0_MB21_ID1, val)
-#define bfin_read_CAN0_MB22_DATA0() bfin_read16(CAN0_MB22_DATA0)
-#define bfin_write_CAN0_MB22_DATA0(val) bfin_write16(CAN0_MB22_DATA0, val)
-#define bfin_read_CAN0_MB22_DATA1() bfin_read16(CAN0_MB22_DATA1)
-#define bfin_write_CAN0_MB22_DATA1(val) bfin_write16(CAN0_MB22_DATA1, val)
-#define bfin_read_CAN0_MB22_DATA2() bfin_read16(CAN0_MB22_DATA2)
-#define bfin_write_CAN0_MB22_DATA2(val) bfin_write16(CAN0_MB22_DATA2, val)
-#define bfin_read_CAN0_MB22_DATA3() bfin_read16(CAN0_MB22_DATA3)
-#define bfin_write_CAN0_MB22_DATA3(val) bfin_write16(CAN0_MB22_DATA3, val)
-#define bfin_read_CAN0_MB22_LENGTH() bfin_read16(CAN0_MB22_LENGTH)
-#define bfin_write_CAN0_MB22_LENGTH(val) bfin_write16(CAN0_MB22_LENGTH, val)
-#define bfin_read_CAN0_MB22_TIMESTAMP() bfin_read16(CAN0_MB22_TIMESTAMP)
-#define bfin_write_CAN0_MB22_TIMESTAMP(val) bfin_write16(CAN0_MB22_TIMESTAMP, val)
-#define bfin_read_CAN0_MB22_ID0() bfin_read16(CAN0_MB22_ID0)
-#define bfin_write_CAN0_MB22_ID0(val) bfin_write16(CAN0_MB22_ID0, val)
-#define bfin_read_CAN0_MB22_ID1() bfin_read16(CAN0_MB22_ID1)
-#define bfin_write_CAN0_MB22_ID1(val) bfin_write16(CAN0_MB22_ID1, val)
-#define bfin_read_CAN0_MB23_DATA0() bfin_read16(CAN0_MB23_DATA0)
-#define bfin_write_CAN0_MB23_DATA0(val) bfin_write16(CAN0_MB23_DATA0, val)
-#define bfin_read_CAN0_MB23_DATA1() bfin_read16(CAN0_MB23_DATA1)
-#define bfin_write_CAN0_MB23_DATA1(val) bfin_write16(CAN0_MB23_DATA1, val)
-#define bfin_read_CAN0_MB23_DATA2() bfin_read16(CAN0_MB23_DATA2)
-#define bfin_write_CAN0_MB23_DATA2(val) bfin_write16(CAN0_MB23_DATA2, val)
-#define bfin_read_CAN0_MB23_DATA3() bfin_read16(CAN0_MB23_DATA3)
-#define bfin_write_CAN0_MB23_DATA3(val) bfin_write16(CAN0_MB23_DATA3, val)
-#define bfin_read_CAN0_MB23_LENGTH() bfin_read16(CAN0_MB23_LENGTH)
-#define bfin_write_CAN0_MB23_LENGTH(val) bfin_write16(CAN0_MB23_LENGTH, val)
-#define bfin_read_CAN0_MB23_TIMESTAMP() bfin_read16(CAN0_MB23_TIMESTAMP)
-#define bfin_write_CAN0_MB23_TIMESTAMP(val) bfin_write16(CAN0_MB23_TIMESTAMP, val)
-#define bfin_read_CAN0_MB23_ID0() bfin_read16(CAN0_MB23_ID0)
-#define bfin_write_CAN0_MB23_ID0(val) bfin_write16(CAN0_MB23_ID0, val)
-#define bfin_read_CAN0_MB23_ID1() bfin_read16(CAN0_MB23_ID1)
-#define bfin_write_CAN0_MB23_ID1(val) bfin_write16(CAN0_MB23_ID1, val)
-#define bfin_read_CAN0_MB24_DATA0() bfin_read16(CAN0_MB24_DATA0)
-#define bfin_write_CAN0_MB24_DATA0(val) bfin_write16(CAN0_MB24_DATA0, val)
-#define bfin_read_CAN0_MB24_DATA1() bfin_read16(CAN0_MB24_DATA1)
-#define bfin_write_CAN0_MB24_DATA1(val) bfin_write16(CAN0_MB24_DATA1, val)
-#define bfin_read_CAN0_MB24_DATA2() bfin_read16(CAN0_MB24_DATA2)
-#define bfin_write_CAN0_MB24_DATA2(val) bfin_write16(CAN0_MB24_DATA2, val)
-#define bfin_read_CAN0_MB24_DATA3() bfin_read16(CAN0_MB24_DATA3)
-#define bfin_write_CAN0_MB24_DATA3(val) bfin_write16(CAN0_MB24_DATA3, val)
-#define bfin_read_CAN0_MB24_LENGTH() bfin_read16(CAN0_MB24_LENGTH)
-#define bfin_write_CAN0_MB24_LENGTH(val) bfin_write16(CAN0_MB24_LENGTH, val)
-#define bfin_read_CAN0_MB24_TIMESTAMP() bfin_read16(CAN0_MB24_TIMESTAMP)
-#define bfin_write_CAN0_MB24_TIMESTAMP(val) bfin_write16(CAN0_MB24_TIMESTAMP, val)
-#define bfin_read_CAN0_MB24_ID0() bfin_read16(CAN0_MB24_ID0)
-#define bfin_write_CAN0_MB24_ID0(val) bfin_write16(CAN0_MB24_ID0, val)
-#define bfin_read_CAN0_MB24_ID1() bfin_read16(CAN0_MB24_ID1)
-#define bfin_write_CAN0_MB24_ID1(val) bfin_write16(CAN0_MB24_ID1, val)
-#define bfin_read_CAN0_MB25_DATA0() bfin_read16(CAN0_MB25_DATA0)
-#define bfin_write_CAN0_MB25_DATA0(val) bfin_write16(CAN0_MB25_DATA0, val)
-#define bfin_read_CAN0_MB25_DATA1() bfin_read16(CAN0_MB25_DATA1)
-#define bfin_write_CAN0_MB25_DATA1(val) bfin_write16(CAN0_MB25_DATA1, val)
-#define bfin_read_CAN0_MB25_DATA2() bfin_read16(CAN0_MB25_DATA2)
-#define bfin_write_CAN0_MB25_DATA2(val) bfin_write16(CAN0_MB25_DATA2, val)
-#define bfin_read_CAN0_MB25_DATA3() bfin_read16(CAN0_MB25_DATA3)
-#define bfin_write_CAN0_MB25_DATA3(val) bfin_write16(CAN0_MB25_DATA3, val)
-#define bfin_read_CAN0_MB25_LENGTH() bfin_read16(CAN0_MB25_LENGTH)
-#define bfin_write_CAN0_MB25_LENGTH(val) bfin_write16(CAN0_MB25_LENGTH, val)
-#define bfin_read_CAN0_MB25_TIMESTAMP() bfin_read16(CAN0_MB25_TIMESTAMP)
-#define bfin_write_CAN0_MB25_TIMESTAMP(val) bfin_write16(CAN0_MB25_TIMESTAMP, val)
-#define bfin_read_CAN0_MB25_ID0() bfin_read16(CAN0_MB25_ID0)
-#define bfin_write_CAN0_MB25_ID0(val) bfin_write16(CAN0_MB25_ID0, val)
-#define bfin_read_CAN0_MB25_ID1() bfin_read16(CAN0_MB25_ID1)
-#define bfin_write_CAN0_MB25_ID1(val) bfin_write16(CAN0_MB25_ID1, val)
-#define bfin_read_CAN0_MB26_DATA0() bfin_read16(CAN0_MB26_DATA0)
-#define bfin_write_CAN0_MB26_DATA0(val) bfin_write16(CAN0_MB26_DATA0, val)
-#define bfin_read_CAN0_MB26_DATA1() bfin_read16(CAN0_MB26_DATA1)
-#define bfin_write_CAN0_MB26_DATA1(val) bfin_write16(CAN0_MB26_DATA1, val)
-#define bfin_read_CAN0_MB26_DATA2() bfin_read16(CAN0_MB26_DATA2)
-#define bfin_write_CAN0_MB26_DATA2(val) bfin_write16(CAN0_MB26_DATA2, val)
-#define bfin_read_CAN0_MB26_DATA3() bfin_read16(CAN0_MB26_DATA3)
-#define bfin_write_CAN0_MB26_DATA3(val) bfin_write16(CAN0_MB26_DATA3, val)
-#define bfin_read_CAN0_MB26_LENGTH() bfin_read16(CAN0_MB26_LENGTH)
-#define bfin_write_CAN0_MB26_LENGTH(val) bfin_write16(CAN0_MB26_LENGTH, val)
-#define bfin_read_CAN0_MB26_TIMESTAMP() bfin_read16(CAN0_MB26_TIMESTAMP)
-#define bfin_write_CAN0_MB26_TIMESTAMP(val) bfin_write16(CAN0_MB26_TIMESTAMP, val)
-#define bfin_read_CAN0_MB26_ID0() bfin_read16(CAN0_MB26_ID0)
-#define bfin_write_CAN0_MB26_ID0(val) bfin_write16(CAN0_MB26_ID0, val)
-#define bfin_read_CAN0_MB26_ID1() bfin_read16(CAN0_MB26_ID1)
-#define bfin_write_CAN0_MB26_ID1(val) bfin_write16(CAN0_MB26_ID1, val)
-#define bfin_read_CAN0_MB27_DATA0() bfin_read16(CAN0_MB27_DATA0)
-#define bfin_write_CAN0_MB27_DATA0(val) bfin_write16(CAN0_MB27_DATA0, val)
-#define bfin_read_CAN0_MB27_DATA1() bfin_read16(CAN0_MB27_DATA1)
-#define bfin_write_CAN0_MB27_DATA1(val) bfin_write16(CAN0_MB27_DATA1, val)
-#define bfin_read_CAN0_MB27_DATA2() bfin_read16(CAN0_MB27_DATA2)
-#define bfin_write_CAN0_MB27_DATA2(val) bfin_write16(CAN0_MB27_DATA2, val)
-#define bfin_read_CAN0_MB27_DATA3() bfin_read16(CAN0_MB27_DATA3)
-#define bfin_write_CAN0_MB27_DATA3(val) bfin_write16(CAN0_MB27_DATA3, val)
-#define bfin_read_CAN0_MB27_LENGTH() bfin_read16(CAN0_MB27_LENGTH)
-#define bfin_write_CAN0_MB27_LENGTH(val) bfin_write16(CAN0_MB27_LENGTH, val)
-#define bfin_read_CAN0_MB27_TIMESTAMP() bfin_read16(CAN0_MB27_TIMESTAMP)
-#define bfin_write_CAN0_MB27_TIMESTAMP(val) bfin_write16(CAN0_MB27_TIMESTAMP, val)
-#define bfin_read_CAN0_MB27_ID0() bfin_read16(CAN0_MB27_ID0)
-#define bfin_write_CAN0_MB27_ID0(val) bfin_write16(CAN0_MB27_ID0, val)
-#define bfin_read_CAN0_MB27_ID1() bfin_read16(CAN0_MB27_ID1)
-#define bfin_write_CAN0_MB27_ID1(val) bfin_write16(CAN0_MB27_ID1, val)
-#define bfin_read_CAN0_MB28_DATA0() bfin_read16(CAN0_MB28_DATA0)
-#define bfin_write_CAN0_MB28_DATA0(val) bfin_write16(CAN0_MB28_DATA0, val)
-#define bfin_read_CAN0_MB28_DATA1() bfin_read16(CAN0_MB28_DATA1)
-#define bfin_write_CAN0_MB28_DATA1(val) bfin_write16(CAN0_MB28_DATA1, val)
-#define bfin_read_CAN0_MB28_DATA2() bfin_read16(CAN0_MB28_DATA2)
-#define bfin_write_CAN0_MB28_DATA2(val) bfin_write16(CAN0_MB28_DATA2, val)
-#define bfin_read_CAN0_MB28_DATA3() bfin_read16(CAN0_MB28_DATA3)
-#define bfin_write_CAN0_MB28_DATA3(val) bfin_write16(CAN0_MB28_DATA3, val)
-#define bfin_read_CAN0_MB28_LENGTH() bfin_read16(CAN0_MB28_LENGTH)
-#define bfin_write_CAN0_MB28_LENGTH(val) bfin_write16(CAN0_MB28_LENGTH, val)
-#define bfin_read_CAN0_MB28_TIMESTAMP() bfin_read16(CAN0_MB28_TIMESTAMP)
-#define bfin_write_CAN0_MB28_TIMESTAMP(val) bfin_write16(CAN0_MB28_TIMESTAMP, val)
-#define bfin_read_CAN0_MB28_ID0() bfin_read16(CAN0_MB28_ID0)
-#define bfin_write_CAN0_MB28_ID0(val) bfin_write16(CAN0_MB28_ID0, val)
-#define bfin_read_CAN0_MB28_ID1() bfin_read16(CAN0_MB28_ID1)
-#define bfin_write_CAN0_MB28_ID1(val) bfin_write16(CAN0_MB28_ID1, val)
-#define bfin_read_CAN0_MB29_DATA0() bfin_read16(CAN0_MB29_DATA0)
-#define bfin_write_CAN0_MB29_DATA0(val) bfin_write16(CAN0_MB29_DATA0, val)
-#define bfin_read_CAN0_MB29_DATA1() bfin_read16(CAN0_MB29_DATA1)
-#define bfin_write_CAN0_MB29_DATA1(val) bfin_write16(CAN0_MB29_DATA1, val)
-#define bfin_read_CAN0_MB29_DATA2() bfin_read16(CAN0_MB29_DATA2)
-#define bfin_write_CAN0_MB29_DATA2(val) bfin_write16(CAN0_MB29_DATA2, val)
-#define bfin_read_CAN0_MB29_DATA3() bfin_read16(CAN0_MB29_DATA3)
-#define bfin_write_CAN0_MB29_DATA3(val) bfin_write16(CAN0_MB29_DATA3, val)
-#define bfin_read_CAN0_MB29_LENGTH() bfin_read16(CAN0_MB29_LENGTH)
-#define bfin_write_CAN0_MB29_LENGTH(val) bfin_write16(CAN0_MB29_LENGTH, val)
-#define bfin_read_CAN0_MB29_TIMESTAMP() bfin_read16(CAN0_MB29_TIMESTAMP)
-#define bfin_write_CAN0_MB29_TIMESTAMP(val) bfin_write16(CAN0_MB29_TIMESTAMP, val)
-#define bfin_read_CAN0_MB29_ID0() bfin_read16(CAN0_MB29_ID0)
-#define bfin_write_CAN0_MB29_ID0(val) bfin_write16(CAN0_MB29_ID0, val)
-#define bfin_read_CAN0_MB29_ID1() bfin_read16(CAN0_MB29_ID1)
-#define bfin_write_CAN0_MB29_ID1(val) bfin_write16(CAN0_MB29_ID1, val)
-#define bfin_read_CAN0_MB30_DATA0() bfin_read16(CAN0_MB30_DATA0)
-#define bfin_write_CAN0_MB30_DATA0(val) bfin_write16(CAN0_MB30_DATA0, val)
-#define bfin_read_CAN0_MB30_DATA1() bfin_read16(CAN0_MB30_DATA1)
-#define bfin_write_CAN0_MB30_DATA1(val) bfin_write16(CAN0_MB30_DATA1, val)
-#define bfin_read_CAN0_MB30_DATA2() bfin_read16(CAN0_MB30_DATA2)
-#define bfin_write_CAN0_MB30_DATA2(val) bfin_write16(CAN0_MB30_DATA2, val)
-#define bfin_read_CAN0_MB30_DATA3() bfin_read16(CAN0_MB30_DATA3)
-#define bfin_write_CAN0_MB30_DATA3(val) bfin_write16(CAN0_MB30_DATA3, val)
-#define bfin_read_CAN0_MB30_LENGTH() bfin_read16(CAN0_MB30_LENGTH)
-#define bfin_write_CAN0_MB30_LENGTH(val) bfin_write16(CAN0_MB30_LENGTH, val)
-#define bfin_read_CAN0_MB30_TIMESTAMP() bfin_read16(CAN0_MB30_TIMESTAMP)
-#define bfin_write_CAN0_MB30_TIMESTAMP(val) bfin_write16(CAN0_MB30_TIMESTAMP, val)
-#define bfin_read_CAN0_MB30_ID0() bfin_read16(CAN0_MB30_ID0)
-#define bfin_write_CAN0_MB30_ID0(val) bfin_write16(CAN0_MB30_ID0, val)
-#define bfin_read_CAN0_MB30_ID1() bfin_read16(CAN0_MB30_ID1)
-#define bfin_write_CAN0_MB30_ID1(val) bfin_write16(CAN0_MB30_ID1, val)
-#define bfin_read_CAN0_MB31_DATA0() bfin_read16(CAN0_MB31_DATA0)
-#define bfin_write_CAN0_MB31_DATA0(val) bfin_write16(CAN0_MB31_DATA0, val)
-#define bfin_read_CAN0_MB31_DATA1() bfin_read16(CAN0_MB31_DATA1)
-#define bfin_write_CAN0_MB31_DATA1(val) bfin_write16(CAN0_MB31_DATA1, val)
-#define bfin_read_CAN0_MB31_DATA2() bfin_read16(CAN0_MB31_DATA2)
-#define bfin_write_CAN0_MB31_DATA2(val) bfin_write16(CAN0_MB31_DATA2, val)
-#define bfin_read_CAN0_MB31_DATA3() bfin_read16(CAN0_MB31_DATA3)
-#define bfin_write_CAN0_MB31_DATA3(val) bfin_write16(CAN0_MB31_DATA3, val)
-#define bfin_read_CAN0_MB31_LENGTH() bfin_read16(CAN0_MB31_LENGTH)
-#define bfin_write_CAN0_MB31_LENGTH(val) bfin_write16(CAN0_MB31_LENGTH, val)
-#define bfin_read_CAN0_MB31_TIMESTAMP() bfin_read16(CAN0_MB31_TIMESTAMP)
-#define bfin_write_CAN0_MB31_TIMESTAMP(val) bfin_write16(CAN0_MB31_TIMESTAMP, val)
-#define bfin_read_CAN0_MB31_ID0() bfin_read16(CAN0_MB31_ID0)
-#define bfin_write_CAN0_MB31_ID0(val) bfin_write16(CAN0_MB31_ID0, val)
-#define bfin_read_CAN0_MB31_ID1() bfin_read16(CAN0_MB31_ID1)
-#define bfin_write_CAN0_MB31_ID1(val) bfin_write16(CAN0_MB31_ID1, val)
-
-/* Counter Registers */
-
-#define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG)
-#define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val)
-#define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK)
-#define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val)
-#define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS)
-#define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val)
-#define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND)
-#define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val)
-#define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE)
-#define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val)
-#define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER)
-#define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val)
-#define bfin_read_CNT_MAX() bfin_read32(CNT_MAX)
-#define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val)
-#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN)
-#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val)
-
-/* RSI Register */
-#define bfin_read_RSI_CLK_CTL() bfin_read16(RSI_CLK_CONTROL)
-#define bfin_write_RSI_CLK_CTL(val) bfin_write16(RSI_CLK_CONTROL, val)
-#define bfin_read_RSI_ARGUMENT() bfin_read32(RSI_ARGUMENT)
-#define bfin_write_RSI_ARGUMENT(val) bfin_write32(RSI_ARGUMENT, val)
-#define bfin_read_RSI_COMMAND() bfin_read16(RSI_COMMAND)
-#define bfin_write_RSI_COMMAND(val) bfin_write16(RSI_COMMAND, val)
-#define bfin_read_RSI_RESP_CMD() bfin_read16(RSI_RESP_CMD)
-#define bfin_write_RSI_RESP_CMD(val) bfin_write16(RSI_RESP_CMD, val)
-#define bfin_read_RSI_RESPONSE0() bfin_read32(RSI_RESPONSE0)
-#define bfin_write_RSI_RESPONSE0(val) bfin_write32(RSI_RESPONSE0, val)
-#define bfin_read_RSI_RESPONSE1() bfin_read32(RSI_RESPONSE1)
-#define bfin_write_RSI_RESPONSE1(val) bfin_write32(RSI_RESPONSE1, val)
-#define bfin_read_RSI_RESPONSE2() bfin_read32(RSI_RESPONSE2)
-#define bfin_write_RSI_RESPONSE2(val) bfin_write32(RSI_RESPONSE2, val)
-#define bfin_read_RSI_RESPONSE3() bfin_read32(RSI_RESPONSE3)
-#define bfin_write_RSI_RESPONSE3(val) bfin_write32(RSI_RESPONSE3, val)
-#define bfin_read_RSI_DATA_TIMER() bfin_read32(RSI_DATA_TIMER)
-#define bfin_write_RSI_DATA_TIMER(val) bfin_write32(RSI_DATA_TIMER, val)
-#define bfin_read_RSI_DATA_LGTH() bfin_read16(RSI_DATA_LGTH)
-#define bfin_write_RSI_DATA_LGTH(val) bfin_write16(RSI_DATA_LGTH, val)
-#define bfin_read_RSI_DATA_CTL() bfin_read16(RSI_DATA_CONTROL)
-#define bfin_write_RSI_DATA_CTL(val) bfin_write16(RSI_DATA_CONTROL, val)
-#define bfin_read_RSI_DATA_CNT() bfin_read16(RSI_DATA_CNT)
-#define bfin_write_RSI_DATA_CNT(val) bfin_write16(RSI_DATA_CNT, val)
-#define bfin_read_RSI_STATUS() bfin_read32(RSI_STATUS)
-#define bfin_write_RSI_STATUS(val) bfin_write32(RSI_STATUS, val)
-#define bfin_read_RSI_STATUS_CLR() bfin_read16(RSI_STATUSCL)
-#define bfin_write_RSI_STATUS_CLR(val) bfin_write16(RSI_STATUSCL, val)
-#define bfin_read_RSI_MASK0() bfin_read32(RSI_MASK0)
-#define bfin_write_RSI_MASK0(val) bfin_write32(RSI_MASK0, val)
-#define bfin_read_RSI_MASK1() bfin_read32(RSI_MASK1)
-#define bfin_write_RSI_MASK1(val) bfin_write32(RSI_MASK1, val)
-#define bfin_read_RSI_FIFO_CNT() bfin_read16(RSI_FIFO_CNT)
-#define bfin_write_RSI_FIFO_CNT(val) bfin_write16(RSI_FIFO_CNT, val)
-#define bfin_read_RSI_CEATA_CONTROL() bfin_read16(RSI_CEATA_CONTROL)
-#define bfin_write_RSI_CEATA_CONTROL(val) bfin_write16(RSI_CEATA_CONTROL, val)
-#define bfin_read_RSI_BLKSZ() bfin_read16(RSI_BLKSZ)
-#define bfin_write_RSI_BLKSZ(val) bfin_write16(RSI_BLKSZ, val)
-#define bfin_read_RSI_FIFO() bfin_read32(RSI_FIFO)
-#define bfin_write_RSI_FIFO(val) bfin_write32(RSI_FIFO, val)
-#define bfin_read_RSI_E_STATUS() bfin_read32(RSI_ESTAT)
-#define bfin_write_RSI_E_STATUS(val) bfin_write32(RSI_ESTAT, val)
-#define bfin_read_RSI_E_MASK() bfin_read32(RSI_EMASK)
-#define bfin_write_RSI_E_MASK(val) bfin_write32(RSI_EMASK, val)
-#define bfin_read_RSI_CFG() bfin_read16(RSI_CONFIG)
-#define bfin_write_RSI_CFG(val) bfin_write16(RSI_CONFIG, val)
-#define bfin_read_RSI_RD_WAIT_EN() bfin_read16(RSI_RD_WAIT_EN)
-#define bfin_write_RSI_RD_WAIT_EN(val) bfin_write16(RSI_RD_WAIT_EN, val)
-#define bfin_read_RSI_PID0() bfin_read16(RSI_PID0)
-#define bfin_write_RSI_PID0(val) bfin_write16(RSI_PID0, val)
-#define bfin_read_RSI_PID1() bfin_read16(RSI_PID1)
-#define bfin_write_RSI_PID1(val) bfin_write16(RSI_PID1, val)
-#define bfin_read_RSI_PID2() bfin_read16(RSI_PID2)
-#define bfin_write_RSI_PID2(val) bfin_write16(RSI_PID2, val)
-#define bfin_read_RSI_PID3() bfin_read16(RSI_PID3)
-#define bfin_write_RSI_PID3(val) bfin_write16(RSI_PID3, val)
-
-/* usb register */
-#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLL_OSC)
-#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLL_OSC, val)
-#define bfin_write_USB_VBUS_CTL(val) bfin_write8(USB_VBUS_CTL, val)
-#define bfin_write_USB_APHY_CNTRL(val) bfin_write8(USB_PHY_CTL, val)
-#define bfin_read_USB_APHY_CNTRL() bfin_read8(USB_PHY_CTL)
-
-#endif /* _CDEF_BF60X_H */
-
+++ /dev/null
-/*
- * Copyright 2011 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF609_H
-#define _DEF_BF609_H
-
-/* Include defBF60x_base.h for the set of #defines that are common to all ADSP-BF60x processors */
-#include "defBF60x_base.h"
-
-/* The following are the #defines needed by ADSP-BF609 that are not in the common header */
-/* =========================
- PIXC Registers
- ========================= */
-
-/* =========================
- PIXC0
- ========================= */
-#define PIXC0_CTL 0xFFC19000 /* PIXC0 Control Register */
-#define PIXC0_PPL 0xFFC19004 /* PIXC0 Pixels Per Line Register */
-#define PIXC0_LPF 0xFFC19008 /* PIXC0 Line Per Frame Register */
-#define PIXC0_HSTART_A 0xFFC1900C /* PIXC0 Overlay A Horizontal Start Register */
-#define PIXC0_HEND_A 0xFFC19010 /* PIXC0 Overlay A Horizontal End Register */
-#define PIXC0_VSTART_A 0xFFC19014 /* PIXC0 Overlay A Vertical Start Register */
-#define PIXC0_VEND_A 0xFFC19018 /* PIXC0 Overlay A Vertical End Register */
-#define PIXC0_TRANSP_A 0xFFC1901C /* PIXC0 Overlay A Transparency Ratio Register */
-#define PIXC0_HSTART_B 0xFFC19020 /* PIXC0 Overlay B Horizontal Start Register */
-#define PIXC0_HEND_B 0xFFC19024 /* PIXC0 Overlay B Horizontal End Register */
-#define PIXC0_VSTART_B 0xFFC19028 /* PIXC0 Overlay B Vertical Start Register */
-#define PIXC0_VEND_B 0xFFC1902C /* PIXC0 Overlay B Vertical End Register */
-#define PIXC0_TRANSP_B 0xFFC19030 /* PIXC0 Overlay B Transparency Ratio Register */
-#define PIXC0_IRQSTAT 0xFFC1903C /* PIXC0 Interrupt Status Register */
-#define PIXC0_CONRY 0xFFC19040 /* PIXC0 RY Conversion Component Register */
-#define PIXC0_CONGU 0xFFC19044 /* PIXC0 GU Conversion Component Register */
-#define PIXC0_CONBV 0xFFC19048 /* PIXC0 BV Conversion Component Register */
-#define PIXC0_CCBIAS 0xFFC1904C /* PIXC0 Conversion Bias Register */
-#define PIXC0_TC 0xFFC19050 /* PIXC0 Transparency Register */
-#define PIXC0_REVID 0xFFC19054 /* PIXC0 PIXC Revision Id */
-
-/* =========================
- PVP Registers
- ========================= */
-
-/* =========================
- PVP0
- ========================= */
-#define PVP0_REVID 0xFFC1A000 /* PVP0 Revision ID */
-#define PVP0_CTL 0xFFC1A004 /* PVP0 Control */
-#define PVP0_IMSK0 0xFFC1A008 /* PVP0 INTn interrupt line masks */
-#define PVP0_IMSK1 0xFFC1A00C /* PVP0 INTn interrupt line masks */
-#define PVP0_STAT 0xFFC1A010 /* PVP0 Status */
-#define PVP0_ILAT 0xFFC1A014 /* PVP0 Latched status */
-#define PVP0_IREQ0 0xFFC1A018 /* PVP0 INT0 masked latched status */
-#define PVP0_IREQ1 0xFFC1A01C /* PVP0 INT0 masked latched status */
-#define PVP0_OPF0_CFG 0xFFC1A020 /* PVP0 Config */
-#define PVP0_OPF1_CFG 0xFFC1A040 /* PVP0 Config */
-#define PVP0_OPF2_CFG 0xFFC1A060 /* PVP0 Config */
-#define PVP0_OPF0_CTL 0xFFC1A024 /* PVP0 Control */
-#define PVP0_OPF1_CTL 0xFFC1A044 /* PVP0 Control */
-#define PVP0_OPF2_CTL 0xFFC1A064 /* PVP0 Control */
-#define PVP0_OPF3_CFG 0xFFC1A080 /* PVP0 Config */
-#define PVP0_OPF3_CTL 0xFFC1A084 /* PVP0 Control */
-#define PVP0_PEC_CFG 0xFFC1A0A0 /* PVP0 Config */
-#define PVP0_PEC_CTL 0xFFC1A0A4 /* PVP0 Control */
-#define PVP0_PEC_D1TH0 0xFFC1A0A8 /* PVP0 Lower Hysteresis Threshold */
-#define PVP0_PEC_D1TH1 0xFFC1A0AC /* PVP0 Upper Hysteresis Threshold */
-#define PVP0_PEC_D2TH0 0xFFC1A0B0 /* PVP0 Weak Zero Crossing Threshold */
-#define PVP0_PEC_D2TH1 0xFFC1A0B4 /* PVP0 Strong Zero Crossing Threshold */
-#define PVP0_IIM0_CFG 0xFFC1A0C0 /* PVP0 Config */
-#define PVP0_IIM1_CFG 0xFFC1A0E0 /* PVP0 Config */
-#define PVP0_IIM0_CTL 0xFFC1A0C4 /* PVP0 Control */
-#define PVP0_IIM1_CTL 0xFFC1A0E4 /* PVP0 Control */
-#define PVP0_IIM0_SCALE 0xFFC1A0C8 /* PVP0 Scaler Values */
-#define PVP0_IIM1_SCALE 0xFFC1A0E8 /* PVP0 Scaler Values */
-#define PVP0_IIM0_SOVF_STAT 0xFFC1A0CC /* PVP0 Signed Overflow Status */
-#define PVP0_IIM1_SOVF_STAT 0xFFC1A0EC /* PVP0 Signed Overflow Status */
-#define PVP0_IIM0_UOVF_STAT 0xFFC1A0D0 /* PVP0 Unsigned Overflow Status */
-#define PVP0_IIM1_UOVF_STAT 0xFFC1A0F0 /* PVP0 Unsigned Overflow Status */
-#define PVP0_ACU_CFG 0xFFC1A100 /* PVP0 ACU Configuration Register */
-#define PVP0_ACU_CTL 0xFFC1A104 /* PVP0 ACU Control Register */
-#define PVP0_ACU_OFFSET 0xFFC1A108 /* PVP0 SUM constant register */
-#define PVP0_ACU_FACTOR 0xFFC1A10C /* PVP0 PROD constant register */
-#define PVP0_ACU_SHIFT 0xFFC1A110 /* PVP0 Shift constant register */
-#define PVP0_ACU_MIN 0xFFC1A114 /* PVP0 Lower saturation threshold set to MIN */
-#define PVP0_ACU_MAX 0xFFC1A118 /* PVP0 Upper saturation threshold set to MAX */
-#define PVP0_UDS_CFG 0xFFC1A140 /* PVP0 UDS Configuration Register */
-#define PVP0_UDS_CTL 0xFFC1A144 /* PVP0 UDS Control Register */
-#define PVP0_UDS_OHCNT 0xFFC1A148 /* PVP0 UDS Output H Dimension */
-#define PVP0_UDS_OVCNT 0xFFC1A14C /* PVP0 UDS Output V Dimension */
-#define PVP0_UDS_HAVG 0xFFC1A150 /* PVP0 UDS H Taps */
-#define PVP0_UDS_VAVG 0xFFC1A154 /* PVP0 UDS V Taps */
-#define PVP0_IPF0_CFG 0xFFC1A180 /* PVP0 Configuration */
-#define PVP0_IPF0_PIPECTL 0xFFC1A184 /* PVP0 Pipe Control */
-#define PVP0_IPF1_PIPECTL 0xFFC1A1C4 /* PVP0 Pipe Control */
-#define PVP0_IPF0_CTL 0xFFC1A188 /* PVP0 Control */
-#define PVP0_IPF1_CTL 0xFFC1A1C8 /* PVP0 Control */
-#define PVP0_IPF0_TAG 0xFFC1A18C /* PVP0 TAG Value */
-#define PVP0_IPF1_TAG 0xFFC1A1CC /* PVP0 TAG Value */
-#define PVP0_IPF0_FCNT 0xFFC1A190 /* PVP0 Frame Count */
-#define PVP0_IPF1_FCNT 0xFFC1A1D0 /* PVP0 Frame Count */
-#define PVP0_IPF0_HCNT 0xFFC1A194 /* PVP0 Horizontal Count */
-#define PVP0_IPF1_HCNT 0xFFC1A1D4 /* PVP0 Horizontal Count */
-#define PVP0_IPF0_VCNT 0xFFC1A198 /* PVP0 Vertical Count */
-#define PVP0_IPF1_VCNT 0xFFC1A1D8 /* PVP0 Vertical Count */
-#define PVP0_IPF0_HPOS 0xFFC1A19C /* PVP0 Horizontal Position */
-#define PVP0_IPF0_VPOS 0xFFC1A1A0 /* PVP0 Vertical Position */
-#define PVP0_IPF0_TAG_STAT 0xFFC1A1A4 /* PVP0 TAG Status */
-#define PVP0_IPF1_TAG_STAT 0xFFC1A1E4 /* PVP0 TAG Status */
-#define PVP0_IPF1_CFG 0xFFC1A1C0 /* PVP0 Configuration */
-#define PVP0_CNV0_CFG 0xFFC1A200 /* PVP0 Configuration */
-#define PVP0_CNV1_CFG 0xFFC1A280 /* PVP0 Configuration */
-#define PVP0_CNV2_CFG 0xFFC1A300 /* PVP0 Configuration */
-#define PVP0_CNV3_CFG 0xFFC1A380 /* PVP0 Configuration */
-#define PVP0_CNV0_CTL 0xFFC1A204 /* PVP0 Control */
-#define PVP0_CNV1_CTL 0xFFC1A284 /* PVP0 Control */
-#define PVP0_CNV2_CTL 0xFFC1A304 /* PVP0 Control */
-#define PVP0_CNV3_CTL 0xFFC1A384 /* PVP0 Control */
-#define PVP0_CNV0_C00C01 0xFFC1A208 /* PVP0 Coefficients 0, 0 and 0, 1 */
-#define PVP0_CNV1_C00C01 0xFFC1A288 /* PVP0 Coefficients 0, 0 and 0, 1 */
-#define PVP0_CNV2_C00C01 0xFFC1A308 /* PVP0 Coefficients 0, 0 and 0, 1 */
-#define PVP0_CNV3_C00C01 0xFFC1A388 /* PVP0 Coefficients 0, 0 and 0, 1 */
-#define PVP0_CNV0_C02C03 0xFFC1A20C /* PVP0 Coefficients 0, 2 and 0, 3 */
-#define PVP0_CNV1_C02C03 0xFFC1A28C /* PVP0 Coefficients 0, 2 and 0, 3 */
-#define PVP0_CNV2_C02C03 0xFFC1A30C /* PVP0 Coefficients 0, 2 and 0, 3 */
-#define PVP0_CNV3_C02C03 0xFFC1A38C /* PVP0 Coefficients 0, 2 and 0, 3 */
-#define PVP0_CNV0_C04 0xFFC1A210 /* PVP0 Coefficient 0, 4 */
-#define PVP0_CNV1_C04 0xFFC1A290 /* PVP0 Coefficient 0, 4 */
-#define PVP0_CNV2_C04 0xFFC1A310 /* PVP0 Coefficient 0, 4 */
-#define PVP0_CNV3_C04 0xFFC1A390 /* PVP0 Coefficient 0, 4 */
-#define PVP0_CNV0_C10C11 0xFFC1A214 /* PVP0 Coefficients 1, 0 and 1, 1 */
-#define PVP0_CNV1_C10C11 0xFFC1A294 /* PVP0 Coefficients 1, 0 and 1, 1 */
-#define PVP0_CNV2_C10C11 0xFFC1A314 /* PVP0 Coefficients 1, 0 and 1, 1 */
-#define PVP0_CNV3_C10C11 0xFFC1A394 /* PVP0 Coefficients 1, 0 and 1, 1 */
-#define PVP0_CNV0_C12C13 0xFFC1A218 /* PVP0 Coefficients 1, 2 and 1, 3 */
-#define PVP0_CNV1_C12C13 0xFFC1A298 /* PVP0 Coefficients 1, 2 and 1, 3 */
-#define PVP0_CNV2_C12C13 0xFFC1A318 /* PVP0 Coefficients 1, 2 and 1, 3 */
-#define PVP0_CNV3_C12C13 0xFFC1A398 /* PVP0 Coefficients 1, 2 and 1, 3 */
-#define PVP0_CNV0_C14 0xFFC1A21C /* PVP0 Coefficient 1, 4 */
-#define PVP0_CNV1_C14 0xFFC1A29C /* PVP0 Coefficient 1, 4 */
-#define PVP0_CNV2_C14 0xFFC1A31C /* PVP0 Coefficient 1, 4 */
-#define PVP0_CNV3_C14 0xFFC1A39C /* PVP0 Coefficient 1, 4 */
-#define PVP0_CNV0_C20C21 0xFFC1A220 /* PVP0 Coefficients 2, 0 and 2, 1 */
-#define PVP0_CNV1_C20C21 0xFFC1A2A0 /* PVP0 Coefficients 2, 0 and 2, 1 */
-#define PVP0_CNV2_C20C21 0xFFC1A320 /* PVP0 Coefficients 2, 0 and 2, 1 */
-#define PVP0_CNV3_C20C21 0xFFC1A3A0 /* PVP0 Coefficients 2, 0 and 2, 1 */
-#define PVP0_CNV0_C22C23 0xFFC1A224 /* PVP0 Coefficients 2, 2 and 2, 3 */
-#define PVP0_CNV1_C22C23 0xFFC1A2A4 /* PVP0 Coefficients 2, 2 and 2, 3 */
-#define PVP0_CNV2_C22C23 0xFFC1A324 /* PVP0 Coefficients 2, 2 and 2, 3 */
-#define PVP0_CNV3_C22C23 0xFFC1A3A4 /* PVP0 Coefficients 2, 2 and 2, 3 */
-#define PVP0_CNV0_C24 0xFFC1A228 /* PVP0 Coefficient 2,4 */
-#define PVP0_CNV1_C24 0xFFC1A2A8 /* PVP0 Coefficient 2,4 */
-#define PVP0_CNV2_C24 0xFFC1A328 /* PVP0 Coefficient 2,4 */
-#define PVP0_CNV3_C24 0xFFC1A3A8 /* PVP0 Coefficient 2,4 */
-#define PVP0_CNV0_C30C31 0xFFC1A22C /* PVP0 Coefficients 3, 0 and 3, 1 */
-#define PVP0_CNV1_C30C31 0xFFC1A2AC /* PVP0 Coefficients 3, 0 and 3, 1 */
-#define PVP0_CNV2_C30C31 0xFFC1A32C /* PVP0 Coefficients 3, 0 and 3, 1 */
-#define PVP0_CNV3_C30C31 0xFFC1A3AC /* PVP0 Coefficients 3, 0 and 3, 1 */
-#define PVP0_CNV0_C32C33 0xFFC1A230 /* PVP0 Coefficients 3, 2 and 3, 3 */
-#define PVP0_CNV1_C32C33 0xFFC1A2B0 /* PVP0 Coefficients 3, 2 and 3, 3 */
-#define PVP0_CNV2_C32C33 0xFFC1A330 /* PVP0 Coefficients 3, 2 and 3, 3 */
-#define PVP0_CNV3_C32C33 0xFFC1A3B0 /* PVP0 Coefficients 3, 2 and 3, 3 */
-#define PVP0_CNV0_C34 0xFFC1A234 /* PVP0 Coefficient 3, 4 */
-#define PVP0_CNV1_C34 0xFFC1A2B4 /* PVP0 Coefficient 3, 4 */
-#define PVP0_CNV2_C34 0xFFC1A334 /* PVP0 Coefficient 3, 4 */
-#define PVP0_CNV3_C34 0xFFC1A3B4 /* PVP0 Coefficient 3, 4 */
-#define PVP0_CNV0_C40C41 0xFFC1A238 /* PVP0 Coefficients 4, 0 and 4, 1 */
-#define PVP0_CNV1_C40C41 0xFFC1A2B8 /* PVP0 Coefficients 4, 0 and 4, 1 */
-#define PVP0_CNV2_C40C41 0xFFC1A338 /* PVP0 Coefficients 4, 0 and 4, 1 */
-#define PVP0_CNV3_C40C41 0xFFC1A3B8 /* PVP0 Coefficients 4, 0 and 4, 1 */
-#define PVP0_CNV0_C42C43 0xFFC1A23C /* PVP0 Coefficients 4, 2 and 4, 3 */
-#define PVP0_CNV1_C42C43 0xFFC1A2BC /* PVP0 Coefficients 4, 2 and 4, 3 */
-#define PVP0_CNV2_C42C43 0xFFC1A33C /* PVP0 Coefficients 4, 2 and 4, 3 */
-#define PVP0_CNV3_C42C43 0xFFC1A3BC /* PVP0 Coefficients 4, 2 and 4, 3 */
-#define PVP0_CNV0_C44 0xFFC1A240 /* PVP0 Coefficient 4, 4 */
-#define PVP0_CNV1_C44 0xFFC1A2C0 /* PVP0 Coefficient 4, 4 */
-#define PVP0_CNV2_C44 0xFFC1A340 /* PVP0 Coefficient 4, 4 */
-#define PVP0_CNV3_C44 0xFFC1A3C0 /* PVP0 Coefficient 4, 4 */
-#define PVP0_CNV0_SCALE 0xFFC1A244 /* PVP0 Scaling factor */
-#define PVP0_CNV1_SCALE 0xFFC1A2C4 /* PVP0 Scaling factor */
-#define PVP0_CNV2_SCALE 0xFFC1A344 /* PVP0 Scaling factor */
-#define PVP0_CNV3_SCALE 0xFFC1A3C4 /* PVP0 Scaling factor */
-#define PVP0_THC0_CFG 0xFFC1A400 /* PVP0 Configuration */
-#define PVP0_THC1_CFG 0xFFC1A500 /* PVP0 Configuration */
-#define PVP0_THC0_CTL 0xFFC1A404 /* PVP0 Control */
-#define PVP0_THC1_CTL 0xFFC1A504 /* PVP0 Control */
-#define PVP0_THC0_HFCNT 0xFFC1A408 /* PVP0 Number of frames */
-#define PVP0_THC1_HFCNT 0xFFC1A508 /* PVP0 Number of frames */
-#define PVP0_THC0_RMAXREP 0xFFC1A40C /* PVP0 Maximum number of RLE reports */
-#define PVP0_THC1_RMAXREP 0xFFC1A50C /* PVP0 Maximum number of RLE reports */
-#define PVP0_THC0_CMINVAL 0xFFC1A410 /* PVP0 Min clip value */
-#define PVP0_THC1_CMINVAL 0xFFC1A510 /* PVP0 Min clip value */
-#define PVP0_THC0_CMINTH 0xFFC1A414 /* PVP0 Clip Min Threshold */
-#define PVP0_THC1_CMINTH 0xFFC1A514 /* PVP0 Clip Min Threshold */
-#define PVP0_THC0_CMAXTH 0xFFC1A418 /* PVP0 Clip Max Threshold */
-#define PVP0_THC1_CMAXTH 0xFFC1A518 /* PVP0 Clip Max Threshold */
-#define PVP0_THC0_CMAXVAL 0xFFC1A41C /* PVP0 Max clip value */
-#define PVP0_THC1_CMAXVAL 0xFFC1A51C /* PVP0 Max clip value */
-#define PVP0_THC0_TH0 0xFFC1A420 /* PVP0 Threshold Value */
-#define PVP0_THC1_TH0 0xFFC1A520 /* PVP0 Threshold Value */
-#define PVP0_THC0_TH1 0xFFC1A424 /* PVP0 Threshold Value */
-#define PVP0_THC1_TH1 0xFFC1A524 /* PVP0 Threshold Value */
-#define PVP0_THC0_TH2 0xFFC1A428 /* PVP0 Threshold Value */
-#define PVP0_THC1_TH2 0xFFC1A528 /* PVP0 Threshold Value */
-#define PVP0_THC0_TH3 0xFFC1A42C /* PVP0 Threshold Value */
-#define PVP0_THC1_TH3 0xFFC1A52C /* PVP0 Threshold Value */
-#define PVP0_THC0_TH4 0xFFC1A430 /* PVP0 Threshold Value */
-#define PVP0_THC1_TH4 0xFFC1A530 /* PVP0 Threshold Value */
-#define PVP0_THC0_TH5 0xFFC1A434 /* PVP0 Threshold Value */
-#define PVP0_THC1_TH5 0xFFC1A534 /* PVP0 Threshold Value */
-#define PVP0_THC0_TH6 0xFFC1A438 /* PVP0 Threshold Value */
-#define PVP0_THC1_TH6 0xFFC1A538 /* PVP0 Threshold Value */
-#define PVP0_THC0_TH7 0xFFC1A43C /* PVP0 Threshold Value */
-#define PVP0_THC1_TH7 0xFFC1A53C /* PVP0 Threshold Value */
-#define PVP0_THC0_TH8 0xFFC1A440 /* PVP0 Threshold Value */
-#define PVP0_THC1_TH8 0xFFC1A540 /* PVP0 Threshold Value */
-#define PVP0_THC0_TH9 0xFFC1A444 /* PVP0 Threshold Value */
-#define PVP0_THC1_TH9 0xFFC1A544 /* PVP0 Threshold Value */
-#define PVP0_THC0_TH10 0xFFC1A448 /* PVP0 Threshold Value */
-#define PVP0_THC1_TH10 0xFFC1A548 /* PVP0 Threshold Value */
-#define PVP0_THC0_TH11 0xFFC1A44C /* PVP0 Threshold Value */
-#define PVP0_THC1_TH11 0xFFC1A54C /* PVP0 Threshold Value */
-#define PVP0_THC0_TH12 0xFFC1A450 /* PVP0 Threshold Value */
-#define PVP0_THC1_TH12 0xFFC1A550 /* PVP0 Threshold Value */
-#define PVP0_THC0_TH13 0xFFC1A454 /* PVP0 Threshold Value */
-#define PVP0_THC1_TH13 0xFFC1A554 /* PVP0 Threshold Value */
-#define PVP0_THC0_TH14 0xFFC1A458 /* PVP0 Threshold Value */
-#define PVP0_THC1_TH14 0xFFC1A558 /* PVP0 Threshold Value */
-#define PVP0_THC0_TH15 0xFFC1A45C /* PVP0 Threshold Value */
-#define PVP0_THC1_TH15 0xFFC1A55C /* PVP0 Threshold Value */
-#define PVP0_THC0_HHPOS 0xFFC1A460 /* PVP0 Window start X-coordinate */
-#define PVP0_THC1_HHPOS 0xFFC1A560 /* PVP0 Window start X-coordinate */
-#define PVP0_THC0_HVPOS 0xFFC1A464 /* PVP0 Window start Y-coordinate */
-#define PVP0_THC1_HVPOS 0xFFC1A564 /* PVP0 Window start Y-coordinate */
-#define PVP0_THC0_HHCNT 0xFFC1A468 /* PVP0 Window width in X dimension */
-#define PVP0_THC1_HHCNT 0xFFC1A568 /* PVP0 Window width in X dimension */
-#define PVP0_THC0_HVCNT 0xFFC1A46C /* PVP0 Window width in Y dimension */
-#define PVP0_THC1_HVCNT 0xFFC1A56C /* PVP0 Window width in Y dimension */
-#define PVP0_THC0_RHPOS 0xFFC1A470 /* PVP0 Window start X-coordinate */
-#define PVP0_THC1_RHPOS 0xFFC1A570 /* PVP0 Window start X-coordinate */
-#define PVP0_THC0_RVPOS 0xFFC1A474 /* PVP0 Window start Y-coordinate */
-#define PVP0_THC1_RVPOS 0xFFC1A574 /* PVP0 Window start Y-coordinate */
-#define PVP0_THC0_RHCNT 0xFFC1A478 /* PVP0 Window width in X dimension */
-#define PVP0_THC1_RHCNT 0xFFC1A578 /* PVP0 Window width in X dimension */
-#define PVP0_THC0_RVCNT 0xFFC1A47C /* PVP0 Window width in Y dimension */
-#define PVP0_THC1_RVCNT 0xFFC1A57C /* PVP0 Window width in Y dimension */
-#define PVP0_THC0_HFCNT_STAT 0xFFC1A480 /* PVP0 Current Frame counter */
-#define PVP0_THC1_HFCNT_STAT 0xFFC1A580 /* PVP0 Current Frame counter */
-#define PVP0_THC0_HCNT0_STAT 0xFFC1A484 /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT0_STAT 0xFFC1A584 /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT1_STAT 0xFFC1A488 /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT1_STAT 0xFFC1A588 /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT2_STAT 0xFFC1A48C /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT2_STAT 0xFFC1A58C /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT3_STAT 0xFFC1A490 /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT3_STAT 0xFFC1A590 /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT4_STAT 0xFFC1A494 /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT4_STAT 0xFFC1A594 /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT5_STAT 0xFFC1A498 /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT5_STAT 0xFFC1A598 /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT6_STAT 0xFFC1A49C /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT6_STAT 0xFFC1A59C /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT7_STAT 0xFFC1A4A0 /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT7_STAT 0xFFC1A5A0 /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT8_STAT 0xFFC1A4A4 /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT8_STAT 0xFFC1A5A4 /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT9_STAT 0xFFC1A4A8 /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT9_STAT 0xFFC1A5A8 /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT10_STAT 0xFFC1A4AC /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT10_STAT 0xFFC1A5AC /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT11_STAT 0xFFC1A4B0 /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT11_STAT 0xFFC1A5B0 /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT12_STAT 0xFFC1A4B4 /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT12_STAT 0xFFC1A5B4 /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT13_STAT 0xFFC1A4B8 /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT13_STAT 0xFFC1A5B8 /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT14_STAT 0xFFC1A4BC /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT14_STAT 0xFFC1A5BC /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT15_STAT 0xFFC1A4C0 /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT15_STAT 0xFFC1A5C0 /* PVP0 Histogram counter value */
-#define PVP0_THC0_RREP_STAT 0xFFC1A4C4 /* PVP0 Number of RLE Reports */
-#define PVP0_THC1_RREP_STAT 0xFFC1A5C4 /* PVP0 Number of RLE Reports */
-#define PVP0_PMA_CFG 0xFFC1A600 /* PVP0 PMA Configuration Register */
-
-#endif /* _DEF_BF609_H */
+++ /dev/null
-/*
- * Copyright 2011 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF60X_H
-#define _DEF_BF60X_H
-
-
-/* ************************************************************** */
-/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF60x */
-/* ************************************************************** */
-
-
-/* =========================
- CNT Registers
- ========================= */
-
-/* =========================
- CNT0
- ========================= */
-#define CNT_CONFIG 0xFFC00400 /* CNT0 Configuration Register */
-#define CNT_IMASK 0xFFC00404 /* CNT0 Interrupt Mask Register */
-#define CNT_STATUS 0xFFC00408 /* CNT0 Status Register */
-#define CNT_COMMAND 0xFFC0040C /* CNT0 Command Register */
-#define CNT_DEBOUNCE 0xFFC00410 /* CNT0 Debounce Register */
-#define CNT_COUNTER 0xFFC00414 /* CNT0 Counter Register */
-#define CNT_MAX 0xFFC00418 /* CNT0 Maximum Count Register */
-#define CNT_MIN 0xFFC0041C /* CNT0 Minimum Count Register */
-
-
-/* =========================
- RSI Registers
- ========================= */
-
-#define RSI_CLK_CONTROL 0xFFC00604 /* RSI0 Clock Control Register */
-#define RSI_ARGUMENT 0xFFC00608 /* RSI0 Argument Register */
-#define RSI_COMMAND 0xFFC0060C /* RSI0 Command Register */
-#define RSI_RESP_CMD 0xFFC00610 /* RSI0 Response Command Register */
-#define RSI_RESPONSE0 0xFFC00614 /* RSI0 Response 0 Register */
-#define RSI_RESPONSE1 0xFFC00618 /* RSI0 Response 1 Register */
-#define RSI_RESPONSE2 0xFFC0061C /* RSI0 Response 2 Register */
-#define RSI_RESPONSE3 0xFFC00620 /* RSI0 Response 3 Register */
-#define RSI_DATA_TIMER 0xFFC00624 /* RSI0 Data Timer Register */
-#define RSI_DATA_LGTH 0xFFC00628 /* RSI0 Data Length Register */
-#define RSI_DATA_CONTROL 0xFFC0062C /* RSI0 Data Control Register */
-#define RSI_DATA_CNT 0xFFC00630 /* RSI0 Data Count Register */
-#define RSI_STATUS 0xFFC00634 /* RSI0 Status Register */
-#define RSI_STATUSCL 0xFFC00638 /* RSI0 Status Clear Register */
-#define RSI_MASK0 0xFFC0063C /* RSI0 Interrupt 0 Mask Register */
-#define RSI_MASK1 0xFFC00640 /* RSI0 Interrupt 1 Mask Register */
-#define RSI_FIFO_CNT 0xFFC00648 /* RSI0 FIFO Counter Register */
-#define RSI_CEATA_CONTROL 0xFFC0064C /* RSI0 This register contains bit to dis CCS gen */
-#define RSI_BOOT_TCNTR 0xFFC00650 /* RSI0 Boot Timing Counter Register */
-#define RSI_BACK_TOUT 0xFFC00654 /* RSI0 Boot Acknowledge Timeout Register */
-#define RSI_SLP_WKUP_TOUT 0xFFC00658 /* RSI0 Sleep Wakeup Timeout Register */
-#define RSI_BLKSZ 0xFFC0065C /* RSI0 Block Size Register */
-#define RSI_FIFO 0xFFC00680 /* RSI0 Data FIFO Register */
-#define RSI_ESTAT 0xFFC006C0 /* RSI0 Exception Status Register */
-#define RSI_EMASK 0xFFC006C4 /* RSI0 Exception Mask Register */
-#define RSI_CONFIG 0xFFC006C8 /* RSI0 Configuration Register */
-#define RSI_RD_WAIT_EN 0xFFC006CC /* RSI0 Read Wait Enable Register */
-#define RSI_PID0 0xFFC006D0 /* RSI0 Peripheral Identification Register */
-#define RSI_PID1 0xFFC006D4 /* RSI0 Peripheral Identification Register */
-#define RSI_PID2 0xFFC006D8 /* RSI0 Peripheral Identification Register */
-#define RSI_PID3 0xFFC006DC /* RSI0 Peripheral Identification Register */
-
-/* =========================
- CAN Registers
- ========================= */
-
-/* =========================
- CAN0
- ========================= */
-#define CAN0_MC1 0xFFC00A00 /* CAN0 Mailbox Configuration Register 1 */
-#define CAN0_MD1 0xFFC00A04 /* CAN0 Mailbox Direction Register 1 */
-#define CAN0_TRS1 0xFFC00A08 /* CAN0 Transmission Request Set Register 1 */
-#define CAN0_TRR1 0xFFC00A0C /* CAN0 Transmission Request Reset Register 1 */
-#define CAN0_TA1 0xFFC00A10 /* CAN0 Transmission Acknowledge Register 1 */
-#define CAN0_AA1 0xFFC00A14 /* CAN0 Abort Acknowledge Register 1 */
-#define CAN0_RMP1 0xFFC00A18 /* CAN0 Receive Message Pending Register 1 */
-#define CAN0_RML1 0xFFC00A1C /* CAN0 Receive Message Lost Register 1 */
-#define CAN0_MBTIF1 0xFFC00A20 /* CAN0 Mailbox Transmit Interrupt Flag Register 1 */
-#define CAN0_MBRIF1 0xFFC00A24 /* CAN0 Mailbox Receive Interrupt Flag Register 1 */
-#define CAN0_MBIM1 0xFFC00A28 /* CAN0 Mailbox Interrupt Mask Register 1 */
-#define CAN0_RFH1 0xFFC00A2C /* CAN0 Remote Frame Handling Register 1 */
-#define CAN0_OPSS1 0xFFC00A30 /* CAN0 Overwrite Protection/Single Shot Transmission Register 1 */
-#define CAN0_MC2 0xFFC00A40 /* CAN0 Mailbox Configuration Register 2 */
-#define CAN0_MD2 0xFFC00A44 /* CAN0 Mailbox Direction Register 2 */
-#define CAN0_TRS2 0xFFC00A48 /* CAN0 Transmission Request Set Register 2 */
-#define CAN0_TRR2 0xFFC00A4C /* CAN0 Transmission Request Reset Register 2 */
-#define CAN0_TA2 0xFFC00A50 /* CAN0 Transmission Acknowledge Register 2 */
-#define CAN0_AA2 0xFFC00A54 /* CAN0 Abort Acknowledge Register 2 */
-#define CAN0_RMP2 0xFFC00A58 /* CAN0 Receive Message Pending Register 2 */
-#define CAN0_RML2 0xFFC00A5C /* CAN0 Receive Message Lost Register 2 */
-#define CAN0_MBTIF2 0xFFC00A60 /* CAN0 Mailbox Transmit Interrupt Flag Register 2 */
-#define CAN0_MBRIF2 0xFFC00A64 /* CAN0 Mailbox Receive Interrupt Flag Register 2 */
-#define CAN0_MBIM2 0xFFC00A68 /* CAN0 Mailbox Interrupt Mask Register 2 */
-#define CAN0_RFH2 0xFFC00A6C /* CAN0 Remote Frame Handling Register 2 */
-#define CAN0_OPSS2 0xFFC00A70 /* CAN0 Overwrite Protection/Single Shot Transmission Register 2 */
-#define CAN0_CLOCK 0xFFC00A80 /* CAN0 Clock Register */
-#define CAN0_TIMING 0xFFC00A84 /* CAN0 Timing Register */
-#define CAN0_DEBUG 0xFFC00A88 /* CAN0 Debug Register */
-#define CAN0_STATUS 0xFFC00A8C /* CAN0 Status Register */
-#define CAN0_CEC 0xFFC00A90 /* CAN0 Error Counter Register */
-#define CAN0_GIS 0xFFC00A94 /* CAN0 Global CAN Interrupt Status */
-#define CAN0_GIM 0xFFC00A98 /* CAN0 Global CAN Interrupt Mask */
-#define CAN0_GIF 0xFFC00A9C /* CAN0 Global CAN Interrupt Flag */
-#define CAN0_CONTROL 0xFFC00AA0 /* CAN0 CAN Master Control Register */
-#define CAN0_INTR 0xFFC00AA4 /* CAN0 Interrupt Pending Register */
-#define CAN0_MBTD 0xFFC00AAC /* CAN0 Temporary Mailbox Disable Register */
-#define CAN0_EWR 0xFFC00AB0 /* CAN0 Error Counter Warning Level Register */
-#define CAN0_ESR 0xFFC00AB4 /* CAN0 Error Status Register */
-#define CAN0_UCCNT 0xFFC00AC4 /* CAN0 Universal Counter Register */
-#define CAN0_UCRC 0xFFC00AC8 /* CAN0 Universal Counter Reload/Capture Register */
-#define CAN0_UCCNF 0xFFC00ACC /* CAN0 Universal Counter Configuration Mode Register */
-#define CAN0_AM00L 0xFFC00B00 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM01L 0xFFC00B08 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM02L 0xFFC00B10 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM03L 0xFFC00B18 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM04L 0xFFC00B20 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM05L 0xFFC00B28 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM06L 0xFFC00B30 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM07L 0xFFC00B38 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM08L 0xFFC00B40 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM09L 0xFFC00B48 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM10L 0xFFC00B50 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM11L 0xFFC00B58 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM12L 0xFFC00B60 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM13L 0xFFC00B68 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM14L 0xFFC00B70 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM15L 0xFFC00B78 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM16L 0xFFC00B80 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM17L 0xFFC00B88 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM18L 0xFFC00B90 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM19L 0xFFC00B98 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM20L 0xFFC00BA0 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM21L 0xFFC00BA8 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM22L 0xFFC00BB0 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM23L 0xFFC00BB8 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM24L 0xFFC00BC0 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM25L 0xFFC00BC8 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM26L 0xFFC00BD0 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM27L 0xFFC00BD8 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM28L 0xFFC00BE0 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM29L 0xFFC00BE8 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM30L 0xFFC00BF0 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM31L 0xFFC00BF8 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM00H 0xFFC00B04 /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM01H 0xFFC00B0C /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM02H 0xFFC00B14 /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM03H 0xFFC00B1C /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM04H 0xFFC00B24 /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM05H 0xFFC00B2C /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM06H 0xFFC00B34 /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM07H 0xFFC00B3C /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM08H 0xFFC00B44 /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM09H 0xFFC00B4C /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM10H 0xFFC00B54 /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM11H 0xFFC00B5C /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM12H 0xFFC00B64 /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM13H 0xFFC00B6C /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM14H 0xFFC00B74 /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM15H 0xFFC00B7C /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM16H 0xFFC00B84 /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM17H 0xFFC00B8C /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM18H 0xFFC00B94 /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM19H 0xFFC00B9C /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM20H 0xFFC00BA4 /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM21H 0xFFC00BAC /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM22H 0xFFC00BB4 /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM23H 0xFFC00BBC /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM24H 0xFFC00BC4 /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM25H 0xFFC00BCC /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM26H 0xFFC00BD4 /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM27H 0xFFC00BDC /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM28H 0xFFC00BE4 /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM29H 0xFFC00BEC /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM30H 0xFFC00BF4 /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM31H 0xFFC00BFC /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_MB00_DATA0 0xFFC00C00 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB01_DATA0 0xFFC00C20 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB02_DATA0 0xFFC00C40 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB03_DATA0 0xFFC00C60 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB04_DATA0 0xFFC00C80 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB05_DATA0 0xFFC00CA0 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB06_DATA0 0xFFC00CC0 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB07_DATA0 0xFFC00CE0 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB08_DATA0 0xFFC00D00 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB09_DATA0 0xFFC00D20 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB10_DATA0 0xFFC00D40 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB11_DATA0 0xFFC00D60 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB12_DATA0 0xFFC00D80 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB13_DATA0 0xFFC00DA0 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB14_DATA0 0xFFC00DC0 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB15_DATA0 0xFFC00DE0 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB16_DATA0 0xFFC00E00 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB17_DATA0 0xFFC00E20 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB18_DATA0 0xFFC00E40 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB19_DATA0 0xFFC00E60 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB20_DATA0 0xFFC00E80 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB21_DATA0 0xFFC00EA0 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB22_DATA0 0xFFC00EC0 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB23_DATA0 0xFFC00EE0 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB24_DATA0 0xFFC00F00 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB25_DATA0 0xFFC00F20 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB26_DATA0 0xFFC00F40 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB27_DATA0 0xFFC00F60 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB28_DATA0 0xFFC00F80 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB29_DATA0 0xFFC00FA0 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB30_DATA0 0xFFC00FC0 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB31_DATA0 0xFFC00FE0 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB00_DATA1 0xFFC00C04 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB01_DATA1 0xFFC00C24 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB02_DATA1 0xFFC00C44 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB03_DATA1 0xFFC00C64 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB04_DATA1 0xFFC00C84 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB05_DATA1 0xFFC00CA4 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB06_DATA1 0xFFC00CC4 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB07_DATA1 0xFFC00CE4 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB08_DATA1 0xFFC00D04 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB09_DATA1 0xFFC00D24 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB10_DATA1 0xFFC00D44 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB11_DATA1 0xFFC00D64 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB12_DATA1 0xFFC00D84 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB13_DATA1 0xFFC00DA4 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB14_DATA1 0xFFC00DC4 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB15_DATA1 0xFFC00DE4 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB16_DATA1 0xFFC00E04 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB17_DATA1 0xFFC00E24 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB18_DATA1 0xFFC00E44 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB19_DATA1 0xFFC00E64 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB20_DATA1 0xFFC00E84 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB21_DATA1 0xFFC00EA4 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB22_DATA1 0xFFC00EC4 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB23_DATA1 0xFFC00EE4 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB24_DATA1 0xFFC00F04 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB25_DATA1 0xFFC00F24 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB26_DATA1 0xFFC00F44 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB27_DATA1 0xFFC00F64 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB28_DATA1 0xFFC00F84 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB29_DATA1 0xFFC00FA4 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB30_DATA1 0xFFC00FC4 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB31_DATA1 0xFFC00FE4 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB00_DATA2 0xFFC00C08 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB01_DATA2 0xFFC00C28 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB02_DATA2 0xFFC00C48 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB03_DATA2 0xFFC00C68 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB04_DATA2 0xFFC00C88 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB05_DATA2 0xFFC00CA8 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB06_DATA2 0xFFC00CC8 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB07_DATA2 0xFFC00CE8 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB08_DATA2 0xFFC00D08 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB09_DATA2 0xFFC00D28 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB10_DATA2 0xFFC00D48 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB11_DATA2 0xFFC00D68 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB12_DATA2 0xFFC00D88 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB13_DATA2 0xFFC00DA8 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB14_DATA2 0xFFC00DC8 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB15_DATA2 0xFFC00DE8 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB16_DATA2 0xFFC00E08 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB17_DATA2 0xFFC00E28 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB18_DATA2 0xFFC00E48 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB19_DATA2 0xFFC00E68 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB20_DATA2 0xFFC00E88 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB21_DATA2 0xFFC00EA8 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB22_DATA2 0xFFC00EC8 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB23_DATA2 0xFFC00EE8 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB24_DATA2 0xFFC00F08 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB25_DATA2 0xFFC00F28 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB26_DATA2 0xFFC00F48 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB27_DATA2 0xFFC00F68 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB28_DATA2 0xFFC00F88 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB29_DATA2 0xFFC00FA8 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB30_DATA2 0xFFC00FC8 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB31_DATA2 0xFFC00FE8 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB00_DATA3 0xFFC00C0C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB01_DATA3 0xFFC00C2C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB02_DATA3 0xFFC00C4C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB03_DATA3 0xFFC00C6C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB04_DATA3 0xFFC00C8C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB05_DATA3 0xFFC00CAC /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB06_DATA3 0xFFC00CCC /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB07_DATA3 0xFFC00CEC /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB08_DATA3 0xFFC00D0C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB09_DATA3 0xFFC00D2C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB10_DATA3 0xFFC00D4C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB11_DATA3 0xFFC00D6C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB12_DATA3 0xFFC00D8C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB13_DATA3 0xFFC00DAC /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB14_DATA3 0xFFC00DCC /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB15_DATA3 0xFFC00DEC /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB16_DATA3 0xFFC00E0C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB17_DATA3 0xFFC00E2C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB18_DATA3 0xFFC00E4C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB19_DATA3 0xFFC00E6C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB20_DATA3 0xFFC00E8C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB21_DATA3 0xFFC00EAC /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB22_DATA3 0xFFC00ECC /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB23_DATA3 0xFFC00EEC /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB24_DATA3 0xFFC00F0C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB25_DATA3 0xFFC00F2C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB26_DATA3 0xFFC00F4C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB27_DATA3 0xFFC00F6C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB28_DATA3 0xFFC00F8C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB29_DATA3 0xFFC00FAC /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB30_DATA3 0xFFC00FCC /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB31_DATA3 0xFFC00FEC /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB00_LENGTH 0xFFC00C10 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB01_LENGTH 0xFFC00C30 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB02_LENGTH 0xFFC00C50 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB03_LENGTH 0xFFC00C70 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB04_LENGTH 0xFFC00C90 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB05_LENGTH 0xFFC00CB0 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB06_LENGTH 0xFFC00CD0 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB07_LENGTH 0xFFC00CF0 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB08_LENGTH 0xFFC00D10 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB09_LENGTH 0xFFC00D30 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB10_LENGTH 0xFFC00D50 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB11_LENGTH 0xFFC00D70 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB12_LENGTH 0xFFC00D90 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB13_LENGTH 0xFFC00DB0 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB14_LENGTH 0xFFC00DD0 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB15_LENGTH 0xFFC00DF0 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB16_LENGTH 0xFFC00E10 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB17_LENGTH 0xFFC00E30 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB18_LENGTH 0xFFC00E50 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB19_LENGTH 0xFFC00E70 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB20_LENGTH 0xFFC00E90 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB21_LENGTH 0xFFC00EB0 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB22_LENGTH 0xFFC00ED0 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB23_LENGTH 0xFFC00EF0 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB24_LENGTH 0xFFC00F10 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB25_LENGTH 0xFFC00F30 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB26_LENGTH 0xFFC00F50 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB27_LENGTH 0xFFC00F70 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB28_LENGTH 0xFFC00F90 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB29_LENGTH 0xFFC00FB0 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB30_LENGTH 0xFFC00FD0 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB31_LENGTH 0xFFC00FF0 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB00_TIMESTAMP 0xFFC00C14 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB01_TIMESTAMP 0xFFC00C34 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB02_TIMESTAMP 0xFFC00C54 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB03_TIMESTAMP 0xFFC00C74 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB04_TIMESTAMP 0xFFC00C94 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB05_TIMESTAMP 0xFFC00CB4 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB06_TIMESTAMP 0xFFC00CD4 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB07_TIMESTAMP 0xFFC00CF4 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB08_TIMESTAMP 0xFFC00D14 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB09_TIMESTAMP 0xFFC00D34 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB10_TIMESTAMP 0xFFC00D54 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB11_TIMESTAMP 0xFFC00D74 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB12_TIMESTAMP 0xFFC00D94 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB13_TIMESTAMP 0xFFC00DB4 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB14_TIMESTAMP 0xFFC00DD4 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB15_TIMESTAMP 0xFFC00DF4 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB16_TIMESTAMP 0xFFC00E14 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB17_TIMESTAMP 0xFFC00E34 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB18_TIMESTAMP 0xFFC00E54 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB19_TIMESTAMP 0xFFC00E74 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB20_TIMESTAMP 0xFFC00E94 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB21_TIMESTAMP 0xFFC00EB4 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB22_TIMESTAMP 0xFFC00ED4 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB23_TIMESTAMP 0xFFC00EF4 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB24_TIMESTAMP 0xFFC00F14 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB25_TIMESTAMP 0xFFC00F34 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB26_TIMESTAMP 0xFFC00F54 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB27_TIMESTAMP 0xFFC00F74 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB28_TIMESTAMP 0xFFC00F94 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB29_TIMESTAMP 0xFFC00FB4 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB30_TIMESTAMP 0xFFC00FD4 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB31_TIMESTAMP 0xFFC00FF4 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB00_ID0 0xFFC00C18 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB01_ID0 0xFFC00C38 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB02_ID0 0xFFC00C58 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB03_ID0 0xFFC00C78 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB04_ID0 0xFFC00C98 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB05_ID0 0xFFC00CB8 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB06_ID0 0xFFC00CD8 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB07_ID0 0xFFC00CF8 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB08_ID0 0xFFC00D18 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB09_ID0 0xFFC00D38 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB10_ID0 0xFFC00D58 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB11_ID0 0xFFC00D78 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB12_ID0 0xFFC00D98 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB13_ID0 0xFFC00DB8 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB14_ID0 0xFFC00DD8 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB15_ID0 0xFFC00DF8 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB16_ID0 0xFFC00E18 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB17_ID0 0xFFC00E38 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB18_ID0 0xFFC00E58 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB19_ID0 0xFFC00E78 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB20_ID0 0xFFC00E98 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB21_ID0 0xFFC00EB8 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB22_ID0 0xFFC00ED8 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB23_ID0 0xFFC00EF8 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB24_ID0 0xFFC00F18 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB25_ID0 0xFFC00F38 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB26_ID0 0xFFC00F58 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB27_ID0 0xFFC00F78 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB28_ID0 0xFFC00F98 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB29_ID0 0xFFC00FB8 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB30_ID0 0xFFC00FD8 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB31_ID0 0xFFC00FF8 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB00_ID1 0xFFC00C1C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB01_ID1 0xFFC00C3C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB02_ID1 0xFFC00C5C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB03_ID1 0xFFC00C7C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB04_ID1 0xFFC00C9C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB05_ID1 0xFFC00CBC /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB06_ID1 0xFFC00CDC /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB07_ID1 0xFFC00CFC /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB08_ID1 0xFFC00D1C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB09_ID1 0xFFC00D3C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB10_ID1 0xFFC00D5C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB11_ID1 0xFFC00D7C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB12_ID1 0xFFC00D9C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB13_ID1 0xFFC00DBC /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB14_ID1 0xFFC00DDC /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB15_ID1 0xFFC00DFC /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB16_ID1 0xFFC00E1C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB17_ID1 0xFFC00E3C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB18_ID1 0xFFC00E5C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB19_ID1 0xFFC00E7C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB20_ID1 0xFFC00E9C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB21_ID1 0xFFC00EBC /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB22_ID1 0xFFC00EDC /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB23_ID1 0xFFC00EFC /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB24_ID1 0xFFC00F1C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB25_ID1 0xFFC00F3C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB26_ID1 0xFFC00F5C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB27_ID1 0xFFC00F7C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB28_ID1 0xFFC00F9C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB29_ID1 0xFFC00FBC /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB30_ID1 0xFFC00FDC /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB31_ID1 0xFFC00FFC /* CAN0 Mailbox Word 7 Register */
-
-/* =========================
- LINK PORT Registers
- ========================= */
-#define LP0_CTL 0xFFC01000 /* LP0 Control Register */
-#define LP0_STAT 0xFFC01004 /* LP0 Status Register */
-#define LP0_DIV 0xFFC01008 /* LP0 Clock Divider Value */
-#define LP0_CNT 0xFFC0100C /* LP0 Current Count Value of Clock Divider */
-#define LP0_TX 0xFFC01010 /* LP0 Transmit Buffer */
-#define LP0_RX 0xFFC01014 /* LP0 Receive Buffer */
-#define LP0_TXIN_SHDW 0xFFC01018 /* LP0 Shadow Input Transmit Buffer */
-#define LP0_TXOUT_SHDW 0xFFC0101C /* LP0 Shadow Output Transmit Buffer */
-#define LP1_CTL 0xFFC01100 /* LP1 Control Register */
-#define LP1_STAT 0xFFC01104 /* LP1 Status Register */
-#define LP1_DIV 0xFFC01108 /* LP1 Clock Divider Value */
-#define LP1_CNT 0xFFC0110C /* LP1 Current Count Value of Clock Divider */
-#define LP1_TX 0xFFC01110 /* LP1 Transmit Buffer */
-#define LP1_RX 0xFFC01114 /* LP1 Receive Buffer */
-#define LP1_TXIN_SHDW 0xFFC01118 /* LP1 Shadow Input Transmit Buffer */
-#define LP1_TXOUT_SHDW 0xFFC0111C /* LP1 Shadow Output Transmit Buffer */
-#define LP2_CTL 0xFFC01200 /* LP2 Control Register */
-#define LP2_STAT 0xFFC01204 /* LP2 Status Register */
-#define LP2_DIV 0xFFC01208 /* LP2 Clock Divider Value */
-#define LP2_CNT 0xFFC0120C /* LP2 Current Count Value of Clock Divider */
-#define LP2_TX 0xFFC01210 /* LP2 Transmit Buffer */
-#define LP2_RX 0xFFC01214 /* LP2 Receive Buffer */
-#define LP2_TXIN_SHDW 0xFFC01218 /* LP2 Shadow Input Transmit Buffer */
-#define LP2_TXOUT_SHDW 0xFFC0121C /* LP2 Shadow Output Transmit Buffer */
-#define LP3_CTL 0xFFC01300 /* LP3 Control Register */
-#define LP3_STAT 0xFFC01304 /* LP3 Status Register */
-#define LP3_DIV 0xFFC01308 /* LP3 Clock Divider Value */
-#define LP3_CNT 0xFFC0130C /* LP3 Current Count Value of Clock Divider */
-#define LP3_TX 0xFFC01310 /* LP3 Transmit Buffer */
-#define LP3_RX 0xFFC01314 /* LP3 Receive Buffer */
-#define LP3_TXIN_SHDW 0xFFC01318 /* LP3 Shadow Input Transmit Buffer */
-#define LP3_TXOUT_SHDW 0xFFC0131C /* LP3 Shadow Output Transmit Buffer */
-
-/* =========================
- TIMER Registers
- ========================= */
-#define TIMER_REVID 0xFFC01400 /* GPTIMER Timer IP Version ID */
-#define TIMER_RUN 0xFFC01404 /* GPTIMER Timer Run Register */
-#define TIMER_RUN_SET 0xFFC01408 /* GPTIMER Run Register Alias to Set */
-#define TIMER_RUN_CLR 0xFFC0140C /* GPTIMER Run Register Alias to Clear */
-#define TIMER_STOP_CFG 0xFFC01410 /* GPTIMER Stop Config Register */
-#define TIMER_STOP_CFG_SET 0xFFC01414 /* GPTIMER Stop Config Alias to Set */
-#define TIMER_STOP_CFG_CLR 0xFFC01418 /* GPTIMER Stop Config Alias to Clear */
-#define TIMER_DATA_IMSK 0xFFC0141C /* GPTIMER Data Interrupt Mask register */
-#define TIMER_STAT_IMSK 0xFFC01420 /* GPTIMER Status Interrupt Mask register */
-#define TIMER_TRG_MSK 0xFFC01424 /* GPTIMER Output Trigger Mask register */
-#define TIMER_TRG_IE 0xFFC01428 /* GPTIMER Slave Trigger Enable register */
-#define TIMER_DATA_ILAT 0xFFC0142C /* GPTIMER Data Interrupt Register */
-#define TIMER_STAT_ILAT 0xFFC01430 /* GPTIMER Status (Error) Interrupt Register */
-#define TIMER_ERR_TYPE 0xFFC01434 /* GPTIMER Register Indicating Type of Error */
-#define TIMER_BCAST_PER 0xFFC01438 /* GPTIMER Broadcast Period */
-#define TIMER_BCAST_WID 0xFFC0143C /* GPTIMER Broadcast Width */
-#define TIMER_BCAST_DLY 0xFFC01440 /* GPTIMER Broadcast Delay */
-
-/* =========================
- TIMER0~7
- ========================= */
-#define TIMER0_CONFIG 0xFFC01460 /* TIMER0 Per Timer Config Register */
-#define TIMER0_COUNTER 0xFFC01464 /* TIMER0 Per Timer Counter Register */
-#define TIMER0_PERIOD 0xFFC01468 /* TIMER0 Per Timer Period Register */
-#define TIMER0_WIDTH 0xFFC0146C /* TIMER0 Per Timer Width Register */
-#define TIMER0_DELAY 0xFFC01470 /* TIMER0 Per Timer Delay Register */
-
-#define TIMER1_CONFIG 0xFFC01480 /* TIMER1 Per Timer Config Register */
-#define TIMER1_COUNTER 0xFFC01484 /* TIMER1 Per Timer Counter Register */
-#define TIMER1_PERIOD 0xFFC01488 /* TIMER1 Per Timer Period Register */
-#define TIMER1_WIDTH 0xFFC0148C /* TIMER1 Per Timer Width Register */
-#define TIMER1_DELAY 0xFFC01490 /* TIMER1 Per Timer Delay Register */
-
-#define TIMER2_CONFIG 0xFFC014A0 /* TIMER2 Per Timer Config Register */
-#define TIMER2_COUNTER 0xFFC014A4 /* TIMER2 Per Timer Counter Register */
-#define TIMER2_PERIOD 0xFFC014A8 /* TIMER2 Per Timer Period Register */
-#define TIMER2_WIDTH 0xFFC014AC /* TIMER2 Per Timer Width Register */
-#define TIMER2_DELAY 0xFFC014B0 /* TIMER2 Per Timer Delay Register */
-
-#define TIMER3_CONFIG 0xFFC014C0 /* TIMER3 Per Timer Config Register */
-#define TIMER3_COUNTER 0xFFC014C4 /* TIMER3 Per Timer Counter Register */
-#define TIMER3_PERIOD 0xFFC014C8 /* TIMER3 Per Timer Period Register */
-#define TIMER3_WIDTH 0xFFC014CC /* TIMER3 Per Timer Width Register */
-#define TIMER3_DELAY 0xFFC014D0 /* TIMER3 Per Timer Delay Register */
-
-#define TIMER4_CONFIG 0xFFC014E0 /* TIMER4 Per Timer Config Register */
-#define TIMER4_COUNTER 0xFFC014E4 /* TIMER4 Per Timer Counter Register */
-#define TIMER4_PERIOD 0xFFC014E8 /* TIMER4 Per Timer Period Register */
-#define TIMER4_WIDTH 0xFFC014EC /* TIMER4 Per Timer Width Register */
-#define TIMER4_DELAY 0xFFC014F0 /* TIMER4 Per Timer Delay Register */
-
-#define TIMER5_CONFIG 0xFFC01500 /* TIMER5 Per Timer Config Register */
-#define TIMER5_COUNTER 0xFFC01504 /* TIMER5 Per Timer Counter Register */
-#define TIMER5_PERIOD 0xFFC01508 /* TIMER5 Per Timer Period Register */
-#define TIMER5_WIDTH 0xFFC0150C /* TIMER5 Per Timer Width Register */
-#define TIMER5_DELAY 0xFFC01510 /* TIMER5 Per Timer Delay Register */
-
-#define TIMER6_CONFIG 0xFFC01520 /* TIMER6 Per Timer Config Register */
-#define TIMER6_COUNTER 0xFFC01524 /* TIMER6 Per Timer Counter Register */
-#define TIMER6_PERIOD 0xFFC01528 /* TIMER6 Per Timer Period Register */
-#define TIMER6_WIDTH 0xFFC0152C /* TIMER6 Per Timer Width Register */
-#define TIMER6_DELAY 0xFFC01530 /* TIMER6 Per Timer Delay Register */
-
-#define TIMER7_CONFIG 0xFFC01540 /* TIMER7 Per Timer Config Register */
-#define TIMER7_COUNTER 0xFFC01544 /* TIMER7 Per Timer Counter Register */
-#define TIMER7_PERIOD 0xFFC01548 /* TIMER7 Per Timer Period Register */
-#define TIMER7_WIDTH 0xFFC0154C /* TIMER7 Per Timer Width Register */
-#define TIMER7_DELAY 0xFFC01550 /* TIMER7 Per Timer Delay Register */
-
-/* =========================
- CRC Registers
- ========================= */
-
-/* =========================
- CRC0
- ========================= */
-#define REG_CRC0_CTL 0xFFC01C00 /* CRC0 Control Register */
-#define REG_CRC0_DCNT 0xFFC01C04 /* CRC0 Data Word Count Register */
-#define REG_CRC0_DCNTRLD 0xFFC01C08 /* CRC0 Data Word Count Reload Register */
-#define REG_CRC0_COMP 0xFFC01C14 /* CRC0 DATA Compare Register */
-#define REG_CRC0_FILLVAL 0xFFC01C18 /* CRC0 Fill Value Register */
-#define REG_CRC0_DFIFO 0xFFC01C1C /* CRC0 DATA FIFO Register */
-#define REG_CRC0_INEN 0xFFC01C20 /* CRC0 Interrupt Enable Register */
-#define REG_CRC0_INEN_SET 0xFFC01C24 /* CRC0 Interrupt Enable Set Register */
-#define REG_CRC0_INEN_CLR 0xFFC01C28 /* CRC0 Interrupt Enable Clear Register */
-#define REG_CRC0_POLY 0xFFC01C2C /* CRC0 Polynomial Register */
-#define REG_CRC0_STAT 0xFFC01C40 /* CRC0 Status Register */
-#define REG_CRC0_DCNTCAP 0xFFC01C44 /* CRC0 DATA Count Capture Register */
-#define REG_CRC0_RESULT_FIN 0xFFC01C4C /* CRC0 Final CRC Result Register */
-#define REG_CRC0_RESULT_CUR 0xFFC01C50 /* CRC0 Current CRC Result Register */
-#define REG_CRC0_REVID 0xFFC01C60 /* CRC0 Revision ID Register */
-
-/* =========================
- CRC1
- ========================= */
-#define REG_CRC1_CTL 0xFFC01D00 /* CRC1 Control Register */
-#define REG_CRC1_DCNT 0xFFC01D04 /* CRC1 Data Word Count Register */
-#define REG_CRC1_DCNTRLD 0xFFC01D08 /* CRC1 Data Word Count Reload Register */
-#define REG_CRC1_COMP 0xFFC01D14 /* CRC1 DATA Compare Register */
-#define REG_CRC1_FILLVAL 0xFFC01D18 /* CRC1 Fill Value Register */
-#define REG_CRC1_DFIFO 0xFFC01D1C /* CRC1 DATA FIFO Register */
-#define REG_CRC1_INEN 0xFFC01D20 /* CRC1 Interrupt Enable Register */
-#define REG_CRC1_INEN_SET 0xFFC01D24 /* CRC1 Interrupt Enable Set Register */
-#define REG_CRC1_INEN_CLR 0xFFC01D28 /* CRC1 Interrupt Enable Clear Register */
-#define REG_CRC1_POLY 0xFFC01D2C /* CRC1 Polynomial Register */
-#define REG_CRC1_STAT 0xFFC01D40 /* CRC1 Status Register */
-#define REG_CRC1_DCNTCAP 0xFFC01D44 /* CRC1 DATA Count Capture Register */
-#define REG_CRC1_RESULT_FIN 0xFFC01D4C /* CRC1 Final CRC Result Register */
-#define REG_CRC1_RESULT_CUR 0xFFC01D50 /* CRC1 Current CRC Result Register */
-#define REG_CRC1_REVID 0xFFC01D60 /* CRC1 Revision ID Register */
-
-/* =========================
- TWI Registers
- ========================= */
-
-/* =========================
- TWI0
- ========================= */
-#define TWI0_CLKDIV 0xFFC01E00 /* TWI0 SCL Clock Divider */
-#define TWI0_CONTROL 0xFFC01E04 /* TWI0 Control Register */
-#define TWI0_SLAVE_CTL 0xFFC01E08 /* TWI0 Slave Mode Control Register */
-#define TWI0_SLAVE_STAT 0xFFC01E0C /* TWI0 Slave Mode Status Register */
-#define TWI0_SLAVE_ADDR 0xFFC01E10 /* TWI0 Slave Mode Address Register */
-#define TWI0_MASTER_CTL 0xFFC01E14 /* TWI0 Master Mode Control Registers */
-#define TWI0_MASTER_STAT 0xFFC01E18 /* TWI0 Master Mode Status Register */
-#define TWI0_MASTER_ADDR 0xFFC01E1C /* TWI0 Master Mode Address Register */
-#define TWI0_INT_STAT 0xFFC01E20 /* TWI0 Interrupt Status Register */
-#define TWI0_INT_MASK 0xFFC01E24 /* TWI0 Interrupt Mask Register */
-#define TWI0_FIFO_CTL 0xFFC01E28 /* TWI0 FIFO Control Register */
-#define TWI0_FIFO_STAT 0xFFC01E2C /* TWI0 FIFO Status Register */
-#define TWI0_XMT_DATA8 0xFFC01E80 /* TWI0 FIFO Transmit Data Single-Byte Register */
-#define TWI0_XMT_DATA16 0xFFC01E84 /* TWI0 FIFO Transmit Data Double-Byte Register */
-#define TWI0_RCV_DATA8 0xFFC01E88 /* TWI0 FIFO Transmit Data Single-Byte Register */
-#define TWI0_RCV_DATA16 0xFFC01E8C /* TWI0 FIFO Transmit Data Double-Byte Register */
-
-/* =========================
- TWI1
- ========================= */
-#define TWI1_CLKDIV 0xFFC01F00 /* TWI1 SCL Clock Divider */
-#define TWI1_CONTROL 0xFFC01F04 /* TWI1 Control Register */
-#define TWI1_SLAVE_CTL 0xFFC01F08 /* TWI1 Slave Mode Control Register */
-#define TWI1_SLAVE_STAT 0xFFC01F0C /* TWI1 Slave Mode Status Register */
-#define TWI1_SLAVE_ADDR 0xFFC01F10 /* TWI1 Slave Mode Address Register */
-#define TWI1_MASTER_CTL 0xFFC01F14 /* TWI1 Master Mode Control Registers */
-#define TWI1_MASTER_STAT 0xFFC01F18 /* TWI1 Master Mode Status Register */
-#define TWI1_MASTER_ADDR 0xFFC01F1C /* TWI1 Master Mode Address Register */
-#define TWI1_INT_STAT 0xFFC01F20 /* TWI1 Interrupt Status Register */
-#define TWI1_INT_MASK 0xFFC01F24 /* TWI1 Interrupt Mask Register */
-#define TWI1_FIFO_CTL 0xFFC01F28 /* TWI1 FIFO Control Register */
-#define TWI1_FIFO_STAT 0xFFC01F2C /* TWI1 FIFO Status Register */
-#define TWI1_XMT_DATA8 0xFFC01F80 /* TWI1 FIFO Transmit Data Single-Byte Register */
-#define TWI1_XMT_DATA16 0xFFC01F84 /* TWI1 FIFO Transmit Data Double-Byte Register */
-#define TWI1_RCV_DATA8 0xFFC01F88 /* TWI1 FIFO Transmit Data Single-Byte Register */
-#define TWI1_RCV_DATA16 0xFFC01F8C /* TWI1 FIFO Transmit Data Double-Byte Register */
-
-
-/* =========================
- UART Registers
- ========================= */
-
-/* =========================
- UART0
- ========================= */
-#define UART0_REVID 0xFFC02000 /* UART0 Revision ID Register */
-#define UART0_CTL 0xFFC02004 /* UART0 Control Register */
-#define UART0_STAT 0xFFC02008 /* UART0 Status Register */
-#define UART0_SCR 0xFFC0200C /* UART0 Scratch Register */
-#define UART0_CLK 0xFFC02010 /* UART0 Clock Rate Register */
-#define UART0_IER 0xFFC02014 /* UART0 Interrupt Mask Register */
-#define UART0_IER_SET 0xFFC02018 /* UART0 Interrupt Mask Set Register */
-#define UART0_IER_CLR 0xFFC0201C /* UART0 Interrupt Mask Clear Register */
-#define UART0_RBR 0xFFC02020 /* UART0 Receive Buffer Register */
-#define UART0_THR 0xFFC02024 /* UART0 Transmit Hold Register */
-#define UART0_TAIP 0xFFC02028 /* UART0 Transmit Address/Insert Pulse Register */
-#define UART0_TSR 0xFFC0202C /* UART0 Transmit Shift Register */
-#define UART0_RSR 0xFFC02030 /* UART0 Receive Shift Register */
-#define UART0_TXDIV 0xFFC02034 /* UART0 Transmit Clock Devider Register */
-#define UART0_RXDIV 0xFFC02038 /* UART0 Receive Clock Devider Register */
-
-/* =========================
- UART1
- ========================= */
-#define UART1_REVID 0xFFC02400 /* UART1 Revision ID Register */
-#define UART1_CTL 0xFFC02404 /* UART1 Control Register */
-#define UART1_STAT 0xFFC02408 /* UART1 Status Register */
-#define UART1_SCR 0xFFC0240C /* UART1 Scratch Register */
-#define UART1_CLK 0xFFC02410 /* UART1 Clock Rate Register */
-#define UART1_IER 0xFFC02414 /* UART1 Interrupt Mask Register */
-#define UART1_IER_SET 0xFFC02418 /* UART1 Interrupt Mask Set Register */
-#define UART1_IER_CLR 0xFFC0241C /* UART1 Interrupt Mask Clear Register */
-#define UART1_RBR 0xFFC02420 /* UART1 Receive Buffer Register */
-#define UART1_THR 0xFFC02424 /* UART1 Transmit Hold Register */
-#define UART1_TAIP 0xFFC02428 /* UART1 Transmit Address/Insert Pulse Register */
-#define UART1_TSR 0xFFC0242C /* UART1 Transmit Shift Register */
-#define UART1_RSR 0xFFC02430 /* UART1 Receive Shift Register */
-#define UART1_TXDIV 0xFFC02434 /* UART1 Transmit Clock Devider Register */
-#define UART1_RXDIV 0xFFC02438 /* UART1 Receive Clock Devider Register */
-
-
-/* =========================
- PORT Registers
- ========================= */
-
-/* =========================
- PORTA
- ========================= */
-#define PORTA_FER 0xFFC03000 /* PORTA Port x Function Enable Register */
-#define PORTA_FER_SET 0xFFC03004 /* PORTA Port x Function Enable Set Register */
-#define PORTA_FER_CLEAR 0xFFC03008 /* PORTA Port x Function Enable Clear Register */
-#define PORTA_DATA 0xFFC0300C /* PORTA Port x GPIO Data Register */
-#define PORTA_DATA_SET 0xFFC03010 /* PORTA Port x GPIO Data Set Register */
-#define PORTA_DATA_CLEAR 0xFFC03014 /* PORTA Port x GPIO Data Clear Register */
-#define PORTA_DIR 0xFFC03018 /* PORTA Port x GPIO Direction Register */
-#define PORTA_DIR_SET 0xFFC0301C /* PORTA Port x GPIO Direction Set Register */
-#define PORTA_DIR_CLEAR 0xFFC03020 /* PORTA Port x GPIO Direction Clear Register */
-#define PORTA_INEN 0xFFC03024 /* PORTA Port x GPIO Input Enable Register */
-#define PORTA_INEN_SET 0xFFC03028 /* PORTA Port x GPIO Input Enable Set Register */
-#define PORTA_INEN_CLEAR 0xFFC0302C /* PORTA Port x GPIO Input Enable Clear Register */
-#define PORTA_MUX 0xFFC03030 /* PORTA Port x Multiplexer Control Register */
-#define PORTA_DATA_TGL 0xFFC03034 /* PORTA Port x GPIO Input Enable Toggle Register */
-#define PORTA_POL 0xFFC03038 /* PORTA Port x GPIO Programming Inversion Register */
-#define PORTA_POL_SET 0xFFC0303C /* PORTA Port x GPIO Programming Inversion Set Register */
-#define PORTA_POL_CLEAR 0xFFC03040 /* PORTA Port x GPIO Programming Inversion Clear Register */
-#define PORTA_LOCK 0xFFC03044 /* PORTA Port x GPIO Lock Register */
-#define PORTA_REVID 0xFFC0307C /* PORTA Port x GPIO Revision ID */
-
-/* =========================
- PORTB
- ========================= */
-#define PORTB_FER 0xFFC03080 /* PORTB Port x Function Enable Register */
-#define PORTB_FER_SET 0xFFC03084 /* PORTB Port x Function Enable Set Register */
-#define PORTB_FER_CLEAR 0xFFC03088 /* PORTB Port x Function Enable Clear Register */
-#define PORTB_DATA 0xFFC0308C /* PORTB Port x GPIO Data Register */
-#define PORTB_DATA_SET 0xFFC03090 /* PORTB Port x GPIO Data Set Register */
-#define PORTB_DATA_CLEAR 0xFFC03094 /* PORTB Port x GPIO Data Clear Register */
-#define PORTB_DIR 0xFFC03098 /* PORTB Port x GPIO Direction Register */
-#define PORTB_DIR_SET 0xFFC0309C /* PORTB Port x GPIO Direction Set Register */
-#define PORTB_DIR_CLEAR 0xFFC030A0 /* PORTB Port x GPIO Direction Clear Register */
-#define PORTB_INEN 0xFFC030A4 /* PORTB Port x GPIO Input Enable Register */
-#define PORTB_INEN_SET 0xFFC030A8 /* PORTB Port x GPIO Input Enable Set Register */
-#define PORTB_INEN_CLEAR 0xFFC030AC /* PORTB Port x GPIO Input Enable Clear Register */
-#define PORTB_MUX 0xFFC030B0 /* PORTB Port x Multiplexer Control Register */
-#define PORTB_DATA_TGL 0xFFC030B4 /* PORTB Port x GPIO Input Enable Toggle Register */
-#define PORTB_POL 0xFFC030B8 /* PORTB Port x GPIO Programming Inversion Register */
-#define PORTB_POL_SET 0xFFC030BC /* PORTB Port x GPIO Programming Inversion Set Register */
-#define PORTB_POL_CLEAR 0xFFC030C0 /* PORTB Port x GPIO Programming Inversion Clear Register */
-#define PORTB_LOCK 0xFFC030C4 /* PORTB Port x GPIO Lock Register */
-#define PORTB_REVID 0xFFC030FC /* PORTB Port x GPIO Revision ID */
-
-/* =========================
- PORTC
- ========================= */
-#define PORTC_FER 0xFFC03100 /* PORTC Port x Function Enable Register */
-#define PORTC_FER_SET 0xFFC03104 /* PORTC Port x Function Enable Set Register */
-#define PORTC_FER_CLEAR 0xFFC03108 /* PORTC Port x Function Enable Clear Register */
-#define PORTC_DATA 0xFFC0310C /* PORTC Port x GPIO Data Register */
-#define PORTC_DATA_SET 0xFFC03110 /* PORTC Port x GPIO Data Set Register */
-#define PORTC_DATA_CLEAR 0xFFC03114 /* PORTC Port x GPIO Data Clear Register */
-#define PORTC_DIR 0xFFC03118 /* PORTC Port x GPIO Direction Register */
-#define PORTC_DIR_SET 0xFFC0311C /* PORTC Port x GPIO Direction Set Register */
-#define PORTC_DIR_CLEAR 0xFFC03120 /* PORTC Port x GPIO Direction Clear Register */
-#define PORTC_INEN 0xFFC03124 /* PORTC Port x GPIO Input Enable Register */
-#define PORTC_INEN_SET 0xFFC03128 /* PORTC Port x GPIO Input Enable Set Register */
-#define PORTC_INEN_CLEAR 0xFFC0312C /* PORTC Port x GPIO Input Enable Clear Register */
-#define PORTC_MUX 0xFFC03130 /* PORTC Port x Multiplexer Control Register */
-#define PORTC_DATA_TGL 0xFFC03134 /* PORTC Port x GPIO Input Enable Toggle Register */
-#define PORTC_POL 0xFFC03138 /* PORTC Port x GPIO Programming Inversion Register */
-#define PORTC_POL_SET 0xFFC0313C /* PORTC Port x GPIO Programming Inversion Set Register */
-#define PORTC_POL_CLEAR 0xFFC03140 /* PORTC Port x GPIO Programming Inversion Clear Register */
-#define PORTC_LOCK 0xFFC03144 /* PORTC Port x GPIO Lock Register */
-#define PORTC_REVID 0xFFC0317C /* PORTC Port x GPIO Revision ID */
-
-/* =========================
- PORTD
- ========================= */
-#define PORTD_FER 0xFFC03180 /* PORTD Port x Function Enable Register */
-#define PORTD_FER_SET 0xFFC03184 /* PORTD Port x Function Enable Set Register */
-#define PORTD_FER_CLEAR 0xFFC03188 /* PORTD Port x Function Enable Clear Register */
-#define PORTD_DATA 0xFFC0318C /* PORTD Port x GPIO Data Register */
-#define PORTD_DATA_SET 0xFFC03190 /* PORTD Port x GPIO Data Set Register */
-#define PORTD_DATA_CLEAR 0xFFC03194 /* PORTD Port x GPIO Data Clear Register */
-#define PORTD_DIR 0xFFC03198 /* PORTD Port x GPIO Direction Register */
-#define PORTD_DIR_SET 0xFFC0319C /* PORTD Port x GPIO Direction Set Register */
-#define PORTD_DIR_CLEAR 0xFFC031A0 /* PORTD Port x GPIO Direction Clear Register */
-#define PORTD_INEN 0xFFC031A4 /* PORTD Port x GPIO Input Enable Register */
-#define PORTD_INEN_SET 0xFFC031A8 /* PORTD Port x GPIO Input Enable Set Register */
-#define PORTD_INEN_CLEAR 0xFFC031AC /* PORTD Port x GPIO Input Enable Clear Register */
-#define PORTD_MUX 0xFFC031B0 /* PORTD Port x Multiplexer Control Register */
-#define PORTD_DATA_TGL 0xFFC031B4 /* PORTD Port x GPIO Input Enable Toggle Register */
-#define PORTD_POL 0xFFC031B8 /* PORTD Port x GPIO Programming Inversion Register */
-#define PORTD_POL_SET 0xFFC031BC /* PORTD Port x GPIO Programming Inversion Set Register */
-#define PORTD_POL_CLEAR 0xFFC031C0 /* PORTD Port x GPIO Programming Inversion Clear Register */
-#define PORTD_LOCK 0xFFC031C4 /* PORTD Port x GPIO Lock Register */
-#define PORTD_REVID 0xFFC031FC /* PORTD Port x GPIO Revision ID */
-
-/* =========================
- PORTE
- ========================= */
-#define PORTE_FER 0xFFC03200 /* PORTE Port x Function Enable Register */
-#define PORTE_FER_SET 0xFFC03204 /* PORTE Port x Function Enable Set Register */
-#define PORTE_FER_CLEAR 0xFFC03208 /* PORTE Port x Function Enable Clear Register */
-#define PORTE_DATA 0xFFC0320C /* PORTE Port x GPIO Data Register */
-#define PORTE_DATA_SET 0xFFC03210 /* PORTE Port x GPIO Data Set Register */
-#define PORTE_DATA_CLEAR 0xFFC03214 /* PORTE Port x GPIO Data Clear Register */
-#define PORTE_DIR 0xFFC03218 /* PORTE Port x GPIO Direction Register */
-#define PORTE_DIR_SET 0xFFC0321C /* PORTE Port x GPIO Direction Set Register */
-#define PORTE_DIR_CLEAR 0xFFC03220 /* PORTE Port x GPIO Direction Clear Register */
-#define PORTE_INEN 0xFFC03224 /* PORTE Port x GPIO Input Enable Register */
-#define PORTE_INEN_SET 0xFFC03228 /* PORTE Port x GPIO Input Enable Set Register */
-#define PORTE_INEN_CLEAR 0xFFC0322C /* PORTE Port x GPIO Input Enable Clear Register */
-#define PORTE_MUX 0xFFC03230 /* PORTE Port x Multiplexer Control Register */
-#define PORTE_DATA_TGL 0xFFC03234 /* PORTE Port x GPIO Input Enable Toggle Register */
-#define PORTE_POL 0xFFC03238 /* PORTE Port x GPIO Programming Inversion Register */
-#define PORTE_POL_SET 0xFFC0323C /* PORTE Port x GPIO Programming Inversion Set Register */
-#define PORTE_POL_CLEAR 0xFFC03240 /* PORTE Port x GPIO Programming Inversion Clear Register */
-#define PORTE_LOCK 0xFFC03244 /* PORTE Port x GPIO Lock Register */
-#define PORTE_REVID 0xFFC0327C /* PORTE Port x GPIO Revision ID */
-
-/* =========================
- PORTF
- ========================= */
-#define PORTF_FER 0xFFC03280 /* PORTF Port x Function Enable Register */
-#define PORTF_FER_SET 0xFFC03284 /* PORTF Port x Function Enable Set Register */
-#define PORTF_FER_CLEAR 0xFFC03288 /* PORTF Port x Function Enable Clear Register */
-#define PORTF_DATA 0xFFC0328C /* PORTF Port x GPIO Data Register */
-#define PORTF_DATA_SET 0xFFC03290 /* PORTF Port x GPIO Data Set Register */
-#define PORTF_DATA_CLEAR 0xFFC03294 /* PORTF Port x GPIO Data Clear Register */
-#define PORTF_DIR 0xFFC03298 /* PORTF Port x GPIO Direction Register */
-#define PORTF_DIR_SET 0xFFC0329C /* PORTF Port x GPIO Direction Set Register */
-#define PORTF_DIR_CLEAR 0xFFC032A0 /* PORTF Port x GPIO Direction Clear Register */
-#define PORTF_INEN 0xFFC032A4 /* PORTF Port x GPIO Input Enable Register */
-#define PORTF_INEN_SET 0xFFC032A8 /* PORTF Port x GPIO Input Enable Set Register */
-#define PORTF_INEN_CLEAR 0xFFC032AC /* PORTF Port x GPIO Input Enable Clear Register */
-#define PORTF_MUX 0xFFC032B0 /* PORTF Port x Multiplexer Control Register */
-#define PORTF_DATA_TGL 0xFFC032B4 /* PORTF Port x GPIO Input Enable Toggle Register */
-#define PORTF_POL 0xFFC032B8 /* PORTF Port x GPIO Programming Inversion Register */
-#define PORTF_POL_SET 0xFFC032BC /* PORTF Port x GPIO Programming Inversion Set Register */
-#define PORTF_POL_CLEAR 0xFFC032C0 /* PORTF Port x GPIO Programming Inversion Clear Register */
-#define PORTF_LOCK 0xFFC032C4 /* PORTF Port x GPIO Lock Register */
-#define PORTF_REVID 0xFFC032FC /* PORTF Port x GPIO Revision ID */
-
-/* =========================
- PORTG
- ========================= */
-#define PORTG_FER 0xFFC03300 /* PORTG Port x Function Enable Register */
-#define PORTG_FER_SET 0xFFC03304 /* PORTG Port x Function Enable Set Register */
-#define PORTG_FER_CLEAR 0xFFC03308 /* PORTG Port x Function Enable Clear Register */
-#define PORTG_DATA 0xFFC0330C /* PORTG Port x GPIO Data Register */
-#define PORTG_DATA_SET 0xFFC03310 /* PORTG Port x GPIO Data Set Register */
-#define PORTG_DATA_CLEAR 0xFFC03314 /* PORTG Port x GPIO Data Clear Register */
-#define PORTG_DIR 0xFFC03318 /* PORTG Port x GPIO Direction Register */
-#define PORTG_DIR_SET 0xFFC0331C /* PORTG Port x GPIO Direction Set Register */
-#define PORTG_DIR_CLEAR 0xFFC03320 /* PORTG Port x GPIO Direction Clear Register */
-#define PORTG_INEN 0xFFC03324 /* PORTG Port x GPIO Input Enable Register */
-#define PORTG_INEN_SET 0xFFC03328 /* PORTG Port x GPIO Input Enable Set Register */
-#define PORTG_INEN_CLEAR 0xFFC0332C /* PORTG Port x GPIO Input Enable Clear Register */
-#define PORTG_MUX 0xFFC03330 /* PORTG Port x Multiplexer Control Register */
-#define PORTG_DATA_TGL 0xFFC03334 /* PORTG Port x GPIO Input Enable Toggle Register */
-#define PORTG_POL 0xFFC03338 /* PORTG Port x GPIO Programming Inversion Register */
-#define PORTG_POL_SET 0xFFC0333C /* PORTG Port x GPIO Programming Inversion Set Register */
-#define PORTG_POL_CLEAR 0xFFC03340 /* PORTG Port x GPIO Programming Inversion Clear Register */
-#define PORTG_LOCK 0xFFC03344 /* PORTG Port x GPIO Lock Register */
-#define PORTG_REVID 0xFFC0337C /* PORTG Port x GPIO Revision ID */
-
-/* ==================================================
- Pads Controller Registers
- ================================================== */
-
-/* =========================
- PADS0
- ========================= */
-#define PADS0_EMAC_PTP_CLKSEL 0xFFC03404 /* PADS0 Clock Selection for EMAC and PTP */
-#define PADS0_TWI_VSEL 0xFFC03408 /* PADS0 TWI Voltage Selection */
-#define PADS0_PORTS_HYST 0xFFC03440 /* PADS0 Hysteresis Enable Register */
-
-/* =========================
- PINT Registers
- ========================= */
-
-/* =========================
- PINT0
- ========================= */
-#define PINT0_MASK_SET 0xFFC04000 /* PINT0 Pint Mask Set Register */
-#define PINT0_MASK_CLEAR 0xFFC04004 /* PINT0 Pint Mask Clear Register */
-#define PINT0_REQUEST 0xFFC04008 /* PINT0 Pint Request Register */
-#define PINT0_ASSIGN 0xFFC0400C /* PINT0 Pint Assign Register */
-#define PINT0_EDGE_SET 0xFFC04010 /* PINT0 Pint Edge Set Register */
-#define PINT0_EDGE_CLEAR 0xFFC04014 /* PINT0 Pint Edge Clear Register */
-#define PINT0_INVERT_SET 0xFFC04018 /* PINT0 Pint Invert Set Register */
-#define PINT0_INVERT_CLEAR 0xFFC0401C /* PINT0 Pint Invert Clear Register */
-#define PINT0_PINSTATE 0xFFC04020 /* PINT0 Pint Pinstate Register */
-#define PINT0_LATCH 0xFFC04024 /* PINT0 Pint Latch Register */
-
-/* =========================
- PINT1
- ========================= */
-#define PINT1_MASK_SET 0xFFC04100 /* PINT1 Pint Mask Set Register */
-#define PINT1_MASK_CLEAR 0xFFC04104 /* PINT1 Pint Mask Clear Register */
-#define PINT1_REQUEST 0xFFC04108 /* PINT1 Pint Request Register */
-#define PINT1_ASSIGN 0xFFC0410C /* PINT1 Pint Assign Register */
-#define PINT1_EDGE_SET 0xFFC04110 /* PINT1 Pint Edge Set Register */
-#define PINT1_EDGE_CLEAR 0xFFC04114 /* PINT1 Pint Edge Clear Register */
-#define PINT1_INVERT_SET 0xFFC04118 /* PINT1 Pint Invert Set Register */
-#define PINT1_INVERT_CLEAR 0xFFC0411C /* PINT1 Pint Invert Clear Register */
-#define PINT1_PINSTATE 0xFFC04120 /* PINT1 Pint Pinstate Register */
-#define PINT1_LATCH 0xFFC04124 /* PINT1 Pint Latch Register */
-
-/* =========================
- PINT2
- ========================= */
-#define PINT2_MASK_SET 0xFFC04200 /* PINT2 Pint Mask Set Register */
-#define PINT2_MASK_CLEAR 0xFFC04204 /* PINT2 Pint Mask Clear Register */
-#define PINT2_REQUEST 0xFFC04208 /* PINT2 Pint Request Register */
-#define PINT2_ASSIGN 0xFFC0420C /* PINT2 Pint Assign Register */
-#define PINT2_EDGE_SET 0xFFC04210 /* PINT2 Pint Edge Set Register */
-#define PINT2_EDGE_CLEAR 0xFFC04214 /* PINT2 Pint Edge Clear Register */
-#define PINT2_INVERT_SET 0xFFC04218 /* PINT2 Pint Invert Set Register */
-#define PINT2_INVERT_CLEAR 0xFFC0421C /* PINT2 Pint Invert Clear Register */
-#define PINT2_PINSTATE 0xFFC04220 /* PINT2 Pint Pinstate Register */
-#define PINT2_LATCH 0xFFC04224 /* PINT2 Pint Latch Register */
-
-/* =========================
- PINT3
- ========================= */
-#define PINT3_MASK_SET 0xFFC04300 /* PINT3 Pint Mask Set Register */
-#define PINT3_MASK_CLEAR 0xFFC04304 /* PINT3 Pint Mask Clear Register */
-#define PINT3_REQUEST 0xFFC04308 /* PINT3 Pint Request Register */
-#define PINT3_ASSIGN 0xFFC0430C /* PINT3 Pint Assign Register */
-#define PINT3_EDGE_SET 0xFFC04310 /* PINT3 Pint Edge Set Register */
-#define PINT3_EDGE_CLEAR 0xFFC04314 /* PINT3 Pint Edge Clear Register */
-#define PINT3_INVERT_SET 0xFFC04318 /* PINT3 Pint Invert Set Register */
-#define PINT3_INVERT_CLEAR 0xFFC0431C /* PINT3 Pint Invert Clear Register */
-#define PINT3_PINSTATE 0xFFC04320 /* PINT3 Pint Pinstate Register */
-#define PINT3_LATCH 0xFFC04324 /* PINT3 Pint Latch Register */
-
-/* =========================
- PINT4
- ========================= */
-#define PINT4_MASK_SET 0xFFC04400 /* PINT4 Pint Mask Set Register */
-#define PINT4_MASK_CLEAR 0xFFC04404 /* PINT4 Pint Mask Clear Register */
-#define PINT4_REQUEST 0xFFC04408 /* PINT4 Pint Request Register */
-#define PINT4_ASSIGN 0xFFC0440C /* PINT4 Pint Assign Register */
-#define PINT4_EDGE_SET 0xFFC04410 /* PINT4 Pint Edge Set Register */
-#define PINT4_EDGE_CLEAR 0xFFC04414 /* PINT4 Pint Edge Clear Register */
-#define PINT4_INVERT_SET 0xFFC04418 /* PINT4 Pint Invert Set Register */
-#define PINT4_INVERT_CLEAR 0xFFC0441C /* PINT4 Pint Invert Clear Register */
-#define PINT4_PINSTATE 0xFFC04420 /* PINT4 Pint Pinstate Register */
-#define PINT4_LATCH 0xFFC04424 /* PINT4 Pint Latch Register */
-
-/* =========================
- PINT5
- ========================= */
-#define PINT5_MASK_SET 0xFFC04500 /* PINT5 Pint Mask Set Register */
-#define PINT5_MASK_CLEAR 0xFFC04504 /* PINT5 Pint Mask Clear Register */
-#define PINT5_REQUEST 0xFFC04508 /* PINT5 Pint Request Register */
-#define PINT5_ASSIGN 0xFFC0450C /* PINT5 Pint Assign Register */
-#define PINT5_EDGE_SET 0xFFC04510 /* PINT5 Pint Edge Set Register */
-#define PINT5_EDGE_CLEAR 0xFFC04514 /* PINT5 Pint Edge Clear Register */
-#define PINT5_INVERT_SET 0xFFC04518 /* PINT5 Pint Invert Set Register */
-#define PINT5_INVERT_CLEAR 0xFFC0451C /* PINT5 Pint Invert Clear Register */
-#define PINT5_PINSTATE 0xFFC04520 /* PINT5 Pint Pinstate Register */
-#define PINT5_LATCH 0xFFC04524 /* PINT5 Pint Latch Register */
-
-
-/* =========================
- SMC Registers
- ========================= */
-
-/* =========================
- SMC0
- ========================= */
-#define SMC_GCTL 0xFFC16004 /* SMC0 SMC Control Register */
-#define SMC_GSTAT 0xFFC16008 /* SMC0 SMC Status Register */
-#define SMC_B0CTL 0xFFC1600C /* SMC0 SMC Bank0 Control Register */
-#define SMC_B0TIM 0xFFC16010 /* SMC0 SMC Bank0 Timing Register */
-#define SMC_B0ETIM 0xFFC16014 /* SMC0 SMC Bank0 Extended Timing Register */
-#define SMC_B1CTL 0xFFC1601C /* SMC0 SMC BANK1 Control Register */
-#define SMC_B1TIM 0xFFC16020 /* SMC0 SMC BANK1 Timing Register */
-#define SMC_B1ETIM 0xFFC16024 /* SMC0 SMC BANK1 Extended Timing Register */
-#define SMC_B2CTL 0xFFC1602C /* SMC0 SMC BANK2 Control Register */
-#define SMC_B2TIM 0xFFC16030 /* SMC0 SMC BANK2 Timing Register */
-#define SMC_B2ETIM 0xFFC16034 /* SMC0 SMC BANK2 Extended Timing Register */
-#define SMC_B3CTL 0xFFC1603C /* SMC0 SMC BANK3 Control Register */
-#define SMC_B3TIM 0xFFC16040 /* SMC0 SMC BANK3 Timing Register */
-#define SMC_B3ETIM 0xFFC16044 /* SMC0 SMC BANK3 Extended Timing Register */
-
-
-/* =========================
- WDOG Registers
- ========================= */
-
-/* =========================
- WDOG0
- ========================= */
-#define WDOG0_CTL 0xFFC17000 /* WDOG0 Control Register */
-#define WDOG0_CNT 0xFFC17004 /* WDOG0 Count Register */
-#define WDOG0_STAT 0xFFC17008 /* WDOG0 Watchdog Timer Status Register */
-#define WDOG_CTL WDOG0_CTL
-#define WDOG_CNT WDOG0_CNT
-#define WDOG_STAT WDOG0_STAT
-
-/* =========================
- WDOG1
- ========================= */
-#define WDOG1_CTL 0xFFC17800 /* WDOG1 Control Register */
-#define WDOG1_CNT 0xFFC17804 /* WDOG1 Count Register */
-#define WDOG1_STAT 0xFFC17808 /* WDOG1 Watchdog Timer Status Register */
-
-
-/* =========================
- SDU Registers
- ========================= */
-
-/* =========================
- SDU0
- ========================= */
-#define SDU0_IDCODE 0xFFC1F020 /* SDU0 ID Code Register */
-#define SDU0_CTL 0xFFC1F050 /* SDU0 Control Register */
-#define SDU0_STAT 0xFFC1F054 /* SDU0 Status Register */
-#define SDU0_MACCTL 0xFFC1F058 /* SDU0 Memory Access Control Register */
-#define SDU0_MACADDR 0xFFC1F05C /* SDU0 Memory Access Address Register */
-#define SDU0_MACDATA 0xFFC1F060 /* SDU0 Memory Access Data Register */
-#define SDU0_DMARD 0xFFC1F064 /* SDU0 DMA Read Data Register */
-#define SDU0_DMAWD 0xFFC1F068 /* SDU0 DMA Write Data Register */
-#define SDU0_MSG 0xFFC1F080 /* SDU0 Message Register */
-#define SDU0_MSG_SET 0xFFC1F084 /* SDU0 Message Set Register */
-#define SDU0_MSG_CLR 0xFFC1F088 /* SDU0 Message Clear Register */
-#define SDU0_GHLT 0xFFC1F08C /* SDU0 Group Halt Register */
-
-
-/* =========================
- EMAC Registers
- ========================= */
-/* =========================
- EMAC0
- ========================= */
-#define EMAC0_MACCFG 0xFFC20000 /* EMAC0 MAC Configuration Register */
-#define EMAC0_MACFRMFILT 0xFFC20004 /* EMAC0 Filter Register for filtering Received Frames */
-#define EMAC0_HASHTBL_HI 0xFFC20008 /* EMAC0 Contains the Upper 32 bits of the hash table */
-#define EMAC0_HASHTBL_LO 0xFFC2000C /* EMAC0 Contains the lower 32 bits of the hash table */
-#define EMAC0_GMII_ADDR 0xFFC20010 /* EMAC0 Management Address Register */
-#define EMAC0_GMII_DATA 0xFFC20014 /* EMAC0 Management Data Register */
-#define EMAC0_FLOWCTL 0xFFC20018 /* EMAC0 MAC FLow Control Register */
-#define EMAC0_VLANTAG 0xFFC2001C /* EMAC0 VLAN Tag Register */
-#define EMAC0_VER 0xFFC20020 /* EMAC0 EMAC Version Register */
-#define EMAC0_DBG 0xFFC20024 /* EMAC0 EMAC Debug Register */
-#define EMAC0_RMTWKUP 0xFFC20028 /* EMAC0 Remote wake up frame register */
-#define EMAC0_PMT_CTLSTAT 0xFFC2002C /* EMAC0 PMT Control and Status Register */
-#define EMAC0_ISTAT 0xFFC20038 /* EMAC0 EMAC Interrupt Status Register */
-#define EMAC0_IMSK 0xFFC2003C /* EMAC0 EMAC Interrupt Mask Register */
-#define EMAC0_ADDR0_HI 0xFFC20040 /* EMAC0 EMAC Address0 High Register */
-#define EMAC0_ADDR0_LO 0xFFC20044 /* EMAC0 EMAC Address0 Low Register */
-#define EMAC0_MMC_CTL 0xFFC20100 /* EMAC0 MMC Control Register */
-#define EMAC0_MMC_RXINT 0xFFC20104 /* EMAC0 MMC RX Interrupt Register */
-#define EMAC0_MMC_TXINT 0xFFC20108 /* EMAC0 MMC TX Interrupt Register */
-#define EMAC0_MMC_RXIMSK 0xFFC2010C /* EMAC0 MMC RX Interrupt Mask Register */
-#define EMAC0_MMC_TXIMSK 0xFFC20110 /* EMAC0 MMC TX Interrupt Mask Register */
-#define EMAC0_TXOCTCNT_GB 0xFFC20114 /* EMAC0 Num bytes transmitted exclusive of preamble */
-#define EMAC0_TXFRMCNT_GB 0xFFC20118 /* EMAC0 Num frames transmitted exclusive of retired */
-#define EMAC0_TXBCASTFRM_G 0xFFC2011C /* EMAC0 Number of good broadcast frames transmitted. */
-#define EMAC0_TXMCASTFRM_G 0xFFC20120 /* EMAC0 Number of good multicast frames transmitted. */
-#define EMAC0_TX64_GB 0xFFC20124 /* EMAC0 Number of 64 byte length frames */
-#define EMAC0_TX65TO127_GB 0xFFC20128 /* EMAC0 Number of frames of length b/w 65-127 (inclusive) bytes */
-#define EMAC0_TX128TO255_GB 0xFFC2012C /* EMAC0 Number of frames of length b/w 128-255 (inclusive) bytes */
-#define EMAC0_TX256TO511_GB 0xFFC20130 /* EMAC0 Number of frames of length b/w 256-511 (inclusive) bytes */
-#define EMAC0_TX512TO1023_GB 0xFFC20134 /* EMAC0 Number of frames of length b/w 512-1023 (inclusive) bytes */
-#define EMAC0_TX1024TOMAX_GB 0xFFC20138 /* EMAC0 Number of frames of length b/w 1024-max (inclusive) bytes */
-#define EMAC0_TXUCASTFRM_GB 0xFFC2013C /* EMAC0 Number of good and bad unicast frames transmitted */
-#define EMAC0_TXMCASTFRM_GB 0xFFC20140 /* EMAC0 Number of good and bad multicast frames transmitted */
-#define EMAC0_TXBCASTFRM_GB 0xFFC20144 /* EMAC0 Number of good and bad broadcast frames transmitted */
-#define EMAC0_TXUNDR_ERR 0xFFC20148 /* EMAC0 Number of frames aborted due to frame underflow error */
-#define EMAC0_TXSNGCOL_G 0xFFC2014C /* EMAC0 Number of transmitted frames after single collision */
-#define EMAC0_TXMULTCOL_G 0xFFC20150 /* EMAC0 Number of transmitted frames with more than one collision */
-#define EMAC0_TXDEFERRED 0xFFC20154 /* EMAC0 Number of transmitted frames after deferral */
-#define EMAC0_TXLATECOL 0xFFC20158 /* EMAC0 Number of frames aborted due to late collision error */
-#define EMAC0_TXEXCESSCOL 0xFFC2015C /* EMAC0 Number of aborted frames due to excessive collisions */
-#define EMAC0_TXCARR_ERR 0xFFC20160 /* EMAC0 Number of aborted frames due to carrier sense error */
-#define EMAC0_TXOCTCNT_G 0xFFC20164 /* EMAC0 Number of bytes transmitted in good frames only */
-#define EMAC0_TXFRMCNT_G 0xFFC20168 /* EMAC0 Number of good frames transmitted. */
-#define EMAC0_TXEXCESSDEF 0xFFC2016C /* EMAC0 Number of frames aborted due to excessive deferral */
-#define EMAC0_TXPAUSEFRM 0xFFC20170 /* EMAC0 Number of good PAUSE frames transmitted. */
-#define EMAC0_TXVLANFRM_G 0xFFC20174 /* EMAC0 Number of VLAN frames transmitted */
-#define EMAC0_RXFRMCNT_GB 0xFFC20180 /* EMAC0 Number of good and bad frames received. */
-#define EMAC0_RXOCTCNT_GB 0xFFC20184 /* EMAC0 Number of bytes received in good and bad frames */
-#define EMAC0_RXOCTCNT_G 0xFFC20188 /* EMAC0 Number of bytes received only in good frames */
-#define EMAC0_RXBCASTFRM_G 0xFFC2018C /* EMAC0 Number of good broadcast frames received. */
-#define EMAC0_RXMCASTFRM_G 0xFFC20190 /* EMAC0 Number of good multicast frames received */
-#define EMAC0_RXCRC_ERR 0xFFC20194 /* EMAC0 Number of frames received with CRC error */
-#define EMAC0_RXALIGN_ERR 0xFFC20198 /* EMAC0 Number of frames with alignment error */
-#define EMAC0_RXRUNT_ERR 0xFFC2019C /* EMAC0 Number of frames received with runt error. */
-#define EMAC0_RXJAB_ERR 0xFFC201A0 /* EMAC0 Number of frames received with length greater than 1518 */
-#define EMAC0_RXUSIZE_G 0xFFC201A4 /* EMAC0 Number of frames received with length 64 */
-#define EMAC0_RXOSIZE_G 0xFFC201A8 /* EMAC0 Number of frames received with length greater than maxium */
-#define EMAC0_RX64_GB 0xFFC201AC /* EMAC0 Number of good and bad frames of lengh 64 bytes */
-#define EMAC0_RX65TO127_GB 0xFFC201B0 /* EMAC0 Number of good and bad frame between 64-127(inclusive) */
-#define EMAC0_RX128TO255_GB 0xFFC201B4 /* EMAC0 Number of good and bad frames received with length between 128 and 255 (inclusive) bytes, exclusive of preamble. */
-#define EMAC0_RX256TO511_GB 0xFFC201B8 /* EMAC0 Number of good and bad frames between 256-511(inclusive) */
-#define EMAC0_RX512TO1023_GB 0xFFC201BC /* EMAC0 Number of good and bad frames received between 512-1023 */
-#define EMAC0_RX1024TOMAX_GB 0xFFC201C0 /* EMAC0 Number of frames received between 1024 and maxsize */
-#define EMAC0_RXUCASTFRM_G 0xFFC201C4 /* EMAC0 Number of good unicast frames received. */
-#define EMAC0_RXLEN_ERR 0xFFC201C8 /* EMAC0 Number of frames received with length error */
-#define EMAC0_RXOORTYPE 0xFFC201CC /* EMAC0 Number of frames with length not equal to valid frame size */
-#define EMAC0_RXPAUSEFRM 0xFFC201D0 /* EMAC0 Number of good and valid PAUSE frames received. */
-#define EMAC0_RXFIFO_OVF 0xFFC201D4 /* EMAC0 Number of missed received frames due to FIFO overflow. This counter is not present in the GMAC-CORE configuration. */
-#define EMAC0_RXVLANFRM_GB 0xFFC201D8 /* EMAC0 Number of good and bad VLAN frames received. */
-#define EMAC0_RXWDOG_ERR 0xFFC201DC /* EMAC0 Frames received with error due to watchdog timeout */
-#define EMAC0_IPC_RXIMSK 0xFFC20200 /* EMAC0 MMC IPC RX Interrupt Mask Register */
-#define EMAC0_IPC_RXINT 0xFFC20208 /* EMAC0 MMC IPC RX Interrupt Register */
-#define EMAC0_RXIPV4_GD_FRM 0xFFC20210 /* EMAC0 Number of good IPv4 datagrams */
-#define EMAC0_RXIPV4_HDR_ERR_FRM 0xFFC20214 /* EMAC0 Number of IPv4 datagrams with header errors */
-#define EMAC0_RXIPV4_NOPAY_FRM 0xFFC20218 /* EMAC0 Number of IPv4 datagrams without checksum */
-#define EMAC0_RXIPV4_FRAG_FRM 0xFFC2021C /* EMAC0 Number of good IPv4 datagrams with fragmentation */
-#define EMAC0_RXIPV4_UDSBL_FRM 0xFFC20220 /* EMAC0 Number of IPv4 UDP datagrams with disabled checksum */
-#define EMAC0_RXIPV6_GD_FRM 0xFFC20224 /* EMAC0 Number of IPv4 datagrams with TCP/UDP/ICMP payloads */
-#define EMAC0_RXIPV6_HDR_ERR_FRM 0xFFC20228 /* EMAC0 Number of IPv6 datagrams with header errors */
-#define EMAC0_RXIPV6_NOPAY_FRM 0xFFC2022C /* EMAC0 Number of IPv6 datagrams with no TCP/UDP/ICMP payload */
-#define EMAC0_RXUDP_GD_FRM 0xFFC20230 /* EMAC0 Number of good IP datagrames with good UDP payload */
-#define EMAC0_RXUDP_ERR_FRM 0xFFC20234 /* EMAC0 Number of good IP datagrams with UDP checksum errors */
-#define EMAC0_RXTCP_GD_FRM 0xFFC20238 /* EMAC0 Number of good IP datagrams with a good TCP payload */
-#define EMAC0_RXTCP_ERR_FRM 0xFFC2023C /* EMAC0 Number of good IP datagrams with TCP checksum errors */
-#define EMAC0_RXICMP_GD_FRM 0xFFC20240 /* EMAC0 Number of good IP datagrams with a good ICMP payload */
-#define EMAC0_RXICMP_ERR_FRM 0xFFC20244 /* EMAC0 Number of good IP datagrams with ICMP checksum errors */
-#define EMAC0_RXIPV4_GD_OCT 0xFFC20250 /* EMAC0 Bytes received in IPv4 datagrams including tcp,udp or icmp */
-#define EMAC0_RXIPV4_HDR_ERR_OCT 0xFFC20254 /* EMAC0 Bytes received in IPv4 datagrams with header errors */
-#define EMAC0_RXIPV4_NOPAY_OCT 0xFFC20258 /* EMAC0 Bytes received in IPv4 datagrams without tcp,udp,icmp load */
-#define EMAC0_RXIPV4_FRAG_OCT 0xFFC2025C /* EMAC0 Bytes received in fragmented IPv4 datagrams */
-#define EMAC0_RXIPV4_UDSBL_OCT 0xFFC20260 /* EMAC0 Bytes received in UDP segment with checksum disabled */
-#define EMAC0_RXIPV6_GD_OCT 0xFFC20264 /* EMAC0 Bytes received in good IPv6 including tcp,udp or icmp load */
-#define EMAC0_RXIPV6_HDR_ERR_OCT 0xFFC20268 /* EMAC0 Number of bytes received in IPv6 with header errors */
-#define EMAC0_RXIPV6_NOPAY_OCT 0xFFC2026C /* EMAC0 Bytes received in IPv6 without tcp,udp or icmp load */
-#define EMAC0_RXUDP_GD_OCT 0xFFC20270 /* EMAC0 Number of bytes received in good UDP segments */
-#define EMAC0_RXUDP_ERR_OCT 0xFFC20274 /* EMAC0 Number of bytes received in UDP segment with checksum err */
-#define EMAC0_RXTCP_GD_OCT 0xFFC20278 /* EMAC0 Number of bytes received in a good TCP segment */
-#define EMAC0_RXTCP_ERR_OCT 0xFFC2027C /* EMAC0 Number of bytes received in TCP segment with checksum err */
-#define EMAC0_RXICMP_GD_OCT 0xFFC20280 /* EMAC0 Number of bytes received in a good ICMP segment */
-#define EMAC0_RXICMP_ERR_OCT 0xFFC20284 /* EMAC0 Bytes received in an ICMP segment with checksum errors */
-#define EMAC0_TM_CTL 0xFFC20700 /* EMAC0 EMAC Time Stamp Control Register */
-#define EMAC0_TM_SUBSEC 0xFFC20704 /* EMAC0 EMAC Time Stamp Sub Second Increment */
-#define EMAC0_TM_SEC 0xFFC20708 /* EMAC0 EMAC Time Stamp Second Register */
-#define EMAC0_TM_NSEC 0xFFC2070C /* EMAC0 EMAC Time Stamp Nano Second Register */
-#define EMAC0_TM_SECUPDT 0xFFC20710 /* EMAC0 EMAC Time Stamp Seconds Update */
-#define EMAC0_TM_NSECUPDT 0xFFC20714 /* EMAC0 EMAC Time Stamp Nano Seconds Update */
-#define EMAC0_TM_ADDEND 0xFFC20718 /* EMAC0 EMAC Time Stamp Addend Register */
-#define EMAC0_TM_TGTM 0xFFC2071C /* EMAC0 EMAC Time Stamp Target Time Sec. */
-#define EMAC0_TM_NTGTM 0xFFC20720 /* EMAC0 EMAC Time Stamp Target Time Nanosec. */
-#define EMAC0_TM_HISEC 0xFFC20724 /* EMAC0 EMAC Time Stamp High Second Register */
-#define EMAC0_TM_STMPSTAT 0xFFC20728 /* EMAC0 EMAC Time Stamp Status Register */
-#define EMAC0_TM_PPSCTL 0xFFC2072C /* EMAC0 EMAC PPS Control Register */
-#define EMAC0_TM_AUXSTMP_NSEC 0xFFC20730 /* EMAC0 EMAC Auxillary Time Stamp Nano Register */
-#define EMAC0_TM_AUXSTMP_SEC 0xFFC20734 /* EMAC0 EMAC Auxillary Time Stamp Sec Register */
-#define EMAC0_DMA_BUSMODE 0xFFC21000 /* EMAC0 Bus Operating Modes for EMAC DMA */
-#define EMAC0_DMA_TXPOLL 0xFFC21004 /* EMAC0 TX DMA Poll demand register */
-#define EMAC0_DMA_RXPOLL 0xFFC21008 /* EMAC0 RX DMA Poll demand register */
-#define EMAC0_DMA_RXDSC_ADDR 0xFFC2100C /* EMAC0 RX Descriptor List Address */
-#define EMAC0_DMA_TXDSC_ADDR 0xFFC21010 /* EMAC0 TX Descriptor List Address */
-#define EMAC0_DMA_STAT 0xFFC21014 /* EMAC0 DMA Status Register */
-#define EMAC0_DMA_OPMODE 0xFFC21018 /* EMAC0 DMA Operation Mode Register */
-#define EMAC0_DMA_IEN 0xFFC2101C /* EMAC0 DMA Interrupt Enable Register */
-#define EMAC0_DMA_MISS_FRM 0xFFC21020 /* EMAC0 DMA missed frame and buffer overflow counter */
-#define EMAC0_DMA_RXIWDOG 0xFFC21024 /* EMAC0 DMA RX Interrupt Watch Dog timer */
-#define EMAC0_DMA_BMMODE 0xFFC21028 /* EMAC0 AXI Bus Mode Register */
-#define EMAC0_DMA_BMSTAT 0xFFC2102C /* EMAC0 AXI Status Register */
-#define EMAC0_DMA_TXDSC_CUR 0xFFC21048 /* EMAC0 TX current descriptor register */
-#define EMAC0_DMA_RXDSC_CUR 0xFFC2104C /* EMAC0 RX current descriptor register */
-#define EMAC0_DMA_TXBUF_CUR 0xFFC21050 /* EMAC0 TX current buffer pointer register */
-#define EMAC0_DMA_RXBUF_CUR 0xFFC21054 /* EMAC0 RX current buffer pointer register */
-#define EMAC0_HWFEAT 0xFFC21058 /* EMAC0 Hardware Feature Register */
-
-/* =========================
- EMAC1
- ========================= */
-#define EMAC1_MACCFG 0xFFC22000 /* EMAC1 MAC Configuration Register */
-#define EMAC1_MACFRMFILT 0xFFC22004 /* EMAC1 Filter Register for filtering Received Frames */
-#define EMAC1_HASHTBL_HI 0xFFC22008 /* EMAC1 Contains the Upper 32 bits of the hash table */
-#define EMAC1_HASHTBL_LO 0xFFC2200C /* EMAC1 Contains the lower 32 bits of the hash table */
-#define EMAC1_GMII_ADDR 0xFFC22010 /* EMAC1 Management Address Register */
-#define EMAC1_GMII_DATA 0xFFC22014 /* EMAC1 Management Data Register */
-#define EMAC1_FLOWCTL 0xFFC22018 /* EMAC1 MAC FLow Control Register */
-#define EMAC1_VLANTAG 0xFFC2201C /* EMAC1 VLAN Tag Register */
-#define EMAC1_VER 0xFFC22020 /* EMAC1 EMAC Version Register */
-#define EMAC1_DBG 0xFFC22024 /* EMAC1 EMAC Debug Register */
-#define EMAC1_RMTWKUP 0xFFC22028 /* EMAC1 Remote wake up frame register */
-#define EMAC1_PMT_CTLSTAT 0xFFC2202C /* EMAC1 PMT Control and Status Register */
-#define EMAC1_ISTAT 0xFFC22038 /* EMAC1 EMAC Interrupt Status Register */
-#define EMAC1_IMSK 0xFFC2203C /* EMAC1 EMAC Interrupt Mask Register */
-#define EMAC1_ADDR0_HI 0xFFC22040 /* EMAC1 EMAC Address0 High Register */
-#define EMAC1_ADDR0_LO 0xFFC22044 /* EMAC1 EMAC Address0 Low Register */
-#define EMAC1_MMC_CTL 0xFFC22100 /* EMAC1 MMC Control Register */
-#define EMAC1_MMC_RXINT 0xFFC22104 /* EMAC1 MMC RX Interrupt Register */
-#define EMAC1_MMC_TXINT 0xFFC22108 /* EMAC1 MMC TX Interrupt Register */
-#define EMAC1_MMC_RXIMSK 0xFFC2210C /* EMAC1 MMC RX Interrupt Mask Register */
-#define EMAC1_MMC_TXIMSK 0xFFC22110 /* EMAC1 MMC TX Interrupt Mask Register */
-#define EMAC1_TXOCTCNT_GB 0xFFC22114 /* EMAC1 Num bytes transmitted exclusive of preamble */
-#define EMAC1_TXFRMCNT_GB 0xFFC22118 /* EMAC1 Num frames transmitted exclusive of retired */
-#define EMAC1_TXBCASTFRM_G 0xFFC2211C /* EMAC1 Number of good broadcast frames transmitted. */
-#define EMAC1_TXMCASTFRM_G 0xFFC22120 /* EMAC1 Number of good multicast frames transmitted. */
-#define EMAC1_TX64_GB 0xFFC22124 /* EMAC1 Number of 64 byte length frames */
-#define EMAC1_TX65TO127_GB 0xFFC22128 /* EMAC1 Number of frames of length b/w 65-127 (inclusive) bytes */
-#define EMAC1_TX128TO255_GB 0xFFC2212C /* EMAC1 Number of frames of length b/w 128-255 (inclusive) bytes */
-#define EMAC1_TX256TO511_GB 0xFFC22130 /* EMAC1 Number of frames of length b/w 256-511 (inclusive) bytes */
-#define EMAC1_TX512TO1023_GB 0xFFC22134 /* EMAC1 Number of frames of length b/w 512-1023 (inclusive) bytes */
-#define EMAC1_TX1024TOMAX_GB 0xFFC22138 /* EMAC1 Number of frames of length b/w 1024-max (inclusive) bytes */
-#define EMAC1_TXUCASTFRM_GB 0xFFC2213C /* EMAC1 Number of good and bad unicast frames transmitted */
-#define EMAC1_TXMCASTFRM_GB 0xFFC22140 /* EMAC1 Number of good and bad multicast frames transmitted */
-#define EMAC1_TXBCASTFRM_GB 0xFFC22144 /* EMAC1 Number of good and bad broadcast frames transmitted */
-#define EMAC1_TXUNDR_ERR 0xFFC22148 /* EMAC1 Number of frames aborted due to frame underflow error */
-#define EMAC1_TXSNGCOL_G 0xFFC2214C /* EMAC1 Number of transmitted frames after single collision */
-#define EMAC1_TXMULTCOL_G 0xFFC22150 /* EMAC1 Number of transmitted frames with more than one collision */
-#define EMAC1_TXDEFERRED 0xFFC22154 /* EMAC1 Number of transmitted frames after deferral */
-#define EMAC1_TXLATECOL 0xFFC22158 /* EMAC1 Number of frames aborted due to late collision error */
-#define EMAC1_TXEXCESSCOL 0xFFC2215C /* EMAC1 Number of aborted frames due to excessive collisions */
-#define EMAC1_TXCARR_ERR 0xFFC22160 /* EMAC1 Number of aborted frames due to carrier sense error */
-#define EMAC1_TXOCTCNT_G 0xFFC22164 /* EMAC1 Number of bytes transmitted in good frames only */
-#define EMAC1_TXFRMCNT_G 0xFFC22168 /* EMAC1 Number of good frames transmitted. */
-#define EMAC1_TXEXCESSDEF 0xFFC2216C /* EMAC1 Number of frames aborted due to excessive deferral */
-#define EMAC1_TXPAUSEFRM 0xFFC22170 /* EMAC1 Number of good PAUSE frames transmitted. */
-#define EMAC1_TXVLANFRM_G 0xFFC22174 /* EMAC1 Number of VLAN frames transmitted */
-#define EMAC1_RXFRMCNT_GB 0xFFC22180 /* EMAC1 Number of good and bad frames received. */
-#define EMAC1_RXOCTCNT_GB 0xFFC22184 /* EMAC1 Number of bytes received in good and bad frames */
-#define EMAC1_RXOCTCNT_G 0xFFC22188 /* EMAC1 Number of bytes received only in good frames */
-#define EMAC1_RXBCASTFRM_G 0xFFC2218C /* EMAC1 Number of good broadcast frames received. */
-#define EMAC1_RXMCASTFRM_G 0xFFC22190 /* EMAC1 Number of good multicast frames received */
-#define EMAC1_RXCRC_ERR 0xFFC22194 /* EMAC1 Number of frames received with CRC error */
-#define EMAC1_RXALIGN_ERR 0xFFC22198 /* EMAC1 Number of frames with alignment error */
-#define EMAC1_RXRUNT_ERR 0xFFC2219C /* EMAC1 Number of frames received with runt error. */
-#define EMAC1_RXJAB_ERR 0xFFC221A0 /* EMAC1 Number of frames received with length greater than 1518 */
-#define EMAC1_RXUSIZE_G 0xFFC221A4 /* EMAC1 Number of frames received with length 64 */
-#define EMAC1_RXOSIZE_G 0xFFC221A8 /* EMAC1 Number of frames received with length greater than maxium */
-#define EMAC1_RX64_GB 0xFFC221AC /* EMAC1 Number of good and bad frames of lengh 64 bytes */
-#define EMAC1_RX65TO127_GB 0xFFC221B0 /* EMAC1 Number of good and bad frame between 64-127(inclusive) */
-#define EMAC1_RX128TO255_GB 0xFFC221B4 /* EMAC1 Number of good and bad frames received with length between 128 and 255 (inclusive) bytes, exclusive of preamble. */
-#define EMAC1_RX256TO511_GB 0xFFC221B8 /* EMAC1 Number of good and bad frames between 256-511(inclusive) */
-#define EMAC1_RX512TO1023_GB 0xFFC221BC /* EMAC1 Number of good and bad frames received between 512-1023 */
-#define EMAC1_RX1024TOMAX_GB 0xFFC221C0 /* EMAC1 Number of frames received between 1024 and maxsize */
-#define EMAC1_RXUCASTFRM_G 0xFFC221C4 /* EMAC1 Number of good unicast frames received. */
-#define EMAC1_RXLEN_ERR 0xFFC221C8 /* EMAC1 Number of frames received with length error */
-#define EMAC1_RXOORTYPE 0xFFC221CC /* EMAC1 Number of frames with length not equal to valid frame size */
-#define EMAC1_RXPAUSEFRM 0xFFC221D0 /* EMAC1 Number of good and valid PAUSE frames received. */
-#define EMAC1_RXFIFO_OVF 0xFFC221D4 /* EMAC1 Number of missed received frames due to FIFO overflow. This counter is not present in the GMAC-CORE configuration. */
-#define EMAC1_RXVLANFRM_GB 0xFFC221D8 /* EMAC1 Number of good and bad VLAN frames received. */
-#define EMAC1_RXWDOG_ERR 0xFFC221DC /* EMAC1 Frames received with error due to watchdog timeout */
-#define EMAC1_IPC_RXIMSK 0xFFC22200 /* EMAC1 MMC IPC RX Interrupt Mask Register */
-#define EMAC1_IPC_RXINT 0xFFC22208 /* EMAC1 MMC IPC RX Interrupt Register */
-#define EMAC1_RXIPV4_GD_FRM 0xFFC22210 /* EMAC1 Number of good IPv4 datagrams */
-#define EMAC1_RXIPV4_HDR_ERR_FRM 0xFFC22214 /* EMAC1 Number of IPv4 datagrams with header errors */
-#define EMAC1_RXIPV4_NOPAY_FRM 0xFFC22218 /* EMAC1 Number of IPv4 datagrams without checksum */
-#define EMAC1_RXIPV4_FRAG_FRM 0xFFC2221C /* EMAC1 Number of good IPv4 datagrams with fragmentation */
-#define EMAC1_RXIPV4_UDSBL_FRM 0xFFC22220 /* EMAC1 Number of IPv4 UDP datagrams with disabled checksum */
-#define EMAC1_RXIPV6_GD_FRM 0xFFC22224 /* EMAC1 Number of IPv4 datagrams with TCP/UDP/ICMP payloads */
-#define EMAC1_RXIPV6_HDR_ERR_FRM 0xFFC22228 /* EMAC1 Number of IPv6 datagrams with header errors */
-#define EMAC1_RXIPV6_NOPAY_FRM 0xFFC2222C /* EMAC1 Number of IPv6 datagrams with no TCP/UDP/ICMP payload */
-#define EMAC1_RXUDP_GD_FRM 0xFFC22230 /* EMAC1 Number of good IP datagrames with good UDP payload */
-#define EMAC1_RXUDP_ERR_FRM 0xFFC22234 /* EMAC1 Number of good IP datagrams with UDP checksum errors */
-#define EMAC1_RXTCP_GD_FRM 0xFFC22238 /* EMAC1 Number of good IP datagrams with a good TCP payload */
-#define EMAC1_RXTCP_ERR_FRM 0xFFC2223C /* EMAC1 Number of good IP datagrams with TCP checksum errors */
-#define EMAC1_RXICMP_GD_FRM 0xFFC22240 /* EMAC1 Number of good IP datagrams with a good ICMP payload */
-#define EMAC1_RXICMP_ERR_FRM 0xFFC22244 /* EMAC1 Number of good IP datagrams with ICMP checksum errors */
-#define EMAC1_RXIPV4_GD_OCT 0xFFC22250 /* EMAC1 Bytes received in IPv4 datagrams including tcp,udp or icmp */
-#define EMAC1_RXIPV4_HDR_ERR_OCT 0xFFC22254 /* EMAC1 Bytes received in IPv4 datagrams with header errors */
-#define EMAC1_RXIPV4_NOPAY_OCT 0xFFC22258 /* EMAC1 Bytes received in IPv4 datagrams without tcp,udp,icmp load */
-#define EMAC1_RXIPV4_FRAG_OCT 0xFFC2225C /* EMAC1 Bytes received in fragmented IPv4 datagrams */
-#define EMAC1_RXIPV4_UDSBL_OCT 0xFFC22260 /* EMAC1 Bytes received in UDP segment with checksum disabled */
-#define EMAC1_RXIPV6_GD_OCT 0xFFC22264 /* EMAC1 Bytes received in good IPv6 including tcp,udp or icmp load */
-#define EMAC1_RXIPV6_HDR_ERR_OCT 0xFFC22268 /* EMAC1 Number of bytes received in IPv6 with header errors */
-#define EMAC1_RXIPV6_NOPAY_OCT 0xFFC2226C /* EMAC1 Bytes received in IPv6 without tcp,udp or icmp load */
-#define EMAC1_RXUDP_GD_OCT 0xFFC22270 /* EMAC1 Number of bytes received in good UDP segments */
-#define EMAC1_RXUDP_ERR_OCT 0xFFC22274 /* EMAC1 Number of bytes received in UDP segment with checksum err */
-#define EMAC1_RXTCP_GD_OCT 0xFFC22278 /* EMAC1 Number of bytes received in a good TCP segment */
-#define EMAC1_RXTCP_ERR_OCT 0xFFC2227C /* EMAC1 Number of bytes received in TCP segment with checksum err */
-#define EMAC1_RXICMP_GD_OCT 0xFFC22280 /* EMAC1 Number of bytes received in a good ICMP segment */
-#define EMAC1_RXICMP_ERR_OCT 0xFFC22284 /* EMAC1 Bytes received in an ICMP segment with checksum errors */
-#define EMAC1_TM_CTL 0xFFC22700 /* EMAC1 EMAC Time Stamp Control Register */
-#define EMAC1_TM_SUBSEC 0xFFC22704 /* EMAC1 EMAC Time Stamp Sub Second Increment */
-#define EMAC1_TM_SEC 0xFFC22708 /* EMAC1 EMAC Time Stamp Second Register */
-#define EMAC1_TM_NSEC 0xFFC2270C /* EMAC1 EMAC Time Stamp Nano Second Register */
-#define EMAC1_TM_SECUPDT 0xFFC22710 /* EMAC1 EMAC Time Stamp Seconds Update */
-#define EMAC1_TM_NSECUPDT 0xFFC22714 /* EMAC1 EMAC Time Stamp Nano Seconds Update */
-#define EMAC1_TM_ADDEND 0xFFC22718 /* EMAC1 EMAC Time Stamp Addend Register */
-#define EMAC1_TM_TGTM 0xFFC2271C /* EMAC1 EMAC Time Stamp Target Time Sec. */
-#define EMAC1_TM_NTGTM 0xFFC22720 /* EMAC1 EMAC Time Stamp Target Time Nanosec. */
-#define EMAC1_TM_HISEC 0xFFC22724 /* EMAC1 EMAC Time Stamp High Second Register */
-#define EMAC1_TM_STMPSTAT 0xFFC22728 /* EMAC1 EMAC Time Stamp Status Register */
-#define EMAC1_TM_PPSCTL 0xFFC2272C /* EMAC1 EMAC PPS Control Register */
-#define EMAC1_TM_AUXSTMP_NSEC 0xFFC22730 /* EMAC1 EMAC Auxillary Time Stamp Nano Register */
-#define EMAC1_TM_AUXSTMP_SEC 0xFFC22734 /* EMAC1 EMAC Auxillary Time Stamp Sec Register */
-#define EMAC1_DMA_BUSMODE 0xFFC23000 /* EMAC1 Bus Operating Modes for EMAC DMA */
-#define EMAC1_DMA_TXPOLL 0xFFC23004 /* EMAC1 TX DMA Poll demand register */
-#define EMAC1_DMA_RXPOLL 0xFFC23008 /* EMAC1 RX DMA Poll demand register */
-#define EMAC1_DMA_RXDSC_ADDR 0xFFC2300C /* EMAC1 RX Descriptor List Address */
-#define EMAC1_DMA_TXDSC_ADDR 0xFFC23010 /* EMAC1 TX Descriptor List Address */
-#define EMAC1_DMA_STAT 0xFFC23014 /* EMAC1 DMA Status Register */
-#define EMAC1_DMA_OPMODE 0xFFC23018 /* EMAC1 DMA Operation Mode Register */
-#define EMAC1_DMA_IEN 0xFFC2301C /* EMAC1 DMA Interrupt Enable Register */
-#define EMAC1_DMA_MISS_FRM 0xFFC23020 /* EMAC1 DMA missed frame and buffer overflow counter */
-#define EMAC1_DMA_RXIWDOG 0xFFC23024 /* EMAC1 DMA RX Interrupt Watch Dog timer */
-#define EMAC1_DMA_BMMODE 0xFFC23028 /* EMAC1 AXI Bus Mode Register */
-#define EMAC1_DMA_BMSTAT 0xFFC2302C /* EMAC1 AXI Status Register */
-#define EMAC1_DMA_TXDSC_CUR 0xFFC23048 /* EMAC1 TX current descriptor register */
-#define EMAC1_DMA_RXDSC_CUR 0xFFC2304C /* EMAC1 RX current descriptor register */
-#define EMAC1_DMA_TXBUF_CUR 0xFFC23050 /* EMAC1 TX current buffer pointer register */
-#define EMAC1_DMA_RXBUF_CUR 0xFFC23054 /* EMAC1 RX current buffer pointer register */
-#define EMAC1_HWFEAT 0xFFC23058 /* EMAC1 Hardware Feature Register */
-
-
-/* =========================
- SPI Registers
- ========================= */
-
-/* =========================
- SPI0
- ========================= */
-#define SPI0_REGBASE 0xFFC40400
-#define SPI0_CTL 0xFFC40404 /* SPI0 Control Register */
-#define SPI0_RXCTL 0xFFC40408 /* SPI0 RX Control Register */
-#define SPI0_TXCTL 0xFFC4040C /* SPI0 TX Control Register */
-#define SPI0_CLK 0xFFC40410 /* SPI0 Clock Rate Register */
-#define SPI0_DLY 0xFFC40414 /* SPI0 Delay Register */
-#define SPI0_SLVSEL 0xFFC40418 /* SPI0 Slave Select Register */
-#define SPI0_RWC 0xFFC4041C /* SPI0 Received Word-Count Register */
-#define SPI0_RWCR 0xFFC40420 /* SPI0 Received Word-Count Reload Register */
-#define SPI0_TWC 0xFFC40424 /* SPI0 Transmitted Word-Count Register */
-#define SPI0_TWCR 0xFFC40428 /* SPI0 Transmitted Word-Count Reload Register */
-#define SPI0_IMSK 0xFFC40430 /* SPI0 Interrupt Mask Register */
-#define SPI0_IMSK_CLR 0xFFC40434 /* SPI0 Interrupt Mask Clear Register */
-#define SPI0_IMSK_SET 0xFFC40438 /* SPI0 Interrupt Mask Set Register */
-#define SPI0_STAT 0xFFC40440 /* SPI0 Status Register */
-#define SPI0_ILAT 0xFFC40444 /* SPI0 Masked Interrupt Condition Register */
-#define SPI0_ILAT_CLR 0xFFC40448 /* SPI0 Masked Interrupt Clear Register */
-#define SPI0_RFIFO 0xFFC40450 /* SPI0 Receive FIFO Data Register */
-#define SPI0_TFIFO 0xFFC40458 /* SPI0 Transmit FIFO Data Register */
-
-/* =========================
- SPI1
- ========================= */
-#define SPI1_REGBASE 0xFFC40500
-#define SPI1_CTL 0xFFC40504 /* SPI1 Control Register */
-#define SPI1_RXCTL 0xFFC40508 /* SPI1 RX Control Register */
-#define SPI1_TXCTL 0xFFC4050C /* SPI1 TX Control Register */
-#define SPI1_CLK 0xFFC40510 /* SPI1 Clock Rate Register */
-#define SPI1_DLY 0xFFC40514 /* SPI1 Delay Register */
-#define SPI1_SLVSEL 0xFFC40518 /* SPI1 Slave Select Register */
-#define SPI1_RWC 0xFFC4051C /* SPI1 Received Word-Count Register */
-#define SPI1_RWCR 0xFFC40520 /* SPI1 Received Word-Count Reload Register */
-#define SPI1_TWC 0xFFC40524 /* SPI1 Transmitted Word-Count Register */
-#define SPI1_TWCR 0xFFC40528 /* SPI1 Transmitted Word-Count Reload Register */
-#define SPI1_IMSK 0xFFC40530 /* SPI1 Interrupt Mask Register */
-#define SPI1_IMSK_CLR 0xFFC40534 /* SPI1 Interrupt Mask Clear Register */
-#define SPI1_IMSK_SET 0xFFC40538 /* SPI1 Interrupt Mask Set Register */
-#define SPI1_STAT 0xFFC40540 /* SPI1 Status Register */
-#define SPI1_ILAT 0xFFC40544 /* SPI1 Masked Interrupt Condition Register */
-#define SPI1_ILAT_CLR 0xFFC40548 /* SPI1 Masked Interrupt Clear Register */
-#define SPI1_RFIFO 0xFFC40550 /* SPI1 Receive FIFO Data Register */
-#define SPI1_TFIFO 0xFFC40558 /* SPI1 Transmit FIFO Data Register */
-
-/* =========================
- SPORT Registers
- ========================= */
-
-/* =========================
- SPORT0
- ========================= */
-#define SPORT0_CTL_A 0xFFC40000 /* SPORT0 'A' Control Register */
-#define SPORT0_DIV_A 0xFFC40004 /* SPORT0 'A' Clock and FS Divide Register */
-#define SPORT0_MCTL_A 0xFFC40008 /* SPORT0 'A' Multichannel Control Register */
-#define SPORT0_CS0_A 0xFFC4000C /* SPORT0 'A' Multichannel Select Register (Channels 0-31) */
-#define SPORT0_CS1_A 0xFFC40010 /* SPORT0 'A' Multichannel Select Register (Channels 32-63) */
-#define SPORT0_CS2_A 0xFFC40014 /* SPORT0 'A' Multichannel Select Register (Channels 64-95) */
-#define SPORT0_CS3_A 0xFFC40018 /* SPORT0 'A' Multichannel Select Register (Channels 96-127) */
-#define SPORT0_CNT_A 0xFFC4001C /* SPORT0 'A' Frame Sync And Clock Divisor Current Count */
-#define SPORT0_ERR_A 0xFFC40020 /* SPORT0 'A' Error Register */
-#define SPORT0_MSTAT_A 0xFFC40024 /* SPORT0 'A' Multichannel Mode Status Register */
-#define SPORT0_CTL2_A 0xFFC40028 /* SPORT0 'A' Control Register 2 */
-#define SPORT0_TXPRI_A 0xFFC40040 /* SPORT0 'A' Primary Channel Transmit Buffer Register */
-#define SPORT0_RXPRI_A 0xFFC40044 /* SPORT0 'A' Primary Channel Receive Buffer Register */
-#define SPORT0_TXSEC_A 0xFFC40048 /* SPORT0 'A' Secondary Channel Transmit Buffer Register */
-#define SPORT0_RXSEC_A 0xFFC4004C /* SPORT0 'A' Secondary Channel Receive Buffer Register */
-#define SPORT0_CTL_B 0xFFC40080 /* SPORT0 'B' Control Register */
-#define SPORT0_DIV_B 0xFFC40084 /* SPORT0 'B' Clock and FS Divide Register */
-#define SPORT0_MCTL_B 0xFFC40088 /* SPORT0 'B' Multichannel Control Register */
-#define SPORT0_CS0_B 0xFFC4008C /* SPORT0 'B' Multichannel Select Register (Channels 0-31) */
-#define SPORT0_CS1_B 0xFFC40090 /* SPORT0 'B' Multichannel Select Register (Channels 32-63) */
-#define SPORT0_CS2_B 0xFFC40094 /* SPORT0 'B' Multichannel Select Register (Channels 64-95) */
-#define SPORT0_CS3_B 0xFFC40098 /* SPORT0 'B' Multichannel Select Register (Channels 96-127) */
-#define SPORT0_CNT_B 0xFFC4009C /* SPORT0 'B' Frame Sync And Clock Divisor Current Count */
-#define SPORT0_ERR_B 0xFFC400A0 /* SPORT0 'B' Error Register */
-#define SPORT0_MSTAT_B 0xFFC400A4 /* SPORT0 'B' Multichannel Mode Status Register */
-#define SPORT0_CTL2_B 0xFFC400A8 /* SPORT0 'B' Control Register 2 */
-#define SPORT0_TXPRI_B 0xFFC400C0 /* SPORT0 'B' Primary Channel Transmit Buffer Register */
-#define SPORT0_RXPRI_B 0xFFC400C4 /* SPORT0 'B' Primary Channel Receive Buffer Register */
-#define SPORT0_TXSEC_B 0xFFC400C8 /* SPORT0 'B' Secondary Channel Transmit Buffer Register */
-#define SPORT0_RXSEC_B 0xFFC400CC /* SPORT0 'B' Secondary Channel Receive Buffer Register */
-
-/* =========================
- SPORT1
- ========================= */
-#define SPORT1_CTL_A 0xFFC40100 /* SPORT1 'A' Control Register */
-#define SPORT1_DIV_A 0xFFC40104 /* SPORT1 'A' Clock and FS Divide Register */
-#define SPORT1_MCTL_A 0xFFC40108 /* SPORT1 'A' Multichannel Control Register */
-#define SPORT1_CS0_A 0xFFC4010C /* SPORT1 'A' Multichannel Select Register (Channels 0-31) */
-#define SPORT1_CS1_A 0xFFC40110 /* SPORT1 'A' Multichannel Select Register (Channels 32-63) */
-#define SPORT1_CS2_A 0xFFC40114 /* SPORT1 'A' Multichannel Select Register (Channels 64-95) */
-#define SPORT1_CS3_A 0xFFC40118 /* SPORT1 'A' Multichannel Select Register (Channels 96-127) */
-#define SPORT1_CNT_A 0xFFC4011C /* SPORT1 'A' Frame Sync And Clock Divisor Current Count */
-#define SPORT1_ERR_A 0xFFC40120 /* SPORT1 'A' Error Register */
-#define SPORT1_MSTAT_A 0xFFC40124 /* SPORT1 'A' Multichannel Mode Status Register */
-#define SPORT1_CTL2_A 0xFFC40128 /* SPORT1 'A' Control Register 2 */
-#define SPORT1_TXPRI_A 0xFFC40140 /* SPORT1 'A' Primary Channel Transmit Buffer Register */
-#define SPORT1_RXPRI_A 0xFFC40144 /* SPORT1 'A' Primary Channel Receive Buffer Register */
-#define SPORT1_TXSEC_A 0xFFC40148 /* SPORT1 'A' Secondary Channel Transmit Buffer Register */
-#define SPORT1_RXSEC_A 0xFFC4014C /* SPORT1 'A' Secondary Channel Receive Buffer Register */
-#define SPORT1_CTL_B 0xFFC40180 /* SPORT1 'B' Control Register */
-#define SPORT1_DIV_B 0xFFC40184 /* SPORT1 'B' Clock and FS Divide Register */
-#define SPORT1_MCTL_B 0xFFC40188 /* SPORT1 'B' Multichannel Control Register */
-#define SPORT1_CS0_B 0xFFC4018C /* SPORT1 'B' Multichannel Select Register (Channels 0-31) */
-#define SPORT1_CS1_B 0xFFC40190 /* SPORT1 'B' Multichannel Select Register (Channels 32-63) */
-#define SPORT1_CS2_B 0xFFC40194 /* SPORT1 'B' Multichannel Select Register (Channels 64-95) */
-#define SPORT1_CS3_B 0xFFC40198 /* SPORT1 'B' Multichannel Select Register (Channels 96-127) */
-#define SPORT1_CNT_B 0xFFC4019C /* SPORT1 'B' Frame Sync And Clock Divisor Current Count */
-#define SPORT1_ERR_B 0xFFC401A0 /* SPORT1 'B' Error Register */
-#define SPORT1_MSTAT_B 0xFFC401A4 /* SPORT1 'B' Multichannel Mode Status Register */
-#define SPORT1_CTL2_B 0xFFC401A8 /* SPORT1 'B' Control Register 2 */
-#define SPORT1_TXPRI_B 0xFFC401C0 /* SPORT1 'B' Primary Channel Transmit Buffer Register */
-#define SPORT1_RXPRI_B 0xFFC401C4 /* SPORT1 'B' Primary Channel Receive Buffer Register */
-#define SPORT1_TXSEC_B 0xFFC401C8 /* SPORT1 'B' Secondary Channel Transmit Buffer Register */
-#define SPORT1_RXSEC_B 0xFFC401CC /* SPORT1 'B' Secondary Channel Receive Buffer Register */
-
-/* =========================
- SPORT2
- ========================= */
-#define SPORT2_CTL_A 0xFFC40200 /* SPORT2 'A' Control Register */
-#define SPORT2_DIV_A 0xFFC40204 /* SPORT2 'A' Clock and FS Divide Register */
-#define SPORT2_MCTL_A 0xFFC40208 /* SPORT2 'A' Multichannel Control Register */
-#define SPORT2_CS0_A 0xFFC4020C /* SPORT2 'A' Multichannel Select Register (Channels 0-31) */
-#define SPORT2_CS1_A 0xFFC40210 /* SPORT2 'A' Multichannel Select Register (Channels 32-63) */
-#define SPORT2_CS2_A 0xFFC40214 /* SPORT2 'A' Multichannel Select Register (Channels 64-95) */
-#define SPORT2_CS3_A 0xFFC40218 /* SPORT2 'A' Multichannel Select Register (Channels 96-127) */
-#define SPORT2_CNT_A 0xFFC4021C /* SPORT2 'A' Frame Sync And Clock Divisor Current Count */
-#define SPORT2_ERR_A 0xFFC40220 /* SPORT2 'A' Error Register */
-#define SPORT2_MSTAT_A 0xFFC40224 /* SPORT2 'A' Multichannel Mode Status Register */
-#define SPORT2_CTL2_A 0xFFC40228 /* SPORT2 'A' Control Register 2 */
-#define SPORT2_TXPRI_A 0xFFC40240 /* SPORT2 'A' Primary Channel Transmit Buffer Register */
-#define SPORT2_RXPRI_A 0xFFC40244 /* SPORT2 'A' Primary Channel Receive Buffer Register */
-#define SPORT2_TXSEC_A 0xFFC40248 /* SPORT2 'A' Secondary Channel Transmit Buffer Register */
-#define SPORT2_RXSEC_A 0xFFC4024C /* SPORT2 'A' Secondary Channel Receive Buffer Register */
-#define SPORT2_CTL_B 0xFFC40280 /* SPORT2 'B' Control Register */
-#define SPORT2_DIV_B 0xFFC40284 /* SPORT2 'B' Clock and FS Divide Register */
-#define SPORT2_MCTL_B 0xFFC40288 /* SPORT2 'B' Multichannel Control Register */
-#define SPORT2_CS0_B 0xFFC4028C /* SPORT2 'B' Multichannel Select Register (Channels 0-31) */
-#define SPORT2_CS1_B 0xFFC40290 /* SPORT2 'B' Multichannel Select Register (Channels 32-63) */
-#define SPORT2_CS2_B 0xFFC40294 /* SPORT2 'B' Multichannel Select Register (Channels 64-95) */
-#define SPORT2_CS3_B 0xFFC40298 /* SPORT2 'B' Multichannel Select Register (Channels 96-127) */
-#define SPORT2_CNT_B 0xFFC4029C /* SPORT2 'B' Frame Sync And Clock Divisor Current Count */
-#define SPORT2_ERR_B 0xFFC402A0 /* SPORT2 'B' Error Register */
-#define SPORT2_MSTAT_B 0xFFC402A4 /* SPORT2 'B' Multichannel Mode Status Register */
-#define SPORT2_CTL2_B 0xFFC402A8 /* SPORT2 'B' Control Register 2 */
-#define SPORT2_TXPRI_B 0xFFC402C0 /* SPORT2 'B' Primary Channel Transmit Buffer Register */
-#define SPORT2_RXPRI_B 0xFFC402C4 /* SPORT2 'B' Primary Channel Receive Buffer Register */
-#define SPORT2_TXSEC_B 0xFFC402C8 /* SPORT2 'B' Secondary Channel Transmit Buffer Register */
-#define SPORT2_RXSEC_B 0xFFC402CC /* SPORT2 'B' Secondary Channel Receive Buffer Register */
-
-/* =========================
- EPPI Registers
- ========================= */
-
-/* =========================
- EPPI0
- ========================= */
-#define EPPI0_STAT 0xFFC18000 /* EPPI0 Status Register */
-#define EPPI0_HCNT 0xFFC18004 /* EPPI0 Horizontal Transfer Count Register */
-#define EPPI0_HDLY 0xFFC18008 /* EPPI0 Horizontal Delay Count Register */
-#define EPPI0_VCNT 0xFFC1800C /* EPPI0 Vertical Transfer Count Register */
-#define EPPI0_VDLY 0xFFC18010 /* EPPI0 Vertical Delay Count Register */
-#define EPPI0_FRAME 0xFFC18014 /* EPPI0 Lines Per Frame Register */
-#define EPPI0_LINE 0xFFC18018 /* EPPI0 Samples Per Line Register */
-#define EPPI0_CLKDIV 0xFFC1801C /* EPPI0 Clock Divide Register */
-#define EPPI0_CTL 0xFFC18020 /* EPPI0 Control Register */
-#define EPPI0_FS1_WLHB 0xFFC18024 /* EPPI0 FS1 Width Register / EPPI Horizontal Blanking Samples Per Line Register */
-#define EPPI0_FS1_PASPL 0xFFC18028 /* EPPI0 FS1 Period Register / EPPI Active Samples Per Line Register */
-#define EPPI0_FS2_WLVB 0xFFC1802C /* EPPI0 FS2 Width Register / EPPI Lines Of Vertical Blanking Register */
-#define EPPI0_FS2_PALPF 0xFFC18030 /* EPPI0 FS2 Period Register / EPPI Active Lines Per Field Register */
-#define EPPI0_IMSK 0xFFC18034 /* EPPI0 Interrupt Mask Register */
-#define EPPI0_ODDCLIP 0xFFC1803C /* EPPI0 Clipping Register for ODD (Chroma) Data */
-#define EPPI0_EVENCLIP 0xFFC18040 /* EPPI0 Clipping Register for EVEN (Luma) Data */
-#define EPPI0_FS1_DLY 0xFFC18044 /* EPPI0 Frame Sync 1 Delay Value */
-#define EPPI0_FS2_DLY 0xFFC18048 /* EPPI0 Frame Sync 2 Delay Value */
-#define EPPI0_CTL2 0xFFC1804C /* EPPI0 Control Register 2 */
-
-/* =========================
- EPPI1
- ========================= */
-#define EPPI1_STAT 0xFFC18400 /* EPPI1 Status Register */
-#define EPPI1_HCNT 0xFFC18404 /* EPPI1 Horizontal Transfer Count Register */
-#define EPPI1_HDLY 0xFFC18408 /* EPPI1 Horizontal Delay Count Register */
-#define EPPI1_VCNT 0xFFC1840C /* EPPI1 Vertical Transfer Count Register */
-#define EPPI1_VDLY 0xFFC18410 /* EPPI1 Vertical Delay Count Register */
-#define EPPI1_FRAME 0xFFC18414 /* EPPI1 Lines Per Frame Register */
-#define EPPI1_LINE 0xFFC18418 /* EPPI1 Samples Per Line Register */
-#define EPPI1_CLKDIV 0xFFC1841C /* EPPI1 Clock Divide Register */
-#define EPPI1_CTL 0xFFC18420 /* EPPI1 Control Register */
-#define EPPI1_FS1_WLHB 0xFFC18424 /* EPPI1 FS1 Width Register / EPPI Horizontal Blanking Samples Per Line Register */
-#define EPPI1_FS1_PASPL 0xFFC18428 /* EPPI1 FS1 Period Register / EPPI Active Samples Per Line Register */
-#define EPPI1_FS2_WLVB 0xFFC1842C /* EPPI1 FS2 Width Register / EPPI Lines Of Vertical Blanking Register */
-#define EPPI1_FS2_PALPF 0xFFC18430 /* EPPI1 FS2 Period Register / EPPI Active Lines Per Field Register */
-#define EPPI1_IMSK 0xFFC18434 /* EPPI1 Interrupt Mask Register */
-#define EPPI1_ODDCLIP 0xFFC1843C /* EPPI1 Clipping Register for ODD (Chroma) Data */
-#define EPPI1_EVENCLIP 0xFFC18440 /* EPPI1 Clipping Register for EVEN (Luma) Data */
-#define EPPI1_FS1_DLY 0xFFC18444 /* EPPI1 Frame Sync 1 Delay Value */
-#define EPPI1_FS2_DLY 0xFFC18448 /* EPPI1 Frame Sync 2 Delay Value */
-#define EPPI1_CTL2 0xFFC1844C /* EPPI1 Control Register 2 */
-
-/* =========================
- EPPI2
- ========================= */
-#define EPPI2_STAT 0xFFC18800 /* EPPI2 Status Register */
-#define EPPI2_HCNT 0xFFC18804 /* EPPI2 Horizontal Transfer Count Register */
-#define EPPI2_HDLY 0xFFC18808 /* EPPI2 Horizontal Delay Count Register */
-#define EPPI2_VCNT 0xFFC1880C /* EPPI2 Vertical Transfer Count Register */
-#define EPPI2_VDLY 0xFFC18810 /* EPPI2 Vertical Delay Count Register */
-#define EPPI2_FRAME 0xFFC18814 /* EPPI2 Lines Per Frame Register */
-#define EPPI2_LINE 0xFFC18818 /* EPPI2 Samples Per Line Register */
-#define EPPI2_CLKDIV 0xFFC1881C /* EPPI2 Clock Divide Register */
-#define EPPI2_CTL 0xFFC18820 /* EPPI2 Control Register */
-#define EPPI2_FS1_WLHB 0xFFC18824 /* EPPI2 FS1 Width Register / EPPI Horizontal Blanking Samples Per Line Register */
-#define EPPI2_FS1_PASPL 0xFFC18828 /* EPPI2 FS1 Period Register / EPPI Active Samples Per Line Register */
-#define EPPI2_FS2_WLVB 0xFFC1882C /* EPPI2 FS2 Width Register / EPPI Lines Of Vertical Blanking Register */
-#define EPPI2_FS2_PALPF 0xFFC18830 /* EPPI2 FS2 Period Register / EPPI Active Lines Per Field Register */
-#define EPPI2_IMSK 0xFFC18834 /* EPPI2 Interrupt Mask Register */
-#define EPPI2_ODDCLIP 0xFFC1883C /* EPPI2 Clipping Register for ODD (Chroma) Data */
-#define EPPI2_EVENCLIP 0xFFC18840 /* EPPI2 Clipping Register for EVEN (Luma) Data */
-#define EPPI2_FS1_DLY 0xFFC18844 /* EPPI2 Frame Sync 1 Delay Value */
-#define EPPI2_FS2_DLY 0xFFC18848 /* EPPI2 Frame Sync 2 Delay Value */
-#define EPPI2_CTL2 0xFFC1884C /* EPPI2 Control Register 2 */
-
-
-
-/* =========================
- DDE Registers
- ========================= */
-
-/* =========================
- DMA0
- ========================= */
-#define DMA0_NEXT_DESC_PTR 0xFFC41000 /* DMA0 Pointer to Next Initial Descriptor */
-#define DMA0_START_ADDR 0xFFC41004 /* DMA0 Start Address of Current Buffer */
-#define DMA0_CONFIG 0xFFC41008 /* DMA0 Configuration Register */
-#define DMA0_X_COUNT 0xFFC4100C /* DMA0 Inner Loop Count Start Value */
-#define DMA0_X_MODIFY 0xFFC41010 /* DMA0 Inner Loop Address Increment */
-#define DMA0_Y_COUNT 0xFFC41014 /* DMA0 Outer Loop Count Start Value (2D only) */
-#define DMA0_Y_MODIFY 0xFFC41018 /* DMA0 Outer Loop Address Increment (2D only) */
-#define DMA0_CURR_DESC_PTR 0xFFC41024 /* DMA0 Current Descriptor Pointer */
-#define DMA0_PREV_DESC_PTR 0xFFC41028 /* DMA0 Previous Initial Descriptor Pointer */
-#define DMA0_CURR_ADDR 0xFFC4102C /* DMA0 Current Address */
-#define DMA0_IRQ_STATUS 0xFFC41030 /* DMA0 Status Register */
-#define DMA0_CURR_X_COUNT 0xFFC41034 /* DMA0 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA0_CURR_Y_COUNT 0xFFC41038 /* DMA0 Current Row Count (2D only) */
-#define DMA0_BWL_COUNT 0xFFC41040 /* DMA0 Bandwidth Limit Count */
-#define DMA0_CURR_BWL_COUNT 0xFFC41044 /* DMA0 Bandwidth Limit Count Current */
-#define DMA0_BWM_COUNT 0xFFC41048 /* DMA0 Bandwidth Monitor Count */
-#define DMA0_CURR_BWM_COUNT 0xFFC4104C /* DMA0 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA1
- ========================= */
-#define DMA1_NEXT_DESC_PTR 0xFFC41080 /* DMA1 Pointer to Next Initial Descriptor */
-#define DMA1_START_ADDR 0xFFC41084 /* DMA1 Start Address of Current Buffer */
-#define DMA1_CONFIG 0xFFC41088 /* DMA1 Configuration Register */
-#define DMA1_X_COUNT 0xFFC4108C /* DMA1 Inner Loop Count Start Value */
-#define DMA1_X_MODIFY 0xFFC41090 /* DMA1 Inner Loop Address Increment */
-#define DMA1_Y_COUNT 0xFFC41094 /* DMA1 Outer Loop Count Start Value (2D only) */
-#define DMA1_Y_MODIFY 0xFFC41098 /* DMA1 Outer Loop Address Increment (2D only) */
-#define DMA1_CURR_DESC_PTR 0xFFC410A4 /* DMA1 Current Descriptor Pointer */
-#define DMA1_PREV_DESC_PTR 0xFFC410A8 /* DMA1 Previous Initial Descriptor Pointer */
-#define DMA1_CURR_ADDR 0xFFC410AC /* DMA1 Current Address */
-#define DMA1_IRQ_STATUS 0xFFC410B0 /* DMA1 Status Register */
-#define DMA1_CURR_X_COUNT 0xFFC410B4 /* DMA1 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA1_CURR_Y_COUNT 0xFFC410B8 /* DMA1 Current Row Count (2D only) */
-#define DMA1_BWL_COUNT 0xFFC410C0 /* DMA1 Bandwidth Limit Count */
-#define DMA1_CURR_BWL_COUNT 0xFFC410C4 /* DMA1 Bandwidth Limit Count Current */
-#define DMA1_BWM_COUNT 0xFFC410C8 /* DMA1 Bandwidth Monitor Count */
-#define DMA1_CURR_BWM_COUNT 0xFFC410CC /* DMA1 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA2
- ========================= */
-#define DMA2_NEXT_DESC_PTR 0xFFC41100 /* DMA2 Pointer to Next Initial Descriptor */
-#define DMA2_START_ADDR 0xFFC41104 /* DMA2 Start Address of Current Buffer */
-#define DMA2_CONFIG 0xFFC41108 /* DMA2 Configuration Register */
-#define DMA2_X_COUNT 0xFFC4110C /* DMA2 Inner Loop Count Start Value */
-#define DMA2_X_MODIFY 0xFFC41110 /* DMA2 Inner Loop Address Increment */
-#define DMA2_Y_COUNT 0xFFC41114 /* DMA2 Outer Loop Count Start Value (2D only) */
-#define DMA2_Y_MODIFY 0xFFC41118 /* DMA2 Outer Loop Address Increment (2D only) */
-#define DMA2_CURR_DESC_PTR 0xFFC41124 /* DMA2 Current Descriptor Pointer */
-#define DMA2_PREV_DESC_PTR 0xFFC41128 /* DMA2 Previous Initial Descriptor Pointer */
-#define DMA2_CURR_ADDR 0xFFC4112C /* DMA2 Current Address */
-#define DMA2_IRQ_STATUS 0xFFC41130 /* DMA2 Status Register */
-#define DMA2_CURR_X_COUNT 0xFFC41134 /* DMA2 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA2_CURR_Y_COUNT 0xFFC41138 /* DMA2 Current Row Count (2D only) */
-#define DMA2_BWL_COUNT 0xFFC41140 /* DMA2 Bandwidth Limit Count */
-#define DMA2_CURR_BWL_COUNT 0xFFC41144 /* DMA2 Bandwidth Limit Count Current */
-#define DMA2_BWM_COUNT 0xFFC41148 /* DMA2 Bandwidth Monitor Count */
-#define DMA2_CURR_BWM_COUNT 0xFFC4114C /* DMA2 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA3
- ========================= */
-#define DMA3_NEXT_DESC_PTR 0xFFC41180 /* DMA3 Pointer to Next Initial Descriptor */
-#define DMA3_START_ADDR 0xFFC41184 /* DMA3 Start Address of Current Buffer */
-#define DMA3_CONFIG 0xFFC41188 /* DMA3 Configuration Register */
-#define DMA3_X_COUNT 0xFFC4118C /* DMA3 Inner Loop Count Start Value */
-#define DMA3_X_MODIFY 0xFFC41190 /* DMA3 Inner Loop Address Increment */
-#define DMA3_Y_COUNT 0xFFC41194 /* DMA3 Outer Loop Count Start Value (2D only) */
-#define DMA3_Y_MODIFY 0xFFC41198 /* DMA3 Outer Loop Address Increment (2D only) */
-#define DMA3_CURR_DESC_PTR 0xFFC411A4 /* DMA3 Current Descriptor Pointer */
-#define DMA3_PREV_DESC_PTR 0xFFC411A8 /* DMA3 Previous Initial Descriptor Pointer */
-#define DMA3_CURR_ADDR 0xFFC411AC /* DMA3 Current Address */
-#define DMA3_IRQ_STATUS 0xFFC411B0 /* DMA3 Status Register */
-#define DMA3_CURR_X_COUNT 0xFFC411B4 /* DMA3 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA3_CURR_Y_COUNT 0xFFC411B8 /* DMA3 Current Row Count (2D only) */
-#define DMA3_BWL_COUNT 0xFFC411C0 /* DMA3 Bandwidth Limit Count */
-#define DMA3_CURR_BWL_COUNT 0xFFC411C4 /* DMA3 Bandwidth Limit Count Current */
-#define DMA3_BWM_COUNT 0xFFC411C8 /* DMA3 Bandwidth Monitor Count */
-#define DMA3_CURR_BWM_COUNT 0xFFC411CC /* DMA3 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA4
- ========================= */
-#define DMA4_NEXT_DESC_PTR 0xFFC41200 /* DMA4 Pointer to Next Initial Descriptor */
-#define DMA4_START_ADDR 0xFFC41204 /* DMA4 Start Address of Current Buffer */
-#define DMA4_CONFIG 0xFFC41208 /* DMA4 Configuration Register */
-#define DMA4_X_COUNT 0xFFC4120C /* DMA4 Inner Loop Count Start Value */
-#define DMA4_X_MODIFY 0xFFC41210 /* DMA4 Inner Loop Address Increment */
-#define DMA4_Y_COUNT 0xFFC41214 /* DMA4 Outer Loop Count Start Value (2D only) */
-#define DMA4_Y_MODIFY 0xFFC41218 /* DMA4 Outer Loop Address Increment (2D only) */
-#define DMA4_CURR_DESC_PTR 0xFFC41224 /* DMA4 Current Descriptor Pointer */
-#define DMA4_PREV_DESC_PTR 0xFFC41228 /* DMA4 Previous Initial Descriptor Pointer */
-#define DMA4_CURR_ADDR 0xFFC4122C /* DMA4 Current Address */
-#define DMA4_IRQ_STATUS 0xFFC41230 /* DMA4 Status Register */
-#define DMA4_CURR_X_COUNT 0xFFC41234 /* DMA4 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA4_CURR_Y_COUNT 0xFFC41238 /* DMA4 Current Row Count (2D only) */
-#define DMA4_BWL_COUNT 0xFFC41240 /* DMA4 Bandwidth Limit Count */
-#define DMA4_CURR_BWL_COUNT 0xFFC41244 /* DMA4 Bandwidth Limit Count Current */
-#define DMA4_BWM_COUNT 0xFFC41248 /* DMA4 Bandwidth Monitor Count */
-#define DMA4_CURR_BWM_COUNT 0xFFC4124C /* DMA4 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA5
- ========================= */
-#define DMA5_NEXT_DESC_PTR 0xFFC41280 /* DMA5 Pointer to Next Initial Descriptor */
-#define DMA5_START_ADDR 0xFFC41284 /* DMA5 Start Address of Current Buffer */
-#define DMA5_CONFIG 0xFFC41288 /* DMA5 Configuration Register */
-#define DMA5_X_COUNT 0xFFC4128C /* DMA5 Inner Loop Count Start Value */
-#define DMA5_X_MODIFY 0xFFC41290 /* DMA5 Inner Loop Address Increment */
-#define DMA5_Y_COUNT 0xFFC41294 /* DMA5 Outer Loop Count Start Value (2D only) */
-#define DMA5_Y_MODIFY 0xFFC41298 /* DMA5 Outer Loop Address Increment (2D only) */
-#define DMA5_CURR_DESC_PTR 0xFFC412A4 /* DMA5 Current Descriptor Pointer */
-#define DMA5_PREV_DESC_PTR 0xFFC412A8 /* DMA5 Previous Initial Descriptor Pointer */
-#define DMA5_CURR_ADDR 0xFFC412AC /* DMA5 Current Address */
-#define DMA5_IRQ_STATUS 0xFFC412B0 /* DMA5 Status Register */
-#define DMA5_CURR_X_COUNT 0xFFC412B4 /* DMA5 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA5_CURR_Y_COUNT 0xFFC412B8 /* DMA5 Current Row Count (2D only) */
-#define DMA5_BWL_COUNT 0xFFC412C0 /* DMA5 Bandwidth Limit Count */
-#define DMA5_CURR_BWL_COUNT 0xFFC412C4 /* DMA5 Bandwidth Limit Count Current */
-#define DMA5_BWM_COUNT 0xFFC412C8 /* DMA5 Bandwidth Monitor Count */
-#define DMA5_CURR_BWM_COUNT 0xFFC412CC /* DMA5 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA6
- ========================= */
-#define DMA6_NEXT_DESC_PTR 0xFFC41300 /* DMA6 Pointer to Next Initial Descriptor */
-#define DMA6_START_ADDR 0xFFC41304 /* DMA6 Start Address of Current Buffer */
-#define DMA6_CONFIG 0xFFC41308 /* DMA6 Configuration Register */
-#define DMA6_X_COUNT 0xFFC4130C /* DMA6 Inner Loop Count Start Value */
-#define DMA6_X_MODIFY 0xFFC41310 /* DMA6 Inner Loop Address Increment */
-#define DMA6_Y_COUNT 0xFFC41314 /* DMA6 Outer Loop Count Start Value (2D only) */
-#define DMA6_Y_MODIFY 0xFFC41318 /* DMA6 Outer Loop Address Increment (2D only) */
-#define DMA6_CURR_DESC_PTR 0xFFC41324 /* DMA6 Current Descriptor Pointer */
-#define DMA6_PREV_DESC_PTR 0xFFC41328 /* DMA6 Previous Initial Descriptor Pointer */
-#define DMA6_CURR_ADDR 0xFFC4132C /* DMA6 Current Address */
-#define DMA6_IRQ_STATUS 0xFFC41330 /* DMA6 Status Register */
-#define DMA6_CURR_X_COUNT 0xFFC41334 /* DMA6 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA6_CURR_Y_COUNT 0xFFC41338 /* DMA6 Current Row Count (2D only) */
-#define DMA6_BWL_COUNT 0xFFC41340 /* DMA6 Bandwidth Limit Count */
-#define DMA6_CURR_BWL_COUNT 0xFFC41344 /* DMA6 Bandwidth Limit Count Current */
-#define DMA6_BWM_COUNT 0xFFC41348 /* DMA6 Bandwidth Monitor Count */
-#define DMA6_CURR_BWM_COUNT 0xFFC4134C /* DMA6 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA7
- ========================= */
-#define DMA7_NEXT_DESC_PTR 0xFFC41380 /* DMA7 Pointer to Next Initial Descriptor */
-#define DMA7_START_ADDR 0xFFC41384 /* DMA7 Start Address of Current Buffer */
-#define DMA7_CONFIG 0xFFC41388 /* DMA7 Configuration Register */
-#define DMA7_X_COUNT 0xFFC4138C /* DMA7 Inner Loop Count Start Value */
-#define DMA7_X_MODIFY 0xFFC41390 /* DMA7 Inner Loop Address Increment */
-#define DMA7_Y_COUNT 0xFFC41394 /* DMA7 Outer Loop Count Start Value (2D only) */
-#define DMA7_Y_MODIFY 0xFFC41398 /* DMA7 Outer Loop Address Increment (2D only) */
-#define DMA7_CURR_DESC_PTR 0xFFC413A4 /* DMA7 Current Descriptor Pointer */
-#define DMA7_PREV_DESC_PTR 0xFFC413A8 /* DMA7 Previous Initial Descriptor Pointer */
-#define DMA7_CURR_ADDR 0xFFC413AC /* DMA7 Current Address */
-#define DMA7_IRQ_STATUS 0xFFC413B0 /* DMA7 Status Register */
-#define DMA7_CURR_X_COUNT 0xFFC413B4 /* DMA7 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA7_CURR_Y_COUNT 0xFFC413B8 /* DMA7 Current Row Count (2D only) */
-#define DMA7_BWL_COUNT 0xFFC413C0 /* DMA7 Bandwidth Limit Count */
-#define DMA7_CURR_BWL_COUNT 0xFFC413C4 /* DMA7 Bandwidth Limit Count Current */
-#define DMA7_BWM_COUNT 0xFFC413C8 /* DMA7 Bandwidth Monitor Count */
-#define DMA7_CURR_BWM_COUNT 0xFFC413CC /* DMA7 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA8
- ========================= */
-#define DMA8_NEXT_DESC_PTR 0xFFC41400 /* DMA8 Pointer to Next Initial Descriptor */
-#define DMA8_START_ADDR 0xFFC41404 /* DMA8 Start Address of Current Buffer */
-#define DMA8_CONFIG 0xFFC41408 /* DMA8 Configuration Register */
-#define DMA8_X_COUNT 0xFFC4140C /* DMA8 Inner Loop Count Start Value */
-#define DMA8_X_MODIFY 0xFFC41410 /* DMA8 Inner Loop Address Increment */
-#define DMA8_Y_COUNT 0xFFC41414 /* DMA8 Outer Loop Count Start Value (2D only) */
-#define DMA8_Y_MODIFY 0xFFC41418 /* DMA8 Outer Loop Address Increment (2D only) */
-#define DMA8_CURR_DESC_PTR 0xFFC41424 /* DMA8 Current Descriptor Pointer */
-#define DMA8_PREV_DESC_PTR 0xFFC41428 /* DMA8 Previous Initial Descriptor Pointer */
-#define DMA8_CURR_ADDR 0xFFC4142C /* DMA8 Current Address */
-#define DMA8_IRQ_STATUS 0xFFC41430 /* DMA8 Status Register */
-#define DMA8_CURR_X_COUNT 0xFFC41434 /* DMA8 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA8_CURR_Y_COUNT 0xFFC41438 /* DMA8 Current Row Count (2D only) */
-#define DMA8_BWL_COUNT 0xFFC41440 /* DMA8 Bandwidth Limit Count */
-#define DMA8_CURR_BWL_COUNT 0xFFC41444 /* DMA8 Bandwidth Limit Count Current */
-#define DMA8_BWM_COUNT 0xFFC41448 /* DMA8 Bandwidth Monitor Count */
-#define DMA8_CURR_BWM_COUNT 0xFFC4144C /* DMA8 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA9
- ========================= */
-#define DMA9_NEXT_DESC_PTR 0xFFC41480 /* DMA9 Pointer to Next Initial Descriptor */
-#define DMA9_START_ADDR 0xFFC41484 /* DMA9 Start Address of Current Buffer */
-#define DMA9_CONFIG 0xFFC41488 /* DMA9 Configuration Register */
-#define DMA9_X_COUNT 0xFFC4148C /* DMA9 Inner Loop Count Start Value */
-#define DMA9_X_MODIFY 0xFFC41490 /* DMA9 Inner Loop Address Increment */
-#define DMA9_Y_COUNT 0xFFC41494 /* DMA9 Outer Loop Count Start Value (2D only) */
-#define DMA9_Y_MODIFY 0xFFC41498 /* DMA9 Outer Loop Address Increment (2D only) */
-#define DMA9_CURR_DESC_PTR 0xFFC414A4 /* DMA9 Current Descriptor Pointer */
-#define DMA9_PREV_DESC_PTR 0xFFC414A8 /* DMA9 Previous Initial Descriptor Pointer */
-#define DMA9_CURR_ADDR 0xFFC414AC /* DMA9 Current Address */
-#define DMA9_IRQ_STATUS 0xFFC414B0 /* DMA9 Status Register */
-#define DMA9_CURR_X_COUNT 0xFFC414B4 /* DMA9 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA9_CURR_Y_COUNT 0xFFC414B8 /* DMA9 Current Row Count (2D only) */
-#define DMA9_BWL_COUNT 0xFFC414C0 /* DMA9 Bandwidth Limit Count */
-#define DMA9_CURR_BWL_COUNT 0xFFC414C4 /* DMA9 Bandwidth Limit Count Current */
-#define DMA9_BWM_COUNT 0xFFC414C8 /* DMA9 Bandwidth Monitor Count */
-#define DMA9_CURR_BWM_COUNT 0xFFC414CC /* DMA9 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA10
- ========================= */
-#define DMA10_NEXT_DESC_PTR 0xFFC05000 /* DMA10 Pointer to Next Initial Descriptor */
-#define DMA10_START_ADDR 0xFFC05004 /* DMA10 Start Address of Current Buffer */
-#define DMA10_CONFIG 0xFFC05008 /* DMA10 Configuration Register */
-#define DMA10_X_COUNT 0xFFC0500C /* DMA10 Inner Loop Count Start Value */
-#define DMA10_X_MODIFY 0xFFC05010 /* DMA10 Inner Loop Address Increment */
-#define DMA10_Y_COUNT 0xFFC05014 /* DMA10 Outer Loop Count Start Value (2D only) */
-#define DMA10_Y_MODIFY 0xFFC05018 /* DMA10 Outer Loop Address Increment (2D only) */
-#define DMA10_CURR_DESC_PTR 0xFFC05024 /* DMA10 Current Descriptor Pointer */
-#define DMA10_PREV_DESC_PTR 0xFFC05028 /* DMA10 Previous Initial Descriptor Pointer */
-#define DMA10_CURR_ADDR 0xFFC0502C /* DMA10 Current Address */
-#define DMA10_IRQ_STATUS 0xFFC05030 /* DMA10 Status Register */
-#define DMA10_CURR_X_COUNT 0xFFC05034 /* DMA10 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA10_CURR_Y_COUNT 0xFFC05038 /* DMA10 Current Row Count (2D only) */
-#define DMA10_BWL_COUNT 0xFFC05040 /* DMA10 Bandwidth Limit Count */
-#define DMA10_CURR_BWL_COUNT 0xFFC05044 /* DMA10 Bandwidth Limit Count Current */
-#define DMA10_BWM_COUNT 0xFFC05048 /* DMA10 Bandwidth Monitor Count */
-#define DMA10_CURR_BWM_COUNT 0xFFC0504C /* DMA10 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA11
- ========================= */
-#define DMA11_NEXT_DESC_PTR 0xFFC05080 /* DMA11 Pointer to Next Initial Descriptor */
-#define DMA11_START_ADDR 0xFFC05084 /* DMA11 Start Address of Current Buffer */
-#define DMA11_CONFIG 0xFFC05088 /* DMA11 Configuration Register */
-#define DMA11_X_COUNT 0xFFC0508C /* DMA11 Inner Loop Count Start Value */
-#define DMA11_X_MODIFY 0xFFC05090 /* DMA11 Inner Loop Address Increment */
-#define DMA11_Y_COUNT 0xFFC05094 /* DMA11 Outer Loop Count Start Value (2D only) */
-#define DMA11_Y_MODIFY 0xFFC05098 /* DMA11 Outer Loop Address Increment (2D only) */
-#define DMA11_CURR_DESC_PTR 0xFFC050A4 /* DMA11 Current Descriptor Pointer */
-#define DMA11_PREV_DESC_PTR 0xFFC050A8 /* DMA11 Previous Initial Descriptor Pointer */
-#define DMA11_CURR_ADDR 0xFFC050AC /* DMA11 Current Address */
-#define DMA11_IRQ_STATUS 0xFFC050B0 /* DMA11 Status Register */
-#define DMA11_CURR_X_COUNT 0xFFC050B4 /* DMA11 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA11_CURR_Y_COUNT 0xFFC050B8 /* DMA11 Current Row Count (2D only) */
-#define DMA11_BWL_COUNT 0xFFC050C0 /* DMA11 Bandwidth Limit Count */
-#define DMA11_CURR_BWL_COUNT 0xFFC050C4 /* DMA11 Bandwidth Limit Count Current */
-#define DMA11_BWM_COUNT 0xFFC050C8 /* DMA11 Bandwidth Monitor Count */
-#define DMA11_CURR_BWM_COUNT 0xFFC050CC /* DMA11 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA12
- ========================= */
-#define DMA12_NEXT_DESC_PTR 0xFFC05100 /* DMA12 Pointer to Next Initial Descriptor */
-#define DMA12_START_ADDR 0xFFC05104 /* DMA12 Start Address of Current Buffer */
-#define DMA12_CONFIG 0xFFC05108 /* DMA12 Configuration Register */
-#define DMA12_X_COUNT 0xFFC0510C /* DMA12 Inner Loop Count Start Value */
-#define DMA12_X_MODIFY 0xFFC05110 /* DMA12 Inner Loop Address Increment */
-#define DMA12_Y_COUNT 0xFFC05114 /* DMA12 Outer Loop Count Start Value (2D only) */
-#define DMA12_Y_MODIFY 0xFFC05118 /* DMA12 Outer Loop Address Increment (2D only) */
-#define DMA12_CURR_DESC_PTR 0xFFC05124 /* DMA12 Current Descriptor Pointer */
-#define DMA12_PREV_DESC_PTR 0xFFC05128 /* DMA12 Previous Initial Descriptor Pointer */
-#define DMA12_CURR_ADDR 0xFFC0512C /* DMA12 Current Address */
-#define DMA12_IRQ_STATUS 0xFFC05130 /* DMA12 Status Register */
-#define DMA12_CURR_X_COUNT 0xFFC05134 /* DMA12 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA12_CURR_Y_COUNT 0xFFC05138 /* DMA12 Current Row Count (2D only) */
-#define DMA12_BWL_COUNT 0xFFC05140 /* DMA12 Bandwidth Limit Count */
-#define DMA12_CURR_BWL_COUNT 0xFFC05144 /* DMA12 Bandwidth Limit Count Current */
-#define DMA12_BWM_COUNT 0xFFC05148 /* DMA12 Bandwidth Monitor Count */
-#define DMA12_CURR_BWM_COUNT 0xFFC0514C /* DMA12 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA13
- ========================= */
-#define DMA13_NEXT_DESC_PTR 0xFFC07000 /* DMA13 Pointer to Next Initial Descriptor */
-#define DMA13_START_ADDR 0xFFC07004 /* DMA13 Start Address of Current Buffer */
-#define DMA13_CONFIG 0xFFC07008 /* DMA13 Configuration Register */
-#define DMA13_X_COUNT 0xFFC0700C /* DMA13 Inner Loop Count Start Value */
-#define DMA13_X_MODIFY 0xFFC07010 /* DMA13 Inner Loop Address Increment */
-#define DMA13_Y_COUNT 0xFFC07014 /* DMA13 Outer Loop Count Start Value (2D only) */
-#define DMA13_Y_MODIFY 0xFFC07018 /* DMA13 Outer Loop Address Increment (2D only) */
-#define DMA13_CURR_DESC_PTR 0xFFC07024 /* DMA13 Current Descriptor Pointer */
-#define DMA13_PREV_DESC_PTR 0xFFC07028 /* DMA13 Previous Initial Descriptor Pointer */
-#define DMA13_CURR_ADDR 0xFFC0702C /* DMA13 Current Address */
-#define DMA13_IRQ_STATUS 0xFFC07030 /* DMA13 Status Register */
-#define DMA13_CURR_X_COUNT 0xFFC07034 /* DMA13 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA13_CURR_Y_COUNT 0xFFC07038 /* DMA13 Current Row Count (2D only) */
-#define DMA13_BWL_COUNT 0xFFC07040 /* DMA13 Bandwidth Limit Count */
-#define DMA13_CURR_BWL_COUNT 0xFFC07044 /* DMA13 Bandwidth Limit Count Current */
-#define DMA13_BWM_COUNT 0xFFC07048 /* DMA13 Bandwidth Monitor Count */
-#define DMA13_CURR_BWM_COUNT 0xFFC0704C /* DMA13 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA14
- ========================= */
-#define DMA14_NEXT_DESC_PTR 0xFFC07080 /* DMA14 Pointer to Next Initial Descriptor */
-#define DMA14_START_ADDR 0xFFC07084 /* DMA14 Start Address of Current Buffer */
-#define DMA14_CONFIG 0xFFC07088 /* DMA14 Configuration Register */
-#define DMA14_X_COUNT 0xFFC0708C /* DMA14 Inner Loop Count Start Value */
-#define DMA14_X_MODIFY 0xFFC07090 /* DMA14 Inner Loop Address Increment */
-#define DMA14_Y_COUNT 0xFFC07094 /* DMA14 Outer Loop Count Start Value (2D only) */
-#define DMA14_Y_MODIFY 0xFFC07098 /* DMA14 Outer Loop Address Increment (2D only) */
-#define DMA14_CURR_DESC_PTR 0xFFC070A4 /* DMA14 Current Descriptor Pointer */
-#define DMA14_PREV_DESC_PTR 0xFFC070A8 /* DMA14 Previous Initial Descriptor Pointer */
-#define DMA14_CURR_ADDR 0xFFC070AC /* DMA14 Current Address */
-#define DMA14_IRQ_STATUS 0xFFC070B0 /* DMA14 Status Register */
-#define DMA14_CURR_X_COUNT 0xFFC070B4 /* DMA14 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA14_CURR_Y_COUNT 0xFFC070B8 /* DMA14 Current Row Count (2D only) */
-#define DMA14_BWL_COUNT 0xFFC070C0 /* DMA14 Bandwidth Limit Count */
-#define DMA14_CURR_BWL_COUNT 0xFFC070C4 /* DMA14 Bandwidth Limit Count Current */
-#define DMA14_BWM_COUNT 0xFFC070C8 /* DMA14 Bandwidth Monitor Count */
-#define DMA14_CURR_BWM_COUNT 0xFFC070CC /* DMA14 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA15
- ========================= */
-#define DMA15_NEXT_DESC_PTR 0xFFC07100 /* DMA15 Pointer to Next Initial Descriptor */
-#define DMA15_START_ADDR 0xFFC07104 /* DMA15 Start Address of Current Buffer */
-#define DMA15_CONFIG 0xFFC07108 /* DMA15 Configuration Register */
-#define DMA15_X_COUNT 0xFFC0710C /* DMA15 Inner Loop Count Start Value */
-#define DMA15_X_MODIFY 0xFFC07110 /* DMA15 Inner Loop Address Increment */
-#define DMA15_Y_COUNT 0xFFC07114 /* DMA15 Outer Loop Count Start Value (2D only) */
-#define DMA15_Y_MODIFY 0xFFC07118 /* DMA15 Outer Loop Address Increment (2D only) */
-#define DMA15_CURR_DESC_PTR 0xFFC07124 /* DMA15 Current Descriptor Pointer */
-#define DMA15_PREV_DESC_PTR 0xFFC07128 /* DMA15 Previous Initial Descriptor Pointer */
-#define DMA15_CURR_ADDR 0xFFC0712C /* DMA15 Current Address */
-#define DMA15_IRQ_STATUS 0xFFC07130 /* DMA15 Status Register */
-#define DMA15_CURR_X_COUNT 0xFFC07134 /* DMA15 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA15_CURR_Y_COUNT 0xFFC07138 /* DMA15 Current Row Count (2D only) */
-#define DMA15_BWL_COUNT 0xFFC07140 /* DMA15 Bandwidth Limit Count */
-#define DMA15_CURR_BWL_COUNT 0xFFC07144 /* DMA15 Bandwidth Limit Count Current */
-#define DMA15_BWM_COUNT 0xFFC07148 /* DMA15 Bandwidth Monitor Count */
-#define DMA15_CURR_BWM_COUNT 0xFFC0714C /* DMA15 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA16
- ========================= */
-#define DMA16_NEXT_DESC_PTR 0xFFC07180 /* DMA16 Pointer to Next Initial Descriptor */
-#define DMA16_START_ADDR 0xFFC07184 /* DMA16 Start Address of Current Buffer */
-#define DMA16_CONFIG 0xFFC07188 /* DMA16 Configuration Register */
-#define DMA16_X_COUNT 0xFFC0718C /* DMA16 Inner Loop Count Start Value */
-#define DMA16_X_MODIFY 0xFFC07190 /* DMA16 Inner Loop Address Increment */
-#define DMA16_Y_COUNT 0xFFC07194 /* DMA16 Outer Loop Count Start Value (2D only) */
-#define DMA16_Y_MODIFY 0xFFC07198 /* DMA16 Outer Loop Address Increment (2D only) */
-#define DMA16_CURR_DESC_PTR 0xFFC071A4 /* DMA16 Current Descriptor Pointer */
-#define DMA16_PREV_DESC_PTR 0xFFC071A8 /* DMA16 Previous Initial Descriptor Pointer */
-#define DMA16_CURR_ADDR 0xFFC071AC /* DMA16 Current Address */
-#define DMA16_IRQ_STATUS 0xFFC071B0 /* DMA16 Status Register */
-#define DMA16_CURR_X_COUNT 0xFFC071B4 /* DMA16 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA16_CURR_Y_COUNT 0xFFC071B8 /* DMA16 Current Row Count (2D only) */
-#define DMA16_BWL_COUNT 0xFFC071C0 /* DMA16 Bandwidth Limit Count */
-#define DMA16_CURR_BWL_COUNT 0xFFC071C4 /* DMA16 Bandwidth Limit Count Current */
-#define DMA16_BWM_COUNT 0xFFC071C8 /* DMA16 Bandwidth Monitor Count */
-#define DMA16_CURR_BWM_COUNT 0xFFC071CC /* DMA16 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA17
- ========================= */
-#define DMA17_NEXT_DESC_PTR 0xFFC07200 /* DMA17 Pointer to Next Initial Descriptor */
-#define DMA17_START_ADDR 0xFFC07204 /* DMA17 Start Address of Current Buffer */
-#define DMA17_CONFIG 0xFFC07208 /* DMA17 Configuration Register */
-#define DMA17_X_COUNT 0xFFC0720C /* DMA17 Inner Loop Count Start Value */
-#define DMA17_X_MODIFY 0xFFC07210 /* DMA17 Inner Loop Address Increment */
-#define DMA17_Y_COUNT 0xFFC07214 /* DMA17 Outer Loop Count Start Value (2D only) */
-#define DMA17_Y_MODIFY 0xFFC07218 /* DMA17 Outer Loop Address Increment (2D only) */
-#define DMA17_CURR_DESC_PTR 0xFFC07224 /* DMA17 Current Descriptor Pointer */
-#define DMA17_PREV_DESC_PTR 0xFFC07228 /* DMA17 Previous Initial Descriptor Pointer */
-#define DMA17_CURR_ADDR 0xFFC0722C /* DMA17 Current Address */
-#define DMA17_IRQ_STATUS 0xFFC07230 /* DMA17 Status Register */
-#define DMA17_CURR_X_COUNT 0xFFC07234 /* DMA17 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA17_CURR_Y_COUNT 0xFFC07238 /* DMA17 Current Row Count (2D only) */
-#define DMA17_BWL_COUNT 0xFFC07240 /* DMA17 Bandwidth Limit Count */
-#define DMA17_CURR_BWL_COUNT 0xFFC07244 /* DMA17 Bandwidth Limit Count Current */
-#define DMA17_BWM_COUNT 0xFFC07248 /* DMA17 Bandwidth Monitor Count */
-#define DMA17_CURR_BWM_COUNT 0xFFC0724C /* DMA17 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA18
- ========================= */
-#define DMA18_NEXT_DESC_PTR 0xFFC07280 /* DMA18 Pointer to Next Initial Descriptor */
-#define DMA18_START_ADDR 0xFFC07284 /* DMA18 Start Address of Current Buffer */
-#define DMA18_CONFIG 0xFFC07288 /* DMA18 Configuration Register */
-#define DMA18_X_COUNT 0xFFC0728C /* DMA18 Inner Loop Count Start Value */
-#define DMA18_X_MODIFY 0xFFC07290 /* DMA18 Inner Loop Address Increment */
-#define DMA18_Y_COUNT 0xFFC07294 /* DMA18 Outer Loop Count Start Value (2D only) */
-#define DMA18_Y_MODIFY 0xFFC07298 /* DMA18 Outer Loop Address Increment (2D only) */
-#define DMA18_CURR_DESC_PTR 0xFFC072A4 /* DMA18 Current Descriptor Pointer */
-#define DMA18_PREV_DESC_PTR 0xFFC072A8 /* DMA18 Previous Initial Descriptor Pointer */
-#define DMA18_CURR_ADDR 0xFFC072AC /* DMA18 Current Address */
-#define DMA18_IRQ_STATUS 0xFFC072B0 /* DMA18 Status Register */
-#define DMA18_CURR_X_COUNT 0xFFC072B4 /* DMA18 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA18_CURR_Y_COUNT 0xFFC072B8 /* DMA18 Current Row Count (2D only) */
-#define DMA18_BWL_COUNT 0xFFC072C0 /* DMA18 Bandwidth Limit Count */
-#define DMA18_CURR_BWL_COUNT 0xFFC072C4 /* DMA18 Bandwidth Limit Count Current */
-#define DMA18_BWM_COUNT 0xFFC072C8 /* DMA18 Bandwidth Monitor Count */
-#define DMA18_CURR_BWM_COUNT 0xFFC072CC /* DMA18 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA19
- ========================= */
-#define DMA19_NEXT_DESC_PTR 0xFFC07300 /* DMA19 Pointer to Next Initial Descriptor */
-#define DMA19_START_ADDR 0xFFC07304 /* DMA19 Start Address of Current Buffer */
-#define DMA19_CONFIG 0xFFC07308 /* DMA19 Configuration Register */
-#define DMA19_X_COUNT 0xFFC0730C /* DMA19 Inner Loop Count Start Value */
-#define DMA19_X_MODIFY 0xFFC07310 /* DMA19 Inner Loop Address Increment */
-#define DMA19_Y_COUNT 0xFFC07314 /* DMA19 Outer Loop Count Start Value (2D only) */
-#define DMA19_Y_MODIFY 0xFFC07318 /* DMA19 Outer Loop Address Increment (2D only) */
-#define DMA19_CURR_DESC_PTR 0xFFC07324 /* DMA19 Current Descriptor Pointer */
-#define DMA19_PREV_DESC_PTR 0xFFC07328 /* DMA19 Previous Initial Descriptor Pointer */
-#define DMA19_CURR_ADDR 0xFFC0732C /* DMA19 Current Address */
-#define DMA19_IRQ_STATUS 0xFFC07330 /* DMA19 Status Register */
-#define DMA19_CURR_X_COUNT 0xFFC07334 /* DMA19 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA19_CURR_Y_COUNT 0xFFC07338 /* DMA19 Current Row Count (2D only) */
-#define DMA19_BWL_COUNT 0xFFC07340 /* DMA19 Bandwidth Limit Count */
-#define DMA19_CURR_BWL_COUNT 0xFFC07344 /* DMA19 Bandwidth Limit Count Current */
-#define DMA19_BWM_COUNT 0xFFC07348 /* DMA19 Bandwidth Monitor Count */
-#define DMA19_CURR_BWM_COUNT 0xFFC0734C /* DMA19 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA20
- ========================= */
-#define DMA20_NEXT_DESC_PTR 0xFFC07380 /* DMA20 Pointer to Next Initial Descriptor */
-#define DMA20_START_ADDR 0xFFC07384 /* DMA20 Start Address of Current Buffer */
-#define DMA20_CONFIG 0xFFC07388 /* DMA20 Configuration Register */
-#define DMA20_X_COUNT 0xFFC0738C /* DMA20 Inner Loop Count Start Value */
-#define DMA20_X_MODIFY 0xFFC07390 /* DMA20 Inner Loop Address Increment */
-#define DMA20_Y_COUNT 0xFFC07394 /* DMA20 Outer Loop Count Start Value (2D only) */
-#define DMA20_Y_MODIFY 0xFFC07398 /* DMA20 Outer Loop Address Increment (2D only) */
-#define DMA20_CURR_DESC_PTR 0xFFC073A4 /* DMA20 Current Descriptor Pointer */
-#define DMA20_PREV_DESC_PTR 0xFFC073A8 /* DMA20 Previous Initial Descriptor Pointer */
-#define DMA20_CURR_ADDR 0xFFC073AC /* DMA20 Current Address */
-#define DMA20_IRQ_STATUS 0xFFC073B0 /* DMA20 Status Register */
-#define DMA20_CURR_X_COUNT 0xFFC073B4 /* DMA20 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA20_CURR_Y_COUNT 0xFFC073B8 /* DMA20 Current Row Count (2D only) */
-#define DMA20_BWL_COUNT 0xFFC073C0 /* DMA20 Bandwidth Limit Count */
-#define DMA20_CURR_BWL_COUNT 0xFFC073C4 /* DMA20 Bandwidth Limit Count Current */
-#define DMA20_BWM_COUNT 0xFFC073C8 /* DMA20 Bandwidth Monitor Count */
-#define DMA20_CURR_BWM_COUNT 0xFFC073CC /* DMA20 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA21
- ========================= */
-#define DMA21_NEXT_DESC_PTR 0xFFC09000 /* DMA21 Pointer to Next Initial Descriptor */
-#define DMA21_START_ADDR 0xFFC09004 /* DMA21 Start Address of Current Buffer */
-#define DMA21_CONFIG 0xFFC09008 /* DMA21 Configuration Register */
-#define DMA21_X_COUNT 0xFFC0900C /* DMA21 Inner Loop Count Start Value */
-#define DMA21_X_MODIFY 0xFFC09010 /* DMA21 Inner Loop Address Increment */
-#define DMA21_Y_COUNT 0xFFC09014 /* DMA21 Outer Loop Count Start Value (2D only) */
-#define DMA21_Y_MODIFY 0xFFC09018 /* DMA21 Outer Loop Address Increment (2D only) */
-#define DMA21_CURR_DESC_PTR 0xFFC09024 /* DMA21 Current Descriptor Pointer */
-#define DMA21_PREV_DESC_PTR 0xFFC09028 /* DMA21 Previous Initial Descriptor Pointer */
-#define DMA21_CURR_ADDR 0xFFC0902C /* DMA21 Current Address */
-#define DMA21_IRQ_STATUS 0xFFC09030 /* DMA21 Status Register */
-#define DMA21_CURR_X_COUNT 0xFFC09034 /* DMA21 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA21_CURR_Y_COUNT 0xFFC09038 /* DMA21 Current Row Count (2D only) */
-#define DMA21_BWL_COUNT 0xFFC09040 /* DMA21 Bandwidth Limit Count */
-#define DMA21_CURR_BWL_COUNT 0xFFC09044 /* DMA21 Bandwidth Limit Count Current */
-#define DMA21_BWM_COUNT 0xFFC09048 /* DMA21 Bandwidth Monitor Count */
-#define DMA21_CURR_BWM_COUNT 0xFFC0904C /* DMA21 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA22
- ========================= */
-#define DMA22_NEXT_DESC_PTR 0xFFC09080 /* DMA22 Pointer to Next Initial Descriptor */
-#define DMA22_START_ADDR 0xFFC09084 /* DMA22 Start Address of Current Buffer */
-#define DMA22_CONFIG 0xFFC09088 /* DMA22 Configuration Register */
-#define DMA22_X_COUNT 0xFFC0908C /* DMA22 Inner Loop Count Start Value */
-#define DMA22_X_MODIFY 0xFFC09090 /* DMA22 Inner Loop Address Increment */
-#define DMA22_Y_COUNT 0xFFC09094 /* DMA22 Outer Loop Count Start Value (2D only) */
-#define DMA22_Y_MODIFY 0xFFC09098 /* DMA22 Outer Loop Address Increment (2D only) */
-#define DMA22_CURR_DESC_PTR 0xFFC090A4 /* DMA22 Current Descriptor Pointer */
-#define DMA22_PREV_DESC_PTR 0xFFC090A8 /* DMA22 Previous Initial Descriptor Pointer */
-#define DMA22_CURR_ADDR 0xFFC090AC /* DMA22 Current Address */
-#define DMA22_IRQ_STATUS 0xFFC090B0 /* DMA22 Status Register */
-#define DMA22_CURR_X_COUNT 0xFFC090B4 /* DMA22 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA22_CURR_Y_COUNT 0xFFC090B8 /* DMA22 Current Row Count (2D only) */
-#define DMA22_BWL_COUNT 0xFFC090C0 /* DMA22 Bandwidth Limit Count */
-#define DMA22_CURR_BWL_COUNT 0xFFC090C4 /* DMA22 Bandwidth Limit Count Current */
-#define DMA22_BWM_COUNT 0xFFC090C8 /* DMA22 Bandwidth Monitor Count */
-#define DMA22_CURR_BWM_COUNT 0xFFC090CC /* DMA22 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA23
- ========================= */
-#define DMA23_NEXT_DESC_PTR 0xFFC09100 /* DMA23 Pointer to Next Initial Descriptor */
-#define DMA23_START_ADDR 0xFFC09104 /* DMA23 Start Address of Current Buffer */
-#define DMA23_CONFIG 0xFFC09108 /* DMA23 Configuration Register */
-#define DMA23_X_COUNT 0xFFC0910C /* DMA23 Inner Loop Count Start Value */
-#define DMA23_X_MODIFY 0xFFC09110 /* DMA23 Inner Loop Address Increment */
-#define DMA23_Y_COUNT 0xFFC09114 /* DMA23 Outer Loop Count Start Value (2D only) */
-#define DMA23_Y_MODIFY 0xFFC09118 /* DMA23 Outer Loop Address Increment (2D only) */
-#define DMA23_CURR_DESC_PTR 0xFFC09124 /* DMA23 Current Descriptor Pointer */
-#define DMA23_PREV_DESC_PTR 0xFFC09128 /* DMA23 Previous Initial Descriptor Pointer */
-#define DMA23_CURR_ADDR 0xFFC0912C /* DMA23 Current Address */
-#define DMA23_IRQ_STATUS 0xFFC09130 /* DMA23 Status Register */
-#define DMA23_CURR_X_COUNT 0xFFC09134 /* DMA23 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA23_CURR_Y_COUNT 0xFFC09138 /* DMA23 Current Row Count (2D only) */
-#define DMA23_BWL_COUNT 0xFFC09140 /* DMA23 Bandwidth Limit Count */
-#define DMA23_CURR_BWL_COUNT 0xFFC09144 /* DMA23 Bandwidth Limit Count Current */
-#define DMA23_BWM_COUNT 0xFFC09148 /* DMA23 Bandwidth Monitor Count */
-#define DMA23_CURR_BWM_COUNT 0xFFC0914C /* DMA23 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA24
- ========================= */
-#define DMA24_NEXT_DESC_PTR 0xFFC09180 /* DMA24 Pointer to Next Initial Descriptor */
-#define DMA24_START_ADDR 0xFFC09184 /* DMA24 Start Address of Current Buffer */
-#define DMA24_CONFIG 0xFFC09188 /* DMA24 Configuration Register */
-#define DMA24_X_COUNT 0xFFC0918C /* DMA24 Inner Loop Count Start Value */
-#define DMA24_X_MODIFY 0xFFC09190 /* DMA24 Inner Loop Address Increment */
-#define DMA24_Y_COUNT 0xFFC09194 /* DMA24 Outer Loop Count Start Value (2D only) */
-#define DMA24_Y_MODIFY 0xFFC09198 /* DMA24 Outer Loop Address Increment (2D only) */
-#define DMA24_CURR_DESC_PTR 0xFFC091A4 /* DMA24 Current Descriptor Pointer */
-#define DMA24_PREV_DESC_PTR 0xFFC091A8 /* DMA24 Previous Initial Descriptor Pointer */
-#define DMA24_CURR_ADDR 0xFFC091AC /* DMA24 Current Address */
-#define DMA24_IRQ_STATUS 0xFFC091B0 /* DMA24 Status Register */
-#define DMA24_CURR_X_COUNT 0xFFC091B4 /* DMA24 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA24_CURR_Y_COUNT 0xFFC091B8 /* DMA24 Current Row Count (2D only) */
-#define DMA24_BWL_COUNT 0xFFC091C0 /* DMA24 Bandwidth Limit Count */
-#define DMA24_CURR_BWL_COUNT 0xFFC091C4 /* DMA24 Bandwidth Limit Count Current */
-#define DMA24_BWM_COUNT 0xFFC091C8 /* DMA24 Bandwidth Monitor Count */
-#define DMA24_CURR_BWM_COUNT 0xFFC091CC /* DMA24 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA25
- ========================= */
-#define DMA25_NEXT_DESC_PTR 0xFFC09200 /* DMA25 Pointer to Next Initial Descriptor */
-#define DMA25_START_ADDR 0xFFC09204 /* DMA25 Start Address of Current Buffer */
-#define DMA25_CONFIG 0xFFC09208 /* DMA25 Configuration Register */
-#define DMA25_X_COUNT 0xFFC0920C /* DMA25 Inner Loop Count Start Value */
-#define DMA25_X_MODIFY 0xFFC09210 /* DMA25 Inner Loop Address Increment */
-#define DMA25_Y_COUNT 0xFFC09214 /* DMA25 Outer Loop Count Start Value (2D only) */
-#define DMA25_Y_MODIFY 0xFFC09218 /* DMA25 Outer Loop Address Increment (2D only) */
-#define DMA25_CURR_DESC_PTR 0xFFC09224 /* DMA25 Current Descriptor Pointer */
-#define DMA25_PREV_DESC_PTR 0xFFC09228 /* DMA25 Previous Initial Descriptor Pointer */
-#define DMA25_CURR_ADDR 0xFFC0922C /* DMA25 Current Address */
-#define DMA25_IRQ_STATUS 0xFFC09230 /* DMA25 Status Register */
-#define DMA25_CURR_X_COUNT 0xFFC09234 /* DMA25 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA25_CURR_Y_COUNT 0xFFC09238 /* DMA25 Current Row Count (2D only) */
-#define DMA25_BWL_COUNT 0xFFC09240 /* DMA25 Bandwidth Limit Count */
-#define DMA25_CURR_BWL_COUNT 0xFFC09244 /* DMA25 Bandwidth Limit Count Current */
-#define DMA25_BWM_COUNT 0xFFC09248 /* DMA25 Bandwidth Monitor Count */
-#define DMA25_CURR_BWM_COUNT 0xFFC0924C /* DMA25 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA26
- ========================= */
-#define DMA26_NEXT_DESC_PTR 0xFFC09280 /* DMA26 Pointer to Next Initial Descriptor */
-#define DMA26_START_ADDR 0xFFC09284 /* DMA26 Start Address of Current Buffer */
-#define DMA26_CONFIG 0xFFC09288 /* DMA26 Configuration Register */
-#define DMA26_X_COUNT 0xFFC0928C /* DMA26 Inner Loop Count Start Value */
-#define DMA26_X_MODIFY 0xFFC09290 /* DMA26 Inner Loop Address Increment */
-#define DMA26_Y_COUNT 0xFFC09294 /* DMA26 Outer Loop Count Start Value (2D only) */
-#define DMA26_Y_MODIFY 0xFFC09298 /* DMA26 Outer Loop Address Increment (2D only) */
-#define DMA26_CURR_DESC_PTR 0xFFC092A4 /* DMA26 Current Descriptor Pointer */
-#define DMA26_PREV_DESC_PTR 0xFFC092A8 /* DMA26 Previous Initial Descriptor Pointer */
-#define DMA26_CURR_ADDR 0xFFC092AC /* DMA26 Current Address */
-#define DMA26_IRQ_STATUS 0xFFC092B0 /* DMA26 Status Register */
-#define DMA26_CURR_X_COUNT 0xFFC092B4 /* DMA26 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA26_CURR_Y_COUNT 0xFFC092B8 /* DMA26 Current Row Count (2D only) */
-#define DMA26_BWL_COUNT 0xFFC092C0 /* DMA26 Bandwidth Limit Count */
-#define DMA26_CURR_BWL_COUNT 0xFFC092C4 /* DMA26 Bandwidth Limit Count Current */
-#define DMA26_BWM_COUNT 0xFFC092C8 /* DMA26 Bandwidth Monitor Count */
-#define DMA26_CURR_BWM_COUNT 0xFFC092CC /* DMA26 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA27
- ========================= */
-#define DMA27_NEXT_DESC_PTR 0xFFC09300 /* DMA27 Pointer to Next Initial Descriptor */
-#define DMA27_START_ADDR 0xFFC09304 /* DMA27 Start Address of Current Buffer */
-#define DMA27_CONFIG 0xFFC09308 /* DMA27 Configuration Register */
-#define DMA27_X_COUNT 0xFFC0930C /* DMA27 Inner Loop Count Start Value */
-#define DMA27_X_MODIFY 0xFFC09310 /* DMA27 Inner Loop Address Increment */
-#define DMA27_Y_COUNT 0xFFC09314 /* DMA27 Outer Loop Count Start Value (2D only) */
-#define DMA27_Y_MODIFY 0xFFC09318 /* DMA27 Outer Loop Address Increment (2D only) */
-#define DMA27_CURR_DESC_PTR 0xFFC09324 /* DMA27 Current Descriptor Pointer */
-#define DMA27_PREV_DESC_PTR 0xFFC09328 /* DMA27 Previous Initial Descriptor Pointer */
-#define DMA27_CURR_ADDR 0xFFC0932C /* DMA27 Current Address */
-#define DMA27_IRQ_STATUS 0xFFC09330 /* DMA27 Status Register */
-#define DMA27_CURR_X_COUNT 0xFFC09334 /* DMA27 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA27_CURR_Y_COUNT 0xFFC09338 /* DMA27 Current Row Count (2D only) */
-#define DMA27_BWL_COUNT 0xFFC09340 /* DMA27 Bandwidth Limit Count */
-#define DMA27_CURR_BWL_COUNT 0xFFC09344 /* DMA27 Bandwidth Limit Count Current */
-#define DMA27_BWM_COUNT 0xFFC09348 /* DMA27 Bandwidth Monitor Count */
-#define DMA27_CURR_BWM_COUNT 0xFFC0934C /* DMA27 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA28
- ========================= */
-#define DMA28_NEXT_DESC_PTR 0xFFC09380 /* DMA28 Pointer to Next Initial Descriptor */
-#define DMA28_START_ADDR 0xFFC09384 /* DMA28 Start Address of Current Buffer */
-#define DMA28_CONFIG 0xFFC09388 /* DMA28 Configuration Register */
-#define DMA28_X_COUNT 0xFFC0938C /* DMA28 Inner Loop Count Start Value */
-#define DMA28_X_MODIFY 0xFFC09390 /* DMA28 Inner Loop Address Increment */
-#define DMA28_Y_COUNT 0xFFC09394 /* DMA28 Outer Loop Count Start Value (2D only) */
-#define DMA28_Y_MODIFY 0xFFC09398 /* DMA28 Outer Loop Address Increment (2D only) */
-#define DMA28_CURR_DESC_PTR 0xFFC093A4 /* DMA28 Current Descriptor Pointer */
-#define DMA28_PREV_DESC_PTR 0xFFC093A8 /* DMA28 Previous Initial Descriptor Pointer */
-#define DMA28_CURR_ADDR 0xFFC093AC /* DMA28 Current Address */
-#define DMA28_IRQ_STATUS 0xFFC093B0 /* DMA28 Status Register */
-#define DMA28_CURR_X_COUNT 0xFFC093B4 /* DMA28 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA28_CURR_Y_COUNT 0xFFC093B8 /* DMA28 Current Row Count (2D only) */
-#define DMA28_BWL_COUNT 0xFFC093C0 /* DMA28 Bandwidth Limit Count */
-#define DMA28_CURR_BWL_COUNT 0xFFC093C4 /* DMA28 Bandwidth Limit Count Current */
-#define DMA28_BWM_COUNT 0xFFC093C8 /* DMA28 Bandwidth Monitor Count */
-#define DMA28_CURR_BWM_COUNT 0xFFC093CC /* DMA28 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA29
- ========================= */
-#define DMA29_NEXT_DESC_PTR 0xFFC0B000 /* DMA29 Pointer to Next Initial Descriptor */
-#define DMA29_START_ADDR 0xFFC0B004 /* DMA29 Start Address of Current Buffer */
-#define DMA29_CONFIG 0xFFC0B008 /* DMA29 Configuration Register */
-#define DMA29_X_COUNT 0xFFC0B00C /* DMA29 Inner Loop Count Start Value */
-#define DMA29_X_MODIFY 0xFFC0B010 /* DMA29 Inner Loop Address Increment */
-#define DMA29_Y_COUNT 0xFFC0B014 /* DMA29 Outer Loop Count Start Value (2D only) */
-#define DMA29_Y_MODIFY 0xFFC0B018 /* DMA29 Outer Loop Address Increment (2D only) */
-#define DMA29_CURR_DESC_PTR 0xFFC0B024 /* DMA29 Current Descriptor Pointer */
-#define DMA29_PREV_DESC_PTR 0xFFC0B028 /* DMA29 Previous Initial Descriptor Pointer */
-#define DMA29_CURR_ADDR 0xFFC0B02C /* DMA29 Current Address */
-#define DMA29_IRQ_STATUS 0xFFC0B030 /* DMA29 Status Register */
-#define DMA29_CURR_X_COUNT 0xFFC0B034 /* DMA29 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA29_CURR_Y_COUNT 0xFFC0B038 /* DMA29 Current Row Count (2D only) */
-#define DMA29_BWL_COUNT 0xFFC0B040 /* DMA29 Bandwidth Limit Count */
-#define DMA29_CURR_BWL_COUNT 0xFFC0B044 /* DMA29 Bandwidth Limit Count Current */
-#define DMA29_BWM_COUNT 0xFFC0B048 /* DMA29 Bandwidth Monitor Count */
-#define DMA29_CURR_BWM_COUNT 0xFFC0B04C /* DMA29 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA30
- ========================= */
-#define DMA30_NEXT_DESC_PTR 0xFFC0B080 /* DMA30 Pointer to Next Initial Descriptor */
-#define DMA30_START_ADDR 0xFFC0B084 /* DMA30 Start Address of Current Buffer */
-#define DMA30_CONFIG 0xFFC0B088 /* DMA30 Configuration Register */
-#define DMA30_X_COUNT 0xFFC0B08C /* DMA30 Inner Loop Count Start Value */
-#define DMA30_X_MODIFY 0xFFC0B090 /* DMA30 Inner Loop Address Increment */
-#define DMA30_Y_COUNT 0xFFC0B094 /* DMA30 Outer Loop Count Start Value (2D only) */
-#define DMA30_Y_MODIFY 0xFFC0B098 /* DMA30 Outer Loop Address Increment (2D only) */
-#define DMA30_CURR_DESC_PTR 0xFFC0B0A4 /* DMA30 Current Descriptor Pointer */
-#define DMA30_PREV_DESC_PTR 0xFFC0B0A8 /* DMA30 Previous Initial Descriptor Pointer */
-#define DMA30_CURR_ADDR 0xFFC0B0AC /* DMA30 Current Address */
-#define DMA30_IRQ_STATUS 0xFFC0B0B0 /* DMA30 Status Register */
-#define DMA30_CURR_X_COUNT 0xFFC0B0B4 /* DMA30 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA30_CURR_Y_COUNT 0xFFC0B0B8 /* DMA30 Current Row Count (2D only) */
-#define DMA30_BWL_COUNT 0xFFC0B0C0 /* DMA30 Bandwidth Limit Count */
-#define DMA30_CURR_BWL_COUNT 0xFFC0B0C4 /* DMA30 Bandwidth Limit Count Current */
-#define DMA30_BWM_COUNT 0xFFC0B0C8 /* DMA30 Bandwidth Monitor Count */
-#define DMA30_CURR_BWM_COUNT 0xFFC0B0CC /* DMA30 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA31
- ========================= */
-#define DMA31_NEXT_DESC_PTR 0xFFC0B100 /* DMA31 Pointer to Next Initial Descriptor */
-#define DMA31_START_ADDR 0xFFC0B104 /* DMA31 Start Address of Current Buffer */
-#define DMA31_CONFIG 0xFFC0B108 /* DMA31 Configuration Register */
-#define DMA31_X_COUNT 0xFFC0B10C /* DMA31 Inner Loop Count Start Value */
-#define DMA31_X_MODIFY 0xFFC0B110 /* DMA31 Inner Loop Address Increment */
-#define DMA31_Y_COUNT 0xFFC0B114 /* DMA31 Outer Loop Count Start Value (2D only) */
-#define DMA31_Y_MODIFY 0xFFC0B118 /* DMA31 Outer Loop Address Increment (2D only) */
-#define DMA31_CURR_DESC_PTR 0xFFC0B124 /* DMA31 Current Descriptor Pointer */
-#define DMA31_PREV_DESC_PTR 0xFFC0B128 /* DMA31 Previous Initial Descriptor Pointer */
-#define DMA31_CURR_ADDR 0xFFC0B12C /* DMA31 Current Address */
-#define DMA31_IRQ_STATUS 0xFFC0B130 /* DMA31 Status Register */
-#define DMA31_CURR_X_COUNT 0xFFC0B134 /* DMA31 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA31_CURR_Y_COUNT 0xFFC0B138 /* DMA31 Current Row Count (2D only) */
-#define DMA31_BWL_COUNT 0xFFC0B140 /* DMA31 Bandwidth Limit Count */
-#define DMA31_CURR_BWL_COUNT 0xFFC0B144 /* DMA31 Bandwidth Limit Count Current */
-#define DMA31_BWM_COUNT 0xFFC0B148 /* DMA31 Bandwidth Monitor Count */
-#define DMA31_CURR_BWM_COUNT 0xFFC0B14C /* DMA31 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA32
- ========================= */
-#define DMA32_NEXT_DESC_PTR 0xFFC0B180 /* DMA32 Pointer to Next Initial Descriptor */
-#define DMA32_START_ADDR 0xFFC0B184 /* DMA32 Start Address of Current Buffer */
-#define DMA32_CONFIG 0xFFC0B188 /* DMA32 Configuration Register */
-#define DMA32_X_COUNT 0xFFC0B18C /* DMA32 Inner Loop Count Start Value */
-#define DMA32_X_MODIFY 0xFFC0B190 /* DMA32 Inner Loop Address Increment */
-#define DMA32_Y_COUNT 0xFFC0B194 /* DMA32 Outer Loop Count Start Value (2D only) */
-#define DMA32_Y_MODIFY 0xFFC0B198 /* DMA32 Outer Loop Address Increment (2D only) */
-#define DMA32_CURR_DESC_PTR 0xFFC0B1A4 /* DMA32 Current Descriptor Pointer */
-#define DMA32_PREV_DESC_PTR 0xFFC0B1A8 /* DMA32 Previous Initial Descriptor Pointer */
-#define DMA32_CURR_ADDR 0xFFC0B1AC /* DMA32 Current Address */
-#define DMA32_IRQ_STATUS 0xFFC0B1B0 /* DMA32 Status Register */
-#define DMA32_CURR_X_COUNT 0xFFC0B1B4 /* DMA32 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA32_CURR_Y_COUNT 0xFFC0B1B8 /* DMA32 Current Row Count (2D only) */
-#define DMA32_BWL_COUNT 0xFFC0B1C0 /* DMA32 Bandwidth Limit Count */
-#define DMA32_CURR_BWL_COUNT 0xFFC0B1C4 /* DMA32 Bandwidth Limit Count Current */
-#define DMA32_BWM_COUNT 0xFFC0B1C8 /* DMA32 Bandwidth Monitor Count */
-#define DMA32_CURR_BWM_COUNT 0xFFC0B1CC /* DMA32 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA33
- ========================= */
-#define DMA33_NEXT_DESC_PTR 0xFFC0D000 /* DMA33 Pointer to Next Initial Descriptor */
-#define DMA33_START_ADDR 0xFFC0D004 /* DMA33 Start Address of Current Buffer */
-#define DMA33_CONFIG 0xFFC0D008 /* DMA33 Configuration Register */
-#define DMA33_X_COUNT 0xFFC0D00C /* DMA33 Inner Loop Count Start Value */
-#define DMA33_X_MODIFY 0xFFC0D010 /* DMA33 Inner Loop Address Increment */
-#define DMA33_Y_COUNT 0xFFC0D014 /* DMA33 Outer Loop Count Start Value (2D only) */
-#define DMA33_Y_MODIFY 0xFFC0D018 /* DMA33 Outer Loop Address Increment (2D only) */
-#define DMA33_CURR_DESC_PTR 0xFFC0D024 /* DMA33 Current Descriptor Pointer */
-#define DMA33_PREV_DESC_PTR 0xFFC0D028 /* DMA33 Previous Initial Descriptor Pointer */
-#define DMA33_CURR_ADDR 0xFFC0D02C /* DMA33 Current Address */
-#define DMA33_IRQ_STATUS 0xFFC0D030 /* DMA33 Status Register */
-#define DMA33_CURR_X_COUNT 0xFFC0D034 /* DMA33 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA33_CURR_Y_COUNT 0xFFC0D038 /* DMA33 Current Row Count (2D only) */
-#define DMA33_BWL_COUNT 0xFFC0D040 /* DMA33 Bandwidth Limit Count */
-#define DMA33_CURR_BWL_COUNT 0xFFC0D044 /* DMA33 Bandwidth Limit Count Current */
-#define DMA33_BWM_COUNT 0xFFC0D048 /* DMA33 Bandwidth Monitor Count */
-#define DMA33_CURR_BWM_COUNT 0xFFC0D04C /* DMA33 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA34
- ========================= */
-#define DMA34_NEXT_DESC_PTR 0xFFC0D080 /* DMA34 Pointer to Next Initial Descriptor */
-#define DMA34_START_ADDR 0xFFC0D084 /* DMA34 Start Address of Current Buffer */
-#define DMA34_CONFIG 0xFFC0D088 /* DMA34 Configuration Register */
-#define DMA34_X_COUNT 0xFFC0D08C /* DMA34 Inner Loop Count Start Value */
-#define DMA34_X_MODIFY 0xFFC0D090 /* DMA34 Inner Loop Address Increment */
-#define DMA34_Y_COUNT 0xFFC0D094 /* DMA34 Outer Loop Count Start Value (2D only) */
-#define DMA34_Y_MODIFY 0xFFC0D098 /* DMA34 Outer Loop Address Increment (2D only) */
-#define DMA34_CURR_DESC_PTR 0xFFC0D0A4 /* DMA34 Current Descriptor Pointer */
-#define DMA34_PREV_DESC_PTR 0xFFC0D0A8 /* DMA34 Previous Initial Descriptor Pointer */
-#define DMA34_CURR_ADDR 0xFFC0D0AC /* DMA34 Current Address */
-#define DMA34_IRQ_STATUS 0xFFC0D0B0 /* DMA34 Status Register */
-#define DMA34_CURR_X_COUNT 0xFFC0D0B4 /* DMA34 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA34_CURR_Y_COUNT 0xFFC0D0B8 /* DMA34 Current Row Count (2D only) */
-#define DMA34_BWL_COUNT 0xFFC0D0C0 /* DMA34 Bandwidth Limit Count */
-#define DMA34_CURR_BWL_COUNT 0xFFC0D0C4 /* DMA34 Bandwidth Limit Count Current */
-#define DMA34_BWM_COUNT 0xFFC0D0C8 /* DMA34 Bandwidth Monitor Count */
-#define DMA34_CURR_BWM_COUNT 0xFFC0D0CC /* DMA34 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA35
- ========================= */
-#define DMA35_NEXT_DESC_PTR 0xFFC10000 /* DMA35 Pointer to Next Initial Descriptor */
-#define DMA35_START_ADDR 0xFFC10004 /* DMA35 Start Address of Current Buffer */
-#define DMA35_CONFIG 0xFFC10008 /* DMA35 Configuration Register */
-#define DMA35_X_COUNT 0xFFC1000C /* DMA35 Inner Loop Count Start Value */
-#define DMA35_X_MODIFY 0xFFC10010 /* DMA35 Inner Loop Address Increment */
-#define DMA35_Y_COUNT 0xFFC10014 /* DMA35 Outer Loop Count Start Value (2D only) */
-#define DMA35_Y_MODIFY 0xFFC10018 /* DMA35 Outer Loop Address Increment (2D only) */
-#define DMA35_CURR_DESC_PTR 0xFFC10024 /* DMA35 Current Descriptor Pointer */
-#define DMA35_PREV_DESC_PTR 0xFFC10028 /* DMA35 Previous Initial Descriptor Pointer */
-#define DMA35_CURR_ADDR 0xFFC1002C /* DMA35 Current Address */
-#define DMA35_IRQ_STATUS 0xFFC10030 /* DMA35 Status Register */
-#define DMA35_CURR_X_COUNT 0xFFC10034 /* DMA35 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA35_CURR_Y_COUNT 0xFFC10038 /* DMA35 Current Row Count (2D only) */
-#define DMA35_BWL_COUNT 0xFFC10040 /* DMA35 Bandwidth Limit Count */
-#define DMA35_CURR_BWL_COUNT 0xFFC10044 /* DMA35 Bandwidth Limit Count Current */
-#define DMA35_BWM_COUNT 0xFFC10048 /* DMA35 Bandwidth Monitor Count */
-#define DMA35_CURR_BWM_COUNT 0xFFC1004C /* DMA35 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA36
- ========================= */
-#define DMA36_NEXT_DESC_PTR 0xFFC10080 /* DMA36 Pointer to Next Initial Descriptor */
-#define DMA36_START_ADDR 0xFFC10084 /* DMA36 Start Address of Current Buffer */
-#define DMA36_CONFIG 0xFFC10088 /* DMA36 Configuration Register */
-#define DMA36_X_COUNT 0xFFC1008C /* DMA36 Inner Loop Count Start Value */
-#define DMA36_X_MODIFY 0xFFC10090 /* DMA36 Inner Loop Address Increment */
-#define DMA36_Y_COUNT 0xFFC10094 /* DMA36 Outer Loop Count Start Value (2D only) */
-#define DMA36_Y_MODIFY 0xFFC10098 /* DMA36 Outer Loop Address Increment (2D only) */
-#define DMA36_CURR_DESC_PTR 0xFFC100A4 /* DMA36 Current Descriptor Pointer */
-#define DMA36_PREV_DESC_PTR 0xFFC100A8 /* DMA36 Previous Initial Descriptor Pointer */
-#define DMA36_CURR_ADDR 0xFFC100AC /* DMA36 Current Address */
-#define DMA36_IRQ_STATUS 0xFFC100B0 /* DMA36 Status Register */
-#define DMA36_CURR_X_COUNT 0xFFC100B4 /* DMA36 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA36_CURR_Y_COUNT 0xFFC100B8 /* DMA36 Current Row Count (2D only) */
-#define DMA36_BWL_COUNT 0xFFC100C0 /* DMA36 Bandwidth Limit Count */
-#define DMA36_CURR_BWL_COUNT 0xFFC100C4 /* DMA36 Bandwidth Limit Count Current */
-#define DMA36_BWM_COUNT 0xFFC100C8 /* DMA36 Bandwidth Monitor Count */
-#define DMA36_CURR_BWM_COUNT 0xFFC100CC /* DMA36 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA37
- ========================= */
-#define DMA37_NEXT_DESC_PTR 0xFFC10100 /* DMA37 Pointer to Next Initial Descriptor */
-#define DMA37_START_ADDR 0xFFC10104 /* DMA37 Start Address of Current Buffer */
-#define DMA37_CONFIG 0xFFC10108 /* DMA37 Configuration Register */
-#define DMA37_X_COUNT 0xFFC1010C /* DMA37 Inner Loop Count Start Value */
-#define DMA37_X_MODIFY 0xFFC10110 /* DMA37 Inner Loop Address Increment */
-#define DMA37_Y_COUNT 0xFFC10114 /* DMA37 Outer Loop Count Start Value (2D only) */
-#define DMA37_Y_MODIFY 0xFFC10118 /* DMA37 Outer Loop Address Increment (2D only) */
-#define DMA37_CURR_DESC_PTR 0xFFC10124 /* DMA37 Current Descriptor Pointer */
-#define DMA37_PREV_DESC_PTR 0xFFC10128 /* DMA37 Previous Initial Descriptor Pointer */
-#define DMA37_CURR_ADDR 0xFFC1012C /* DMA37 Current Address */
-#define DMA37_IRQ_STATUS 0xFFC10130 /* DMA37 Status Register */
-#define DMA37_CURR_X_COUNT 0xFFC10134 /* DMA37 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA37_CURR_Y_COUNT 0xFFC10138 /* DMA37 Current Row Count (2D only) */
-#define DMA37_BWL_COUNT 0xFFC10140 /* DMA37 Bandwidth Limit Count */
-#define DMA37_CURR_BWL_COUNT 0xFFC10144 /* DMA37 Bandwidth Limit Count Current */
-#define DMA37_BWM_COUNT 0xFFC10148 /* DMA37 Bandwidth Monitor Count */
-#define DMA37_CURR_BWM_COUNT 0xFFC1014C /* DMA37 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA38
- ========================= */
-#define DMA38_NEXT_DESC_PTR 0xFFC12000 /* DMA38 Pointer to Next Initial Descriptor */
-#define DMA38_START_ADDR 0xFFC12004 /* DMA38 Start Address of Current Buffer */
-#define DMA38_CONFIG 0xFFC12008 /* DMA38 Configuration Register */
-#define DMA38_X_COUNT 0xFFC1200C /* DMA38 Inner Loop Count Start Value */
-#define DMA38_X_MODIFY 0xFFC12010 /* DMA38 Inner Loop Address Increment */
-#define DMA38_Y_COUNT 0xFFC12014 /* DMA38 Outer Loop Count Start Value (2D only) */
-#define DMA38_Y_MODIFY 0xFFC12018 /* DMA38 Outer Loop Address Increment (2D only) */
-#define DMA38_CURR_DESC_PTR 0xFFC12024 /* DMA38 Current Descriptor Pointer */
-#define DMA38_PREV_DESC_PTR 0xFFC12028 /* DMA38 Previous Initial Descriptor Pointer */
-#define DMA38_CURR_ADDR 0xFFC1202C /* DMA38 Current Address */
-#define DMA38_IRQ_STATUS 0xFFC12030 /* DMA38 Status Register */
-#define DMA38_CURR_X_COUNT 0xFFC12034 /* DMA38 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA38_CURR_Y_COUNT 0xFFC12038 /* DMA38 Current Row Count (2D only) */
-#define DMA38_BWL_COUNT 0xFFC12040 /* DMA38 Bandwidth Limit Count */
-#define DMA38_CURR_BWL_COUNT 0xFFC12044 /* DMA38 Bandwidth Limit Count Current */
-#define DMA38_BWM_COUNT 0xFFC12048 /* DMA38 Bandwidth Monitor Count */
-#define DMA38_CURR_BWM_COUNT 0xFFC1204C /* DMA38 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA39
- ========================= */
-#define DMA39_NEXT_DESC_PTR 0xFFC12080 /* DMA39 Pointer to Next Initial Descriptor */
-#define DMA39_START_ADDR 0xFFC12084 /* DMA39 Start Address of Current Buffer */
-#define DMA39_CONFIG 0xFFC12088 /* DMA39 Configuration Register */
-#define DMA39_X_COUNT 0xFFC1208C /* DMA39 Inner Loop Count Start Value */
-#define DMA39_X_MODIFY 0xFFC12090 /* DMA39 Inner Loop Address Increment */
-#define DMA39_Y_COUNT 0xFFC12094 /* DMA39 Outer Loop Count Start Value (2D only) */
-#define DMA39_Y_MODIFY 0xFFC12098 /* DMA39 Outer Loop Address Increment (2D only) */
-#define DMA39_CURR_DESC_PTR 0xFFC120A4 /* DMA39 Current Descriptor Pointer */
-#define DMA39_PREV_DESC_PTR 0xFFC120A8 /* DMA39 Previous Initial Descriptor Pointer */
-#define DMA39_CURR_ADDR 0xFFC120AC /* DMA39 Current Address */
-#define DMA39_IRQ_STATUS 0xFFC120B0 /* DMA39 Status Register */
-#define DMA39_CURR_X_COUNT 0xFFC120B4 /* DMA39 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA39_CURR_Y_COUNT 0xFFC120B8 /* DMA39 Current Row Count (2D only) */
-#define DMA39_BWL_COUNT 0xFFC120C0 /* DMA39 Bandwidth Limit Count */
-#define DMA39_CURR_BWL_COUNT 0xFFC120C4 /* DMA39 Bandwidth Limit Count Current */
-#define DMA39_BWM_COUNT 0xFFC120C8 /* DMA39 Bandwidth Monitor Count */
-#define DMA39_CURR_BWM_COUNT 0xFFC120CC /* DMA39 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA40
- ========================= */
-#define DMA40_NEXT_DESC_PTR 0xFFC12100 /* DMA40 Pointer to Next Initial Descriptor */
-#define DMA40_START_ADDR 0xFFC12104 /* DMA40 Start Address of Current Buffer */
-#define DMA40_CONFIG 0xFFC12108 /* DMA40 Configuration Register */
-#define DMA40_X_COUNT 0xFFC1210C /* DMA40 Inner Loop Count Start Value */
-#define DMA40_X_MODIFY 0xFFC12110 /* DMA40 Inner Loop Address Increment */
-#define DMA40_Y_COUNT 0xFFC12114 /* DMA40 Outer Loop Count Start Value (2D only) */
-#define DMA40_Y_MODIFY 0xFFC12118 /* DMA40 Outer Loop Address Increment (2D only) */
-#define DMA40_CURR_DESC_PTR 0xFFC12124 /* DMA40 Current Descriptor Pointer */
-#define DMA40_PREV_DESC_PTR 0xFFC12128 /* DMA40 Previous Initial Descriptor Pointer */
-#define DMA40_CURR_ADDR 0xFFC1212C /* DMA40 Current Address */
-#define DMA40_IRQ_STATUS 0xFFC12130 /* DMA40 Status Register */
-#define DMA40_CURR_X_COUNT 0xFFC12134 /* DMA40 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA40_CURR_Y_COUNT 0xFFC12138 /* DMA40 Current Row Count (2D only) */
-#define DMA40_BWL_COUNT 0xFFC12140 /* DMA40 Bandwidth Limit Count */
-#define DMA40_CURR_BWL_COUNT 0xFFC12144 /* DMA40 Bandwidth Limit Count Current */
-#define DMA40_BWM_COUNT 0xFFC12148 /* DMA40 Bandwidth Monitor Count */
-#define DMA40_CURR_BWM_COUNT 0xFFC1214C /* DMA40 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA41
- ========================= */
-#define DMA41_NEXT_DESC_PTR 0xFFC12180 /* DMA41 Pointer to Next Initial Descriptor */
-#define DMA41_START_ADDR 0xFFC12184 /* DMA41 Start Address of Current Buffer */
-#define DMA41_CONFIG 0xFFC12188 /* DMA41 Configuration Register */
-#define DMA41_X_COUNT 0xFFC1218C /* DMA41 Inner Loop Count Start Value */
-#define DMA41_X_MODIFY 0xFFC12190 /* DMA41 Inner Loop Address Increment */
-#define DMA41_Y_COUNT 0xFFC12194 /* DMA41 Outer Loop Count Start Value (2D only) */
-#define DMA41_Y_MODIFY 0xFFC12198 /* DMA41 Outer Loop Address Increment (2D only) */
-#define DMA41_CURR_DESC_PTR 0xFFC121A4 /* DMA41 Current Descriptor Pointer */
-#define DMA41_PREV_DESC_PTR 0xFFC121A8 /* DMA41 Previous Initial Descriptor Pointer */
-#define DMA41_CURR_ADDR 0xFFC121AC /* DMA41 Current Address */
-#define DMA41_IRQ_STATUS 0xFFC121B0 /* DMA41 Status Register */
-#define DMA41_CURR_X_COUNT 0xFFC121B4 /* DMA41 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA41_CURR_Y_COUNT 0xFFC121B8 /* DMA41 Current Row Count (2D only) */
-#define DMA41_BWL_COUNT 0xFFC121C0 /* DMA41 Bandwidth Limit Count */
-#define DMA41_CURR_BWL_COUNT 0xFFC121C4 /* DMA41 Bandwidth Limit Count Current */
-#define DMA41_BWM_COUNT 0xFFC121C8 /* DMA41 Bandwidth Monitor Count */
-#define DMA41_CURR_BWM_COUNT 0xFFC121CC /* DMA41 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA42
- ========================= */
-#define DMA42_NEXT_DESC_PTR 0xFFC14000 /* DMA42 Pointer to Next Initial Descriptor */
-#define DMA42_START_ADDR 0xFFC14004 /* DMA42 Start Address of Current Buffer */
-#define DMA42_CONFIG 0xFFC14008 /* DMA42 Configuration Register */
-#define DMA42_X_COUNT 0xFFC1400C /* DMA42 Inner Loop Count Start Value */
-#define DMA42_X_MODIFY 0xFFC14010 /* DMA42 Inner Loop Address Increment */
-#define DMA42_Y_COUNT 0xFFC14014 /* DMA42 Outer Loop Count Start Value (2D only) */
-#define DMA42_Y_MODIFY 0xFFC14018 /* DMA42 Outer Loop Address Increment (2D only) */
-#define DMA42_CURR_DESC_PTR 0xFFC14024 /* DMA42 Current Descriptor Pointer */
-#define DMA42_PREV_DESC_PTR 0xFFC14028 /* DMA42 Previous Initial Descriptor Pointer */
-#define DMA42_CURR_ADDR 0xFFC1402C /* DMA42 Current Address */
-#define DMA42_IRQ_STATUS 0xFFC14030 /* DMA42 Status Register */
-#define DMA42_CURR_X_COUNT 0xFFC14034 /* DMA42 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA42_CURR_Y_COUNT 0xFFC14038 /* DMA42 Current Row Count (2D only) */
-#define DMA42_BWL_COUNT 0xFFC14040 /* DMA42 Bandwidth Limit Count */
-#define DMA42_CURR_BWL_COUNT 0xFFC14044 /* DMA42 Bandwidth Limit Count Current */
-#define DMA42_BWM_COUNT 0xFFC14048 /* DMA42 Bandwidth Monitor Count */
-#define DMA42_CURR_BWM_COUNT 0xFFC1404C /* DMA42 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA43
- ========================= */
-#define DMA43_NEXT_DESC_PTR 0xFFC14080 /* DMA43 Pointer to Next Initial Descriptor */
-#define DMA43_START_ADDR 0xFFC14084 /* DMA43 Start Address of Current Buffer */
-#define DMA43_CONFIG 0xFFC14088 /* DMA43 Configuration Register */
-#define DMA43_X_COUNT 0xFFC1408C /* DMA43 Inner Loop Count Start Value */
-#define DMA43_X_MODIFY 0xFFC14090 /* DMA43 Inner Loop Address Increment */
-#define DMA43_Y_COUNT 0xFFC14094 /* DMA43 Outer Loop Count Start Value (2D only) */
-#define DMA43_Y_MODIFY 0xFFC14098 /* DMA43 Outer Loop Address Increment (2D only) */
-#define DMA43_CURR_DESC_PTR 0xFFC140A4 /* DMA43 Current Descriptor Pointer */
-#define DMA43_PREV_DESC_PTR 0xFFC140A8 /* DMA43 Previous Initial Descriptor Pointer */
-#define DMA43_CURR_ADDR 0xFFC140AC /* DMA43 Current Address */
-#define DMA43_IRQ_STATUS 0xFFC140B0 /* DMA43 Status Register */
-#define DMA43_CURR_X_COUNT 0xFFC140B4 /* DMA43 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA43_CURR_Y_COUNT 0xFFC140B8 /* DMA43 Current Row Count (2D only) */
-#define DMA43_BWL_COUNT 0xFFC140C0 /* DMA43 Bandwidth Limit Count */
-#define DMA43_CURR_BWL_COUNT 0xFFC140C4 /* DMA43 Bandwidth Limit Count Current */
-#define DMA43_BWM_COUNT 0xFFC140C8 /* DMA43 Bandwidth Monitor Count */
-#define DMA43_CURR_BWM_COUNT 0xFFC140CC /* DMA43 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA44
- ========================= */
-#define DMA44_NEXT_DESC_PTR 0xFFC14100 /* DMA44 Pointer to Next Initial Descriptor */
-#define DMA44_START_ADDR 0xFFC14104 /* DMA44 Start Address of Current Buffer */
-#define DMA44_CONFIG 0xFFC14108 /* DMA44 Configuration Register */
-#define DMA44_X_COUNT 0xFFC1410C /* DMA44 Inner Loop Count Start Value */
-#define DMA44_X_MODIFY 0xFFC14110 /* DMA44 Inner Loop Address Increment */
-#define DMA44_Y_COUNT 0xFFC14114 /* DMA44 Outer Loop Count Start Value (2D only) */
-#define DMA44_Y_MODIFY 0xFFC14118 /* DMA44 Outer Loop Address Increment (2D only) */
-#define DMA44_CURR_DESC_PTR 0xFFC14124 /* DMA44 Current Descriptor Pointer */
-#define DMA44_PREV_DESC_PTR 0xFFC14128 /* DMA44 Previous Initial Descriptor Pointer */
-#define DMA44_CURR_ADDR 0xFFC1412C /* DMA44 Current Address */
-#define DMA44_IRQ_STATUS 0xFFC14130 /* DMA44 Status Register */
-#define DMA44_CURR_X_COUNT 0xFFC14134 /* DMA44 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA44_CURR_Y_COUNT 0xFFC14138 /* DMA44 Current Row Count (2D only) */
-#define DMA44_BWL_COUNT 0xFFC14140 /* DMA44 Bandwidth Limit Count */
-#define DMA44_CURR_BWL_COUNT 0xFFC14144 /* DMA44 Bandwidth Limit Count Current */
-#define DMA44_BWM_COUNT 0xFFC14148 /* DMA44 Bandwidth Monitor Count */
-#define DMA44_CURR_BWM_COUNT 0xFFC1414C /* DMA44 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA45
- ========================= */
-#define DMA45_NEXT_DESC_PTR 0xFFC14180 /* DMA45 Pointer to Next Initial Descriptor */
-#define DMA45_START_ADDR 0xFFC14184 /* DMA45 Start Address of Current Buffer */
-#define DMA45_CONFIG 0xFFC14188 /* DMA45 Configuration Register */
-#define DMA45_X_COUNT 0xFFC1418C /* DMA45 Inner Loop Count Start Value */
-#define DMA45_X_MODIFY 0xFFC14190 /* DMA45 Inner Loop Address Increment */
-#define DMA45_Y_COUNT 0xFFC14194 /* DMA45 Outer Loop Count Start Value (2D only) */
-#define DMA45_Y_MODIFY 0xFFC14198 /* DMA45 Outer Loop Address Increment (2D only) */
-#define DMA45_CURR_DESC_PTR 0xFFC141A4 /* DMA45 Current Descriptor Pointer */
-#define DMA45_PREV_DESC_PTR 0xFFC141A8 /* DMA45 Previous Initial Descriptor Pointer */
-#define DMA45_CURR_ADDR 0xFFC141AC /* DMA45 Current Address */
-#define DMA45_IRQ_STATUS 0xFFC141B0 /* DMA45 Status Register */
-#define DMA45_CURR_X_COUNT 0xFFC141B4 /* DMA45 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA45_CURR_Y_COUNT 0xFFC141B8 /* DMA45 Current Row Count (2D only) */
-#define DMA45_BWL_COUNT 0xFFC141C0 /* DMA45 Bandwidth Limit Count */
-#define DMA45_CURR_BWL_COUNT 0xFFC141C4 /* DMA45 Bandwidth Limit Count Current */
-#define DMA45_BWM_COUNT 0xFFC141C8 /* DMA45 Bandwidth Monitor Count */
-#define DMA45_CURR_BWM_COUNT 0xFFC141CC /* DMA45 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA46
- ========================= */
-#define DMA46_NEXT_DESC_PTR 0xFFC14200 /* DMA46 Pointer to Next Initial Descriptor */
-#define DMA46_START_ADDR 0xFFC14204 /* DMA46 Start Address of Current Buffer */
-#define DMA46_CONFIG 0xFFC14208 /* DMA46 Configuration Register */
-#define DMA46_X_COUNT 0xFFC1420C /* DMA46 Inner Loop Count Start Value */
-#define DMA46_X_MODIFY 0xFFC14210 /* DMA46 Inner Loop Address Increment */
-#define DMA46_Y_COUNT 0xFFC14214 /* DMA46 Outer Loop Count Start Value (2D only) */
-#define DMA46_Y_MODIFY 0xFFC14218 /* DMA46 Outer Loop Address Increment (2D only) */
-#define DMA46_CURR_DESC_PTR 0xFFC14224 /* DMA46 Current Descriptor Pointer */
-#define DMA46_PREV_DESC_PTR 0xFFC14228 /* DMA46 Previous Initial Descriptor Pointer */
-#define DMA46_CURR_ADDR 0xFFC1422C /* DMA46 Current Address */
-#define DMA46_IRQ_STATUS 0xFFC14230 /* DMA46 Status Register */
-#define DMA46_CURR_X_COUNT 0xFFC14234 /* DMA46 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA46_CURR_Y_COUNT 0xFFC14238 /* DMA46 Current Row Count (2D only) */
-#define DMA46_BWL_COUNT 0xFFC14240 /* DMA46 Bandwidth Limit Count */
-#define DMA46_CURR_BWL_COUNT 0xFFC14244 /* DMA46 Bandwidth Limit Count Current */
-#define DMA46_BWM_COUNT 0xFFC14248 /* DMA46 Bandwidth Monitor Count */
-#define DMA46_CURR_BWM_COUNT 0xFFC1424C /* DMA46 Bandwidth Monitor Count Current */
-
-
-/********************************************************************************
- DMA Alias Definitions
- ********************************************************************************/
-#define MDMA0_DEST_CRC0_NEXT_DESC_PTR (DMA22_NEXT_DESC_PTR)
-#define MDMA0_DEST_CRC0_START_ADDR (DMA22_START_ADDR)
-#define MDMA0_DEST_CRC0_CONFIG (DMA22_CONFIG)
-#define MDMA0_DEST_CRC0_X_COUNT (DMA22_X_COUNT)
-#define MDMA0_DEST_CRC0_X_MODIFY (DMA22_X_MODIFY)
-#define MDMA0_DEST_CRC0_Y_COUNT (DMA22_Y_COUNT)
-#define MDMA0_DEST_CRC0_Y_MODIFY (DMA22_Y_MODIFY)
-#define MDMA0_DEST_CRC0_CURR_DESC_PTR (DMA22_CURR_DESC_PTR)
-#define MDMA0_DEST_CRC0_PREV_DESC_PTR (DMA22_PREV_DESC_PTR)
-#define MDMA0_DEST_CRC0_CURR_ADDR (DMA22_CURR_ADDR)
-#define MDMA0_DEST_CRC0_IRQ_STATUS (DMA22_IRQ_STATUS)
-#define MDMA0_DEST_CRC0_CURR_X_COUNT (DMA22_CURR_X_COUNT)
-#define MDMA0_DEST_CRC0_CURR_Y_COUNT (DMA22_CURR_Y_COUNT)
-#define MDMA0_DEST_CRC0_BWL_COUNT (DMA22_BWL_COUNT)
-#define MDMA0_DEST_CRC0_CURR_BWL_COUNT (DMA22_CURR_BWL_COUNT)
-#define MDMA0_DEST_CRC0_BWM_COUNT (DMA22_BWM_COUNT)
-#define MDMA0_DEST_CRC0_CURR_BWM_COUNT (DMA22_CURR_BWM_COUNT)
-#define MDMA0_SRC_CRC0_NEXT_DESC_PTR (DMA21_NEXT_DESC_PTR)
-#define MDMA0_SRC_CRC0_START_ADDR (DMA21_START_ADDR)
-#define MDMA0_SRC_CRC0_CONFIG (DMA21_CONFIG)
-#define MDMA0_SRC_CRC0_X_COUNT (DMA21_X_COUNT)
-#define MDMA0_SRC_CRC0_X_MODIFY (DMA21_X_MODIFY)
-#define MDMA0_SRC_CRC0_Y_COUNT (DMA21_Y_COUNT)
-#define MDMA0_SRC_CRC0_Y_MODIFY (DMA21_Y_MODIFY)
-#define MDMA0_SRC_CRC0_CURR_DESC_PTR (DMA21_CURR_DESC_PTR)
-#define MDMA0_SRC_CRC0_PREV_DESC_PTR (DMA21_PREV_DESC_PTR)
-#define MDMA0_SRC_CRC0_CURR_ADDR (DMA21_CURR_ADDR)
-#define MDMA0_SRC_CRC0_IRQ_STATUS (DMA21_IRQ_STATUS)
-#define MDMA0_SRC_CRC0_CURR_X_COUNT (DMA21_CURR_X_COUNT)
-#define MDMA0_SRC_CRC0_CURR_Y_COUNT (DMA21_CURR_Y_COUNT)
-#define MDMA0_SRC_CRC0_BWL_COUNT (DMA21_BWL_COUNT)
-#define MDMA0_SRC_CRC0_CURR_BWL_COUNT (DMA21_CURR_BWL_COUNT)
-#define MDMA0_SRC_CRC0_BWM_COUNT (DMA21_BWM_COUNT)
-#define MDMA0_SRC_CRC0_CURR_BWM_COUNT (DMA21_CURR_BWM_COUNT)
-#define MDMA1_DEST_CRC1_NEXT_DESC_PTR (DMA24_NEXT_DESC_PTR)
-#define MDMA1_DEST_CRC1_START_ADDR (DMA24_START_ADDR)
-#define MDMA1_DEST_CRC1_CONFIG (DMA24_CONFIG)
-#define MDMA1_DEST_CRC1_X_COUNT (DMA24_X_COUNT)
-#define MDMA1_DEST_CRC1_X_MODIFY (DMA24_X_MODIFY)
-#define MDMA1_DEST_CRC1_Y_COUNT (DMA24_Y_COUNT)
-#define MDMA1_DEST_CRC1_Y_MODIFY (DMA24_Y_MODIFY)
-#define MDMA1_DEST_CRC1_CURR_DESC_PTR (DMA24_CURR_DESC_PTR)
-#define MDMA1_DEST_CRC1_PREV_DESC_PTR (DMA24_PREV_DESC_PTR)
-#define MDMA1_DEST_CRC1_CURR_ADDR (DMA24_CURR_ADDR)
-#define MDMA1_DEST_CRC1_IRQ_STATUS (DMA24_IRQ_STATUS)
-#define MDMA1_DEST_CRC1_CURR_X_COUNT (DMA24_CURR_X_COUNT)
-#define MDMA1_DEST_CRC1_CURR_Y_COUNT (DMA24_CURR_Y_COUNT)
-#define MDMA1_DEST_CRC1_BWL_COUNT (DMA24_BWL_COUNT)
-#define MDMA1_DEST_CRC1_CURR_BWL_COUNT (DMA24_CURR_BWL_COUNT)
-#define MDMA1_DEST_CRC1_BWM_COUNT (DMA24_BWM_COUNT)
-#define MDMA1_DEST_CRC1_CURR_BWM_COUNT (DMA24_CURR_BWM_COUNT)
-#define MDMA1_SRC_CRC1_NEXT_DESC_PTR (DMA23_NEXT_DESC_PTR)
-#define MDMA1_SRC_CRC1_START_ADDR (DMA23_START_ADDR)
-#define MDMA1_SRC_CRC1_CONFIG (DMA23_CONFIG)
-#define MDMA1_SRC_CRC1_X_COUNT (DMA23_X_COUNT)
-#define MDMA1_SRC_CRC1_X_MODIFY (DMA23_X_MODIFY)
-#define MDMA1_SRC_CRC1_Y_COUNT (DMA23_Y_COUNT)
-#define MDMA1_SRC_CRC1_Y_MODIFY (DMA23_Y_MODIFY)
-#define MDMA1_SRC_CRC1_CURR_DESC_PTR (DMA23_CURR_DESC_PTR)
-#define MDMA1_SRC_CRC1_PREV_DESC_PTR (DMA23_PREV_DESC_PTR)
-#define MDMA1_SRC_CRC1_CURR_ADDR (DMA23_CURR_ADDR)
-#define MDMA1_SRC_CRC1_IRQ_STATUS (DMA23_IRQ_STATUS)
-#define MDMA1_SRC_CRC1_CURR_X_COUNT (DMA23_CURR_X_COUNT)
-#define MDMA1_SRC_CRC1_CURR_Y_COUNT (DMA23_CURR_Y_COUNT)
-#define MDMA1_SRC_CRC1_BWL_COUNT (DMA23_BWL_COUNT)
-#define MDMA1_SRC_CRC1_CURR_BWL_COUNT (DMA23_CURR_BWL_COUNT)
-#define MDMA1_SRC_CRC1_BWM_COUNT (DMA23_BWM_COUNT)
-#define MDMA1_SRC_CRC1_CURR_BWM_COUNT (DMA23_CURR_BWM_COUNT)
-#define MDMA2_DEST_NEXT_DESC_PTR (DMA26_NEXT_DESC_PTR)
-#define MDMA2_DEST_START_ADDR (DMA26_START_ADDR)
-#define MDMA2_DEST_CONFIG (DMA26_CONFIG)
-#define MDMA2_DEST_X_COUNT (DMA26_X_COUNT)
-#define MDMA2_DEST_X_MODIFY (DMA26_X_MODIFY)
-#define MDMA2_DEST_Y_COUNT (DMA26_Y_COUNT)
-#define MDMA2_DEST_Y_MODIFY (DMA26_Y_MODIFY)
-#define MDMA2_DEST_CURR_DESC_PTR (DMA26_CURR_DESC_PTR)
-#define MDMA2_DEST_PREV_DESC_PTR (DMA26_PREV_DESC_PTR)
-#define MDMA2_DEST_CURR_ADDR (DMA26_CURR_ADDR)
-#define MDMA2_DEST_IRQ_STATUS (DMA26_IRQ_STATUS)
-#define MDMA2_DEST_CURR_X_COUNT (DMA26_CURR_X_COUNT)
-#define MDMA2_DEST_CURR_Y_COUNT (DMA26_CURR_Y_COUNT)
-#define MDMA2_DEST_BWL_COUNT (DMA26_BWL_COUNT)
-#define MDMA2_DEST_CURR_BWL_COUNT (DMA26_CURR_BWL_COUNT)
-#define MDMA2_DEST_BWM_COUNT (DMA26_BWM_COUNT)
-#define MDMA2_DEST_CURR_BWM_COUNT (DMA26_CURR_BWM_COUNT)
-#define MDMA2_SRC_NEXT_DESC_PTR (DMA25_NEXT_DESC_PTR)
-#define MDMA2_SRC_START_ADDR (DMA25_START_ADDR)
-#define MDMA2_SRC_CONFIG (DMA25_CONFIG)
-#define MDMA2_SRC_X_COUNT (DMA25_X_COUNT)
-#define MDMA2_SRC_X_MODIFY (DMA25_X_MODIFY)
-#define MDMA2_SRC_Y_COUNT (DMA25_Y_COUNT)
-#define MDMA2_SRC_Y_MODIFY (DMA25_Y_MODIFY)
-#define MDMA2_SRC_CURR_DESC_PTR (DMA25_CURR_DESC_PTR)
-#define MDMA2_SRC_PREV_DESC_PTR (DMA25_PREV_DESC_PTR)
-#define MDMA2_SRC_CURR_ADDR (DMA25_CURR_ADDR)
-#define MDMA2_SRC_IRQ_STATUS (DMA25_IRQ_STATUS)
-#define MDMA2_SRC_CURR_X_COUNT (DMA25_CURR_X_COUNT)
-#define MDMA2_SRC_CURR_Y_COUNT (DMA25_CURR_Y_COUNT)
-#define MDMA2_SRC_BWL_COUNT (DMA25_BWL_COUNT)
-#define MDMA2_SRC_CURR_BWL_COUNT (DMA25_CURR_BWL_COUNT)
-#define MDMA2_SRC_BWM_COUNT (DMA25_BWM_COUNT)
-#define MDMA2_SRC_CURR_BWM_COUNT (DMA25_CURR_BWM_COUNT)
-#define MDMA3_DEST_NEXT_DESC_PTR (DMA28_NEXT_DESC_PTR)
-#define MDMA3_DEST_START_ADDR (DMA28_START_ADDR)
-#define MDMA3_DEST_CONFIG (DMA28_CONFIG)
-#define MDMA3_DEST_X_COUNT (DMA28_X_COUNT)
-#define MDMA3_DEST_X_MODIFY (DMA28_X_MODIFY)
-#define MDMA3_DEST_Y_COUNT (DMA28_Y_COUNT)
-#define MDMA3_DEST_Y_MODIFY (DMA28_Y_MODIFY)
-#define MDMA3_DEST_CURR_DESC_PTR (DMA28_CURR_DESC_PTR)
-#define MDMA3_DEST_PREV_DESC_PTR (DMA28_PREV_DESC_PTR)
-#define MDMA3_DEST_CURR_ADDR (DMA28_CURR_ADDR)
-#define MDMA3_DEST_IRQ_STATUS (DMA28_IRQ_STATUS)
-#define MDMA3_DEST_CURR_X_COUNT (DMA28_CURR_X_COUNT)
-#define MDMA3_DEST_CURR_Y_COUNT (DMA28_CURR_Y_COUNT)
-#define MDMA3_DEST_BWL_COUNT (DMA28_BWL_COUNT)
-#define MDMA3_DEST_CURR_BWL_COUNT (DMA28_CURR_BWL_COUNT)
-#define MDMA3_DEST_BWM_COUNT (DMA28_BWM_COUNT)
-#define MDMA3_DEST_CURR_BWM_COUNT (DMA28_CURR_BWM_COUNT)
-#define MDMA3_SRC_NEXT_DESC_PTR (DMA27_NEXT_DESC_PTR)
-#define MDMA3_SRC_START_ADDR (DMA27_START_ADDR)
-#define MDMA3_SRC_CONFIG (DMA27_CONFIG)
-#define MDMA3_SRC_X_COUNT (DMA27_X_COUNT)
-#define MDMA3_SRC_X_MODIFY (DMA27_X_MODIFY)
-#define MDMA3_SRC_Y_COUNT (DMA27_Y_COUNT)
-#define MDMA3_SRC_Y_MODIFY (DMA27_Y_MODIFY)
-#define MDMA3_SRC_CURR_DESC_PTR (DMA27_CURR_DESC_PTR)
-#define MDMA3_SRC_PREV_DESC_PTR (DMA27_PREV_DESC_PTR)
-#define MDMA3_SRC_CURR_ADDR (DMA27_CURR_ADDR)
-#define MDMA3_SRC_IRQ_STATUS (DMA27_IRQ_STATUS)
-#define MDMA3_SRC_CURR_X_COUNT (DMA27_CURR_X_COUNT)
-#define MDMA3_SRC_CURR_Y_COUNT (DMA27_CURR_Y_COUNT)
-#define MDMA3_SRC_BWL_COUNT (DMA27_BWL_COUNT)
-#define MDMA3_SRC_CURR_BWL_COUNT (DMA27_CURR_BWL_COUNT)
-#define MDMA3_SRC_BWM_COUNT (DMA27_BWM_COUNT)
-#define MDMA3_SRC_CURR_BWM_COUNT (DMA27_CURR_BWM_COUNT)
-
-
-/* =========================
- DMC Registers
- ========================= */
-
-/* =========================
- DMC0
- ========================= */
-#define DMC0_ID 0xFFC80000 /* DMC0 Identification Register */
-#define DMC0_CTL 0xFFC80004 /* DMC0 Control Register */
-#define DMC0_STAT 0xFFC80008 /* DMC0 Status Register */
-#define DMC0_EFFCTL 0xFFC8000C /* DMC0 Efficiency Controller */
-#define DMC0_PRIO 0xFFC80010 /* DMC0 Priority ID Register */
-#define DMC0_PRIOMSK 0xFFC80014 /* DMC0 Priority ID Mask */
-#define DMC0_CFG 0xFFC80040 /* DMC0 SDRAM Configuration */
-#define DMC0_TR0 0xFFC80044 /* DMC0 Timing Register 0 */
-#define DMC0_TR1 0xFFC80048 /* DMC0 Timing Register 1 */
-#define DMC0_TR2 0xFFC8004C /* DMC0 Timing Register 2 */
-#define DMC0_MSK 0xFFC8005C /* DMC0 Mode Register Mask */
-#define DMC0_MR 0xFFC80060 /* DMC0 Mode Shadow register */
-#define DMC0_EMR1 0xFFC80064 /* DMC0 EMR1 Shadow Register */
-#define DMC0_EMR2 0xFFC80068 /* DMC0 EMR2 Shadow Register */
-#define DMC0_EMR3 0xFFC8006C /* DMC0 EMR3 Shadow Register */
-#define DMC0_DLLCTL 0xFFC80080 /* DMC0 DLL Control Register */
-#define DMC0_PADCTL 0xFFC800C0 /* DMC0 PAD Control Register 0 */
-
-#define DEVSZ_64 0x000 /* DMC External Bank Size = 64Mbit */
-#define DEVSZ_128 0x100 /* DMC External Bank Size = 128Mbit */
-#define DEVSZ_256 0x200 /* DMC External Bank Size = 256Mbit */
-#define DEVSZ_512 0x300 /* DMC External Bank Size = 512Mbit */
-#define DEVSZ_1G 0x400 /* DMC External Bank Size = 1Gbit */
-#define DEVSZ_2G 0x500 /* DMC External Bank Size = 2Gbit */
-
-/* =========================
- L2CTL Registers
- ========================= */
-
-/* =========================
- L2CTL0
- ========================= */
-#define L2CTL0_CTL 0xFFCA3000 /* L2CTL0 L2 Control Register */
-#define L2CTL0_ACTL_C0 0xFFCA3004 /* L2CTL0 L2 Core 0 Access Control Register */
-#define L2CTL0_ACTL_C1 0xFFCA3008 /* L2CTL0 L2 Core 1 Access Control Register */
-#define L2CTL0_ACTL_SYS 0xFFCA300C /* L2CTL0 L2 System Access Control Register */
-#define L2CTL0_STAT 0xFFCA3010 /* L2CTL0 L2 Status Register */
-#define L2CTL0_RPCR 0xFFCA3014 /* L2CTL0 L2 Read Priority Count Register */
-#define L2CTL0_WPCR 0xFFCA3018 /* L2CTL0 L2 Write Priority Count Register */
-#define L2CTL0_RFA 0xFFCA3024 /* L2CTL0 L2 Refresh Address Register */
-#define L2CTL0_ERRADDR0 0xFFCA3040 /* L2CTL0 L2 Bank 0 ECC Error Address Register */
-#define L2CTL0_ERRADDR1 0xFFCA3044 /* L2CTL0 L2 Bank 1 ECC Error Address Register */
-#define L2CTL0_ERRADDR2 0xFFCA3048 /* L2CTL0 L2 Bank 2 ECC Error Address Register */
-#define L2CTL0_ERRADDR3 0xFFCA304C /* L2CTL0 L2 Bank 3 ECC Error Address Register */
-#define L2CTL0_ERRADDR4 0xFFCA3050 /* L2CTL0 L2 Bank 4 ECC Error Address Register */
-#define L2CTL0_ERRADDR5 0xFFCA3054 /* L2CTL0 L2 Bank 5 ECC Error Address Register */
-#define L2CTL0_ERRADDR6 0xFFCA3058 /* L2CTL0 L2 Bank 6 ECC Error Address Register */
-#define L2CTL0_ERRADDR7 0xFFCA305C /* L2CTL0 L2 Bank 7 ECC Error Address Register */
-#define L2CTL0_ET0 0xFFCA3080 /* L2CTL0 L2 AXI Error 0 Type Register */
-#define L2CTL0_EADDR0 0xFFCA3084 /* L2CTL0 L2 AXI Error 0 Address Register */
-#define L2CTL0_ET1 0xFFCA3088 /* L2CTL0 L2 AXI Error 1 Type Register */
-#define L2CTL0_EADDR1 0xFFCA308C /* L2CTL0 L2 AXI Error 1 Address Register */
-
-
-/* =========================
- SEC Registers
- ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC Core Interface (SCI) Register Definitions
- ------------------------------------------------------------------------------------------------------------------------ */
-
-#define SEC_SCI_BASE 0xFFCA4400
-#define SEC_SCI_OFF 0x40
-#define SEC_CCTL 0x0 /* SEC Core Control Register n */
-#define SEC_CSTAT 0x4 /* SEC Core Status Register n */
-#define SEC_CPND 0x8 /* SEC Core Pending IRQ Register n */
-#define SEC_CACT 0xC /* SEC Core Active IRQ Register n */
-#define SEC_CPMSK 0x10 /* SEC Core IRQ Priority Mask Register n */
-#define SEC_CGMSK 0x14 /* SEC Core IRQ Group Mask Register n */
-#define SEC_CPLVL 0x18 /* SEC Core IRQ Priority Level Register n */
-#define SEC_CSID 0x1C /* SEC Core IRQ Source ID Register n */
-
-#define bfin_read_SEC_SCI(n, reg) bfin_read32(SEC_SCI_BASE + (n) * SEC_SCI_OFF + reg)
-#define bfin_write_SEC_SCI(n, reg, val) \
- bfin_write32(SEC_SCI_BASE + (n) * SEC_SCI_OFF + reg, val)
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC Fault Management Interface (SFI) Register Definitions
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_FCTL 0xFFCA4010 /* SEC Fault Control Register */
-#define SEC_FSTAT 0xFFCA4014 /* SEC Fault Status Register */
-#define SEC_FSID 0xFFCA4018 /* SEC Fault Source ID Register */
-#define SEC_FEND 0xFFCA401C /* SEC Fault End Register */
-#define SEC_FDLY 0xFFCA4020 /* SEC Fault Delay Register */
-#define SEC_FDLY_CUR 0xFFCA4024 /* SEC Fault Delay Current Register */
-#define SEC_FSRDLY 0xFFCA4028 /* SEC Fault System Reset Delay Register */
-#define SEC_FSRDLY_CUR 0xFFCA402C /* SEC Fault System Reset Delay Current Register */
-#define SEC_FCOPP 0xFFCA4030 /* SEC Fault COP Period Register */
-#define SEC_FCOPP_CUR 0xFFCA4034 /* SEC Fault COP Period Current Register */
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC Global Register Definitions
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_GCTL 0xFFCA4000 /* SEC Global Control Register */
-#define SEC_GSTAT 0xFFCA4004 /* SEC Global Status Register */
-#define SEC_RAISE 0xFFCA4008 /* SEC Global Raise Register */
-#define SEC_END 0xFFCA400C /* SEC Global End Register */
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC Source Interface (SSI) Register Definitions
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_SCTL0 0xFFCA4800 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL1 0xFFCA4808 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL2 0xFFCA4810 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL3 0xFFCA4818 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL4 0xFFCA4820 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL5 0xFFCA4828 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL6 0xFFCA4830 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL7 0xFFCA4838 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL8 0xFFCA4840 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL9 0xFFCA4848 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL10 0xFFCA4850 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL11 0xFFCA4858 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL12 0xFFCA4860 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL13 0xFFCA4868 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL14 0xFFCA4870 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL15 0xFFCA4878 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL16 0xFFCA4880 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL17 0xFFCA4888 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL18 0xFFCA4890 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL19 0xFFCA4898 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL20 0xFFCA48A0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL21 0xFFCA48A8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL22 0xFFCA48B0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL23 0xFFCA48B8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL24 0xFFCA48C0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL25 0xFFCA48C8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL26 0xFFCA48D0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL27 0xFFCA48D8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL28 0xFFCA48E0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL29 0xFFCA48E8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL30 0xFFCA48F0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL31 0xFFCA48F8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL32 0xFFCA4900 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL33 0xFFCA4908 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL34 0xFFCA4910 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL35 0xFFCA4918 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL36 0xFFCA4920 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL37 0xFFCA4928 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL38 0xFFCA4930 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL39 0xFFCA4938 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL40 0xFFCA4940 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL41 0xFFCA4948 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL42 0xFFCA4950 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL43 0xFFCA4958 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL44 0xFFCA4960 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL45 0xFFCA4968 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL46 0xFFCA4970 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL47 0xFFCA4978 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL48 0xFFCA4980 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL49 0xFFCA4988 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL50 0xFFCA4990 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL51 0xFFCA4998 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL52 0xFFCA49A0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL53 0xFFCA49A8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL54 0xFFCA49B0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL55 0xFFCA49B8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL56 0xFFCA49C0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL57 0xFFCA49C8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL58 0xFFCA49D0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL59 0xFFCA49D8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL60 0xFFCA49E0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL61 0xFFCA49E8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL62 0xFFCA49F0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL63 0xFFCA49F8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL64 0xFFCA4A00 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL65 0xFFCA4A08 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL66 0xFFCA4A10 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL67 0xFFCA4A18 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL68 0xFFCA4A20 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL69 0xFFCA4A28 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL70 0xFFCA4A30 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL71 0xFFCA4A38 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL72 0xFFCA4A40 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL73 0xFFCA4A48 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL74 0xFFCA4A50 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL75 0xFFCA4A58 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL76 0xFFCA4A60 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL77 0xFFCA4A68 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL78 0xFFCA4A70 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL79 0xFFCA4A78 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL80 0xFFCA4A80 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL81 0xFFCA4A88 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL82 0xFFCA4A90 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL83 0xFFCA4A98 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL84 0xFFCA4AA0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL85 0xFFCA4AA8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL86 0xFFCA4AB0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL87 0xFFCA4AB8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL88 0xFFCA4AC0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL89 0xFFCA4AC8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL90 0xFFCA4AD0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL91 0xFFCA4AD8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL92 0xFFCA4AE0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL93 0xFFCA4AE8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL94 0xFFCA4AF0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL95 0xFFCA4AF8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL96 0xFFCA4B00 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL97 0xFFCA4B08 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL98 0xFFCA4B10 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL99 0xFFCA4B18 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL100 0xFFCA4B20 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL101 0xFFCA4B28 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL102 0xFFCA4B30 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL103 0xFFCA4B38 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL104 0xFFCA4B40 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL105 0xFFCA4B48 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL106 0xFFCA4B50 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL107 0xFFCA4B58 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL108 0xFFCA4B60 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL109 0xFFCA4B68 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL110 0xFFCA4B70 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL111 0xFFCA4B78 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL112 0xFFCA4B80 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL113 0xFFCA4B88 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL114 0xFFCA4B90 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL115 0xFFCA4B98 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL116 0xFFCA4BA0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL117 0xFFCA4BA8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL118 0xFFCA4BB0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL119 0xFFCA4BB8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL120 0xFFCA4BC0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL121 0xFFCA4BC8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL122 0xFFCA4BD0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL123 0xFFCA4BD8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL124 0xFFCA4BE0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL125 0xFFCA4BE8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL126 0xFFCA4BF0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL127 0xFFCA4BF8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL128 0xFFCA4C00 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL129 0xFFCA4C08 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL130 0xFFCA4C10 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL131 0xFFCA4C18 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL132 0xFFCA4C20 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL133 0xFFCA4C28 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL134 0xFFCA4C30 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL135 0xFFCA4C38 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL136 0xFFCA4C40 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL137 0xFFCA4C48 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL138 0xFFCA4C50 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL139 0xFFCA4C58 /* SEC IRQ Source Control Register n */
-#define SEC_SSTAT0 0xFFCA4804 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT1 0xFFCA480C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT2 0xFFCA4814 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT3 0xFFCA481C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT4 0xFFCA4824 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT5 0xFFCA482C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT6 0xFFCA4834 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT7 0xFFCA483C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT8 0xFFCA4844 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT9 0xFFCA484C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT10 0xFFCA4854 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT11 0xFFCA485C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT12 0xFFCA4864 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT13 0xFFCA486C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT14 0xFFCA4874 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT15 0xFFCA487C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT16 0xFFCA4884 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT17 0xFFCA488C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT18 0xFFCA4894 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT19 0xFFCA489C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT20 0xFFCA48A4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT21 0xFFCA48AC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT22 0xFFCA48B4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT23 0xFFCA48BC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT24 0xFFCA48C4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT25 0xFFCA48CC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT26 0xFFCA48D4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT27 0xFFCA48DC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT28 0xFFCA48E4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT29 0xFFCA48EC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT30 0xFFCA48F4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT31 0xFFCA48FC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT32 0xFFCA4904 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT33 0xFFCA490C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT34 0xFFCA4914 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT35 0xFFCA491C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT36 0xFFCA4924 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT37 0xFFCA492C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT38 0xFFCA4934 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT39 0xFFCA493C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT40 0xFFCA4944 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT41 0xFFCA494C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT42 0xFFCA4954 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT43 0xFFCA495C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT44 0xFFCA4964 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT45 0xFFCA496C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT46 0xFFCA4974 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT47 0xFFCA497C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT48 0xFFCA4984 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT49 0xFFCA498C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT50 0xFFCA4994 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT51 0xFFCA499C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT52 0xFFCA49A4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT53 0xFFCA49AC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT54 0xFFCA49B4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT55 0xFFCA49BC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT56 0xFFCA49C4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT57 0xFFCA49CC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT58 0xFFCA49D4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT59 0xFFCA49DC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT60 0xFFCA49E4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT61 0xFFCA49EC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT62 0xFFCA49F4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT63 0xFFCA49FC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT64 0xFFCA4A04 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT65 0xFFCA4A0C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT66 0xFFCA4A14 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT67 0xFFCA4A1C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT68 0xFFCA4A24 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT69 0xFFCA4A2C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT70 0xFFCA4A34 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT71 0xFFCA4A3C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT72 0xFFCA4A44 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT73 0xFFCA4A4C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT74 0xFFCA4A54 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT75 0xFFCA4A5C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT76 0xFFCA4A64 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT77 0xFFCA4A6C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT78 0xFFCA4A74 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT79 0xFFCA4A7C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT80 0xFFCA4A84 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT81 0xFFCA4A8C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT82 0xFFCA4A94 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT83 0xFFCA4A9C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT84 0xFFCA4AA4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT85 0xFFCA4AAC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT86 0xFFCA4AB4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT87 0xFFCA4ABC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT88 0xFFCA4AC4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT89 0xFFCA4ACC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT90 0xFFCA4AD4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT91 0xFFCA4ADC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT92 0xFFCA4AE4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT93 0xFFCA4AEC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT94 0xFFCA4AF4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT95 0xFFCA4AFC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT96 0xFFCA4B04 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT97 0xFFCA4B0C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT98 0xFFCA4B14 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT99 0xFFCA4B1C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT100 0xFFCA4B24 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT101 0xFFCA4B2C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT102 0xFFCA4B34 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT103 0xFFCA4B3C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT104 0xFFCA4B44 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT105 0xFFCA4B4C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT106 0xFFCA4B54 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT107 0xFFCA4B5C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT108 0xFFCA4B64 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT109 0xFFCA4B6C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT110 0xFFCA4B74 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT111 0xFFCA4B7C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT112 0xFFCA4B84 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT113 0xFFCA4B8C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT114 0xFFCA4B94 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT115 0xFFCA4B9C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT116 0xFFCA4BA4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT117 0xFFCA4BAC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT118 0xFFCA4BB4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT119 0xFFCA4BBC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT120 0xFFCA4BC4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT121 0xFFCA4BCC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT122 0xFFCA4BD4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT123 0xFFCA4BDC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT124 0xFFCA4BE4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT125 0xFFCA4BEC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT126 0xFFCA4BF4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT127 0xFFCA4BFC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT128 0xFFCA4C04 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT129 0xFFCA4C0C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT130 0xFFCA4C14 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT131 0xFFCA4C1C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT132 0xFFCA4C24 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT133 0xFFCA4C2C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT134 0xFFCA4C34 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT135 0xFFCA4C3C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT136 0xFFCA4C44 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT137 0xFFCA4C4C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT138 0xFFCA4C54 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT139 0xFFCA4C5C /* SEC IRQ Source Status Register n */
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_CCTL Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_CCTL_LOCK 0x80000000 /* LOCK: Lock */
-#define SEC_CCTL_NMI_EN 0x00010000 /* NMIEN: Enable */
-#define SEC_CCTL_WAITIDLE 0x00001000 /* WFI: Wait for Idle */
-#define SEC_CCTL_RESET 0x00000002 /* RESET: Reset */
-#define SEC_CCTL_EN 0x00000001 /* EN: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_CSTAT Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_CSTAT_NMI 0x00010000 /* NMI Status */
-#define SEC_CSTAT_WAITING 0x00001000 /* WFI: Waiting */
-#define SEC_CSTAT_VALID_SID 0x00000400 /* SIDV: Valid */
-#define SEC_CSTAT_VALID_ACT 0x00000200 /* ACTV: Valid */
-#define SEC_CSTAT_VALID_PND 0x00000100 /* PNDV: Valid */
-#define SEC_CSTAT_ERRC 0x00000030 /* Error Cause */
-#define SEC_CSTAT_ACKERR 0x00000010 /* ERRC: Acknowledge Error */
-#define SEC_CSTAT_ERR 0x00000002 /* ERR: Error Occurred */
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_CPND Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_CPND_PRIO 0x0000FF00 /* Highest Pending IRQ Priority */
-#define SEC_CPND_SID 0x000000FF /* Highest Pending IRQ Source ID */
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_CACT Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_CACT_PRIO 0x0000FF00 /* Highest Active IRQ Priority */
-#define SEC_CACT_SID 0x000000FF /* Highest Active IRQ Source ID */
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_CPMSK Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_CPMSK_LOCK 0x80000000 /* LOCK: Lock */
-#define SEC_CPMSK_PRIO 0x000000FF /* IRQ Priority Mask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_CGMSK Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_CGMSK_LOCK 0x80000000 /* LOCK: Lock */
-#define SEC_CGMSK_MASK 0x00000100 /* UGRP: Mask Ungrouped Sources */
-#define SEC_CGMSK_GRP 0x0000000F /* Grouped Mask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_CPLVL Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_CPLVL_LOCK 0x80000000 /* LOCK: Lock */
-#define SEC_CPLVL_PLVL 0x00000007 /* Priority Levels */
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_CSID Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_CSID_SID 0x000000FF /* Source ID */
-
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_FCTL Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_FCTL_LOCK 0x80000000 /* LOCK: Lock */
-#define SEC_FCTL_FLTPND_MODE 0x00002000 /* TES: Fault Pending Mode */
-#define SEC_FCTL_COP_MODE 0x00001000 /* CMS: COP Mode */
-#define SEC_FCTL_FLTIN_EN 0x00000080 /* FIEN: Enable */
-#define SEC_FCTL_SYSRST_EN 0x00000040 /* SREN: Enable */
-#define SEC_FCTL_TRGOUT_EN 0x00000020 /* TOEN: Enable */
-#define SEC_FCTL_FLTOUT_EN 0x00000010 /* FOEN: Enable */
-#define SEC_FCTL_RESET 0x00000002 /* RESET: Reset */
-#define SEC_FCTL_EN 0x00000001 /* EN: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_FSTAT Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_FSTAT_NXTFLT 0x00000400 /* NPND: Pending */
-#define SEC_FSTAT_FLTACT 0x00000200 /* ACT: Active Fault */
-#define SEC_FSTAT_FLTPND 0x00000100 /* PND: Pending */
-#define SEC_FSTAT_ERRC 0x00000030 /* Error Cause */
-#define SEC_FSTAT_ENDERR 0x00000020 /* ERRC: End Error */
-#define SEC_FSTAT_ERR 0x00000002 /* ERR: Error Occurred */
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_FSID Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_FSID_SRC_EXTFLT 0x00010000 /* FEXT: Fault External */
-#define SEC_FSID_SID 0x000000FF /* Source ID */
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_FEND Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_FEND_END_EXTFLT 0x00010000 /* FEXT: Fault External */
-#define SEC_FEND_SID 0x000000FF /* Source ID */
-
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_GCTL Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_GCTL_LOCK 0x80000000 /* Lock */
-#define SEC_GCTL_RESET 0x00000002 /* Reset */
-#define SEC_GCTL_EN 0x00000001 /* Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_GSTAT Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_GSTAT_LWERR 0x80000000 /* LWERR: Error Occurred */
-#define SEC_GSTAT_ADRERR 0x40000000 /* ADRERR: Error Occurred */
-#define SEC_GSTAT_SID 0x00FF0000 /* Source ID for SSI Error */
-#define SEC_GSTAT_SCI 0x00000F00 /* SCI ID for SCI Error */
-#define SEC_GSTAT_ERRC 0x00000030 /* Error Cause */
-#define SEC_GSTAT_SCIERR 0x00000010 /* ERRC: SCI Error */
-#define SEC_GSTAT_SSIERR 0x00000020 /* ERRC: SSI Error */
-#define SEC_GSTAT_ERR 0x00000002 /* ERR: Error Occurred */
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_RAISE Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_RAISE_SID 0x000000FF /* Source ID IRQ Set to Pending */
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_END Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_END_SID 0x000000FF /* Source ID IRQ to End */
-
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_SCTL Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_SCTL_LOCK 0x80000000 /* Lock */
-#define SEC_SCTL_CTG 0x0F000000 /* Core Target Select */
-#define SEC_SCTL_GRP 0x000F0000 /* Group Select */
-#define SEC_SCTL_PRIO 0x0000FF00 /* Priority Level Select */
-#define SEC_SCTL_ERR_EN 0x00000010 /* ERREN: Enable */
-#define SEC_SCTL_EDGE 0x00000008 /* ES: Edge Sensitive */
-#define SEC_SCTL_SRC_EN 0x00000004 /* SEN: Enable */
-#define SEC_SCTL_FAULT_EN 0x00000002 /* FEN: Enable */
-#define SEC_SCTL_INT_EN 0x00000001 /* IEN: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_SSTAT Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_SSTAT_CHID 0x00FF0000 /* Channel ID */
-#define SEC_SSTAT_ACTIVE_SRC 0x00000200 /* ACT: Active Source */
-#define SEC_SSTAT_PENDING 0x00000100 /* PND: Pending */
-#define SEC_SSTAT_ERRC 0x00000030 /* Error Cause */
-#define SEC_SSTAT_ENDERR 0x00000020 /* ERRC: End Error */
-#define SEC_SSTAT_ERR 0x00000002 /* Error */
-
-
-/* =========================
- RCU Registers
- ========================= */
-
-/* =========================
- RCU0
- ========================= */
-#define RCU0_CTL 0xFFCA6000 /* RCU0 Control Register */
-#define RCU0_STAT 0xFFCA6004 /* RCU0 Status Register */
-#define RCU0_CRCTL 0xFFCA6008 /* RCU0 Core Reset Control Register */
-#define RCU0_CRSTAT 0xFFCA600C /* RCU0 Core Reset Status Register */
-#define RCU0_SIDIS 0xFFCA6010 /* RCU0 System Interface Disable Register */
-#define RCU0_SISTAT 0xFFCA6014 /* RCU0 System Interface Status Register */
-#define RCU0_SVECT_LCK 0xFFCA6018 /* RCU0 SVECT Lock Register */
-#define RCU0_BCODE 0xFFCA601C /* RCU0 Boot Code Register */
-#define RCU0_SVECT0 0xFFCA6020 /* RCU0 Software Vector Register n */
-#define RCU0_SVECT1 0xFFCA6024 /* RCU0 Software Vector Register n */
-
-
-/* =========================
- CGU0
- ========================= */
-#define CGU0_CTL 0xFFCA8000 /* CGU0 Control Register */
-#define CGU0_STAT 0xFFCA8004 /* CGU0 Status Register */
-#define CGU0_DIV 0xFFCA8008 /* CGU0 Divisor Register */
-#define CGU0_CLKOUTSEL 0xFFCA800C /* CGU0 CLKOUT Select Register */
-
-
-/* =========================
- DPM Registers
- ========================= */
-
-/* =========================
- DPM0
- ========================= */
-#define DPM0_CTL 0xFFCA9000 /* DPM0 Control Register */
-#define DPM0_STAT 0xFFCA9004 /* DPM0 Status Register */
-#define DPM0_CCBF_DIS 0xFFCA9008 /* DPM0 Core Clock Buffer Disable Register */
-#define DPM0_CCBF_EN 0xFFCA900C /* DPM0 Core Clock Buffer Enable Register */
-#define DPM0_CCBF_STAT 0xFFCA9010 /* DPM0 Core Clock Buffer Status Register */
-#define DPM0_CCBF_STAT_STKY 0xFFCA9014 /* DPM0 Core Clock Buffer Status Sticky Register */
-#define DPM0_SCBF_DIS 0xFFCA9018 /* DPM0 System Clock Buffer Disable Register */
-#define DPM0_WAKE_EN 0xFFCA901C /* DPM0 Wakeup Enable Register */
-#define DPM0_WAKE_POL 0xFFCA9020 /* DPM0 Wakeup Polarity Register */
-#define DPM0_WAKE_STAT 0xFFCA9024 /* DPM0 Wakeup Status Register */
-#define DPM0_HIB_DIS 0xFFCA9028 /* DPM0 Hibernate Disable Register */
-#define DPM0_PGCNTR 0xFFCA902C /* DPM0 Power Good Counter Register */
-#define DPM0_RESTORE0 0xFFCA9030 /* DPM0 Restore Register */
-#define DPM0_RESTORE1 0xFFCA9034 /* DPM0 Restore Register */
-#define DPM0_RESTORE2 0xFFCA9038 /* DPM0 Restore Register */
-#define DPM0_RESTORE3 0xFFCA903C /* DPM0 Restore Register */
-#define DPM0_RESTORE4 0xFFCA9040 /* DPM0 Restore Register */
-#define DPM0_RESTORE5 0xFFCA9044 /* DPM0 Restore Register */
-#define DPM0_RESTORE6 0xFFCA9048 /* DPM0 Restore Register */
-#define DPM0_RESTORE7 0xFFCA904C /* DPM0 Restore Register */
-#define DPM0_RESTORE8 0xFFCA9050 /* DPM0 Restore Register */
-#define DPM0_RESTORE9 0xFFCA9054 /* DPM0 Restore Register */
-#define DPM0_RESTORE10 0xFFCA9058 /* DPM0 Restore Register */
-#define DPM0_RESTORE11 0xFFCA905C /* DPM0 Restore Register */
-#define DPM0_RESTORE12 0xFFCA9060 /* DPM0 Restore Register */
-#define DPM0_RESTORE13 0xFFCA9064 /* DPM0 Restore Register */
-#define DPM0_RESTORE14 0xFFCA9068 /* DPM0 Restore Register */
-#define DPM0_RESTORE15 0xFFCA906C /* DPM0 Restore Register */
-
-
-/* =========================
- DBG Registers
- ========================= */
-
-/* USB register */
-#define USB_FADDR 0xFFCC1000 /* USB Device Address in Peripheral Mode */
-#define USB_POWER 0xFFCC1001 /* USB Power and Device Control */
-#define USB_INTRTX 0xFFCC1002 /* USB Transmit Interrupt */
-#define USB_INTRRX 0xFFCC1004 /* USB Receive Interrupts */
-#define USB_INTRTXE 0xFFCC1006 /* USB Transmit Interrupt Enable */
-#define USB_INTRRXE 0xFFCC1008 /* USB Receive Interrupt Enable */
-#define USB_INTRUSB 0xFFCC100A /* USB USB Interrupts */
-#define USB_INTRUSBE 0xFFCC100B /* USB USB Interrupt Enable */
-#define USB_FRAME 0xFFCC100C /* USB Frame Number */
-#define USB_INDEX 0xFFCC100E /* USB Index */
-#define USB_TESTMODE 0xFFCC100F /* USB Testmodes */
-#define USB_EPI_TXMAXP0 0xFFCC1010 /* USB Transmit Maximum Packet Length */
-#define USB_EP_NI0_TXMAXP 0xFFCC1010
-#define USB_EP0I_CSR0_H 0xFFCC1012 /* USB Config and Status EP0 */
-#define USB_EPI_TXCSR0_H 0xFFCC1012 /* USB Transmit Configuration and Status */
-#define USB_EP0I_CSR0_P 0xFFCC1012 /* USB Config and Status EP0 */
-#define USB_EPI_TXCSR0_P 0xFFCC1012 /* USB Transmit Configuration and Status */
-#define USB_EPI_RXMAXP0 0xFFCC1014 /* USB Receive Maximum Packet Length */
-#define USB_EPI_RXCSR0_H 0xFFCC1016 /* USB Receive Configuration and Status Register */
-#define USB_EPI_RXCSR0_P 0xFFCC1016 /* USB Receive Configuration and Status Register */
-#define USB_EP0I_CNT0 0xFFCC1018 /* USB Number of Received Bytes for Endpoint 0 */
-#define USB_EPI_RXCNT0 0xFFCC1018 /* USB Number of Byte Received */
-#define USB_EP0I_TYPE0 0xFFCC101A /* USB Speed for Endpoint 0 */
-#define USB_EPI_TXTYPE0 0xFFCC101A /* USB Transmit Type */
-#define USB_EP0I_NAKLIMIT0 0xFFCC101B /* USB NAK Response Timeout for Endpoint 0 */
-#define USB_EPI_TXINTERVAL0 0xFFCC101B /* USB Transmit Polling Interval */
-#define USB_EPI_RXTYPE0 0xFFCC101C /* USB Receive Type */
-#define USB_EPI_RXINTERVAL0 0xFFCC101D /* USB Receive Polling Interval */
-#define USB_EP0I_CFGDATA0 0xFFCC101F /* USB Configuration Information */
-#define USB_FIFOB0 0xFFCC1020 /* USB FIFO Data */
-#define USB_FIFOB1 0xFFCC1024 /* USB FIFO Data */
-#define USB_FIFOB2 0xFFCC1028 /* USB FIFO Data */
-#define USB_FIFOB3 0xFFCC102C /* USB FIFO Data */
-#define USB_FIFOB4 0xFFCC1030 /* USB FIFO Data */
-#define USB_FIFOB5 0xFFCC1034 /* USB FIFO Data */
-#define USB_FIFOB6 0xFFCC1038 /* USB FIFO Data */
-#define USB_FIFOB7 0xFFCC103C /* USB FIFO Data */
-#define USB_FIFOB8 0xFFCC1040 /* USB FIFO Data */
-#define USB_FIFOB9 0xFFCC1044 /* USB FIFO Data */
-#define USB_FIFOB10 0xFFCC1048 /* USB FIFO Data */
-#define USB_FIFOB11 0xFFCC104C /* USB FIFO Data */
-#define USB_FIFOH0 0xFFCC1020 /* USB FIFO Data */
-#define USB_FIFOH1 0xFFCC1024 /* USB FIFO Data */
-#define USB_FIFOH2 0xFFCC1028 /* USB FIFO Data */
-#define USB_FIFOH3 0xFFCC102C /* USB FIFO Data */
-#define USB_FIFOH4 0xFFCC1030 /* USB FIFO Data */
-#define USB_FIFOH5 0xFFCC1034 /* USB FIFO Data */
-#define USB_FIFOH6 0xFFCC1038 /* USB FIFO Data */
-#define USB_FIFOH7 0xFFCC103C /* USB FIFO Data */
-#define USB_FIFOH8 0xFFCC1040 /* USB FIFO Data */
-#define USB_FIFOH9 0xFFCC1044 /* USB FIFO Data */
-#define USB_FIFOH10 0xFFCC1048 /* USB FIFO Data */
-#define USB_FIFOH11 0xFFCC104C /* USB FIFO Data */
-#define USB_FIFO0 0xFFCC1020 /* USB FIFO Data */
-#define USB_EP0_FIFO 0xFFCC1020
-#define USB_FIFO1 0xFFCC1024 /* USB FIFO Data */
-#define USB_FIFO2 0xFFCC1028 /* USB FIFO Data */
-#define USB_FIFO3 0xFFCC102C /* USB FIFO Data */
-#define USB_FIFO4 0xFFCC1030 /* USB FIFO Data */
-#define USB_FIFO5 0xFFCC1034 /* USB FIFO Data */
-#define USB_FIFO6 0xFFCC1038 /* USB FIFO Data */
-#define USB_FIFO7 0xFFCC103C /* USB FIFO Data */
-#define USB_FIFO8 0xFFCC1040 /* USB FIFO Data */
-#define USB_FIFO9 0xFFCC1044 /* USB FIFO Data */
-#define USB_FIFO10 0xFFCC1048 /* USB FIFO Data */
-#define USB_FIFO11 0xFFCC104C /* USB FIFO Data */
-#define USB_OTG_DEV_CTL 0xFFCC1060 /* USB Device Control */
-#define USB_TXFIFOSZ 0xFFCC1062 /* USB Transmit FIFO Size */
-#define USB_RXFIFOSZ 0xFFCC1063 /* USB Receive FIFO Size */
-#define USB_TXFIFOADDR 0xFFCC1064 /* USB Transmit FIFO Address */
-#define USB_RXFIFOADDR 0xFFCC1066 /* USB Receive FIFO Address */
-#define USB_VENDSTAT 0xFFCC1068 /* USB Vendor Status */
-#define USB_HWVERS 0xFFCC106C /* USB Hardware Version */
-#define USB_EPINFO 0xFFCC1078 /* USB Endpoint Info */
-#define USB_RAMINFO 0xFFCC1079 /* USB Ram Information */
-#define USB_LINKINFO 0xFFCC107A /* USB Programmable Delay Values */
-#define USB_VPLEN 0xFFCC107B /* USB VBus Pulse Duration */
-#define USB_HS_EOF1 0xFFCC107C /* USB High Speed End of Frame Remaining */
-#define USB_FS_EOF1 0xFFCC107D /* USB Full Speed End of Frame Remaining */
-#define USB_LS_EOF1 0xFFCC107E /* USB Low Speed End of Frame Remaining */
-#define USB_SOFT_RST 0xFFCC107F /* USB Software Reset */
-#define USB_TXFUNCADDR0 0xFFCC1080 /* USB Transmit Function Address */
-#define USB_TXFUNCADDR1 0xFFCC1088 /* USB Transmit Function Address */
-#define USB_TXFUNCADDR2 0xFFCC1090 /* USB Transmit Function Address */
-#define USB_TXFUNCADDR3 0xFFCC1098 /* USB Transmit Function Address */
-#define USB_TXFUNCADDR4 0xFFCC10A0 /* USB Transmit Function Address */
-#define USB_TXFUNCADDR5 0xFFCC10A8 /* USB Transmit Function Address */
-#define USB_TXFUNCADDR6 0xFFCC10B0 /* USB Transmit Function Address */
-#define USB_TXFUNCADDR7 0xFFCC10B8 /* USB Transmit Function Address */
-#define USB_TXFUNCADDR8 0xFFCC10C0 /* USB Transmit Function Address */
-#define USB_TXFUNCADDR9 0xFFCC10C8 /* USB Transmit Function Address */
-#define USB_TXFUNCADDR10 0xFFCC10D0 /* USB Transmit Function Address */
-#define USB_TXFUNCADDR11 0xFFCC10D8 /* USB Transmit Function Address */
-#define USB_TXHUBADDR0 0xFFCC1082 /* USB Transmit Hub Address */
-#define USB_TXHUBADDR1 0xFFCC108A /* USB Transmit Hub Address */
-#define USB_TXHUBADDR2 0xFFCC1092 /* USB Transmit Hub Address */
-#define USB_TXHUBADDR3 0xFFCC109A /* USB Transmit Hub Address */
-#define USB_TXHUBADDR4 0xFFCC10A2 /* USB Transmit Hub Address */
-#define USB_TXHUBADDR5 0xFFCC10AA /* USB Transmit Hub Address */
-#define USB_TXHUBADDR6 0xFFCC10B2 /* USB Transmit Hub Address */
-#define USB_TXHUBADDR7 0xFFCC10BA /* USB Transmit Hub Address */
-#define USB_TXHUBADDR8 0xFFCC10C2 /* USB Transmit Hub Address */
-#define USB_TXHUBADDR9 0xFFCC10CA /* USB Transmit Hub Address */
-#define USB_TXHUBADDR10 0xFFCC10D2 /* USB Transmit Hub Address */
-#define USB_TXHUBADDR11 0xFFCC10DA /* USB Transmit Hub Address */
-#define USB_TXHUBPORT0 0xFFCC1083 /* USB Transmit Hub Port */
-#define USB_TXHUBPORT1 0xFFCC108B /* USB Transmit Hub Port */
-#define USB_TXHUBPORT2 0xFFCC1093 /* USB Transmit Hub Port */
-#define USB_TXHUBPORT3 0xFFCC109B /* USB Transmit Hub Port */
-#define USB_TXHUBPORT4 0xFFCC10A3 /* USB Transmit Hub Port */
-#define USB_TXHUBPORT5 0xFFCC10AB /* USB Transmit Hub Port */
-#define USB_TXHUBPORT6 0xFFCC10B3 /* USB Transmit Hub Port */
-#define USB_TXHUBPORT7 0xFFCC10BB /* USB Transmit Hub Port */
-#define USB_TXHUBPORT8 0xFFCC10C3 /* USB Transmit Hub Port */
-#define USB_TXHUBPORT9 0xFFCC10CB /* USB Transmit Hub Port */
-#define USB_TXHUBPORT10 0xFFCC10D3 /* USB Transmit Hub Port */
-#define USB_TXHUBPORT11 0xFFCC10DB /* USB Transmit Hub Port */
-#define USB_RXFUNCADDR0 0xFFCC1084 /* USB Receive Function Address */
-#define USB_RXFUNCADDR1 0xFFCC108C /* USB Receive Function Address */
-#define USB_RXFUNCADDR2 0xFFCC1094 /* USB Receive Function Address */
-#define USB_RXFUNCADDR3 0xFFCC109C /* USB Receive Function Address */
-#define USB_RXFUNCADDR4 0xFFCC10A4 /* USB Receive Function Address */
-#define USB_RXFUNCADDR5 0xFFCC10AC /* USB Receive Function Address */
-#define USB_RXFUNCADDR6 0xFFCC10B4 /* USB Receive Function Address */
-#define USB_RXFUNCADDR7 0xFFCC10BC /* USB Receive Function Address */
-#define USB_RXFUNCADDR8 0xFFCC10C4 /* USB Receive Function Address */
-#define USB_RXFUNCADDR9 0xFFCC10CC /* USB Receive Function Address */
-#define USB_RXFUNCADDR10 0xFFCC10D4 /* USB Receive Function Address */
-#define USB_RXFUNCADDR11 0xFFCC10DC /* USB Receive Function Address */
-#define USB_RXHUBADDR0 0xFFCC1086 /* USB Receive Hub Address */
-#define USB_RXHUBADDR1 0xFFCC108E /* USB Receive Hub Address */
-#define USB_RXHUBADDR2 0xFFCC1096 /* USB Receive Hub Address */
-#define USB_RXHUBADDR3 0xFFCC109E /* USB Receive Hub Address */
-#define USB_RXHUBADDR4 0xFFCC10A6 /* USB Receive Hub Address */
-#define USB_RXHUBADDR5 0xFFCC10AE /* USB Receive Hub Address */
-#define USB_RXHUBADDR6 0xFFCC10B6 /* USB Receive Hub Address */
-#define USB_RXHUBADDR7 0xFFCC10BE /* USB Receive Hub Address */
-#define USB_RXHUBADDR8 0xFFCC10C6 /* USB Receive Hub Address */
-#define USB_RXHUBADDR9 0xFFCC10CE /* USB Receive Hub Address */
-#define USB_RXHUBADDR10 0xFFCC10D6 /* USB Receive Hub Address */
-#define USB_RXHUBADDR11 0xFFCC10DE /* USB Receive Hub Address */
-#define USB_RXHUBPORT0 0xFFCC1087 /* USB Receive Hub Port */
-#define USB_RXHUBPORT1 0xFFCC108F /* USB Receive Hub Port */
-#define USB_RXHUBPORT2 0xFFCC1097 /* USB Receive Hub Port */
-#define USB_RXHUBPORT3 0xFFCC109F /* USB Receive Hub Port */
-#define USB_RXHUBPORT4 0xFFCC10A7 /* USB Receive Hub Port */
-#define USB_RXHUBPORT5 0xFFCC10AF /* USB Receive Hub Port */
-#define USB_RXHUBPORT6 0xFFCC10B7 /* USB Receive Hub Port */
-#define USB_RXHUBPORT7 0xFFCC10BF /* USB Receive Hub Port */
-#define USB_RXHUBPORT8 0xFFCC10C7 /* USB Receive Hub Port */
-#define USB_RXHUBPORT9 0xFFCC10CF /* USB Receive Hub Port */
-#define USB_RXHUBPORT10 0xFFCC10D7 /* USB Receive Hub Port */
-#define USB_RXHUBPORT11 0xFFCC10DF /* USB Receive Hub Port */
-#define USB_EP0_CSR0_H 0xFFCC1102 /* USB Config and Status EP0 */
-#define USB_EP0_CSR0_P 0xFFCC1102 /* USB Config and Status EP0 */
-#define USB_EP0_CNT0 0xFFCC1108 /* USB Number of Received Bytes for Endpoint 0 */
-#define USB_EP0_TYPE0 0xFFCC110A /* USB Speed for Endpoint 0 */
-#define USB_EP0_NAKLIMIT0 0xFFCC110B /* USB NAK Response Timeout for Endpoint 0 */
-#define USB_EP0_CFGDATA0 0xFFCC110F /* USB Configuration Information */
-#define USB_EP_TXMAXP0 0xFFCC1110 /* USB Transmit Maximum Packet Length */
-#define USB_EP_TXMAXP1 0xFFCC1120 /* USB Transmit Maximum Packet Length */
-#define USB_EP_TXMAXP2 0xFFCC1130 /* USB Transmit Maximum Packet Length */
-#define USB_EP_TXMAXP3 0xFFCC1140 /* USB Transmit Maximum Packet Length */
-#define USB_EP_TXMAXP4 0xFFCC1150 /* USB Transmit Maximum Packet Length */
-#define USB_EP_TXMAXP5 0xFFCC1160 /* USB Transmit Maximum Packet Length */
-#define USB_EP_TXMAXP6 0xFFCC1170 /* USB Transmit Maximum Packet Length */
-#define USB_EP_TXMAXP7 0xFFCC1180 /* USB Transmit Maximum Packet Length */
-#define USB_EP_TXMAXP8 0xFFCC1190 /* USB Transmit Maximum Packet Length */
-#define USB_EP_TXMAXP9 0xFFCC11A0 /* USB Transmit Maximum Packet Length */
-#define USB_EP_TXMAXP10 0xFFCC11B0 /* USB Transmit Maximum Packet Length */
-#define USB_EP_TXCSR0_H 0xFFCC1112 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR1_H 0xFFCC1122 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR2_H 0xFFCC1132 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR3_H 0xFFCC1142 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR4_H 0xFFCC1152 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR5_H 0xFFCC1162 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR6_H 0xFFCC1172 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR7_H 0xFFCC1182 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR8_H 0xFFCC1192 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR9_H 0xFFCC11A2 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR10_H 0xFFCC11B2 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR0_P 0xFFCC1112 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR1_P 0xFFCC1122 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR2_P 0xFFCC1132 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR3_P 0xFFCC1142 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR4_P 0xFFCC1152 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR5_P 0xFFCC1162 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR6_P 0xFFCC1172 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR7_P 0xFFCC1182 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR8_P 0xFFCC1192 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR9_P 0xFFCC11A2 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR10_P 0xFFCC11B2 /* USB Transmit Configuration and Status */
-#define USB_EP_RXMAXP0 0xFFCC1114 /* USB Receive Maximum Packet Length */
-#define USB_EP_RXMAXP1 0xFFCC1124 /* USB Receive Maximum Packet Length */
-#define USB_EP_RXMAXP2 0xFFCC1134 /* USB Receive Maximum Packet Length */
-#define USB_EP_RXMAXP3 0xFFCC1144 /* USB Receive Maximum Packet Length */
-#define USB_EP_RXMAXP4 0xFFCC1154 /* USB Receive Maximum Packet Length */
-#define USB_EP_RXMAXP5 0xFFCC1164 /* USB Receive Maximum Packet Length */
-#define USB_EP_RXMAXP6 0xFFCC1174 /* USB Receive Maximum Packet Length */
-#define USB_EP_RXMAXP7 0xFFCC1184 /* USB Receive Maximum Packet Length */
-#define USB_EP_RXMAXP8 0xFFCC1194 /* USB Receive Maximum Packet Length */
-#define USB_EP_RXMAXP9 0xFFCC11A4 /* USB Receive Maximum Packet Length */
-#define USB_EP_RXMAXP10 0xFFCC11B4 /* USB Receive Maximum Packet Length */
-#define USB_EP_RXCSR0_H 0xFFCC1116 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR1_H 0xFFCC1126 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR2_H 0xFFCC1136 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR3_H 0xFFCC1146 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR4_H 0xFFCC1156 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR5_H 0xFFCC1166 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR6_H 0xFFCC1176 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR7_H 0xFFCC1186 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR8_H 0xFFCC1196 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR9_H 0xFFCC11A6 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR10_H 0xFFCC11B6 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR0_P 0xFFCC1116 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR1_P 0xFFCC1126 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR2_P 0xFFCC1136 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR3_P 0xFFCC1146 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR4_P 0xFFCC1156 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR5_P 0xFFCC1166 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR6_P 0xFFCC1176 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR7_P 0xFFCC1186 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR8_P 0xFFCC1196 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR9_P 0xFFCC11A6 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR10_P 0xFFCC11B6 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCNT0 0xFFCC1118 /* USB Number of Byte Received */
-#define USB_EP_RXCNT1 0xFFCC1128 /* USB Number of Byte Received */
-#define USB_EP_RXCNT2 0xFFCC1138 /* USB Number of Byte Received */
-#define USB_EP_RXCNT3 0xFFCC1148 /* USB Number of Byte Received */
-#define USB_EP_RXCNT4 0xFFCC1158 /* USB Number of Byte Received */
-#define USB_EP_RXCNT5 0xFFCC1168 /* USB Number of Byte Received */
-#define USB_EP_RXCNT6 0xFFCC1178 /* USB Number of Byte Received */
-#define USB_EP_RXCNT7 0xFFCC1188 /* USB Number of Byte Received */
-#define USB_EP_RXCNT8 0xFFCC1198 /* USB Number of Byte Received */
-#define USB_EP_RXCNT9 0xFFCC11A8 /* USB Number of Byte Received */
-#define USB_EP_RXCNT10 0xFFCC11B8 /* USB Number of Byte Received */
-#define USB_EP_TXTYPE0 0xFFCC111A /* USB Transmit Type */
-#define USB_EP_TXTYPE1 0xFFCC112A /* USB Transmit Type */
-#define USB_EP_TXTYPE2 0xFFCC113A /* USB Transmit Type */
-#define USB_EP_TXTYPE3 0xFFCC114A /* USB Transmit Type */
-#define USB_EP_TXTYPE4 0xFFCC115A /* USB Transmit Type */
-#define USB_EP_TXTYPE5 0xFFCC116A /* USB Transmit Type */
-#define USB_EP_TXTYPE6 0xFFCC117A /* USB Transmit Type */
-#define USB_EP_TXTYPE7 0xFFCC118A /* USB Transmit Type */
-#define USB_EP_TXTYPE8 0xFFCC119A /* USB Transmit Type */
-#define USB_EP_TXTYPE9 0xFFCC11AA /* USB Transmit Type */
-#define USB_EP_TXTYPE10 0xFFCC11BA /* USB Transmit Type */
-#define USB_EP_TXINTERVAL0 0xFFCC111B /* USB Transmit Polling Interval */
-#define USB_EP_TXINTERVAL1 0xFFCC112B /* USB Transmit Polling Interval */
-#define USB_EP_TXINTERVAL2 0xFFCC113B /* USB Transmit Polling Interval */
-#define USB_EP_TXINTERVAL3 0xFFCC114B /* USB Transmit Polling Interval */
-#define USB_EP_TXINTERVAL4 0xFFCC115B /* USB Transmit Polling Interval */
-#define USB_EP_TXINTERVAL5 0xFFCC116B /* USB Transmit Polling Interval */
-#define USB_EP_TXINTERVAL6 0xFFCC117B /* USB Transmit Polling Interval */
-#define USB_EP_TXINTERVAL7 0xFFCC118B /* USB Transmit Polling Interval */
-#define USB_EP_TXINTERVAL8 0xFFCC119B /* USB Transmit Polling Interval */
-#define USB_EP_TXINTERVAL9 0xFFCC11AB /* USB Transmit Polling Interval */
-#define USB_EP_TXINTERVAL10 0xFFCC11BB /* USB Transmit Polling Interval */
-#define USB_EP_RXTYPE0 0xFFCC111C /* USB Receive Type */
-#define USB_EP_RXTYPE1 0xFFCC112C /* USB Receive Type */
-#define USB_EP_RXTYPE2 0xFFCC113C /* USB Receive Type */
-#define USB_EP_RXTYPE3 0xFFCC114C /* USB Receive Type */
-#define USB_EP_RXTYPE4 0xFFCC115C /* USB Receive Type */
-#define USB_EP_RXTYPE5 0xFFCC116C /* USB Receive Type */
-#define USB_EP_RXTYPE6 0xFFCC117C /* USB Receive Type */
-#define USB_EP_RXTYPE7 0xFFCC118C /* USB Receive Type */
-#define USB_EP_RXTYPE8 0xFFCC119C /* USB Receive Type */
-#define USB_EP_RXTYPE9 0xFFCC11AC /* USB Receive Type */
-#define USB_EP_RXTYPE10 0xFFCC11BC /* USB Receive Type */
-#define USB_EP_RXINTERVAL0 0xFFCC111D /* USB Receive Polling Interval */
-#define USB_EP_RXINTERVAL1 0xFFCC112D /* USB Receive Polling Interval */
-#define USB_EP_RXINTERVAL2 0xFFCC113D /* USB Receive Polling Interval */
-#define USB_EP_RXINTERVAL3 0xFFCC114D /* USB Receive Polling Interval */
-#define USB_EP_RXINTERVAL4 0xFFCC115D /* USB Receive Polling Interval */
-#define USB_EP_RXINTERVAL5 0xFFCC116D /* USB Receive Polling Interval */
-#define USB_EP_RXINTERVAL6 0xFFCC117D /* USB Receive Polling Interval */
-#define USB_EP_RXINTERVAL7 0xFFCC118D /* USB Receive Polling Interval */
-#define USB_EP_RXINTERVAL8 0xFFCC119D /* USB Receive Polling Interval */
-#define USB_EP_RXINTERVAL9 0xFFCC11AD /* USB Receive Polling Interval */
-#define USB_EP_RXINTERVAL10 0xFFCC11BD /* USB Receive Polling Interval */
-#define USB_DMA_IRQ 0xFFCC1200 /* USB Interrupt Register */
-#define USB_DMA_CTL0 0xFFCC1204 /* USB DMA Control */
-#define USB_DMA_CTL1 0xFFCC1214 /* USB DMA Control */
-#define USB_DMA_CTL2 0xFFCC1224 /* USB DMA Control */
-#define USB_DMA_CTL3 0xFFCC1234 /* USB DMA Control */
-#define USB_DMA_CTL4 0xFFCC1244 /* USB DMA Control */
-#define USB_DMA_CTL5 0xFFCC1254 /* USB DMA Control */
-#define USB_DMA_CTL6 0xFFCC1264 /* USB DMA Control */
-#define USB_DMA_CTL7 0xFFCC1274 /* USB DMA Control */
-#define USB_DMA_ADDR0 0xFFCC1208 /* USB DMA Address */
-#define USB_DMA_ADDR1 0xFFCC1218 /* USB DMA Address */
-#define USB_DMA_ADDR2 0xFFCC1228 /* USB DMA Address */
-#define USB_DMA_ADDR3 0xFFCC1238 /* USB DMA Address */
-#define USB_DMA_ADDR4 0xFFCC1248 /* USB DMA Address */
-#define USB_DMA_ADDR5 0xFFCC1258 /* USB DMA Address */
-#define USB_DMA_ADDR6 0xFFCC1268 /* USB DMA Address */
-#define USB_DMA_ADDR7 0xFFCC1278 /* USB DMA Address */
-#define USB_DMA_CNT0 0xFFCC120C /* USB DMA Count */
-#define USB_DMA_CNT1 0xFFCC121C /* USB DMA Count */
-#define USB_DMA_CNT2 0xFFCC122C /* USB DMA Count */
-#define USB_DMA_CNT3 0xFFCC123C /* USB DMA Count */
-#define USB_DMA_CNT4 0xFFCC124C /* USB DMA Count */
-#define USB_DMA_CNT5 0xFFCC125C /* USB DMA Count */
-#define USB_DMA_CNT6 0xFFCC126C /* USB DMA Count */
-#define USB_DMA_CNT7 0xFFCC127C /* USB DMA Count */
-#define USB_RQPKTCNT0 0xFFCC1300 /* USB Request Packet Count */
-#define USB_RQPKTCNT1 0xFFCC1304 /* USB Request Packet Count */
-#define USB_RQPKTCNT2 0xFFCC1308 /* USB Request Packet Count */
-#define USB_RQPKTCNT3 0xFFCC130C /* USB Request Packet Count */
-#define USB_RQPKTCNT4 0xFFCC1310 /* USB Request Packet Count */
-#define USB_RQPKTCNT5 0xFFCC1314 /* USB Request Packet Count */
-#define USB_RQPKTCNT6 0xFFCC1318 /* USB Request Packet Count */
-#define USB_RQPKTCNT7 0xFFCC131C /* USB Request Packet Count */
-#define USB_RQPKTCNT8 0xFFCC1320 /* USB Request Packet Count */
-#define USB_RQPKTCNT9 0xFFCC1324 /* USB Request Packet Count */
-#define USB_RQPKTCNT10 0xFFCC1328 /* USB Request Packet Count */
-#define USB_CT_UCH 0xFFCC1344 /* USB Chirp Timeout */
-#define USB_CT_HHSRTN 0xFFCC1346 /* USB High Speed Resume Return to Normal */
-#define USB_CT_HSBT 0xFFCC1348 /* USB High Speed Timeout */
-#define USB_LPM_ATTR 0xFFCC1360 /* USB LPM Attribute */
-#define USB_LPM_CTL 0xFFCC1362 /* USB LPM Control */
-#define USB_LPM_IEN 0xFFCC1363 /* USB LPM Interrupt Enable */
-#define USB_LPM_IRQ 0xFFCC1364 /* USB LPM Interrupt */
-#define USB_LPM_FADDR 0xFFCC1365 /* USB LPM Function Address */
-#define USB_VBUS_CTL 0xFFCC1380 /* USB VBus Control */
-#define USB_BAT_CHG 0xFFCC1381 /* USB Battery Charging */
-#define USB_PHY_CTL 0xFFCC1394 /* USB PHY Control */
-#define USB_TESTCTL 0xFFCC1397 /* USB Test Control */
-#define USB_PLL_OSC 0xFFCC1398 /* USB PLL and Oscillator Control */
-
-
-
-/* =========================
- CHIPID
- ========================= */
-
-#define CHIPID 0xffc00014
-/* CHIPID Masks */
-#define CHIPID_VERSION 0xF0000000
-#define CHIPID_FAMILY 0x0FFFF000
-#define CHIPID_MANUFACTURE 0x00000FFE
-
-
-#endif /* _DEF_BF60X_H */
+++ /dev/null
-/* mach/dma.h - arch-specific DMA defines
- *
- * Copyright 2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_DMA_H_
-#define _MACH_DMA_H_
-
-#define CH_SPORT0_TX 0
-#define CH_SPORT0_RX 1
-#define CH_SPORT1_TX 2
-#define CH_SPORT1_RX 3
-#define CH_SPORT2_TX 4
-#define CH_SPORT2_RX 5
-#define CH_SPI0_TX 6
-#define CH_SPI0_RX 7
-#define CH_SPI1_TX 8
-#define CH_SPI1_RX 9
-#define CH_RSI 10
-#define CH_SDU 11
-#define CH_LP0 13
-#define CH_LP1 14
-#define CH_LP2 15
-#define CH_LP3 16
-#define CH_UART0_TX 17
-#define CH_UART0_RX 18
-#define CH_UART1_TX 19
-#define CH_UART1_RX 20
-#define CH_MEM_STREAM0_SRC_CRC0 21
-#define CH_MEM_STREAM0_SRC CH_MEM_STREAM0_SRC_CRC0
-#define CH_MEM_STREAM0_DEST_CRC0 22
-#define CH_MEM_STREAM0_DEST CH_MEM_STREAM0_DEST_CRC0
-#define CH_MEM_STREAM1_SRC_CRC1 23
-#define CH_MEM_STREAM1_SRC CH_MEM_STREAM1_SRC_CRC1
-#define CH_MEM_STREAM1_DEST_CRC1 24
-#define CH_MEM_STREAM1_DEST CH_MEM_STREAM1_DEST_CRC1
-#define CH_MEM_STREAM2_SRC 25
-#define CH_MEM_STREAM2_DEST 26
-#define CH_MEM_STREAM3_SRC 27
-#define CH_MEM_STREAM3_DEST 28
-#define CH_EPPI0_CH0 29
-#define CH_EPPI0_CH1 30
-#define CH_EPPI1_CH0 31
-#define CH_EPPI1_CH1 32
-#define CH_EPPI2_CH0 33
-#define CH_EPPI2_CH1 34
-#define CH_PIXC_CH0 35
-#define CH_PIXC_CH1 36
-#define CH_PIXC_CH2 37
-#define CH_PVP_CPDOB 38
-#define CH_PVP_CPDOC 39
-#define CH_PVP_CPSTAT 40
-#define CH_PVP_CPCI 41
-#define CH_PVP_MPDO 42
-#define CH_PVP_MPDI 43
-#define CH_PVP_MPSTAT 44
-#define CH_PVP_MPCI 45
-#define CH_PVP_CPDOA 46
-
-#define MAX_DMA_CHANNELS 47
-#define MAX_DMA_SUSPEND_CHANNELS 0
-#define DMA_MMR_SIZE_32
-
-#define bfin_read_MDMA_S0_CONFIG bfin_read_MDMA0_SRC_CRC0_CONFIG
-#define bfin_write_MDMA_S0_CONFIG bfin_write_MDMA0_SRC_CRC0_CONFIG
-#define bfin_read_MDMA_S0_IRQ_STATUS bfin_read_MDMA0_SRC_CRC0_IRQ_STATUS
-#define bfin_write_MDMA_S0_IRQ_STATUS bfin_write_MDMA0_SRC_CRC0_IRQ_STATUS
-#define bfin_write_MDMA_S0_START_ADDR bfin_write_MDMA0_SRC_CRC0_START_ADDR
-#define bfin_write_MDMA_S0_X_COUNT bfin_write_MDMA0_SRC_CRC0_X_COUNT
-#define bfin_write_MDMA_S0_X_MODIFY bfin_write_MDMA0_SRC_CRC0_X_MODIFY
-#define bfin_write_MDMA_S0_Y_COUNT bfin_write_MDMA0_SRC_CRC0_Y_COUNT
-#define bfin_write_MDMA_S0_Y_MODIFY bfin_write_MDMA0_SRC_CRC0_Y_MODIFY
-#define bfin_read_MDMA_D0_CONFIG bfin_read_MDMA0_DEST_CRC0_CONFIG
-#define bfin_write_MDMA_D0_CONFIG bfin_write_MDMA0_DEST_CRC0_CONFIG
-#define bfin_read_MDMA_D0_IRQ_STATUS bfin_read_MDMA0_DEST_CRC0_IRQ_STATUS
-#define bfin_write_MDMA_D0_IRQ_STATUS bfin_write_MDMA0_DEST_CRC0_IRQ_STATUS
-#define bfin_write_MDMA_D0_START_ADDR bfin_write_MDMA0_DEST_CRC0_START_ADDR
-#define bfin_write_MDMA_D0_X_COUNT bfin_write_MDMA0_DEST_CRC0_X_COUNT
-#define bfin_write_MDMA_D0_X_MODIFY bfin_write_MDMA0_DEST_CRC0_X_MODIFY
-#define bfin_write_MDMA_D0_Y_COUNT bfin_write_MDMA0_DEST_CRC0_Y_COUNT
-#define bfin_write_MDMA_D0_Y_MODIFY bfin_write_MDMA0_DEST_CRC0_Y_MODIFY
-
-#define bfin_read_MDMA_S1_CONFIG bfin_read_MDMA1_SRC_CRC1_CONFIG
-#define bfin_write_MDMA_S1_CONFIG bfin_write_MDMA1_SRC_CRC1_CONFIG
-#define bfin_read_MDMA_D1_CONFIG bfin_read_MDMA1_DEST_CRC1_CONFIG
-#define bfin_write_MDMA_D1_CONFIG bfin_write_MDMA1_DEST_CRC1_CONFIG
-#define bfin_read_MDMA_D1_IRQ_STATUS bfin_read_MDMA1_DEST_CRC1_IRQ_STATUS
-#define bfin_write_MDMA_D1_IRQ_STATUS bfin_write_MDMA1_DEST_CRC1_IRQ_STATUS
-
-#define bfin_read_MDMA_S3_CONFIG bfin_read_MDMA3_SRC_CONFIG
-#define bfin_write_MDMA_S3_CONFIG bfin_write_MDMA3_SRC_CONFIG
-#define bfin_read_MDMA_S3_IRQ_STATUS bfin_read_MDMA3_SRC_IRQ_STATUS
-#define bfin_write_MDMA_S3_IRQ_STATUS bfin_write_MDMA3_SRC_IRQ_STATUS
-#define bfin_write_MDMA_S3_START_ADDR bfin_write_MDMA3_SRC_START_ADDR
-#define bfin_write_MDMA_S3_X_COUNT bfin_write_MDMA3_SRC_X_COUNT
-#define bfin_write_MDMA_S3_X_MODIFY bfin_write_MDMA3_SRC_X_MODIFY
-#define bfin_write_MDMA_S3_Y_COUNT bfin_write_MDMA3_SRC_Y_COUNT
-#define bfin_write_MDMA_S3_Y_MODIFY bfin_write_MDMA3_SRC_Y_MODIFY
-#define bfin_read_MDMA_D3_CONFIG bfin_read_MDMA3_DEST_CONFIG
-#define bfin_write_MDMA_D3_CONFIG bfin_write_MDMA3_DEST_CONFIG
-#define bfin_read_MDMA_D3_IRQ_STATUS bfin_read_MDMA3_DEST_IRQ_STATUS
-#define bfin_write_MDMA_D3_IRQ_STATUS bfin_write_MDMA3_DEST_IRQ_STATUS
-#define bfin_write_MDMA_D3_START_ADDR bfin_write_MDMA3_DEST_START_ADDR
-#define bfin_write_MDMA_D3_X_COUNT bfin_write_MDMA3_DEST_X_COUNT
-#define bfin_write_MDMA_D3_X_MODIFY bfin_write_MDMA3_DEST_X_MODIFY
-#define bfin_write_MDMA_D3_Y_COUNT bfin_write_MDMA3_DEST_Y_COUNT
-#define bfin_write_MDMA_D3_Y_MODIFY bfin_write_MDMA3_DEST_Y_MODIFY
-
-#define MDMA_S0_NEXT_DESC_PTR MDMA0_SRC_CRC0_NEXT_DESC_PTR
-#define MDMA_D0_NEXT_DESC_PTR MDMA0_DEST_CRC0_NEXT_DESC_PTR
-#define MDMA_S1_NEXT_DESC_PTR MDMA1_SRC_CRC1_NEXT_DESC_PTR
-#define MDMA_D1_NEXT_DESC_PTR MDMA1_DEST_CRC1_NEXT_DESC_PTR
-
-#endif
+++ /dev/null
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_GPIO_H_
-#define _MACH_GPIO_H_
-
-#define MAX_BLACKFIN_GPIOS 112
-
-#define GPIO_PA0 0
-#define GPIO_PA1 1
-#define GPIO_PA2 2
-#define GPIO_PA3 3
-#define GPIO_PA4 4
-#define GPIO_PA5 5
-#define GPIO_PA6 6
-#define GPIO_PA7 7
-#define GPIO_PA8 8
-#define GPIO_PA9 9
-#define GPIO_PA10 10
-#define GPIO_PA11 11
-#define GPIO_PA12 12
-#define GPIO_PA13 13
-#define GPIO_PA14 14
-#define GPIO_PA15 15
-#define GPIO_PB0 16
-#define GPIO_PB1 17
-#define GPIO_PB2 18
-#define GPIO_PB3 19
-#define GPIO_PB4 20
-#define GPIO_PB5 21
-#define GPIO_PB6 22
-#define GPIO_PB7 23
-#define GPIO_PB8 24
-#define GPIO_PB9 25
-#define GPIO_PB10 26
-#define GPIO_PB11 27
-#define GPIO_PB12 28
-#define GPIO_PB13 29
-#define GPIO_PB14 30
-#define GPIO_PB15 31
-#define GPIO_PC0 32
-#define GPIO_PC1 33
-#define GPIO_PC2 34
-#define GPIO_PC3 35
-#define GPIO_PC4 36
-#define GPIO_PC5 37
-#define GPIO_PC6 38
-#define GPIO_PC7 39
-#define GPIO_PC8 40
-#define GPIO_PC9 41
-#define GPIO_PC10 42
-#define GPIO_PC11 43
-#define GPIO_PC12 44
-#define GPIO_PC13 45
-#define GPIO_PC14 46
-#define GPIO_PC15 47
-#define GPIO_PD0 48
-#define GPIO_PD1 49
-#define GPIO_PD2 50
-#define GPIO_PD3 51
-#define GPIO_PD4 52
-#define GPIO_PD5 53
-#define GPIO_PD6 54
-#define GPIO_PD7 55
-#define GPIO_PD8 56
-#define GPIO_PD9 57
-#define GPIO_PD10 58
-#define GPIO_PD11 59
-#define GPIO_PD12 60
-#define GPIO_PD13 61
-#define GPIO_PD14 62
-#define GPIO_PD15 63
-#define GPIO_PE0 64
-#define GPIO_PE1 65
-#define GPIO_PE2 66
-#define GPIO_PE3 67
-#define GPIO_PE4 68
-#define GPIO_PE5 69
-#define GPIO_PE6 70
-#define GPIO_PE7 71
-#define GPIO_PE8 72
-#define GPIO_PE9 73
-#define GPIO_PE10 74
-#define GPIO_PE11 75
-#define GPIO_PE12 76
-#define GPIO_PE13 77
-#define GPIO_PE14 78
-#define GPIO_PE15 79
-#define GPIO_PF0 80
-#define GPIO_PF1 81
-#define GPIO_PF2 82
-#define GPIO_PF3 83
-#define GPIO_PF4 84
-#define GPIO_PF5 85
-#define GPIO_PF6 86
-#define GPIO_PF7 87
-#define GPIO_PF8 88
-#define GPIO_PF9 89
-#define GPIO_PF10 90
-#define GPIO_PF11 91
-#define GPIO_PF12 92
-#define GPIO_PF13 93
-#define GPIO_PF14 94
-#define GPIO_PF15 95
-#define GPIO_PG0 96
-#define GPIO_PG1 97
-#define GPIO_PG2 98
-#define GPIO_PG3 99
-#define GPIO_PG4 100
-#define GPIO_PG5 101
-#define GPIO_PG6 102
-#define GPIO_PG7 103
-#define GPIO_PG8 104
-#define GPIO_PG9 105
-#define GPIO_PG10 106
-#define GPIO_PG11 107
-#define GPIO_PG12 108
-#define GPIO_PG13 109
-#define GPIO_PG14 110
-#define GPIO_PG15 111
-
-
-#define BFIN_GPIO_PINT 1
-#define NR_PINT_SYS_IRQS 6
-#define NR_PINTS 112
-
-
-#ifndef __ASSEMBLY__
-
-struct gpio_port_t {
- unsigned long port_fer;
- unsigned long port_fer_set;
- unsigned long port_fer_clear;
- unsigned long data;
- unsigned long data_set;
- unsigned long data_clear;
- unsigned long dir;
- unsigned long dir_set;
- unsigned long dir_clear;
- unsigned long inen;
- unsigned long inen_set;
- unsigned long inen_clear;
- unsigned long port_mux;
- unsigned long toggle;
- unsigned long polar;
- unsigned long polar_set;
- unsigned long polar_clear;
- unsigned long lock;
- unsigned long spare;
- unsigned long revid;
-};
-
-#endif
-
-#include <mach-common/ports-a.h>
-#include <mach-common/ports-b.h>
-#include <mach-common/ports-c.h>
-#include <mach-common/ports-d.h>
-#include <mach-common/ports-e.h>
-#include <mach-common/ports-f.h>
-#include <mach-common/ports-g.h>
-
-#endif /* _MACH_GPIO_H_ */
+++ /dev/null
-/*
- * Copyright 2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BF60x_IRQ_H_
-#define _BF60x_IRQ_H_
-
-#include <mach-common/irq.h>
-
-#define NR_PERI_INTS (5 * 32)
-
-#define IRQ_SEC_ERR BFIN_IRQ(0) /* SEC Error */
-#define IRQ_CGU_EVT BFIN_IRQ(1) /* CGU Event */
-#define IRQ_WATCH0 BFIN_IRQ(2) /* Watchdog0 Interrupt */
-#define IRQ_WATCH1 BFIN_IRQ(3) /* Watchdog1 Interrupt */
-#define IRQ_L2CTL0_ECC_ERR BFIN_IRQ(4) /* L2 ECC Error */
-#define IRQ_L2CTL0_ECC_WARN BFIN_IRQ(5) /* L2 ECC Waring */
-#define IRQ_C0_DBL_FAULT BFIN_IRQ(6) /* Core 0 Double Fault */
-#define IRQ_C1_DBL_FAULT BFIN_IRQ(7) /* Core 1 Double Fault */
-#define IRQ_C0_HW_ERR BFIN_IRQ(8) /* Core 0 Hardware Error */
-#define IRQ_C1_HW_ERR BFIN_IRQ(9) /* Core 1 Hardware Error */
-#define IRQ_C0_NMI_L1_PARITY_ERR BFIN_IRQ(10) /* Core 0 Unhandled NMI or L1 Memory Parity Error */
-#define IRQ_C1_NMI_L1_PARITY_ERR BFIN_IRQ(11) /* Core 1 Unhandled NMI or L1 Memory Parity Error */
-#define CORE_IRQS (IRQ_C1_NMI_L1_PARITY_ERR + 1)
-
-#define IRQ_TIMER0 BFIN_IRQ(12) /* Timer 0 Interrupt */
-#define IRQ_TIMER1 BFIN_IRQ(13) /* Timer 1 Interrupt */
-#define IRQ_TIMER2 BFIN_IRQ(14) /* Timer 2 Interrupt */
-#define IRQ_TIMER3 BFIN_IRQ(15) /* Timer 3 Interrupt */
-#define IRQ_TIMER4 BFIN_IRQ(16) /* Timer 4 Interrupt */
-#define IRQ_TIMER5 BFIN_IRQ(17) /* Timer 5 Interrupt */
-#define IRQ_TIMER6 BFIN_IRQ(18) /* Timer 6 Interrupt */
-#define IRQ_TIMER7 BFIN_IRQ(19) /* Timer 7 Interrupt */
-#define IRQ_TIMER_STAT BFIN_IRQ(20) /* Timer Block Status */
-#define IRQ_PINT0 BFIN_IRQ(21) /* PINT0 Interrupt */
-#define IRQ_PINT1 BFIN_IRQ(22) /* PINT1 Interrupt */
-#define IRQ_PINT2 BFIN_IRQ(23) /* PINT2 Interrupt */
-#define IRQ_PINT3 BFIN_IRQ(24) /* PINT3 Interrupt */
-#define IRQ_PINT4 BFIN_IRQ(25) /* PINT4 Interrupt */
-#define IRQ_PINT5 BFIN_IRQ(26) /* PINT5 Interrupt */
-#define IRQ_CNT BFIN_IRQ(27) /* CNT Interrupt */
-#define IRQ_PWM0_TRIP BFIN_IRQ(28) /* PWM0 Trip Interrupt */
-#define IRQ_PWM0_SYNC BFIN_IRQ(29) /* PWM0 Sync Interrupt */
-#define IRQ_PWM1_TRIP BFIN_IRQ(30) /* PWM1 Trip Interrupt */
-#define IRQ_PWM1_SYNC BFIN_IRQ(31) /* PWM1 Sync Interrupt */
-#define IRQ_TWI0 BFIN_IRQ(32) /* TWI0 Interrupt */
-#define IRQ_TWI1 BFIN_IRQ(33) /* TWI1 Interrupt */
-#define IRQ_SOFT0 BFIN_IRQ(34) /* Software-Driven Interrupt 0 */
-#define IRQ_SOFT1 BFIN_IRQ(35) /* Software-Driven Interrupt 1 */
-#define IRQ_SOFT2 BFIN_IRQ(36) /* Software-Driven Interrupt 2 */
-#define IRQ_SOFT3 BFIN_IRQ(37) /* Software-Driven Interrupt 3 */
-#define IRQ_ACM_EVT_MISS BFIN_IRQ(38) /* ACM Event Miss */
-#define IRQ_ACM_EVT_COMPLETE BFIN_IRQ(39) /* ACM Event Complete */
-#define IRQ_CAN0_RX BFIN_IRQ(40) /* CAN0 Receive Interrupt */
-#define IRQ_CAN0_TX BFIN_IRQ(41) /* CAN0 Transmit Interrupt */
-#define IRQ_CAN0_STAT BFIN_IRQ(42) /* CAN0 Status */
-#define IRQ_SPORT0_TX BFIN_IRQ(43) /* SPORT0 TX Interrupt (DMA0) */
-#define IRQ_SPORT0_TX_STAT BFIN_IRQ(44) /* SPORT0 TX Status Interrupt */
-#define IRQ_SPORT0_RX BFIN_IRQ(45) /* SPORT0 RX Interrupt (DMA1) */
-#define IRQ_SPORT0_RX_STAT BFIN_IRQ(46) /* SPORT0 RX Status Interrupt */
-#define IRQ_SPORT1_TX BFIN_IRQ(47) /* SPORT1 TX Interrupt (DMA2) */
-#define IRQ_SPORT1_TX_STAT BFIN_IRQ(48) /* SPORT1 TX Status Interrupt */
-#define IRQ_SPORT1_RX BFIN_IRQ(49) /* SPORT1 RX Interrupt (DMA3) */
-#define IRQ_SPORT1_RX_STAT BFIN_IRQ(50) /* SPORT1 RX Status Interrupt */
-#define IRQ_SPORT2_TX BFIN_IRQ(51) /* SPORT2 TX Interrupt (DMA4) */
-#define IRQ_SPORT2_TX_STAT BFIN_IRQ(52) /* SPORT2 TX Status Interrupt */
-#define IRQ_SPORT2_RX BFIN_IRQ(53) /* SPORT2 RX Interrupt (DMA5) */
-#define IRQ_SPORT2_RX_STAT BFIN_IRQ(54) /* SPORT2 RX Status Interrupt */
-#define IRQ_SPI0_TX BFIN_IRQ(55) /* SPI0 TX Interrupt (DMA6) */
-#define IRQ_SPI0_RX BFIN_IRQ(56) /* SPI0 RX Interrupt (DMA7) */
-#define IRQ_SPI0_STAT BFIN_IRQ(57) /* SPI0 Status Interrupt */
-#define IRQ_SPI1_TX BFIN_IRQ(58) /* SPI1 TX Interrupt (DMA8) */
-#define IRQ_SPI1_RX BFIN_IRQ(59) /* SPI1 RX Interrupt (DMA9) */
-#define IRQ_SPI1_STAT BFIN_IRQ(60) /* SPI1 Status Interrupt */
-#define IRQ_RSI BFIN_IRQ(61) /* RSI (DMA10) Interrupt */
-#define IRQ_RSI_INT0 BFIN_IRQ(62) /* RSI Interrupt0 */
-#define IRQ_RSI_INT1 BFIN_IRQ(63) /* RSI Interrupt1 */
-#define IRQ_SDU BFIN_IRQ(64) /* DMA11 Data (SDU) */
-/* -- RESERVED -- 65 DMA12 Data (Reserved) */
-/* -- RESERVED -- 66 Reserved */
-/* -- RESERVED -- 67 Reserved */
-#define IRQ_EMAC0_STAT BFIN_IRQ(68) /* EMAC0 Status */
-/* -- RESERVED -- 69 EMAC0 Power (Reserved) */
-#define IRQ_EMAC1_STAT BFIN_IRQ(70) /* EMAC1 Status */
-/* -- RESERVED -- 71 EMAC1 Power (Reserved) */
-#define IRQ_LP0 BFIN_IRQ(72) /* DMA13 Data (Link Port 0) */
-#define IRQ_LP0_STAT BFIN_IRQ(73) /* Link Port 0 Status */
-#define IRQ_LP1 BFIN_IRQ(74) /* DMA14 Data (Link Port 1) */
-#define IRQ_LP1_STAT BFIN_IRQ(75) /* Link Port 1 Status */
-#define IRQ_LP2 BFIN_IRQ(76) /* DMA15 Data (Link Port 2) */
-#define IRQ_LP2_STAT BFIN_IRQ(77) /* Link Port 2 Status */
-#define IRQ_LP3 BFIN_IRQ(78) /* DMA16 Data(Link Port 3) */
-#define IRQ_LP3_STAT BFIN_IRQ(79) /* Link Port 3 Status */
-#define IRQ_UART0_TX BFIN_IRQ(80) /* UART0 TX Interrupt (DMA17) */
-#define IRQ_UART0_RX BFIN_IRQ(81) /* UART0 RX Interrupt (DMA18) */
-#define IRQ_UART0_STAT BFIN_IRQ(82) /* UART0 Status(Error) Interrupt */
-#define IRQ_UART1_TX BFIN_IRQ(83) /* UART1 TX Interrupt (DMA19) */
-#define IRQ_UART1_RX BFIN_IRQ(84) /* UART1 RX Interrupt (DMA20) */
-#define IRQ_UART1_STAT BFIN_IRQ(85) /* UART1 Status(Error) Interrupt */
-#define IRQ_MDMA0_SRC_CRC0 BFIN_IRQ(86) /* DMA21 Data (MDMA Stream 0 Source/CRC0 Input Channel) */
-#define IRQ_MDMA0_DEST_CRC0 BFIN_IRQ(87) /* DMA22 Data (MDMA Stream 0 Destination/CRC0 Output Channel) */
-#define IRQ_MDMAS0 IRQ_MDMA0_DEST_CRC0
-#define IRQ_CRC0_DCNTEXP BFIN_IRQ(88) /* CRC0 DATACOUNT Expiration */
-#define IRQ_CRC0_ERR BFIN_IRQ(89) /* CRC0 Error */
-#define IRQ_MDMA1_SRC_CRC1 BFIN_IRQ(90) /* DMA23 Data (MDMA Stream 1 Source/CRC1 Input Channel) */
-#define IRQ_MDMA1_DEST_CRC1 BFIN_IRQ(91) /* DMA24 Data (MDMA Stream 1 Destination/CRC1 Output Channel) */
-#define IRQ_MDMAS1 IRQ_MDMA1_DEST_CRC1
-#define IRQ_CRC1_DCNTEXP BFIN_IRQ(92) /* CRC1 DATACOUNT Expiration */
-#define IRQ_CRC1_ERR BFIN_IRQ(93) /* CRC1 Error */
-#define IRQ_MDMA2_SRC BFIN_IRQ(94) /* DMA25 Data (MDMA Stream 2 Source Channel) */
-#define IRQ_MDMA2_DEST BFIN_IRQ(95) /* DMA26 Data (MDMA Stream 2 Destination Channel) */
-#define IRQ_MDMAS2 IRQ_MDMA2_DEST
-#define IRQ_MDMA3_SRC BFIN_IRQ(96) /* DMA27 Data (MDMA Stream 3 Source Channel) */
-#define IRQ_MDMA3_DEST BFIN_IRQ(97) /* DMA28 Data (MDMA Stream 3 Destination Channel) */
-#define IRQ_MDMAS3 IRQ_MDMA3_DEST
-#define IRQ_EPPI0_CH0 BFIN_IRQ(98) /* DMA29 Data (EPPI0 Channel 0) */
-#define IRQ_EPPI0_CH1 BFIN_IRQ(99) /* DMA30 Data (EPPI0 Channel 1) */
-#define IRQ_EPPI0_STAT BFIN_IRQ(100) /* EPPI0 Status */
-#define IRQ_EPPI2_CH0 BFIN_IRQ(101) /* DMA31 Data (EPPI2 Channel 0) */
-#define IRQ_EPPI2_CH1 BFIN_IRQ(102) /* DMA32 Data (EPPI2 Channel 1) */
-#define IRQ_EPPI2_STAT BFIN_IRQ(103) /* EPPI2 Status */
-#define IRQ_EPPI1_CH0 BFIN_IRQ(104) /* DMA33 Data (EPPI1 Channel 0) */
-#define IRQ_EPPI1_CH1 BFIN_IRQ(105) /* DMA34 Data (EPPI1 Channel 1) */
-#define IRQ_EPPI1_STAT BFIN_IRQ(106) /* EPPI1 Status */
-#define IRQ_PIXC_CH0 BFIN_IRQ(107) /* DMA35 Data (PIXC Channel 0) */
-#define IRQ_PIXC_CH1 BFIN_IRQ(108) /* DMA36 Data (PIXC Channel 1) */
-#define IRQ_PIXC_CH2 BFIN_IRQ(109) /* DMA37 Data (PIXC Channel 2) */
-#define IRQ_PIXC_STAT BFIN_IRQ(110) /* PIXC Status */
-#define IRQ_PVP_CPDOB BFIN_IRQ(111) /* DMA38 Data (PVP0 Camera Pipe Data Out B) */
-#define IRQ_PVP_CPDOC BFIN_IRQ(112) /* DMA39 Data (PVP0 Camera Pipe Data Out C) */
-#define IRQ_PVP_CPSTAT BFIN_IRQ(113) /* DMA40 Data (PVP0 Camera Pipe Status Out) */
-#define IRQ_PVP_CPCI BFIN_IRQ(114) /* DMA41 Data (PVP0 Camera Pipe Control In) */
-#define IRQ_PVP_STAT0 BFIN_IRQ(115) /* PVP0 Status 0 */
-#define IRQ_PVP_MPDO BFIN_IRQ(116) /* DMA42 Data (PVP0 Memory Pipe Data Out) */
-#define IRQ_PVP_MPDI BFIN_IRQ(117) /* DMA43 Data (PVP0 Memory Pipe Data In) */
-#define IRQ_PVP_MPSTAT BFIN_IRQ(118) /* DMA44 Data (PVP0 Memory Pipe Status Out) */
-#define IRQ_PVP_MPCI BFIN_IRQ(119) /* DMA45 Data (PVP0 Memory Pipe Control In) */
-#define IRQ_PVP_CPDOA BFIN_IRQ(120) /* DMA46 Data (PVP0 Camera Pipe Data Out A) */
-#define IRQ_PVP_STAT1 BFIN_IRQ(121) /* PVP0 Status 1 */
-#define IRQ_USB_STAT BFIN_IRQ(122) /* USB Status Interrupt */
-#define IRQ_USB_DMA BFIN_IRQ(123) /* USB DMA Interrupt */
-#define IRQ_TRU_INT0 BFIN_IRQ(124) /* TRU0 Interrupt 0 */
-#define IRQ_TRU_INT1 BFIN_IRQ(125) /* TRU0 Interrupt 1 */
-#define IRQ_TRU_INT2 BFIN_IRQ(126) /* TRU0 Interrupt 2 */
-#define IRQ_TRU_INT3 BFIN_IRQ(127) /* TRU0 Interrupt 3 */
-#define IRQ_DMAC0_ERROR BFIN_IRQ(128) /* DMAC0 Status Interrupt */
-#define IRQ_CGU0_ERROR BFIN_IRQ(129) /* CGU0 Error */
-/* -- RESERVED -- 130 Reserved */
-#define IRQ_DPM BFIN_IRQ(131) /* DPM0 Event */
-/* -- RESERVED -- 132 Reserved */
-#define IRQ_SWU0 BFIN_IRQ(133) /* SWU0 */
-#define IRQ_SWU1 BFIN_IRQ(134) /* SWU1 */
-#define IRQ_SWU2 BFIN_IRQ(135) /* SWU2 */
-#define IRQ_SWU3 BFIN_IRQ(136) /* SWU3 */
-#define IRQ_SWU4 BFIN_IRQ(137) /* SWU4 */
-#define IRQ_SWU5 BFIN_IRQ(138) /* SWU5 */
-#define IRQ_SWU6 BFIN_IRQ(139) /* SWU6 */
-
-#define SYS_IRQS IRQ_SWU6
-
-#define BFIN_PA_IRQ(x) ((x) + SYS_IRQS + 1)
-#define IRQ_PA0 BFIN_PA_IRQ(0)
-#define IRQ_PA1 BFIN_PA_IRQ(1)
-#define IRQ_PA2 BFIN_PA_IRQ(2)
-#define IRQ_PA3 BFIN_PA_IRQ(3)
-#define IRQ_PA4 BFIN_PA_IRQ(4)
-#define IRQ_PA5 BFIN_PA_IRQ(5)
-#define IRQ_PA6 BFIN_PA_IRQ(6)
-#define IRQ_PA7 BFIN_PA_IRQ(7)
-#define IRQ_PA8 BFIN_PA_IRQ(8)
-#define IRQ_PA9 BFIN_PA_IRQ(9)
-#define IRQ_PA10 BFIN_PA_IRQ(10)
-#define IRQ_PA11 BFIN_PA_IRQ(11)
-#define IRQ_PA12 BFIN_PA_IRQ(12)
-#define IRQ_PA13 BFIN_PA_IRQ(13)
-#define IRQ_PA14 BFIN_PA_IRQ(14)
-#define IRQ_PA15 BFIN_PA_IRQ(15)
-
-#define BFIN_PB_IRQ(x) ((x) + IRQ_PA15 + 1)
-#define IRQ_PB0 BFIN_PB_IRQ(0)
-#define IRQ_PB1 BFIN_PB_IRQ(1)
-#define IRQ_PB2 BFIN_PB_IRQ(2)
-#define IRQ_PB3 BFIN_PB_IRQ(3)
-#define IRQ_PB4 BFIN_PB_IRQ(4)
-#define IRQ_PB5 BFIN_PB_IRQ(5)
-#define IRQ_PB6 BFIN_PB_IRQ(6)
-#define IRQ_PB7 BFIN_PB_IRQ(7)
-#define IRQ_PB8 BFIN_PB_IRQ(8)
-#define IRQ_PB9 BFIN_PB_IRQ(9)
-#define IRQ_PB10 BFIN_PB_IRQ(10)
-#define IRQ_PB11 BFIN_PB_IRQ(11)
-#define IRQ_PB12 BFIN_PB_IRQ(12)
-#define IRQ_PB13 BFIN_PB_IRQ(13)
-#define IRQ_PB14 BFIN_PB_IRQ(14)
-#define IRQ_PB15 BFIN_PB_IRQ(15) /* N/A */
-
-#define BFIN_PC_IRQ(x) ((x) + IRQ_PB15 + 1)
-#define IRQ_PC0 BFIN_PC_IRQ(0)
-#define IRQ_PC1 BFIN_PC_IRQ(1)
-#define IRQ_PC2 BFIN_PC_IRQ(2)
-#define IRQ_PC3 BFIN_PC_IRQ(3)
-#define IRQ_PC4 BFIN_PC_IRQ(4)
-#define IRQ_PC5 BFIN_PC_IRQ(5)
-#define IRQ_PC6 BFIN_PC_IRQ(6)
-#define IRQ_PC7 BFIN_PC_IRQ(7)
-#define IRQ_PC8 BFIN_PC_IRQ(8)
-#define IRQ_PC9 BFIN_PC_IRQ(9)
-#define IRQ_PC10 BFIN_PC_IRQ(10)
-#define IRQ_PC11 BFIN_PC_IRQ(11)
-#define IRQ_PC12 BFIN_PC_IRQ(12)
-#define IRQ_PC13 BFIN_PC_IRQ(13)
-#define IRQ_PC14 BFIN_PC_IRQ(14) /* N/A */
-#define IRQ_PC15 BFIN_PC_IRQ(15) /* N/A */
-
-#define BFIN_PD_IRQ(x) ((x) + IRQ_PC15 + 1)
-#define IRQ_PD0 BFIN_PD_IRQ(0)
-#define IRQ_PD1 BFIN_PD_IRQ(1)
-#define IRQ_PD2 BFIN_PD_IRQ(2)
-#define IRQ_PD3 BFIN_PD_IRQ(3)
-#define IRQ_PD4 BFIN_PD_IRQ(4)
-#define IRQ_PD5 BFIN_PD_IRQ(5)
-#define IRQ_PD6 BFIN_PD_IRQ(6)
-#define IRQ_PD7 BFIN_PD_IRQ(7)
-#define IRQ_PD8 BFIN_PD_IRQ(8)
-#define IRQ_PD9 BFIN_PD_IRQ(9)
-#define IRQ_PD10 BFIN_PD_IRQ(10)
-#define IRQ_PD11 BFIN_PD_IRQ(11)
-#define IRQ_PD12 BFIN_PD_IRQ(12)
-#define IRQ_PD13 BFIN_PD_IRQ(13)
-#define IRQ_PD14 BFIN_PD_IRQ(14)
-#define IRQ_PD15 BFIN_PD_IRQ(15)
-
-#define BFIN_PE_IRQ(x) ((x) + IRQ_PD15 + 1)
-#define IRQ_PE0 BFIN_PE_IRQ(0)
-#define IRQ_PE1 BFIN_PE_IRQ(1)
-#define IRQ_PE2 BFIN_PE_IRQ(2)
-#define IRQ_PE3 BFIN_PE_IRQ(3)
-#define IRQ_PE4 BFIN_PE_IRQ(4)
-#define IRQ_PE5 BFIN_PE_IRQ(5)
-#define IRQ_PE6 BFIN_PE_IRQ(6)
-#define IRQ_PE7 BFIN_PE_IRQ(7)
-#define IRQ_PE8 BFIN_PE_IRQ(8)
-#define IRQ_PE9 BFIN_PE_IRQ(9)
-#define IRQ_PE10 BFIN_PE_IRQ(10)
-#define IRQ_PE11 BFIN_PE_IRQ(11)
-#define IRQ_PE12 BFIN_PE_IRQ(12)
-#define IRQ_PE13 BFIN_PE_IRQ(13)
-#define IRQ_PE14 BFIN_PE_IRQ(14)
-#define IRQ_PE15 BFIN_PE_IRQ(15)
-
-#define BFIN_PF_IRQ(x) ((x) + IRQ_PE15 + 1)
-#define IRQ_PF0 BFIN_PF_IRQ(0)
-#define IRQ_PF1 BFIN_PF_IRQ(1)
-#define IRQ_PF2 BFIN_PF_IRQ(2)
-#define IRQ_PF3 BFIN_PF_IRQ(3)
-#define IRQ_PF4 BFIN_PF_IRQ(4)
-#define IRQ_PF5 BFIN_PF_IRQ(5)
-#define IRQ_PF6 BFIN_PF_IRQ(6)
-#define IRQ_PF7 BFIN_PF_IRQ(7)
-#define IRQ_PF8 BFIN_PF_IRQ(8)
-#define IRQ_PF9 BFIN_PF_IRQ(9)
-#define IRQ_PF10 BFIN_PF_IRQ(10)
-#define IRQ_PF11 BFIN_PF_IRQ(11)
-#define IRQ_PF12 BFIN_PF_IRQ(12)
-#define IRQ_PF13 BFIN_PF_IRQ(13)
-#define IRQ_PF14 BFIN_PF_IRQ(14)
-#define IRQ_PF15 BFIN_PF_IRQ(15)
-
-#define BFIN_PG_IRQ(x) ((x) + IRQ_PF15 + 1)
-#define IRQ_PG0 BFIN_PG_IRQ(0)
-#define IRQ_PG1 BFIN_PG_IRQ(1)
-#define IRQ_PG2 BFIN_PG_IRQ(2)
-#define IRQ_PG3 BFIN_PG_IRQ(3)
-#define IRQ_PG4 BFIN_PG_IRQ(4)
-#define IRQ_PG5 BFIN_PG_IRQ(5)
-#define IRQ_PG6 BFIN_PG_IRQ(6)
-#define IRQ_PG7 BFIN_PG_IRQ(7)
-#define IRQ_PG8 BFIN_PG_IRQ(8)
-#define IRQ_PG9 BFIN_PG_IRQ(9)
-#define IRQ_PG10 BFIN_PG_IRQ(10)
-#define IRQ_PG11 BFIN_PG_IRQ(11)
-#define IRQ_PG12 BFIN_PG_IRQ(12)
-#define IRQ_PG13 BFIN_PG_IRQ(13)
-#define IRQ_PG14 BFIN_PG_IRQ(14)
-#define IRQ_PG15 BFIN_PG_IRQ(15)
-
-#define GPIO_IRQ_BASE IRQ_PA0
-
-#define NR_MACH_IRQS (IRQ_PG15 + 1)
-
-#define SEC_SCTL_PRIO_OFFSET 8
-
-#ifndef __ASSEMBLY__
-#include <linux/types.h>
-
-extern u8 sec_int_priority[];
-
-/*
- * gpio pint registers layout
- */
-struct bfin_pint_regs {
- u32 mask_set;
- u32 mask_clear;
- u32 request;
- u32 assign;
- u32 edge_set;
- u32 edge_clear;
- u32 invert_set;
- u32 invert_clear;
- u32 pinstate;
- u32 latch;
- u32 __pad0[2];
-};
-
-#endif
-
-#endif
+++ /dev/null
-/*
- * BF60x memory map
- *
- * Copyright 2011 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MACH_MEM_MAP_H__
-#define __BFIN_MACH_MEM_MAP_H__
-
-#ifndef __BFIN_MEM_MAP_H__
-# error "do not include mach/mem_map.h directly -- use asm/mem_map.h"
-#endif
-
-/* Async Memory Banks */
-#define ASYNC_BANK3_BASE 0xBC000000 /* Async Bank 3 */
-#define ASYNC_BANK3_SIZE 0x04000000 /* 64M */
-#define ASYNC_BANK2_BASE 0xB8000000 /* Async Bank 2 */
-#define ASYNC_BANK2_SIZE 0x04000000 /* 64M */
-#define ASYNC_BANK1_BASE 0xB4000000 /* Async Bank 1 */
-#define ASYNC_BANK1_SIZE 0x04000000 /* 64M */
-#define ASYNC_BANK0_BASE 0xB0000000 /* Async Bank 0 */
-#define ASYNC_BANK0_SIZE 0x04000000 /* 64M */
-
-/* Boot ROM Memory */
-
-#define BOOT_ROM_START 0xC8000000
-#define BOOT_ROM_LENGTH 0x8000
-
-/* Level 1 Memory */
-
-/* Memory Map for ADSP-BF60x processors */
-#ifdef CONFIG_BFIN_ICACHE
-#define BFIN_ICACHESIZE (16*1024)
-#define L1_CODE_LENGTH 0x10000
-#else
-#define BFIN_ICACHESIZE (0*1024)
-#define L1_CODE_LENGTH 0x14000
-#endif
-
-#define L1_CODE_START 0xFFA00000
-#define L1_DATA_A_START 0xFF800000
-#define L1_DATA_B_START 0xFF900000
-
-
-#define COREA_L1_SCRATCH_START 0xFFB00000
-#define COREB_L1_SCRATCH_START 0xFF700000
-
-#define COREB_L1_CODE_START 0xFF600000
-#define COREB_L1_DATA_A_START 0xFF400000
-#define COREB_L1_DATA_B_START 0xFF500000
-
-#define COREB_L1_CODE_LENGTH 0x14000
-#define COREB_L1_DATA_A_LENGTH 0x8000
-#define COREB_L1_DATA_B_LENGTH 0x8000
-
-
-#ifdef CONFIG_BFIN_DCACHE
-
-#ifdef CONFIG_BFIN_DCACHE_BANKA
-#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE (16*1024)
-#define BFIN_DSUPBANKS 1
-#else
-#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
-#define BFIN_DCACHESIZE (32*1024)
-#define BFIN_DSUPBANKS 2
-#endif
-
-#else
-#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH 0x8000
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE (0*1024)
-#define BFIN_DSUPBANKS 0
-#endif /*CONFIG_BFIN_DCACHE*/
-
-/* Level 2 Memory */
-#define L2_START 0xC8080000
-#define L2_LENGTH 0x40000
-
-#endif
+++ /dev/null
-/* #include <mach-common/pll.h> */
+++ /dev/null
-/*
- * Blackfin bf609 power management
- *
- * Copyright 2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2
- */
-
-#ifndef __MACH_BF609_PM_H__
-#define __MACH_BF609_PM_H__
-
-#include <linux/suspend.h>
-#include <linux/platform_device.h>
-
-extern int bfin609_pm_enter(suspend_state_t state);
-extern int bf609_pm_prepare(void);
-extern void bf609_pm_finish(void);
-
-void bf609_hibernate(void);
-void bfin_sec_raise_irq(unsigned int sid);
-void coreb_enable(void);
-
-int bf609_nor_flash_init(struct platform_device *pdev);
-void bf609_nor_flash_exit(struct platform_device *pdev);
-#endif
+++ /dev/null
-/*
- * Copyright 2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _MACH_PORTMUX_H_
-#define _MACH_PORTMUX_H_
-
-/* EMAC RMII Port Mux */
-#define P_MII0_MDC (P_DEFINED | P_IDENT(GPIO_PC6) | P_FUNCT(0))
-#define P_MII0_MDIO (P_DEFINED | P_IDENT(GPIO_PC7) | P_FUNCT(0))
-#define P_MII0_ETxD0 (P_DEFINED | P_IDENT(GPIO_PC2) | P_FUNCT(0))
-#define P_MII0_ERxD0 (P_DEFINED | P_IDENT(GPIO_PC0) | P_FUNCT(0))
-#define P_MII0_ETxD1 (P_DEFINED | P_IDENT(GPIO_PC3) | P_FUNCT(0))
-#define P_MII0_ERxD1 (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(0))
-#define P_MII0_ETxEN (P_DEFINED | P_IDENT(GPIO_PB13) | P_FUNCT(0))
-#define P_MII0_PHYINT (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(0))
-#define P_MII0_CRS (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(0))
-#define P_MII0_ERxER (P_DEFINED | P_IDENT(GPIO_PC4) | P_FUNCT(0))
-#define P_MII0_TxCLK (P_DEFINED | P_IDENT(GPIO_PB14) | P_FUNCT(0))
-#define P_MII0_PTPPPS (P_DEFINED | P_IDENT(GPIO_PB15) | P_FUNCT(0))
-
-#define P_RMII0 {\
- P_MII0_ETxD0, \
- P_MII0_ETxD1, \
- P_MII0_ETxEN, \
- P_MII0_ERxD0, \
- P_MII0_ERxD1, \
- P_MII0_ERxER, \
- P_MII0_TxCLK, \
- P_MII0_PHYINT, \
- P_MII0_CRS, \
- P_MII0_PTPPPS, \
- P_MII0_MDC, \
- P_MII0_MDIO, 0}
-
-#define P_MII1_MDC (P_DEFINED | P_IDENT(GPIO_PE10) | P_FUNCT(0))
-#define P_MII1_MDIO (P_DEFINED | P_IDENT(GPIO_PE11) | P_FUNCT(0))
-#define P_MII1_ETxD0 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
-#define P_MII1_ERxD0 (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
-#define P_MII1_ETxD1 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0))
-#define P_MII1_ERxD1 (P_DEFINED | P_IDENT(GPIO_PE15) | P_FUNCT(0))
-#define P_MII1_ETxEN (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
-#define P_MII1_PHYINT (P_DEFINED | P_IDENT(GPIO_PE12) | P_FUNCT(0))
-#define P_MII1_CRS (P_DEFINED | P_IDENT(GPIO_PE13) | P_FUNCT(0))
-#define P_MII1_ERxER (P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(0))
-#define P_MII1_TxCLK (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
-#define P_MII1_PTPPPS (P_DEFINED | P_IDENT(GPIO_PC9) | P_FUNCT(0))
-
-#define P_RMII1 {\
- P_MII1_ETxD0, \
- P_MII1_ETxD1, \
- P_MII1_ETxEN, \
- P_MII1_ERxD0, \
- P_MII1_ERxD1, \
- P_MII1_ERxER, \
- P_MII1_TxCLK, \
- P_MII1_PHYINT, \
- P_MII1_CRS, \
- P_MII1_PTPPPS, \
- P_MII1_MDC, \
- P_MII1_MDIO, 0}
-
-/* PPI Port Mux */
-#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
-#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
-#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
-#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
-#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
-#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
-#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
-#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
-#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
-#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
-#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1))
-#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1))
-#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1))
-#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1))
-#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
-#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
-#define P_PPI0_D16 (P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(1))
-#define P_PPI0_D17 (P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(1))
-#define P_PPI0_D18 (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(1))
-#define P_PPI0_D19 (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(1))
-#define P_PPI0_D20 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(1))
-#define P_PPI0_D21 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(1))
-#define P_PPI0_D22 (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(1))
-#define P_PPI0_D23 (P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(1))
-#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PE9) | P_FUNCT(1))
-#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PE8) | P_FUNCT(1))
-#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(1))
-#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(1))
-
-#define P_PPI1_D0 (P_DEFINED | P_IDENT(GPIO_PC0) | P_FUNCT(1))
-#define P_PPI1_D1 (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(1))
-#define P_PPI1_D2 (P_DEFINED | P_IDENT(GPIO_PC2) | P_FUNCT(1))
-#define P_PPI1_D3 (P_DEFINED | P_IDENT(GPIO_PC3) | P_FUNCT(1))
-#define P_PPI1_D4 (P_DEFINED | P_IDENT(GPIO_PC4) | P_FUNCT(1))
-#define P_PPI1_D5 (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(1))
-#define P_PPI1_D6 (P_DEFINED | P_IDENT(GPIO_PC6) | P_FUNCT(1))
-#define P_PPI1_D7 (P_DEFINED | P_IDENT(GPIO_PC7) | P_FUNCT(1))
-#define P_PPI1_D8 (P_DEFINED | P_IDENT(GPIO_PC8) | P_FUNCT(1))
-#define P_PPI1_D9 (P_DEFINED | P_IDENT(GPIO_PC9) | P_FUNCT(1))
-#define P_PPI1_D10 (P_DEFINED | P_IDENT(GPIO_PC10) | P_FUNCT(1))
-#define P_PPI1_D11 (P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(1))
-#define P_PPI1_D12 (P_DEFINED | P_IDENT(GPIO_PC12) | P_FUNCT(1))
-#define P_PPI1_D13 (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(1))
-#define P_PPI1_D14 (P_DEFINED | P_IDENT(GPIO_PC14) | P_FUNCT(1))
-#define P_PPI1_D15 (P_DEFINED | P_IDENT(GPIO_PC15) | P_FUNCT(1))
-#define P_PPI1_D16 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(1))
-#define P_PPI1_D17 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(1))
-#define P_PPI1_CLK (P_DEFINED | P_IDENT(GPIO_PB14) | P_FUNCT(1))
-#define P_PPI1_FS1 (P_DEFINED | P_IDENT(GPIO_PB13) | P_FUNCT(1))
-#define P_PPI1_FS2 (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(1))
-#define P_PPI1_FS3 (P_DEFINED | P_IDENT(GPIO_PB15) | P_FUNCT(1))
-
-#define P_PPI2_D0 (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(1))
-#define P_PPI2_D1 (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(1))
-#define P_PPI2_D2 (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(1))
-#define P_PPI2_D3 (P_DEFINED | P_IDENT(GPIO_PA3) | P_FUNCT(1))
-#define P_PPI2_D4 (P_DEFINED | P_IDENT(GPIO_PA4) | P_FUNCT(1))
-#define P_PPI2_D5 (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(1))
-#define P_PPI2_D6 (P_DEFINED | P_IDENT(GPIO_PA6) | P_FUNCT(1))
-#define P_PPI2_D7 (P_DEFINED | P_IDENT(GPIO_PA7) | P_FUNCT(1))
-#define P_PPI2_D8 (P_DEFINED | P_IDENT(GPIO_PA8) | P_FUNCT(1))
-#define P_PPI2_D9 (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(1))
-#define P_PPI2_D10 (P_DEFINED | P_IDENT(GPIO_PA10) | P_FUNCT(1))
-#define P_PPI2_D11 (P_DEFINED | P_IDENT(GPIO_PA11) | P_FUNCT(1))
-#define P_PPI2_D12 (P_DEFINED | P_IDENT(GPIO_PA12) | P_FUNCT(1))
-#define P_PPI2_D13 (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(1))
-#define P_PPI2_D14 (P_DEFINED | P_IDENT(GPIO_PA14) | P_FUNCT(1))
-#define P_PPI2_D15 (P_DEFINED | P_IDENT(GPIO_PA15) | P_FUNCT(1))
-#define P_PPI2_D16 (P_DEFINED | P_IDENT(GPIO_PB7) | P_FUNCT(1))
-#define P_PPI2_D17 (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(1))
-#define P_PPI2_CLK (P_DEFINED | P_IDENT(GPIO_PB0) | P_FUNCT(1))
-#define P_PPI2_FS1 (P_DEFINED | P_IDENT(GPIO_PB1) | P_FUNCT(1))
-#define P_PPI2_FS2 (P_DEFINED | P_IDENT(GPIO_PB2) | P_FUNCT(1))
-#define P_PPI2_FS3 (P_DEFINED | P_IDENT(GPIO_PB3) | P_FUNCT(1))
-
-/* SPI Port Mux */
-#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(3))
-#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(0))
-#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(0))
-#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(0))
-#define P_SPI0_RDY (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(0))
-#define P_SPI0_D2 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(0))
-#define P_SPI0_D3 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(0))
-
-#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(0))
-#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(2))
-#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(2))
-#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PC15) | P_FUNCT(0))
-#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(0))
-#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(0))
-#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PC12) | P_FUNCT(0))
-
-#define P_SPI1_SS (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(3))
-#define P_SPI1_SCK (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(0))
-#define P_SPI1_MISO (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(0))
-#define P_SPI1_MOSI (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(0))
-#define P_SPI1_RDY (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(0))
-#define P_SPI1_D2 (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(0))
-#define P_SPI1_D3 (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(0))
-
-#define P_SPI1_SSEL1 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(0))
-#define P_SPI1_SSEL2 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(2))
-#define P_SPI1_SSEL3 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(2))
-#define P_SPI1_SSEL4 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(2))
-#define P_SPI1_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
-#define P_SPI1_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
-#define P_SPI1_SSEL7 (P_DEFINED | P_IDENT(GPIO_PC14) | P_FUNCT(0))
-
-#define GPIO_DEFAULT_BOOT_SPI_CS
-#define P_DEFAULT_BOOT_SPI_CS
-
-/* CORE IDLE */
-#define P_IDLEA (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1))
-#define P_IDLEB (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
-#define P_SLEEP (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(2))
-
-/* UART Port Mux */
-#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(1))
-#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(1))
-#define P_UART0_RTS (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(1))
-#define P_UART0_CTS (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(1))
-
-#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
-#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
-#define P_UART1_RTS (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
-#define P_UART1_CTS (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
-
-/* Timer */
-#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(3))
-#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(2))
-#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1))
-#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(1))
-#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1))
-#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1))
-#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
-#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
-#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
-
-/* RSI */
-#define P_RSI_DATA0 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(2))
-#define P_RSI_DATA1 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(2))
-#define P_RSI_DATA2 (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(2))
-#define P_RSI_DATA3 (P_DEFINED | P_IDENT(GPIO_PE15) | P_FUNCT(2))
-#define P_RSI_DATA4 (P_DEFINED | P_IDENT(GPIO_PE13) | P_FUNCT(2))
-#define P_RSI_DATA5 (P_DEFINED | P_IDENT(GPIO_PE12) | P_FUNCT(2))
-#define P_RSI_DATA6 (P_DEFINED | P_IDENT(GPIO_PE10) | P_FUNCT(2))
-#define P_RSI_DATA7 (P_DEFINED | P_IDENT(GPIO_PE11) | P_FUNCT(2))
-#define P_RSI_CMD (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1))
-#define P_RSI_CLK (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
-
-/* PTP */
-#define P_PTP0_PPS (P_DEFINED | P_IDENT(GPIO_PB15) | P_FUNCT(0))
-#define P_PTP0_CLKIN (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(2))
-#define P_PTP0_AUXIN (P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(2))
-
-#define P_PTP1_PPS (P_DEFINED | P_IDENT(GPIO_PC9) | P_FUNCT(0))
-#define P_PTP1_CLKIN (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(2))
-#define P_PTP1_AUXIN (P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(2))
-
-/* SMC Port Mux */
-#define P_A3 (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(0))
-#define P_A4 (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(0))
-#define P_A5 (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(0))
-#define P_A6 (P_DEFINED | P_IDENT(GPIO_PA3) | P_FUNCT(0))
-#define P_A7 (P_DEFINED | P_IDENT(GPIO_PA4) | P_FUNCT(0))
-#define P_A8 (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(0))
-#define P_A9 (P_DEFINED | P_IDENT(GPIO_PA6) | P_FUNCT(0))
-#define P_A10 (P_DEFINED | P_IDENT(GPIO_PA7) | P_FUNCT(0))
-#define P_A11 (P_DEFINED | P_IDENT(GPIO_PA8) | P_FUNCT(0))
-#define P_A12 (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(0))
-#define P_A13 (P_DEFINED | P_IDENT(GPIO_PB2) | P_FUNCT(0))
-#define P_A14 (P_DEFINED | P_IDENT(GPIO_PA10) | P_FUNCT(0))
-#define P_A15 (P_DEFINED | P_IDENT(GPIO_PA11) | P_FUNCT(0))
-#define P_A16 (P_DEFINED | P_IDENT(GPIO_PB3) | P_FUNCT(0))
-#define P_A17 (P_DEFINED | P_IDENT(GPIO_PA12) | P_FUNCT(0))
-#define P_A18 (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(0))
-#define P_A19 (P_DEFINED | P_IDENT(GPIO_PA14) | P_FUNCT(0))
-#define P_A20 (P_DEFINED | P_IDENT(GPIO_PA15) | P_FUNCT(0))
-#define P_A21 (P_DEFINED | P_IDENT(GPIO_PB6) | P_FUNCT(0))
-#define P_A22 (P_DEFINED | P_IDENT(GPIO_PB7) | P_FUNCT(0))
-#define P_A23 (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(0))
-#define P_A24 (P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(0))
-#define P_A25 (P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(0))
-#define P_NORCK (P_DEFINED | P_IDENT(GPIO_PB0) | P_FUNCT(0))
-
-#define P_AMS1 (P_DEFINED | P_IDENT(GPIO_PB1) | P_FUNCT(0))
-#define P_AMS2 (P_DEFINED | P_IDENT(GPIO_PB4) | P_FUNCT(0))
-#define P_AMS3 (P_DEFINED | P_IDENT(GPIO_PB5) | P_FUNCT(0))
-
-/* CAN */
-#define P_CAN0_TX (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2))
-#define P_CAN0_RX (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(2))
-
-/* SPORT */
-#define P_SPORT0_ACLK (P_DEFINED | P_IDENT(GPIO_PB5) | P_FUNCT(2))
-#define P_SPORT0_AFS (P_DEFINED | P_IDENT(GPIO_PB4) | P_FUNCT(2))
-#define P_SPORT0_AD0 (P_DEFINED | P_IDENT(GPIO_PB9) | P_FUNCT(2))
-#define P_SPORT0_AD1 (P_DEFINED | P_IDENT(GPIO_PB12) | P_FUNCT(2))
-#define P_SPORT0_ATDV (P_DEFINED | P_IDENT(GPIO_PB6) | P_FUNCT(1))
-#define P_SPORT0_BCLK (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(2))
-#define P_SPORT0_BFS (P_DEFINED | P_IDENT(GPIO_PB7) | P_FUNCT(2))
-#define P_SPORT0_BD0 (P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(2))
-#define P_SPORT0_BD1 (P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(2))
-#define P_SPORT0_BTDV (P_DEFINED | P_IDENT(GPIO_PB12) | P_FUNCT(1))
-
-#define P_SPORT1_ACLK (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(2))
-#define P_SPORT1_AFS (P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(2))
-#define P_SPORT1_AD0 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(2))
-#define P_SPORT1_AD1 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(2))
-#define P_SPORT1_ATDV (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(0))
-#define P_SPORT1_BCLK (P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(2))
-#define P_SPORT1_BFS (P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(2))
-#define P_SPORT1_BD0 (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(2))
-#define P_SPORT1_BD1 (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(2))
-#define P_SPORT1_BTDV (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(0))
-
-#define P_SPORT2_ACLK (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0))
-#define P_SPORT2_AFS (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
-#define P_SPORT2_AD0 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
-#define P_SPORT2_AD1 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
-#define P_SPORT2_ATDV (P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(1))
-#define P_SPORT2_BCLK (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1))
-#define P_SPORT2_BFS (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
-#define P_SPORT2_BD0 (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
-#define P_SPORT2_BD1 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0))
-#define P_SPORT2_BTDV (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2))
-
-/* LINK PORT */
-#define P_LP0_CLK (P_DEFINED | P_IDENT(GPIO_PB0) | P_FUNCT(2))
-#define P_LP0_ACK (P_DEFINED | P_IDENT(GPIO_PB1) | P_FUNCT(2))
-#define P_LP0_D0 (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(2))
-#define P_LP0_D1 (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(2))
-#define P_LP0_D2 (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(2))
-#define P_LP0_D3 (P_DEFINED | P_IDENT(GPIO_PA3) | P_FUNCT(2))
-#define P_LP0_D4 (P_DEFINED | P_IDENT(GPIO_PA4) | P_FUNCT(2))
-#define P_LP0_D5 (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(2))
-#define P_LP0_D6 (P_DEFINED | P_IDENT(GPIO_PA6) | P_FUNCT(2))
-#define P_LP0_D7 (P_DEFINED | P_IDENT(GPIO_PA7) | P_FUNCT(2))
-
-#define P_LP1_CLK (P_DEFINED | P_IDENT(GPIO_PB3) | P_FUNCT(2))
-#define P_LP1_ACK (P_DEFINED | P_IDENT(GPIO_PB2) | P_FUNCT(2))
-#define P_LP1_D0 (P_DEFINED | P_IDENT(GPIO_PA8) | P_FUNCT(2))
-#define P_LP1_D1 (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(2))
-#define P_LP1_D2 (P_DEFINED | P_IDENT(GPIO_PA10) | P_FUNCT(2))
-#define P_LP1_D3 (P_DEFINED | P_IDENT(GPIO_PA11) | P_FUNCT(2))
-#define P_LP1_D4 (P_DEFINED | P_IDENT(GPIO_PA12) | P_FUNCT(2))
-#define P_LP1_D5 (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(2))
-#define P_LP1_D6 (P_DEFINED | P_IDENT(GPIO_PA14) | P_FUNCT(2))
-#define P_LP1_D7 (P_DEFINED | P_IDENT(GPIO_PA15) | P_FUNCT(2))
-
-#define P_LP2_CLK (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(2))
-#define P_LP2_ACK (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(2))
-#define P_LP2_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(2))
-#define P_LP2_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(2))
-#define P_LP2_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(2))
-#define P_LP2_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(2))
-#define P_LP2_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(2))
-#define P_LP2_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(2))
-#define P_LP2_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(2))
-#define P_LP2_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(2))
-
-#define P_LP3_CLK (P_DEFINED | P_IDENT(GPIO_PE9) | P_FUNCT(2))
-#define P_LP3_ACK (P_DEFINED | P_IDENT(GPIO_PE8) | P_FUNCT(2))
-#define P_LP3_D0 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(2))
-#define P_LP3_D1 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(2))
-#define P_LP3_D2 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(2))
-#define P_LP3_D3 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(2))
-#define P_LP3_D4 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(2))
-#define P_LP3_D5 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(2))
-#define P_LP3_D6 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(2))
-#define P_LP3_D7 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(2))
-
-/* TWI */
-#define P_TWI0_SCL (P_DONTCARE)
-#define P_TWI0_SDA (P_DONTCARE)
-#define P_TWI1_SCL (P_DONTCARE)
-#define P_TWI1_SDA (P_DONTCARE)
-
-/* Rotary Encoder */
-#define P_CNT_CZM (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(3))
-#define P_CNT_CUD (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(3))
-#define P_CNT_CDG (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(3))
-
-#endif /* _MACH_PORTMUX_H_ */
+++ /dev/null
-/*
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- *
- * Set up the interrupt priorities
- */
-
-#include <linux/module.h>
-#include <linux/irq.h>
-#include <asm/blackfin.h>
-
-u8 sec_int_priority[] = {
- 255, /* IRQ_SEC_ERR */
- 255, /* IRQ_CGU_EVT */
- 254, /* IRQ_WATCH0 */
- 254, /* IRQ_WATCH1 */
- 253, /* IRQ_L2CTL0_ECC_ERR */
- 253, /* IRQ_L2CTL0_ECC_WARN */
- 253, /* IRQ_C0_DBL_FAULT */
- 253, /* IRQ_C1_DBL_FAULT */
- 252, /* IRQ_C0_HW_ERR */
- 252, /* IRQ_C1_HW_ERR */
- 255, /* IRQ_C0_NMI_L1_PARITY_ERR */
- 255, /* IRQ_C1_NMI_L1_PARITY_ERR */
-
- 50, /* IRQ_TIMER0 */
- 50, /* IRQ_TIMER1 */
- 50, /* IRQ_TIMER2 */
- 50, /* IRQ_TIMER3 */
- 50, /* IRQ_TIMER4 */
- 50, /* IRQ_TIMER5 */
- 50, /* IRQ_TIMER6 */
- 50, /* IRQ_TIMER7 */
- 50, /* IRQ_TIMER_STAT */
- 0, /* IRQ_PINT0 */
- 0, /* IRQ_PINT1 */
- 0, /* IRQ_PINT2 */
- 0, /* IRQ_PINT3 */
- 0, /* IRQ_PINT4 */
- 0, /* IRQ_PINT5 */
- 0, /* IRQ_CNT */
- 50, /* RQ_PWM0_TRIP */
- 50, /* IRQ_PWM0_SYNC */
- 50, /* IRQ_PWM1_TRIP */
- 50, /* IRQ_PWM1_SYNC */
- 0, /* IRQ_TWI0 */
- 0, /* IRQ_TWI1 */
- 10, /* IRQ_SOFT0 */
- 10, /* IRQ_SOFT1 */
- 10, /* IRQ_SOFT2 */
- 10, /* IRQ_SOFT3 */
- 0, /* IRQ_ACM_EVT_MISS */
- 0, /* IRQ_ACM_EVT_COMPLETE */
- 0, /* IRQ_CAN0_RX */
- 0, /* IRQ_CAN0_TX */
- 0, /* IRQ_CAN0_STAT */
- 100, /* IRQ_SPORT0_TX */
- 100, /* IRQ_SPORT0_TX_STAT */
- 100, /* IRQ_SPORT0_RX */
- 100, /* IRQ_SPORT0_RX_STAT */
- 100, /* IRQ_SPORT1_TX */
- 100, /* IRQ_SPORT1_TX_STAT */
- 100, /* IRQ_SPORT1_RX */
- 100, /* IRQ_SPORT1_RX_STAT */
- 100, /* IRQ_SPORT2_TX */
- 100, /* IRQ_SPORT2_TX_STAT */
- 100, /* IRQ_SPORT2_RX */
- 100, /* IRQ_SPORT2_RX_STAT */
- 0, /* IRQ_SPI0_TX */
- 0, /* IRQ_SPI0_RX */
- 0, /* IRQ_SPI0_STAT */
- 0, /* IRQ_SPI1_TX */
- 0, /* IRQ_SPI1_RX */
- 0, /* IRQ_SPI1_STAT */
- 0, /* IRQ_RSI */
- 0, /* IRQ_RSI_INT0 */
- 0, /* IRQ_RSI_INT1 */
- 0, /* DMA11 Data (SDU) */
- 0, /* DMA12 Data (Reserved) */
- 0, /* Reserved */
- 0, /* Reserved */
- 30, /* IRQ_EMAC0_STAT */
- 0, /* EMAC0 Power (Reserved) */
- 30, /* IRQ_EMAC1_STAT */
- 0, /* EMAC1 Power (Reserved) */
- 0, /* IRQ_LP0 */
- 0, /* IRQ_LP0_STAT */
- 0, /* IRQ_LP1 */
- 0, /* IRQ_LP1_STAT */
- 0, /* IRQ_LP2 */
- 0, /* IRQ_LP2_STAT */
- 0, /* IRQ_LP3 */
- 0, /* IRQ_LP3_STAT */
- 0, /* IRQ_UART0_TX */
- 0, /* IRQ_UART0_RX */
- 0, /* IRQ_UART0_STAT */
- 0, /* IRQ_UART1_TX */
- 0, /* IRQ_UART1_RX */
- 0, /* IRQ_UART1_STAT */
- 0, /* IRQ_MDMA0_SRC_CRC0 */
- 0, /* IRQ_MDMA0_DEST_CRC0 */
- 0, /* IRQ_CRC0_DCNTEXP */
- 0, /* IRQ_CRC0_ERR */
- 0, /* IRQ_MDMA1_SRC_CRC1 */
- 0, /* IRQ_MDMA1_DEST_CRC1 */
- 0, /* IRQ_CRC1_DCNTEXP */
- 0, /* IRQ_CRC1_ERR */
- 0, /* IRQ_MDMA2_SRC */
- 0, /* IRQ_MDMA2_DEST */
- 0, /* IRQ_MDMA3_SRC */
- 0, /* IRQ_MDMA3_DEST */
- 120, /* IRQ_EPPI0_CH0 */
- 120, /* IRQ_EPPI0_CH1 */
- 120, /* IRQ_EPPI0_STAT */
- 120, /* IRQ_EPPI2_CH0 */
- 120, /* IRQ_EPPI2_CH1 */
- 120, /* IRQ_EPPI2_STAT */
- 120, /* IRQ_EPPI1_CH0 */
- 120, /* IRQ_EPPI1_CH1 */
- 120, /* IRQ_EPPI1_STAT */
- 120, /* IRQ_PIXC_CH0 */
- 120, /* IRQ_PIXC_CH1 */
- 120, /* IRQ_PIXC_CH2 */
- 120, /* IRQ_PIXC_STAT */
- 120, /* IRQ_PVP_CPDOB */
- 120, /* IRQ_PVP_CPDOC */
- 120, /* IRQ_PVP_CPSTAT */
- 120, /* IRQ_PVP_CPCI */
- 120, /* IRQ_PVP_STAT0 */
- 120, /* IRQ_PVP_MPDO */
- 120, /* IRQ_PVP_MPDI */
- 120, /* IRQ_PVP_MPSTAT */
- 120, /* IRQ_PVP_MPCI */
- 120, /* IRQ_PVP_CPDOA */
- 120, /* IRQ_PVP_STAT1 */
- 0, /* IRQ_USB_STAT */
- 0, /* IRQ_USB_DMA */
- 0, /* IRQ_TRU_INT0 */
- 0, /* IRQ_TRU_INT1 */
- 0, /* IRQ_TRU_INT2 */
- 0, /* IRQ_TRU_INT3 */
- 0, /* IRQ_DMAC0_ERROR */
- 0, /* IRQ_CGU0_ERROR */
- 0, /* Reserved */
- 0, /* IRQ_DPM */
- 0, /* Reserved */
- 0, /* IRQ_SWU0 */
- 0, /* IRQ_SWU1 */
- 0, /* IRQ_SWU2 */
- 0, /* IRQ_SWU3 */
- 0, /* IRQ_SWU4 */
- 0, /* IRQ_SWU4 */
- 0, /* IRQ_SWU6 */
-};
-
+++ /dev/null
-/*
- * Blackfin bf609 power management
- *
- * Copyright 2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2
- */
-
-#include <linux/suspend.h>
-#include <linux/io.h>
-#include <linux/interrupt.h>
-#include <linux/gpio.h>
-#include <linux/irq.h>
-#include <linux/delay.h>
-#include <linux/syscore_ops.h>
-
-#include <asm/dpmc.h>
-#include <asm/pm.h>
-#include <mach/pm.h>
-#include <asm/blackfin.h>
-#include <asm/mem_init.h>
-
-/***********************************************************/
-/* */
-/* Wakeup Actions for DPM_RESTORE */
-/* */
-/***********************************************************/
-#define BITP_ROM_WUA_CHKHDR 24
-#define BITP_ROM_WUA_DDRLOCK 7
-#define BITP_ROM_WUA_DDRDLLEN 6
-#define BITP_ROM_WUA_DDR 5
-#define BITP_ROM_WUA_CGU 4
-#define BITP_ROM_WUA_MEMBOOT 2
-#define BITP_ROM_WUA_EN 1
-
-#define BITM_ROM_WUA_CHKHDR (0xFF000000)
-#define ENUM_ROM_WUA_CHKHDR_AD 0xAD000000
-
-#define BITM_ROM_WUA_DDRLOCK (0x00000080)
-#define BITM_ROM_WUA_DDRDLLEN (0x00000040)
-#define BITM_ROM_WUA_DDR (0x00000020)
-#define BITM_ROM_WUA_CGU (0x00000010)
-#define BITM_ROM_WUA_MEMBOOT (0x00000002)
-#define BITM_ROM_WUA_EN (0x00000001)
-
-/***********************************************************/
-/* */
-/* Syscontrol */
-/* */
-/***********************************************************/
-#define BITP_ROM_SYSCTRL_CGU_LOCKINGEN 28 /* unlocks CGU_CTL register */
-#define BITP_ROM_SYSCTRL_WUA_OVERRIDE 24
-#define BITP_ROM_SYSCTRL_WUA_DDRDLLEN 20 /* Saves the DDR DLL and PADS registers to the DPM registers */
-#define BITP_ROM_SYSCTRL_WUA_DDR 19 /* Saves the DDR registers to the DPM registers */
-#define BITP_ROM_SYSCTRL_WUA_CGU 18 /* Saves the CGU registers into DPM registers */
-#define BITP_ROM_SYSCTRL_WUA_DPMWRITE 17 /* Saves the Syscontrol structure structure contents into DPM registers */
-#define BITP_ROM_SYSCTRL_WUA_EN 16 /* reads current PLL and DDR configuration into structure */
-#define BITP_ROM_SYSCTRL_DDR_WRITE 13 /* writes the DDR registers from Syscontrol structure for wakeup initialization of DDR */
-#define BITP_ROM_SYSCTRL_DDR_READ 12 /* Read the DDR registers into the Syscontrol structure for storing prior to hibernate */
-#define BITP_ROM_SYSCTRL_CGU_AUTODIS 11 /* Disables auto handling of UPDT and ALGN fields */
-#define BITP_ROM_SYSCTRL_CGU_CLKOUTSEL 7 /* access CGU_CLKOUTSEL register */
-#define BITP_ROM_SYSCTRL_CGU_DIV 6 /* access CGU_DIV register */
-#define BITP_ROM_SYSCTRL_CGU_STAT 5 /* access CGU_STAT register */
-#define BITP_ROM_SYSCTRL_CGU_CTL 4 /* access CGU_CTL register */
-#define BITP_ROM_SYSCTRL_CGU_RTNSTAT 2 /* Update structure STAT field upon error */
-#define BITP_ROM_SYSCTRL_WRITE 1 /* write registers */
-#define BITP_ROM_SYSCTRL_READ 0 /* read registers */
-
-#define BITM_ROM_SYSCTRL_CGU_READ (0x00000001) /* Read CGU registers */
-#define BITM_ROM_SYSCTRL_CGU_WRITE (0x00000002) /* Write registers */
-#define BITM_ROM_SYSCTRL_CGU_RTNSTAT (0x00000004) /* Update structure STAT field upon error or after a write operation */
-#define BITM_ROM_SYSCTRL_CGU_CTL (0x00000010) /* Access CGU_CTL register */
-#define BITM_ROM_SYSCTRL_CGU_STAT (0x00000020) /* Access CGU_STAT register */
-#define BITM_ROM_SYSCTRL_CGU_DIV (0x00000040) /* Access CGU_DIV register */
-#define BITM_ROM_SYSCTRL_CGU_CLKOUTSEL (0x00000080) /* Access CGU_CLKOUTSEL register */
-#define BITM_ROM_SYSCTRL_CGU_AUTODIS (0x00000800) /* Disables auto handling of UPDT and ALGN fields */
-#define BITM_ROM_SYSCTRL_DDR_READ (0x00001000) /* Reads the contents of the DDR registers and stores them into the structure */
-#define BITM_ROM_SYSCTRL_DDR_WRITE (0x00002000) /* Writes the DDR registers from the structure, only really intented for wakeup functionality and not for full DDR configuration */
-#define BITM_ROM_SYSCTRL_WUA_EN (0x00010000) /* Wakeup entry or exit opertation enable */
-#define BITM_ROM_SYSCTRL_WUA_DPMWRITE (0x00020000) /* When set indicates a restore of the PLL and DDR is to be performed otherwise a save is required */
-#define BITM_ROM_SYSCTRL_WUA_CGU (0x00040000) /* Only applicable for a PLL and DDR save operation to the DPM, saves the current settings if cleared or the contents of the structure if set */
-#define BITM_ROM_SYSCTRL_WUA_DDR (0x00080000) /* Only applicable for a PLL and DDR save operation to the DPM, saves the current settings if cleared or the contents of the structure if set */
-#define BITM_ROM_SYSCTRL_WUA_DDRDLLEN (0x00100000) /* Enables saving/restoring of the DDR DLLCTL register */
-#define BITM_ROM_SYSCTRL_WUA_OVERRIDE (0x01000000)
-#define BITM_ROM_SYSCTRL_CGU_LOCKINGEN (0x10000000) /* Unlocks the CGU_CTL register */
-
-
-/* Structures for the syscontrol() function */
-struct STRUCT_ROM_SYSCTRL {
- uint32_t ulCGU_CTL;
- uint32_t ulCGU_STAT;
- uint32_t ulCGU_DIV;
- uint32_t ulCGU_CLKOUTSEL;
- uint32_t ulWUA_Flags;
- uint32_t ulWUA_BootAddr;
- uint32_t ulWUA_User;
- uint32_t ulDDR_CTL;
- uint32_t ulDDR_CFG;
- uint32_t ulDDR_TR0;
- uint32_t ulDDR_TR1;
- uint32_t ulDDR_TR2;
- uint32_t ulDDR_MR;
- uint32_t ulDDR_EMR1;
- uint32_t ulDDR_EMR2;
- uint32_t ulDDR_PADCTL;
- uint32_t ulDDR_DLLCTL;
- uint32_t ulReserved;
-};
-
-struct bfin_pm_data {
- uint32_t magic;
- uint32_t resume_addr;
- uint32_t sp;
-};
-
-struct bfin_pm_data bf609_pm_data;
-
-struct STRUCT_ROM_SYSCTRL configvalues;
-uint32_t dactionflags;
-
-#define FUNC_ROM_SYSCONTROL 0xC8000080
-__attribute__((l1_data))
-static uint32_t (* const bfrom_SysControl)(uint32_t action_flags, struct STRUCT_ROM_SYSCTRL *settings, void *reserved) = (void *)FUNC_ROM_SYSCONTROL;
-
-__attribute__((l1_text))
-void bfin_cpu_suspend(void)
-{
- __asm__ __volatile__( \
- ".align 8;" \
- "idle;" \
- : : \
- );
-}
-
-__attribute__((l1_text))
-void bf609_ddr_sr(void)
-{
- dmc_enter_self_refresh();
-}
-
-__attribute__((l1_text))
-void bf609_ddr_sr_exit(void)
-{
- dmc_exit_self_refresh();
-
- /* After wake up from deep sleep and exit DDR from self refress mode,
- * should wait till CGU PLL is locked.
- */
- while (bfin_read32(CGU0_STAT) & CLKSALGN)
- continue;
-}
-
-__attribute__((l1_text))
-void bf609_resume_ccbuf(void)
-{
- bfin_write32(DPM0_CCBF_EN, 3);
- bfin_write32(DPM0_CTL, 2);
-
- while ((bfin_read32(DPM0_STAT) & 0xf) != 1);
-}
-
-__attribute__((l1_text))
-void bfin_hibernate_syscontrol(void)
-{
- configvalues.ulWUA_Flags = (0xAD000000 | BITM_ROM_WUA_EN
- | BITM_ROM_WUA_CGU | BITM_ROM_WUA_DDR | BITM_ROM_WUA_DDRDLLEN);
-
- dactionflags = (BITM_ROM_SYSCTRL_WUA_EN
- | BITM_ROM_SYSCTRL_WUA_DPMWRITE | BITM_ROM_SYSCTRL_WUA_CGU
- | BITM_ROM_SYSCTRL_WUA_DDR | BITM_ROM_SYSCTRL_WUA_DDRDLLEN);
-
- bfrom_SysControl(dactionflags, &configvalues, NULL);
-
- bfin_write32(DPM0_RESTORE5, bfin_read32(DPM0_RESTORE5) | 4);
-}
-
-asmlinkage void enter_deepsleep(void);
-
-__attribute__((l1_text))
-void bfin_deepsleep(unsigned long mask, unsigned long pol_mask)
-{
- bfin_write32(DPM0_WAKE_EN, mask);
- bfin_write32(DPM0_WAKE_POL, pol_mask);
- SSYNC();
- enter_deepsleep();
-}
-
-void bfin_hibernate(unsigned long mask, unsigned long pol_mask)
-{
- bfin_write32(DPM0_WAKE_EN, mask);
- bfin_write32(DPM0_WAKE_POL, pol_mask);
- bfin_write32(DPM0_PGCNTR, 0x0000FFFF);
- bfin_write32(DPM0_HIB_DIS, 0xFFFF);
-
- bf609_hibernate();
-}
-
-void bf609_cpu_pm_enter(suspend_state_t state)
-{
- int error;
- unsigned long wakeup = 0;
- unsigned long wakeup_pol = 0;
-
-#ifdef CONFIG_PM_BFIN_WAKE_PA15
- wakeup |= PA15WE;
-# if CONFIG_PM_BFIN_WAKE_PA15_POL
- wakeup_pol |= PA15WE;
-# endif
-#endif
-
-#ifdef CONFIG_PM_BFIN_WAKE_PB15
- wakeup |= PB15WE;
-# if CONFIG_PM_BFIN_WAKE_PB15_POL
- wakeup_pol |= PB15WE;
-# endif
-#endif
-
-#ifdef CONFIG_PM_BFIN_WAKE_PC15
- wakeup |= PC15WE;
-# if CONFIG_PM_BFIN_WAKE_PC15_POL
- wakeup_pol |= PC15WE;
-# endif
-#endif
-
-#ifdef CONFIG_PM_BFIN_WAKE_PD06
- wakeup |= PD06WE;
-# if CONFIG_PM_BFIN_WAKE_PD06_POL
- wakeup_pol |= PD06WE;
-# endif
-#endif
-
-#ifdef CONFIG_PM_BFIN_WAKE_PE12
- wakeup |= PE12WE;
-# if CONFIG_PM_BFIN_WAKE_PE12_POL
- wakeup_pol |= PE12WE;
-# endif
-#endif
-
-#ifdef CONFIG_PM_BFIN_WAKE_PG04
- wakeup |= PG04WE;
-# if CONFIG_PM_BFIN_WAKE_PG04_POL
- wakeup_pol |= PG04WE;
-# endif
-#endif
-
-#ifdef CONFIG_PM_BFIN_WAKE_PG13
- wakeup |= PG13WE;
-# if CONFIG_PM_BFIN_WAKE_PG13_POL
- wakeup_pol |= PG13WE;
-# endif
-#endif
-
-#ifdef CONFIG_PM_BFIN_WAKE_USB
- wakeup |= USBWE;
-# if CONFIG_PM_BFIN_WAKE_USB_POL
- wakeup_pol |= USBWE;
-# endif
-#endif
-
- error = irq_set_irq_wake(255, 1);
- if(error < 0)
- printk(KERN_DEBUG "Unable to get irq wake\n");
- error = irq_set_irq_wake(231, 1);
- if (error < 0)
- printk(KERN_DEBUG "Unable to get irq wake\n");
-
- if (state == PM_SUSPEND_STANDBY)
- bfin_deepsleep(wakeup, wakeup_pol);
- else {
- bfin_hibernate(wakeup, wakeup_pol);
- }
-
-}
-
-int bf609_cpu_pm_prepare(void)
-{
- return 0;
-}
-
-void bf609_cpu_pm_finish(void)
-{
-
-}
-
-static struct bfin_cpu_pm_fns bf609_cpu_pm = {
- .enter = bf609_cpu_pm_enter,
- .prepare = bf609_cpu_pm_prepare,
- .finish = bf609_cpu_pm_finish,
-};
-
-#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
-static int smc_pm_syscore_suspend(void)
-{
- bf609_nor_flash_exit(NULL);
- return 0;
-}
-
-static void smc_pm_syscore_resume(void)
-{
- bf609_nor_flash_init(NULL);
-}
-
-static struct syscore_ops smc_pm_syscore_ops = {
- .suspend = smc_pm_syscore_suspend,
- .resume = smc_pm_syscore_resume,
-};
-#endif
-
-static irqreturn_t test_isr(int irq, void *dev_id)
-{
- printk(KERN_DEBUG "gpio irq %d\n", irq);
- if (irq == 231)
- bfin_sec_raise_irq(BFIN_SYSIRQ(IRQ_SOFT1));
- return IRQ_HANDLED;
-}
-
-static irqreturn_t dpm0_isr(int irq, void *dev_id)
-{
- bfin_write32(DPM0_WAKE_STAT, bfin_read32(DPM0_WAKE_STAT));
- bfin_write32(CGU0_STAT, bfin_read32(CGU0_STAT));
- return IRQ_HANDLED;
-}
-
-static int __init bf609_init_pm(void)
-{
- int irq;
- int error;
-
-#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
- register_syscore_ops(&smc_pm_syscore_ops);
-#endif
-
-#ifdef CONFIG_PM_BFIN_WAKE_PE12
- irq = gpio_to_irq(GPIO_PE12);
- if (irq < 0) {
- error = irq;
- printk(KERN_DEBUG "Unable to get irq number for GPIO %d, error %d\n",
- GPIO_PE12, error);
- }
-
- error = request_irq(irq, test_isr, IRQF_TRIGGER_RISING | IRQF_NO_SUSPEND
- | IRQF_FORCE_RESUME, "gpiope12", NULL);
- if(error < 0)
- printk(KERN_DEBUG "Unable to get irq\n");
-#endif
-
- error = request_irq(IRQ_CGU_EVT, dpm0_isr, IRQF_NO_SUSPEND |
- IRQF_FORCE_RESUME, "cgu0 event", NULL);
- if(error < 0)
- printk(KERN_DEBUG "Unable to get irq\n");
-
- error = request_irq(IRQ_DPM, dpm0_isr, IRQF_NO_SUSPEND |
- IRQF_FORCE_RESUME, "dpm0 event", NULL);
- if (error < 0)
- printk(KERN_DEBUG "Unable to get irq\n");
-
- bfin_cpu_pm = &bf609_cpu_pm;
- return 0;
-}
-
-late_initcall(bf609_init_pm);
+++ /dev/null
-/*
- * arch/blackfin/mach-common/scb-init.c - reprogram system cross bar priority
- *
- * Copyright 2012 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <asm/blackfin.h>
-#include <asm/scb.h>
-
-struct scb_mi_prio scb_data[] = {
-#ifdef CONFIG_SCB0_MI0
- { REG_SCB0_ARBR0, REG_SCB0_ARBW0, 32, {
- CONFIG_SCB0_MI0_SLOT0,
- CONFIG_SCB0_MI0_SLOT1,
- CONFIG_SCB0_MI0_SLOT2,
- CONFIG_SCB0_MI0_SLOT3,
- CONFIG_SCB0_MI0_SLOT4,
- CONFIG_SCB0_MI0_SLOT5,
- CONFIG_SCB0_MI0_SLOT6,
- CONFIG_SCB0_MI0_SLOT7,
- CONFIG_SCB0_MI0_SLOT8,
- CONFIG_SCB0_MI0_SLOT9,
- CONFIG_SCB0_MI0_SLOT10,
- CONFIG_SCB0_MI0_SLOT11,
- CONFIG_SCB0_MI0_SLOT12,
- CONFIG_SCB0_MI0_SLOT13,
- CONFIG_SCB0_MI0_SLOT14,
- CONFIG_SCB0_MI0_SLOT15,
- CONFIG_SCB0_MI0_SLOT16,
- CONFIG_SCB0_MI0_SLOT17,
- CONFIG_SCB0_MI0_SLOT18,
- CONFIG_SCB0_MI0_SLOT19,
- CONFIG_SCB0_MI0_SLOT20,
- CONFIG_SCB0_MI0_SLOT21,
- CONFIG_SCB0_MI0_SLOT22,
- CONFIG_SCB0_MI0_SLOT23,
- CONFIG_SCB0_MI0_SLOT24,
- CONFIG_SCB0_MI0_SLOT25,
- CONFIG_SCB0_MI0_SLOT26,
- CONFIG_SCB0_MI0_SLOT27,
- CONFIG_SCB0_MI0_SLOT28,
- CONFIG_SCB0_MI0_SLOT29,
- CONFIG_SCB0_MI0_SLOT30,
- CONFIG_SCB0_MI0_SLOT31
- },
- },
-#endif
-#ifdef CONFIG_SCB0_MI1
- { REG_SCB0_ARBR1, REG_SCB0_ARBW1, 32, {
- CONFIG_SCB0_MI1_SLOT0,
- CONFIG_SCB0_MI1_SLOT1,
- CONFIG_SCB0_MI1_SLOT2,
- CONFIG_SCB0_MI1_SLOT3,
- CONFIG_SCB0_MI1_SLOT4,
- CONFIG_SCB0_MI1_SLOT5,
- CONFIG_SCB0_MI1_SLOT6,
- CONFIG_SCB0_MI1_SLOT7,
- CONFIG_SCB0_MI1_SLOT8,
- CONFIG_SCB0_MI1_SLOT9,
- CONFIG_SCB0_MI1_SLOT10,
- CONFIG_SCB0_MI1_SLOT11,
- CONFIG_SCB0_MI1_SLOT12,
- CONFIG_SCB0_MI1_SLOT13,
- CONFIG_SCB0_MI1_SLOT14,
- CONFIG_SCB0_MI1_SLOT15,
- CONFIG_SCB0_MI1_SLOT16,
- CONFIG_SCB0_MI1_SLOT17,
- CONFIG_SCB0_MI1_SLOT18,
- CONFIG_SCB0_MI1_SLOT19,
- CONFIG_SCB0_MI1_SLOT20,
- CONFIG_SCB0_MI1_SLOT21,
- CONFIG_SCB0_MI1_SLOT22,
- CONFIG_SCB0_MI1_SLOT23,
- CONFIG_SCB0_MI1_SLOT24,
- CONFIG_SCB0_MI1_SLOT25,
- CONFIG_SCB0_MI1_SLOT26,
- CONFIG_SCB0_MI1_SLOT27,
- CONFIG_SCB0_MI1_SLOT28,
- CONFIG_SCB0_MI1_SLOT29,
- CONFIG_SCB0_MI1_SLOT30,
- CONFIG_SCB0_MI1_SLOT31
- },
- },
-#endif
-#ifdef CONFIG_SCB0_MI2
- { REG_SCB0_ARBR2, REG_SCB0_ARBW2, 32, {
- CONFIG_SCB0_MI2_SLOT0,
- CONFIG_SCB0_MI2_SLOT1,
- CONFIG_SCB0_MI2_SLOT2,
- CONFIG_SCB0_MI2_SLOT3,
- CONFIG_SCB0_MI2_SLOT4,
- CONFIG_SCB0_MI2_SLOT5,
- CONFIG_SCB0_MI2_SLOT6,
- CONFIG_SCB0_MI2_SLOT7,
- CONFIG_SCB0_MI2_SLOT8,
- CONFIG_SCB0_MI2_SLOT9,
- CONFIG_SCB0_MI2_SLOT10,
- CONFIG_SCB0_MI2_SLOT11,
- CONFIG_SCB0_MI2_SLOT12,
- CONFIG_SCB0_MI2_SLOT13,
- CONFIG_SCB0_MI2_SLOT14,
- CONFIG_SCB0_MI2_SLOT15,
- CONFIG_SCB0_MI2_SLOT16,
- CONFIG_SCB0_MI2_SLOT17,
- CONFIG_SCB0_MI2_SLOT18,
- CONFIG_SCB0_MI2_SLOT19,
- CONFIG_SCB0_MI2_SLOT20,
- CONFIG_SCB0_MI2_SLOT21,
- CONFIG_SCB0_MI2_SLOT22,
- CONFIG_SCB0_MI2_SLOT23,
- CONFIG_SCB0_MI2_SLOT24,
- CONFIG_SCB0_MI2_SLOT25,
- CONFIG_SCB0_MI2_SLOT26,
- CONFIG_SCB0_MI2_SLOT27,
- CONFIG_SCB0_MI2_SLOT28,
- CONFIG_SCB0_MI2_SLOT29,
- CONFIG_SCB0_MI2_SLOT30,
- CONFIG_SCB0_MI2_SLOT31
- },
- },
-#endif
-#ifdef CONFIG_SCB0_MI3
- { REG_SCB0_ARBR3, REG_SCB0_ARBW3, 32, {
- CONFIG_SCB0_MI3_SLOT0,
- CONFIG_SCB0_MI3_SLOT1,
- CONFIG_SCB0_MI3_SLOT2,
- CONFIG_SCB0_MI3_SLOT3,
- CONFIG_SCB0_MI3_SLOT4,
- CONFIG_SCB0_MI3_SLOT5,
- CONFIG_SCB0_MI3_SLOT6,
- CONFIG_SCB0_MI3_SLOT7,
- CONFIG_SCB0_MI3_SLOT8,
- CONFIG_SCB0_MI3_SLOT9,
- CONFIG_SCB0_MI3_SLOT10,
- CONFIG_SCB0_MI3_SLOT11,
- CONFIG_SCB0_MI3_SLOT12,
- CONFIG_SCB0_MI3_SLOT13,
- CONFIG_SCB0_MI3_SLOT14,
- CONFIG_SCB0_MI3_SLOT15,
- CONFIG_SCB0_MI3_SLOT16,
- CONFIG_SCB0_MI3_SLOT17,
- CONFIG_SCB0_MI3_SLOT18,
- CONFIG_SCB0_MI3_SLOT19,
- CONFIG_SCB0_MI3_SLOT20,
- CONFIG_SCB0_MI3_SLOT21,
- CONFIG_SCB0_MI3_SLOT22,
- CONFIG_SCB0_MI3_SLOT23,
- CONFIG_SCB0_MI3_SLOT24,
- CONFIG_SCB0_MI3_SLOT25,
- CONFIG_SCB0_MI3_SLOT26,
- CONFIG_SCB0_MI3_SLOT27,
- CONFIG_SCB0_MI3_SLOT28,
- CONFIG_SCB0_MI3_SLOT29,
- CONFIG_SCB0_MI3_SLOT30,
- CONFIG_SCB0_MI3_SLOT31
- },
- },
-#endif
-#ifdef CONFIG_SCB0_MI4
- { REG_SCB0_ARBR4, REG_SCB4_ARBW0, 32, {
- CONFIG_SCB0_MI4_SLOT0,
- CONFIG_SCB0_MI4_SLOT1,
- CONFIG_SCB0_MI4_SLOT2,
- CONFIG_SCB0_MI4_SLOT3,
- CONFIG_SCB0_MI4_SLOT4,
- CONFIG_SCB0_MI4_SLOT5,
- CONFIG_SCB0_MI4_SLOT6,
- CONFIG_SCB0_MI4_SLOT7,
- CONFIG_SCB0_MI4_SLOT8,
- CONFIG_SCB0_MI4_SLOT9,
- CONFIG_SCB0_MI4_SLOT10,
- CONFIG_SCB0_MI4_SLOT11,
- CONFIG_SCB0_MI4_SLOT12,
- CONFIG_SCB0_MI4_SLOT13,
- CONFIG_SCB0_MI4_SLOT14,
- CONFIG_SCB0_MI4_SLOT15,
- CONFIG_SCB0_MI4_SLOT16,
- CONFIG_SCB0_MI4_SLOT17,
- CONFIG_SCB0_MI4_SLOT18,
- CONFIG_SCB0_MI4_SLOT19,
- CONFIG_SCB0_MI4_SLOT20,
- CONFIG_SCB0_MI4_SLOT21,
- CONFIG_SCB0_MI4_SLOT22,
- CONFIG_SCB0_MI4_SLOT23,
- CONFIG_SCB0_MI4_SLOT24,
- CONFIG_SCB0_MI4_SLOT25,
- CONFIG_SCB0_MI4_SLOT26,
- CONFIG_SCB0_MI4_SLOT27,
- CONFIG_SCB0_MI4_SLOT28,
- CONFIG_SCB0_MI4_SLOT29,
- CONFIG_SCB0_MI4_SLOT30,
- CONFIG_SCB0_MI4_SLOT31
- },
- },
-#endif
-#ifdef CONFIG_SCB0_MI5
- { REG_SCB0_ARBR5, REG_SCB0_ARBW5, 16, {
- CONFIG_SCB0_MI5_SLOT0,
- CONFIG_SCB0_MI5_SLOT1,
- CONFIG_SCB0_MI5_SLOT2,
- CONFIG_SCB0_MI5_SLOT3,
- CONFIG_SCB0_MI5_SLOT4,
- CONFIG_SCB0_MI5_SLOT5,
- CONFIG_SCB0_MI5_SLOT6,
- CONFIG_SCB0_MI5_SLOT7,
- CONFIG_SCB0_MI5_SLOT8,
- CONFIG_SCB0_MI5_SLOT9,
- CONFIG_SCB0_MI5_SLOT10,
- CONFIG_SCB0_MI5_SLOT11,
- CONFIG_SCB0_MI5_SLOT12,
- CONFIG_SCB0_MI5_SLOT13,
- CONFIG_SCB0_MI5_SLOT14,
- CONFIG_SCB0_MI5_SLOT15
- },
- },
-#endif
-#ifdef CONFIG_SCB1_MI0
- { REG_SCB1_ARBR0, REG_SCB1_ARBW0, 20, {
- CONFIG_SCB1_MI0_SLOT0,
- CONFIG_SCB1_MI0_SLOT1,
- CONFIG_SCB1_MI0_SLOT2,
- CONFIG_SCB1_MI0_SLOT3,
- CONFIG_SCB1_MI0_SLOT4,
- CONFIG_SCB1_MI0_SLOT5,
- CONFIG_SCB1_MI0_SLOT6,
- CONFIG_SCB1_MI0_SLOT7,
- CONFIG_SCB1_MI0_SLOT8,
- CONFIG_SCB1_MI0_SLOT9,
- CONFIG_SCB1_MI0_SLOT10,
- CONFIG_SCB1_MI0_SLOT11,
- CONFIG_SCB1_MI0_SLOT12,
- CONFIG_SCB1_MI0_SLOT13,
- CONFIG_SCB1_MI0_SLOT14,
- CONFIG_SCB1_MI0_SLOT15,
- CONFIG_SCB1_MI0_SLOT16,
- CONFIG_SCB1_MI0_SLOT17,
- CONFIG_SCB1_MI0_SLOT18,
- CONFIG_SCB1_MI0_SLOT19
- },
- },
-#endif
-#ifdef CONFIG_SCB2_MI0
- { REG_SCB2_ARBR0, REG_SCB2_ARBW0, 10, {
- CONFIG_SCB2_MI0_SLOT0,
- CONFIG_SCB2_MI0_SLOT1,
- CONFIG_SCB2_MI0_SLOT2,
- CONFIG_SCB2_MI0_SLOT3,
- CONFIG_SCB2_MI0_SLOT4,
- CONFIG_SCB2_MI0_SLOT5,
- CONFIG_SCB2_MI0_SLOT6,
- CONFIG_SCB2_MI0_SLOT7,
- CONFIG_SCB2_MI0_SLOT8,
- CONFIG_SCB2_MI0_SLOT9
- },
- },
-#endif
-#ifdef CONFIG_SCB3_MI0
- { REG_SCB3_ARBR0, REG_SCB3_ARBW0, 16, {
- CONFIG_SCB3_MI0_SLOT0,
- CONFIG_SCB3_MI0_SLOT1,
- CONFIG_SCB3_MI0_SLOT2,
- CONFIG_SCB3_MI0_SLOT3,
- CONFIG_SCB3_MI0_SLOT4,
- CONFIG_SCB3_MI0_SLOT5,
- CONFIG_SCB3_MI0_SLOT6,
- CONFIG_SCB3_MI0_SLOT7,
- CONFIG_SCB3_MI0_SLOT8,
- CONFIG_SCB3_MI0_SLOT9,
- CONFIG_SCB3_MI0_SLOT10,
- CONFIG_SCB3_MI0_SLOT11,
- CONFIG_SCB3_MI0_SLOT12,
- CONFIG_SCB3_MI0_SLOT13,
- CONFIG_SCB3_MI0_SLOT14,
- CONFIG_SCB3_MI0_SLOT15
- },
- },
-#endif
-#ifdef CONFIG_SCB4_MI0
- { REG_SCB4_ARBR0, REG_SCB4_ARBW0, 16, {
- CONFIG_SCB4_MI0_SLOT0,
- CONFIG_SCB4_MI0_SLOT1,
- CONFIG_SCB4_MI0_SLOT2,
- CONFIG_SCB4_MI0_SLOT3,
- CONFIG_SCB4_MI0_SLOT4,
- CONFIG_SCB4_MI0_SLOT5,
- CONFIG_SCB4_MI0_SLOT6,
- CONFIG_SCB4_MI0_SLOT7,
- CONFIG_SCB4_MI0_SLOT8,
- CONFIG_SCB4_MI0_SLOT9,
- CONFIG_SCB4_MI0_SLOT10,
- CONFIG_SCB4_MI0_SLOT11,
- CONFIG_SCB4_MI0_SLOT12,
- CONFIG_SCB4_MI0_SLOT13,
- CONFIG_SCB4_MI0_SLOT14,
- CONFIG_SCB4_MI0_SLOT15
- },
- },
-#endif
-#ifdef CONFIG_SCB5_MI0
- { REG_SCB5_ARBR0, REG_SCB5_ARBW0, 8, {
- CONFIG_SCB5_MI0_SLOT0,
- CONFIG_SCB5_MI0_SLOT1,
- CONFIG_SCB5_MI0_SLOT2,
- CONFIG_SCB5_MI0_SLOT3,
- CONFIG_SCB5_MI0_SLOT4,
- CONFIG_SCB5_MI0_SLOT5,
- CONFIG_SCB5_MI0_SLOT6,
- CONFIG_SCB5_MI0_SLOT7
- },
- },
-#endif
-#ifdef CONFIG_SCB6_MI0
- { REG_SCB6_ARBR0, REG_SCB6_ARBW0, 4, {
- CONFIG_SCB6_MI0_SLOT0,
- CONFIG_SCB6_MI0_SLOT1,
- CONFIG_SCB6_MI0_SLOT2,
- CONFIG_SCB6_MI0_SLOT3
- },
- },
-#endif
-#ifdef CONFIG_SCB7_MI0
- { REG_SCB7_ARBR0, REG_SCB7_ARBW0, 6, {
- CONFIG_SCB7_MI0_SLOT0,
- CONFIG_SCB7_MI0_SLOT1,
- CONFIG_SCB7_MI0_SLOT2,
- CONFIG_SCB7_MI0_SLOT3,
- CONFIG_SCB7_MI0_SLOT4,
- CONFIG_SCB7_MI0_SLOT5
- },
- },
-#endif
-#ifdef CONFIG_SCB8_MI0
- { REG_SCB8_ARBR0, REG_SCB8_ARBW0, 8, {
- CONFIG_SCB8_MI0_SLOT0,
- CONFIG_SCB8_MI0_SLOT1,
- CONFIG_SCB8_MI0_SLOT2,
- CONFIG_SCB8_MI0_SLOT3,
- CONFIG_SCB8_MI0_SLOT4,
- CONFIG_SCB8_MI0_SLOT5,
- CONFIG_SCB8_MI0_SLOT6,
- CONFIG_SCB8_MI0_SLOT7
- },
- },
-#endif
-#ifdef CONFIG_SCB9_MI0
- { REG_SCB9_ARBR0, REG_SCB9_ARBW0, 10, {
- CONFIG_SCB9_MI0_SLOT0,
- CONFIG_SCB9_MI0_SLOT1,
- CONFIG_SCB9_MI0_SLOT2,
- CONFIG_SCB9_MI0_SLOT3,
- CONFIG_SCB9_MI0_SLOT4,
- CONFIG_SCB9_MI0_SLOT5,
- CONFIG_SCB9_MI0_SLOT6,
- CONFIG_SCB9_MI0_SLOT7,
- CONFIG_SCB9_MI0_SLOT8,
- CONFIG_SCB9_MI0_SLOT9
- },
- },
-#endif
- { 0, }
-};
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0
-#
-# arch/blackfin/mach-common/Makefile
-#
-
-obj-y := \
- cache.o cache-c.o entry.o head.o \
- interrupt.o arch_checks.o ints-priority.o
-
-obj-$(CONFIG_PM) += pm.o
-ifneq ($(CONFIG_BF60x),y)
-obj-$(CONFIG_PM) += dpmc_modes.o
-endif
-obj-$(CONFIG_SCB_PRIORITY) += scb-init.o
-obj-$(CONFIG_CPU_VOLTAGE) += dpmc.o
-obj-$(CONFIG_SMP) += smp.o
-obj-$(CONFIG_BFIN_KERNEL_CLOCK) += clocks-init.o
+++ /dev/null
-/*
- * Do some checking to make sure things are OK
- *
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <asm/fixed_code.h>
-#include <mach/anomaly.h>
-#include <asm/clocks.h>
-
-#ifdef CONFIG_BFIN_KERNEL_CLOCK
-
-# if (CONFIG_VCO_HZ > CONFIG_MAX_VCO_HZ)
-# error "VCO selected is more than maximum value. Please change the VCO multipler"
-# endif
-
-# if (CONFIG_SCLK_HZ > CONFIG_MAX_SCLK_HZ)
-# error "Sclk value selected is more than maximum. Please select a proper value for SCLK multiplier"
-# endif
-
-# if (CONFIG_SCLK_HZ < CONFIG_MIN_SCLK_HZ)
-# error "Sclk value selected is less than minimum. Please select a proper value for SCLK multiplier"
-# endif
-
-# if (ANOMALY_05000273) && (CONFIG_SCLK_HZ * 2 > CONFIG_CCLK_HZ)
-# error "ANOMALY 05000273, please make sure CCLK is at least 2x SCLK"
-# endif
-
-# if (CONFIG_SCLK_HZ > CONFIG_CCLK_HZ) && (CONFIG_SCLK_HZ != CONFIG_CLKIN_HZ) && (CONFIG_CCLK_HZ != CONFIG_CLKIN_HZ)
-# error "Please select sclk less than cclk"
-# endif
-
-#endif /* CONFIG_BFIN_KERNEL_CLOCK */
-
-#if CONFIG_BOOT_LOAD < FIXED_CODE_END
-# error "The kernel load address must be after the fixed code section"
-#endif
-
-#if (CONFIG_BOOT_LOAD & 0x3)
-# error "The kernel load address must be 4 byte aligned"
-#endif
-
-/* The entire kernel must be able to make a 24bit pcrel call to start of L1 */
-#if ((0xffffffff - L1_CODE_START + 1) + CONFIG_BOOT_LOAD) > 0x1000000
-# error "The kernel load address is too high; keep it below 10meg for safety"
-#endif
-
-#if ANOMALY_05000263 && defined(CONFIG_MPU)
-# error the MPU will not function safely while Anomaly 05000263 applies
-#endif
-
-#if ANOMALY_05000448
-# error You are using a part with anomaly 05000448, this issue causes random memory read/write failures - that means random crashes.
-#endif
-
-/* if 220 exists, can not set External Memory WB and L2 not_cached, either External Memory not_cached and L2 WB */
-#if ANOMALY_05000220 && \
- (defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK))
-# error "Anomaly 05000220 does not allow you to use Write Back cache with L2 or External Memory"
-#endif
-
-#if ANOMALY_05000491 && !defined(CONFIG_ICACHE_FLUSH_L1)
-# error You need IFLUSH in L1 inst while Anomaly 05000491 applies
-#endif
+++ /dev/null
-/*
- * Blackfin cache control code (simpler control-style functions)
- *
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <asm/blackfin.h>
-#include <asm/cplbinit.h>
-
-/* Invalidate the Entire Data cache by
- * clearing DMC[1:0] bits
- */
-void blackfin_invalidate_entire_dcache(void)
-{
- u32 dmem = bfin_read_DMEM_CONTROL();
- bfin_write_DMEM_CONTROL(dmem & ~0xc);
- SSYNC();
- bfin_write_DMEM_CONTROL(dmem);
- SSYNC();
-}
-
-/* Invalidate the Entire Instruction cache by
- * clearing IMC bit
- */
-void blackfin_invalidate_entire_icache(void)
-{
- u32 imem = bfin_read_IMEM_CONTROL();
- bfin_write_IMEM_CONTROL(imem & ~0x4);
- SSYNC();
- bfin_write_IMEM_CONTROL(imem);
- SSYNC();
-}
-
-#if defined(CONFIG_BFIN_ICACHE) || defined(CONFIG_BFIN_DCACHE)
-
-static void
-bfin_cache_init(struct cplb_entry *cplb_tbl, unsigned long cplb_addr,
- unsigned long cplb_data, unsigned long mem_control,
- unsigned long mem_mask)
-{
- int i;
-#ifdef CONFIG_L1_PARITY_CHECK
- u32 ctrl;
-
- if (cplb_addr == DCPLB_ADDR0) {
- ctrl = bfin_read32(mem_control) | (1 << RDCHK);
- CSYNC();
- bfin_write32(mem_control, ctrl);
- SSYNC();
- }
-#endif
-
- for (i = 0; i < MAX_CPLBS; i++) {
- bfin_write32(cplb_addr + i * 4, cplb_tbl[i].addr);
- bfin_write32(cplb_data + i * 4, cplb_tbl[i].data);
- }
-
- _enable_cplb(mem_control, mem_mask);
-}
-
-#ifdef CONFIG_BFIN_ICACHE
-void bfin_icache_init(struct cplb_entry *icplb_tbl)
-{
- bfin_cache_init(icplb_tbl, ICPLB_ADDR0, ICPLB_DATA0, IMEM_CONTROL,
- (IMC | ENICPLB));
-}
-#endif
-
-#ifdef CONFIG_BFIN_DCACHE
-void bfin_dcache_init(struct cplb_entry *dcplb_tbl)
-{
- /*
- * Anomaly notes:
- * 05000287 - We implement workaround #2 - Change the DMEM_CONTROL
- * register, so that the port preferences for DAG0 and DAG1 are set
- * to port B
- */
- bfin_cache_init(dcplb_tbl, DCPLB_ADDR0, DCPLB_DATA0, DMEM_CONTROL,
- (DMEM_CNTR | PORT_PREF0 | (ANOMALY_05000287 ? PORT_PREF1 : 0)));
-}
-#endif
-
-#endif
+++ /dev/null
-/*
- * Blackfin cache control code
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/linkage.h>
-#include <asm/blackfin.h>
-#include <asm/cache.h>
-#include <asm/page.h>
-
-/* 05000443 - IFLUSH cannot be last instruction in hardware loop */
-#if ANOMALY_05000443
-# define BROK_FLUSH_INST "IFLUSH"
-#else
-# define BROK_FLUSH_INST "no anomaly! yeah!"
-#endif
-
-/* Since all L1 caches work the same way, we use the same method for flushing
- * them. Only the actual flush instruction differs. We write this in asm as
- * GCC can be hard to coax into writing nice hardware loops.
- *
- * Also, we assume the following register setup:
- * R0 = start address
- * R1 = end address
- */
-.macro do_flush flushins:req label
-
- R2 = -L1_CACHE_BYTES;
-
- /* start = (start & -L1_CACHE_BYTES) */
- R0 = R0 & R2;
-
- /* end = ((end - 1) & -L1_CACHE_BYTES) + L1_CACHE_BYTES; */
- R1 += -1;
- R1 = R1 & R2;
- R1 += L1_CACHE_BYTES;
-
- /* count = (end - start) >> L1_CACHE_SHIFT */
- R2 = R1 - R0;
- R2 >>= L1_CACHE_SHIFT;
- P1 = R2;
-
-.ifnb \label
-\label :
-.endif
- P0 = R0;
-
- LSETUP (1f, 2f) LC1 = P1;
-1:
-.ifeqs "\flushins", BROK_FLUSH_INST
- \flushins [P0++];
- nop;
- nop;
-2: nop;
-.else
-2: \flushins [P0++];
-.endif
-
- RTS;
-.endm
-
-#ifdef CONFIG_ICACHE_FLUSH_L1
-.section .l1.text
-#else
-.text
-#endif
-
-/* Invalidate all instruction cache lines assocoiated with this memory area */
-#ifdef CONFIG_SMP
-# define _blackfin_icache_flush_range _blackfin_icache_flush_range_l1
-#endif
-ENTRY(_blackfin_icache_flush_range)
- do_flush IFLUSH
-ENDPROC(_blackfin_icache_flush_range)
-
-#ifdef CONFIG_SMP
-.text
-# undef _blackfin_icache_flush_range
-ENTRY(_blackfin_icache_flush_range)
- p0.L = LO(DSPID);
- p0.H = HI(DSPID);
- r3 = [p0];
- r3 = r3.b (z);
- p2 = r3;
- p0.L = _blackfin_iflush_l1_entry;
- p0.H = _blackfin_iflush_l1_entry;
- p0 = p0 + (p2 << 2);
- p1 = [p0];
- jump (p1);
-ENDPROC(_blackfin_icache_flush_range)
-#endif
-
-#ifdef CONFIG_DCACHE_FLUSH_L1
-.section .l1.text
-#else
-.text
-#endif
-
-/* Throw away all D-cached data in specified region without any obligation to
- * write them back. Since the Blackfin ISA does not have an "invalidate"
- * instruction, we use flush/invalidate. Perhaps as a speed optimization we
- * could bang on the DTEST MMRs ...
- */
-ENTRY(_blackfin_dcache_invalidate_range)
- do_flush FLUSHINV
-ENDPROC(_blackfin_dcache_invalidate_range)
-
-/* Flush all data cache lines assocoiated with this memory area */
-ENTRY(_blackfin_dcache_flush_range)
- do_flush FLUSH, .Ldfr
-ENDPROC(_blackfin_dcache_flush_range)
-
-/* Our headers convert the page structure to an address, so just need to flush
- * its contents like normal. We know the start address is page aligned (which
- * greater than our cache alignment), as is the end address. So just jump into
- * the middle of the dcache flush function.
- */
-ENTRY(_blackfin_dflush_page)
- P1 = 1 << (PAGE_SHIFT - L1_CACHE_SHIFT);
- jump .Ldfr;
-ENDPROC(_blackfin_dflush_page)
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __MACH_COMMON_CLKDEV_H
-#define __MACH_COMMON_CLKDEV_H
-
-#include <linux/clk.h>
-
-struct clk_ops {
- unsigned long (*get_rate)(struct clk *clk);
- unsigned long (*round_rate)(struct clk *clk, unsigned long rate);
- int (*set_rate)(struct clk *clk, unsigned long rate);
- int (*enable)(struct clk *clk);
- int (*disable)(struct clk *clk);
-};
-
-struct clk {
- const char *name;
- unsigned long rate;
- spinlock_t lock;
- u32 flags;
- const struct clk_ops *ops;
- const struct params *params;
- void __iomem *reg;
- u32 mask;
- u32 shift;
-};
-
-#endif
-
+++ /dev/null
-/*
- * arch/blackfin/mach-common/clocks-init.c - reprogram clocks / memory
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/linkage.h>
-#include <asm/blackfin.h>
-
-#include <asm/dma.h>
-#include <asm/clocks.h>
-#include <asm/mem_init.h>
-#include <asm/dpmc.h>
-
-#ifdef CONFIG_BF60x
-
-#define CGU_CTL_VAL ((CONFIG_VCO_MULT << 8) | CLKIN_HALF)
-#define CGU_DIV_VAL \
- ((CONFIG_CCLK_DIV << CSEL_OFFSET) | \
- (CONFIG_SCLK_DIV << SYSSEL_OFFSET) | \
- (CONFIG_SCLK0_DIV << S0SEL_OFFSET) | \
- (CONFIG_SCLK1_DIV << S1SEL_OFFSET) | \
- (CONFIG_DCLK_DIV << DSEL_OFFSET))
-
-#define CONFIG_BFIN_DCLK (((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / CONFIG_DCLK_DIV) / 1000000)
-#if ((CONFIG_BFIN_DCLK != 125) && \
- (CONFIG_BFIN_DCLK != 133) && (CONFIG_BFIN_DCLK != 150) && \
- (CONFIG_BFIN_DCLK != 166) && (CONFIG_BFIN_DCLK != 200) && \
- (CONFIG_BFIN_DCLK != 225) && (CONFIG_BFIN_DCLK != 250))
-#error "DCLK must be in (125, 133, 150, 166, 200, 225, 250)MHz"
-#endif
-
-#else
-#define SDGCTL_WIDTH (1 << 31) /* SDRAM external data path width */
-#define PLL_CTL_VAL \
- (((CONFIG_VCO_MULT & 63) << 9) | CLKIN_HALF | \
- (PLL_BYPASS << 8) | (ANOMALY_05000305 ? 0 : 0x8000))
-#endif
-
-__attribute__((l1_text))
-static void do_sync(void)
-{
- __builtin_bfin_ssync();
-}
-
-__attribute__((l1_text))
-void init_clocks(void)
-{
- /* Kill any active DMAs as they may trigger external memory accesses
- * in the middle of reprogramming things, and that'll screw us up.
- * For example, any automatic DMAs left by U-Boot for splash screens.
- */
-#ifdef CONFIG_BF60x
- init_cgu(CGU_DIV_VAL, CGU_CTL_VAL);
- init_dmc(CONFIG_BFIN_DCLK);
-#else
- size_t i;
- for (i = 0; i < MAX_DMA_CHANNELS; ++i) {
- struct dma_register *dma = dma_io_base_addr[i];
- dma->cfg = 0;
- }
-
- do_sync();
-
-#ifdef SIC_IWR0
- bfin_write_SIC_IWR0(IWR_ENABLE(0));
-# ifdef SIC_IWR1
- /* BF52x system reset does not properly reset SIC_IWR1 which
- * will screw up the bootrom as it relies on MDMA0/1 waking it
- * up from IDLE instructions. See this report for more info:
- * http://blackfin.uclinux.org/gf/tracker/4323
- */
- if (ANOMALY_05000435)
- bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
- else
- bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
-# endif
-# ifdef SIC_IWR2
- bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
-# endif
-#else
- bfin_write_SIC_IWR(IWR_ENABLE(0));
-#endif
- do_sync();
-#ifdef EBIU_SDGCTL
- bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() | SRFS);
- do_sync();
-#endif
-
-#ifdef CLKBUFOE
- bfin_write16(VR_CTL, bfin_read_VR_CTL() | CLKBUFOE);
- do_sync();
- __asm__ __volatile__("IDLE;");
-#endif
- bfin_write_PLL_LOCKCNT(0x300);
- do_sync();
- /* We always write PLL_CTL thus avoiding Anomaly 05000242 */
- bfin_write16(PLL_CTL, PLL_CTL_VAL);
- __asm__ __volatile__("IDLE;");
- bfin_write_PLL_DIV(CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
-#ifdef EBIU_SDGCTL
- bfin_write_EBIU_SDRRC(mem_SDRRC);
- bfin_write_EBIU_SDGCTL((bfin_read_EBIU_SDGCTL() & SDGCTL_WIDTH) | mem_SDGCTL);
-#else
- bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() & ~(SRREQ));
- do_sync();
- bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | 0x1);
- bfin_write_EBIU_DDRCTL0(mem_DDRCTL0);
- bfin_write_EBIU_DDRCTL1(mem_DDRCTL1);
- bfin_write_EBIU_DDRCTL2(mem_DDRCTL2);
-#ifdef CONFIG_MEM_EBIU_DDRQUE
- bfin_write_EBIU_DDRQUE(CONFIG_MEM_EBIU_DDRQUE);
-#endif
-#endif
-#endif
- do_sync();
- bfin_read16(0);
-
-}
+++ /dev/null
-/*
- * Copyright 2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/cdev.h>
-#include <linux/device.h>
-#include <linux/errno.h>
-#include <linux/fs.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/types.h>
-#include <linux/cpufreq.h>
-
-#include <asm/delay.h>
-#include <asm/dpmc.h>
-
-#define DRIVER_NAME "bfin dpmc"
-
-struct bfin_dpmc_platform_data *pdata;
-
-/**
- * bfin_set_vlev - Update VLEV field in VR_CTL Reg.
- * Avoid BYPASS sequence
- */
-static void bfin_set_vlev(unsigned int vlev)
-{
- unsigned pll_lcnt;
-
- pll_lcnt = bfin_read_PLL_LOCKCNT();
-
- bfin_write_PLL_LOCKCNT(1);
- bfin_write_VR_CTL((bfin_read_VR_CTL() & ~VLEV) | vlev);
- bfin_write_PLL_LOCKCNT(pll_lcnt);
-}
-
-/**
- * bfin_get_vlev - Get CPU specific VLEV from platform device data
- */
-static unsigned int bfin_get_vlev(unsigned int freq)
-{
- int i;
-
- if (!pdata)
- goto err_out;
-
- freq >>= 16;
-
- for (i = 0; i < pdata->tabsize; i++)
- if (freq <= (pdata->tuple_tab[i] & 0xFFFF))
- return pdata->tuple_tab[i] >> 16;
-
-err_out:
- printk(KERN_WARNING "DPMC: No suitable CCLK VDDINT voltage pair found\n");
- return VLEV_120;
-}
-
-#ifdef CONFIG_CPU_FREQ
-# ifdef CONFIG_SMP
-static void bfin_idle_this_cpu(void *info)
-{
- unsigned long flags = 0;
- unsigned long iwr0, iwr1, iwr2;
- unsigned int cpu = smp_processor_id();
-
- local_irq_save_hw(flags);
- bfin_iwr_set_sup0(&iwr0, &iwr1, &iwr2);
-
- platform_clear_ipi(cpu, IRQ_SUPPLE_0);
- SSYNC();
- asm("IDLE;");
- bfin_iwr_restore(iwr0, iwr1, iwr2);
-
- local_irq_restore_hw(flags);
-}
-
-static void bfin_idle_cpu(void)
-{
- smp_call_function(bfin_idle_this_cpu, NULL, 0);
-}
-
-static void bfin_wakeup_cpu(void)
-{
- unsigned int cpu;
- unsigned int this_cpu = smp_processor_id();
- cpumask_t mask;
-
- cpumask_copy(&mask, cpu_online_mask);
- cpumask_clear_cpu(this_cpu, &mask);
- for_each_cpu(cpu, &mask)
- platform_send_ipi_cpu(cpu, IRQ_SUPPLE_0);
-}
-
-# else
-static void bfin_idle_cpu(void) {}
-static void bfin_wakeup_cpu(void) {}
-# endif
-
-static int
-vreg_cpufreq_notifier(struct notifier_block *nb, unsigned long val, void *data)
-{
- struct cpufreq_freqs *freq = data;
-
- if (freq->cpu != CPUFREQ_CPU)
- return 0;
-
- if (val == CPUFREQ_PRECHANGE && freq->old < freq->new) {
- bfin_idle_cpu();
- bfin_set_vlev(bfin_get_vlev(freq->new));
- udelay(pdata->vr_settling_time); /* Wait until Volatge settled */
- bfin_wakeup_cpu();
- } else if (val == CPUFREQ_POSTCHANGE && freq->old > freq->new) {
- bfin_idle_cpu();
- bfin_set_vlev(bfin_get_vlev(freq->new));
- bfin_wakeup_cpu();
- }
-
- return 0;
-}
-
-static struct notifier_block vreg_cpufreq_notifier_block = {
- .notifier_call = vreg_cpufreq_notifier
-};
-#endif /* CONFIG_CPU_FREQ */
-
-/**
- * bfin_dpmc_probe -
- *
- */
-static int bfin_dpmc_probe(struct platform_device *pdev)
-{
- if (pdev->dev.platform_data)
- pdata = pdev->dev.platform_data;
- else
- return -EINVAL;
-
- return cpufreq_register_notifier(&vreg_cpufreq_notifier_block,
- CPUFREQ_TRANSITION_NOTIFIER);
-}
-
-/**
- * bfin_dpmc_remove -
- */
-static int bfin_dpmc_remove(struct platform_device *pdev)
-{
- pdata = NULL;
- return cpufreq_unregister_notifier(&vreg_cpufreq_notifier_block,
- CPUFREQ_TRANSITION_NOTIFIER);
-}
-
-struct platform_driver bfin_dpmc_device_driver = {
- .probe = bfin_dpmc_probe,
- .remove = bfin_dpmc_remove,
- .driver = {
- .name = DRIVER_NAME,
- }
-};
-module_platform_driver(bfin_dpmc_device_driver);
-
-MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
-MODULE_DESCRIPTION("cpu power management driver for Blackfin");
-MODULE_LICENSE("GPL");
+++ /dev/null
-/*
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/linkage.h>
-#include <asm/blackfin.h>
-#include <mach/irq.h>
-#include <asm/dpmc.h>
-
-.section .l1.text
-ENTRY(_sleep_mode)
- [--SP] = (R7:4, P5:3);
- [--SP] = RETS;
-
- call _set_sic_iwr;
-
- P0.H = hi(PLL_CTL);
- P0.L = lo(PLL_CTL);
- R1 = W[P0](z);
- BITSET (R1, 3);
- W[P0] = R1.L;
-
- CLI R2;
- SSYNC;
- IDLE;
- STI R2;
-
- call _test_pll_locked;
-
- R0 = IWR_ENABLE(0);
- R1 = IWR_DISABLE_ALL;
- R2 = IWR_DISABLE_ALL;
-
- call _set_sic_iwr;
-
- P0.H = hi(PLL_CTL);
- P0.L = lo(PLL_CTL);
- R7 = w[p0](z);
- BITCLR (R7, 3);
- BITCLR (R7, 5);
- w[p0] = R7.L;
- IDLE;
-
- bfin_init_pm_bench_cycles;
-
- call _test_pll_locked;
-
- RETS = [SP++];
- (R7:4, P5:3) = [SP++];
- RTS;
-ENDPROC(_sleep_mode)
-
-/*
- * This func never returns as it puts the part into hibernate, and
- * is only called from do_hibernate, so we don't bother saving or
- * restoring any of the normal C runtime state. When we wake up,
- * the entry point will be in do_hibernate and not here.
- *
- * We accept just one argument -- the value to write to VR_CTL.
- */
-
-ENTRY(_hibernate_mode)
- /* Save/setup the regs we need early for minor pipeline optimization */
- R4 = R0;
-
- P3.H = hi(VR_CTL);
- P3.L = lo(VR_CTL);
- /* Disable all wakeup sources */
- R0 = IWR_DISABLE_ALL;
- R1 = IWR_DISABLE_ALL;
- R2 = IWR_DISABLE_ALL;
- call _set_sic_iwr;
- call _set_dram_srfs;
- SSYNC;
-
- /* Finally, we climb into our cave to hibernate */
- W[P3] = R4.L;
-
- bfin_init_pm_bench_cycles;
-
- CLI R2;
- IDLE;
-.Lforever:
- jump .Lforever;
-ENDPROC(_hibernate_mode)
-
-ENTRY(_sleep_deeper)
- [--SP] = (R7:4, P5:3);
- [--SP] = RETS;
-
- CLI R4;
-
- P3 = R0;
- P4 = R1;
- P5 = R2;
-
- R0 = IWR_ENABLE(0);
- R1 = IWR_DISABLE_ALL;
- R2 = IWR_DISABLE_ALL;
-
- call _set_sic_iwr;
- call _set_dram_srfs; /* Set SDRAM Self Refresh */
-
- P0.H = hi(PLL_DIV);
- P0.L = lo(PLL_DIV);
- R6 = W[P0](z);
- R0.L = 0xF;
- W[P0] = R0.l; /* Set Max VCO to SCLK divider */
-
- P0.H = hi(PLL_CTL);
- P0.L = lo(PLL_CTL);
- R5 = W[P0](z);
- R0.L = (CONFIG_MIN_VCO_HZ/CONFIG_CLKIN_HZ) << 9;
- W[P0] = R0.l; /* Set Min CLKIN to VCO multiplier */
-
- SSYNC;
- IDLE;
-
- call _test_pll_locked;
-
- P0.H = hi(VR_CTL);
- P0.L = lo(VR_CTL);
- R7 = W[P0](z);
- R1 = 0x6;
- R1 <<= 16;
- R2 = 0x0404(Z);
- R1 = R1|R2;
-
- R2 = DEPOSIT(R7, R1);
- W[P0] = R2; /* Set Min Core Voltage */
-
- SSYNC;
- IDLE;
-
- call _test_pll_locked;
-
- R0 = P3;
- R1 = P4;
- R3 = P5;
- call _set_sic_iwr; /* Set Awake from IDLE */
-
- P0.H = hi(PLL_CTL);
- P0.L = lo(PLL_CTL);
- R0 = W[P0](z);
- BITSET (R0, 3);
- W[P0] = R0.L; /* Turn CCLK OFF */
- SSYNC;
- IDLE;
-
- call _test_pll_locked;
-
- R0 = IWR_ENABLE(0);
- R1 = IWR_DISABLE_ALL;
- R2 = IWR_DISABLE_ALL;
-
- call _set_sic_iwr; /* Set Awake from IDLE PLL */
-
- P0.H = hi(VR_CTL);
- P0.L = lo(VR_CTL);
- W[P0]= R7;
-
- SSYNC;
- IDLE;
-
- bfin_init_pm_bench_cycles;
-
- call _test_pll_locked;
-
- P0.H = hi(PLL_DIV);
- P0.L = lo(PLL_DIV);
- W[P0]= R6; /* Restore CCLK and SCLK divider */
-
- P0.H = hi(PLL_CTL);
- P0.L = lo(PLL_CTL);
- w[p0] = R5; /* Restore VCO multiplier */
- IDLE;
- call _test_pll_locked;
-
- call _unset_dram_srfs; /* SDRAM Self Refresh Off */
-
- STI R4;
-
- RETS = [SP++];
- (R7:4, P5:3) = [SP++];
- RTS;
-ENDPROC(_sleep_deeper)
-
-ENTRY(_set_dram_srfs)
- /* set the dram to self refresh mode */
- SSYNC;
-#if defined(EBIU_RSTCTL) /* DDR */
- P0.H = hi(EBIU_RSTCTL);
- P0.L = lo(EBIU_RSTCTL);
- R2 = [P0];
- BITSET(R2, 3); /* SRREQ enter self-refresh mode */
- [P0] = R2;
- SSYNC;
-1:
- R2 = [P0];
- CC = BITTST(R2, 4);
- if !CC JUMP 1b;
-#else /* SDRAM */
- P0.L = lo(EBIU_SDGCTL);
- P0.H = hi(EBIU_SDGCTL);
- P1.L = lo(EBIU_SDSTAT);
- P1.H = hi(EBIU_SDSTAT);
-
- R2 = [P0];
- BITSET(R2, 24); /* SRFS enter self-refresh mode */
- [P0] = R2;
- SSYNC;
-
-1:
- R2 = w[P1];
- SSYNC;
- cc = BITTST(R2, 1); /* SDSRA poll self-refresh status */
- if !cc jump 1b;
-
- R2 = [P0];
- BITCLR(R2, 0); /* SCTLE disable CLKOUT */
- [P0] = R2;
-#endif
- RTS;
-ENDPROC(_set_dram_srfs)
-
-ENTRY(_unset_dram_srfs)
- /* set the dram out of self refresh mode */
-
-#if defined(EBIU_RSTCTL) /* DDR */
- P0.H = hi(EBIU_RSTCTL);
- P0.L = lo(EBIU_RSTCTL);
- R2 = [P0];
- BITCLR(R2, 3); /* clear SRREQ bit */
- [P0] = R2;
-#elif defined(EBIU_SDGCTL) /* SDRAM */
- /* release CLKOUT from self-refresh */
- P0.L = lo(EBIU_SDGCTL);
- P0.H = hi(EBIU_SDGCTL);
-
- R2 = [P0];
- BITSET(R2, 0); /* SCTLE enable CLKOUT */
- [P0] = R2
- SSYNC;
-
- /* release SDRAM from self-refresh */
- R2 = [P0];
- BITCLR(R2, 24); /* clear SRFS bit */
- [P0] = R2
-#endif
-
- SSYNC;
- RTS;
-ENDPROC(_unset_dram_srfs)
-
-ENTRY(_set_sic_iwr)
-#ifdef SIC_IWR0
- P0.H = hi(SYSMMR_BASE);
- P0.L = lo(SYSMMR_BASE);
- [P0 + (SIC_IWR0 - SYSMMR_BASE)] = R0;
- [P0 + (SIC_IWR1 - SYSMMR_BASE)] = R1;
-# ifdef SIC_IWR2
- [P0 + (SIC_IWR2 - SYSMMR_BASE)] = R2;
-# endif
-#else
- P0.H = hi(SIC_IWR);
- P0.L = lo(SIC_IWR);
- [P0] = R0;
-#endif
-
- SSYNC;
- RTS;
-ENDPROC(_set_sic_iwr)
-
-ENTRY(_test_pll_locked)
- P0.H = hi(PLL_STAT);
- P0.L = lo(PLL_STAT);
-1:
- R0 = W[P0] (Z);
- CC = BITTST(R0,5);
- IF !CC JUMP 1b;
- RTS;
-ENDPROC(_test_pll_locked)
-
-.section .text
-ENTRY(_do_hibernate)
- bfin_cpu_reg_save;
- bfin_sys_mmr_save;
- bfin_core_mmr_save;
-
- /* Setup args to hibernate mode early for pipeline optimization */
- R0 = M3;
- P1.H = _hibernate_mode;
- P1.L = _hibernate_mode;
-
- /* Save Magic, return address and Stack Pointer */
- P0 = 0;
- R1.H = 0xDEAD; /* Hibernate Magic */
- R1.L = 0xBEEF;
- R2.H = .Lpm_resume_here;
- R2.L = .Lpm_resume_here;
- [P0++] = R1; /* Store Hibernate Magic */
- [P0++] = R2; /* Save Return Address */
- [P0++] = SP; /* Save Stack Pointer */
-
- /* Must use an indirect call as we need to jump to L1 */
- call (P1); /* Goodbye */
-
-.Lpm_resume_here:
-
- bfin_core_mmr_restore;
- bfin_sys_mmr_restore;
- bfin_cpu_reg_restore;
-
- [--sp] = RETI; /* Clear Global Interrupt Disable */
- SP += 4;
-
- RTS;
-ENDPROC(_do_hibernate)
+++ /dev/null
-/*
- * Contains the system-call and fault low-level handling routines.
- * This also contains the timer-interrupt handler, as well as all
- * interrupts and faults that can result in a task-switch.
- *
- * Copyright 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-/* NOTE: This code handles signal-recognition, which happens every time
- * after a timer-interrupt and after each system call.
- */
-
-#include <linux/init.h>
-#include <linux/linkage.h>
-#include <linux/unistd.h>
-#include <asm/blackfin.h>
-#include <asm/errno.h>
-#include <asm/fixed_code.h>
-#include <asm/thread_info.h> /* TIF_NEED_RESCHED */
-#include <asm/asm-offsets.h>
-#include <asm/trace.h>
-#include <asm/traps.h>
-
-#include <asm/context.S>
-
-
-#ifdef CONFIG_EXCPT_IRQ_SYSC_L1
-.section .l1.text
-#else
-.text
-#endif
-
-/* Slightly simplified and streamlined entry point for CPLB misses.
- * This one does not lower the level to IRQ5, and thus can be used to
- * patch up CPLB misses on the kernel stack.
- */
-#if ANOMALY_05000261
-#define _ex_dviol _ex_workaround_261
-#define _ex_dmiss _ex_workaround_261
-#define _ex_dmult _ex_workaround_261
-
-ENTRY(_ex_workaround_261)
- /*
- * Work around an anomaly: if we see a new DCPLB fault, return
- * without doing anything. Then, if we get the same fault again,
- * handle it.
- */
- P4 = R7; /* Store EXCAUSE */
-
- GET_PDA(p5, r7);
- r7 = [p5 + PDA_LFRETX];
- r6 = retx;
- [p5 + PDA_LFRETX] = r6;
- cc = r6 == r7;
- if !cc jump _bfin_return_from_exception;
- /* fall through */
- R7 = P4;
- R6 = VEC_CPLB_M; /* Data CPLB Miss */
- cc = R6 == R7;
- if cc jump _ex_dcplb_miss (BP);
-#ifdef CONFIG_MPU
- R6 = VEC_CPLB_VL; /* Data CPLB Violation */
- cc = R6 == R7;
- if cc jump _ex_dcplb_viol (BP);
-#endif
- /* Handle Data CPLB Protection Violation
- * and Data CPLB Multiple Hits - Linux Trap Zero
- */
- jump _ex_trap_c;
-ENDPROC(_ex_workaround_261)
-
-#else
-#ifdef CONFIG_MPU
-#define _ex_dviol _ex_dcplb_viol
-#else
-#define _ex_dviol _ex_trap_c
-#endif
-#define _ex_dmiss _ex_dcplb_miss
-#define _ex_dmult _ex_trap_c
-#endif
-
-
-ENTRY(_ex_dcplb_viol)
-ENTRY(_ex_dcplb_miss)
-ENTRY(_ex_icplb_miss)
- (R7:6,P5:4) = [sp++];
- /* We leave the previously pushed ASTAT on the stack. */
- SAVE_CONTEXT_CPLB
-
- /* We must load R1 here, _before_ DEBUG_HWTRACE_SAVE, since that
- * will change the stack pointer. */
- R0 = SEQSTAT;
- R1 = SP;
-
- DEBUG_HWTRACE_SAVE(p5, r7)
-
- sp += -12;
- call _cplb_hdr;
- sp += 12;
- CC = R0 == 0;
- IF !CC JUMP _handle_bad_cplb;
-
-#ifdef CONFIG_DEBUG_DOUBLEFAULT
- /* While we were processing this, did we double fault? */
- r7 = SEQSTAT; /* reason code is in bit 5:0 */
- r6.l = lo(SEQSTAT_EXCAUSE);
- r6.h = hi(SEQSTAT_EXCAUSE);
- r7 = r7 & r6;
- r6 = 0x25;
- CC = R7 == R6;
- if CC JUMP _double_fault;
-#endif
-
- DEBUG_HWTRACE_RESTORE(p5, r7)
- RESTORE_CONTEXT_CPLB
- ASTAT = [SP++];
- SP = EX_SCRATCH_REG;
- rtx;
-ENDPROC(_ex_icplb_miss)
-
-ENTRY(_ex_syscall)
- raise 15; /* invoked by TRAP #0, for sys call */
- jump.s _bfin_return_from_exception;
-ENDPROC(_ex_syscall)
-
-ENTRY(_ex_single_step)
- /* If we just returned from an interrupt, the single step event is
- for the RTI instruction. */
- r7 = retx;
- r6 = reti;
- cc = r7 == r6;
- if cc jump _bfin_return_from_exception;
-
-#ifdef CONFIG_KGDB
- /* Don't do single step in hardware exception handler */
- p5.l = lo(IPEND);
- p5.h = hi(IPEND);
- r6 = [p5];
- cc = bittst(r6, 4);
- if cc jump _bfin_return_from_exception;
- cc = bittst(r6, 5);
- if cc jump _bfin_return_from_exception;
-
- /* skip single step if current interrupt priority is higher than
- * that of the first instruction, from which gdb starts single step */
- r6 >>= 6;
- r7 = 10;
-.Lfind_priority_start:
- cc = bittst(r6, 0);
- if cc jump .Lfind_priority_done;
- r6 >>= 1;
- r7 += -1;
- cc = r7 == 0;
- if cc jump .Lfind_priority_done;
- jump.s .Lfind_priority_start;
-.Lfind_priority_done:
- p4.l = _kgdb_single_step;
- p4.h = _kgdb_single_step;
- r6 = [p4];
- cc = r6 == 0;
- if cc jump .Ldo_single_step;
- r6 += -1;
- cc = r6 < r7;
- if cc jump 1f;
-.Ldo_single_step:
-#else
- /* If we were in user mode, do the single step normally. */
- p5.l = lo(IPEND);
- p5.h = hi(IPEND);
- r6 = [p5];
- r7 = 0xffe0 (z);
- r7 = r7 & r6;
- cc = r7 == 0;
- if !cc jump 1f;
-#endif
-#ifdef CONFIG_EXACT_HWERR
- /* Read the ILAT, and to check to see if the process we are
- * single stepping caused a previous hardware error
- * If so, do not single step, (which lowers to IRQ5, and makes
- * us miss the error).
- */
- p5.l = lo(ILAT);
- p5.h = hi(ILAT);
- r7 = [p5];
- cc = bittst(r7, EVT_IVHW_P);
- if cc jump 1f;
-#endif
- /* Single stepping only a single instruction, so clear the trace
- * bit here. */
- r7 = syscfg;
- bitclr (r7, SYSCFG_SSSTEP_P);
- syscfg = R7;
- jump _ex_trap_c;
-
-1:
- /*
- * We were in an interrupt handler. By convention, all of them save
- * SYSCFG with their first instruction, so by checking whether our
- * RETX points at the entry point, we can determine whether to allow
- * a single step, or whether to clear SYSCFG.
- *
- * First, find out the interrupt level and the event vector for it.
- */
- p5.l = lo(EVT0);
- p5.h = hi(EVT0);
- p5 += -4;
-2:
- r7 = rot r7 by -1;
- p5 += 4;
- if !cc jump 2b;
-
- /* What we actually do is test for the _second_ instruction in the
- * IRQ handler. That way, if there are insns following the restore
- * of SYSCFG after leaving the handler, we will not turn off SYSCFG
- * for them. */
-
- r7 = [p5];
- r7 += 2;
- r6 = RETX;
- cc = R7 == R6;
- if !cc jump _bfin_return_from_exception;
-
- r7 = syscfg;
- bitclr (r7, SYSCFG_SSSTEP_P); /* Turn off single step */
- syscfg = R7;
-
- /* Fall through to _bfin_return_from_exception. */
-ENDPROC(_ex_single_step)
-
-ENTRY(_bfin_return_from_exception)
-#if ANOMALY_05000257
- R7=LC0;
- LC0=R7;
- R7=LC1;
- LC1=R7;
-#endif
-
-#ifdef CONFIG_DEBUG_DOUBLEFAULT
- /* While we were processing the current exception,
- * did we cause another, and double fault?
- */
- r7 = SEQSTAT; /* reason code is in bit 5:0 */
- r6.l = lo(SEQSTAT_EXCAUSE);
- r6.h = hi(SEQSTAT_EXCAUSE);
- r7 = r7 & r6;
- r6 = VEC_UNCOV;
- CC = R7 == R6;
- if CC JUMP _double_fault;
-#endif
-
- (R7:6,P5:4) = [sp++];
- ASTAT = [sp++];
- sp = EX_SCRATCH_REG;
- rtx;
-ENDPROC(_bfin_return_from_exception)
-
-ENTRY(_handle_bad_cplb)
- DEBUG_HWTRACE_RESTORE(p5, r7)
- /* To get here, we just tried and failed to change a CPLB
- * so, handle things in trap_c (C code), by lowering to
- * IRQ5, just like we normally do. Since this is not a
- * "normal" return path, we have a do a lot of stuff to
- * the stack to get ready so, we can fall through - we
- * need to make a CPLB exception look like a normal exception
- */
- RESTORE_CONTEXT_CPLB
- /* ASTAT is still on the stack, where it is needed. */
- [--sp] = (R7:6,P5:4);
-
-ENTRY(_ex_replaceable)
- nop;
-
-ENTRY(_ex_trap_c)
- /* The only thing that has been saved in this context is
- * (R7:6,P5:4), ASTAT & SP - don't use anything else
- */
-
- GET_PDA(p5, r6);
-
- /* Make sure we are not in a double fault */
- p4.l = lo(IPEND);
- p4.h = hi(IPEND);
- r7 = [p4];
- CC = BITTST (r7, 5);
- if CC jump _double_fault;
- [p5 + PDA_EXIPEND] = r7;
-
- /* Call C code (trap_c) to handle the exception, which most
- * likely involves sending a signal to the current process.
- * To avoid double faults, lower our priority to IRQ5 first.
- */
- r7.h = _exception_to_level5;
- r7.l = _exception_to_level5;
- p4.l = lo(EVT5);
- p4.h = hi(EVT5);
- [p4] = r7;
- csync;
-
- /*
- * Save these registers, as they are only valid in exception context
- * (where we are now - as soon as we defer to IRQ5, they can change)
- * DCPLB_STATUS and ICPLB_STATUS are also only valid in EVT3,
- * but they are not very interesting, so don't save them
- */
-
- p4.l = lo(DCPLB_FAULT_ADDR);
- p4.h = hi(DCPLB_FAULT_ADDR);
- r7 = [p4];
- [p5 + PDA_DCPLB] = r7;
-
- p4.l = lo(ICPLB_FAULT_ADDR);
- p4.h = hi(ICPLB_FAULT_ADDR);
- r6 = [p4];
- [p5 + PDA_ICPLB] = r6;
-
- r6 = retx;
- [p5 + PDA_RETX] = r6;
-
- r6 = SEQSTAT;
- [p5 + PDA_SEQSTAT] = r6;
-
- /* Save the state of single stepping */
- r6 = SYSCFG;
- [p5 + PDA_SYSCFG] = r6;
- /* Clear it while we handle the exception in IRQ5 mode */
- BITCLR(r6, SYSCFG_SSSTEP_P);
- SYSCFG = r6;
-
- /* Save the current IMASK, since we change in order to jump to level 5 */
- cli r6;
- [p5 + PDA_EXIMASK] = r6;
-
- p4.l = lo(SAFE_USER_INSTRUCTION);
- p4.h = hi(SAFE_USER_INSTRUCTION);
- retx = p4;
-
- /* Disable all interrupts, but make sure level 5 is enabled so
- * we can switch to that level.
- */
- r6 = 0x3f;
- sti r6;
-
- /* In case interrupts are disabled IPEND[4] (global interrupt disable bit)
- * clear it (re-enabling interrupts again) by the special sequence of pushing
- * RETI onto the stack. This way we can lower ourselves to IVG5 even if the
- * exception was taken after the interrupt handler was called but before it
- * got a chance to enable global interrupts itself.
- */
- [--sp] = reti;
- sp += 4;
-
- raise 5;
- jump.s _bfin_return_from_exception;
-ENDPROC(_ex_trap_c)
-
-/* We just realized we got an exception, while we were processing a different
- * exception. This is a unrecoverable event, so crash.
- * Note: this cannot be ENTRY() as we jump here with "if cc jump" ...
- */
-ENTRY(_double_fault)
- /* Turn caches & protection off, to ensure we don't get any more
- * double exceptions
- */
-
- P4.L = LO(IMEM_CONTROL);
- P4.H = HI(IMEM_CONTROL);
-
- R5 = [P4]; /* Control Register*/
- BITCLR(R5,ENICPLB_P);
- CSYNC; /* Disabling of CPLBs should be proceeded by a CSYNC */
- [P4] = R5;
- SSYNC;
-
- P4.L = LO(DMEM_CONTROL);
- P4.H = HI(DMEM_CONTROL);
- R5 = [P4];
- BITCLR(R5,ENDCPLB_P);
- CSYNC; /* Disabling of CPLBs should be proceeded by a CSYNC */
- [P4] = R5;
- SSYNC;
-
- /* Fix up the stack */
- (R7:6,P5:4) = [sp++];
- ASTAT = [sp++];
- SP = EX_SCRATCH_REG;
-
- /* We should be out of the exception stack, and back down into
- * kernel or user space stack
- */
- SAVE_ALL_SYS
-
- /* The dumping functions expect the return address in the RETI
- * slot. */
- r6 = retx;
- [sp + PT_PC] = r6;
-
- r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */
- SP += -12;
- pseudo_long_call _double_fault_c, p5;
- SP += 12;
-.L_double_fault_panic:
- JUMP .L_double_fault_panic
-
-ENDPROC(_double_fault)
-
-ENTRY(_exception_to_level5)
- SAVE_ALL_SYS
-
- GET_PDA(p5, r7); /* Fetch current PDA */
- r6 = [p5 + PDA_RETX];
- [sp + PT_PC] = r6;
-
- r6 = [p5 + PDA_SYSCFG];
- [sp + PT_SYSCFG] = r6;
-
- r6 = [p5 + PDA_SEQSTAT]; /* Read back seqstat */
- [sp + PT_SEQSTAT] = r6;
-
- /* Restore the hardware error vector. */
- r7.h = _evt_ivhw;
- r7.l = _evt_ivhw;
- p4.l = lo(EVT5);
- p4.h = hi(EVT5);
- [p4] = r7;
- csync;
-
-#ifdef CONFIG_DEBUG_DOUBLEFAULT
- /* Now that we have the hardware error vector programmed properly
- * we can re-enable interrupts (IPEND[4]), so if the _trap_c causes
- * another hardware error, we can catch it (self-nesting).
- */
- [--sp] = reti;
- sp += 4;
-#endif
-
- r7 = [p5 + PDA_EXIPEND] /* Read the IPEND from the Exception state */
- [sp + PT_IPEND] = r7; /* Store IPEND onto the stack */
-
- r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */
- SP += -12;
- pseudo_long_call _trap_c, p4;
- SP += 12;
-
- /* If interrupts were off during the exception (IPEND[4] = 1), turn them off
- * before we return.
- */
- CC = BITTST(r7, EVT_IRPTEN_P)
- if !CC jump 1f;
- /* this will load a random value into the reti register - but that is OK,
- * since we do restore it to the correct value in the 'RESTORE_ALL_SYS' macro
- */
- sp += -4;
- reti = [sp++];
-1:
- /* restore the interrupt mask (IMASK) */
- r6 = [p5 + PDA_EXIMASK];
- sti r6;
-
- call _ret_from_exception;
- RESTORE_ALL_SYS
- rti;
-ENDPROC(_exception_to_level5)
-
-ENTRY(_trap) /* Exception: 4th entry into system event table(supervisor mode)*/
- /* Since the kernel stack can be anywhere, it's not guaranteed to be
- * covered by a CPLB. Switch to an exception stack; use RETN as a
- * scratch register (for want of a better option).
- */
- EX_SCRATCH_REG = sp;
- GET_PDA_SAFE(sp);
- sp = [sp + PDA_EXSTACK];
- /* Try to deal with syscalls quickly. */
- [--sp] = ASTAT;
- [--sp] = (R7:6,P5:4);
-
- ANOMALY_283_315_WORKAROUND(p5, r7)
-
-#ifdef CONFIG_EXACT_HWERR
- /* Make sure all pending read/writes complete. This will ensure any
- * accesses which could cause hardware errors completes, and signal
- * the the hardware before we do something silly, like crash the
- * kernel. We don't need to work around anomaly 05000312, since
- * we are already atomic
- */
- ssync;
-#endif
-
-#ifdef CONFIG_DEBUG_DOUBLEFAULT
- /*
- * Save these registers, as they are only valid in exception context
- * (where we are now - as soon as we defer to IRQ5, they can change)
- * DCPLB_STATUS and ICPLB_STATUS are also only valid in EVT3,
- * but they are not very interesting, so don't save them
- */
-
- GET_PDA(p5, r7);
- p4.l = lo(DCPLB_FAULT_ADDR);
- p4.h = hi(DCPLB_FAULT_ADDR);
- r7 = [p4];
- [p5 + PDA_DF_DCPLB] = r7;
-
- p4.l = lo(ICPLB_FAULT_ADDR);
- p4.h = hi(ICPLB_FAULT_ADDR);
- r7 = [p4];
- [p5 + PDA_DF_ICPLB] = r7;
-
- r7 = retx;
- [p5 + PDA_DF_RETX] = r7;
-
- r7 = SEQSTAT; /* reason code is in bit 5:0 */
- [p5 + PDA_DF_SEQSTAT] = r7;
-#else
- r7 = SEQSTAT; /* reason code is in bit 5:0 */
-#endif
- r6.l = lo(SEQSTAT_EXCAUSE);
- r6.h = hi(SEQSTAT_EXCAUSE);
- r7 = r7 & r6;
- p5.h = _ex_table;
- p5.l = _ex_table;
- p4 = r7;
- p5 = p5 + (p4 << 2);
- p4 = [p5];
- jump (p4);
-
-.Lbadsys:
- r7 = -ENOSYS; /* signextending enough */
- [sp + PT_R0] = r7; /* return value from system call */
- jump .Lsyscall_really_exit;
-ENDPROC(_trap)
-
-ENTRY(_system_call)
- /* Store IPEND */
- p2.l = lo(IPEND);
- p2.h = hi(IPEND);
- csync;
- r0 = [p2];
- [sp + PT_IPEND] = r0;
-
- /* Store RETS for now */
- r0 = rets;
- [sp + PT_RESERVED] = r0;
- /* Set the stack for the current process */
- r7 = sp;
- r6.l = lo(ALIGN_PAGE_MASK);
- r6.h = hi(ALIGN_PAGE_MASK);
- r7 = r7 & r6; /* thread_info */
- p2 = r7;
- p2 = [p2];
-
- [p2+(TASK_THREAD+THREAD_KSP)] = sp;
-#ifdef CONFIG_IPIPE
- r0 = sp;
- SP += -12;
- pseudo_long_call ___ipipe_syscall_root, p0;
- SP += 12;
- cc = r0 == 1;
- if cc jump .Lsyscall_really_exit;
- cc = r0 == -1;
- if cc jump .Lresume_userspace;
- r3 = [sp + PT_R3];
- r4 = [sp + PT_R4];
- p0 = [sp + PT_ORIG_P0];
-#endif /* CONFIG_IPIPE */
-
- /* are we tracing syscalls?*/
- r7 = sp;
- r6.l = lo(ALIGN_PAGE_MASK);
- r6.h = hi(ALIGN_PAGE_MASK);
- r7 = r7 & r6;
- p2 = r7;
- r7 = [p2+TI_FLAGS];
- CC = BITTST(r7,TIF_SYSCALL_TRACE);
- if CC JUMP _sys_trace;
- CC = BITTST(r7,TIF_SINGLESTEP);
- if CC JUMP _sys_trace;
-
- /* Make sure the system call # is valid */
- p4 = __NR_syscall;
- /* System call number is passed in P0 */
- cc = p4 <= p0;
- if cc jump .Lbadsys;
-
- /* Execute the appropriate system call */
-
- p4 = p0;
- p5.l = _sys_call_table;
- p5.h = _sys_call_table;
- p5 = p5 + (p4 << 2);
- r0 = [sp + PT_R0];
- r1 = [sp + PT_R1];
- r2 = [sp + PT_R2];
- p5 = [p5];
-
- [--sp] = r5;
- [--sp] = r4;
- [--sp] = r3;
- SP += -12;
- call (p5);
- SP += 24;
- [sp + PT_R0] = r0;
-
-.Lresume_userspace:
- r7 = sp;
- r4.l = lo(ALIGN_PAGE_MASK);
- r4.h = hi(ALIGN_PAGE_MASK);
- r7 = r7 & r4; /* thread_info->flags */
- p5 = r7;
-.Lresume_userspace_1:
- /* Disable interrupts. */
- [--sp] = reti;
- reti = [sp++];
-
- r7 = [p5 + TI_FLAGS];
- r4.l = lo(_TIF_WORK_MASK);
- r4.h = hi(_TIF_WORK_MASK);
- r7 = r7 & r4;
-
-.Lsyscall_resched:
-#ifdef CONFIG_IPIPE
- cc = BITTST(r7, TIF_IRQ_SYNC);
- if !cc jump .Lsyscall_no_irqsync;
- /*
- * Clear IPEND[4] manually to undo what resume_userspace_1 just did;
- * we need this so that high priority domain interrupts may still
- * preempt the current domain while the pipeline log is being played
- * back.
- */
- [--sp] = reti;
- SP += 4; /* don't merge with next insn to keep the pattern obvious */
- SP += -12;
- pseudo_long_call ___ipipe_sync_root, p4;
- SP += 12;
- jump .Lresume_userspace_1;
-.Lsyscall_no_irqsync:
-#endif
- cc = BITTST(r7, TIF_NEED_RESCHED);
- if !cc jump .Lsyscall_sigpending;
-
- /* Reenable interrupts. */
- [--sp] = reti;
- sp += 4;
-
- SP += -12;
- pseudo_long_call _schedule, p4;
- SP += 12;
-
- jump .Lresume_userspace_1;
-
-.Lsyscall_sigpending:
- cc = BITTST(r7, TIF_SIGPENDING);
- if cc jump .Lsyscall_do_signals;
- cc = BITTST(r7, TIF_NOTIFY_RESUME);
- if !cc jump .Lsyscall_really_exit;
-.Lsyscall_do_signals:
- /* Reenable interrupts. */
- [--sp] = reti;
- sp += 4;
-
- r0 = sp;
- SP += -12;
- pseudo_long_call _do_notify_resume, p5;
- SP += 12;
-
-.Lsyscall_really_exit:
- r5 = [sp + PT_RESERVED];
- rets = r5;
- rts;
-ENDPROC(_system_call)
-
-/* Do not mark as ENTRY() to avoid error in assembler ...
- * this symbol need not be global anyways, so ...
- */
-_sys_trace:
- r0 = sp;
- pseudo_long_call _syscall_trace_enter, p5;
-
- /* Make sure the system call # is valid */
- p4 = [SP + PT_P0];
- p3 = __NR_syscall;
- cc = p3 <= p4;
- r0 = -ENOSYS;
- if cc jump .Lsys_trace_badsys;
-
- /* Execute the appropriate system call */
- p5.l = _sys_call_table;
- p5.h = _sys_call_table;
- p5 = p5 + (p4 << 2);
- r0 = [sp + PT_R0];
- r1 = [sp + PT_R1];
- r2 = [sp + PT_R2];
- r3 = [sp + PT_R3];
- r4 = [sp + PT_R4];
- r5 = [sp + PT_R5];
- p5 = [p5];
-
- [--sp] = r5;
- [--sp] = r4;
- [--sp] = r3;
- SP += -12;
- call (p5);
- SP += 24;
-.Lsys_trace_badsys:
- [sp + PT_R0] = r0;
-
- r0 = sp;
- pseudo_long_call _syscall_trace_leave, p5;
- jump .Lresume_userspace;
-ENDPROC(_sys_trace)
-
-ENTRY(_resume)
- /*
- * Beware - when entering resume, prev (the current task) is
- * in r0, next (the new task) is in r1.
- */
- p0 = r0;
- p1 = r1;
- [--sp] = rets;
- [--sp] = fp;
- [--sp] = (r7:4, p5:3);
-
- /* save usp */
- p2 = usp;
- [p0+(TASK_THREAD+THREAD_USP)] = p2;
-
- /* save current kernel stack pointer */
- [p0+(TASK_THREAD+THREAD_KSP)] = sp;
-
- /* save program counter */
- r1.l = _new_old_task;
- r1.h = _new_old_task;
- [p0+(TASK_THREAD+THREAD_PC)] = r1;
-
- /* restore the kernel stack pointer */
- sp = [p1+(TASK_THREAD+THREAD_KSP)];
-
- /* restore user stack pointer */
- p0 = [p1+(TASK_THREAD+THREAD_USP)];
- usp = p0;
-
- /* restore pc */
- p0 = [p1+(TASK_THREAD+THREAD_PC)];
- jump (p0);
-
- /*
- * Following code actually lands up in a new (old) task.
- */
-
-_new_old_task:
- (r7:4, p5:3) = [sp++];
- fp = [sp++];
- rets = [sp++];
-
- /*
- * When we come out of resume, r0 carries "old" task, because we are
- * in "new" task.
- */
- rts;
-ENDPROC(_resume)
-
-ENTRY(_ret_from_exception)
-#ifdef CONFIG_IPIPE
- p2.l = _ipipe_percpu_domain;
- p2.h = _ipipe_percpu_domain;
- r0.l = _ipipe_root;
- r0.h = _ipipe_root;
- r2 = [p2];
- cc = r0 == r2;
- if !cc jump 4f; /* not on behalf of the root domain, get out */
-#endif /* CONFIG_IPIPE */
- p2.l = lo(IPEND);
- p2.h = hi(IPEND);
-
- csync;
- r0 = [p2];
- [sp + PT_IPEND] = r0;
-
-1:
- r2 = LO(~0x37) (Z);
- r0 = r2 & r0;
- cc = r0 == 0;
- if !cc jump 4f; /* if not return to user mode, get out */
-
- /* Make sure any pending system call or deferred exception
- * return in ILAT for this process to get executed, otherwise
- * in case context switch happens, system call of
- * first process (i.e in ILAT) will be carried
- * forward to the switched process
- */
-
- p2.l = lo(ILAT);
- p2.h = hi(ILAT);
- r0 = [p2];
- r1 = (EVT_IVG14 | EVT_IVG15) (z);
- r0 = r0 & r1;
- cc = r0 == 0;
- if !cc jump 5f;
-
- /* Set the stack for the current process */
- r7 = sp;
- r4.l = lo(ALIGN_PAGE_MASK);
- r4.h = hi(ALIGN_PAGE_MASK);
- r7 = r7 & r4; /* thread_info->flags */
- p5 = r7;
- r7 = [p5 + TI_FLAGS];
- r4.l = lo(_TIF_WORK_MASK);
- r4.h = hi(_TIF_WORK_MASK);
- r7 = r7 & r4;
- cc = r7 == 0;
- if cc jump 4f;
-
- p0.l = lo(EVT15);
- p0.h = hi(EVT15);
- p1.l = _schedule_and_signal;
- p1.h = _schedule_and_signal;
- [p0] = p1;
- csync;
- raise 15; /* raise evt15 to do signal or reschedule */
-4:
- r0 = syscfg;
- bitclr(r0, SYSCFG_SSSTEP_P); /* Turn off single step */
- syscfg = r0;
-5:
- rts;
-ENDPROC(_ret_from_exception)
-
-#if defined(CONFIG_PREEMPT)
-
-ENTRY(_up_to_irq14)
-#if ANOMALY_05000281 || ANOMALY_05000461
- r0.l = lo(SAFE_USER_INSTRUCTION);
- r0.h = hi(SAFE_USER_INSTRUCTION);
- reti = r0;
-#endif
-
-#ifdef CONFIG_DEBUG_HWERR
- /* enable irq14 & hwerr interrupt, until we transition to _evt_evt14 */
- r0 = (EVT_IVG14 | EVT_IVHW | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU);
-#else
- /* Only enable irq14 interrupt, until we transition to _evt_evt14 */
- r0 = (EVT_IVG14 | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU);
-#endif
- sti r0;
-
- p0.l = lo(EVT14);
- p0.h = hi(EVT14);
- p1.l = _evt_up_evt14;
- p1.h = _evt_up_evt14;
- [p0] = p1;
- csync;
-
- raise 14;
-1:
- jump 1b;
-ENDPROC(_up_to_irq14)
-
-ENTRY(_evt_up_evt14)
-#ifdef CONFIG_DEBUG_HWERR
- r0 = (EVT_IVHW | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU);
- sti r0;
-#else
- cli r0;
-#endif
-#ifdef CONFIG_TRACE_IRQFLAGS
- [--sp] = rets;
- sp += -12;
- call _trace_hardirqs_off;
- sp += 12;
- rets = [sp++];
-#endif
- [--sp] = RETI;
- SP += 4;
-
- /* restore normal evt14 */
- p0.l = lo(EVT14);
- p0.h = hi(EVT14);
- p1.l = _evt_evt14;
- p1.h = _evt_evt14;
- [p0] = p1;
- csync;
-
- rts;
-ENDPROC(_evt_up_evt14)
-
-#endif
-
-#ifdef CONFIG_IPIPE
-
-_resume_kernel_from_int:
- r1 = LO(~0x8000) (Z);
- r1 = r0 & r1;
- r0 = 1;
- r0 = r1 - r0;
- r2 = r1 & r0;
- cc = r2 == 0;
- /* Sync the root stage only from the outer interrupt level. */
- if !cc jump .Lnosync;
- r0.l = ___ipipe_sync_root;
- r0.h = ___ipipe_sync_root;
- [--sp] = reti;
- [--sp] = rets;
- [--sp] = ( r7:4, p5:3 );
- SP += -12;
- call ___ipipe_call_irqtail
- SP += 12;
- ( r7:4, p5:3 ) = [sp++];
- rets = [sp++];
- reti = [sp++];
-.Lnosync:
- rts
-#elif defined(CONFIG_PREEMPT)
-
-_resume_kernel_from_int:
- /* check preempt_count */
- r7 = sp;
- r4.l = lo(ALIGN_PAGE_MASK);
- r4.h = hi(ALIGN_PAGE_MASK);
- r7 = r7 & r4;
- p5 = r7;
- r7 = [p5 + TI_PREEMPT];
- cc = r7 == 0x0;
- if !cc jump .Lreturn_to_kernel;
-.Lneed_schedule:
- r7 = [p5 + TI_FLAGS];
- r4.l = lo(_TIF_WORK_MASK);
- r4.h = hi(_TIF_WORK_MASK);
- r7 = r7 & r4;
- cc = BITTST(r7, TIF_NEED_RESCHED);
- if !cc jump .Lreturn_to_kernel;
- /*
- * let schedule done at level 15, otherwise sheduled process will run
- * at high level and block low level interrupt
- */
- r6 = reti; /* save reti */
- r5.l = .Lkernel_schedule;
- r5.h = .Lkernel_schedule;
- reti = r5;
- rti;
-.Lkernel_schedule:
- [--sp] = rets;
- sp += -12;
- pseudo_long_call _preempt_schedule_irq, p4;
- sp += 12;
- rets = [sp++];
-
- [--sp] = rets;
- sp += -12;
- /* up to irq14 so that reti after restore_all can return to irq15(kernel) */
- pseudo_long_call _up_to_irq14, p4;
- sp += 12;
- rets = [sp++];
-
- reti = r6; /* restore reti so that origin process can return to interrupted point */
-
- jump .Lneed_schedule;
-#else
-
-#define _resume_kernel_from_int .Lreturn_to_kernel
-#endif
-
-ENTRY(_return_from_int)
- /* If someone else already raised IRQ 15, do nothing. */
- csync;
- p2.l = lo(ILAT);
- p2.h = hi(ILAT);
- r0 = [p2];
- cc = bittst (r0, EVT_IVG15_P);
- if cc jump .Lreturn_to_kernel;
-
- /* if not return to user mode, get out */
- p2.l = lo(IPEND);
- p2.h = hi(IPEND);
- r0 = [p2];
- r1 = 0x17(Z);
- r2 = ~r1;
- r2.h = 0;
- r0 = r2 & r0;
- r1 = 1;
- r1 = r0 - r1;
- r2 = r0 & r1;
- cc = r2 == 0;
- if !cc jump _resume_kernel_from_int;
-
- /* Lower the interrupt level to 15. */
- p0.l = lo(EVT15);
- p0.h = hi(EVT15);
- p1.l = _schedule_and_signal_from_int;
- p1.h = _schedule_and_signal_from_int;
- [p0] = p1;
- csync;
-#if ANOMALY_05000281 || ANOMALY_05000461
- r0.l = lo(SAFE_USER_INSTRUCTION);
- r0.h = hi(SAFE_USER_INSTRUCTION);
- reti = r0;
-#endif
- r0 = 0x801f (z);
- STI r0;
- raise 15; /* raise evt15 to do signal or reschedule */
- rti;
-.Lreturn_to_kernel:
- rts;
-ENDPROC(_return_from_int)
-
-ENTRY(_lower_to_irq14)
-#if ANOMALY_05000281 || ANOMALY_05000461
- r0.l = lo(SAFE_USER_INSTRUCTION);
- r0.h = hi(SAFE_USER_INSTRUCTION);
- reti = r0;
-#endif
-
-#ifdef CONFIG_DEBUG_HWERR
- /* enable irq14 & hwerr interrupt, until we transition to _evt_evt14 */
- r0 = (EVT_IVG14 | EVT_IVHW | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU);
-#else
- /* Only enable irq14 interrupt, until we transition to _evt_evt14 */
- r0 = (EVT_IVG14 | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU);
-#endif
- sti r0;
- raise 14;
- rti;
-ENDPROC(_lower_to_irq14)
-
-ENTRY(_evt_evt14)
-#ifdef CONFIG_DEBUG_HWERR
- r0 = (EVT_IVHW | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU);
- sti r0;
-#else
- cli r0;
-#endif
-#ifdef CONFIG_TRACE_IRQFLAGS
- [--sp] = rets;
- sp += -12;
- call _trace_hardirqs_off;
- sp += 12;
- rets = [sp++];
-#endif
- [--sp] = RETI;
- SP += 4;
- rts;
-ENDPROC(_evt_evt14)
-
-ENTRY(_schedule_and_signal_from_int)
- /* To end up here, vector 15 was changed - so we have to change it
- * back.
- */
- p0.l = lo(EVT15);
- p0.h = hi(EVT15);
- p1.l = _evt_system_call;
- p1.h = _evt_system_call;
- [p0] = p1;
- csync;
-
- /* Set orig_p0 to -1 to indicate this isn't the end of a syscall. */
- r0 = -1 (x);
- [sp + PT_ORIG_P0] = r0;
-
- p1 = rets;
- [sp + PT_RESERVED] = p1;
-
-#ifdef CONFIG_TRACE_IRQFLAGS
- /* trace_hardirqs_on() checks if all irqs are disabled. But here IRQ 15
- * is turned on, so disable all irqs. */
- cli r0;
- sp += -12;
- call _trace_hardirqs_on;
- sp += 12;
-#endif
-#ifdef CONFIG_SMP
- GET_PDA(p0, r0); /* Fetch current PDA (can't migrate to other CPU here) */
- r0 = [p0 + PDA_IRQFLAGS];
-#else
- p0.l = _bfin_irq_flags;
- p0.h = _bfin_irq_flags;
- r0 = [p0];
-#endif
- sti r0;
-
- /* finish the userspace "atomic" functions for it */
- r1.l = lo(FIXED_CODE_END);
- r1.h = hi(FIXED_CODE_END);
- r2 = [sp + PT_PC];
- cc = r1 <= r2;
- if cc jump .Lresume_userspace (bp);
-
- r0 = sp;
- sp += -12;
-
- pseudo_long_call _finish_atomic_sections, p5;
- sp += 12;
- jump.s .Lresume_userspace;
-ENDPROC(_schedule_and_signal_from_int)
-
-ENTRY(_schedule_and_signal)
- SAVE_CONTEXT_SYSCALL
- /* To end up here, vector 15 was changed - so we have to change it
- * back.
- */
- p0.l = lo(EVT15);
- p0.h = hi(EVT15);
- p1.l = _evt_system_call;
- p1.h = _evt_system_call;
- [p0] = p1;
- csync;
- p0.l = 1f;
- p0.h = 1f;
- [sp + PT_RESERVED] = P0;
- call .Lresume_userspace;
-1:
- RESTORE_CONTEXT
- rti;
-ENDPROC(_schedule_and_signal)
-
-/* We handle this 100% in exception space - to reduce overhead
- * Only potiential problem is if the software buffer gets swapped out of the
- * CPLB table - then double fault. - so we don't let this happen in other places
- */
-#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND
-ENTRY(_ex_trace_buff_full)
- [--sp] = P3;
- [--sp] = P2;
- [--sp] = LC0;
- [--sp] = LT0;
- [--sp] = LB0;
- P5.L = _trace_buff_offset;
- P5.H = _trace_buff_offset;
- P3 = [P5]; /* trace_buff_offset */
- P5.L = lo(TBUFSTAT);
- P5.H = hi(TBUFSTAT);
- R7 = [P5];
- R7 <<= 1; /* double, since we need to read twice */
- LC0 = R7;
- R7 <<= 2; /* need to shift over again,
- * to get the number of bytes */
- P5.L = lo(TBUF);
- P5.H = hi(TBUF);
- R6 = ((1 << CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN)*1024) - 1;
-
- P2 = R7;
- P3 = P3 + P2;
- R7 = P3;
- R7 = R7 & R6;
- P3 = R7;
- P2.L = _trace_buff_offset;
- P2.H = _trace_buff_offset;
- [P2] = P3;
-
- P2.L = _software_trace_buff;
- P2.H = _software_trace_buff;
-
- LSETUP (.Lstart, .Lend) LC0;
-.Lstart:
- R7 = [P5]; /* read TBUF */
- P4 = P3 + P2;
- [P4] = R7;
- P3 += -4;
- R7 = P3;
- R7 = R7 & R6;
-.Lend:
- P3 = R7;
-
- LB0 = [sp++];
- LT0 = [sp++];
- LC0 = [sp++];
- P2 = [sp++];
- P3 = [sp++];
- jump _bfin_return_from_exception;
-ENDPROC(_ex_trace_buff_full)
-
-#if CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN == 4
-.data
-#else
-.section .l1.data.B
-#endif /* CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN */
-ENTRY(_trace_buff_offset)
- .long 0;
-ALIGN
-ENTRY(_software_trace_buff)
- .rept ((1 << CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN)*256);
- .long 0
- .endr
-#endif /* CONFIG_DEBUG_BFIN_HWTRACE_EXPAND */
-
-#ifdef CONFIG_EARLY_PRINTK
-__INIT
-ENTRY(_early_trap)
- SAVE_ALL_SYS
- trace_buffer_stop(p0,r0);
-
- ANOMALY_283_315_WORKAROUND(p4, r5)
-
- /* Turn caches off, to ensure we don't get double exceptions */
-
- P4.L = LO(IMEM_CONTROL);
- P4.H = HI(IMEM_CONTROL);
-
- R5 = [P4]; /* Control Register*/
- BITCLR(R5,ENICPLB_P);
- CSYNC; /* Disabling of CPLBs should be proceeded by a CSYNC */
- [P4] = R5;
- SSYNC;
-
- P4.L = LO(DMEM_CONTROL);
- P4.H = HI(DMEM_CONTROL);
- R5 = [P4];
- BITCLR(R5,ENDCPLB_P);
- CSYNC; /* Disabling of CPLBs should be proceeded by a CSYNC */
- [P4] = R5;
- SSYNC;
-
- r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */
- r1 = RETX;
-
- SP += -12;
- call _early_trap_c;
- SP += 12;
-ENDPROC(_early_trap)
-__FINIT
-#endif /* CONFIG_EARLY_PRINTK */
-
-/*
- * Put these in the kernel data section - that should always be covered by
- * a CPLB. This is needed to ensure we don't get double fault conditions
- */
-
-#ifdef CONFIG_SYSCALL_TAB_L1
-.section .l1.data
-#else
-.data
-#endif
-
-ENTRY(_ex_table)
- /* entry for each EXCAUSE[5:0]
- * This table must be in sync with the table in ./kernel/traps.c
- * EXCPT instruction can provide 4 bits of EXCAUSE, allowing 16 to be user defined
- */
- .long _ex_syscall /* 0x00 - User Defined - Linux Syscall */
- .long _ex_trap_c /* 0x01 - User Defined - Software breakpoint */
-#ifdef CONFIG_KGDB
- .long _ex_trap_c /* 0x02 - User Defined - KGDB initial connection
- and break signal trap */
-#else
- .long _ex_replaceable /* 0x02 - User Defined */
-#endif
- .long _ex_trap_c /* 0x03 - User Defined - userspace stack overflow */
- .long _ex_trap_c /* 0x04 - User Defined - dump trace buffer */
- .long _ex_replaceable /* 0x05 - User Defined */
- .long _ex_replaceable /* 0x06 - User Defined */
- .long _ex_replaceable /* 0x07 - User Defined */
- .long _ex_replaceable /* 0x08 - User Defined */
- .long _ex_replaceable /* 0x09 - User Defined */
- .long _ex_replaceable /* 0x0A - User Defined */
- .long _ex_replaceable /* 0x0B - User Defined */
- .long _ex_replaceable /* 0x0C - User Defined */
- .long _ex_replaceable /* 0x0D - User Defined */
- .long _ex_replaceable /* 0x0E - User Defined */
- .long _ex_replaceable /* 0x0F - User Defined */
- .long _ex_single_step /* 0x10 - HW Single step */
-#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND
- .long _ex_trace_buff_full /* 0x11 - Trace Buffer Full */
-#else
- .long _ex_trap_c /* 0x11 - Trace Buffer Full */
-#endif
- .long _ex_trap_c /* 0x12 - Reserved */
- .long _ex_trap_c /* 0x13 - Reserved */
- .long _ex_trap_c /* 0x14 - Reserved */
- .long _ex_trap_c /* 0x15 - Reserved */
- .long _ex_trap_c /* 0x16 - Reserved */
- .long _ex_trap_c /* 0x17 - Reserved */
- .long _ex_trap_c /* 0x18 - Reserved */
- .long _ex_trap_c /* 0x19 - Reserved */
- .long _ex_trap_c /* 0x1A - Reserved */
- .long _ex_trap_c /* 0x1B - Reserved */
- .long _ex_trap_c /* 0x1C - Reserved */
- .long _ex_trap_c /* 0x1D - Reserved */
- .long _ex_trap_c /* 0x1E - Reserved */
- .long _ex_trap_c /* 0x1F - Reserved */
- .long _ex_trap_c /* 0x20 - Reserved */
- .long _ex_trap_c /* 0x21 - Undefined Instruction */
- .long _ex_trap_c /* 0x22 - Illegal Instruction Combination */
- .long _ex_dviol /* 0x23 - Data CPLB Protection Violation */
- .long _ex_trap_c /* 0x24 - Data access misaligned */
- .long _ex_trap_c /* 0x25 - Unrecoverable Event */
- .long _ex_dmiss /* 0x26 - Data CPLB Miss */
- .long _ex_dmult /* 0x27 - Data CPLB Multiple Hits - Linux Trap Zero */
- .long _ex_trap_c /* 0x28 - Emulation Watchpoint */
- .long _ex_trap_c /* 0x29 - Instruction fetch access error (535 only) */
- .long _ex_trap_c /* 0x2A - Instruction fetch misaligned */
- .long _ex_trap_c /* 0x2B - Instruction CPLB protection Violation */
- .long _ex_icplb_miss /* 0x2C - Instruction CPLB miss */
- .long _ex_trap_c /* 0x2D - Instruction CPLB Multiple Hits */
- .long _ex_trap_c /* 0x2E - Illegal use of Supervisor Resource */
- .long _ex_trap_c /* 0x2E - Illegal use of Supervisor Resource */
- .long _ex_trap_c /* 0x2F - Reserved */
- .long _ex_trap_c /* 0x30 - Reserved */
- .long _ex_trap_c /* 0x31 - Reserved */
- .long _ex_trap_c /* 0x32 - Reserved */
- .long _ex_trap_c /* 0x33 - Reserved */
- .long _ex_trap_c /* 0x34 - Reserved */
- .long _ex_trap_c /* 0x35 - Reserved */
- .long _ex_trap_c /* 0x36 - Reserved */
- .long _ex_trap_c /* 0x37 - Reserved */
- .long _ex_trap_c /* 0x38 - Reserved */
- .long _ex_trap_c /* 0x39 - Reserved */
- .long _ex_trap_c /* 0x3A - Reserved */
- .long _ex_trap_c /* 0x3B - Reserved */
- .long _ex_trap_c /* 0x3C - Reserved */
- .long _ex_trap_c /* 0x3D - Reserved */
- .long _ex_trap_c /* 0x3E - Reserved */
- .long _ex_trap_c /* 0x3F - Reserved */
-END(_ex_table)
-
-ENTRY(_sys_call_table)
- .long _sys_restart_syscall /* 0 */
- .long _sys_exit
- .long _sys_ni_syscall /* fork */
- .long _sys_read
- .long _sys_write
- .long _sys_open /* 5 */
- .long _sys_close
- .long _sys_ni_syscall /* old waitpid */
- .long _sys_creat
- .long _sys_link
- .long _sys_unlink /* 10 */
- .long _sys_execve
- .long _sys_chdir
- .long _sys_time
- .long _sys_mknod
- .long _sys_chmod /* 15 */
- .long _sys_chown /* chown16 */
- .long _sys_ni_syscall /* old break syscall holder */
- .long _sys_ni_syscall /* old stat */
- .long _sys_lseek
- .long _sys_getpid /* 20 */
- .long _sys_mount
- .long _sys_ni_syscall /* old umount */
- .long _sys_setuid
- .long _sys_getuid
- .long _sys_stime /* 25 */
- .long _sys_ptrace
- .long _sys_alarm
- .long _sys_ni_syscall /* old fstat */
- .long _sys_pause
- .long _sys_ni_syscall /* old utime */ /* 30 */
- .long _sys_ni_syscall /* old stty syscall holder */
- .long _sys_ni_syscall /* old gtty syscall holder */
- .long _sys_access
- .long _sys_nice
- .long _sys_ni_syscall /* 35 */ /* old ftime syscall holder */
- .long _sys_sync
- .long _sys_kill
- .long _sys_rename
- .long _sys_mkdir
- .long _sys_rmdir /* 40 */
- .long _sys_dup
- .long _sys_pipe
- .long _sys_times
- .long _sys_ni_syscall /* old prof syscall holder */
- .long _sys_brk /* 45 */
- .long _sys_setgid
- .long _sys_getgid
- .long _sys_ni_syscall /* old sys_signal */
- .long _sys_geteuid /* geteuid16 */
- .long _sys_getegid /* getegid16 */ /* 50 */
- .long _sys_acct
- .long _sys_umount /* recycled never used phys() */
- .long _sys_ni_syscall /* old lock syscall holder */
- .long _sys_ioctl
- .long _sys_fcntl /* 55 */
- .long _sys_ni_syscall /* old mpx syscall holder */
- .long _sys_setpgid
- .long _sys_ni_syscall /* old ulimit syscall holder */
- .long _sys_ni_syscall /* old old uname */
- .long _sys_umask /* 60 */
- .long _sys_chroot
- .long _sys_ustat
- .long _sys_dup2
- .long _sys_getppid
- .long _sys_getpgrp /* 65 */
- .long _sys_setsid
- .long _sys_ni_syscall /* old sys_sigaction */
- .long _sys_sgetmask
- .long _sys_ssetmask
- .long _sys_setreuid /* setreuid16 */ /* 70 */
- .long _sys_setregid /* setregid16 */
- .long _sys_ni_syscall /* old sys_sigsuspend */
- .long _sys_ni_syscall /* old sys_sigpending */
- .long _sys_sethostname
- .long _sys_setrlimit /* 75 */
- .long _sys_ni_syscall /* old getrlimit */
- .long _sys_getrusage
- .long _sys_gettimeofday
- .long _sys_settimeofday
- .long _sys_getgroups /* getgroups16 */ /* 80 */
- .long _sys_setgroups /* setgroups16 */
- .long _sys_ni_syscall /* old_select */
- .long _sys_symlink
- .long _sys_ni_syscall /* old lstat */
- .long _sys_readlink /* 85 */
- .long _sys_uselib
- .long _sys_ni_syscall /* sys_swapon */
- .long _sys_reboot
- .long _sys_ni_syscall /* old_readdir */
- .long _sys_ni_syscall /* sys_mmap */ /* 90 */
- .long _sys_munmap
- .long _sys_truncate
- .long _sys_ftruncate
- .long _sys_fchmod
- .long _sys_fchown /* fchown16 */ /* 95 */
- .long _sys_getpriority
- .long _sys_setpriority
- .long _sys_ni_syscall /* old profil syscall holder */
- .long _sys_statfs
- .long _sys_fstatfs /* 100 */
- .long _sys_ni_syscall
- .long _sys_ni_syscall /* old sys_socketcall */
- .long _sys_syslog
- .long _sys_setitimer
- .long _sys_getitimer /* 105 */
- .long _sys_newstat
- .long _sys_newlstat
- .long _sys_newfstat
- .long _sys_ni_syscall /* old uname */
- .long _sys_ni_syscall /* iopl for i386 */ /* 110 */
- .long _sys_vhangup
- .long _sys_ni_syscall /* obsolete idle() syscall */
- .long _sys_ni_syscall /* vm86old for i386 */
- .long _sys_wait4
- .long _sys_ni_syscall /* 115 */ /* sys_swapoff */
- .long _sys_sysinfo
- .long _sys_ni_syscall /* old sys_ipc */
- .long _sys_fsync
- .long _sys_ni_syscall /* old sys_sigreturn */
- .long _bfin_clone /* 120 */
- .long _sys_setdomainname
- .long _sys_newuname
- .long _sys_ni_syscall /* old sys_modify_ldt */
- .long _sys_adjtimex
- .long _sys_mprotect /* 125 */
- .long _sys_ni_syscall /* old sys_sigprocmask */
- .long _sys_ni_syscall /* old "creat_module" */
- .long _sys_init_module
- .long _sys_delete_module
- .long _sys_ni_syscall /* 130: old "get_kernel_syms" */
- .long _sys_quotactl
- .long _sys_getpgid
- .long _sys_fchdir
- .long _sys_bdflush
- .long _sys_ni_syscall /* 135 */ /* sys_sysfs */
- .long _sys_personality
- .long _sys_ni_syscall /* for afs_syscall */
- .long _sys_setfsuid /* setfsuid16 */
- .long _sys_setfsgid /* setfsgid16 */
- .long _sys_llseek /* 140 */
- .long _sys_getdents
- .long _sys_ni_syscall /* sys_select */
- .long _sys_flock
- .long _sys_msync
- .long _sys_readv /* 145 */
- .long _sys_writev
- .long _sys_getsid
- .long _sys_fdatasync
- .long _sys_sysctl
- .long _sys_mlock /* 150 */
- .long _sys_munlock
- .long _sys_mlockall
- .long _sys_munlockall
- .long _sys_sched_setparam
- .long _sys_sched_getparam /* 155 */
- .long _sys_sched_setscheduler
- .long _sys_sched_getscheduler
- .long _sys_sched_yield
- .long _sys_sched_get_priority_max
- .long _sys_sched_get_priority_min /* 160 */
- .long _sys_sched_rr_get_interval
- .long _sys_nanosleep
- .long _sys_mremap
- .long _sys_setresuid /* setresuid16 */
- .long _sys_getresuid /* getresuid16 */ /* 165 */
- .long _sys_ni_syscall /* for vm86 */
- .long _sys_ni_syscall /* old "query_module" */
- .long _sys_ni_syscall /* sys_poll */
- .long _sys_ni_syscall /* old nfsservctl */
- .long _sys_setresgid /* setresgid16 */ /* 170 */
- .long _sys_getresgid /* getresgid16 */
- .long _sys_prctl
- .long _sys_rt_sigreturn
- .long _sys_rt_sigaction
- .long _sys_rt_sigprocmask /* 175 */
- .long _sys_rt_sigpending
- .long _sys_rt_sigtimedwait
- .long _sys_rt_sigqueueinfo
- .long _sys_rt_sigsuspend
- .long _sys_pread64 /* 180 */
- .long _sys_pwrite64
- .long _sys_lchown /* lchown16 */
- .long _sys_getcwd
- .long _sys_capget
- .long _sys_capset /* 185 */
- .long _sys_sigaltstack
- .long _sys_sendfile
- .long _sys_ni_syscall /* streams1 */
- .long _sys_ni_syscall /* streams2 */
- .long _sys_vfork /* 190 */
- .long _sys_getrlimit
- .long _sys_mmap_pgoff
- .long _sys_truncate64
- .long _sys_ftruncate64
- .long _sys_stat64 /* 195 */
- .long _sys_lstat64
- .long _sys_fstat64
- .long _sys_chown
- .long _sys_getuid
- .long _sys_getgid /* 200 */
- .long _sys_geteuid
- .long _sys_getegid
- .long _sys_setreuid
- .long _sys_setregid
- .long _sys_getgroups /* 205 */
- .long _sys_setgroups
- .long _sys_fchown
- .long _sys_setresuid
- .long _sys_getresuid
- .long _sys_setresgid /* 210 */
- .long _sys_getresgid
- .long _sys_lchown
- .long _sys_setuid
- .long _sys_setgid
- .long _sys_setfsuid /* 215 */
- .long _sys_setfsgid
- .long _sys_pivot_root
- .long _sys_mincore
- .long _sys_madvise
- .long _sys_getdents64 /* 220 */
- .long _sys_fcntl64
- .long _sys_ni_syscall /* reserved for TUX */
- .long _sys_ni_syscall
- .long _sys_gettid
- .long _sys_readahead /* 225 */
- .long _sys_setxattr
- .long _sys_lsetxattr
- .long _sys_fsetxattr
- .long _sys_getxattr
- .long _sys_lgetxattr /* 230 */
- .long _sys_fgetxattr
- .long _sys_listxattr
- .long _sys_llistxattr
- .long _sys_flistxattr
- .long _sys_removexattr /* 235 */
- .long _sys_lremovexattr
- .long _sys_fremovexattr
- .long _sys_tkill
- .long _sys_sendfile64
- .long _sys_futex /* 240 */
- .long _sys_sched_setaffinity
- .long _sys_sched_getaffinity
- .long _sys_ni_syscall /* sys_set_thread_area */
- .long _sys_ni_syscall /* sys_get_thread_area */
- .long _sys_io_setup /* 245 */
- .long _sys_io_destroy
- .long _sys_io_getevents
- .long _sys_io_submit
- .long _sys_io_cancel
- .long _sys_ni_syscall /* 250 */ /* sys_alloc_hugepages */
- .long _sys_ni_syscall /* sys_freec_hugepages */
- .long _sys_exit_group
- .long _sys_lookup_dcookie
- .long _sys_bfin_spinlock
- .long _sys_epoll_create /* 255 */
- .long _sys_epoll_ctl
- .long _sys_epoll_wait
- .long _sys_ni_syscall /* remap_file_pages */
- .long _sys_set_tid_address
- .long _sys_timer_create /* 260 */
- .long _sys_timer_settime
- .long _sys_timer_gettime
- .long _sys_timer_getoverrun
- .long _sys_timer_delete
- .long _sys_clock_settime /* 265 */
- .long _sys_clock_gettime
- .long _sys_clock_getres
- .long _sys_clock_nanosleep
- .long _sys_statfs64
- .long _sys_fstatfs64 /* 270 */
- .long _sys_tgkill
- .long _sys_utimes
- .long _sys_fadvise64_64
- .long _sys_ni_syscall /* vserver */
- .long _sys_mbind /* 275 */
- .long _sys_ni_syscall /* get_mempolicy */
- .long _sys_ni_syscall /* set_mempolicy */
- .long _sys_mq_open
- .long _sys_mq_unlink
- .long _sys_mq_timedsend /* 280 */
- .long _sys_mq_timedreceive
- .long _sys_mq_notify
- .long _sys_mq_getsetattr
- .long _sys_ni_syscall /* kexec_load */
- .long _sys_waitid /* 285 */
- .long _sys_add_key
- .long _sys_request_key
- .long _sys_keyctl
- .long _sys_ioprio_set
- .long _sys_ioprio_get /* 290 */
- .long _sys_inotify_init
- .long _sys_inotify_add_watch
- .long _sys_inotify_rm_watch
- .long _sys_ni_syscall /* migrate_pages */
- .long _sys_openat /* 295 */
- .long _sys_mkdirat
- .long _sys_mknodat
- .long _sys_fchownat
- .long _sys_futimesat
- .long _sys_fstatat64 /* 300 */
- .long _sys_unlinkat
- .long _sys_renameat
- .long _sys_linkat
- .long _sys_symlinkat
- .long _sys_readlinkat /* 305 */
- .long _sys_fchmodat
- .long _sys_faccessat
- .long _sys_pselect6
- .long _sys_ppoll
- .long _sys_unshare /* 310 */
- .long _sys_sram_alloc
- .long _sys_sram_free
- .long _sys_dma_memcpy
- .long _sys_accept
- .long _sys_bind /* 315 */
- .long _sys_connect
- .long _sys_getpeername
- .long _sys_getsockname
- .long _sys_getsockopt
- .long _sys_listen /* 320 */
- .long _sys_recv
- .long _sys_recvfrom
- .long _sys_recvmsg
- .long _sys_send
- .long _sys_sendmsg /* 325 */
- .long _sys_sendto
- .long _sys_setsockopt
- .long _sys_shutdown
- .long _sys_socket
- .long _sys_socketpair /* 330 */
- .long _sys_semctl
- .long _sys_semget
- .long _sys_semop
- .long _sys_msgctl
- .long _sys_msgget /* 335 */
- .long _sys_msgrcv
- .long _sys_msgsnd
- .long _sys_shmat
- .long _sys_shmctl
- .long _sys_shmdt /* 340 */
- .long _sys_shmget
- .long _sys_splice
- .long _sys_sync_file_range
- .long _sys_tee
- .long _sys_vmsplice /* 345 */
- .long _sys_epoll_pwait
- .long _sys_utimensat
- .long _sys_signalfd
- .long _sys_timerfd_create
- .long _sys_eventfd /* 350 */
- .long _sys_pread64
- .long _sys_pwrite64
- .long _sys_fadvise64
- .long _sys_set_robust_list
- .long _sys_get_robust_list /* 355 */
- .long _sys_fallocate
- .long _sys_semtimedop
- .long _sys_timerfd_settime
- .long _sys_timerfd_gettime
- .long _sys_signalfd4 /* 360 */
- .long _sys_eventfd2
- .long _sys_epoll_create1
- .long _sys_dup3
- .long _sys_pipe2
- .long _sys_inotify_init1 /* 365 */
- .long _sys_preadv
- .long _sys_pwritev
- .long _sys_rt_tgsigqueueinfo
- .long _sys_perf_event_open
- .long _sys_recvmmsg /* 370 */
- .long _sys_fanotify_init
- .long _sys_fanotify_mark
- .long _sys_prlimit64
- .long _sys_cacheflush
- .long _sys_name_to_handle_at /* 375 */
- .long _sys_open_by_handle_at
- .long _sys_clock_adjtime
- .long _sys_syncfs
- .long _sys_setns
- .long _sys_sendmmsg /* 380 */
- .long _sys_process_vm_readv
- .long _sys_process_vm_writev
- .long _sys_kcmp
- .long _sys_finit_module
- .long _sys_sched_setattr /* 385 */
- .long _sys_sched_getattr
- .long _sys_renameat2
- .long _sys_seccomp
- .long _sys_getrandom
- .long _sys_memfd_create /* 390 */
- .long _sys_bpf
- .long _sys_execveat
-
- .rept NR_syscalls-(.-_sys_call_table)/4
- .long _sys_ni_syscall
- .endr
-END(_sys_call_table)
+++ /dev/null
-/*
- * Common Blackfin startup code
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/linkage.h>
-#include <linux/init.h>
-#include <asm/blackfin.h>
-#include <asm/thread_info.h>
-#include <asm/trace.h>
-#include <asm/asm-offsets.h>
-
-__INIT
-
-ENTRY(__init_clear_bss)
- r2 = r2 - r1;
- cc = r2 == 0;
- if cc jump .L_bss_done;
- r2 >>= 2;
- p1 = r1;
- p2 = r2;
- lsetup (1f, 1f) lc0 = p2;
-1: [p1++] = r0;
-.L_bss_done:
- rts;
-ENDPROC(__init_clear_bss)
-
-ENTRY(__start)
- /* R0: argument of command line string, passed from uboot, save it */
- R7 = R0;
-
- /* Enable Cycle Counter and Nesting Of Interrupts */
-#ifdef CONFIG_BFIN_SCRATCH_REG_CYCLES
- R0 = SYSCFG_SNEN;
-#else
- R0 = SYSCFG_SNEN | SYSCFG_CCEN;
-#endif
- SYSCFG = R0;
-
- /* Optimization register tricks: keep a base value in the
- * reserved P registers so we use the load/store with an
- * offset syntax. R0 = [P5 + <constant>];
- * P5 - core MMR base
- * R6 - 0
- */
- r6 = 0;
- p5.l = 0;
- p5.h = hi(COREMMR_BASE);
-
- /* Zero out registers required by Blackfin ABI */
-
- /* Disable circular buffers */
- L0 = r6;
- L1 = r6;
- L2 = r6;
- L3 = r6;
-
- /* Disable hardware loops in case we were started by 'go' */
- LC0 = r6;
- LC1 = r6;
-
- /*
- * Clear ITEST_COMMAND and DTEST_COMMAND registers,
- * Leaving these as non-zero can confuse the emulator
- */
- [p5 + (DTEST_COMMAND - COREMMR_BASE)] = r6;
- [p5 + (ITEST_COMMAND - COREMMR_BASE)] = r6;
- CSYNC;
-
- trace_buffer_init(p0,r0);
-
- /* Turn off the icache */
- r1 = [p5 + (IMEM_CONTROL - COREMMR_BASE)];
- BITCLR (r1, ENICPLB_P);
- [p5 + (IMEM_CONTROL - COREMMR_BASE)] = r1;
- SSYNC;
-
- /* Turn off the dcache */
- r1 = [p5 + (DMEM_CONTROL - COREMMR_BASE)];
- BITCLR (r1, ENDCPLB_P);
- [p5 + (DMEM_CONTROL - COREMMR_BASE)] = r1;
- SSYNC;
-
- /* in case of double faults, save a few things */
- p1.l = _initial_pda;
- p1.h = _initial_pda;
- r4 = RETX;
-#ifdef CONFIG_DEBUG_DOUBLEFAULT
- /* Only save these if we are storing them,
- * This happens here, since L1 gets clobbered
- * below
- */
- GET_PDA(p0, r0);
- r0 = [p0 + PDA_DF_RETX];
- r1 = [p0 + PDA_DF_DCPLB];
- r2 = [p0 + PDA_DF_ICPLB];
- r3 = [p0 + PDA_DF_SEQSTAT];
- [p1 + PDA_INIT_DF_RETX] = r0;
- [p1 + PDA_INIT_DF_DCPLB] = r1;
- [p1 + PDA_INIT_DF_ICPLB] = r2;
- [p1 + PDA_INIT_DF_SEQSTAT] = r3;
-#endif
- [p1 + PDA_INIT_RETX] = r4;
-
- /* Initialize stack pointer */
- sp.l = _init_thread_union + THREAD_SIZE;
- sp.h = _init_thread_union + THREAD_SIZE;
- fp = sp;
- usp = sp;
-
-#ifdef CONFIG_EARLY_PRINTK
- call _init_early_exception_vectors;
- r0 = (EVT_IVHW | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU);
- sti r0;
-#endif
-
- r0 = r6;
- /* Zero out all of the fun bss regions */
-#if L1_DATA_A_LENGTH > 0
- r1.l = __sbss_l1;
- r1.h = __sbss_l1;
- r2.l = __ebss_l1;
- r2.h = __ebss_l1;
- call __init_clear_bss
-#endif
-#if L1_DATA_B_LENGTH > 0
- r1.l = __sbss_b_l1;
- r1.h = __sbss_b_l1;
- r2.l = __ebss_b_l1;
- r2.h = __ebss_b_l1;
- call __init_clear_bss
-#endif
-#if L2_LENGTH > 0
- r1.l = __sbss_l2;
- r1.h = __sbss_l2;
- r2.l = __ebss_l2;
- r2.h = __ebss_l2;
- call __init_clear_bss
-#endif
- r1.l = ___bss_start;
- r1.h = ___bss_start;
- r2.l = ___bss_stop;
- r2.h = ___bss_stop;
- call __init_clear_bss
-
- /* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
- call _bfin_relocate_l1_mem;
-
-#ifdef CONFIG_ROMKERNEL
- call _bfin_relocate_xip_data;
-#endif
-
-#ifdef CONFIG_BFIN_KERNEL_CLOCK
- /* Only use on-chip scratch space for stack when absolutely required
- * to avoid Anomaly 05000227 ... we know the init_clocks() func only
- * uses L1 text and stack space and no other memory region.
- */
-# define KERNEL_CLOCK_STACK (L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12)
- sp.l = lo(KERNEL_CLOCK_STACK);
- sp.h = hi(KERNEL_CLOCK_STACK);
- call _init_clocks;
- sp = usp; /* usp hasn't been touched, so restore from there */
-#endif
-
- /* This section keeps the processor in supervisor mode
- * during kernel boot. Switches to user mode at end of boot.
- * See page 3-9 of Hardware Reference manual for documentation.
- */
-
- /* EVT15 = _real_start */
-
- p1.l = _real_start;
- p1.h = _real_start;
- [p5 + (EVT15 - COREMMR_BASE)] = p1;
- csync;
-
-#ifdef CONFIG_EARLY_PRINTK
- r0 = (EVT_IVG15 | EVT_IVHW | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU) (z);
-#else
- r0 = EVT_IVG15 (z);
-#endif
- sti r0;
-
- raise 15;
-#ifdef CONFIG_EARLY_PRINTK
- p0.l = _early_trap;
- p0.h = _early_trap;
-#else
- p0.l = .LWAIT_HERE;
- p0.h = .LWAIT_HERE;
-#endif
- reti = p0;
-#if ANOMALY_05000281
- nop; nop; nop;
-#endif
- rti;
-
-.LWAIT_HERE:
- jump .LWAIT_HERE;
-ENDPROC(__start)
-
-/* A little BF561 glue ... */
-#ifndef WDOG_CTL
-# define WDOG_CTL WDOGA_CTL
-#endif
-
-ENTRY(_real_start)
- /* Enable nested interrupts */
- [--sp] = reti;
- /* watchdog off for now */
- p0.l = lo(WDOG_CTL);
- p0.h = hi(WDOG_CTL);
- r0 = 0xAD6(z);
- w[p0] = r0;
- ssync;
- /* Pass the u-boot arguments to the global value command line */
- R0 = R7;
- call _cmdline_init;
-
- sp += -12 + 4; /* +4 is for reti loading above */
- call _init_pda
- sp += 12;
- jump.l _start_kernel;
-ENDPROC(_real_start)
-
-__FINIT
+++ /dev/null
-/*
- * Interrupt Entries
- *
- * Copyright 2005-2009 Analog Devices Inc.
- * D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>
- * Kenneth Albanowski <kjahds@kjahds.com>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <asm/blackfin.h>
-#include <mach/irq.h>
-#include <linux/linkage.h>
-#include <asm/entry.h>
-#include <asm/asm-offsets.h>
-#include <asm/trace.h>
-#include <asm/traps.h>
-#include <asm/thread_info.h>
-
-#include <asm/context.S>
-
-.extern _ret_from_exception
-
-#ifdef CONFIG_I_ENTRY_L1
-.section .l1.text
-#else
-.text
-#endif
-
-.align 4 /* just in case */
-
-/* Common interrupt entry code. First we do CLI, then push
- * RETI, to keep interrupts disabled, but to allow this state to be changed
- * by local_bh_enable.
- * R0 contains the interrupt number, while R1 may contain the value of IPEND,
- * or garbage if IPEND won't be needed by the ISR. */
-__common_int_entry:
- [--sp] = fp;
- [--sp] = usp;
-
- [--sp] = i0;
- [--sp] = i1;
- [--sp] = i2;
- [--sp] = i3;
-
- [--sp] = m0;
- [--sp] = m1;
- [--sp] = m2;
- [--sp] = m3;
-
- [--sp] = l0;
- [--sp] = l1;
- [--sp] = l2;
- [--sp] = l3;
-
- [--sp] = b0;
- [--sp] = b1;
- [--sp] = b2;
- [--sp] = b3;
- [--sp] = a0.x;
- [--sp] = a0.w;
- [--sp] = a1.x;
- [--sp] = a1.w;
-
- [--sp] = LC0;
- [--sp] = LC1;
- [--sp] = LT0;
- [--sp] = LT1;
- [--sp] = LB0;
- [--sp] = LB1;
-
- [--sp] = ASTAT;
-
- [--sp] = r0; /* Skip reserved */
- [--sp] = RETS;
- r2 = RETI;
- [--sp] = r2;
- [--sp] = RETX;
- [--sp] = RETN;
- [--sp] = RETE;
- [--sp] = SEQSTAT;
- [--sp] = r1; /* IPEND - R1 may or may not be set up before jumping here. */
-
- /* Switch to other method of keeping interrupts disabled. */
-#ifdef CONFIG_DEBUG_HWERR
- r1 = 0x3f;
- sti r1;
-#else
- cli r1;
-#endif
-#ifdef CONFIG_TRACE_IRQFLAGS
- [--sp] = r0;
- sp += -12;
- call _trace_hardirqs_off;
- sp += 12;
- r0 = [sp++];
-#endif
- [--sp] = RETI; /* orig_pc */
- /* Clear all L registers. */
- r1 = 0 (x);
- l0 = r1;
- l1 = r1;
- l2 = r1;
- l3 = r1;
-#ifdef CONFIG_FRAME_POINTER
- fp = 0;
-#endif
-
- ANOMALY_283_315_WORKAROUND(p5, r7)
-
- r1 = sp;
- SP += -12;
-#ifdef CONFIG_IPIPE
- call ___ipipe_grab_irq
- SP += 12;
- cc = r0 == 0;
- if cc jump .Lcommon_restore_context;
-#else /* CONFIG_IPIPE */
-
-#ifdef CONFIG_PREEMPT
- r7 = sp;
- r4.l = lo(ALIGN_PAGE_MASK);
- r4.h = hi(ALIGN_PAGE_MASK);
- r7 = r7 & r4;
- p5 = r7;
- r7 = [p5 + TI_PREEMPT]; /* get preempt count */
- r7 += 1; /* increment it */
- [p5 + TI_PREEMPT] = r7;
-#endif
- pseudo_long_call _do_irq, p2;
-
-#ifdef CONFIG_PREEMPT
- r7 += -1;
- [p5 + TI_PREEMPT] = r7; /* restore preempt count */
-#endif
-
- SP += 12;
-#endif /* CONFIG_IPIPE */
- pseudo_long_call _return_from_int, p2;
-.Lcommon_restore_context:
- RESTORE_CONTEXT
- rti;
-
-/* interrupt routine for ivhw - 5 */
-ENTRY(_evt_ivhw)
- /* In case a single action kicks off multiple memory transactions, (like
- * a cache line fetch, - this can cause multiple hardware errors, let's
- * catch them all. First - make sure all the actions are complete, and
- * the core sees the hardware errors.
- */
- SSYNC;
- SSYNC;
-
- SAVE_ALL_SYS
-#ifdef CONFIG_FRAME_POINTER
- fp = 0;
-#endif
-
- ANOMALY_283_315_WORKAROUND(p5, r7)
-
- /* Handle all stacked hardware errors
- * To make sure we don't hang forever, only do it 10 times
- */
- R0 = 0;
- R2 = 10;
-1:
- P0.L = LO(ILAT);
- P0.H = HI(ILAT);
- R1 = [P0];
- CC = BITTST(R1, EVT_IVHW_P);
- IF ! CC JUMP 2f;
- /* OK a hardware error is pending - clear it */
- R1 = EVT_IVHW_P;
- [P0] = R1;
- R0 += 1;
- CC = R1 == R2;
- if CC JUMP 2f;
- JUMP 1b;
-2:
- # We are going to dump something out, so make sure we print IPEND properly
- p2.l = lo(IPEND);
- p2.h = hi(IPEND);
- r0 = [p2];
- [sp + PT_IPEND] = r0;
-
- /* set the EXCAUSE to HWERR for trap_c */
- r0 = [sp + PT_SEQSTAT];
- R1.L = LO(VEC_HWERR);
- R1.H = HI(VEC_HWERR);
- R0 = R0 | R1;
- [sp + PT_SEQSTAT] = R0;
-
- r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */
- SP += -12;
- pseudo_long_call _trap_c, p5;
- SP += 12;
-
-#ifdef EBIU_ERRMST
- /* make sure EBIU_ERRMST is clear */
- p0.l = LO(EBIU_ERRMST);
- p0.h = HI(EBIU_ERRMST);
- r0.l = (CORE_ERROR | CORE_MERROR);
- w[p0] = r0.l;
-#endif
-
- pseudo_long_call _ret_from_exception, p2;
-
-.Lcommon_restore_all_sys:
- RESTORE_ALL_SYS
- rti;
-ENDPROC(_evt_ivhw)
-
-/* Interrupt routine for evt2 (NMI).
- * For inner circle type details, please see:
- * http://docs.blackfin.uclinux.org/doku.php?id=linux-kernel:nmi
- */
-ENTRY(_evt_nmi)
-#ifndef CONFIG_NMI_WATCHDOG
-.weak _evt_nmi
-#else
- /* Not take account of CPLBs, this handler will not return */
- SAVE_ALL_SYS
- r0 = sp;
- r1 = retn;
- [sp + PT_PC] = r1;
- trace_buffer_save(p4,r5);
-
- ANOMALY_283_315_WORKAROUND(p4, r5)
-
- SP += -12;
- call _do_nmi;
- SP += 12;
-1:
- jump 1b;
-#endif
- rtn;
-ENDPROC(_evt_nmi)
-
-/* interrupt routine for core timer - 6 */
-ENTRY(_evt_timer)
- TIMER_INTERRUPT_ENTRY(EVT_IVTMR_P)
-
-/* interrupt routine for evt7 - 7 */
-ENTRY(_evt_evt7)
- INTERRUPT_ENTRY(EVT_IVG7_P)
-ENTRY(_evt_evt8)
- INTERRUPT_ENTRY(EVT_IVG8_P)
-ENTRY(_evt_evt9)
- INTERRUPT_ENTRY(EVT_IVG9_P)
-ENTRY(_evt_evt10)
- INTERRUPT_ENTRY(EVT_IVG10_P)
-ENTRY(_evt_evt11)
- INTERRUPT_ENTRY(EVT_IVG11_P)
-ENTRY(_evt_evt12)
- INTERRUPT_ENTRY(EVT_IVG12_P)
-ENTRY(_evt_evt13)
- INTERRUPT_ENTRY(EVT_IVG13_P)
-
-
- /* interrupt routine for system_call - 15 */
-ENTRY(_evt_system_call)
- SAVE_CONTEXT_SYSCALL
-#ifdef CONFIG_FRAME_POINTER
- fp = 0;
-#endif
- pseudo_long_call _system_call, p2;
- jump .Lcommon_restore_context;
-ENDPROC(_evt_system_call)
-
-#ifdef CONFIG_IPIPE
-/*
- * __ipipe_call_irqtail: lowers the current priority level to EVT15
- * before running a user-defined routine, then raises the priority
- * level to EVT14 to prepare the caller for a normal interrupt
- * return through RTI.
- *
- * We currently use this feature in two occasions:
- *
- * - before branching to __ipipe_irq_tail_hook as requested by a high
- * priority domain after the pipeline delivered an interrupt,
- * e.g. such as Xenomai, in order to start its rescheduling
- * procedure, since we may not switch tasks when IRQ levels are
- * nested on the Blackfin, so we have to fake an interrupt return
- * so that we may reschedule immediately.
- *
- * - before branching to __ipipe_sync_root(), in order to play any interrupt
- * pending for the root domain (i.e. the Linux kernel). This lowers
- * the core priority level enough so that Linux IRQ handlers may
- * never delay interrupts handled by high priority domains; we defer
- * those handlers until this point instead. This is a substitute
- * to using a threaded interrupt model for the Linux kernel.
- *
- * r0: address of user-defined routine
- * context: caller must have preempted EVT15, hw interrupts must be off.
- */
-ENTRY(___ipipe_call_irqtail)
- p0 = r0;
- r0.l = 1f;
- r0.h = 1f;
- reti = r0;
- rti;
-1:
- [--sp] = rets;
- [--sp] = ( r7:4, p5:3 );
- sp += -12;
- call (p0);
- sp += 12;
- ( r7:4, p5:3 ) = [sp++];
- rets = [sp++];
-
-#ifdef CONFIG_DEBUG_HWERR
- /* enable irq14 & hwerr interrupt, until we transition to _evt_evt14 */
- r0 = (EVT_IVG14 | EVT_IVHW | \
- EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU);
-#else
- /* Only enable irq14 interrupt, until we transition to _evt_evt14 */
- r0 = (EVT_IVG14 | \
- EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU);
-#endif
- sti r0;
- raise 14; /* Branches to _evt_evt14 */
-2:
- jump 2b; /* Likely paranoid. */
-ENDPROC(___ipipe_call_irqtail)
-
-#endif /* CONFIG_IPIPE */
+++ /dev/null
-/*
- * Set up the interrupt priorities
- *
- * Copyright 2004-2009 Analog Devices Inc.
- * 2003 Bas Vermeulen <bas@buyways.nl>
- * 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
- * 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
- * 1999 D. Jeff Dionne <jeff@uclinux.org>
- * 1996 Roman Zippel
- *
- * Licensed under the GPL-2
- */
-
-#include <linux/module.h>
-#include <linux/kernel_stat.h>
-#include <linux/seq_file.h>
-#include <linux/irq.h>
-#include <linux/sched.h>
-#include <linux/sched/debug.h>
-#include <linux/syscore_ops.h>
-#include <asm/delay.h>
-#ifdef CONFIG_IPIPE
-#include <linux/ipipe.h>
-#endif
-#include <asm/traps.h>
-#include <asm/blackfin.h>
-#include <asm/irq_handler.h>
-#include <asm/dpmc.h>
-#include <asm/traps.h>
-#include <asm/gpio.h>
-
-/*
- * NOTES:
- * - we have separated the physical Hardware interrupt from the
- * levels that the LINUX kernel sees (see the description in irq.h)
- * -
- */
-
-#ifndef CONFIG_SMP
-/* Initialize this to an actual value to force it into the .data
- * section so that we know it is properly initialized at entry into
- * the kernel but before bss is initialized to zero (which is where
- * it would live otherwise). The 0x1f magic represents the IRQs we
- * cannot actually mask out in hardware.
- */
-unsigned long bfin_irq_flags = 0x1f;
-EXPORT_SYMBOL(bfin_irq_flags);
-#endif
-
-#ifdef CONFIG_PM
-unsigned long bfin_sic_iwr[3]; /* Up to 3 SIC_IWRx registers */
-unsigned vr_wakeup;
-#endif
-
-#ifndef SEC_GCTL
-static struct ivgx {
- /* irq number for request_irq, available in mach-bf5xx/irq.h */
- unsigned int irqno;
- /* corresponding bit in the SIC_ISR register */
- unsigned int isrflag;
-} ivg_table[NR_PERI_INTS];
-
-static struct ivg_slice {
- /* position of first irq in ivg_table for given ivg */
- struct ivgx *ifirst;
- struct ivgx *istop;
-} ivg7_13[IVG13 - IVG7 + 1];
-
-
-/*
- * Search SIC_IAR and fill tables with the irqvalues
- * and their positions in the SIC_ISR register.
- */
-static void __init search_IAR(void)
-{
- unsigned ivg, irq_pos = 0;
- for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) {
- int irqN;
-
- ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos];
-
- for (irqN = 0; irqN < NR_PERI_INTS; irqN += 4) {
- int irqn;
- u32 iar =
- bfin_read32((unsigned long *)SIC_IAR0 +
-#if defined(CONFIG_BF51x) || defined(CONFIG_BF52x) || \
- defined(CONFIG_BF538) || defined(CONFIG_BF539)
- ((irqN % 32) >> 3) + ((irqN / 32) * ((SIC_IAR4 - SIC_IAR0) / 4))
-#else
- (irqN >> 3)
-#endif
- );
- for (irqn = irqN; irqn < irqN + 4; ++irqn) {
- int iar_shift = (irqn & 7) * 4;
- if (ivg == (0xf & (iar >> iar_shift))) {
- ivg_table[irq_pos].irqno = IVG7 + irqn;
- ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
- ivg7_13[ivg].istop++;
- irq_pos++;
- }
- }
- }
- }
-}
-#endif
-
-/*
- * This is for core internal IRQs
- */
-void bfin_ack_noop(struct irq_data *d)
-{
- /* Dummy function. */
-}
-
-static void bfin_core_mask_irq(struct irq_data *d)
-{
- bfin_irq_flags &= ~(1 << d->irq);
- if (!hard_irqs_disabled())
- hard_local_irq_enable();
-}
-
-static void bfin_core_unmask_irq(struct irq_data *d)
-{
- bfin_irq_flags |= 1 << d->irq;
- /*
- * If interrupts are enabled, IMASK must contain the same value
- * as bfin_irq_flags. Make sure that invariant holds. If interrupts
- * are currently disabled we need not do anything; one of the
- * callers will take care of setting IMASK to the proper value
- * when reenabling interrupts.
- * local_irq_enable just does "STI bfin_irq_flags", so it's exactly
- * what we need.
- */
- if (!hard_irqs_disabled())
- hard_local_irq_enable();
- return;
-}
-
-#ifndef SEC_GCTL
-void bfin_internal_mask_irq(unsigned int irq)
-{
- unsigned long flags = hard_local_irq_save();
-#ifdef SIC_IMASK0
- unsigned mask_bank = BFIN_SYSIRQ(irq) / 32;
- unsigned mask_bit = BFIN_SYSIRQ(irq) % 32;
- bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
- ~(1 << mask_bit));
-# if defined(CONFIG_SMP) || defined(CONFIG_ICC)
- bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) &
- ~(1 << mask_bit));
-# endif
-#else
- bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
- ~(1 << BFIN_SYSIRQ(irq)));
-#endif /* end of SIC_IMASK0 */
- hard_local_irq_restore(flags);
-}
-
-static void bfin_internal_mask_irq_chip(struct irq_data *d)
-{
- bfin_internal_mask_irq(d->irq);
-}
-
-#ifdef CONFIG_SMP
-void bfin_internal_unmask_irq_affinity(unsigned int irq,
- const struct cpumask *affinity)
-#else
-void bfin_internal_unmask_irq(unsigned int irq)
-#endif
-{
- unsigned long flags = hard_local_irq_save();
-
-#ifdef SIC_IMASK0
- unsigned mask_bank = BFIN_SYSIRQ(irq) / 32;
- unsigned mask_bit = BFIN_SYSIRQ(irq) % 32;
-# ifdef CONFIG_SMP
- if (cpumask_test_cpu(0, affinity))
-# endif
- bfin_write_SIC_IMASK(mask_bank,
- bfin_read_SIC_IMASK(mask_bank) |
- (1 << mask_bit));
-# ifdef CONFIG_SMP
- if (cpumask_test_cpu(1, affinity))
- bfin_write_SICB_IMASK(mask_bank,
- bfin_read_SICB_IMASK(mask_bank) |
- (1 << mask_bit));
-# endif
-#else
- bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
- (1 << BFIN_SYSIRQ(irq)));
-#endif
- hard_local_irq_restore(flags);
-}
-
-#ifdef CONFIG_SMP
-static void bfin_internal_unmask_irq_chip(struct irq_data *d)
-{
- bfin_internal_unmask_irq_affinity(d->irq,
- irq_data_get_affinity_mask(d));
-}
-
-static int bfin_internal_set_affinity(struct irq_data *d,
- const struct cpumask *mask, bool force)
-{
- bfin_internal_mask_irq(d->irq);
- bfin_internal_unmask_irq_affinity(d->irq, mask);
-
- return 0;
-}
-#else
-static void bfin_internal_unmask_irq_chip(struct irq_data *d)
-{
- bfin_internal_unmask_irq(d->irq);
-}
-#endif
-
-#if defined(CONFIG_PM)
-int bfin_internal_set_wake(unsigned int irq, unsigned int state)
-{
- u32 bank, bit, wakeup = 0;
- unsigned long flags;
- bank = BFIN_SYSIRQ(irq) / 32;
- bit = BFIN_SYSIRQ(irq) % 32;
-
- switch (irq) {
-#ifdef IRQ_RTC
- case IRQ_RTC:
- wakeup |= WAKE;
- break;
-#endif
-#ifdef IRQ_CAN0_RX
- case IRQ_CAN0_RX:
- wakeup |= CANWE;
- break;
-#endif
-#ifdef IRQ_CAN1_RX
- case IRQ_CAN1_RX:
- wakeup |= CANWE;
- break;
-#endif
-#ifdef IRQ_USB_INT0
- case IRQ_USB_INT0:
- wakeup |= USBWE;
- break;
-#endif
-#ifdef CONFIG_BF54x
- case IRQ_CNT:
- wakeup |= ROTWE;
- break;
-#endif
- default:
- break;
- }
-
- flags = hard_local_irq_save();
-
- if (state) {
- bfin_sic_iwr[bank] |= (1 << bit);
- vr_wakeup |= wakeup;
-
- } else {
- bfin_sic_iwr[bank] &= ~(1 << bit);
- vr_wakeup &= ~wakeup;
- }
-
- hard_local_irq_restore(flags);
-
- return 0;
-}
-
-static int bfin_internal_set_wake_chip(struct irq_data *d, unsigned int state)
-{
- return bfin_internal_set_wake(d->irq, state);
-}
-#else
-inline int bfin_internal_set_wake(unsigned int irq, unsigned int state)
-{
- return 0;
-}
-# define bfin_internal_set_wake_chip NULL
-#endif
-
-#else /* SEC_GCTL */
-static void bfin_sec_preflow_handler(struct irq_data *d)
-{
- unsigned long flags = hard_local_irq_save();
- unsigned int sid = BFIN_SYSIRQ(d->irq);
-
- bfin_write_SEC_SCI(0, SEC_CSID, sid);
-
- hard_local_irq_restore(flags);
-}
-
-static void bfin_sec_mask_ack_irq(struct irq_data *d)
-{
- unsigned long flags = hard_local_irq_save();
- unsigned int sid = BFIN_SYSIRQ(d->irq);
-
- bfin_write_SEC_SCI(0, SEC_CSID, sid);
-
- hard_local_irq_restore(flags);
-}
-
-static void bfin_sec_unmask_irq(struct irq_data *d)
-{
- unsigned long flags = hard_local_irq_save();
- unsigned int sid = BFIN_SYSIRQ(d->irq);
-
- bfin_write32(SEC_END, sid);
-
- hard_local_irq_restore(flags);
-}
-
-static void bfin_sec_enable_ssi(unsigned int sid)
-{
- unsigned long flags = hard_local_irq_save();
- uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
-
- reg_sctl |= SEC_SCTL_SRC_EN;
- bfin_write_SEC_SCTL(sid, reg_sctl);
-
- hard_local_irq_restore(flags);
-}
-
-static void bfin_sec_disable_ssi(unsigned int sid)
-{
- unsigned long flags = hard_local_irq_save();
- uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
-
- reg_sctl &= ((uint32_t)~SEC_SCTL_SRC_EN);
- bfin_write_SEC_SCTL(sid, reg_sctl);
-
- hard_local_irq_restore(flags);
-}
-
-static void bfin_sec_set_ssi_coreid(unsigned int sid, unsigned int coreid)
-{
- unsigned long flags = hard_local_irq_save();
- uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
-
- reg_sctl &= ((uint32_t)~SEC_SCTL_CTG);
- bfin_write_SEC_SCTL(sid, reg_sctl | ((coreid << 20) & SEC_SCTL_CTG));
-
- hard_local_irq_restore(flags);
-}
-
-static void bfin_sec_enable_sci(unsigned int sid)
-{
- unsigned long flags = hard_local_irq_save();
- uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
-
- if (sid == BFIN_SYSIRQ(IRQ_WATCH0))
- reg_sctl |= SEC_SCTL_FAULT_EN;
- else
- reg_sctl |= SEC_SCTL_INT_EN;
- bfin_write_SEC_SCTL(sid, reg_sctl);
-
- hard_local_irq_restore(flags);
-}
-
-static void bfin_sec_disable_sci(unsigned int sid)
-{
- unsigned long flags = hard_local_irq_save();
- uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
-
- reg_sctl &= ((uint32_t)~SEC_SCTL_INT_EN);
- bfin_write_SEC_SCTL(sid, reg_sctl);
-
- hard_local_irq_restore(flags);
-}
-
-static void bfin_sec_enable(struct irq_data *d)
-{
- unsigned long flags = hard_local_irq_save();
- unsigned int sid = BFIN_SYSIRQ(d->irq);
-
- bfin_sec_enable_sci(sid);
- bfin_sec_enable_ssi(sid);
-
- hard_local_irq_restore(flags);
-}
-
-static void bfin_sec_disable(struct irq_data *d)
-{
- unsigned long flags = hard_local_irq_save();
- unsigned int sid = BFIN_SYSIRQ(d->irq);
-
- bfin_sec_disable_sci(sid);
- bfin_sec_disable_ssi(sid);
-
- hard_local_irq_restore(flags);
-}
-
-static void bfin_sec_set_priority(unsigned int sec_int_levels, u8 *sec_int_priority)
-{
- unsigned long flags = hard_local_irq_save();
- uint32_t reg_sctl;
- int i;
-
- bfin_write_SEC_SCI(0, SEC_CPLVL, sec_int_levels);
-
- for (i = 0; i < SYS_IRQS - BFIN_IRQ(0); i++) {
- reg_sctl = bfin_read_SEC_SCTL(i) & ~SEC_SCTL_PRIO;
- reg_sctl |= sec_int_priority[i] << SEC_SCTL_PRIO_OFFSET;
- bfin_write_SEC_SCTL(i, reg_sctl);
- }
-
- hard_local_irq_restore(flags);
-}
-
-void bfin_sec_raise_irq(unsigned int irq)
-{
- unsigned long flags = hard_local_irq_save();
- unsigned int sid = BFIN_SYSIRQ(irq);
-
- bfin_write32(SEC_RAISE, sid);
-
- hard_local_irq_restore(flags);
-}
-
-static void init_software_driven_irq(void)
-{
- bfin_sec_set_ssi_coreid(34, 0);
- bfin_sec_set_ssi_coreid(35, 1);
-
- bfin_sec_enable_sci(35);
- bfin_sec_enable_ssi(35);
- bfin_sec_set_ssi_coreid(36, 0);
- bfin_sec_set_ssi_coreid(37, 1);
- bfin_sec_enable_sci(37);
- bfin_sec_enable_ssi(37);
-}
-
-void handle_sec_sfi_fault(uint32_t gstat)
-{
-
-}
-
-void handle_sec_sci_fault(uint32_t gstat)
-{
- uint32_t core_id;
- uint32_t cstat;
-
- core_id = gstat & SEC_GSTAT_SCI;
- cstat = bfin_read_SEC_SCI(core_id, SEC_CSTAT);
- if (cstat & SEC_CSTAT_ERR) {
- switch (cstat & SEC_CSTAT_ERRC) {
- case SEC_CSTAT_ACKERR:
- printk(KERN_DEBUG "sec ack err\n");
- break;
- default:
- printk(KERN_DEBUG "sec sci unknown err\n");
- }
- }
-
-}
-
-void handle_sec_ssi_fault(uint32_t gstat)
-{
- uint32_t sid;
- uint32_t sstat;
-
- sid = gstat & SEC_GSTAT_SID;
- sstat = bfin_read_SEC_SSTAT(sid);
-
-}
-
-void handle_sec_fault(uint32_t sec_gstat)
-{
- if (sec_gstat & SEC_GSTAT_ERR) {
-
- switch (sec_gstat & SEC_GSTAT_ERRC) {
- case 0:
- handle_sec_sfi_fault(sec_gstat);
- break;
- case SEC_GSTAT_SCIERR:
- handle_sec_sci_fault(sec_gstat);
- break;
- case SEC_GSTAT_SSIERR:
- handle_sec_ssi_fault(sec_gstat);
- break;
- }
-
-
- }
-}
-
-static struct irqaction bfin_fault_irq = {
- .name = "Blackfin fault",
-};
-
-static irqreturn_t bfin_fault_routine(int irq, void *data)
-{
- struct pt_regs *fp = get_irq_regs();
-
- switch (irq) {
- case IRQ_C0_DBL_FAULT:
- double_fault_c(fp);
- break;
- case IRQ_C0_HW_ERR:
- dump_bfin_process(fp);
- dump_bfin_mem(fp);
- show_regs(fp);
- printk(KERN_NOTICE "Kernel Stack\n");
- show_stack(current, NULL);
- print_modules();
- panic("Core 0 hardware error");
- break;
- case IRQ_C0_NMI_L1_PARITY_ERR:
- panic("Core 0 NMI L1 parity error");
- break;
- case IRQ_SEC_ERR:
- pr_err("SEC error\n");
- handle_sec_fault(bfin_read32(SEC_GSTAT));
- break;
- default:
- panic("Unknown fault %d", irq);
- }
-
- return IRQ_HANDLED;
-}
-#endif /* SEC_GCTL */
-
-static struct irq_chip bfin_core_irqchip = {
- .name = "CORE",
- .irq_mask = bfin_core_mask_irq,
- .irq_unmask = bfin_core_unmask_irq,
-};
-
-#ifndef SEC_GCTL
-static struct irq_chip bfin_internal_irqchip = {
- .name = "INTN",
- .irq_mask = bfin_internal_mask_irq_chip,
- .irq_unmask = bfin_internal_unmask_irq_chip,
- .irq_disable = bfin_internal_mask_irq_chip,
- .irq_enable = bfin_internal_unmask_irq_chip,
-#ifdef CONFIG_SMP
- .irq_set_affinity = bfin_internal_set_affinity,
-#endif
- .irq_set_wake = bfin_internal_set_wake_chip,
-};
-#else
-static struct irq_chip bfin_sec_irqchip = {
- .name = "SEC",
- .irq_mask_ack = bfin_sec_mask_ack_irq,
- .irq_mask = bfin_sec_mask_ack_irq,
- .irq_unmask = bfin_sec_unmask_irq,
- .irq_eoi = bfin_sec_unmask_irq,
- .irq_disable = bfin_sec_disable,
- .irq_enable = bfin_sec_enable,
-};
-#endif
-
-void bfin_handle_irq(unsigned irq)
-{
-#ifdef CONFIG_IPIPE
- struct pt_regs regs; /* Contents not used. */
- ipipe_trace_irq_entry(irq);
- __ipipe_handle_irq(irq, ®s);
- ipipe_trace_irq_exit(irq);
-#else /* !CONFIG_IPIPE */
- generic_handle_irq(irq);
-#endif /* !CONFIG_IPIPE */
-}
-
-#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
-static int mac_stat_int_mask;
-
-static void bfin_mac_status_ack_irq(unsigned int irq)
-{
- switch (irq) {
- case IRQ_MAC_MMCINT:
- bfin_write_EMAC_MMC_TIRQS(
- bfin_read_EMAC_MMC_TIRQE() &
- bfin_read_EMAC_MMC_TIRQS());
- bfin_write_EMAC_MMC_RIRQS(
- bfin_read_EMAC_MMC_RIRQE() &
- bfin_read_EMAC_MMC_RIRQS());
- break;
- case IRQ_MAC_RXFSINT:
- bfin_write_EMAC_RX_STKY(
- bfin_read_EMAC_RX_IRQE() &
- bfin_read_EMAC_RX_STKY());
- break;
- case IRQ_MAC_TXFSINT:
- bfin_write_EMAC_TX_STKY(
- bfin_read_EMAC_TX_IRQE() &
- bfin_read_EMAC_TX_STKY());
- break;
- case IRQ_MAC_WAKEDET:
- bfin_write_EMAC_WKUP_CTL(
- bfin_read_EMAC_WKUP_CTL() | MPKS | RWKS);
- break;
- default:
- /* These bits are W1C */
- bfin_write_EMAC_SYSTAT(1L << (irq - IRQ_MAC_PHYINT));
- break;
- }
-}
-
-static void bfin_mac_status_mask_irq(struct irq_data *d)
-{
- unsigned int irq = d->irq;
-
- mac_stat_int_mask &= ~(1L << (irq - IRQ_MAC_PHYINT));
-#ifdef BF537_FAMILY
- switch (irq) {
- case IRQ_MAC_PHYINT:
- bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() & ~PHYIE);
- break;
- default:
- break;
- }
-#else
- if (!mac_stat_int_mask)
- bfin_internal_mask_irq(IRQ_MAC_ERROR);
-#endif
- bfin_mac_status_ack_irq(irq);
-}
-
-static void bfin_mac_status_unmask_irq(struct irq_data *d)
-{
- unsigned int irq = d->irq;
-
-#ifdef BF537_FAMILY
- switch (irq) {
- case IRQ_MAC_PHYINT:
- bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() | PHYIE);
- break;
- default:
- break;
- }
-#else
- if (!mac_stat_int_mask)
- bfin_internal_unmask_irq(IRQ_MAC_ERROR);
-#endif
- mac_stat_int_mask |= 1L << (irq - IRQ_MAC_PHYINT);
-}
-
-#ifdef CONFIG_PM
-int bfin_mac_status_set_wake(struct irq_data *d, unsigned int state)
-{
-#ifdef BF537_FAMILY
- return bfin_internal_set_wake(IRQ_GENERIC_ERROR, state);
-#else
- return bfin_internal_set_wake(IRQ_MAC_ERROR, state);
-#endif
-}
-#else
-# define bfin_mac_status_set_wake NULL
-#endif
-
-static struct irq_chip bfin_mac_status_irqchip = {
- .name = "MACST",
- .irq_mask = bfin_mac_status_mask_irq,
- .irq_unmask = bfin_mac_status_unmask_irq,
- .irq_set_wake = bfin_mac_status_set_wake,
-};
-
-void bfin_demux_mac_status_irq(struct irq_desc *inta_desc)
-{
- int i, irq = 0;
- u32 status = bfin_read_EMAC_SYSTAT();
-
- for (i = 0; i <= (IRQ_MAC_STMDONE - IRQ_MAC_PHYINT); i++)
- if (status & (1L << i)) {
- irq = IRQ_MAC_PHYINT + i;
- break;
- }
-
- if (irq) {
- if (mac_stat_int_mask & (1L << (irq - IRQ_MAC_PHYINT))) {
- bfin_handle_irq(irq);
- } else {
- bfin_mac_status_ack_irq(irq);
- pr_debug("IRQ %d:"
- " MASKED MAC ERROR INTERRUPT ASSERTED\n",
- irq);
- }
- } else
- printk(KERN_ERR
- "%s : %s : LINE %d :\nIRQ ?: MAC ERROR"
- " INTERRUPT ASSERTED BUT NO SOURCE FOUND"
- "(EMAC_SYSTAT=0x%X)\n",
- __func__, __FILE__, __LINE__, status);
-}
-#endif
-
-static inline void bfin_set_irq_handler(struct irq_data *d, irq_flow_handler_t handle)
-{
-#ifdef CONFIG_IPIPE
- handle = handle_level_irq;
-#endif
- irq_set_handler_locked(d, handle);
-}
-
-#ifdef CONFIG_GPIO_ADI
-
-static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS);
-
-static void bfin_gpio_ack_irq(struct irq_data *d)
-{
- /* AFAIK ack_irq in case mask_ack is provided
- * get's only called for edge sense irqs
- */
- set_gpio_data(irq_to_gpio(d->irq), 0);
-}
-
-static void bfin_gpio_mask_ack_irq(struct irq_data *d)
-{
- unsigned int irq = d->irq;
- u32 gpionr = irq_to_gpio(irq);
-
- if (!irqd_is_level_type(d))
- set_gpio_data(gpionr, 0);
-
- set_gpio_maska(gpionr, 0);
-}
-
-static void bfin_gpio_mask_irq(struct irq_data *d)
-{
- set_gpio_maska(irq_to_gpio(d->irq), 0);
-}
-
-static void bfin_gpio_unmask_irq(struct irq_data *d)
-{
- set_gpio_maska(irq_to_gpio(d->irq), 1);
-}
-
-static unsigned int bfin_gpio_irq_startup(struct irq_data *d)
-{
- u32 gpionr = irq_to_gpio(d->irq);
-
- if (__test_and_set_bit(gpionr, gpio_enabled))
- bfin_gpio_irq_prepare(gpionr);
-
- bfin_gpio_unmask_irq(d);
-
- return 0;
-}
-
-static void bfin_gpio_irq_shutdown(struct irq_data *d)
-{
- u32 gpionr = irq_to_gpio(d->irq);
-
- bfin_gpio_mask_irq(d);
- __clear_bit(gpionr, gpio_enabled);
- bfin_gpio_irq_free(gpionr);
-}
-
-static int bfin_gpio_irq_type(struct irq_data *d, unsigned int type)
-{
- unsigned int irq = d->irq;
- int ret;
- char buf[16];
- u32 gpionr = irq_to_gpio(irq);
-
- if (type == IRQ_TYPE_PROBE) {
- /* only probe unenabled GPIO interrupt lines */
- if (test_bit(gpionr, gpio_enabled))
- return 0;
- type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
- }
-
- if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
- IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
-
- snprintf(buf, 16, "gpio-irq%d", irq);
- ret = bfin_gpio_irq_request(gpionr, buf);
- if (ret)
- return ret;
-
- if (__test_and_set_bit(gpionr, gpio_enabled))
- bfin_gpio_irq_prepare(gpionr);
-
- } else {
- __clear_bit(gpionr, gpio_enabled);
- return 0;
- }
-
- set_gpio_inen(gpionr, 0);
- set_gpio_dir(gpionr, 0);
-
- if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
- == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
- set_gpio_both(gpionr, 1);
- else
- set_gpio_both(gpionr, 0);
-
- if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
- set_gpio_polar(gpionr, 1); /* low or falling edge denoted by one */
- else
- set_gpio_polar(gpionr, 0); /* high or rising edge denoted by zero */
-
- if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
- set_gpio_edge(gpionr, 1);
- set_gpio_inen(gpionr, 1);
- set_gpio_data(gpionr, 0);
-
- } else {
- set_gpio_edge(gpionr, 0);
- set_gpio_inen(gpionr, 1);
- }
-
- if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
- bfin_set_irq_handler(d, handle_edge_irq);
- else
- bfin_set_irq_handler(d, handle_level_irq);
-
- return 0;
-}
-
-static void bfin_demux_gpio_block(unsigned int irq)
-{
- unsigned int gpio, mask;
-
- gpio = irq_to_gpio(irq);
- mask = get_gpiop_data(gpio) & get_gpiop_maska(gpio);
-
- while (mask) {
- if (mask & 1)
- bfin_handle_irq(irq);
- irq++;
- mask >>= 1;
- }
-}
-
-void bfin_demux_gpio_irq(struct irq_desc *desc)
-{
- unsigned int inta_irq = irq_desc_get_irq(desc);
- unsigned int irq;
-
- switch (inta_irq) {
-#if defined(BF537_FAMILY)
- case IRQ_PF_INTA_PG_INTA:
- bfin_demux_gpio_block(IRQ_PF0);
- irq = IRQ_PG0;
- break;
- case IRQ_PH_INTA_MAC_RX:
- irq = IRQ_PH0;
- break;
-#elif defined(BF533_FAMILY)
- case IRQ_PROG_INTA:
- irq = IRQ_PF0;
- break;
-#elif defined(BF538_FAMILY)
- case IRQ_PORTF_INTA:
- irq = IRQ_PF0;
- break;
-#elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
- case IRQ_PORTF_INTA:
- irq = IRQ_PF0;
- break;
- case IRQ_PORTG_INTA:
- irq = IRQ_PG0;
- break;
- case IRQ_PORTH_INTA:
- irq = IRQ_PH0;
- break;
-#elif defined(CONFIG_BF561)
- case IRQ_PROG0_INTA:
- irq = IRQ_PF0;
- break;
- case IRQ_PROG1_INTA:
- irq = IRQ_PF16;
- break;
- case IRQ_PROG2_INTA:
- irq = IRQ_PF32;
- break;
-#endif
- default:
- BUG();
- return;
- }
-
- bfin_demux_gpio_block(irq);
-}
-
-#ifdef CONFIG_PM
-
-static int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
-{
- return bfin_gpio_pm_wakeup_ctrl(irq_to_gpio(d->irq), state);
-}
-
-#else
-
-# define bfin_gpio_set_wake NULL
-
-#endif
-
-static struct irq_chip bfin_gpio_irqchip = {
- .name = "GPIO",
- .irq_ack = bfin_gpio_ack_irq,
- .irq_mask = bfin_gpio_mask_irq,
- .irq_mask_ack = bfin_gpio_mask_ack_irq,
- .irq_unmask = bfin_gpio_unmask_irq,
- .irq_disable = bfin_gpio_mask_irq,
- .irq_enable = bfin_gpio_unmask_irq,
- .irq_set_type = bfin_gpio_irq_type,
- .irq_startup = bfin_gpio_irq_startup,
- .irq_shutdown = bfin_gpio_irq_shutdown,
- .irq_set_wake = bfin_gpio_set_wake,
-};
-
-#endif
-
-#ifdef CONFIG_PM
-
-#ifdef SEC_GCTL
-static u32 save_pint_sec_ctl[NR_PINT_SYS_IRQS];
-
-static int sec_suspend(void)
-{
- u32 bank;
-
- for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++)
- save_pint_sec_ctl[bank] = bfin_read_SEC_SCTL(bank + BFIN_SYSIRQ(IRQ_PINT0));
- return 0;
-}
-
-static void sec_resume(void)
-{
- u32 bank;
-
- bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET);
- udelay(100);
- bfin_write_SEC_GCTL(SEC_GCTL_EN);
- bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
-
- for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++)
- bfin_write_SEC_SCTL(bank + BFIN_SYSIRQ(IRQ_PINT0), save_pint_sec_ctl[bank]);
-}
-
-static struct syscore_ops sec_pm_syscore_ops = {
- .suspend = sec_suspend,
- .resume = sec_resume,
-};
-#endif
-
-#endif
-
-void init_exception_vectors(void)
-{
- /* cannot program in software:
- * evt0 - emulation (jtag)
- * evt1 - reset
- */
- bfin_write_EVT2(evt_nmi);
- bfin_write_EVT3(trap);
- bfin_write_EVT5(evt_ivhw);
- bfin_write_EVT6(evt_timer);
- bfin_write_EVT7(evt_evt7);
- bfin_write_EVT8(evt_evt8);
- bfin_write_EVT9(evt_evt9);
- bfin_write_EVT10(evt_evt10);
- bfin_write_EVT11(evt_evt11);
- bfin_write_EVT12(evt_evt12);
- bfin_write_EVT13(evt_evt13);
- bfin_write_EVT14(evt_evt14);
- bfin_write_EVT15(evt_system_call);
- CSYNC();
-}
-
-#ifndef SEC_GCTL
-/*
- * This function should be called during kernel startup to initialize
- * the BFin IRQ handling routines.
- */
-
-int __init init_arch_irq(void)
-{
- int irq;
- unsigned long ilat = 0;
-
- /* Disable all the peripheral intrs - page 4-29 HW Ref manual */
-#ifdef SIC_IMASK0
- bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
- bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
-# ifdef SIC_IMASK2
- bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
-# endif
-# if defined(CONFIG_SMP) || defined(CONFIG_ICC)
- bfin_write_SICB_IMASK0(SIC_UNMASK_ALL);
- bfin_write_SICB_IMASK1(SIC_UNMASK_ALL);
-# endif
-#else
- bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
-#endif
-
- local_irq_disable();
-
- for (irq = 0; irq <= SYS_IRQS; irq++) {
- if (irq <= IRQ_CORETMR)
- irq_set_chip(irq, &bfin_core_irqchip);
- else
- irq_set_chip(irq, &bfin_internal_irqchip);
-
- switch (irq) {
-#if !BFIN_GPIO_PINT
-#if defined(BF537_FAMILY)
- case IRQ_PH_INTA_MAC_RX:
- case IRQ_PF_INTA_PG_INTA:
-#elif defined(BF533_FAMILY)
- case IRQ_PROG_INTA:
-#elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
- case IRQ_PORTF_INTA:
- case IRQ_PORTG_INTA:
- case IRQ_PORTH_INTA:
-#elif defined(CONFIG_BF561)
- case IRQ_PROG0_INTA:
- case IRQ_PROG1_INTA:
- case IRQ_PROG2_INTA:
-#elif defined(BF538_FAMILY)
- case IRQ_PORTF_INTA:
-#endif
- irq_set_chained_handler(irq, bfin_demux_gpio_irq);
- break;
-#endif
-#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
- case IRQ_MAC_ERROR:
- irq_set_chained_handler(irq,
- bfin_demux_mac_status_irq);
- break;
-#endif
-#if defined(CONFIG_SMP) || defined(CONFIG_ICC)
- case IRQ_SUPPLE_0:
- case IRQ_SUPPLE_1:
- irq_set_handler(irq, handle_percpu_irq);
- break;
-#endif
-
-#ifdef CONFIG_TICKSOURCE_CORETMR
- case IRQ_CORETMR:
-# ifdef CONFIG_SMP
- irq_set_handler(irq, handle_percpu_irq);
-# else
- irq_set_handler(irq, handle_simple_irq);
-# endif
- break;
-#endif
-
-#ifdef CONFIG_TICKSOURCE_GPTMR0
- case IRQ_TIMER0:
- irq_set_handler(irq, handle_simple_irq);
- break;
-#endif
-
- default:
-#ifdef CONFIG_IPIPE
- irq_set_handler(irq, handle_level_irq);
-#else
- irq_set_handler(irq, handle_simple_irq);
-#endif
- break;
- }
- }
-
- init_mach_irq();
-
-#if (defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
- for (irq = IRQ_MAC_PHYINT; irq <= IRQ_MAC_STMDONE; irq++)
- irq_set_chip_and_handler(irq, &bfin_mac_status_irqchip,
- handle_level_irq);
-#endif
- /* if configured as edge, then will be changed to do_edge_IRQ */
-#ifdef CONFIG_GPIO_ADI
- for (irq = GPIO_IRQ_BASE;
- irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++)
- irq_set_chip_and_handler(irq, &bfin_gpio_irqchip,
- handle_level_irq);
-#endif
- bfin_write_IMASK(0);
- CSYNC();
- ilat = bfin_read_ILAT();
- CSYNC();
- bfin_write_ILAT(ilat);
- CSYNC();
-
- printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
- /* IMASK=xxx is equivalent to STI xx or bfin_irq_flags=xx,
- * local_irq_enable()
- */
- program_IAR();
- /* Therefore it's better to setup IARs before interrupts enabled */
- search_IAR();
-
- /* Enable interrupts IVG7-15 */
- bfin_irq_flags |= IMASK_IVG15 |
- IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
- IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
-
-
- /* This implicitly covers ANOMALY_05000171
- * Boot-ROM code modifies SICA_IWRx wakeup registers
- */
-#ifdef SIC_IWR0
- bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
-# ifdef SIC_IWR1
- /* BF52x/BF51x system reset does not properly reset SIC_IWR1 which
- * will screw up the bootrom as it relies on MDMA0/1 waking it
- * up from IDLE instructions. See this report for more info:
- * http://blackfin.uclinux.org/gf/tracker/4323
- */
- if (ANOMALY_05000435)
- bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
- else
- bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
-# endif
-# ifdef SIC_IWR2
- bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
-# endif
-#else
- bfin_write_SIC_IWR(IWR_DISABLE_ALL);
-#endif
- return 0;
-}
-
-#ifdef CONFIG_DO_IRQ_L1
-__attribute__((l1_text))
-#endif
-static int vec_to_irq(int vec)
-{
- struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
- struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
- unsigned long sic_status[3];
- if (likely(vec == EVT_IVTMR_P))
- return IRQ_CORETMR;
-#ifdef SIC_ISR
- sic_status[0] = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
-#else
- if (smp_processor_id()) {
-# ifdef SICB_ISR0
- /* This will be optimized out in UP mode. */
- sic_status[0] = bfin_read_SICB_ISR0() & bfin_read_SICB_IMASK0();
- sic_status[1] = bfin_read_SICB_ISR1() & bfin_read_SICB_IMASK1();
-# endif
- } else {
- sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
- sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
- }
-#endif
-#ifdef SIC_ISR2
- sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
-#endif
-
- for (;; ivg++) {
- if (ivg >= ivg_stop)
- return -1;
-#ifdef SIC_ISR
- if (sic_status[0] & ivg->isrflag)
-#else
- if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
-#endif
- return ivg->irqno;
- }
-}
-
-#else /* SEC_GCTL */
-
-/*
- * This function should be called during kernel startup to initialize
- * the BFin IRQ handling routines.
- */
-
-int __init init_arch_irq(void)
-{
- int irq;
- unsigned long ilat = 0;
-
- bfin_write_SEC_GCTL(SEC_GCTL_RESET);
-
- local_irq_disable();
-
- for (irq = 0; irq <= SYS_IRQS; irq++) {
- if (irq <= IRQ_CORETMR) {
- irq_set_chip_and_handler(irq, &bfin_core_irqchip,
- handle_simple_irq);
-#if defined(CONFIG_TICKSOURCE_CORETMR) && defined(CONFIG_SMP)
- if (irq == IRQ_CORETMR)
- irq_set_handler(irq, handle_percpu_irq);
-#endif
- } else if (irq >= BFIN_IRQ(34) && irq <= BFIN_IRQ(37)) {
- irq_set_chip_and_handler(irq, &bfin_sec_irqchip,
- handle_percpu_irq);
- } else {
- irq_set_chip(irq, &bfin_sec_irqchip);
- irq_set_handler(irq, handle_fasteoi_irq);
- __irq_set_preflow_handler(irq, bfin_sec_preflow_handler);
- }
- }
-
- bfin_write_IMASK(0);
- CSYNC();
- ilat = bfin_read_ILAT();
- CSYNC();
- bfin_write_ILAT(ilat);
- CSYNC();
-
- printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
-
- bfin_sec_set_priority(CONFIG_SEC_IRQ_PRIORITY_LEVELS, sec_int_priority);
-
- /* Enable interrupts IVG7-15 */
- bfin_irq_flags |= IMASK_IVG15 |
- IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
- IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
-
-
- bfin_write_SEC_FCTL(SEC_FCTL_EN | SEC_FCTL_SYSRST_EN | SEC_FCTL_FLTIN_EN);
- bfin_sec_enable_sci(BFIN_SYSIRQ(IRQ_WATCH0));
- bfin_sec_enable_ssi(BFIN_SYSIRQ(IRQ_WATCH0));
- bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET);
- udelay(100);
- bfin_write_SEC_GCTL(SEC_GCTL_EN);
- bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
- bfin_write_SEC_SCI(1, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
-
- init_software_driven_irq();
-
-#ifdef CONFIG_PM
- register_syscore_ops(&sec_pm_syscore_ops);
-#endif
-
- bfin_fault_irq.handler = bfin_fault_routine;
-#ifdef CONFIG_L1_PARITY_CHECK
- setup_irq(IRQ_C0_NMI_L1_PARITY_ERR, &bfin_fault_irq);
-#endif
- setup_irq(IRQ_C0_DBL_FAULT, &bfin_fault_irq);
- setup_irq(IRQ_SEC_ERR, &bfin_fault_irq);
-
- return 0;
-}
-
-#ifdef CONFIG_DO_IRQ_L1
-__attribute__((l1_text))
-#endif
-static int vec_to_irq(int vec)
-{
- if (likely(vec == EVT_IVTMR_P))
- return IRQ_CORETMR;
-
- return BFIN_IRQ(bfin_read_SEC_SCI(0, SEC_CSID));
-}
-#endif /* SEC_GCTL */
-
-#ifdef CONFIG_DO_IRQ_L1
-__attribute__((l1_text))
-#endif
-void do_irq(int vec, struct pt_regs *fp)
-{
- int irq = vec_to_irq(vec);
- if (irq == -1)
- return;
- asm_do_IRQ(irq, fp);
-}
-
-#ifdef CONFIG_IPIPE
-
-int __ipipe_get_irq_priority(unsigned irq)
-{
- int ient, prio;
-
- if (irq <= IRQ_CORETMR)
- return irq;
-
-#ifdef SEC_GCTL
- if (irq >= BFIN_IRQ(0))
- return IVG11;
-#else
- for (ient = 0; ient < NR_PERI_INTS; ient++) {
- struct ivgx *ivg = ivg_table + ient;
- if (ivg->irqno == irq) {
- for (prio = 0; prio <= IVG13-IVG7; prio++) {
- if (ivg7_13[prio].ifirst <= ivg &&
- ivg7_13[prio].istop > ivg)
- return IVG7 + prio;
- }
- }
- }
-#endif
-
- return IVG15;
-}
-
-/* Hw interrupts are disabled on entry (check SAVE_CONTEXT). */
-#ifdef CONFIG_DO_IRQ_L1
-__attribute__((l1_text))
-#endif
-asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
-{
- struct ipipe_percpu_domain_data *p = ipipe_root_cpudom_ptr();
- struct ipipe_domain *this_domain = __ipipe_current_domain;
- int irq, s = 0;
-
- irq = vec_to_irq(vec);
- if (irq == -1)
- return 0;
-
- if (irq == IRQ_SYSTMR) {
-#if !defined(CONFIG_GENERIC_CLOCKEVENTS) || defined(CONFIG_TICKSOURCE_GPTMR0)
- bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */
-#endif
- /* This is basically what we need from the register frame. */
- __this_cpu_write(__ipipe_tick_regs.ipend, regs->ipend);
- __this_cpu_write(__ipipe_tick_regs.pc, regs->pc);
- if (this_domain != ipipe_root_domain)
- __this_cpu_and(__ipipe_tick_regs.ipend, ~0x10);
- else
- __this_cpu_or(__ipipe_tick_regs.ipend, 0x10);
- }
-
- /*
- * We don't want Linux interrupt handlers to run at the
- * current core priority level (i.e. < EVT15), since this
- * might delay other interrupts handled by a high priority
- * domain. Here is what we do instead:
- *
- * - we raise the SYNCDEFER bit to prevent
- * __ipipe_handle_irq() to sync the pipeline for the root
- * stage for the incoming interrupt. Upon return, that IRQ is
- * pending in the interrupt log.
- *
- * - we raise the TIF_IRQ_SYNC bit for the current thread, so
- * that _schedule_and_signal_from_int will eventually sync the
- * pipeline from EVT15.
- */
- if (this_domain == ipipe_root_domain) {
- s = __test_and_set_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
- barrier();
- }
-
- ipipe_trace_irq_entry(irq);
- __ipipe_handle_irq(irq, regs);
- ipipe_trace_irq_exit(irq);
-
- if (user_mode(regs) &&
- !ipipe_test_foreign_stack() &&
- (current->ipipe_flags & PF_EVTRET) != 0) {
- /*
- * Testing for user_regs() does NOT fully eliminate
- * foreign stack contexts, because of the forged
- * interrupt returns we do through
- * __ipipe_call_irqtail. In that case, we might have
- * preempted a foreign stack context in a high
- * priority domain, with a single interrupt level now
- * pending after the irqtail unwinding is done. In
- * which case user_mode() is now true, and the event
- * gets dispatched spuriously.
- */
- current->ipipe_flags &= ~PF_EVTRET;
- __ipipe_dispatch_event(IPIPE_EVENT_RETURN, regs);
- }
-
- if (this_domain == ipipe_root_domain) {
- set_thread_flag(TIF_IRQ_SYNC);
- if (!s) {
- __clear_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
- return !test_bit(IPIPE_STALL_FLAG, &p->status);
- }
- }
-
- return 0;
-}
-
-#endif /* CONFIG_IPIPE */
+++ /dev/null
-/*
- * Blackfin power management
- *
- * Copyright 2006-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2
- * based on arm/mach-omap/pm.c
- * Copyright 2001, Cliff Brake <cbrake@accelent.com> and others
- */
-
-#include <linux/suspend.h>
-#include <linux/sched.h>
-#include <linux/proc_fs.h>
-#include <linux/slab.h>
-#include <linux/io.h>
-#include <linux/irq.h>
-#include <linux/delay.h>
-
-#include <asm/cplb.h>
-#include <asm/dma.h>
-#include <asm/dpmc.h>
-#include <asm/pm.h>
-#include <asm/gpio.h>
-
-#ifdef CONFIG_BF60x
-struct bfin_cpu_pm_fns *bfin_cpu_pm;
-#endif
-
-void bfin_pm_suspend_standby_enter(void)
-{
-#if !BFIN_GPIO_PINT
- bfin_pm_standby_setup();
-#endif
-
-#ifdef CONFIG_BF60x
- bfin_cpu_pm->enter(PM_SUSPEND_STANDBY);
-#else
-# ifdef CONFIG_PM_BFIN_SLEEP_DEEPER
- sleep_deeper(bfin_sic_iwr[0], bfin_sic_iwr[1], bfin_sic_iwr[2]);
-# else
- sleep_mode(bfin_sic_iwr[0], bfin_sic_iwr[1], bfin_sic_iwr[2]);
-# endif
-#endif
-
-#if !BFIN_GPIO_PINT
- bfin_pm_standby_restore();
-#endif
-
-#ifndef CONFIG_BF60x
-#ifdef SIC_IWR0
- bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
-# ifdef SIC_IWR1
- /* BF52x system reset does not properly reset SIC_IWR1 which
- * will screw up the bootrom as it relies on MDMA0/1 waking it
- * up from IDLE instructions. See this report for more info:
- * http://blackfin.uclinux.org/gf/tracker/4323
- */
- if (ANOMALY_05000435)
- bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
- else
- bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
-# endif
-# ifdef SIC_IWR2
- bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
-# endif
-#else
- bfin_write_SIC_IWR(IWR_DISABLE_ALL);
-#endif
-
-#endif
-}
-
-int bf53x_suspend_l1_mem(unsigned char *memptr)
-{
- dma_memcpy_nocache(memptr, (const void *) L1_CODE_START,
- L1_CODE_LENGTH);
- dma_memcpy_nocache(memptr + L1_CODE_LENGTH,
- (const void *) L1_DATA_A_START, L1_DATA_A_LENGTH);
- dma_memcpy_nocache(memptr + L1_CODE_LENGTH + L1_DATA_A_LENGTH,
- (const void *) L1_DATA_B_START, L1_DATA_B_LENGTH);
- memcpy(memptr + L1_CODE_LENGTH + L1_DATA_A_LENGTH +
- L1_DATA_B_LENGTH, (const void *) L1_SCRATCH_START,
- L1_SCRATCH_LENGTH);
-
- return 0;
-}
-
-int bf53x_resume_l1_mem(unsigned char *memptr)
-{
- dma_memcpy_nocache((void *) L1_CODE_START, memptr, L1_CODE_LENGTH);
- dma_memcpy_nocache((void *) L1_DATA_A_START, memptr + L1_CODE_LENGTH,
- L1_DATA_A_LENGTH);
- dma_memcpy_nocache((void *) L1_DATA_B_START, memptr + L1_CODE_LENGTH +
- L1_DATA_A_LENGTH, L1_DATA_B_LENGTH);
- memcpy((void *) L1_SCRATCH_START, memptr + L1_CODE_LENGTH +
- L1_DATA_A_LENGTH + L1_DATA_B_LENGTH, L1_SCRATCH_LENGTH);
-
- return 0;
-}
-
-#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
-# ifdef CONFIG_BF60x
-__attribute__((l1_text))
-# endif
-static void flushinv_all_dcache(void)
-{
- register u32 way, bank, subbank, set;
- register u32 status, addr;
- u32 dmem_ctl = bfin_read_DMEM_CONTROL();
-
- for (bank = 0; bank < 2; ++bank) {
- if (!(dmem_ctl & (1 << (DMC1_P - bank))))
- continue;
-
- for (way = 0; way < 2; ++way)
- for (subbank = 0; subbank < 4; ++subbank)
- for (set = 0; set < 64; ++set) {
-
- bfin_write_DTEST_COMMAND(
- way << 26 |
- bank << 23 |
- subbank << 16 |
- set << 5
- );
- CSYNC();
- status = bfin_read_DTEST_DATA0();
-
- /* only worry about valid/dirty entries */
- if ((status & 0x3) != 0x3)
- continue;
-
-
- /* construct the address using the tag */
- addr = (status & 0xFFFFC800) | (subbank << 12) | (set << 5);
-
- /* flush it */
- __asm__ __volatile__("FLUSHINV[%0];" : : "a"(addr));
- }
- }
-}
-#endif
-
-int bfin_pm_suspend_mem_enter(void)
-{
- int ret;
-#ifndef CONFIG_BF60x
- int wakeup;
-#endif
-
- unsigned char *memptr = kmalloc(L1_CODE_LENGTH + L1_DATA_A_LENGTH
- + L1_DATA_B_LENGTH + L1_SCRATCH_LENGTH,
- GFP_ATOMIC);
-
- if (memptr == NULL) {
- panic("bf53x_suspend_l1_mem malloc failed");
- return -ENOMEM;
- }
-
-#ifndef CONFIG_BF60x
- wakeup = bfin_read_VR_CTL() & ~FREQ;
- wakeup |= SCKELOW;
-
-#ifdef CONFIG_PM_BFIN_WAKE_PH6
- wakeup |= PHYWE;
-#endif
-#ifdef CONFIG_PM_BFIN_WAKE_GP
- wakeup |= GPWE;
-#endif
-#endif
-
- ret = blackfin_dma_suspend();
-
- if (ret) {
- kfree(memptr);
- return ret;
- }
-
-#ifdef CONFIG_GPIO_ADI
- bfin_gpio_pm_hibernate_suspend();
-#endif
-
-#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
- flushinv_all_dcache();
- udelay(1);
-#endif
- _disable_dcplb();
- _disable_icplb();
- bf53x_suspend_l1_mem(memptr);
-
-#ifndef CONFIG_BF60x
- do_hibernate(wakeup | vr_wakeup); /* See you later! */
-#else
- bfin_cpu_pm->enter(PM_SUSPEND_MEM);
-#endif
-
- bf53x_resume_l1_mem(memptr);
-
- _enable_icplb();
- _enable_dcplb();
-
-#ifdef CONFIG_GPIO_ADI
- bfin_gpio_pm_hibernate_restore();
-#endif
- blackfin_dma_resume();
-
- kfree(memptr);
-
- return 0;
-}
-
-/*
- * bfin_pm_valid - Tell the PM core that we only support the standby sleep
- * state
- * @state: suspend state we're checking.
- *
- */
-static int bfin_pm_valid(suspend_state_t state)
-{
- return (state == PM_SUSPEND_STANDBY
-#if !(defined(BF533_FAMILY) || defined(CONFIG_BF561))
- /*
- * On BF533/2/1:
- * If we enter Hibernate the SCKE Pin is driven Low,
- * so that the SDRAM enters Self Refresh Mode.
- * However when the reset sequence that follows hibernate
- * state is executed, SCKE is driven High, taking the
- * SDRAM out of Self Refresh.
- *
- * If you reconfigure and access the SDRAM "very quickly",
- * you are likely to avoid errors, otherwise the SDRAM
- * start losing its contents.
- * An external HW workaround is possible using logic gates.
- */
- || state == PM_SUSPEND_MEM
-#endif
- );
-}
-
-/*
- * bfin_pm_enter - Actually enter a sleep state.
- * @state: State we're entering.
- *
- */
-static int bfin_pm_enter(suspend_state_t state)
-{
- switch (state) {
- case PM_SUSPEND_STANDBY:
- bfin_pm_suspend_standby_enter();
- break;
- case PM_SUSPEND_MEM:
- bfin_pm_suspend_mem_enter();
- break;
- default:
- return -EINVAL;
- }
-
- return 0;
-}
-
-#ifdef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH
-void bfin_pm_end(void)
-{
- u32 cycle, cycle2;
- u64 usec64;
- u32 usec;
-
- __asm__ __volatile__ (
- "1: %0 = CYCLES2\n"
- "%1 = CYCLES\n"
- "%2 = CYCLES2\n"
- "CC = %2 == %0\n"
- "if ! CC jump 1b\n"
- : "=d,a" (cycle2), "=d,a" (cycle), "=d,a" (usec) : : "CC"
- );
-
- usec64 = ((u64)cycle2 << 32) + cycle;
- do_div(usec64, get_cclk() / USEC_PER_SEC);
- usec = usec64;
- if (usec == 0)
- usec = 1;
-
- pr_info("PM: resume of kernel completes after %ld msec %03ld usec\n",
- usec / USEC_PER_MSEC, usec % USEC_PER_MSEC);
-}
-#endif
-
-static const struct platform_suspend_ops bfin_pm_ops = {
- .enter = bfin_pm_enter,
- .valid = bfin_pm_valid,
-#ifdef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH
- .end = bfin_pm_end,
-#endif
-};
-
-static int __init bfin_pm_init(void)
-{
- suspend_set_ops(&bfin_pm_ops);
- return 0;
-}
-
-__initcall(bfin_pm_init);
+++ /dev/null
-/*
- * arch/blackfin/mach-common/scb-init.c - reprogram system cross bar priority
- *
- * Copyright 2012 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/errno.h>
-#include <linux/kernel.h>
-#include <asm/scb.h>
-
-__attribute__((l1_text))
-inline void scb_mi_write(unsigned long scb_mi_arbw, unsigned int slots,
- unsigned char *scb_mi_prio)
-{
- unsigned int i;
-
- for (i = 0; i < slots; ++i)
- bfin_write32(scb_mi_arbw, (i << SCB_SLOT_OFFSET) | scb_mi_prio[i]);
-}
-
-__attribute__((l1_text))
-inline void scb_mi_read(unsigned long scb_mi_arbw, unsigned int slots,
- unsigned char *scb_mi_prio)
-{
- unsigned int i;
-
- for (i = 0; i < slots; ++i) {
- bfin_write32(scb_mi_arbw, (0xFF << SCB_SLOT_OFFSET) | i);
- scb_mi_prio[i] = bfin_read32(scb_mi_arbw);
- }
-}
-
-__attribute__((l1_text))
-void init_scb(void)
-{
- unsigned int i, j;
- unsigned char scb_tmp_prio[32];
-
- pr_info("Init System Crossbar\n");
- for (i = 0; scb_data[i].scb_mi_arbr > 0; ++i) {
-
- scb_mi_write(scb_data[i].scb_mi_arbw, scb_data[i].scb_mi_slots, scb_data[i].scb_mi_prio);
-
- pr_debug("scb priority at 0x%lx:\n", scb_data[i].scb_mi_arbr);
- scb_mi_read(scb_data[i].scb_mi_arbw, scb_data[i].scb_mi_slots, scb_tmp_prio);
- for (j = 0; j < scb_data[i].scb_mi_slots; ++j)
- pr_debug("slot %d = %d\n", j, scb_tmp_prio[j]);
- }
-
-}
+++ /dev/null
-/*
- * IPI management based on arch/arm/kernel/smp.c (Copyright 2002 ARM Limited)
- *
- * Copyright 2007-2009 Analog Devices Inc.
- * Philippe Gerum <rpm@xenomai.org>
- *
- * Licensed under the GPL-2.
- */
-
-#include <linux/module.h>
-#include <linux/delay.h>
-#include <linux/init.h>
-#include <linux/spinlock.h>
-#include <linux/sched/mm.h>
-#include <linux/sched/task_stack.h>
-#include <linux/interrupt.h>
-#include <linux/cache.h>
-#include <linux/clockchips.h>
-#include <linux/profile.h>
-#include <linux/errno.h>
-#include <linux/mm.h>
-#include <linux/cpu.h>
-#include <linux/smp.h>
-#include <linux/cpumask.h>
-#include <linux/seq_file.h>
-#include <linux/irq.h>
-#include <linux/slab.h>
-#include <linux/atomic.h>
-#include <asm/cacheflush.h>
-#include <asm/irq_handler.h>
-#include <asm/mmu_context.h>
-#include <asm/pgtable.h>
-#include <asm/pgalloc.h>
-#include <asm/processor.h>
-#include <asm/ptrace.h>
-#include <asm/cpu.h>
-#include <asm/time.h>
-#include <linux/err.h>
-
-/*
- * Anomaly notes:
- * 05000120 - we always define corelock as 32-bit integer in L2
- */
-struct corelock_slot corelock __attribute__ ((__section__(".l2.bss")));
-
-#ifdef CONFIG_ICACHE_FLUSH_L1
-unsigned long blackfin_iflush_l1_entry[NR_CPUS];
-#endif
-
-struct blackfin_initial_pda initial_pda_coreb;
-
-enum ipi_message_type {
- BFIN_IPI_NONE,
- BFIN_IPI_TIMER,
- BFIN_IPI_RESCHEDULE,
- BFIN_IPI_CALL_FUNC,
- BFIN_IPI_CPU_STOP,
-};
-
-struct blackfin_flush_data {
- unsigned long start;
- unsigned long end;
-};
-
-void *secondary_stack;
-
-static struct blackfin_flush_data smp_flush_data;
-
-static DEFINE_SPINLOCK(stop_lock);
-
-/* A magic number - stress test shows this is safe for common cases */
-#define BFIN_IPI_MSGQ_LEN 5
-
-/* Simple FIFO buffer, overflow leads to panic */
-struct ipi_data {
- atomic_t count;
- atomic_t bits;
-};
-
-static DEFINE_PER_CPU(struct ipi_data, bfin_ipi);
-
-static void ipi_cpu_stop(unsigned int cpu)
-{
- spin_lock(&stop_lock);
- printk(KERN_CRIT "CPU%u: stopping\n", cpu);
- dump_stack();
- spin_unlock(&stop_lock);
-
- set_cpu_online(cpu, false);
-
- local_irq_disable();
-
- while (1)
- SSYNC();
-}
-
-static void ipi_flush_icache(void *info)
-{
- struct blackfin_flush_data *fdata = info;
-
- /* Invalidate the memory holding the bounds of the flushed region. */
- blackfin_dcache_invalidate_range((unsigned long)fdata,
- (unsigned long)fdata + sizeof(*fdata));
-
- /* Make sure all write buffers in the data side of the core
- * are flushed before trying to invalidate the icache. This
- * needs to be after the data flush and before the icache
- * flush so that the SSYNC does the right thing in preventing
- * the instruction prefetcher from hitting things in cached
- * memory at the wrong time -- it runs much further ahead than
- * the pipeline.
- */
- SSYNC();
-
- /* ipi_flaush_icache is invoked by generic flush_icache_range,
- * so call blackfin arch icache flush directly here.
- */
- blackfin_icache_flush_range(fdata->start, fdata->end);
-}
-
-/* Use IRQ_SUPPLE_0 to request reschedule.
- * When returning from interrupt to user space,
- * there is chance to reschedule */
-static irqreturn_t ipi_handler_int0(int irq, void *dev_instance)
-{
- unsigned int cpu = smp_processor_id();
-
- platform_clear_ipi(cpu, IRQ_SUPPLE_0);
- return IRQ_HANDLED;
-}
-
-DECLARE_PER_CPU(struct clock_event_device, coretmr_events);
-void ipi_timer(void)
-{
- int cpu = smp_processor_id();
- struct clock_event_device *evt = &per_cpu(coretmr_events, cpu);
- evt->event_handler(evt);
-}
-
-static irqreturn_t ipi_handler_int1(int irq, void *dev_instance)
-{
- struct ipi_data *bfin_ipi_data;
- unsigned int cpu = smp_processor_id();
- unsigned long pending;
- unsigned long msg;
-
- platform_clear_ipi(cpu, IRQ_SUPPLE_1);
-
- smp_rmb();
- bfin_ipi_data = this_cpu_ptr(&bfin_ipi);
- while ((pending = atomic_xchg(&bfin_ipi_data->bits, 0)) != 0) {
- msg = 0;
- do {
- msg = find_next_bit(&pending, BITS_PER_LONG, msg + 1);
- switch (msg) {
- case BFIN_IPI_TIMER:
- ipi_timer();
- break;
- case BFIN_IPI_RESCHEDULE:
- scheduler_ipi();
- break;
- case BFIN_IPI_CALL_FUNC:
- generic_smp_call_function_interrupt();
- break;
- case BFIN_IPI_CPU_STOP:
- ipi_cpu_stop(cpu);
- break;
- default:
- goto out;
- }
- atomic_dec(&bfin_ipi_data->count);
- } while (msg < BITS_PER_LONG);
-
- }
-out:
- return IRQ_HANDLED;
-}
-
-static void bfin_ipi_init(void)
-{
- unsigned int cpu;
- struct ipi_data *bfin_ipi_data;
- for_each_possible_cpu(cpu) {
- bfin_ipi_data = &per_cpu(bfin_ipi, cpu);
- atomic_set(&bfin_ipi_data->bits, 0);
- atomic_set(&bfin_ipi_data->count, 0);
- }
-}
-
-void send_ipi(const struct cpumask *cpumask, enum ipi_message_type msg)
-{
- unsigned int cpu;
- struct ipi_data *bfin_ipi_data;
- unsigned long flags;
-
- local_irq_save(flags);
- for_each_cpu(cpu, cpumask) {
- bfin_ipi_data = &per_cpu(bfin_ipi, cpu);
- atomic_or((1 << msg), &bfin_ipi_data->bits);
- atomic_inc(&bfin_ipi_data->count);
- }
- local_irq_restore(flags);
- smp_wmb();
- for_each_cpu(cpu, cpumask)
- platform_send_ipi_cpu(cpu, IRQ_SUPPLE_1);
-}
-
-void arch_send_call_function_single_ipi(int cpu)
-{
- send_ipi(cpumask_of(cpu), BFIN_IPI_CALL_FUNC);
-}
-
-void arch_send_call_function_ipi_mask(const struct cpumask *mask)
-{
- send_ipi(mask, BFIN_IPI_CALL_FUNC);
-}
-
-void smp_send_reschedule(int cpu)
-{
- send_ipi(cpumask_of(cpu), BFIN_IPI_RESCHEDULE);
-
- return;
-}
-
-void smp_send_msg(const struct cpumask *mask, unsigned long type)
-{
- send_ipi(mask, type);
-}
-
-void smp_timer_broadcast(const struct cpumask *mask)
-{
- smp_send_msg(mask, BFIN_IPI_TIMER);
-}
-
-void smp_send_stop(void)
-{
- cpumask_t callmap;
-
- preempt_disable();
- cpumask_copy(&callmap, cpu_online_mask);
- cpumask_clear_cpu(smp_processor_id(), &callmap);
- if (!cpumask_empty(&callmap))
- send_ipi(&callmap, BFIN_IPI_CPU_STOP);
-
- preempt_enable();
-
- return;
-}
-
-int __cpu_up(unsigned int cpu, struct task_struct *idle)
-{
- int ret;
-
- secondary_stack = task_stack_page(idle) + THREAD_SIZE;
-
- ret = platform_boot_secondary(cpu, idle);
-
- secondary_stack = NULL;
-
- return ret;
-}
-
-static void setup_secondary(unsigned int cpu)
-{
- unsigned long ilat;
-
- bfin_write_IMASK(0);
- CSYNC();
- ilat = bfin_read_ILAT();
- CSYNC();
- bfin_write_ILAT(ilat);
- CSYNC();
-
- /* Enable interrupt levels IVG7-15. IARs have been already
- * programmed by the boot CPU. */
- bfin_irq_flags |= IMASK_IVG15 |
- IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
- IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
-}
-
-void secondary_start_kernel(void)
-{
- unsigned int cpu = smp_processor_id();
- struct mm_struct *mm = &init_mm;
-
- if (_bfin_swrst & SWRST_DBL_FAULT_B) {
- printk(KERN_EMERG "CoreB Recovering from DOUBLE FAULT event\n");
-#ifdef CONFIG_DEBUG_DOUBLEFAULT
- printk(KERN_EMERG " While handling exception (EXCAUSE = %#x) at %pF\n",
- initial_pda_coreb.seqstat_doublefault & SEQSTAT_EXCAUSE,
- initial_pda_coreb.retx_doublefault);
- printk(KERN_NOTICE " DCPLB_FAULT_ADDR: %pF\n",
- initial_pda_coreb.dcplb_doublefault_addr);
- printk(KERN_NOTICE " ICPLB_FAULT_ADDR: %pF\n",
- initial_pda_coreb.icplb_doublefault_addr);
-#endif
- printk(KERN_NOTICE " The instruction at %pF caused a double exception\n",
- initial_pda_coreb.retx);
- }
-
- /*
- * We want the D-cache to be enabled early, in case the atomic
- * support code emulates cache coherence (see
- * __ARCH_SYNC_CORE_DCACHE).
- */
- init_exception_vectors();
-
- local_irq_disable();
-
- /* Attach the new idle task to the global mm. */
- mmget(mm);
- mmgrab(mm);
- current->active_mm = mm;
-
- preempt_disable();
-
- setup_secondary(cpu);
-
- platform_secondary_init(cpu);
- /* setup local core timer */
- bfin_local_timer_setup();
-
- local_irq_enable();
-
- bfin_setup_caches(cpu);
-
- notify_cpu_starting(cpu);
- /*
- * Calibrate loops per jiffy value.
- * IRQs need to be enabled here - D-cache can be invalidated
- * in timer irq handler, so core B can read correct jiffies.
- */
- calibrate_delay();
-
- /* We are done with local CPU inits, unblock the boot CPU. */
- set_cpu_online(cpu, true);
- cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
-}
-
-void __init smp_prepare_boot_cpu(void)
-{
-}
-
-void __init smp_prepare_cpus(unsigned int max_cpus)
-{
- platform_prepare_cpus(max_cpus);
- bfin_ipi_init();
- platform_request_ipi(IRQ_SUPPLE_0, ipi_handler_int0);
- platform_request_ipi(IRQ_SUPPLE_1, ipi_handler_int1);
-}
-
-void __init smp_cpus_done(unsigned int max_cpus)
-{
- unsigned long bogosum = 0;
- unsigned int cpu;
-
- for_each_online_cpu(cpu)
- bogosum += loops_per_jiffy;
-
- printk(KERN_INFO "SMP: Total of %d processors activated "
- "(%lu.%02lu BogoMIPS).\n",
- num_online_cpus(),
- bogosum / (500000/HZ),
- (bogosum / (5000/HZ)) % 100);
-}
-
-void smp_icache_flush_range_others(unsigned long start, unsigned long end)
-{
- smp_flush_data.start = start;
- smp_flush_data.end = end;
-
- preempt_disable();
- if (smp_call_function(&ipi_flush_icache, &smp_flush_data, 1))
- printk(KERN_WARNING "SMP: failed to run I-cache flush request on other CPUs\n");
- preempt_enable();
-}
-EXPORT_SYMBOL_GPL(smp_icache_flush_range_others);
-
-#ifdef __ARCH_SYNC_CORE_ICACHE
-unsigned long icache_invld_count[NR_CPUS];
-void resync_core_icache(void)
-{
- unsigned int cpu = get_cpu();
- blackfin_invalidate_entire_icache();
- icache_invld_count[cpu]++;
- put_cpu();
-}
-EXPORT_SYMBOL(resync_core_icache);
-#endif
-
-#ifdef __ARCH_SYNC_CORE_DCACHE
-unsigned long dcache_invld_count[NR_CPUS];
-unsigned long barrier_mask __attribute__ ((__section__(".l2.bss")));
-
-void resync_core_dcache(void)
-{
- unsigned int cpu = get_cpu();
- blackfin_invalidate_entire_dcache();
- dcache_invld_count[cpu]++;
- put_cpu();
-}
-EXPORT_SYMBOL(resync_core_dcache);
-#endif
-
-#ifdef CONFIG_HOTPLUG_CPU
-int __cpu_disable(void)
-{
- unsigned int cpu = smp_processor_id();
-
- if (cpu == 0)
- return -EPERM;
-
- set_cpu_online(cpu, false);
- return 0;
-}
-
-int __cpu_die(unsigned int cpu)
-{
- return cpu_wait_death(cpu, 5);
-}
-
-void cpu_die(void)
-{
- (void)cpu_report_death();
-
- atomic_dec(&init_mm.mm_users);
- atomic_dec(&init_mm.mm_count);
-
- local_irq_disable();
- platform_cpu_die();
-}
-#endif
+++ /dev/null
-#
-# arch/blackfin/mm/Makefile
-#
-
-obj-y := sram-alloc.o isram-driver.o init.o maccess.o
+++ /dev/null
-/*
- * Local prototypes meant for internal use only
- *
- * Copyright 2006-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BLACKFIN_SRAM_H__
-#define __BLACKFIN_SRAM_H__
-
-extern void *l1sram_alloc(size_t);
-
-#endif
+++ /dev/null
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/gfp.h>
-#include <linux/swap.h>
-#include <linux/bootmem.h>
-#include <linux/uaccess.h>
-#include <linux/export.h>
-#include <asm/bfin-global.h>
-#include <asm/pda.h>
-#include <asm/cplbinit.h>
-#include <asm/early_printk.h>
-#include "blackfin_sram.h"
-
-/*
- * ZERO_PAGE is a special page that is used for zero-initialized data and COW.
- * Let the bss do its zero-init magic so we don't have to do it ourselves.
- */
-char empty_zero_page[PAGE_SIZE] __attribute__((aligned(PAGE_SIZE)));
-EXPORT_SYMBOL(empty_zero_page);
-
-#ifndef CONFIG_EXCEPTION_L1_SCRATCH
-#if defined CONFIG_SYSCALL_TAB_L1
-__attribute__((l1_data))
-#endif
-static unsigned long exception_stack[NR_CPUS][1024];
-#endif
-
-struct blackfin_pda cpu_pda[NR_CPUS];
-EXPORT_SYMBOL(cpu_pda);
-
-/*
- * paging_init() continues the virtual memory environment setup which
- * was begun by the code in arch/head.S.
- * The parameters are pointers to where to stick the starting and ending
- * addresses of available kernel virtual memory.
- */
-void __init paging_init(void)
-{
- /*
- * make sure start_mem is page aligned, otherwise bootmem and
- * page_alloc get different views of the world
- */
- unsigned long end_mem = memory_end & PAGE_MASK;
-
- unsigned long zones_size[MAX_NR_ZONES] = {
- [0] = 0,
- [ZONE_DMA] = (end_mem - CONFIG_PHY_RAM_BASE_ADDRESS) >> PAGE_SHIFT,
- [ZONE_NORMAL] = 0,
-#ifdef CONFIG_HIGHMEM
- [ZONE_HIGHMEM] = 0,
-#endif
- };
-
- /* Set up SFC/DFC registers (user data space) */
- set_fs(KERNEL_DS);
-
- pr_debug("free_area_init -> start_mem is %#lx virtual_end is %#lx\n",
- PAGE_ALIGN(memory_start), end_mem);
- free_area_init_node(0, zones_size,
- CONFIG_PHY_RAM_BASE_ADDRESS >> PAGE_SHIFT, NULL);
-}
-
-asmlinkage void __init init_pda(void)
-{
- unsigned int cpu = raw_smp_processor_id();
-
- early_shadow_stamp();
-
- /* Initialize the PDA fields holding references to other parts
- of the memory. The content of such memory is still
- undefined at the time of the call, we are only setting up
- valid pointers to it. */
- memset(&cpu_pda[cpu], 0, sizeof(cpu_pda[cpu]));
-
-#ifdef CONFIG_EXCEPTION_L1_SCRATCH
- cpu_pda[cpu].ex_stack = (unsigned long *)(L1_SCRATCH_START + \
- L1_SCRATCH_LENGTH);
-#else
- cpu_pda[cpu].ex_stack = exception_stack[cpu + 1];
-#endif
-
-#ifdef CONFIG_SMP
- cpu_pda[cpu].imask = 0x1f;
-#endif
-}
-
-void __init mem_init(void)
-{
- char buf[64];
-
- high_memory = (void *)(memory_end & PAGE_MASK);
- max_mapnr = MAP_NR(high_memory);
- printk(KERN_DEBUG "Kernel managed physical pages: %lu\n", max_mapnr);
-
- /* This will put all low memory onto the freelists. */
- free_all_bootmem();
-
- snprintf(buf, sizeof(buf) - 1, "%uK DMA", DMA_UNCACHED_REGION >> 10);
- mem_init_print_info(buf);
-}
-
-#ifdef CONFIG_BLK_DEV_INITRD
-void __init free_initrd_mem(unsigned long start, unsigned long end)
-{
-#ifndef CONFIG_MPU
- free_reserved_area((void *)start, (void *)end, -1, "initrd");
-#endif
-}
-#endif
-
-void __ref free_initmem(void)
-{
-#if defined CONFIG_RAMKERNEL && !defined CONFIG_MPU
- free_initmem_default(-1);
- if (memory_start == (unsigned long)(&__init_end))
- memory_start = (unsigned long)(&__init_begin);
-#endif
-}
+++ /dev/null
-/*
- * Instruction SRAM accessor functions for the Blackfin
- *
- * Copyright 2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#define pr_fmt(fmt) "isram: " fmt
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/slab.h>
-#include <linux/spinlock.h>
-#include <linux/sched.h>
-#include <linux/sched/debug.h>
-
-#include <asm/blackfin.h>
-#include <asm/dma.h>
-
-/*
- * IMPORTANT WARNING ABOUT THESE FUNCTIONS
- *
- * The emulator will not function correctly if a write command is left in
- * ITEST_COMMAND or DTEST_COMMAND AND access to cache memory is needed by
- * the emulator. To avoid such problems, ensure that both ITEST_COMMAND
- * and DTEST_COMMAND are zero when exiting these functions.
- */
-
-
-/*
- * On the Blackfin, L1 instruction sram (which operates at core speeds) can not
- * be accessed by a normal core load, so we need to go through a few hoops to
- * read/write it.
- * To try to make it easier - we export a memcpy interface, where either src or
- * dest can be in this special L1 memory area.
- * The low level read/write functions should not be exposed to the rest of the
- * kernel, since they operate on 64-bit data, and need specific address alignment
- */
-
-static DEFINE_SPINLOCK(dtest_lock);
-
-/* Takes a void pointer */
-#define IADDR2DTEST(x) \
- ({ unsigned long __addr = (unsigned long)(x); \
- ((__addr & (1 << 11)) << (26 - 11)) | /* addr bit 11 (Way0/Way1) */ \
- (1 << 24) | /* instruction access = 1 */ \
- ((__addr & (1 << 15)) << (23 - 15)) | /* addr bit 15 (Data Bank) */ \
- ((__addr & (3 << 12)) << (16 - 12)) | /* addr bits 13:12 (Subbank) */ \
- (__addr & 0x47F8) | /* addr bits 14 & 10:3 */ \
- (1 << 2); /* data array = 1 */ \
- })
-
-/* Takes a pointer, and returns the offset (in bits) which things should be shifted */
-#define ADDR2OFFSET(x) ((((unsigned long)(x)) & 0x7) * 8)
-
-/* Takes a pointer, determines if it is the last byte in the isram 64-bit data type */
-#define ADDR2LAST(x) ((((unsigned long)x) & 0x7) == 0x7)
-
-static void isram_write(const void *addr, uint64_t data)
-{
- uint32_t cmd;
- unsigned long flags;
-
- if (unlikely(addr >= (void *)(L1_CODE_START + L1_CODE_LENGTH)))
- return;
-
- cmd = IADDR2DTEST(addr) | 2; /* write */
-
- /*
- * Writes to DTEST_DATA[0:1] need to be atomic with write to DTEST_COMMAND
- * While in exception context - atomicity is guaranteed or double fault
- */
- spin_lock_irqsave(&dtest_lock, flags);
-
- bfin_write_DTEST_DATA0(data & 0xFFFFFFFF);
- bfin_write_DTEST_DATA1(data >> 32);
-
- /* use the builtin, since interrupts are already turned off */
- __builtin_bfin_csync();
- bfin_write_DTEST_COMMAND(cmd);
- __builtin_bfin_csync();
-
- bfin_write_DTEST_COMMAND(0);
- __builtin_bfin_csync();
-
- spin_unlock_irqrestore(&dtest_lock, flags);
-}
-
-static uint64_t isram_read(const void *addr)
-{
- uint32_t cmd;
- unsigned long flags;
- uint64_t ret;
-
- if (unlikely(addr > (void *)(L1_CODE_START + L1_CODE_LENGTH)))
- return 0;
-
- cmd = IADDR2DTEST(addr) | 0; /* read */
-
- /*
- * Reads of DTEST_DATA[0:1] need to be atomic with write to DTEST_COMMAND
- * While in exception context - atomicity is guaranteed or double fault
- */
- spin_lock_irqsave(&dtest_lock, flags);
- /* use the builtin, since interrupts are already turned off */
- __builtin_bfin_csync();
- bfin_write_DTEST_COMMAND(cmd);
- __builtin_bfin_csync();
- ret = bfin_read_DTEST_DATA0() | ((uint64_t)bfin_read_DTEST_DATA1() << 32);
-
- bfin_write_DTEST_COMMAND(0);
- __builtin_bfin_csync();
- spin_unlock_irqrestore(&dtest_lock, flags);
-
- return ret;
-}
-
-static bool isram_check_addr(const void *addr, size_t n)
-{
- if ((addr >= (void *)L1_CODE_START) &&
- (addr < (void *)(L1_CODE_START + L1_CODE_LENGTH))) {
- if (unlikely((addr + n) > (void *)(L1_CODE_START + L1_CODE_LENGTH))) {
- show_stack(NULL, NULL);
- pr_err("copy involving %p length (%zu) too long\n", addr, n);
- }
- return true;
- }
- return false;
-}
-
-/*
- * The isram_memcpy() function copies n bytes from memory area src to memory area dest.
- * The isram_memcpy() function returns a pointer to dest.
- * Either dest or src can be in L1 instruction sram.
- */
-void *isram_memcpy(void *dest, const void *src, size_t n)
-{
- uint64_t data_in = 0, data_out = 0;
- size_t count;
- bool dest_in_l1, src_in_l1, need_data, put_data;
- unsigned char byte, *src_byte, *dest_byte;
-
- src_byte = (unsigned char *)src;
- dest_byte = (unsigned char *)dest;
-
- dest_in_l1 = isram_check_addr(dest, n);
- src_in_l1 = isram_check_addr(src, n);
-
- need_data = true;
- put_data = true;
- for (count = 0; count < n; count++) {
- if (src_in_l1) {
- if (need_data) {
- data_in = isram_read(src + count);
- need_data = false;
- }
-
- if (ADDR2LAST(src + count))
- need_data = true;
-
- byte = (unsigned char)((data_in >> ADDR2OFFSET(src + count)) & 0xff);
-
- } else {
- /* src is in L2 or L3 - so just dereference*/
- byte = src_byte[count];
- }
-
- if (dest_in_l1) {
- if (put_data) {
- data_out = isram_read(dest + count);
- put_data = false;
- }
-
- data_out &= ~((uint64_t)0xff << ADDR2OFFSET(dest + count));
- data_out |= ((uint64_t)byte << ADDR2OFFSET(dest + count));
-
- if (ADDR2LAST(dest + count)) {
- put_data = true;
- isram_write(dest + count, data_out);
- }
- } else {
- /* dest in L2 or L3 - so just dereference */
- dest_byte[count] = byte;
- }
- }
-
- /* make sure we dump the last byte if necessary */
- if (dest_in_l1 && !put_data)
- isram_write(dest + count, data_out);
-
- return dest;
-}
-EXPORT_SYMBOL(isram_memcpy);
-
-#ifdef CONFIG_BFIN_ISRAM_SELF_TEST
-
-static int test_len = 0x20000;
-
-static __init void hex_dump(unsigned char *buf, int len)
-{
- while (len--)
- pr_cont("%02x", *buf++);
-}
-
-static __init int isram_read_test(char *sdram, void *l1inst)
-{
- int i, ret = 0;
- uint64_t data1, data2;
-
- pr_info("INFO: running isram_read tests\n");
-
- /* setup some different data to play with */
- for (i = 0; i < test_len; ++i)
- sdram[i] = i % 255;
- dma_memcpy(l1inst, sdram, test_len);
-
- /* make sure we can read the L1 inst */
- for (i = 0; i < test_len; i += sizeof(uint64_t)) {
- data1 = isram_read(l1inst + i);
- memcpy(&data2, sdram + i, sizeof(data2));
- if (data1 != data2) {
- pr_err("FAIL: isram_read(%p) returned %#llx but wanted %#llx\n",
- l1inst + i, data1, data2);
- ++ret;
- }
- }
-
- return ret;
-}
-
-static __init int isram_write_test(char *sdram, void *l1inst)
-{
- int i, ret = 0;
- uint64_t data1, data2;
-
- pr_info("INFO: running isram_write tests\n");
-
- /* setup some different data to play with */
- memset(sdram, 0, test_len * 2);
- dma_memcpy(l1inst, sdram, test_len);
- for (i = 0; i < test_len; ++i)
- sdram[i] = i % 255;
-
- /* make sure we can write the L1 inst */
- for (i = 0; i < test_len; i += sizeof(uint64_t)) {
- memcpy(&data1, sdram + i, sizeof(data1));
- isram_write(l1inst + i, data1);
- data2 = isram_read(l1inst + i);
- if (data1 != data2) {
- pr_err("FAIL: isram_write(%p, %#llx) != %#llx\n",
- l1inst + i, data1, data2);
- ++ret;
- }
- }
-
- dma_memcpy(sdram + test_len, l1inst, test_len);
- if (memcmp(sdram, sdram + test_len, test_len)) {
- pr_err("FAIL: isram_write() did not work properly\n");
- ++ret;
- }
-
- return ret;
-}
-
-static __init int
-_isram_memcpy_test(char pattern, void *sdram, void *l1inst, const char *smemcpy,
- void *(*fmemcpy)(void *, const void *, size_t))
-{
- memset(sdram, pattern, test_len);
- fmemcpy(l1inst, sdram, test_len);
- fmemcpy(sdram + test_len, l1inst, test_len);
- if (memcmp(sdram, sdram + test_len, test_len)) {
- pr_err("FAIL: %s(%p <=> %p, %#x) failed (data is %#x)\n",
- smemcpy, l1inst, sdram, test_len, pattern);
- return 1;
- }
- return 0;
-}
-#define _isram_memcpy_test(a, b, c, d) _isram_memcpy_test(a, b, c, #d, d)
-
-static __init int isram_memcpy_test(char *sdram, void *l1inst)
-{
- int i, j, thisret, ret = 0;
-
- /* check broad isram_memcpy() */
- pr_info("INFO: running broad isram_memcpy tests\n");
- for (i = 0xf; i >= 0; --i)
- ret += _isram_memcpy_test(i, sdram, l1inst, isram_memcpy);
-
- /* check read of small, unaligned, and hardware 64bit limits */
- pr_info("INFO: running isram_memcpy (read) tests\n");
-
- /* setup some different data to play with */
- for (i = 0; i < test_len; ++i)
- sdram[i] = i % 255;
- dma_memcpy(l1inst, sdram, test_len);
-
- thisret = 0;
- for (i = 0; i < test_len - 32; ++i) {
- unsigned char cmp[32];
- for (j = 1; j <= 32; ++j) {
- memset(cmp, 0, sizeof(cmp));
- isram_memcpy(cmp, l1inst + i, j);
- if (memcmp(cmp, sdram + i, j)) {
- pr_err("FAIL: %p:", l1inst + 1);
- hex_dump(cmp, j);
- pr_cont(" SDRAM:");
- hex_dump(sdram + i, j);
- pr_cont("\n");
- if (++thisret > 20) {
- pr_err("FAIL: skipping remaining series\n");
- i = test_len;
- break;
- }
- }
- }
- }
- ret += thisret;
-
- /* check write of small, unaligned, and hardware 64bit limits */
- pr_info("INFO: running isram_memcpy (write) tests\n");
-
- memset(sdram + test_len, 0, test_len);
- dma_memcpy(l1inst, sdram + test_len, test_len);
-
- thisret = 0;
- for (i = 0; i < test_len - 32; ++i) {
- unsigned char cmp[32];
- for (j = 1; j <= 32; ++j) {
- isram_memcpy(l1inst + i, sdram + i, j);
- dma_memcpy(cmp, l1inst + i, j);
- if (memcmp(cmp, sdram + i, j)) {
- pr_err("FAIL: %p:", l1inst + i);
- hex_dump(cmp, j);
- pr_cont(" SDRAM:");
- hex_dump(sdram + i, j);
- pr_cont("\n");
- if (++thisret > 20) {
- pr_err("FAIL: skipping remaining series\n");
- i = test_len;
- break;
- }
- }
- }
- }
- ret += thisret;
-
- return ret;
-}
-
-static __init int isram_test_init(void)
-{
- int ret;
- char *sdram;
- void *l1inst;
-
- /* Try to test as much of L1SRAM as possible */
- while (test_len) {
- test_len >>= 1;
- l1inst = l1_inst_sram_alloc(test_len);
- if (l1inst)
- break;
- }
- if (!l1inst) {
- pr_warning("SKIP: could not allocate L1 inst\n");
- return 0;
- }
- pr_info("INFO: testing %#x bytes (%p - %p)\n",
- test_len, l1inst, l1inst + test_len);
-
- sdram = kmalloc(test_len * 2, GFP_KERNEL);
- if (!sdram) {
- sram_free(l1inst);
- pr_warning("SKIP: could not allocate sdram\n");
- return 0;
- }
-
- /* sanity check initial L1 inst state */
- ret = 1;
- pr_info("INFO: running initial dma_memcpy checks %p\n", sdram);
- if (_isram_memcpy_test(0xa, sdram, l1inst, dma_memcpy))
- goto abort;
- if (_isram_memcpy_test(0x5, sdram, l1inst, dma_memcpy))
- goto abort;
-
- ret = 0;
- ret += isram_read_test(sdram, l1inst);
- ret += isram_write_test(sdram, l1inst);
- ret += isram_memcpy_test(sdram, l1inst);
-
- abort:
- sram_free(l1inst);
- kfree(sdram);
-
- if (ret)
- return -EIO;
-
- pr_info("PASS: all tests worked !\n");
- return 0;
-}
-late_initcall(isram_test_init);
-
-static __exit void isram_test_exit(void)
-{
- /* stub to allow unloading */
-}
-module_exit(isram_test_exit);
-
-#endif
+++ /dev/null
-/*
- * safe read and write memory routines callable while atomic
- *
- * Copyright 2005-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/uaccess.h>
-#include <asm/dma.h>
-
-static int validate_memory_access_address(unsigned long addr, int size)
-{
- if (size < 0 || addr == 0)
- return -EFAULT;
- return bfin_mem_access_type(addr, size);
-}
-
-long probe_kernel_read(void *dst, const void *src, size_t size)
-{
- unsigned long lsrc = (unsigned long)src;
- int mem_type;
-
- mem_type = validate_memory_access_address(lsrc, size);
- if (mem_type < 0)
- return mem_type;
-
- if (lsrc >= SYSMMR_BASE) {
- if (size == 2 && lsrc % 2 == 0) {
- u16 mmr = bfin_read16(src);
- memcpy(dst, &mmr, sizeof(mmr));
- return 0;
- } else if (size == 4 && lsrc % 4 == 0) {
- u32 mmr = bfin_read32(src);
- memcpy(dst, &mmr, sizeof(mmr));
- return 0;
- }
- } else {
- switch (mem_type) {
- case BFIN_MEM_ACCESS_CORE:
- case BFIN_MEM_ACCESS_CORE_ONLY:
- return __probe_kernel_read(dst, src, size);
- /* XXX: should support IDMA here with SMP */
- case BFIN_MEM_ACCESS_DMA:
- if (dma_memcpy(dst, src, size))
- return 0;
- break;
- case BFIN_MEM_ACCESS_ITEST:
- if (isram_memcpy(dst, src, size))
- return 0;
- break;
- }
- }
-
- return -EFAULT;
-}
-
-long probe_kernel_write(void *dst, const void *src, size_t size)
-{
- unsigned long ldst = (unsigned long)dst;
- int mem_type;
-
- mem_type = validate_memory_access_address(ldst, size);
- if (mem_type < 0)
- return mem_type;
-
- if (ldst >= SYSMMR_BASE) {
- if (size == 2 && ldst % 2 == 0) {
- u16 mmr;
- memcpy(&mmr, src, sizeof(mmr));
- bfin_write16(dst, mmr);
- return 0;
- } else if (size == 4 && ldst % 4 == 0) {
- u32 mmr;
- memcpy(&mmr, src, sizeof(mmr));
- bfin_write32(dst, mmr);
- return 0;
- }
- } else {
- switch (mem_type) {
- case BFIN_MEM_ACCESS_CORE:
- case BFIN_MEM_ACCESS_CORE_ONLY:
- return __probe_kernel_write(dst, src, size);
- /* XXX: should support IDMA here with SMP */
- case BFIN_MEM_ACCESS_DMA:
- if (dma_memcpy(dst, src, size))
- return 0;
- break;
- case BFIN_MEM_ACCESS_ITEST:
- if (isram_memcpy(dst, src, size))
- return 0;
- break;
- }
- }
-
- return -EFAULT;
-}
+++ /dev/null
-/*
- * SRAM allocator for Blackfin on-chip memory
- *
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/miscdevice.h>
-#include <linux/ioport.h>
-#include <linux/fcntl.h>
-#include <linux/init.h>
-#include <linux/poll.h>
-#include <linux/proc_fs.h>
-#include <linux/seq_file.h>
-#include <linux/spinlock.h>
-#include <linux/rtc.h>
-#include <linux/slab.h>
-#include <linux/mm_types.h>
-
-#include <asm/blackfin.h>
-#include <asm/mem_map.h>
-#include "blackfin_sram.h"
-
-/* the data structure for L1 scratchpad and DATA SRAM */
-struct sram_piece {
- void *paddr;
- int size;
- pid_t pid;
- struct sram_piece *next;
-};
-
-static DEFINE_PER_CPU_SHARED_ALIGNED(spinlock_t, l1sram_lock);
-static DEFINE_PER_CPU(struct sram_piece, free_l1_ssram_head);
-static DEFINE_PER_CPU(struct sram_piece, used_l1_ssram_head);
-
-#if L1_DATA_A_LENGTH != 0
-static DEFINE_PER_CPU(struct sram_piece, free_l1_data_A_sram_head);
-static DEFINE_PER_CPU(struct sram_piece, used_l1_data_A_sram_head);
-#endif
-
-#if L1_DATA_B_LENGTH != 0
-static DEFINE_PER_CPU(struct sram_piece, free_l1_data_B_sram_head);
-static DEFINE_PER_CPU(struct sram_piece, used_l1_data_B_sram_head);
-#endif
-
-#if L1_DATA_A_LENGTH || L1_DATA_B_LENGTH
-static DEFINE_PER_CPU_SHARED_ALIGNED(spinlock_t, l1_data_sram_lock);
-#endif
-
-#if L1_CODE_LENGTH != 0
-static DEFINE_PER_CPU_SHARED_ALIGNED(spinlock_t, l1_inst_sram_lock);
-static DEFINE_PER_CPU(struct sram_piece, free_l1_inst_sram_head);
-static DEFINE_PER_CPU(struct sram_piece, used_l1_inst_sram_head);
-#endif
-
-#if L2_LENGTH != 0
-static spinlock_t l2_sram_lock ____cacheline_aligned_in_smp;
-static struct sram_piece free_l2_sram_head, used_l2_sram_head;
-#endif
-
-static struct kmem_cache *sram_piece_cache;
-
-/* L1 Scratchpad SRAM initialization function */
-static void __init l1sram_init(void)
-{
- unsigned int cpu;
- unsigned long reserve;
-
-#ifdef CONFIG_SMP
- reserve = 0;
-#else
- reserve = sizeof(struct l1_scratch_task_info);
-#endif
-
- for (cpu = 0; cpu < num_possible_cpus(); ++cpu) {
- per_cpu(free_l1_ssram_head, cpu).next =
- kmem_cache_alloc(sram_piece_cache, GFP_KERNEL);
- if (!per_cpu(free_l1_ssram_head, cpu).next) {
- printk(KERN_INFO "Fail to initialize Scratchpad data SRAM.\n");
- return;
- }
-
- per_cpu(free_l1_ssram_head, cpu).next->paddr = (void *)get_l1_scratch_start_cpu(cpu) + reserve;
- per_cpu(free_l1_ssram_head, cpu).next->size = L1_SCRATCH_LENGTH - reserve;
- per_cpu(free_l1_ssram_head, cpu).next->pid = 0;
- per_cpu(free_l1_ssram_head, cpu).next->next = NULL;
-
- per_cpu(used_l1_ssram_head, cpu).next = NULL;
-
- /* mutex initialize */
- spin_lock_init(&per_cpu(l1sram_lock, cpu));
- printk(KERN_INFO "Blackfin Scratchpad data SRAM: %d KB\n",
- L1_SCRATCH_LENGTH >> 10);
- }
-}
-
-static void __init l1_data_sram_init(void)
-{
-#if L1_DATA_A_LENGTH != 0 || L1_DATA_B_LENGTH != 0
- unsigned int cpu;
-#endif
-#if L1_DATA_A_LENGTH != 0
- for (cpu = 0; cpu < num_possible_cpus(); ++cpu) {
- per_cpu(free_l1_data_A_sram_head, cpu).next =
- kmem_cache_alloc(sram_piece_cache, GFP_KERNEL);
- if (!per_cpu(free_l1_data_A_sram_head, cpu).next) {
- printk(KERN_INFO "Fail to initialize L1 Data A SRAM.\n");
- return;
- }
-
- per_cpu(free_l1_data_A_sram_head, cpu).next->paddr =
- (void *)get_l1_data_a_start_cpu(cpu) + (_ebss_l1 - _sdata_l1);
- per_cpu(free_l1_data_A_sram_head, cpu).next->size =
- L1_DATA_A_LENGTH - (_ebss_l1 - _sdata_l1);
- per_cpu(free_l1_data_A_sram_head, cpu).next->pid = 0;
- per_cpu(free_l1_data_A_sram_head, cpu).next->next = NULL;
-
- per_cpu(used_l1_data_A_sram_head, cpu).next = NULL;
-
- printk(KERN_INFO "Blackfin L1 Data A SRAM: %d KB (%d KB free)\n",
- L1_DATA_A_LENGTH >> 10,
- per_cpu(free_l1_data_A_sram_head, cpu).next->size >> 10);
- }
-#endif
-#if L1_DATA_B_LENGTH != 0
- for (cpu = 0; cpu < num_possible_cpus(); ++cpu) {
- per_cpu(free_l1_data_B_sram_head, cpu).next =
- kmem_cache_alloc(sram_piece_cache, GFP_KERNEL);
- if (!per_cpu(free_l1_data_B_sram_head, cpu).next) {
- printk(KERN_INFO "Fail to initialize L1 Data B SRAM.\n");
- return;
- }
-
- per_cpu(free_l1_data_B_sram_head, cpu).next->paddr =
- (void *)get_l1_data_b_start_cpu(cpu) + (_ebss_b_l1 - _sdata_b_l1);
- per_cpu(free_l1_data_B_sram_head, cpu).next->size =
- L1_DATA_B_LENGTH - (_ebss_b_l1 - _sdata_b_l1);
- per_cpu(free_l1_data_B_sram_head, cpu).next->pid = 0;
- per_cpu(free_l1_data_B_sram_head, cpu).next->next = NULL;
-
- per_cpu(used_l1_data_B_sram_head, cpu).next = NULL;
-
- printk(KERN_INFO "Blackfin L1 Data B SRAM: %d KB (%d KB free)\n",
- L1_DATA_B_LENGTH >> 10,
- per_cpu(free_l1_data_B_sram_head, cpu).next->size >> 10);
- /* mutex initialize */
- }
-#endif
-
-#if L1_DATA_A_LENGTH != 0 || L1_DATA_B_LENGTH != 0
- for (cpu = 0; cpu < num_possible_cpus(); ++cpu)
- spin_lock_init(&per_cpu(l1_data_sram_lock, cpu));
-#endif
-}
-
-static void __init l1_inst_sram_init(void)
-{
-#if L1_CODE_LENGTH != 0
- unsigned int cpu;
- for (cpu = 0; cpu < num_possible_cpus(); ++cpu) {
- per_cpu(free_l1_inst_sram_head, cpu).next =
- kmem_cache_alloc(sram_piece_cache, GFP_KERNEL);
- if (!per_cpu(free_l1_inst_sram_head, cpu).next) {
- printk(KERN_INFO "Failed to initialize L1 Instruction SRAM\n");
- return;
- }
-
- per_cpu(free_l1_inst_sram_head, cpu).next->paddr =
- (void *)get_l1_code_start_cpu(cpu) + (_etext_l1 - _stext_l1);
- per_cpu(free_l1_inst_sram_head, cpu).next->size =
- L1_CODE_LENGTH - (_etext_l1 - _stext_l1);
- per_cpu(free_l1_inst_sram_head, cpu).next->pid = 0;
- per_cpu(free_l1_inst_sram_head, cpu).next->next = NULL;
-
- per_cpu(used_l1_inst_sram_head, cpu).next = NULL;
-
- printk(KERN_INFO "Blackfin L1 Instruction SRAM: %d KB (%d KB free)\n",
- L1_CODE_LENGTH >> 10,
- per_cpu(free_l1_inst_sram_head, cpu).next->size >> 10);
-
- /* mutex initialize */
- spin_lock_init(&per_cpu(l1_inst_sram_lock, cpu));
- }
-#endif
-}
-
-#ifdef __ADSPBF60x__
-static irqreturn_t l2_ecc_err(int irq, void *dev_id)
-{
- int status;
-
- printk(KERN_ERR "L2 ecc error happened\n");
- status = bfin_read32(L2CTL0_STAT);
- if (status & 0x1)
- printk(KERN_ERR "Core channel error type:0x%x, addr:0x%x\n",
- bfin_read32(L2CTL0_ET0), bfin_read32(L2CTL0_EADDR0));
- if (status & 0x2)
- printk(KERN_ERR "System channel error type:0x%x, addr:0x%x\n",
- bfin_read32(L2CTL0_ET1), bfin_read32(L2CTL0_EADDR1));
-
- status = status >> 8;
- if (status)
- printk(KERN_ERR "L2 Bank%d error, addr:0x%x\n",
- status, bfin_read32(L2CTL0_ERRADDR0 + status));
-
- panic("L2 Ecc error");
- return IRQ_HANDLED;
-}
-#endif
-
-static void __init l2_sram_init(void)
-{
-#if L2_LENGTH != 0
-
-#ifdef __ADSPBF60x__
- int ret;
-
- ret = request_irq(IRQ_L2CTL0_ECC_ERR, l2_ecc_err, 0, "l2-ecc-err",
- NULL);
- if (unlikely(ret < 0)) {
- printk(KERN_INFO "Fail to request l2 ecc error interrupt");
- return;
- }
-#endif
-
- free_l2_sram_head.next =
- kmem_cache_alloc(sram_piece_cache, GFP_KERNEL);
- if (!free_l2_sram_head.next) {
- printk(KERN_INFO "Fail to initialize L2 SRAM.\n");
- return;
- }
-
- free_l2_sram_head.next->paddr =
- (void *)L2_START + (_ebss_l2 - _stext_l2);
- free_l2_sram_head.next->size =
- L2_LENGTH - (_ebss_l2 - _stext_l2);
- free_l2_sram_head.next->pid = 0;
- free_l2_sram_head.next->next = NULL;
-
- used_l2_sram_head.next = NULL;
-
- printk(KERN_INFO "Blackfin L2 SRAM: %d KB (%d KB free)\n",
- L2_LENGTH >> 10,
- free_l2_sram_head.next->size >> 10);
-
- /* mutex initialize */
- spin_lock_init(&l2_sram_lock);
-#endif
-}
-
-static int __init bfin_sram_init(void)
-{
- sram_piece_cache = kmem_cache_create("sram_piece_cache",
- sizeof(struct sram_piece),
- 0, SLAB_PANIC, NULL);
-
- l1sram_init();
- l1_data_sram_init();
- l1_inst_sram_init();
- l2_sram_init();
-
- return 0;
-}
-pure_initcall(bfin_sram_init);
-
-/* SRAM allocate function */
-static void *_sram_alloc(size_t size, struct sram_piece *pfree_head,
- struct sram_piece *pused_head)
-{
- struct sram_piece *pslot, *plast, *pavail;
-
- if (size <= 0 || !pfree_head || !pused_head)
- return NULL;
-
- /* Align the size */
- size = (size + 3) & ~3;
-
- pslot = pfree_head->next;
- plast = pfree_head;
-
- /* search an available piece slot */
- while (pslot != NULL && size > pslot->size) {
- plast = pslot;
- pslot = pslot->next;
- }
-
- if (!pslot)
- return NULL;
-
- if (pslot->size == size) {
- plast->next = pslot->next;
- pavail = pslot;
- } else {
- /* use atomic so our L1 allocator can be used atomically */
- pavail = kmem_cache_alloc(sram_piece_cache, GFP_ATOMIC);
-
- if (!pavail)
- return NULL;
-
- pavail->paddr = pslot->paddr;
- pavail->size = size;
- pslot->paddr += size;
- pslot->size -= size;
- }
-
- pavail->pid = current->pid;
-
- pslot = pused_head->next;
- plast = pused_head;
-
- /* insert new piece into used piece list !!! */
- while (pslot != NULL && pavail->paddr < pslot->paddr) {
- plast = pslot;
- pslot = pslot->next;
- }
-
- pavail->next = pslot;
- plast->next = pavail;
-
- return pavail->paddr;
-}
-
-/* Allocate the largest available block. */
-static void *_sram_alloc_max(struct sram_piece *pfree_head,
- struct sram_piece *pused_head,
- unsigned long *psize)
-{
- struct sram_piece *pslot, *pmax;
-
- if (!pfree_head || !pused_head)
- return NULL;
-
- pmax = pslot = pfree_head->next;
-
- /* search an available piece slot */
- while (pslot != NULL) {
- if (pslot->size > pmax->size)
- pmax = pslot;
- pslot = pslot->next;
- }
-
- if (!pmax)
- return NULL;
-
- *psize = pmax->size;
-
- return _sram_alloc(*psize, pfree_head, pused_head);
-}
-
-/* SRAM free function */
-static int _sram_free(const void *addr,
- struct sram_piece *pfree_head,
- struct sram_piece *pused_head)
-{
- struct sram_piece *pslot, *plast, *pavail;
-
- if (!pfree_head || !pused_head)
- return -1;
-
- /* search the relevant memory slot */
- pslot = pused_head->next;
- plast = pused_head;
-
- /* search an available piece slot */
- while (pslot != NULL && pslot->paddr != addr) {
- plast = pslot;
- pslot = pslot->next;
- }
-
- if (!pslot)
- return -1;
-
- plast->next = pslot->next;
- pavail = pslot;
- pavail->pid = 0;
-
- /* insert free pieces back to the free list */
- pslot = pfree_head->next;
- plast = pfree_head;
-
- while (pslot != NULL && addr > pslot->paddr) {
- plast = pslot;
- pslot = pslot->next;
- }
-
- if (plast != pfree_head && plast->paddr + plast->size == pavail->paddr) {
- plast->size += pavail->size;
- kmem_cache_free(sram_piece_cache, pavail);
- } else {
- pavail->next = plast->next;
- plast->next = pavail;
- plast = pavail;
- }
-
- if (pslot && plast->paddr + plast->size == pslot->paddr) {
- plast->size += pslot->size;
- plast->next = pslot->next;
- kmem_cache_free(sram_piece_cache, pslot);
- }
-
- return 0;
-}
-
-int sram_free(const void *addr)
-{
-
-#if L1_CODE_LENGTH != 0
- if (addr >= (void *)get_l1_code_start()
- && addr < (void *)(get_l1_code_start() + L1_CODE_LENGTH))
- return l1_inst_sram_free(addr);
- else
-#endif
-#if L1_DATA_A_LENGTH != 0
- if (addr >= (void *)get_l1_data_a_start()
- && addr < (void *)(get_l1_data_a_start() + L1_DATA_A_LENGTH))
- return l1_data_A_sram_free(addr);
- else
-#endif
-#if L1_DATA_B_LENGTH != 0
- if (addr >= (void *)get_l1_data_b_start()
- && addr < (void *)(get_l1_data_b_start() + L1_DATA_B_LENGTH))
- return l1_data_B_sram_free(addr);
- else
-#endif
-#if L2_LENGTH != 0
- if (addr >= (void *)L2_START
- && addr < (void *)(L2_START + L2_LENGTH))
- return l2_sram_free(addr);
- else
-#endif
- return -1;
-}
-EXPORT_SYMBOL(sram_free);
-
-void *l1_data_A_sram_alloc(size_t size)
-{
-#if L1_DATA_A_LENGTH != 0
- unsigned long flags;
- void *addr;
- unsigned int cpu;
-
- cpu = smp_processor_id();
- /* add mutex operation */
- spin_lock_irqsave(&per_cpu(l1_data_sram_lock, cpu), flags);
-
- addr = _sram_alloc(size, &per_cpu(free_l1_data_A_sram_head, cpu),
- &per_cpu(used_l1_data_A_sram_head, cpu));
-
- /* add mutex operation */
- spin_unlock_irqrestore(&per_cpu(l1_data_sram_lock, cpu), flags);
-
- pr_debug("Allocated address in l1_data_A_sram_alloc is 0x%lx+0x%lx\n",
- (long unsigned int)addr, size);
-
- return addr;
-#else
- return NULL;
-#endif
-}
-EXPORT_SYMBOL(l1_data_A_sram_alloc);
-
-int l1_data_A_sram_free(const void *addr)
-{
-#if L1_DATA_A_LENGTH != 0
- unsigned long flags;
- int ret;
- unsigned int cpu;
-
- cpu = smp_processor_id();
- /* add mutex operation */
- spin_lock_irqsave(&per_cpu(l1_data_sram_lock, cpu), flags);
-
- ret = _sram_free(addr, &per_cpu(free_l1_data_A_sram_head, cpu),
- &per_cpu(used_l1_data_A_sram_head, cpu));
-
- /* add mutex operation */
- spin_unlock_irqrestore(&per_cpu(l1_data_sram_lock, cpu), flags);
-
- return ret;
-#else
- return -1;
-#endif
-}
-EXPORT_SYMBOL(l1_data_A_sram_free);
-
-void *l1_data_B_sram_alloc(size_t size)
-{
-#if L1_DATA_B_LENGTH != 0
- unsigned long flags;
- void *addr;
- unsigned int cpu;
-
- cpu = smp_processor_id();
- /* add mutex operation */
- spin_lock_irqsave(&per_cpu(l1_data_sram_lock, cpu), flags);
-
- addr = _sram_alloc(size, &per_cpu(free_l1_data_B_sram_head, cpu),
- &per_cpu(used_l1_data_B_sram_head, cpu));
-
- /* add mutex operation */
- spin_unlock_irqrestore(&per_cpu(l1_data_sram_lock, cpu), flags);
-
- pr_debug("Allocated address in l1_data_B_sram_alloc is 0x%lx+0x%lx\n",
- (long unsigned int)addr, size);
-
- return addr;
-#else
- return NULL;
-#endif
-}
-EXPORT_SYMBOL(l1_data_B_sram_alloc);
-
-int l1_data_B_sram_free(const void *addr)
-{
-#if L1_DATA_B_LENGTH != 0
- unsigned long flags;
- int ret;
- unsigned int cpu;
-
- cpu = smp_processor_id();
- /* add mutex operation */
- spin_lock_irqsave(&per_cpu(l1_data_sram_lock, cpu), flags);
-
- ret = _sram_free(addr, &per_cpu(free_l1_data_B_sram_head, cpu),
- &per_cpu(used_l1_data_B_sram_head, cpu));
-
- /* add mutex operation */
- spin_unlock_irqrestore(&per_cpu(l1_data_sram_lock, cpu), flags);
-
- return ret;
-#else
- return -1;
-#endif
-}
-EXPORT_SYMBOL(l1_data_B_sram_free);
-
-void *l1_data_sram_alloc(size_t size)
-{
- void *addr = l1_data_A_sram_alloc(size);
-
- if (!addr)
- addr = l1_data_B_sram_alloc(size);
-
- return addr;
-}
-EXPORT_SYMBOL(l1_data_sram_alloc);
-
-void *l1_data_sram_zalloc(size_t size)
-{
- void *addr = l1_data_sram_alloc(size);
-
- if (addr)
- memset(addr, 0x00, size);
-
- return addr;
-}
-EXPORT_SYMBOL(l1_data_sram_zalloc);
-
-int l1_data_sram_free(const void *addr)
-{
- int ret;
- ret = l1_data_A_sram_free(addr);
- if (ret == -1)
- ret = l1_data_B_sram_free(addr);
- return ret;
-}
-EXPORT_SYMBOL(l1_data_sram_free);
-
-void *l1_inst_sram_alloc(size_t size)
-{
-#if L1_CODE_LENGTH != 0
- unsigned long flags;
- void *addr;
- unsigned int cpu;
-
- cpu = smp_processor_id();
- /* add mutex operation */
- spin_lock_irqsave(&per_cpu(l1_inst_sram_lock, cpu), flags);
-
- addr = _sram_alloc(size, &per_cpu(free_l1_inst_sram_head, cpu),
- &per_cpu(used_l1_inst_sram_head, cpu));
-
- /* add mutex operation */
- spin_unlock_irqrestore(&per_cpu(l1_inst_sram_lock, cpu), flags);
-
- pr_debug("Allocated address in l1_inst_sram_alloc is 0x%lx+0x%lx\n",
- (long unsigned int)addr, size);
-
- return addr;
-#else
- return NULL;
-#endif
-}
-EXPORT_SYMBOL(l1_inst_sram_alloc);
-
-int l1_inst_sram_free(const void *addr)
-{
-#if L1_CODE_LENGTH != 0
- unsigned long flags;
- int ret;
- unsigned int cpu;
-
- cpu = smp_processor_id();
- /* add mutex operation */
- spin_lock_irqsave(&per_cpu(l1_inst_sram_lock, cpu), flags);
-
- ret = _sram_free(addr, &per_cpu(free_l1_inst_sram_head, cpu),
- &per_cpu(used_l1_inst_sram_head, cpu));
-
- /* add mutex operation */
- spin_unlock_irqrestore(&per_cpu(l1_inst_sram_lock, cpu), flags);
-
- return ret;
-#else
- return -1;
-#endif
-}
-EXPORT_SYMBOL(l1_inst_sram_free);
-
-/* L1 Scratchpad memory allocate function */
-void *l1sram_alloc(size_t size)
-{
- unsigned long flags;
- void *addr;
- unsigned int cpu;
-
- cpu = smp_processor_id();
- /* add mutex operation */
- spin_lock_irqsave(&per_cpu(l1sram_lock, cpu), flags);
-
- addr = _sram_alloc(size, &per_cpu(free_l1_ssram_head, cpu),
- &per_cpu(used_l1_ssram_head, cpu));
-
- /* add mutex operation */
- spin_unlock_irqrestore(&per_cpu(l1sram_lock, cpu), flags);
-
- return addr;
-}
-
-/* L1 Scratchpad memory allocate function */
-void *l1sram_alloc_max(size_t *psize)
-{
- unsigned long flags;
- void *addr;
- unsigned int cpu;
-
- cpu = smp_processor_id();
- /* add mutex operation */
- spin_lock_irqsave(&per_cpu(l1sram_lock, cpu), flags);
-
- addr = _sram_alloc_max(&per_cpu(free_l1_ssram_head, cpu),
- &per_cpu(used_l1_ssram_head, cpu), psize);
-
- /* add mutex operation */
- spin_unlock_irqrestore(&per_cpu(l1sram_lock, cpu), flags);
-
- return addr;
-}
-
-/* L1 Scratchpad memory free function */
-int l1sram_free(const void *addr)
-{
- unsigned long flags;
- int ret;
- unsigned int cpu;
-
- cpu = smp_processor_id();
- /* add mutex operation */
- spin_lock_irqsave(&per_cpu(l1sram_lock, cpu), flags);
-
- ret = _sram_free(addr, &per_cpu(free_l1_ssram_head, cpu),
- &per_cpu(used_l1_ssram_head, cpu));
-
- /* add mutex operation */
- spin_unlock_irqrestore(&per_cpu(l1sram_lock, cpu), flags);
-
- return ret;
-}
-
-void *l2_sram_alloc(size_t size)
-{
-#if L2_LENGTH != 0
- unsigned long flags;
- void *addr;
-
- /* add mutex operation */
- spin_lock_irqsave(&l2_sram_lock, flags);
-
- addr = _sram_alloc(size, &free_l2_sram_head,
- &used_l2_sram_head);
-
- /* add mutex operation */
- spin_unlock_irqrestore(&l2_sram_lock, flags);
-
- pr_debug("Allocated address in l2_sram_alloc is 0x%lx+0x%lx\n",
- (long unsigned int)addr, size);
-
- return addr;
-#else
- return NULL;
-#endif
-}
-EXPORT_SYMBOL(l2_sram_alloc);
-
-void *l2_sram_zalloc(size_t size)
-{
- void *addr = l2_sram_alloc(size);
-
- if (addr)
- memset(addr, 0x00, size);
-
- return addr;
-}
-EXPORT_SYMBOL(l2_sram_zalloc);
-
-int l2_sram_free(const void *addr)
-{
-#if L2_LENGTH != 0
- unsigned long flags;
- int ret;
-
- /* add mutex operation */
- spin_lock_irqsave(&l2_sram_lock, flags);
-
- ret = _sram_free(addr, &free_l2_sram_head,
- &used_l2_sram_head);
-
- /* add mutex operation */
- spin_unlock_irqrestore(&l2_sram_lock, flags);
-
- return ret;
-#else
- return -1;
-#endif
-}
-EXPORT_SYMBOL(l2_sram_free);
-
-int sram_free_with_lsl(const void *addr)
-{
- struct sram_list_struct *lsl, **tmp;
- struct mm_struct *mm = current->mm;
- int ret = -1;
-
- for (tmp = &mm->context.sram_list; *tmp; tmp = &(*tmp)->next)
- if ((*tmp)->addr == addr) {
- lsl = *tmp;
- ret = sram_free(addr);
- *tmp = lsl->next;
- kfree(lsl);
- break;
- }
-
- return ret;
-}
-EXPORT_SYMBOL(sram_free_with_lsl);
-
-/* Allocate memory and keep in L1 SRAM List (lsl) so that the resources are
- * tracked. These are designed for userspace so that when a process exits,
- * we can safely reap their resources.
- */
-void *sram_alloc_with_lsl(size_t size, unsigned long flags)
-{
- void *addr = NULL;
- struct sram_list_struct *lsl = NULL;
- struct mm_struct *mm = current->mm;
-
- lsl = kzalloc(sizeof(struct sram_list_struct), GFP_KERNEL);
- if (!lsl)
- return NULL;
-
- if (flags & L1_INST_SRAM)
- addr = l1_inst_sram_alloc(size);
-
- if (addr == NULL && (flags & L1_DATA_A_SRAM))
- addr = l1_data_A_sram_alloc(size);
-
- if (addr == NULL && (flags & L1_DATA_B_SRAM))
- addr = l1_data_B_sram_alloc(size);
-
- if (addr == NULL && (flags & L2_SRAM))
- addr = l2_sram_alloc(size);
-
- if (addr == NULL) {
- kfree(lsl);
- return NULL;
- }
- lsl->addr = addr;
- lsl->length = size;
- lsl->next = mm->context.sram_list;
- mm->context.sram_list = lsl;
- return addr;
-}
-EXPORT_SYMBOL(sram_alloc_with_lsl);
-
-#ifdef CONFIG_PROC_FS
-/* Once we get a real allocator, we'll throw all of this away.
- * Until then, we need some sort of visibility into the L1 alloc.
- */
-/* Need to keep line of output the same. Currently, that is 44 bytes
- * (including newline).
- */
-static int _sram_proc_show(struct seq_file *m, const char *desc,
- struct sram_piece *pfree_head,
- struct sram_piece *pused_head)
-{
- struct sram_piece *pslot;
-
- if (!pfree_head || !pused_head)
- return -1;
-
- seq_printf(m, "--- SRAM %-14s Size PID State \n", desc);
-
- /* search the relevant memory slot */
- pslot = pused_head->next;
-
- while (pslot != NULL) {
- seq_printf(m, "%p-%p %10i %5i %-10s\n",
- pslot->paddr, pslot->paddr + pslot->size,
- pslot->size, pslot->pid, "ALLOCATED");
-
- pslot = pslot->next;
- }
-
- pslot = pfree_head->next;
-
- while (pslot != NULL) {
- seq_printf(m, "%p-%p %10i %5i %-10s\n",
- pslot->paddr, pslot->paddr + pslot->size,
- pslot->size, pslot->pid, "FREE");
-
- pslot = pslot->next;
- }
-
- return 0;
-}
-static int sram_proc_show(struct seq_file *m, void *v)
-{
- unsigned int cpu;
-
- for (cpu = 0; cpu < num_possible_cpus(); ++cpu) {
- if (_sram_proc_show(m, "Scratchpad",
- &per_cpu(free_l1_ssram_head, cpu), &per_cpu(used_l1_ssram_head, cpu)))
- goto not_done;
-#if L1_DATA_A_LENGTH != 0
- if (_sram_proc_show(m, "L1 Data A",
- &per_cpu(free_l1_data_A_sram_head, cpu),
- &per_cpu(used_l1_data_A_sram_head, cpu)))
- goto not_done;
-#endif
-#if L1_DATA_B_LENGTH != 0
- if (_sram_proc_show(m, "L1 Data B",
- &per_cpu(free_l1_data_B_sram_head, cpu),
- &per_cpu(used_l1_data_B_sram_head, cpu)))
- goto not_done;
-#endif
-#if L1_CODE_LENGTH != 0
- if (_sram_proc_show(m, "L1 Instruction",
- &per_cpu(free_l1_inst_sram_head, cpu),
- &per_cpu(used_l1_inst_sram_head, cpu)))
- goto not_done;
-#endif
- }
-#if L2_LENGTH != 0
- if (_sram_proc_show(m, "L2", &free_l2_sram_head, &used_l2_sram_head))
- goto not_done;
-#endif
- not_done:
- return 0;
-}
-
-static int sram_proc_open(struct inode *inode, struct file *file)
-{
- return single_open(file, sram_proc_show, NULL);
-}
-
-static const struct file_operations sram_proc_ops = {
- .open = sram_proc_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = single_release,
-};
-
-static int __init sram_proc_init(void)
-{
- struct proc_dir_entry *ptr;
-
- ptr = proc_create("sram", S_IRUGO, NULL, &sram_proc_ops);
- if (!ptr) {
- printk(KERN_WARNING "unable to create /proc/sram\n");
- return -1;
- }
- return 0;
-}
-late_initcall(sram_proc_init);
-#endif
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0
-#
-# arch/blackfin/oprofile/Makefile
-#
-
-obj-$(CONFIG_OPROFILE) += oprofile.o
-
-DRIVER_OBJS := $(addprefix ../../../drivers/oprofile/, \
- oprof.o cpu_buffer.o buffer_sync.o \
- event_buffer.o oprofile_files.o \
- oprofilefs.o oprofile_stats.o \
- timer_int.o )
-
-oprofile-y := $(DRIVER_OBJS) bfin_oprofile.o
+++ /dev/null
-/*
- * bfin_oprofile.c - Blackfin oprofile code
- *
- * Copyright 2004-2008 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/oprofile.h>
-#include <linux/init.h>
-
-int __init oprofile_arch_init(struct oprofile_operations *ops)
-{
- return -1;
-}
-
-void oprofile_arch_exit(void)
-{
-}
CPUHP_PERF_PREPARE,
CPUHP_PERF_X86_PREPARE,
CPUHP_PERF_X86_AMD_UNCORE_PREP,
- CPUHP_PERF_BFIN,
CPUHP_PERF_POWER,
CPUHP_PERF_SUPERH,
CPUHP_X86_HPET_DEAD,
Build samples of seccomp filters using various methods of
BPF filter construction.
-config SAMPLE_BLACKFIN_GPTIMERS
- tristate "Build blackfin gptimers sample code -- loadable modules only"
- depends on BLACKFIN && BFIN_GPTIMERS && m
- help
- Build samples of blackfin gptimers sample module.
-
config SAMPLE_VFIO_MDEV_MTTY
tristate "Build VFIO mtty example mediated device sample code -- loadable modules only"
depends on VFIO_MDEV_DEVICE && m
obj-$(CONFIG_SAMPLES) += kobject/ kprobes/ trace_events/ livepatch/ \
hw_breakpoint/ kfifo/ kdb/ hidraw/ rpmsg/ seccomp/ \
- configfs/ connector/ v4l/ trace_printk/ blackfin/ \
+ configfs/ connector/ v4l/ trace_printk/ \
vfio-mdev/ statx/
+++ /dev/null
-obj-$(CONFIG_SAMPLE_BLACKFIN_GPTIMERS) += gptimers-example.o
+++ /dev/null
-/*
- * Simple gptimers example
- * http://docs.blackfin.uclinux.org/doku.php?id=linux-kernel:drivers:gptimers
- *
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/interrupt.h>
-#include <linux/module.h>
-
-#include <asm/gptimers.h>
-#include <asm/portmux.h>
-
-/* ... random driver includes ... */
-
-#define DRIVER_NAME "gptimer_example"
-
-#ifdef IRQ_TIMER5
-#define SAMPLE_IRQ_TIMER IRQ_TIMER5
-#else
-#define SAMPLE_IRQ_TIMER IRQ_TIMER2
-#endif
-
-struct gptimer_data {
- uint32_t period, width;
-};
-static struct gptimer_data data;
-
-/* ... random driver state ... */
-
-static irqreturn_t gptimer_example_irq(int irq, void *dev_id)
-{
- struct gptimer_data *data = dev_id;
-
- /* make sure it was our timer which caused the interrupt */
- if (!get_gptimer_intr(TIMER5_id))
- return IRQ_NONE;
-
- /* read the width/period values that were captured for the waveform */
- data->width = get_gptimer_pwidth(TIMER5_id);
- data->period = get_gptimer_period(TIMER5_id);
-
- /* acknowledge the interrupt */
- clear_gptimer_intr(TIMER5_id);
-
- /* tell the upper layers we took care of things */
- return IRQ_HANDLED;
-}
-
-/* ... random driver code ... */
-
-static int __init gptimer_example_init(void)
-{
- int ret;
-
- /* grab the peripheral pins */
- ret = peripheral_request(P_TMR5, DRIVER_NAME);
- if (ret) {
- printk(KERN_NOTICE DRIVER_NAME ": peripheral request failed\n");
- return ret;
- }
-
- /* grab the IRQ for the timer */
- ret = request_irq(SAMPLE_IRQ_TIMER, gptimer_example_irq,
- IRQF_SHARED, DRIVER_NAME, &data);
- if (ret) {
- printk(KERN_NOTICE DRIVER_NAME ": IRQ request failed\n");
- peripheral_free(P_TMR5);
- return ret;
- }
-
- /* setup the timer and enable it */
- set_gptimer_config(TIMER5_id,
- WDTH_CAP | PULSE_HI | PERIOD_CNT | IRQ_ENA);
- enable_gptimers(TIMER5bit);
-
- return 0;
-}
-module_init(gptimer_example_init);
-
-static void __exit gptimer_example_exit(void)
-{
- disable_gptimers(TIMER5bit);
- free_irq(SAMPLE_IRQ_TIMER, &data);
- peripheral_free(P_TMR5);
-}
-module_exit(gptimer_example_exit);
-
-MODULE_LICENSE("BSD");
"adding a line without newline at end of file\n" . $herecurr);
}
-# Blackfin: use hi/lo macros
- if ($realfile =~ m@arch/blackfin/.*\.S$@) {
- if ($line =~ /\.[lL][[:space:]]*=.*&[[:space:]]*0x[fF][fF][fF][fF]/) {
- my $herevet = "$here\n" . cat_vet($line) . "\n";
- ERROR("LO_MACRO",
- "use the LO() macro, not (... & 0xFFFF)\n" . $herevet);
- }
- if ($line =~ /\.[hH][[:space:]]*=.*>>[[:space:]]*16/) {
- my $herevet = "$here\n" . cat_vet($line) . "\n";
- ERROR("HI_MACRO",
- "use the HI() macro, not (... >> 16)\n" . $herevet);
- }
- }
-
# check we are in a valid source file C or perl if not then ignore this hunk
next if ($realfile !~ /\.(h|c|pl|dtsi|dts)$/);
"CVS style keyword markers, these will _not_ be updated\n". $herecurr);
}
-# Blackfin: don't use __builtin_bfin_[cs]sync
- if ($line =~ /__builtin_bfin_csync/) {
- my $herevet = "$here\n" . cat_vet($line) . "\n";
- ERROR("CSYNC",
- "use the CSYNC() macro in asm/blackfin.h\n" . $herevet);
- }
- if ($line =~ /__builtin_bfin_ssync/) {
- my $herevet = "$here\n" . cat_vet($line) . "\n";
- ERROR("SSYNC",
- "use the SSYNC() macro in asm/blackfin.h\n" . $herevet);
- }
-
# check for old HOTPLUG __dev<foo> section markings
if ($line =~ /\b(__dev(init|exit)(data|const|))\b/) {
WARN("HOTPLUG_SECTION",
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