arm64: dts: qcom: qcs404: Add WCN3990 WLAN module device node

Add device node for the ath10k SNOC platform driver probe
and add resources required for WCN3990 on qcs404 soc.
Optional clock and regulator controls are not yet available in
upstream, hence add them once available.

Reviewed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Govind Singh <govinds@codeaurora.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>

diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
index 2c2c9b00c02208429578441f9b602b60304d2956..ba41523188547a0860bbf56985e575320e64a2ce 100644 (file)
--- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
@@ -187,3 +187,7 @@ rclk {
                };
        };
 };
+
+&wifi {
+       status = "okay";
+};

diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
index 9b5c16562bbe4a170ac0aa3149219217f0ac4cfd..f3d77e7ee0d231ff9a7bd3e63740972f19c9038d 100644 (file)
--- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
@@ -346,6 +346,26 @@ blsp1_uart2: serial@78b1000 {
                        status = "okay";
                };
 
+               wifi: wifi@a000000 {
+                       compatible = "qcom,wcn3990-wifi";
+                       reg = <0xa000000 0x800000>;
+                       reg-names = "membase";
+                       memory-region = <&wlan_msa_mem>;
+                       interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
+                       status = "disabled";
+               };
+
                intc: interrupt-controller@b000000 {
                        compatible = "qcom,msm-qgic2";
                        interrupt-controller;