arm: dts: qcom: Add TCSR support for IPQ8064

This patch adds TCSR support for use by the GSBI to automatically
configure ADM CRCI values based on the GSBI port configuration.

Signed-off-by: Andy Gross <agross@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Olof Johansson <olof@lixom.net>

diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index cb225dafe97cd83c9ae4cc19482ed55d4a71b8b3..4e01f71c56d8bce535695eb5a1842ebe5153e1e3 100644 (file)
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -120,6 +120,7 @@ saw1: regulator@2099000 {
 
                gsbi2: gsbi@12480000 {
                        compatible = "qcom,gsbi-v1.0.0";
+                       cell-index = <2>;
                        reg = <0x12480000 0x100>;
                        clocks = <&gcc GSBI2_H_CLK>;
                        clock-names = "iface";
@@ -128,6 +129,8 @@ gsbi2: gsbi@12480000 {
                        ranges;
                        status = "disabled";
 
+                       syscon-tcsr = <&tcsr>;
+
                        serial@12490000 {
                                compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
                                reg = <0x12490000 0x1000>,
@@ -155,6 +158,7 @@ i2c@124a0000 {
 
                gsbi4: gsbi@16300000 {
                        compatible = "qcom,gsbi-v1.0.0";
+                       cell-index = <4>;
                        reg = <0x16300000 0x100>;
                        clocks = <&gcc GSBI4_H_CLK>;
                        clock-names = "iface";
@@ -163,6 +167,8 @@ gsbi4: gsbi@16300000 {
                        ranges;
                        status = "disabled";
 
+                       syscon-tcsr = <&tcsr>;
+
                        serial@16340000 {
                                compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
                                reg = <0x16340000 0x1000>,
@@ -189,6 +195,7 @@ i2c@16380000 {
 
                gsbi5: gsbi@1a200000 {
                        compatible = "qcom,gsbi-v1.0.0";
+                       cell-index = <5>;
                        reg = <0x1a200000 0x100>;
                        clocks = <&gcc GSBI5_H_CLK>;
                        clock-names = "iface";
@@ -197,6 +204,8 @@ gsbi5: gsbi@1a200000 {
                        ranges;
                        status = "disabled";
 
+                       syscon-tcsr = <&tcsr>;
+
                        serial@1a240000 {
                                compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
                                reg = <0x1a240000 0x1000>,
@@ -279,5 +288,10 @@ gcc: clock-controller@900000 {
                        #clock-cells = <1>;
                        #reset-cells = <1>;
                };
+
+               tcsr: syscon@1a400000 {
+                       compatible = "qcom,tcsr-ipq8064", "syscon";
+                       reg = <0x1a400000 0x100>;
+               };
        };
 };