cxgb4: collect HMA memory dump

Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Signed-off-by: Ganesh Goudar <ganeshgr@chelsio.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/chelsio/cxgb4/cudbg_entity.h b/drivers/net/ethernet/chelsio/cxgb4/cudbg_entity.h
index 57417f76d4a8d1449790ae7b1c3d251f20ebdcef..880b1cb5b463a6c6f4c3f3307212170222c953e8 100644 (file)
--- a/drivers/net/ethernet/chelsio/cxgb4/cudbg_entity.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/cudbg_entity.h
@@ -23,6 +23,7 @@
 #define MC_FLAG 2
 #define MC0_FLAG 3
 #define MC1_FLAG 4
+#define HMA_FLAG 5
 
 #define CUDBG_ENTITY_SIGNATURE 0xCCEDB001
 

diff --git a/drivers/net/ethernet/chelsio/cxgb4/cudbg_if.h b/drivers/net/ethernet/chelsio/cxgb4/cudbg_if.h
index 200ff82a213c8a7d059d7a623091375626f47a4d..69e2c1578b64f8cac195e113133344765ca26cc8 100644 (file)
--- a/drivers/net/ethernet/chelsio/cxgb4/cudbg_if.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/cudbg_if.h
@@ -77,6 +77,7 @@ enum cudbg_dbg_entity_type {
        CUDBG_PBT_TABLE = 65,
        CUDBG_MBOX_LOG = 66,
        CUDBG_HMA_INDIRECT = 67,
+       CUDBG_HMA = 68,
        CUDBG_MAX_ENTITY = 70,
 };
 

diff --git a/drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c b/drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c
index 2fb27e9f0bceee0317651095c6135ff34efba1ea..4e87218d44762c550d47cbd078892c0ef182a726 100644 (file)
--- a/drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c
@@ -169,6 +169,17 @@ int cudbg_fill_meminfo(struct adapter *padap,
                        meminfo_buff->avail[i].idx = 2;
                        i++;
                }
+
+               if (lo & HMA_MUX_F) {
+                       hi = t4_read_reg(padap, MA_EXT_MEMORY1_BAR_A);
+                       meminfo_buff->avail[i].base =
+                               cudbg_mbytes_to_bytes(EXT_MEM1_BASE_G(hi));
+                       meminfo_buff->avail[i].limit =
+                               meminfo_buff->avail[i].base +
+                               cudbg_mbytes_to_bytes(EXT_MEM1_SIZE_G(hi));
+                       meminfo_buff->avail[i].idx = 5;
+                       i++;
+               }
        }
 
        if (!i) /* no memory available */
@@ -702,6 +713,9 @@ static int cudbg_meminfo_get_mem_index(struct adapter *padap,
        case MEM_MC1:
                flag = MC1_FLAG;
                break;
+       case MEM_HMA:
+               flag = HMA_FLAG;
+               break;
        default:
                return CUDBG_STATUS_ENTITY_NOT_FOUND;
        }
@@ -835,6 +849,14 @@ int cudbg_collect_mc1_meminfo(struct cudbg_init *pdbg_init,
                                        MEM_MC1);
 }
 
+int cudbg_collect_hma_meminfo(struct cudbg_init *pdbg_init,
+                             struct cudbg_buffer *dbg_buff,
+                             struct cudbg_error *cudbg_err)
+{
+       return cudbg_collect_mem_region(pdbg_init, dbg_buff, cudbg_err,
+                                       MEM_HMA);
+}
+
 int cudbg_collect_rss(struct cudbg_init *pdbg_init,
                      struct cudbg_buffer *dbg_buff,
                      struct cudbg_error *cudbg_err)

diff --git a/drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.h b/drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.h
index 8bd3d49e712ec636b21bf66ca939e6b20964fe4b..18742e5a4399f2f50cff5fb6249ab6b759e48a28 100644 (file)
--- a/drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.h
@@ -165,6 +165,9 @@ int cudbg_collect_mbox_log(struct cudbg_init *pdbg_init,
 int cudbg_collect_hma_indirect(struct cudbg_init *pdbg_init,
                               struct cudbg_buffer *dbg_buff,
                               struct cudbg_error *cudbg_err);
+int cudbg_collect_hma_meminfo(struct cudbg_init *pdbg_init,
+                             struct cudbg_buffer *dbg_buff,
+                             struct cudbg_error *cudbg_err);
 
 struct cudbg_entity_hdr *cudbg_get_entity_hdr(void *outbuf, int i);
 void cudbg_align_debug_buffer(struct cudbg_buffer *dbg_buff,

diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h b/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h
index 6f9fa6e3c42a0cc1988e82ae976cce17d45ca0e5..e680beed903049c77e9f3f48c22e6fc768649ebc 100644 (file)
--- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h
@@ -77,7 +77,8 @@ enum {
        MEM_EDC1,
        MEM_MC,
        MEM_MC0 = MEM_MC,
-       MEM_MC1
+       MEM_MC1,
+       MEM_HMA,
 };
 
 enum {

diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_cudbg.c b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_cudbg.c
index 389458cb69a8f5b6412883b60cbecb4d2c523b85..273316f4a20de1eb6400677f3b85723008cbd2de 100644 (file)
--- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_cudbg.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_cudbg.c
@@ -24,6 +24,7 @@ static const struct cxgb4_collect_entity cxgb4_collect_mem_dump[] = {
        { CUDBG_EDC1, cudbg_collect_edc1_meminfo },
        { CUDBG_MC0, cudbg_collect_mc0_meminfo },
        { CUDBG_MC1, cudbg_collect_mc1_meminfo },
+       { CUDBG_HMA, cudbg_collect_hma_meminfo },
 };
 
 static const struct cxgb4_collect_entity cxgb4_collect_hw_dump[] = {
@@ -285,6 +286,17 @@ static u32 cxgb4_get_entity_length(struct adapter *adap, u32 entity)
                        len = sizeof(struct ireg_buf) * n;
                }
                break;
+       case CUDBG_HMA:
+               value = t4_read_reg(adap, MA_TARGET_MEM_ENABLE_A);
+               if (value & HMA_MUX_F) {
+                       /* In T6, there's no MC1.  So, HMA shares MC1
+                        * address space.
+                        */
+                       value = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
+                       len = EXT_MEM1_SIZE_G(value);
+               }
+               len = cudbg_mbytes_to_bytes(len);
+               break;
        default:
                break;
        }

diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
index c6732683cb8c0092cc1226e9750fd664b337be95..4956e429ae1dabcbaf58132d627acfca3b814035 100644 (file)
--- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
@@ -2811,7 +2811,7 @@ static void mem_region_show(struct seq_file *seq, const char *name,
 static int meminfo_show(struct seq_file *seq, void *v)
 {
        static const char * const memory[] = { "EDC0:", "EDC1:", "MC:",
-                                              "MC0:", "MC1:"};
+                                              "MC0:", "MC1:", "HMA:"};
        struct adapter *adap = seq->private;
        struct cudbg_meminfo meminfo;
        int i, rc;

diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c b/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
index f63210f155796c9809415d7da54f59086ebdbf7c..ccb2798c34d1cc82565d32929aebb8cd454707da 100644 (file)
--- a/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
@@ -524,11 +524,14 @@ int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr,
         * MEM_EDC1 = 1
         * MEM_MC   = 2 -- MEM_MC for chips with only 1 memory controller
         * MEM_MC1  = 3 -- for chips with 2 memory controllers (e.g. T5)
+        * MEM_HMA  = 4
         */
        edc_size  = EDRAM0_SIZE_G(t4_read_reg(adap, MA_EDRAM0_BAR_A));
-       if (mtype != MEM_MC1)
+       if (mtype == MEM_HMA) {
+               memoffset = 2 * (edc_size * 1024 * 1024);
+       } else if (mtype != MEM_MC1) {
                memoffset = (mtype * (edc_size * 1024 * 1024));
-       else {
+       } else {
                mc_size = EXT_MEM0_SIZE_G(t4_read_reg(adap,
                                                      MA_EXT_MEMORY0_BAR_A));
                memoffset = (MEM_MC0 * edc_size + mc_size) * 1024 * 1024;

diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4_regs.h b/drivers/net/ethernet/chelsio/cxgb4/t4_regs.h
index a7cfece728282ca96db0aac65266b3146f32d563..f6701e0a6701a7231942b72963d264703ba60aa8 100644 (file)
--- a/drivers/net/ethernet/chelsio/cxgb4/t4_regs.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/t4_regs.h
@@ -961,6 +961,10 @@
 
 #define MA_EXT_MEMORY1_BAR_A 0x7808
 
+#define HMA_MUX_S    5
+#define HMA_MUX_V(x) ((x) << HMA_MUX_S)
+#define HMA_MUX_F    HMA_MUX_V(1U)
+
 #define EXT_MEM1_BASE_S    16
 #define EXT_MEM1_BASE_M    0xfffU
 #define EXT_MEM1_BASE_G(x) (((x) >> EXT_MEM1_BASE_S) & EXT_MEM1_BASE_M)