drm/msm: drop quirks binding

This was never documented or used in upstream dtb.  It is used by
downstream bindings from android device kernels.  But the quirks are
a property of the gpu revision, and as such are redundant to be listed
separately in dt.  Instead, move the quirks to the device table.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
index b8647198c11c66ef0a4c9f8a6bafae9be6b006c6..8308bb8166c8f61574142466928edfee0525359e 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
@@ -327,7 +327,7 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
        /* Enable RBBM error reporting bits */
        gpu_write(gpu, REG_A5XX_RBBM_AHB_CNTL0, 0x00000001);
 
-       if (adreno_gpu->quirks & ADRENO_QUIRK_FAULT_DETECT_MASK) {
+       if (adreno_gpu->info->quirks & ADRENO_QUIRK_FAULT_DETECT_MASK) {
                /*
                 * Mask out the activity signals from RB1-3 to avoid false
                 * positives
@@ -381,7 +381,7 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
 
        gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL, (0x400 << 11 | 0x300 << 22));
 
-       if (adreno_gpu->quirks & ADRENO_QUIRK_TWO_PASS_USE_WFI)
+       if (adreno_gpu->info->quirks & ADRENO_QUIRK_TWO_PASS_USE_WFI)
                gpu_rmw(gpu, REG_A5XX_PC_DBG_ECO_CNTL, 0, (1 << 8));
 
        gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL, 0xc0200100);

diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
index 5fa51a9abc20c7b960ab55df1066d3d1da8d53f0..ece39b16a8641f40050ff27a81124926580a9f57 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/adreno_device.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
@@ -75,12 +75,14 @@ static const struct adreno_info gpulist[] = {
                .gmem  = (SZ_1M + SZ_512K),
                .init  = a4xx_gpu_init,
        }, {
-               .rev = ADRENO_REV(5, 3, 0, ANY_ID),
+               .rev = ADRENO_REV(5, 3, 0, 2),
                .revn = 530,
                .name = "A530",
                .pm4fw = "a530_pm4.fw",
                .pfpfw = "a530_pfp.fw",
                .gmem = SZ_1M,
+               .quirks = ADRENO_QUIRK_TWO_PASS_USE_WFI |
+                       ADRENO_QUIRK_FAULT_DETECT_MASK,
                .init = a5xx_gpu_init,
                .gpmufw = "a530v3_gpmu.fw2",
        },
@@ -181,14 +183,6 @@ static void set_gpu_pdev(struct drm_device *dev,
        priv->gpu_pdev = pdev;
 }
 
-static const struct {
-       const char *str;
-       uint32_t flag;
-} quirks[] = {
-       { "qcom,gpu-quirk-two-pass-use-wfi", ADRENO_QUIRK_TWO_PASS_USE_WFI },
-       { "qcom,gpu-quirk-fault-detect-mask", ADRENO_QUIRK_FAULT_DETECT_MASK },
-};
-
 static int find_chipid(struct device *dev, u32 *chipid)
 {
        struct device_node *node = dev->of_node;
@@ -231,7 +225,7 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)
        static struct adreno_platform_config config = {};
        struct device_node *child, *node = dev->of_node;
        u32 val;
-       int ret, i;
+       int ret;
 
        ret = find_chipid(dev, &val);
        if (ret) {
@@ -267,10 +261,6 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)
                config.slow_rate = 27000000;
        }
 
-       for (i = 0; i < ARRAY_SIZE(quirks); i++)
-               if (of_property_read_bool(node, quirks[i].str))
-                       config.quirks |= quirks[i].flag;
-
        dev->platform_data = &config;
        set_gpu_pdev(dev_get_drvdata(master), to_platform_device(dev));
        return 0;

diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index 686a580c711a99bfe61b5867e5adc75891e5e0a0..c9bd1e6225f4f96e3b8a79a101508f244de17baf 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -352,7 +352,6 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
        adreno_gpu->gmem = adreno_gpu->info->gmem;
        adreno_gpu->revn = adreno_gpu->info->revn;
        adreno_gpu->rev = config->rev;
-       adreno_gpu->quirks = config->quirks;
 
        gpu->fast_rate = config->fast_rate;
        gpu->slow_rate = config->slow_rate;

diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index e8d55b0306ed8c36156e2b03d6fca9ef94ce4104..42e444a67630c5285b5b010c3a1b71689258af19 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -75,6 +75,7 @@ struct adreno_info {
        const char *pm4fw, *pfpfw;
        const char *gpmufw;
        uint32_t gmem;
+       enum adreno_quirks quirks;
        struct msm_gpu *(*init)(struct drm_device *dev);
 };
 
@@ -116,8 +117,6 @@ struct adreno_gpu {
         * code (a3xx_gpu.c) and stored in this common location.
         */
        const unsigned int *reg_offsets;
-
-       uint32_t quirks;
 };
 #define to_adreno_gpu(x) container_of(x, struct adreno_gpu, base)
 
@@ -128,7 +127,6 @@ struct adreno_platform_config {
 #ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING
        struct msm_bus_scale_pdata *bus_scale_table;
 #endif
-       uint32_t quirks;
 };
 
 #define ADRENO_IDLE_TIMEOUT msecs_to_jiffies(1000)