ARM: dts: dra7: Add properties to enable PCIe x2 lane mode

ti,syscon-lane-sel and ti,syscon-lane-conf properties specific to enable
PCIe x2 lane mode are added here.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index d8eb1632bbdfc1f2c6bf09188ee40cb0c28630f7..24c104d1360a80bc1cb48a8201b801ef33f39da2 100644 (file)
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -309,6 +309,8 @@ pcie1_rc: pcie@51000000 {
                                ti,hwmods = "pcie1";
                                phys = <&pcie1_phy>;
                                phy-names = "pcie-phy0";
+                               ti,syscon-lane-conf = <&scm_conf 0x558>;
+                               ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
                                interrupt-map-mask = <0 0 0 7>;
                                interrupt-map = <0 0 0 1 &pcie1_intc 1>,
                                                <0 0 0 2 &pcie1_intc 2>,
@@ -334,6 +336,8 @@ pcie1_ep: pcie_ep@51000000 {
                                phys = <&pcie1_phy>;
                                phy-names = "pcie-phy0";
                                ti,syscon-unaligned-access = <&scm_conf1 0x14 2>;
+                               ti,syscon-lane-conf = <&scm_conf 0x558>;
+                               ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
                                status = "disabled";
                        };
                };