i40e/i40evf: Don't bother setting the CLEARPBA bit

The CLEARPBA bit in the dynamic interrupt control register actually has
no effect either way on the hardware. As per errata 28 in the XL710
specification update the interrupt is actually cleared any time the
register is written with the INTENA_MSK bit set to 0. As such the act of
toggling the enable bit actually will trigger the interrupt being
cleared and could lead to potential lost events if auto-masking is
not enabled.

Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com>
Tested-by: Andrew Bowers <andrewx.bowers@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>

diff --git a/drivers/net/ethernet/intel/i40e/i40e_txrx.c b/drivers/net/ethernet/intel/i40e/i40e_txrx.c
index 6b3fe5d26dc1e7ae557a8f949973505bed746a11..ac1fa9e3c04ff4aeebd4561e7b897a41a3388169 100644 (file)
--- a/drivers/net/ethernet/intel/i40e/i40e_txrx.c
+++ b/drivers/net/ethernet/intel/i40e/i40e_txrx.c
@@ -2281,8 +2281,17 @@ static u32 i40e_buildreg_itr(const int type, const u16 itr)
 {
        u32 val;
 
+       /* We don't bother with setting the CLEARPBA bit as the data sheet
+        * points out doing so is "meaningless since it was already
+        * auto-cleared". The auto-clearing happens when the interrupt is
+        * asserted.
+        *
+        * Hardware errata 28 for also indicates that writing to a
+        * xxINT_DYN_CTLx CSR with INTENA_MSK (bit 31) set to 0 will clear
+        * an event in the PBA anyway so we need to rely on the automask
+        * to hold pending events for us until the interrupt is re-enabled
+        */
        val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
-             I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
              (type << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
              (itr << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT);
 

diff --git a/drivers/net/ethernet/intel/i40evf/i40e_txrx.c b/drivers/net/ethernet/intel/i40evf/i40e_txrx.c
index 3fd7e9731f49913d05dae486754fe5683a3f738f..34d898f0adaae3d4f7d9f18a4d5641fb3108baba 100644 (file)
--- a/drivers/net/ethernet/intel/i40evf/i40e_txrx.c
+++ b/drivers/net/ethernet/intel/i40evf/i40e_txrx.c
@@ -1464,8 +1464,17 @@ static u32 i40e_buildreg_itr(const int type, const u16 itr)
 {
        u32 val;
 
+       /* We don't bother with setting the CLEARPBA bit as the data sheet
+        * points out doing so is "meaningless since it was already
+        * auto-cleared". The auto-clearing happens when the interrupt is
+        * asserted.
+        *
+        * Hardware errata 28 for also indicates that writing to a
+        * xxINT_DYN_CTLx CSR with INTENA_MSK (bit 31) set to 0 will clear
+        * an event in the PBA anyway so we need to rely on the automask
+        * to hold pending events for us until the interrupt is re-enabled
+        */
        val = I40E_VFINT_DYN_CTLN1_INTENA_MASK |
-             I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
              (type << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
              (itr << I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT);