powerpc/mm: Write to PTCR only if ultravisor disabled

In ultravisor enabled systems, PTCR becomes ultravisor privileged only
for writing and an attempt to write to it will cause a Hypervisor
Emulation Assitance interrupt.

This patch uses the set_ptcr_when_no_uv() function to restrict PTCR
writing to only when ultravisor is disabled.

Signed-off-by: Claudio Carvalho <cclaudio@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20190822034838.27876-6-cclaudio@linux.ibm.com

diff --git a/arch/powerpc/include/asm/ultravisor.h b/arch/powerpc/include/asm/ultravisor.h
index 6fe1f365dec8dbb5eab674e22d359a654e041a87..d7aa97aa7834918b891ade99f2e8a34af013d434 100644 (file)
--- a/arch/powerpc/include/asm/ultravisor.h
+++ b/arch/powerpc/include/asm/ultravisor.h
@@ -10,10 +10,22 @@
 
 #include <asm/asm-prototypes.h>
 #include <asm/ultravisor-api.h>
+#include <asm/firmware.h>
 
 int early_init_dt_scan_ultravisor(unsigned long node, const char *uname,
                                  int depth, void *data);
 
+/*
+ * In ultravisor enabled systems, PTCR becomes ultravisor privileged only for
+ * writing and an attempt to write to it will cause a Hypervisor Emulation
+ * Assistance interrupt.
+ */
+static inline void set_ptcr_when_no_uv(u64 val)
+{
+       if (!firmware_has_feature(FW_FEATURE_ULTRAVISOR))
+               mtspr(SPRN_PTCR, val);
+}
+
 static inline int uv_register_pate(u64 lpid, u64 dw0, u64 dw1)
 {
        return ucall_norets(UV_WRITE_PATE, lpid, dw0, dw1);

diff --git a/arch/powerpc/mm/book3s64/hash_utils.c b/arch/powerpc/mm/book3s64/hash_utils.c
index b8ad14bb11704edb30a71892d871c7e98dd50a4d..88aab920caca50e3bf14518e263f23f174365b25 100644 (file)
--- a/arch/powerpc/mm/book3s64/hash_utils.c
+++ b/arch/powerpc/mm/book3s64/hash_utils.c
@@ -61,6 +61,7 @@
 #include <asm/ps3.h>
 #include <asm/pte-walk.h>
 #include <asm/asm-prototypes.h>
+#include <asm/ultravisor.h>
 
 #include <mm/mmu_decl.h>
 
@@ -1075,8 +1076,8 @@ void hash__early_init_mmu_secondary(void)
                if (!cpu_has_feature(CPU_FTR_ARCH_300))
                        mtspr(SPRN_SDR1, _SDR1);
                else
-                       mtspr(SPRN_PTCR,
-                             __pa(partition_tb) | (PATB_SIZE_SHIFT - 12));
+                       set_ptcr_when_no_uv(__pa(partition_tb) |
+                                           (PATB_SIZE_SHIFT - 12));
        }
        /* Initialize SLB */
        slb_initialize();

diff --git a/arch/powerpc/mm/book3s64/pgtable.c b/arch/powerpc/mm/book3s64/pgtable.c
index 4173f6931009f7cf60d2fab86c11c89780aa91a5..01a7570c10e0f6ee7960c9b536493d4d09ba21d2 100644 (file)
--- a/arch/powerpc/mm/book3s64/pgtable.c
+++ b/arch/powerpc/mm/book3s64/pgtable.c
@@ -207,7 +207,7 @@ void __init mmu_partition_table_init(void)
         * 64 K size.
         */
        ptcr = __pa(partition_tb) | (PATB_SIZE_SHIFT - 12);
-       mtspr(SPRN_PTCR, ptcr);
+       set_ptcr_when_no_uv(ptcr);
        powernv_set_nmmu_ptcr(ptcr);
 }
 

diff --git a/arch/powerpc/mm/book3s64/radix_pgtable.c b/arch/powerpc/mm/book3s64/radix_pgtable.c
index b4ca9e95e678110e7f0f07fd9a9d6688a1658d5a..5bc118b4a63494c23a9771849f7fa39798029723 100644 (file)
--- a/arch/powerpc/mm/book3s64/radix_pgtable.c
+++ b/arch/powerpc/mm/book3s64/radix_pgtable.c
@@ -27,6 +27,7 @@
 #include <asm/sections.h>
 #include <asm/trace.h>
 #include <asm/uaccess.h>
+#include <asm/ultravisor.h>
 
 #include <trace/events/thp.h>
 
@@ -650,8 +651,9 @@ void radix__early_init_mmu_secondary(void)
                lpcr = mfspr(SPRN_LPCR);
                mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR);
 
-               mtspr(SPRN_PTCR,
-                     __pa(partition_tb) | (PATB_SIZE_SHIFT - 12));
+               set_ptcr_when_no_uv(__pa(partition_tb) |
+                                   (PATB_SIZE_SHIFT - 12));
+
                radix_init_amor();
        }
 
@@ -667,7 +669,7 @@ void radix__mmu_cleanup_all(void)
        if (!firmware_has_feature(FW_FEATURE_LPAR)) {
                lpcr = mfspr(SPRN_LPCR);
                mtspr(SPRN_LPCR, lpcr & ~LPCR_UPRT);
-               mtspr(SPRN_PTCR, 0);
+               set_ptcr_when_no_uv(0);
                powernv_set_nmmu_ptcr(0);
                radix__flush_tlb_all();
        }