]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
Merge branch 'bna-cleanups'
authorDavid S. Miller <davem@davemloft.net>
Sun, 21 Jun 2015 17:29:07 +0000 (10:29 -0700)
committerDavid S. Miller <davem@davemloft.net>
Sun, 21 Jun 2015 17:29:07 +0000 (10:29 -0700)
Ivan Vecera says:

====================
bna: clean-up 2

Next round of cleaning patches.
====================

Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/brocade/bna/bfa_defs_mfg_comm.h
drivers/net/ethernet/brocade/bna/bfa_ioc.c
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
drivers/net/ethernet/brocade/bna/bna.h
drivers/net/ethernet/brocade/bna/bna_enet.c
drivers/net/ethernet/brocade/bna/bna_tx_rx.c
drivers/net/ethernet/brocade/bna/bnad.c
drivers/net/ethernet/brocade/bna/bnad.h
drivers/net/ethernet/brocade/bna/bnad_debugfs.c

index 16090fdf1dd5498715513a65f0f61f7f91ea7e7c..7e17451c94d1147dbeba80bf922d0c3e49f53df9 100644 (file)
@@ -84,7 +84,7 @@ do {                                                          \
                (prop) |= BFI_ADAPTER_PROTO;                    \
                (gpio) &= ~CB_GPIO_PROTO;                       \
        }                                                       \
-       switch ((gpio)) {                                       \
+       switch (gpio) {                                         \
        case CB_GPIO_TTV:                                       \
                (prop) |= BFI_ADAPTER_TTV;                      \
        case CB_GPIO_DFLY:                                      \
index b009fd7dda6aeb6ccb3a114436dfcf1092b4a94b..b7a0f7879de2d3ee4d2b419a3b26c5e7661224c6 100644 (file)
@@ -1304,7 +1304,7 @@ bfa_nw_ioc_fwver_get(struct bfa_ioc *ioc, struct bfi_ioc_image_hdr *fwhdr)
        for (i = 0; i < (sizeof(struct bfi_ioc_image_hdr) / sizeof(u32));
             i++) {
                fwsig[i] =
-                       swab32(readl((loff) + (ioc->ioc_regs.smem_page_start)));
+                       swab32(readl(loff + ioc->ioc_regs.smem_page_start));
                loff += sizeof(u32);
        }
 }
@@ -1675,7 +1675,7 @@ bfa_raw_sem_get(void __iomem *bar)
 {
        int     locked;
 
-       locked = readl((bar + FLASH_SEM_LOCK_REG));
+       locked = readl(bar + FLASH_SEM_LOCK_REG);
 
        return !locked;
 }
@@ -2049,8 +2049,8 @@ bfa_ioc_download_fw(struct bfa_ioc *ioc, u32 boot_type,
                /**
                 * write smem
                 */
-               writel((swab32(fwimg[BFA_IOC_FLASH_OFFSET_IN_CHUNK(i)])),
-                             ((ioc->ioc_regs.smem_page_start) + (loff)));
+               writel(swab32(fwimg[BFA_IOC_FLASH_OFFSET_IN_CHUNK(i)]),
+                      ioc->ioc_regs.smem_page_start + loff);
 
                loff += sizeof(u32);
 
@@ -2213,7 +2213,7 @@ bfa_nw_ioc_smem_read(struct bfa_ioc *ioc, void *tbuf, u32 soff, u32 sz)
 
        len = sz/sizeof(u32);
        for (i = 0; i < len; i++) {
-               r32 = swab32(readl((loff) + (ioc->ioc_regs.smem_page_start)));
+               r32 = swab32(readl(loff + ioc->ioc_regs.smem_page_start));
                buf[i] = be32_to_cpu(r32);
                loff += sizeof(u32);
 
index 4247d8a44573cfa8c3beb4c1bb220052eba9b02f..74e5ed55ac01839f99b5d1cf9374a175a4a87b0b 100644 (file)
@@ -23,8 +23,7 @@
 #include "bfi_reg.h"
 #include "bfa_defs.h"
 
-#define bfa_ioc_ct_sync_pos(__ioc)     \
-               ((u32)BIT(bfa_ioc_pcifn(__ioc)))
+#define bfa_ioc_ct_sync_pos(__ioc)     BIT(bfa_ioc_pcifn(__ioc))
 #define BFA_IOC_SYNC_REQD_SH           16
 #define bfa_ioc_ct_get_sync_ackd(__val) (__val & 0x0000ffff)
 #define bfa_ioc_ct_clear_sync_ackd(__val) (__val & 0xffff0000)
@@ -536,7 +535,7 @@ bfa_ioc_ct_sync_ack(struct bfa_ioc *ioc)
 {
        u32 r32 = readl(ioc->ioc_regs.ioc_fail_sync);
 
-       writel((r32 | bfa_ioc_ct_sync_pos(ioc)), ioc->ioc_regs.ioc_fail_sync);
+       writel(r32 | bfa_ioc_ct_sync_pos(ioc), ioc->ioc_regs.ioc_fail_sync);
 }
 
 static bool
@@ -667,7 +666,7 @@ bfa_ioc_ct_pll_init(void __iomem *rb, enum bfi_asic_mode asic_mode)
                writel(__PMM_1T_RESET_P, (rb + PMM_1T_RESET_REG_P0));
                writel(__PMM_1T_RESET_P, (rb + PMM_1T_RESET_REG_P1));
        }
-       r32 = readl((rb + PSS_CTL_REG));
+       r32 = readl(rb + PSS_CTL_REG);
        r32 &= ~__PSS_LMEM_RESET;
        writel(r32, (rb + PSS_CTL_REG));
        udelay(1000);
@@ -678,7 +677,7 @@ bfa_ioc_ct_pll_init(void __iomem *rb, enum bfi_asic_mode asic_mode)
 
        writel(__EDRAM_BISTR_START, (rb + MBIST_CTL_REG));
        udelay(1000);
-       r32 = readl((rb + MBIST_STAT_REG));
+       r32 = readl(rb + MBIST_STAT_REG);
        writel(0, (rb + MBIST_CTL_REG));
        return BFA_STATUS_OK;
 }
@@ -691,7 +690,7 @@ bfa_ioc_ct2_sclk_init(void __iomem *rb)
        /*
         * put s_clk PLL and PLL FSM in reset
         */
-       r32 = readl((rb + CT2_APP_PLL_SCLK_CTL_REG));
+       r32 = readl(rb + CT2_APP_PLL_SCLK_CTL_REG);
        r32 &= ~(__APP_PLL_SCLK_ENABLE | __APP_PLL_SCLK_LRESETN);
        r32 |= (__APP_PLL_SCLK_ENARST | __APP_PLL_SCLK_BYPASS |
                __APP_PLL_SCLK_LOGIC_SOFT_RESET);
@@ -701,28 +700,28 @@ bfa_ioc_ct2_sclk_init(void __iomem *rb)
         * Ignore mode and program for the max clock (which is FC16)
         * Firmware/NFC will do the PLL init appropriately
         */
-       r32 = readl((rb + CT2_APP_PLL_SCLK_CTL_REG));
+       r32 = readl(rb + CT2_APP_PLL_SCLK_CTL_REG);
        r32 &= ~(__APP_PLL_SCLK_REFCLK_SEL | __APP_PLL_SCLK_CLK_DIV2);
        writel(r32, (rb + CT2_APP_PLL_SCLK_CTL_REG));
 
        /*
         * while doing PLL init dont clock gate ethernet subsystem
         */
-       r32 = readl((rb + CT2_CHIP_MISC_PRG));
-       writel((r32 | __ETH_CLK_ENABLE_PORT0),
-                               (rb + CT2_CHIP_MISC_PRG));
+       r32 = readl(rb + CT2_CHIP_MISC_PRG);
+       writel(r32 | __ETH_CLK_ENABLE_PORT0,
+              rb + CT2_CHIP_MISC_PRG);
 
-       r32 = readl((rb + CT2_PCIE_MISC_REG));
-       writel((r32 | __ETH_CLK_ENABLE_PORT1),
-                               (rb + CT2_PCIE_MISC_REG));
+       r32 = readl(rb + CT2_PCIE_MISC_REG);
+       writel(r32 | __ETH_CLK_ENABLE_PORT1,
+              rb + CT2_PCIE_MISC_REG);
 
        /*
         * set sclk value
         */
-       r32 = readl((rb + CT2_APP_PLL_SCLK_CTL_REG));
+       r32 = readl(rb + CT2_APP_PLL_SCLK_CTL_REG);
        r32 &= (__P_SCLK_PLL_LOCK | __APP_PLL_SCLK_REFCLK_SEL |
                __APP_PLL_SCLK_CLK_DIV2);
-       writel(r32 | 0x1061731b, (rb + CT2_APP_PLL_SCLK_CTL_REG));
+       writel(r32 | 0x1061731b, rb + CT2_APP_PLL_SCLK_CTL_REG);
 
        /*
         * poll for s_clk lock or delay 1ms
@@ -743,28 +742,28 @@ bfa_ioc_ct2_lclk_init(void __iomem *rb)
        /*
         * put l_clk PLL and PLL FSM in reset
         */
-       r32 = readl((rb + CT2_APP_PLL_LCLK_CTL_REG));
+       r32 = readl(rb + CT2_APP_PLL_LCLK_CTL_REG);
        r32 &= ~(__APP_PLL_LCLK_ENABLE | __APP_PLL_LCLK_LRESETN);
        r32 |= (__APP_PLL_LCLK_ENARST | __APP_PLL_LCLK_BYPASS |
                __APP_PLL_LCLK_LOGIC_SOFT_RESET);
-       writel(r32, (rb + CT2_APP_PLL_LCLK_CTL_REG));
+       writel(r32, rb + CT2_APP_PLL_LCLK_CTL_REG);
 
        /*
         * set LPU speed (set for FC16 which will work for other modes)
         */
-       r32 = readl((rb + CT2_CHIP_MISC_PRG));
+       r32 = readl(rb + CT2_CHIP_MISC_PRG);
        writel(r32, (rb + CT2_CHIP_MISC_PRG));
 
        /*
         * set LPU half speed (set for FC16 which will work for other modes)
         */
-       r32 = readl((rb + CT2_APP_PLL_LCLK_CTL_REG));
-       writel(r32, (rb + CT2_APP_PLL_LCLK_CTL_REG));
+       r32 = readl(rb + CT2_APP_PLL_LCLK_CTL_REG);
+       writel(r32, rb + CT2_APP_PLL_LCLK_CTL_REG);
 
        /*
         * set lclk for mode (set for FC16)
         */
-       r32 = readl((rb + CT2_APP_PLL_LCLK_CTL_REG));
+       r32 = readl(rb + CT2_APP_PLL_LCLK_CTL_REG);
        r32 &= (__P_LCLK_PLL_LOCK | __APP_LPUCLK_HALFSPEED);
        r32 |= 0x20c1731b;
        writel(r32, (rb + CT2_APP_PLL_LCLK_CTL_REG));
@@ -780,14 +779,14 @@ bfa_ioc_ct2_mem_init(void __iomem *rb)
 {
        u32 r32;
 
-       r32 = readl((rb + PSS_CTL_REG));
+       r32 = readl(rb + PSS_CTL_REG);
        r32 &= ~__PSS_LMEM_RESET;
-       writel(r32, (rb + PSS_CTL_REG));
+       writel(r32, rb + PSS_CTL_REG);
        udelay(1000);
 
-       writel(__EDRAM_BISTR_START, (rb + CT2_MBIST_CTL_REG));
+       writel(__EDRAM_BISTR_START, rb + CT2_MBIST_CTL_REG);
        udelay(1000);
-       writel(0, (rb + CT2_MBIST_CTL_REG));
+       writel(0, rb + CT2_MBIST_CTL_REG);
 }
 
 static void
@@ -801,22 +800,22 @@ bfa_ioc_ct2_mac_reset(void __iomem *rb)
        /*
         * release soft reset on s_clk & l_clk
         */
-       r32 = readl((rb + CT2_APP_PLL_SCLK_CTL_REG));
-       writel((r32 & ~__APP_PLL_SCLK_LOGIC_SOFT_RESET),
-                       (rb + CT2_APP_PLL_SCLK_CTL_REG));
+       r32 = readl(rb + CT2_APP_PLL_SCLK_CTL_REG);
+       writel(r32 & ~__APP_PLL_SCLK_LOGIC_SOFT_RESET,
+              rb + CT2_APP_PLL_SCLK_CTL_REG);
 
        /*
         * release soft reset on s_clk & l_clk
         */
-       r32 = readl((rb + CT2_APP_PLL_LCLK_CTL_REG));
-       writel((r32 & ~__APP_PLL_LCLK_LOGIC_SOFT_RESET),
-                       (rb + CT2_APP_PLL_LCLK_CTL_REG));
+       r32 = readl(rb + CT2_APP_PLL_LCLK_CTL_REG);
+       writel(r32 & ~__APP_PLL_LCLK_LOGIC_SOFT_RESET,
+              rb + CT2_APP_PLL_LCLK_CTL_REG);
 
        /* put port0, port1 MAC & AHB in reset */
-       writel((__CSI_MAC_RESET | __CSI_MAC_AHB_RESET),
-                       (rb + CT2_CSI_MAC_CONTROL_REG(0)));
-       writel((__CSI_MAC_RESET | __CSI_MAC_AHB_RESET),
-                       (rb + CT2_CSI_MAC_CONTROL_REG(1)));
+       writel(__CSI_MAC_RESET | __CSI_MAC_AHB_RESET,
+              rb + CT2_CSI_MAC_CONTROL_REG(0));
+       writel(__CSI_MAC_RESET | __CSI_MAC_AHB_RESET,
+              rb + CT2_CSI_MAC_CONTROL_REG(1));
 }
 
 #define CT2_NFC_MAX_DELAY       1000
@@ -861,8 +860,8 @@ bfa_ioc_ct2_pll_init(void __iomem *rb, enum bfi_asic_mode asic_mode)
 
        nfc_ver = readl(rb + CT2_RSC_GPR15_REG);
 
-       if ((wgn == (__A2T_AHB_LOAD | __WGN_READY)) &&
-               (nfc_ver >= CT2_NFC_VER_VALID)) {
+       if (wgn == (__A2T_AHB_LOAD | __WGN_READY) &&
+           nfc_ver >= CT2_NFC_VER_VALID) {
                if (bfa_ioc_ct2_nfc_halted(rb))
                        bfa_ioc_ct2_nfc_resume(rb);
                writel(__RESET_AND_START_SCLK_LCLK_PLLS,
@@ -899,19 +898,19 @@ bfa_ioc_ct2_pll_init(void __iomem *rb, enum bfi_asic_mode asic_mode)
                bfa_ioc_ct2_lclk_init(rb);
 
                /* release soft reset on s_clk & l_clk */
-               r32 = readl((rb + CT2_APP_PLL_SCLK_CTL_REG));
+               r32 = readl(rb + CT2_APP_PLL_SCLK_CTL_REG);
                writel(r32 & ~__APP_PLL_SCLK_LOGIC_SOFT_RESET,
                                rb + CT2_APP_PLL_SCLK_CTL_REG);
-               r32 = readl((rb + CT2_APP_PLL_LCLK_CTL_REG));
+               r32 = readl(rb + CT2_APP_PLL_LCLK_CTL_REG);
                writel(r32 & ~__APP_PLL_LCLK_LOGIC_SOFT_RESET,
                                rb + CT2_APP_PLL_LCLK_CTL_REG);
        }
 
        /* Announce flash device presence, if flash was corrupted. */
        if (wgn == (__WGN_READY | __GLBL_PF_VF_CFG_RDY)) {
-               r32 = readl((rb + PSS_GPIO_OUT_REG));
+               r32 = readl(rb + PSS_GPIO_OUT_REG);
                writel(r32 & ~1, rb + PSS_GPIO_OUT_REG);
-               r32 = readl((rb + PSS_GPIO_OE_REG));
+               r32 = readl(rb + PSS_GPIO_OE_REG);
                writel(r32 | 1, rb + PSS_GPIO_OE_REG);
        }
 
@@ -919,27 +918,27 @@ bfa_ioc_ct2_pll_init(void __iomem *rb, enum bfi_asic_mode asic_mode)
         * Mask the interrupts and clear any
         * pending interrupts left by BIOS/EFI
         */
-       writel(1, (rb + CT2_LPU0_HOSTFN_MBOX0_MSK));
-       writel(1, (rb + CT2_LPU1_HOSTFN_MBOX0_MSK));
+       writel(1, rb + CT2_LPU0_HOSTFN_MBOX0_MSK);
+       writel(1, rb + CT2_LPU1_HOSTFN_MBOX0_MSK);
 
        /* For first time initialization, no need to clear interrupts */
        r32 = readl(rb + HOST_SEM5_REG);
        if (r32 & 0x1) {
-               r32 = readl((rb + CT2_LPU0_HOSTFN_CMD_STAT));
+               r32 = readl(rb + CT2_LPU0_HOSTFN_CMD_STAT);
                if (r32 == 1) {
-                       writel(1, (rb + CT2_LPU0_HOSTFN_CMD_STAT));
-                       readl((rb + CT2_LPU0_HOSTFN_CMD_STAT));
+                       writel(1, rb + CT2_LPU0_HOSTFN_CMD_STAT);
+                       readl(rb + CT2_LPU0_HOSTFN_CMD_STAT);
                }
-               r32 = readl((rb + CT2_LPU1_HOSTFN_CMD_STAT));
+               r32 = readl(rb + CT2_LPU1_HOSTFN_CMD_STAT);
                if (r32 == 1) {
-                       writel(1, (rb + CT2_LPU1_HOSTFN_CMD_STAT));
-                       readl((rb + CT2_LPU1_HOSTFN_CMD_STAT));
+                       writel(1, rb + CT2_LPU1_HOSTFN_CMD_STAT);
+                       readl(rb + CT2_LPU1_HOSTFN_CMD_STAT);
                }
        }
 
        bfa_ioc_ct2_mem_init(rb);
 
-       writel(BFI_IOC_UNINIT, (rb + CT2_BFA_IOC0_STATE_REG));
-       writel(BFI_IOC_UNINIT, (rb + CT2_BFA_IOC1_STATE_REG));
+       writel(BFI_IOC_UNINIT, rb + CT2_BFA_IOC0_STATE_REG);
+       writel(BFI_IOC_UNINIT, rb + CT2_BFA_IOC1_STATE_REG);
        return BFA_STATUS_OK;
 }
index dc845b2571dafe37230bba7bd313c5c5c75216e4..006dcad9a260da150c82bc784902e9fbff68da81 100644 (file)
@@ -243,7 +243,7 @@ do {                                                                        \
 
 /*  Inline functions  */
 
-static inline struct bna_mac *bna_mac_find(struct list_head *q, u8 *addr)
+static inline struct bna_mac *bna_mac_find(struct list_head *q, const u8 *addr)
 {
        struct bna_mac *mac;
 
@@ -362,15 +362,14 @@ void bna_rx_cleanup_complete(struct bna_rx *rx);
 void bna_rx_coalescing_timeo_set(struct bna_rx *rx, int coalescing_timeo);
 void bna_rx_dim_reconfig(struct bna *bna, const u32 vector[][BNA_BIAS_T_MAX]);
 void bna_rx_dim_update(struct bna_ccb *ccb);
-enum bna_cb_status
-bna_rx_ucast_set(struct bna_rx *rx, u8 *ucmac);
-enum bna_cb_status
-bna_rx_ucast_listset(struct bna_rx *rx, int count, u8 *uclist);
-enum bna_cb_status
-bna_rx_mcast_add(struct bna_rx *rx, u8 *mcmac,
-                void (*cbfn)(struct bnad *, struct bna_rx *));
-enum bna_cb_status
-bna_rx_mcast_listset(struct bna_rx *rx, int count, u8 *mcmac);
+enum bna_cb_status bna_rx_ucast_set(struct bna_rx *rx, const u8 *ucmac);
+enum bna_cb_status bna_rx_ucast_listset(struct bna_rx *rx, int count,
+                                       const u8 *uclist);
+enum bna_cb_status bna_rx_mcast_add(struct bna_rx *rx, const u8 *mcmac,
+                                   void (*cbfn)(struct bnad *,
+                                                struct bna_rx *));
+enum bna_cb_status bna_rx_mcast_listset(struct bna_rx *rx, int count,
+                                       const u8 *mcmac);
 void
 bna_rx_mcast_delall(struct bna_rx *rx);
 enum bna_cb_status
index 05680e081b4ff03488d27a21eeeef3a38e3d1eb6..4e5c3874a50ff7e0b2b2ec30bdee7f39f5f017ce 100644 (file)
@@ -207,7 +207,7 @@ bna_bfi_stats_get_rsp(struct bna *bna, struct bfi_msgq_mhdr *msghdr)
        for (i = 0; i < BFI_ENET_CFG_MAX; i++) {
                stats_dst = (u64 *)&(bna->stats.hw_stats.rxf_stats[i]);
                memset(stats_dst, 0, sizeof(struct bfi_enet_stats_rxf));
-               if (rx_enet_mask & ((u32)BIT(i))) {
+               if (rx_enet_mask & BIT(i)) {
                        int k;
                        count = sizeof(struct bfi_enet_stats_rxf) /
                                sizeof(u64);
@@ -222,7 +222,7 @@ bna_bfi_stats_get_rsp(struct bna *bna, struct bfi_msgq_mhdr *msghdr)
        for (i = 0; i < BFI_ENET_CFG_MAX; i++) {
                stats_dst = (u64 *)&(bna->stats.hw_stats.txf_stats[i]);
                memset(stats_dst, 0, sizeof(struct bfi_enet_stats_txf));
-               if (tx_enet_mask & ((u32)BIT(i))) {
+               if (tx_enet_mask & BIT(i)) {
                        int k;
                        count = sizeof(struct bfi_enet_stats_txf) /
                                sizeof(u64);
index 64eb8c48fe79a9a4e08a78e7fbf4b8d8f42da9ac..5d0753cc7e735eb11d4228afced69c8afdae3818 100644 (file)
@@ -353,7 +353,7 @@ bna_bfi_rss_enable(struct bna_rxf *rxf)
 
 /* This function gets the multicast MAC that has already been added to CAM */
 static struct bna_mac *
-bna_rxf_mcmac_get(struct bna_rxf *rxf, u8 *mac_addr)
+bna_rxf_mcmac_get(struct bna_rxf *rxf, const u8 *mac_addr)
 {
        struct bna_mac *mac;
 
@@ -729,7 +729,7 @@ bna_rxf_fail(struct bna_rxf *rxf)
 }
 
 enum bna_cb_status
-bna_rx_ucast_set(struct bna_rx *rx, u8 *ucmac)
+bna_rx_ucast_set(struct bna_rx *rx, const u8 *ucmac)
 {
        struct bna_rxf *rxf = &rx->rxf;
 
@@ -751,7 +751,7 @@ bna_rx_ucast_set(struct bna_rx *rx, u8 *ucmac)
 }
 
 enum bna_cb_status
-bna_rx_mcast_add(struct bna_rx *rx, u8 *addr,
+bna_rx_mcast_add(struct bna_rx *rx, const u8 *addr,
                 void (*cbfn)(struct bnad *, struct bna_rx *))
 {
        struct bna_rxf *rxf = &rx->rxf;
@@ -780,12 +780,12 @@ bna_rx_mcast_add(struct bna_rx *rx, u8 *addr,
 }
 
 enum bna_cb_status
-bna_rx_ucast_listset(struct bna_rx *rx, int count, u8 *uclist)
+bna_rx_ucast_listset(struct bna_rx *rx, int count, const u8 *uclist)
 {
        struct bna_ucam_mod *ucam_mod = &rx->bna->ucam_mod;
        struct bna_rxf *rxf = &rx->rxf;
        struct list_head list_head;
-       u8 *mcaddr;
+       const u8 *mcaddr;
        struct bna_mac *mac, *del_mac;
        int i;
 
@@ -838,12 +838,12 @@ bna_rx_ucast_listset(struct bna_rx *rx, int count, u8 *uclist)
 }
 
 enum bna_cb_status
-bna_rx_mcast_listset(struct bna_rx *rx, int count, u8 *mclist)
+bna_rx_mcast_listset(struct bna_rx *rx, int count, const u8 *mclist)
 {
        struct bna_mcam_mod *mcam_mod = &rx->bna->mcam_mod;
        struct bna_rxf *rxf = &rx->rxf;
        struct list_head list_head;
-       u8 *mcaddr;
+       const u8 *mcaddr;
        struct bna_mac *mac, *del_mac;
        int i;
 
@@ -933,7 +933,7 @@ bna_rx_vlan_add(struct bna_rx *rx, int vlan_id)
 {
        struct bna_rxf *rxf = &rx->rxf;
        int index = (vlan_id >> BFI_VLAN_WORD_SHIFT);
-       int bit = BIT((vlan_id & BFI_VLAN_WORD_MASK));
+       int bit = BIT(vlan_id & BFI_VLAN_WORD_MASK);
        int group_id = (vlan_id >> BFI_VLAN_BLOCK_SHIFT);
 
        rxf->vlan_filter_table[index] |= bit;
@@ -948,7 +948,7 @@ bna_rx_vlan_del(struct bna_rx *rx, int vlan_id)
 {
        struct bna_rxf *rxf = &rx->rxf;
        int index = (vlan_id >> BFI_VLAN_WORD_SHIFT);
-       int bit = BIT((vlan_id & BFI_VLAN_WORD_MASK));
+       int bit = BIT(vlan_id & BFI_VLAN_WORD_MASK);
        int group_id = (vlan_id >> BFI_VLAN_BLOCK_SHIFT);
 
        rxf->vlan_filter_table[index] &= ~bit;
index 6be31ae7b5c9982e901a6c6563219c7b16b5ac37..0612b19f6313bd3e6ffa205be2b543585262e31e 100644 (file)
@@ -309,7 +309,7 @@ bnad_rxq_alloc_init(struct bnad *bnad, struct bna_rcb *rcb)
                }
        }
 
-       BUG_ON(((PAGE_SIZE << order) % unmap_q->map_size));
+       BUG_ON((PAGE_SIZE << order) % unmap_q->map_size);
 
        return 0;
 }
@@ -757,7 +757,7 @@ bnad_msix_rx(int irq, void *data)
        struct bna_ccb *ccb = (struct bna_ccb *)data;
 
        if (ccb) {
-               ((struct bnad_rx_ctrl *)(ccb->ctrl))->rx_intr_ctr++;
+               ((struct bnad_rx_ctrl *)ccb->ctrl)->rx_intr_ctr++;
                bnad_netif_rx_schedule_poll(ccb->bnad, ccb);
        }
 
@@ -2327,7 +2327,7 @@ bnad_rx_coalescing_timeo_set(struct bnad *bnad)
  * Called with bnad->bna_lock held
  */
 int
-bnad_mac_addr_set_locked(struct bnad *bnad, u8 *mac_addr)
+bnad_mac_addr_set_locked(struct bnad *bnad, const u8 *mac_addr)
 {
        int ret;
 
@@ -2356,8 +2356,8 @@ bnad_enable_default_bcast(struct bnad *bnad)
        init_completion(&bnad->bnad_completions.mcast_comp);
 
        spin_lock_irqsave(&bnad->bna_lock, flags);
-       ret = bna_rx_mcast_add(rx_info->rx, (u8 *)bnad_bcast_addr,
-                               bnad_cb_rx_mcast_add);
+       ret = bna_rx_mcast_add(rx_info->rx, bnad_bcast_addr,
+                              bnad_cb_rx_mcast_add);
        spin_unlock_irqrestore(&bnad->bna_lock, flags);
 
        if (ret == BNA_CB_SUCCESS)
@@ -3677,13 +3677,13 @@ bnad_pci_probe(struct pci_dev *pdev,
 
        /* Set up timers */
        setup_timer(&bnad->bna.ioceth.ioc.ioc_timer, bnad_ioc_timeout,
-                               ((unsigned long)bnad));
+                   (unsigned long)bnad);
        setup_timer(&bnad->bna.ioceth.ioc.hb_timer, bnad_ioc_hb_check,
-                               ((unsigned long)bnad));
+                   (unsigned long)bnad);
        setup_timer(&bnad->bna.ioceth.ioc.iocpf_timer, bnad_iocpf_timeout,
-                               ((unsigned long)bnad));
+                   (unsigned long)bnad);
        setup_timer(&bnad->bna.ioceth.ioc.sem_timer, bnad_iocpf_sem_timeout,
-                               ((unsigned long)bnad));
+                   (unsigned long)bnad);
 
        /*
         * Start the chip
index 91fd82d9e9bc94968204c75f079c2bc4fa27cf56..faedbf24777e1f7eb47dd40c12ca6ac1ad32afa1 100644 (file)
@@ -385,7 +385,7 @@ u32 *cna_get_firmware_buf(struct pci_dev *pdev);
 /* Netdev entry point prototypes */
 void bnad_set_rx_mode(struct net_device *netdev);
 struct net_device_stats *bnad_get_netdev_stats(struct net_device *netdev);
-int bnad_mac_addr_set_locked(struct bnad *bnad, u8 *mac_addr);
+int bnad_mac_addr_set_locked(struct bnad *bnad, const u8 *mac_addr);
 int bnad_enable_default_bcast(struct bnad *bnad);
 void bnad_restore_vlans(struct bnad *bnad, u32 rx_id);
 void bnad_set_ethtool_ops(struct net_device *netdev);
index c0fd737e748647d4d1475306f4f1fa1141f048b0..8fc246ea1fb828c5cd2103145903dfd3a81d9cb4 100644 (file)
@@ -268,15 +268,15 @@ bna_reg_offset_check(struct bfa_ioc *ioc, u32 offset, u32 len)
        area = (offset >> 15) & 0x7;
        if (area == 0) {
                /* PCIe core register */
-               if ((offset + (len<<2)) > 0x8000)       /* 8k dwords or 32KB */
+               if (offset + (len << 2) > 0x8000)       /* 8k dwords or 32KB */
                        return BFA_STATUS_EINVAL;
        } else if (area == 0x1) {
                /* CB 32 KB memory page */
-               if ((offset + (len<<2)) > 0x10000)      /* 8k dwords or 32KB */
+               if (offset + (len << 2) > 0x10000)      /* 8k dwords or 32KB */
                        return BFA_STATUS_EINVAL;
        } else {
                /* CB register space 64KB */
-               if ((offset + (len<<2)) > BFA_REG_ADDRMSK(ioc))
+               if (offset + (len << 2) > BFA_REG_ADDRMSK(ioc))
                        return BFA_STATUS_EINVAL;
        }
        return BFA_STATUS_OK;