serial: sh-sci: add FIFO trigger bits

Defines the bits controlling FIFO thresholds, adds the additional
HSCIF registers to the register map.

Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index d7535b47bf1097f5c88c72cc7d1d8ab17b0b2e45..5044a5e5d34036d689217717904eee687106c013 100644 (file)
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -373,6 +373,8 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
                        [HSSRR]         = { 0x40, 16 },
                        [SCDL]          = { 0x30, 16 },
                        [SCCKS]         = { 0x34, 16 },
+                       [HSRTRGR]       = { 0x54, 16 },
+                       [HSTTRGR]       = { 0x58, 16 },
                },
                .fifosize = 128,
                .overrun_reg = SCLSR,

diff --git a/drivers/tty/serial/sh-sci.h b/drivers/tty/serial/sh-sci.h
index 08073f0db732cf18b1b235f34e61010896671597..30b6d67867e7f2cb75503f125270b154d194642f 100644 (file)
--- a/drivers/tty/serial/sh-sci.h
+++ b/drivers/tty/serial/sh-sci.h
@@ -29,6 +29,8 @@ enum {
        SCPDR,                          /* Serial Port Data Register */
        SCDL,                           /* BRG Frequency Division Register */
        SCCKS,                          /* BRG Clock Select Register */
+       HSRTRGR,                        /* Rx FIFO Data Count Trigger Register */
+       HSTTRGR,                        /* Tx FIFO Data Count Trigger Register */
 
        SCIx_NR_REGS,
 };
@@ -99,6 +101,10 @@ enum {
 #define SCIF_BREAK_CLEAR       (u32)(~(SCIF_PER | SCIF_FER | SCIF_BRK))
 
 /* SCFCR (FIFO Control Register) */
+#define SCFCR_RTRG1    BIT(7)  /* Receive FIFO Data Count Trigger */
+#define SCFCR_RTRG0    BIT(6)
+#define SCFCR_TTRG1    BIT(5)  /* Transmit FIFO Data Count Trigger */
+#define SCFCR_TTRG0    BIT(4)
 #define SCFCR_MCE      BIT(3)  /* Modem Control Enable */
 #define SCFCR_TFRST    BIT(2)  /* Transmit FIFO Data Register Reset */
 #define SCFCR_RFRST    BIT(1)  /* Receive FIFO Data Register Reset */