clk: renesas: r8a774b1: Add TMU clock

This patch adds the TMU clocks to the R8A774B1 SoC.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Link: https://lore.kernel.org/r/1569249688-15821-1-git-send-email-biju.das@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r8a774b1-cpg-mssr.c b/drivers/clk/renesas/r8a774b1-cpg-mssr.c
index 6cad6ba4a68240742a17159f97a891c3fd7f1d40..c9af7091731248a2c7bc76713b802cc50840f440 100644 (file)
--- a/drivers/clk/renesas/r8a774b1-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774b1-cpg-mssr.c
@@ -110,6 +110,11 @@ static const struct cpg_core_clk r8a774b1_core_clks[] __initconst = {
 };
 
 static const struct mssr_mod_clk r8a774b1_mod_clks[] __initconst = {
+       DEF_MOD("tmu4",                  121,   R8A774B1_CLK_S0D6),
+       DEF_MOD("tmu3",                  122,   R8A774B1_CLK_S3D2),
+       DEF_MOD("tmu2",                  123,   R8A774B1_CLK_S3D2),
+       DEF_MOD("tmu1",                  124,   R8A774B1_CLK_S3D2),
+       DEF_MOD("tmu0",                  125,   R8A774B1_CLK_CP),
        DEF_MOD("fdp1-0",                119,   R8A774B1_CLK_S0D1),
        DEF_MOD("scif5",                 202,   R8A774B1_CLK_S3D4),
        DEF_MOD("scif4",                 203,   R8A774B1_CLK_S3D4),