]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
ARM: dts: imx6qdl-rex: add gpio expander pca9535
authorGilles DOFFE <gilles.doffe@savoirfairelinux.com>
Wed, 16 Oct 2019 09:22:55 +0000 (11:22 +0200)
committerShawn Guo <shawnguo@kernel.org>
Sat, 26 Oct 2019 12:23:31 +0000 (20:23 +0800)
The pca9535 gpio expander is present on the Rex baseboard, but missing
from the dtsi.
The pca9535 is on i2c2 bus which is common to the three SOM
variants (Basic/Pro/Ultra), thus it is activated by default.

Add also the new gpio controller and the associated interrupt line
MX6QDL_PAD_NANDF_CS3__GPIO6_IO16.

Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
arch/arm/boot/dts/imx6qdl-rex.dtsi

index 97f1659144ea545f4ae2ee0fdedbf57d6177c4fe..de514eb5aa99db4d47bf6d5082cedd3f760a367c 100644 (file)
@@ -132,6 +132,19 @@ &i2c2 {
        pinctrl-0 = <&pinctrl_i2c2>;
        status = "okay";
 
+       pca9535: gpio-expander@27 {
+               compatible = "nxp,pca9535";
+               reg = <0x27>;
+               gpio-controller;
+               #gpio-cells = <2>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_pca9535>;
+               interrupt-parent = <&gpio6>;
+               interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
+               interrupt-controller;
+               #interrupt-cells = <2>;
+       };
+
        eeprom@57 {
                compatible = "atmel,24c02";
                reg = <0x57>;
@@ -237,6 +250,12 @@ MX6QDL_PAD_GPIO_2__GPIO1_IO02              0x80000000
                        >;
                };
 
+               pinctrl_pca9535: pca9535grp {
+                       fsl,pins = <
+                               MX6QDL_PAD_NANDF_CS3__GPIO6_IO16        0x17059
+                  >;
+               };
+
                pinctrl_uart1: uart1grp {
                        fsl,pins = <
                                MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA    0x1b0b1