drm/amd/powerplay: move PHM_WAIT_VFPF_INDIRECT_FIELD to hwmgr.h

the macro is not relevant to SMU, so move to hwmgr.h
and rename to PHM_WAIT_VFPF_INDIRECT_FIELD

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index 85a2df2fbaa95877f0af40fdd1c3a41214c6bd2f..2ac8d7b59e6137ca8dc33594093123e670929375 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -915,4 +915,18 @@ extern int phm_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_t
                (fieldval) << PHM_FIELD_SHIFT(reg, field),              \
                PHM_FIELD_MASK(reg, field))
 
+
+#define PHM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr,             \
+                               port, index, value, mask)               \
+       phm_wait_on_indirect_register(hwmgr,                            \
+               mm##port##_INDEX_11, index, value, mask)
+
+#define PHM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, value, mask) \
+       PHM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
+
+#define PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval) \
+       PHM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg,               \
+               (fieldval) << PHM_FIELD_SHIFT(reg, field),              \
+               PHM_FIELD_MASK(reg, field))
+
 #endif /* _HWMGR_H_ */

diff --git a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
index 125fa3e812b335c48a5cba527632b01acdc9dfd6..099758d405a6fb8566929c26cd01c099a5df0b46 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
@@ -193,16 +193,7 @@ extern bool smum_is_hw_avfs_present(struct pp_hwmgr *hwmgr);
            SMUM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
                           reg, field)
 
-#define SMUM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr,            \
-                               port, index, value, mask)               \
-       smum_wait_on_indirect_register(hwmgr,                           \
-               mm##port##_INDEX_11, index, value, mask)
-
-
-
 
-#define SMUM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, value, mask) \
-       SMUM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
 
 
 
@@ -229,10 +220,7 @@ extern bool smum_is_hw_avfs_present(struct pp_hwmgr *hwmgr);
                                       reg, field, fieldval))
 
 
-#define SMUM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval) \
-       SMUM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg,              \
-               (fieldval) << SMUM_FIELD_SHIFT(reg, field),             \
-               SMUM_FIELD_MASK(reg, field))
+
 
 
 #endif

diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
index 762fe163e86062364fa27dbf958bb47dd1d52e7d..75ed7c3ea9900515d6f05e4d750c2d48226f75c6 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
@@ -96,7 +96,7 @@ static int fiji_start_smu_in_protection_mode(struct pp_hwmgr *hwmgr)
        cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
                        ixFIRMWARE_FLAGS, 0);
 
-       SMUM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, RCU_UC_EVENTS,
+       PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, RCU_UC_EVENTS,
                        INTERRUPTS_ENABLED, 1);
 
        cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, 0x20000);
@@ -115,7 +115,7 @@ static int fiji_start_smu_in_protection_mode(struct pp_hwmgr *hwmgr)
        }
 
        /* Wait for firmware to initialize */
-       SMUM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
+       PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
                        FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
 
        return result;
@@ -153,7 +153,7 @@ static int fiji_start_smu_in_non_protection_mode(struct pp_hwmgr *hwmgr)
                        SMC_SYSCON_RESET_CNTL, rst_reg, 0);
 
        /* Wait for firmware to initialize */
-       SMUM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
+       PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
                        FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
 
        return result;

diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
index 3cc946dee3d1e67f38261c18a5b073f864c25651..fd4ccd09698519651db87b369ade465c3e263db7 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
@@ -241,7 +241,7 @@ static int polaris10_start_smu_in_protection_mode(struct pp_hwmgr *hwmgr)
                                        SMC_SYSCON_RESET_CNTL, rst_reg, 0);
 
 
-       SMUM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, RCU_UC_EVENTS, INTERRUPTS_ENABLED, 1);
+       PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, RCU_UC_EVENTS, INTERRUPTS_ENABLED, 1);
 
 
        /* Call Test SMU message with 0x20000 offset to trigger SMU start */
@@ -265,7 +265,7 @@ static int polaris10_start_smu_in_protection_mode(struct pp_hwmgr *hwmgr)
                                        SMC_SYSCON_RESET_CNTL, rst_reg, 0);
 
        /* Wait for firmware to initialize */
-       SMUM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
+       PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
 
        return result;
 }
@@ -301,7 +301,7 @@ static int polaris10_start_smu_in_non_protection_mode(struct pp_hwmgr *hwmgr)
 
        /* Wait for firmware to initialize */
 
-       SMUM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
+       PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
                                        FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
 
        return result;

diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
index bb26906edb86ba7c179a84e2d57799c0c89760e4..a360c3ce5da2bf88cae5618d0a47e58f1827ab6f 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
@@ -235,7 +235,7 @@ int smu7_wait_for_smc_inactive(struct pp_hwmgr *hwmgr)
        if (!smu7_is_smc_ram_running(hwmgr))
                return -EINVAL;
 
-       SMUM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, SMC_SYSCON_CLOCK_CNTL_0, cken, 0);
+       PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, SMC_SYSCON_CLOCK_CNTL_0, cken, 0);
        return 0;
 }
 

diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
index a0e0f5efb6fb3cb8e98b51f5bd711deff1c9c20b..6a9b3cf3fdaa420fed6d34e763e17b6e58631716 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
@@ -69,7 +69,7 @@ static int tonga_start_in_protection_mode(struct pp_hwmgr *hwmgr)
        cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
                ixFIRMWARE_FLAGS, 0);
 
-       SMUM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
+       PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
                RCU_UC_EVENTS, INTERRUPTS_ENABLED, 1);
 
        /**
@@ -89,7 +89,7 @@ static int tonga_start_in_protection_mode(struct pp_hwmgr *hwmgr)
        }
 
        /* Wait for firmware to initialize */
-       SMUM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
+       PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
                FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
 
        return 0;
@@ -129,7 +129,7 @@ static int tonga_start_in_non_protection_mode(struct pp_hwmgr *hwmgr)
                SMC_SYSCON_RESET_CNTL, rst_reg, 0);
 
        /* Wait for firmware to initialize */
-       SMUM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
+       PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
                FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
 
        return result;