Merge tag 'bitmain-soc-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/mani...

Bitmain SoC changes for v5.4:

Most of the basic infrastructure is completed for BM1880 SoC except
common clock support. We are still couple of patchset away from
booting a distro from eMMC/SD with mainline. Below are the changes
for this cycle:

- Added Reset controller support to BM1880 SoC based on reset-simple
  driver.
- Modified pinctrl memory map for BM1880 SoC. The initial pinctrl support
  included the PWM registers as a part of the pinctrl memory map. But this
  turned out to be useless as PWM registers are not handling any pin muxing
  at all. So removed the PWM registers from pinctrl memory map.

* tag 'bitmain-soc-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/mani/linux-bitmain:
  arm64: dts: bitmain: Modify pin controller memory map
  arm64: dts: bitmain: Add reset controller support for BM1880 SoC

Signed-off-by: Arnd Bergmann <arnd@arndb.de>

diff --git a/arch/arm64/boot/dts/bitmain/bm1880.dtsi b/arch/arm64/boot/dts/bitmain/bm1880.dtsi
index 7726fd4c6be6f68bf9cfaef8cf038a73ae445d7d..d65453f99a993a1d4ad7a5132798b1a109663b34 100644 (file)
--- a/arch/arm64/boot/dts/bitmain/bm1880.dtsi
+++ b/arch/arm64/boot/dts/bitmain/bm1880.dtsi
@@ -5,6 +5,7 @@
  */
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/reset/bitmain,bm1880-reset.h>
 
 / {
        compatible = "bitmain,bm1880";
@@ -88,9 +89,15 @@ sctrl: system-controller@50010000 {
                        #size-cells = <1>;
                        ranges = <0x0 0x0 0x50010000 0x1000>;
 
-                       pinctrl: pinctrl@50 {
+                       pinctrl: pinctrl@400 {
                                compatible = "bitmain,bm1880-pinctrl";
-                               reg = <0x50 0x4B0>;
+                               reg = <0x400 0x120>;
+                       };
+
+                       rst: reset-controller@c00 {
+                               compatible = "bitmain,bm1880-reset";
+                               reg = <0xc00 0x8>;
+                               #reset-cells = <1>;
                        };
                };
 
@@ -154,6 +161,7 @@ uart0: serial@58018000 {
                        interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
                        reg-shift = <2>;
                        reg-io-width = <4>;
+                       resets = <&rst BM1880_RST_UART0_1_CLK>;
                        status = "disabled";
                };
 
@@ -163,6 +171,7 @@ uart1: serial@5801A000 {
                        interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
                        reg-shift = <2>;
                        reg-io-width = <4>;
+                       resets = <&rst BM1880_RST_UART0_1_ACLK>;
                        status = "disabled";
                };
 
@@ -172,6 +181,7 @@ uart2: serial@5801C000 {
                        interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
                        reg-shift = <2>;
                        reg-io-width = <4>;
+                       resets = <&rst BM1880_RST_UART2_3_CLK>;
                        status = "disabled";
                };
 
@@ -181,6 +191,7 @@ uart3: serial@5801E000 {
                        interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
                        reg-shift = <2>;
                        reg-io-width = <4>;
+                       resets = <&rst BM1880_RST_UART2_3_ACLK>;
                        status = "disabled";
                };
        };