drm/i915/execlists: Move RCS mmio workaround to new common wa_list

We can move the remaining RCS workarounds applied to only gen8 to the
engine->wa_list, and then reduce all engine->init_hw callbacks to common
code. The benefit of using the new wa_list is that we verify that the
registers are indeed restored and keep their magic values.

v2: INSTPM_FORCE_ORDERING is already part of gen8_ctx_workarounds, and
as confirmed by the mmio verification is a part of the context image!
v3: MI_MODE is already part of gen8_ctx_workarounds...

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181206180713.6827-2-chris@chris-wilson.co.uk

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index d7fa301b5ec75b8656074f3ac3e2a03ce589bc4e..dc8981be22cf89176afbf8d5f81ef7100206b457 100644 (file)
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1628,6 +1628,7 @@ static bool unexpected_starting_state(struct intel_engine_cs *engine)
 static int gen8_init_common_ring(struct intel_engine_cs *engine)
 {
        intel_engine_apply_workarounds(engine);
+       intel_engine_apply_whitelist(engine);
 
        intel_mocs_init_engine(engine);
 
@@ -1644,43 +1645,6 @@ static int gen8_init_common_ring(struct intel_engine_cs *engine)
        return 0;
 }
 
-static int gen8_init_render_ring(struct intel_engine_cs *engine)
-{
-       struct drm_i915_private *dev_priv = engine->i915;
-       int ret;
-
-       ret = gen8_init_common_ring(engine);
-       if (ret)
-               return ret;
-
-       intel_engine_apply_whitelist(engine);
-
-       /* We need to disable the AsyncFlip performance optimisations in order
-        * to use MI_WAIT_FOR_EVENT within the CS. It should already be
-        * programmed to '1' on all products.
-        *
-        * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
-        */
-       I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
-
-       I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
-
-       return 0;
-}
-
-static int gen9_init_render_ring(struct intel_engine_cs *engine)
-{
-       int ret;
-
-       ret = gen8_init_common_ring(engine);
-       if (ret)
-               return ret;
-
-       intel_engine_apply_whitelist(engine);
-
-       return 0;
-}
-
 static struct i915_request *
 execlists_reset_prepare(struct intel_engine_cs *engine)
 {
@@ -2280,10 +2244,6 @@ int logical_render_ring_init(struct intel_engine_cs *engine)
                engine->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
 
        /* Override some for render ring. */
-       if (INTEL_GEN(dev_priv) >= 9)
-               engine->init_hw = gen9_init_render_ring;
-       else
-               engine->init_hw = gen8_init_render_ring;
        engine->init_context = gen8_init_rcs_context;
        engine->emit_flush = gen8_emit_flush_render;
        engine->emit_breadcrumb = gen8_emit_breadcrumb_rcs;